diff options
Diffstat (limited to 'lib/Target')
34 files changed, 2542 insertions, 2542 deletions
diff --git a/lib/Target/ARM/ARMAddressingModes.h b/lib/Target/ARM/ARMAddressingModes.h index 0189c00..2378485 100644 --- a/lib/Target/ARM/ARMAddressingModes.h +++ b/lib/Target/ARM/ARMAddressingModes.h @@ -46,7 +46,7 @@ namespace ARM_AM { } } - static inline ShiftOpc getShiftOpcForNode(SDOperand N) { + static inline ShiftOpc getShiftOpcForNode(SDValue N) { switch (N.getOpcode()) { default: return ARM_AM::no_shift; case ISD::SHL: return ARM_AM::lsl; diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp index 2d1136f..b79fffe 100644 --- a/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -53,38 +53,38 @@ public: return "ARM Instruction Selection"; } - SDNode *Select(SDOperand Op); + SDNode *Select(SDValue Op); virtual void InstructionSelect(SelectionDAG &DAG); - bool SelectAddrMode2(SDOperand Op, SDOperand N, SDOperand &Base, - SDOperand &Offset, SDOperand &Opc); - bool SelectAddrMode2Offset(SDOperand Op, SDOperand N, - SDOperand &Offset, SDOperand &Opc); - bool SelectAddrMode3(SDOperand Op, SDOperand N, SDOperand &Base, - SDOperand &Offset, SDOperand &Opc); - bool SelectAddrMode3Offset(SDOperand Op, SDOperand N, - SDOperand &Offset, SDOperand &Opc); - bool SelectAddrMode5(SDOperand Op, SDOperand N, SDOperand &Base, - SDOperand &Offset); - - bool SelectAddrModePC(SDOperand Op, SDOperand N, SDOperand &Offset, - SDOperand &Label); - - bool SelectThumbAddrModeRR(SDOperand Op, SDOperand N, SDOperand &Base, - SDOperand &Offset); - bool SelectThumbAddrModeRI5(SDOperand Op, SDOperand N, unsigned Scale, - SDOperand &Base, SDOperand &OffImm, - SDOperand &Offset); - bool SelectThumbAddrModeS1(SDOperand Op, SDOperand N, SDOperand &Base, - SDOperand &OffImm, SDOperand &Offset); - bool SelectThumbAddrModeS2(SDOperand Op, SDOperand N, SDOperand &Base, - SDOperand &OffImm, SDOperand &Offset); - bool SelectThumbAddrModeS4(SDOperand Op, SDOperand N, SDOperand &Base, - SDOperand &OffImm, SDOperand &Offset); - bool SelectThumbAddrModeSP(SDOperand Op, SDOperand N, SDOperand &Base, - SDOperand &OffImm); - - bool SelectShifterOperandReg(SDOperand Op, SDOperand N, SDOperand &A, - SDOperand &B, SDOperand &C); + bool SelectAddrMode2(SDValue Op, SDValue N, SDValue &Base, + SDValue &Offset, SDValue &Opc); + bool SelectAddrMode2Offset(SDValue Op, SDValue N, + SDValue &Offset, SDValue &Opc); + bool SelectAddrMode3(SDValue Op, SDValue N, SDValue &Base, + SDValue &Offset, SDValue &Opc); + bool SelectAddrMode3Offset(SDValue Op, SDValue N, + SDValue &Offset, SDValue &Opc); + bool SelectAddrMode5(SDValue Op, SDValue N, SDValue &Base, + SDValue &Offset); + + bool SelectAddrModePC(SDValue Op, SDValue N, SDValue &Offset, + SDValue &Label); + + bool SelectThumbAddrModeRR(SDValue Op, SDValue N, SDValue &Base, + SDValue &Offset); + bool SelectThumbAddrModeRI5(SDValue Op, SDValue N, unsigned Scale, + SDValue &Base, SDValue &OffImm, + SDValue &Offset); + bool SelectThumbAddrModeS1(SDValue Op, SDValue N, SDValue &Base, + SDValue &OffImm, SDValue &Offset); + bool SelectThumbAddrModeS2(SDValue Op, SDValue N, SDValue &Base, + SDValue &OffImm, SDValue &Offset); + bool SelectThumbAddrModeS4(SDValue Op, SDValue N, SDValue &Base, + SDValue &OffImm, SDValue &Offset); + bool SelectThumbAddrModeSP(SDValue Op, SDValue N, SDValue &Base, + SDValue &OffImm); + + bool SelectShifterOperandReg(SDValue Op, SDValue N, SDValue &A, + SDValue &B, SDValue &C); // Include the pieces autogenerated from the target description. #include "ARMGenDAGISel.inc" @@ -98,9 +98,9 @@ void ARMDAGToDAGISel::InstructionSelect(SelectionDAG &DAG) { DAG.RemoveDeadNodes(); } -bool ARMDAGToDAGISel::SelectAddrMode2(SDOperand Op, SDOperand N, - SDOperand &Base, SDOperand &Offset, - SDOperand &Opc) { +bool ARMDAGToDAGISel::SelectAddrMode2(SDValue Op, SDValue N, + SDValue &Base, SDValue &Offset, + SDValue &Opc) { if (N.getOpcode() == ISD::MUL) { if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { // X * [3,5,9] -> X + X * [2,4,8] etc. @@ -206,8 +206,8 @@ bool ARMDAGToDAGISel::SelectAddrMode2(SDOperand Op, SDOperand N, return true; } -bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDOperand Op, SDOperand N, - SDOperand &Offset, SDOperand &Opc) { +bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDValue Op, SDValue N, + SDValue &Offset, SDValue &Opc) { unsigned Opcode = Op.getOpcode(); ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) ? cast<LoadSDNode>(Op)->getAddressingMode() @@ -245,9 +245,9 @@ bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDOperand Op, SDOperand N, } -bool ARMDAGToDAGISel::SelectAddrMode3(SDOperand Op, SDOperand N, - SDOperand &Base, SDOperand &Offset, - SDOperand &Opc) { +bool ARMDAGToDAGISel::SelectAddrMode3(SDValue Op, SDValue N, + SDValue &Base, SDValue &Offset, + SDValue &Opc) { if (N.getOpcode() == ISD::SUB) { // X - C is canonicalize to X + -C, no need to handle it here. Base = N.getOperand(0); @@ -295,8 +295,8 @@ bool ARMDAGToDAGISel::SelectAddrMode3(SDOperand Op, SDOperand N, return true; } -bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDOperand Op, SDOperand N, - SDOperand &Offset, SDOperand &Opc) { +bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDValue Op, SDValue N, + SDValue &Offset, SDValue &Opc) { unsigned Opcode = Op.getOpcode(); ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) ? cast<LoadSDNode>(Op)->getAddressingMode() @@ -318,8 +318,8 @@ bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDOperand Op, SDOperand N, } -bool ARMDAGToDAGISel::SelectAddrMode5(SDOperand Op, SDOperand N, - SDOperand &Base, SDOperand &Offset) { +bool ARMDAGToDAGISel::SelectAddrMode5(SDValue Op, SDValue N, + SDValue &Base, SDValue &Offset) { if (N.getOpcode() != ISD::ADD) { Base = N; if (N.getOpcode() == ISD::FrameIndex) { @@ -364,11 +364,11 @@ bool ARMDAGToDAGISel::SelectAddrMode5(SDOperand Op, SDOperand N, return true; } -bool ARMDAGToDAGISel::SelectAddrModePC(SDOperand Op, SDOperand N, - SDOperand &Offset, SDOperand &Label) { +bool ARMDAGToDAGISel::SelectAddrModePC(SDValue Op, SDValue N, + SDValue &Offset, SDValue &Label) { if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) { Offset = N.getOperand(0); - SDOperand N1 = N.getOperand(1); + SDValue N1 = N.getOperand(1); Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getValue(), MVT::i32); return true; @@ -376,14 +376,14 @@ bool ARMDAGToDAGISel::SelectAddrModePC(SDOperand Op, SDOperand N, return false; } -bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDOperand Op, SDOperand N, - SDOperand &Base, SDOperand &Offset){ +bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue Op, SDValue N, + SDValue &Base, SDValue &Offset){ if (N.getOpcode() != ISD::ADD) { Base = N; // We must materialize a zero in a reg! Returning an constant here won't // work since its node is -1 so it won't get added to the selection queue. // Explicitly issue a tMOVri8 node! - Offset = SDOperand(CurDAG->getTargetNode(ARM::tMOVi8, MVT::i32, + Offset = SDValue(CurDAG->getTargetNode(ARM::tMOVi8, MVT::i32, CurDAG->getTargetConstant(0, MVT::i32)), 0); return true; } @@ -394,11 +394,11 @@ bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDOperand Op, SDOperand N, } bool -ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDOperand Op, SDOperand N, - unsigned Scale, SDOperand &Base, - SDOperand &OffImm, SDOperand &Offset) { +ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue Op, SDValue N, + unsigned Scale, SDValue &Base, + SDValue &OffImm, SDValue &Offset) { if (Scale == 4) { - SDOperand TmpBase, TmpOffImm; + SDValue TmpBase, TmpOffImm; if (SelectThumbAddrModeSP(Op, N, TmpBase, TmpOffImm)) return false; // We want to select tLDRspi / tSTRspi instead. if (N.getOpcode() == ARMISD::Wrapper && @@ -444,26 +444,26 @@ ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDOperand Op, SDOperand N, return true; } -bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDOperand Op, SDOperand N, - SDOperand &Base, SDOperand &OffImm, - SDOperand &Offset) { +bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDValue Op, SDValue N, + SDValue &Base, SDValue &OffImm, + SDValue &Offset) { return SelectThumbAddrModeRI5(Op, N, 1, Base, OffImm, Offset); } -bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDOperand Op, SDOperand N, - SDOperand &Base, SDOperand &OffImm, - SDOperand &Offset) { +bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDValue Op, SDValue N, + SDValue &Base, SDValue &OffImm, + SDValue &Offset) { return SelectThumbAddrModeRI5(Op, N, 2, Base, OffImm, Offset); } -bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDOperand Op, SDOperand N, - SDOperand &Base, SDOperand &OffImm, - SDOperand &Offset) { +bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDValue Op, SDValue N, + SDValue &Base, SDValue &OffImm, + SDValue &Offset) { return SelectThumbAddrModeRI5(Op, N, 4, Base, OffImm, Offset); } -bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDOperand Op, SDOperand N, - SDOperand &Base, SDOperand &OffImm) { +bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue Op, SDValue N, + SDValue &Base, SDValue &OffImm) { if (N.getOpcode() == ISD::FrameIndex) { int FI = cast<FrameIndexSDNode>(N)->getIndex(); Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); @@ -498,11 +498,11 @@ bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDOperand Op, SDOperand N, return false; } -bool ARMDAGToDAGISel::SelectShifterOperandReg(SDOperand Op, - SDOperand N, - SDOperand &BaseReg, - SDOperand &ShReg, - SDOperand &Opc) { +bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue Op, + SDValue N, + SDValue &BaseReg, + SDValue &ShReg, + SDValue &Opc) { ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N); // Don't match base register only case. That is matched to a separate @@ -523,12 +523,12 @@ bool ARMDAGToDAGISel::SelectShifterOperandReg(SDOperand Op, } /// getAL - Returns a ARMCC::AL immediate node. -static inline SDOperand getAL(SelectionDAG *CurDAG) { +static inline SDValue getAL(SelectionDAG *CurDAG) { return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32); } -SDNode *ARMDAGToDAGISel::Select(SDOperand Op) { +SDNode *ARMDAGToDAGISel::Select(SDValue Op) { SDNode *N = Op.Val; if (N->isMachineOpcode()) @@ -548,7 +548,7 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) { ARM_AM::getSOImmVal(~Val) == -1 && // MVN !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs. if (UseCP) { - SDOperand CPIdx = + SDValue CPIdx = CurDAG->getTargetConstantPool(ConstantInt::get(Type::Int32Ty, Val), TLI.getPointerTy()); @@ -557,7 +557,7 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) { ResNode = CurDAG->getTargetNode(ARM::tLDRcp, MVT::i32, MVT::Other, CPIdx, CurDAG->getEntryNode()); else { - SDOperand Ops[] = { + SDValue Ops[] = { CPIdx, CurDAG->getRegister(0, MVT::i32), CurDAG->getTargetConstant(0, MVT::i32), @@ -567,7 +567,7 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) { }; ResNode=CurDAG->getTargetNode(ARM::LDRcp, MVT::i32, MVT::Other, Ops, 6); } - ReplaceUses(Op, SDOperand(ResNode, 0)); + ReplaceUses(Op, SDValue(ResNode, 0)); return NULL; } @@ -577,12 +577,12 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) { case ISD::FrameIndex: { // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm. int FI = cast<FrameIndexSDNode>(N)->getIndex(); - SDOperand TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); + SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); if (Subtarget->isThumb()) return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI, CurDAG->getTargetConstant(0, MVT::i32)); else { - SDOperand Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32), + SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32), getAL(CurDAG), CurDAG->getRegister(0, MVT::i32), CurDAG->getRegister(0, MVT::i32) }; return CurDAG->SelectNodeTo(N, ARM::ADDri, MVT::i32, Ops, 5); @@ -590,8 +590,8 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) { } case ISD::ADD: { // Select add sp, c to tADDhirr. - SDOperand N0 = Op.getOperand(0); - SDOperand N1 = Op.getOperand(1); + SDValue N0 = Op.getOperand(0); + SDValue N1 = Op.getOperand(1); RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(Op.getOperand(0)); RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(Op.getOperand(1)); if (LHSR && LHSR->getReg() == ARM::SP) { @@ -612,20 +612,20 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) { unsigned RHSV = C->getValue(); if (!RHSV) break; if (isPowerOf2_32(RHSV-1)) { // 2^n+1? - SDOperand V = Op.getOperand(0); + SDValue V = Op.getOperand(0); AddToISelQueue(V); unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV-1)); - SDOperand Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32), + SDValue Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32), CurDAG->getTargetConstant(ShImm, MVT::i32), getAL(CurDAG), CurDAG->getRegister(0, MVT::i32), CurDAG->getRegister(0, MVT::i32) }; return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7); } if (isPowerOf2_32(RHSV+1)) { // 2^n-1? - SDOperand V = Op.getOperand(0); + SDValue V = Op.getOperand(0); AddToISelQueue(V); unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV+1)); - SDOperand Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32), + SDValue Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32), CurDAG->getTargetConstant(ShImm, MVT::i32), getAL(CurDAG), CurDAG->getRegister(0, MVT::i32), CurDAG->getRegister(0, MVT::i32) }; @@ -641,7 +641,7 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) { case ISD::UMUL_LOHI: { AddToISelQueue(Op.getOperand(0)); AddToISelQueue(Op.getOperand(1)); - SDOperand Ops[] = { Op.getOperand(0), Op.getOperand(1), + SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1), getAL(CurDAG), CurDAG->getRegister(0, MVT::i32), CurDAG->getRegister(0, MVT::i32) }; return CurDAG->getTargetNode(ARM::UMULL, MVT::i32, MVT::i32, Ops, 5); @@ -649,7 +649,7 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) { case ISD::SMUL_LOHI: { AddToISelQueue(Op.getOperand(0)); AddToISelQueue(Op.getOperand(1)); - SDOperand Ops[] = { Op.getOperand(0), Op.getOperand(1), + SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1), getAL(CurDAG), CurDAG->getRegister(0, MVT::i32), CurDAG->getRegister(0, MVT::i32) }; return CurDAG->getTargetNode(ARM::SMULL, MVT::i32, MVT::i32, Ops, 5); @@ -659,7 +659,7 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) { ISD::MemIndexedMode AM = LD->getAddressingMode(); MVT LoadedVT = LD->getMemoryVT(); if (AM != ISD::UNINDEXED) { - SDOperand Offset, AMOpc; + SDValue Offset, AMOpc; bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); unsigned Opcode = 0; bool Match = false; @@ -688,12 +688,12 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) { } if (Match) { - SDOperand Chain = LD->getChain(); - SDOperand Base = LD->getBasePtr(); + SDValue Chain = LD->getChain(); + SDValue Base = LD->getBasePtr(); AddToISelQueue(Chain); AddToISelQueue(Base); AddToISelQueue(Offset); - SDOperand Ops[]= { Base, Offset, AMOpc, getAL(CurDAG), + SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG), CurDAG->getRegister(0, MVT::i32), Chain }; return CurDAG->getTargetNode(Opcode, MVT::i32, MVT::i32, MVT::Other, Ops, 6); @@ -712,11 +712,11 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) { // Pattern complexity = 6 cost = 1 size = 0 unsigned Opc = Subtarget->isThumb() ? ARM::tBcc : ARM::Bcc; - SDOperand Chain = Op.getOperand(0); - SDOperand N1 = Op.getOperand(1); - SDOperand N2 = Op.getOperand(2); - SDOperand N3 = Op.getOperand(3); - SDOperand InFlag = Op.getOperand(4); + SDValue Chain = Op.getOperand(0); + SDValue N1 = Op.getOperand(1); + SDValue N2 = Op.getOperand(2); + SDValue N3 = Op.getOperand(3); + SDValue InFlag = Op.getOperand(4); assert(N1.getOpcode() == ISD::BasicBlock); assert(N2.getOpcode() == ISD::Constant); assert(N3.getOpcode() == ISD::Register); @@ -724,35 +724,35 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) { AddToISelQueue(Chain); AddToISelQueue(N1); AddToISelQueue(InFlag); - SDOperand Tmp2 = CurDAG->getTargetConstant(((unsigned) + SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getValue()), MVT::i32); - SDOperand Ops[] = { N1, Tmp2, N3, Chain, InFlag }; + SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag }; SDNode *ResNode = CurDAG->getTargetNode(Opc, MVT::Other, MVT::Flag, Ops, 5); - Chain = SDOperand(ResNode, 0); + Chain = SDValue(ResNode, 0); if (Op.Val->getNumValues() == 2) { - InFlag = SDOperand(ResNode, 1); - ReplaceUses(SDOperand(Op.Val, 1), InFlag); + InFlag = SDValue(ResNode, 1); + ReplaceUses(SDValue(Op.Val, 1), InFlag); } - ReplaceUses(SDOperand(Op.Val, 0), SDOperand(Chain.Val, Chain.ResNo)); + ReplaceUses(SDValue(Op.Val, 0), SDValue(Chain.Val, Chain.ResNo)); return NULL; } case ARMISD::CMOV: { bool isThumb = Subtarget->isThumb(); MVT VT = Op.getValueType(); - SDOperand N0 = Op.getOperand(0); - SDOperand N1 = Op.getOperand(1); - SDOperand N2 = Op.getOperand(2); - SDOperand N3 = Op.getOperand(3); - SDOperand InFlag = Op.getOperand(4); + SDValue N0 = Op.getOperand(0); + SDValue N1 = Op.getOperand(1); + SDValue N2 = Op.getOperand(2); + SDValue N3 = Op.getOperand(3); + SDValue InFlag = Op.getOperand(4); assert(N2.getOpcode() == ISD::Constant); assert(N3.getOpcode() == ISD::Register); // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc) // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc) // Pattern complexity = 18 cost = 1 size = 0 - SDOperand CPTmp0; - SDOperand CPTmp1; - SDOperand CPTmp2; + SDValue CPTmp0; + SDValue CPTmp1; + SDValue CPTmp2; if (!isThumb && VT == MVT::i32 && SelectShifterOperandReg(Op, N1, CPTmp0, CPTmp1, CPTmp2)) { AddToISelQueue(N0); @@ -760,9 +760,9 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) { AddToISelQueue(CPTmp1); AddToISelQueue(CPTmp2); AddToISelQueue(InFlag); - SDOperand Tmp2 = CurDAG->getTargetConstant(((unsigned) + SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getValue()), MVT::i32); - SDOperand Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3, InFlag }; + SDValue Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3, InFlag }; return CurDAG->SelectNodeTo(Op.Val, ARM::MOVCCs, MVT::i32, Ops, 7); } @@ -777,12 +777,12 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) { Predicate_so_imm(N3.Val)) { AddToISelQueue(N0); AddToISelQueue(InFlag); - SDOperand Tmp1 = CurDAG->getTargetConstant(((unsigned) + SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getValue()), MVT::i32); Tmp1 = Transform_so_imm_XFORM(Tmp1.Val); - SDOperand Tmp2 = CurDAG->getTargetConstant(((unsigned) + SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getValue()), MVT::i32); - SDOperand Ops[] = { N0, Tmp1, Tmp2, N3, InFlag }; + SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag }; return CurDAG->SelectNodeTo(Op.Val, ARM::MOVCCi, MVT::i32, Ops, 5); } @@ -798,9 +798,9 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) { AddToISelQueue(N0); AddToISelQueue(N1); AddToISelQueue(InFlag); - SDOperand Tmp2 = CurDAG->getTargetConstant(((unsigned) + SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getValue()), MVT::i32); - SDOperand Ops[] = { N0, N1, Tmp2, N3, InFlag }; + SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag }; unsigned Opc = 0; switch (VT.getSimpleVT()) { default: assert(false && "Illegal conditional move type!"); @@ -819,20 +819,20 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) { } case ARMISD::CNEG: { MVT VT = Op.getValueType(); - SDOperand N0 = Op.getOperand(0); - SDOperand N1 = Op.getOperand(1); - SDOperand N2 = Op.getOperand(2); - SDOperand N3 = Op.getOperand(3); - SDOperand InFlag = Op.getOperand(4); + SDValue N0 = Op.getOperand(0); + SDValue N1 = Op.getOperand(1); + SDValue N2 = Op.getOperand(2); + SDValue N3 = Op.getOperand(3); + SDValue InFlag = Op.getOperand(4); assert(N2.getOpcode() == ISD::Constant); assert(N3.getOpcode() == ISD::Register); AddToISelQueue(N0); AddToISelQueue(N1); AddToISelQueue(InFlag); - SDOperand Tmp2 = CurDAG->getTargetConstant(((unsigned) + SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getValue()), MVT::i32); - SDOperand Ops[] = { N0, N1, Tmp2, N3, InFlag }; + SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag }; unsigned Opc = 0; switch (VT.getSimpleVT()) { default: assert(false && "Illegal conditional move type!"); diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index afc7ebc..c696832 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -399,13 +399,13 @@ HowToPassArgument(MVT ObjectVT, unsigned NumGPRs, /// LowerCALL - Lowering a ISD::CALL node into a callseq_start <- /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter /// nodes. -SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) { +SDValue ARMTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) { MVT RetVT= Op.Val->getValueType(0); - SDOperand Chain = Op.getOperand(0); + SDValue Chain = Op.getOperand(0); unsigned CallConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); assert((CallConv == CallingConv::C || CallConv == CallingConv::Fast) && "unknown calling convention"); - SDOperand Callee = Op.getOperand(4); + SDValue Callee = Op.getOperand(4); unsigned NumOps = (Op.getNumOperands() - 5) / 2; unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot unsigned NumGPRs = 0; // GPRs used for parameter passing. @@ -433,17 +433,17 @@ SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) { Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes, MVT::i32)); - SDOperand StackPtr = DAG.getRegister(ARM::SP, MVT::i32); + SDValue StackPtr = DAG.getRegister(ARM::SP, MVT::i32); static const unsigned GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; NumGPRs = 0; - std::vector<std::pair<unsigned, SDOperand> > RegsToPass; - std::vector<SDOperand> MemOpChains; + std::vector<std::pair<unsigned, SDValue> > RegsToPass; + std::vector<SDValue> MemOpChains; for (unsigned i = 0; i != NumOps; ++i) { - SDOperand Arg = Op.getOperand(5+2*i); + SDValue Arg = Op.getOperand(5+2*i); ISD::ArgFlagsTy Flags = cast<ARG_FLAGSSDNode>(Op.getOperand(5+2*i+1))->getArgFlags(); MVT ArgVT = Arg.getValueType(); @@ -467,22 +467,22 @@ SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) { DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Arg))); break; case MVT::i64: { - SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg, + SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg, DAG.getConstant(0, getPointerTy())); - SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg, + SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg, DAG.getConstant(1, getPointerTy())); RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Lo)); if (ObjGPRs == 2) RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1], Hi)); else { - SDOperand PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType()); + SDValue PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType()); PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); MemOpChains.push_back(DAG.getStore(Chain, Hi, PtrOff, NULL, 0)); } break; } case MVT::f64: { - SDOperand Cvt = DAG.getNode(ARMISD::FMRRD, + SDValue Cvt = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1); RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Cvt)); @@ -490,7 +490,7 @@ SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) { RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1], Cvt.getValue(1))); else { - SDOperand PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType()); + SDValue PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType()); PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); MemOpChains.push_back(DAG.getStore(Chain, Cvt.getValue(1), PtrOff, NULL, 0)); @@ -500,7 +500,7 @@ SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) { } } else { assert(ObjSize != 0); - SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); + SDValue PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); } @@ -515,7 +515,7 @@ SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) { // Build a sequence of copy-to-reg nodes chained together with token chain // and flag operands which copy the outgoing args into the appropriate regs. - SDOperand InFlag; + SDValue InFlag; for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, InFlag); @@ -542,10 +542,10 @@ SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) { if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) { ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex, ARMCP::CPStub, 4); - SDOperand CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2); + SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2); CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0); - SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); + SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel); } else Callee = DAG.getTargetGlobalAddress(GV, getPointerTy()); @@ -559,10 +559,10 @@ SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) { if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) { ARMConstantPoolValue *CPV = new ARMConstantPoolValue(Sym, ARMPCLabelIndex, ARMCP::CPStub, 4); - SDOperand CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2); + SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2); CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0); - SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); + SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel); } else Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy()); @@ -587,7 +587,7 @@ SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) { InFlag = Chain.getValue(1); } - std::vector<SDOperand> Ops; + std::vector<SDValue> Ops; Ops.push_back(Chain); Ops.push_back(Callee); @@ -611,7 +611,7 @@ SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) { if (RetVT != MVT::Other) InFlag = Chain.getValue(1); - std::vector<SDOperand> ResultVals; + std::vector<SDValue> ResultVals; // If the call has results, copy the values out of the ret val registers. switch (RetVT.getSimpleVT()) { @@ -634,8 +634,8 @@ SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) { Chain.getValue(0))); break; case MVT::f64: { - SDOperand Lo = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag); - SDOperand Hi = DAG.getCopyFromReg(Lo, ARM::R1, MVT::i32, Lo.getValue(2)); + SDValue Lo = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag); + SDValue Hi = DAG.getCopyFromReg(Lo, ARM::R1, MVT::i32, Lo.getValue(2)); ResultVals.push_back(DAG.getNode(ARMISD::FMDRR, MVT::f64, Lo, Hi)); break; } @@ -645,19 +645,19 @@ SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) { return Chain; ResultVals.push_back(Chain); - SDOperand Res = DAG.getMergeValues(&ResultVals[0], ResultVals.size()); + SDValue Res = DAG.getMergeValues(&ResultVals[0], ResultVals.size()); return Res.getValue(Op.ResNo); } -static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { - SDOperand Copy; - SDOperand Chain = Op.getOperand(0); +static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) { + SDValue Copy; + SDValue Chain = Op.getOperand(0); switch(Op.getNumOperands()) { default: assert(0 && "Do not know how to return this many arguments!"); abort(); case 1: { - SDOperand LR = DAG.getRegister(ARM::LR, MVT::i32); + SDValue LR = DAG.getRegister(ARM::LR, MVT::i32); return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Chain); } case 3: @@ -668,16 +668,16 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is // available. Op = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32), &Op,1); - SDOperand Sign = DAG.getConstant(0, MVT::i32); + SDValue Sign = DAG.getConstant(0, MVT::i32); return DAG.getNode(ISD::RET, MVT::Other, Chain, Op, Sign, Op.getValue(1), Sign); } - Copy = DAG.getCopyToReg(Chain, ARM::R0, Op, SDOperand()); + Copy = DAG.getCopyToReg(Chain, ARM::R0, Op, SDValue()); if (DAG.getMachineFunction().getRegInfo().liveout_empty()) DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0); break; case 5: - Copy = DAG.getCopyToReg(Chain, ARM::R1, Op.getOperand(3), SDOperand()); + Copy = DAG.getCopyToReg(Chain, ARM::R1, Op.getOperand(3), SDValue()); Copy = DAG.getCopyToReg(Copy, ARM::R0, Op.getOperand(1), Copy.getValue(1)); // If we haven't noted the R0+R1 are live out, do so now. if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { @@ -686,7 +686,7 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { } break; case 9: // i128 -> 4 regs - Copy = DAG.getCopyToReg(Chain, ARM::R3, Op.getOperand(7), SDOperand()); + Copy = DAG.getCopyToReg(Chain, ARM::R3, Op.getOperand(7), SDValue()); Copy = DAG.getCopyToReg(Copy , ARM::R2, Op.getOperand(5), Copy.getValue(1)); Copy = DAG.getCopyToReg(Copy , ARM::R1, Op.getOperand(3), Copy.getValue(1)); Copy = DAG.getCopyToReg(Copy , ARM::R0, Op.getOperand(1), Copy.getValue(1)); @@ -711,10 +711,10 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only // be used to form addressing mode. These wrapped nodes will be selected // into MOVi. -static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) { +static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) { MVT PtrVT = Op.getValueType(); ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); - SDOperand Res; + SDValue Res; if (CP->isMachineConstantPoolEntry()) Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, CP->getAlignment()); @@ -725,7 +725,7 @@ static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) { } // Lower ISD::GlobalTLSAddress using the "general dynamic" model -SDOperand +SDValue ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) { MVT PtrVT = getPointerTy(); @@ -733,12 +733,12 @@ ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue, PCAdj, "tlsgd", true); - SDOperand Argument = DAG.getTargetConstantPool(CPV, PtrVT, 2); + SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 2); Argument = DAG.getNode(ARMISD::Wrapper, MVT::i32, Argument); Argument = DAG.getLoad(PtrVT, DAG.getEntryNode(), Argument, NULL, 0); - SDOperand Chain = Argument.getValue(1); + SDValue Chain = Argument.getValue(1); - SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); + SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); Argument = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Argument, PICLabel); // call __tls_get_addr. @@ -747,7 +747,7 @@ ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, Entry.Node = Argument; Entry.Ty = (const Type *) Type::Int32Ty; Args.push_back(Entry); - std::pair<SDOperand, SDOperand> CallResult = + std::pair<SDValue, SDValue> CallResult = LowerCallTo(Chain, (const Type *) Type::Int32Ty, false, false, false, CallingConv::C, false, DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG); @@ -756,15 +756,15 @@ ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, // Lower ISD::GlobalTLSAddress using the "initial exec" or // "local exec" model. -SDOperand +SDValue ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA, SelectionDAG &DAG) { GlobalValue *GV = GA->getGlobal(); - SDOperand Offset; - SDOperand Chain = DAG.getEntryNode(); + SDValue Offset; + SDValue Chain = DAG.getEntryNode(); MVT PtrVT = getPointerTy(); // Get the Thread Pointer - SDOperand ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, PtrVT); + SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, PtrVT); if (GV->isDeclaration()){ // initial exec model @@ -777,7 +777,7 @@ ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA, Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0); Chain = Offset.getValue(1); - SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); + SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); Offset = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Offset, PICLabel); Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0); @@ -795,8 +795,8 @@ ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA, return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset); } -SDOperand -ARMTargetLowering::LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) { +SDValue +ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) { // TODO: implement the "local dynamic" model assert(Subtarget->isTargetELF() && "TLS not implemented for non-ELF targets"); @@ -809,7 +809,7 @@ ARMTargetLowering::LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) { return LowerToTLSExecModels(GA, DAG); } -SDOperand ARMTargetLowering::LowerGlobalAddressELF(SDOperand Op, +SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) { MVT PtrVT = getPointerTy(); GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); @@ -818,17 +818,17 @@ SDOperand ARMTargetLowering::LowerGlobalAddressELF(SDOperand Op, bool UseGOTOFF = GV->hasInternalLinkage() || GV->hasHiddenVisibility(); ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ? "GOTOFF":"GOT"); - SDOperand CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2); + SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2); CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); - SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); - SDOperand Chain = Result.getValue(1); - SDOperand GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PtrVT); + SDValue Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); + SDValue Chain = Result.getValue(1); + SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PtrVT); Result = DAG.getNode(ISD::ADD, PtrVT, Result, GOT); if (!UseGOTOFF) Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0); return Result; } else { - SDOperand CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2); + SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2); CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); return DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); } @@ -842,13 +842,13 @@ static bool GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model RelocM) { (GV->isDeclaration() && !GV->hasNotBeenReadFromBitcode())); } -SDOperand ARMTargetLowering::LowerGlobalAddressDarwin(SDOperand Op, +SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) { MVT PtrVT = getPointerTy(); GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); Reloc::Model RelocM = getTargetMachine().getRelocationModel(); bool IsIndirect = GVIsIndirectSymbol(GV, RelocM); - SDOperand CPAddr; + SDValue CPAddr; if (RelocM == Reloc::Static) CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2); else { @@ -862,11 +862,11 @@ SDOperand ARMTargetLowering::LowerGlobalAddressDarwin(SDOperand Op, } CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); - SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); - SDOperand Chain = Result.getValue(1); + SDValue Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); + SDValue Chain = Result.getValue(1); if (RelocM == Reloc::PIC_) { - SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); + SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); Result = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel); } if (IsIndirect) @@ -875,7 +875,7 @@ SDOperand ARMTargetLowering::LowerGlobalAddressDarwin(SDOperand Op, return Result; } -SDOperand ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDOperand Op, +SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG){ assert(Subtarget->isTargetELF() && "GLOBAL OFFSET TABLE not implemented for non-ELF targets"); @@ -884,40 +884,40 @@ SDOperand ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDOperand Op, ARMConstantPoolValue *CPV = new ARMConstantPoolValue("_GLOBAL_OFFSET_TABLE_", ARMPCLabelIndex, ARMCP::CPValue, PCAdj); - SDOperand CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2); + SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2); CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); - SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); - SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); + SDValue Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); + SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); return DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel); } -static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) { +static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) { MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue(); switch (IntNo) { - default: return SDOperand(); // Don't custom lower most intrinsics. + default: return SDValue(); // Don't custom lower most intrinsics. case Intrinsic::arm_thread_pointer: return DAG.getNode(ARMISD::THREAD_POINTER, PtrVT); } } -static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG, +static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, unsigned VarArgsFrameIndex) { // vastart just stores the address of the VarArgsFrameIndex slot into the // memory location argument. MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); - SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); + SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0); } -static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG, +static SDValue LowerFORMAL_ARGUMENT(SDValue Op, SelectionDAG &DAG, unsigned ArgNo, unsigned &NumGPRs, unsigned &ArgOffset) { MachineFunction &MF = DAG.getMachineFunction(); MVT ObjectVT = Op.getValue(ArgNo).getValueType(); - SDOperand Root = Op.getOperand(0); - std::vector<SDOperand> ArgValues; + SDValue Root = Op.getOperand(0); + std::vector<SDValue> ArgValues; MachineRegisterInfo &RegInfo = MF.getRegInfo(); static const unsigned GPRArgRegs[] = { @@ -935,7 +935,7 @@ static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG, NumGPRs += GPRPad; ArgOffset += StackPad; - SDOperand ArgValue; + SDValue ArgValue; if (ObjGPRs == 1) { unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass); RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg); @@ -949,7 +949,7 @@ static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG, VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass); RegInfo.addLiveIn(GPRArgRegs[NumGPRs+1], VReg); - SDOperand ArgValue2 = DAG.getCopyFromReg(Root, VReg, MVT::i32); + SDValue ArgValue2 = DAG.getCopyFromReg(Root, VReg, MVT::i32); assert(ObjectVT != MVT::i64 && "i64 should already be lowered"); ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2); @@ -959,11 +959,11 @@ static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG, if (ObjSize) { MachineFrameInfo *MFI = MF.getFrameInfo(); int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); - SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); + SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); if (ObjGPRs == 0) ArgValue = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0); else { - SDOperand ArgValue2 = DAG.getLoad(MVT::i32, Root, FIN, NULL, 0); + SDValue ArgValue2 = DAG.getLoad(MVT::i32, Root, FIN, NULL, 0); assert(ObjectVT != MVT::i64 && "i64 should already be lowered"); ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2); } @@ -974,10 +974,10 @@ static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG, return ArgValue; } -SDOperand -ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) { - std::vector<SDOperand> ArgValues; - SDOperand Root = Op.getOperand(0); +SDValue +ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) { + std::vector<SDValue> ArgValues; + SDValue Root = Op.getOperand(0); unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot unsigned NumGPRs = 0; // GPRs used for parameter passing. @@ -1006,14 +1006,14 @@ ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) { AFI->setVarArgsRegSaveSize(VARegSaveSize); VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset + VARegSaveSize - VARegSize); - SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); + SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); - SmallVector<SDOperand, 4> MemOps; + SmallVector<SDValue, 4> MemOps; for (; NumGPRs < 4; ++NumGPRs) { unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass); RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg); - SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i32); - SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); + SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::i32); + SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); MemOps.push_back(Store); FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getConstant(4, getPointerTy())); @@ -1034,13 +1034,13 @@ ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) { } /// isFloatingPointZero - Return true if this is +0.0. -static bool isFloatingPointZero(SDOperand Op) { +static bool isFloatingPointZero(SDValue Op) { if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) return CFP->getValueAPF().isPosZero(); else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) { // Maybe this has already been legalized into the constant pool? if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) { - SDOperand WrapperOp = Op.getOperand(1).getOperand(0); + SDValue WrapperOp = Op.getOperand(1).getOperand(0); if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp)) if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) return CFP->getValueAPF().isPosZero(); @@ -1056,8 +1056,8 @@ static bool isLegalCmpImmediate(unsigned C, bool isThumb) { /// Returns appropriate ARM CMP (cmp) and corresponding condition code for /// the given operands. -static SDOperand getARMCmp(SDOperand LHS, SDOperand RHS, ISD::CondCode CC, - SDOperand &ARMCC, SelectionDAG &DAG, bool isThumb) { +static SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, + SDValue &ARMCC, SelectionDAG &DAG, bool isThumb) { if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.Val)) { unsigned C = RHSC->getValue(); if (!isLegalCmpImmediate(C, isThumb)) { @@ -1115,8 +1115,8 @@ static SDOperand getARMCmp(SDOperand LHS, SDOperand RHS, ISD::CondCode CC, } /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands. -static SDOperand getVFPCmp(SDOperand LHS, SDOperand RHS, SelectionDAG &DAG) { - SDOperand Cmp; +static SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG) { + SDValue Cmp; if (!isFloatingPointZero(RHS)) Cmp = DAG.getNode(ARMISD::CMPFP, MVT::Flag, LHS, RHS); else @@ -1124,19 +1124,19 @@ static SDOperand getVFPCmp(SDOperand LHS, SDOperand RHS, SelectionDAG &DAG) { return DAG.getNode(ARMISD::FMSTAT, MVT::Flag, Cmp); } -static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG, +static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) { MVT VT = Op.getValueType(); - SDOperand LHS = Op.getOperand(0); - SDOperand RHS = Op.getOperand(1); + SDValue LHS = Op.getOperand(0); + SDValue RHS = Op.getOperand(1); ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); - SDOperand TrueVal = Op.getOperand(2); - SDOperand FalseVal = Op.getOperand(3); + SDValue TrueVal = Op.getOperand(2); + SDValue FalseVal = Op.getOperand(3); if (LHS.getValueType() == MVT::i32) { - SDOperand ARMCC; - SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32); - SDOperand Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb()); + SDValue ARMCC; + SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); + SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb()); return DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal, ARMCC, CCR, Cmp); } @@ -1144,32 +1144,32 @@ static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG, if (FPCCToARMCC(CC, CondCode, CondCode2)) std::swap(TrueVal, FalseVal); - SDOperand ARMCC = DAG.getConstant(CondCode, MVT::i32); - SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32); - SDOperand Cmp = getVFPCmp(LHS, RHS, DAG); - SDOperand Result = DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal, + SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32); + SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); + SDValue Cmp = getVFPCmp(LHS, RHS, DAG); + SDValue Result = DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal, ARMCC, CCR, Cmp); if (CondCode2 != ARMCC::AL) { - SDOperand ARMCC2 = DAG.getConstant(CondCode2, MVT::i32); + SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32); // FIXME: Needs another CMP because flag can have but one use. - SDOperand Cmp2 = getVFPCmp(LHS, RHS, DAG); + SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG); Result = DAG.getNode(ARMISD::CMOV, VT, Result, TrueVal, ARMCC2, CCR, Cmp2); } return Result; } -static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG, +static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) { - SDOperand Chain = Op.getOperand(0); + SDValue Chain = Op.getOperand(0); ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); - SDOperand LHS = Op.getOperand(2); - SDOperand RHS = Op.getOperand(3); - SDOperand Dest = Op.getOperand(4); + SDValue LHS = Op.getOperand(2); + SDValue RHS = Op.getOperand(3); + SDValue Dest = Op.getOperand(4); if (LHS.getValueType() == MVT::i32) { - SDOperand ARMCC; - SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32); - SDOperand Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb()); + SDValue ARMCC; + SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); + SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb()); return DAG.getNode(ARMISD::BRCOND, MVT::Other, Chain, Dest, ARMCC, CCR,Cmp); } @@ -1179,33 +1179,33 @@ static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG, // Swap the LHS/RHS of the comparison if needed. std::swap(LHS, RHS); - SDOperand Cmp = getVFPCmp(LHS, RHS, DAG); - SDOperand ARMCC = DAG.getConstant(CondCode, MVT::i32); - SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32); + SDValue Cmp = getVFPCmp(LHS, RHS, DAG); + SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32); + SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag); - SDOperand Ops[] = { Chain, Dest, ARMCC, CCR, Cmp }; - SDOperand Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5); + SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp }; + SDValue Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5); if (CondCode2 != ARMCC::AL) { ARMCC = DAG.getConstant(CondCode2, MVT::i32); - SDOperand Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) }; + SDValue Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) }; Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5); } return Res; } -SDOperand ARMTargetLowering::LowerBR_JT(SDOperand Op, SelectionDAG &DAG) { - SDOperand Chain = Op.getOperand(0); - SDOperand Table = Op.getOperand(1); - SDOperand Index = Op.getOperand(2); +SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) { + SDValue Chain = Op.getOperand(0); + SDValue Table = Op.getOperand(1); + SDValue Index = Op.getOperand(2); MVT PTy = getPointerTy(); JumpTableSDNode *JT = cast<JumpTableSDNode>(Table); ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>(); - SDOperand UId = DAG.getConstant(AFI->createJumpTableUId(), PTy); - SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy); + SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy); + SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy); Table = DAG.getNode(ARMISD::WrapperJT, MVT::i32, JTI, UId); Index = DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(4, PTy)); - SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table); + SDValue Addr = DAG.getNode(ISD::ADD, PTy, Index, Table); bool isPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; Addr = DAG.getLoad(isPIC ? (MVT)MVT::i32 : PTy, Chain, Addr, NULL, 0); @@ -1215,14 +1215,14 @@ SDOperand ARMTargetLowering::LowerBR_JT(SDOperand Op, SelectionDAG &DAG) { return DAG.getNode(ARMISD::BR_JT, MVT::Other, Chain, Addr, JTI, UId); } -static SDOperand LowerFP_TO_INT(SDOperand Op, SelectionDAG &DAG) { +static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) { unsigned Opc = Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI; Op = DAG.getNode(Opc, MVT::f32, Op.getOperand(0)); return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); } -static SDOperand LowerINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { +static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) { MVT VT = Op.getValueType(); unsigned Opc = Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF; @@ -1231,39 +1231,39 @@ static SDOperand LowerINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { return DAG.getNode(Opc, VT, Op); } -static SDOperand LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) { +static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) { // Implement fcopysign with a fabs and a conditional fneg. - SDOperand Tmp0 = Op.getOperand(0); - SDOperand Tmp1 = Op.getOperand(1); + SDValue Tmp0 = Op.getOperand(0); + SDValue Tmp1 = Op.getOperand(1); MVT VT = Op.getValueType(); MVT SrcVT = Tmp1.getValueType(); - SDOperand AbsVal = DAG.getNode(ISD::FABS, VT, Tmp0); - SDOperand Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG); - SDOperand ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32); - SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32); + SDValue AbsVal = DAG.getNode(ISD::FABS, VT, Tmp0); + SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG); + SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32); + SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); return DAG.getNode(ARMISD::CNEG, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp); } -SDOperand +SDValue ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, - SDOperand Chain, - SDOperand Dst, SDOperand Src, - SDOperand Size, unsigned Align, + SDValue Chain, + SDValue Dst, SDValue Src, + SDValue Size, unsigned Align, bool AlwaysInline, const Value *DstSV, uint64_t DstSVOff, const Value *SrcSV, uint64_t SrcSVOff){ // Do repeated 4-byte loads and stores. To be improved. // This requires 4-byte alignment. if ((Align & 3) != 0) - return SDOperand(); + return SDValue(); // This requires the copy size to be a constant, preferrably // within a subtarget-specific limit. ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); if (!ConstantSize) - return SDOperand(); + return SDValue(); uint64_t SizeVal = ConstantSize->getValue(); if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold()) - return SDOperand(); + return SDValue(); unsigned BytesLeft = SizeVal & 3; unsigned NumMemOps = SizeVal >> 2; @@ -1272,8 +1272,8 @@ ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, unsigned VTSize = 4; unsigned i = 0; const unsigned MAX_LOADS_IN_LDM = 6; - SDOperand TFOps[MAX_LOADS_IN_LDM]; - SDOperand Loads[MAX_LOADS_IN_LDM]; + SDValue TFOps[MAX_LOADS_IN_LDM]; + SDValue Loads[MAX_LOADS_IN_LDM]; uint64_t SrcOff = 0, DstOff = 0; // Emit up to MAX_LOADS_IN_LDM loads, then a TokenFactor barrier, then the @@ -1357,8 +1357,8 @@ static SDNode *ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) { assert(N->getValueType(0) == MVT::i64 && N->getOperand(0).getValueType() == MVT::f64); - SDOperand Op = N->getOperand(0); - SDOperand Cvt = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32), + SDValue Op = N->getOperand(0); + SDValue Cvt = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32), &Op, 1); // Merge the pieces into a single i64 value. @@ -1379,9 +1379,9 @@ static SDNode *ExpandSRx(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) { if (ST->isThumb()) return 0; // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr. - SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0), + SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0), DAG.getConstant(0, MVT::i32)); - SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0), + SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0), DAG.getConstant(1, MVT::i32)); // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and @@ -1397,7 +1397,7 @@ static SDNode *ExpandSRx(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) { } -SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { +SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { switch (Op.getOpcode()) { default: assert(0 && "Don't know how to custom lower this!"); abort(); case ISD::ConstantPool: return LowerConstantPool(Op, DAG); @@ -1424,11 +1424,11 @@ SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { // FIXME: Remove these when LegalizeDAGTypes lands. - case ISD::BIT_CONVERT: return SDOperand(ExpandBIT_CONVERT(Op.Val, DAG), 0); + case ISD::BIT_CONVERT: return SDValue(ExpandBIT_CONVERT(Op.Val, DAG), 0); case ISD::SRL: - case ISD::SRA: return SDOperand(ExpandSRx(Op.Val, DAG,Subtarget),0); + case ISD::SRA: return SDValue(ExpandSRx(Op.Val, DAG,Subtarget),0); } - return SDOperand(); + return SDValue(); } @@ -1516,23 +1516,23 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, //===----------------------------------------------------------------------===// /// PerformFMRRDCombine - Target-specific dag combine xforms for ARMISD::FMRRD. -static SDOperand PerformFMRRDCombine(SDNode *N, +static SDValue PerformFMRRDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) { // fmrrd(fmdrr x, y) -> x,y - SDOperand InDouble = N->getOperand(0); + SDValue InDouble = N->getOperand(0); if (InDouble.getOpcode() == ARMISD::FMDRR) return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1)); - return SDOperand(); + return SDValue(); } -SDOperand ARMTargetLowering::PerformDAGCombine(SDNode *N, +SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { switch (N->getOpcode()) { default: break; case ARMISD::FMRRD: return PerformFMRRDCombine(N, DCI); } - return SDOperand(); + return SDValue(); } @@ -1654,8 +1654,8 @@ bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM, static bool getIndexedAddressParts(SDNode *Ptr, MVT VT, - bool isSEXTLoad, SDOperand &Base, - SDOperand &Offset, bool &isInc, + bool isSEXTLoad, SDValue &Base, + SDValue &Offset, bool &isInc, SelectionDAG &DAG) { if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB) return false; @@ -1713,15 +1713,15 @@ static bool getIndexedAddressParts(SDNode *Ptr, MVT VT, /// offset pointer and addressing mode by reference if the node's address /// can be legally represented as pre-indexed load / store address. bool -ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base, - SDOperand &Offset, +ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, + SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) { if (Subtarget->isThumb()) return false; MVT VT; - SDOperand Ptr; + SDValue Ptr; bool isSEXTLoad = false; if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { Ptr = LD->getBasePtr(); @@ -1747,15 +1747,15 @@ ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base, /// offset pointer and addressing mode by reference if this node can be /// combined with a load / store to form a post-indexed load / store. bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, - SDOperand &Base, - SDOperand &Offset, + SDValue &Base, + SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) { if (Subtarget->isThumb()) return false; MVT VT; - SDOperand Ptr; + SDValue Ptr; bool isSEXTLoad = false; if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { VT = LD->getMemoryVT(); @@ -1775,7 +1775,7 @@ bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, return false; } -void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, +void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, const APInt &Mask, APInt &KnownZero, APInt &KnownOne, diff --git a/lib/Target/ARM/ARMISelLowering.h b/lib/Target/ARM/ARMISelLowering.h index 969d42b..b717e0d 100644 --- a/lib/Target/ARM/ARMISelLowering.h +++ b/lib/Target/ARM/ARMISelLowering.h @@ -75,10 +75,10 @@ namespace llvm { public: explicit ARMTargetLowering(TargetMachine &TM); - virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); + virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); virtual SDNode *ReplaceNodeResults(SDNode *N, SelectionDAG &DAG); - virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; + virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; virtual const char *getTargetNodeName(unsigned Opcode) const; @@ -92,8 +92,8 @@ namespace llvm { /// getPreIndexedAddressParts - returns true by value, base pointer and /// offset pointer and addressing mode by reference if the node's address /// can be legally represented as pre-indexed load / store address. - virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base, - SDOperand &Offset, + virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, + SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG); @@ -101,11 +101,11 @@ namespace llvm { /// offset pointer and addressing mode by reference if this node can be /// combined with a load / store to form a post-indexed load / store. virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, - SDOperand &Base, SDOperand &Offset, + SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG); - virtual void computeMaskedBitsForTargetNode(const SDOperand Op, + virtual void computeMaskedBitsForTargetNode(const SDValue Op, const APInt &Mask, APInt &KnownZero, APInt &KnownOne, @@ -132,22 +132,22 @@ namespace llvm { /// unsigned ARMPCLabelIndex; - SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerGlobalAddressDarwin(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerGlobalAddressELF(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, + SDValue LowerCALL(SDValue Op, SelectionDAG &DAG); + SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG); + SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG); + SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG); + SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, SelectionDAG &DAG); - SDOperand LowerToTLSExecModels(GlobalAddressSDNode *GA, + SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA, SelectionDAG &DAG); - SDOperand LowerGLOBAL_OFFSET_TABLE(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerBR_JT(SDOperand Op, SelectionDAG &DAG); - - SDOperand EmitTargetCodeForMemcpy(SelectionDAG &DAG, - SDOperand Chain, - SDOperand Dst, SDOperand Src, - SDOperand Size, unsigned Align, + SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG); + SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG); + SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG); + + SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, + SDValue Chain, + SDValue Dst, SDValue Src, + SDValue Size, unsigned Align, bool AlwaysInline, const Value *DstSV, uint64_t DstSVOff, const Value *SrcSV, uint64_t SrcSVOff); diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 34487ff..a5719e4 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -152,7 +152,7 @@ def so_imm_not : // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits. def sext_16_node : PatLeaf<(i32 GPR:$a), [{ - return CurDAG->ComputeNumSignBits(SDOperand(N,0)) >= 17; + return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17; }]>; diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp index 01a6856..89dee2a 100644 --- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp +++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp @@ -65,7 +65,7 @@ namespace { /// that the bits 1-7 of LHS are already zero. If LHS is non-null, we are /// in checking mode. If LHS is null, we assume that the mask has already /// been validated before. - uint64_t get_zapImm(SDOperand LHS, uint64_t Constant) { + uint64_t get_zapImm(SDValue LHS, uint64_t Constant) { uint64_t BitsToCheck = 0; unsigned Result = 0; for (unsigned i = 0; i != 8; ++i) { @@ -132,15 +132,15 @@ namespace { return (x - y) == r; } - static bool isFPZ(SDOperand N) { + static bool isFPZ(SDValue N) { ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N); return (CN && (CN->getValueAPF().isZero())); } - static bool isFPZn(SDOperand N) { + static bool isFPZn(SDValue N) { ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N); return (CN && CN->getValueAPF().isNegZero()); } - static bool isFPZp(SDOperand N) { + static bool isFPZp(SDValue N) { ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N); return (CN && CN->getValueAPF().isPosZero()); } @@ -153,13 +153,13 @@ namespace { /// getI64Imm - Return a target constant with the specified value, of type /// i64. - inline SDOperand getI64Imm(int64_t Imm) { + inline SDValue getI64Imm(int64_t Imm) { return CurDAG->getTargetConstant(Imm, MVT::i64); } // Select - Convert the specified operand from a target-independent to a // target-specific node if it hasn't already been changed. - SDNode *Select(SDOperand Op); + SDNode *Select(SDValue Op); /// InstructionSelect - This callback is invoked by /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. @@ -171,11 +171,11 @@ namespace { /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for /// inline asm expressions. - virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op, + virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, - std::vector<SDOperand> &OutOps, + std::vector<SDValue> &OutOps, SelectionDAG &DAG) { - SDOperand Op0; + SDValue Op0; switch (ConstraintCode) { default: return true; case 'm': // memory @@ -192,9 +192,9 @@ namespace { #include "AlphaGenDAGISel.inc" private: - SDOperand getGlobalBaseReg(); - SDOperand getGlobalRetAddr(); - void SelectCALL(SDOperand Op); + SDValue getGlobalBaseReg(); + SDValue getGlobalRetAddr(); + void SelectCALL(SDValue Op); }; } @@ -202,7 +202,7 @@ private: /// getGlobalBaseReg - Output the instructions required to put the /// GOT address into a register. /// -SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() { +SDValue AlphaDAGToDAGISel::getGlobalBaseReg() { unsigned GP = 0; for(MachineRegisterInfo::livein_iterator ii = RegInfo->livein_begin(), ee = RegInfo->livein_end(); ii != ee; ++ii) @@ -217,7 +217,7 @@ SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() { /// getRASaveReg - Grab the return address /// -SDOperand AlphaDAGToDAGISel::getGlobalRetAddr() { +SDValue AlphaDAGToDAGISel::getGlobalRetAddr() { unsigned RA = 0; for(MachineRegisterInfo::livein_iterator ii = RegInfo->livein_begin(), ee = RegInfo->livein_end(); ii != ee; ++ii) @@ -242,7 +242,7 @@ void AlphaDAGToDAGISel::InstructionSelect(SelectionDAG &DAG) { // Select - Convert the specified operand from a target-independent to a // target-specific node if it hasn't already been changed. -SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) { +SDNode *AlphaDAGToDAGISel::Select(SDValue Op) { SDNode *N = Op.Val; if (N->isMachineOpcode()) { return NULL; // Already selected. @@ -261,26 +261,26 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) { getI64Imm(0)); } case ISD::GLOBAL_OFFSET_TABLE: { - SDOperand Result = getGlobalBaseReg(); + SDValue Result = getGlobalBaseReg(); ReplaceUses(Op, Result); return NULL; } case AlphaISD::GlobalRetAddr: { - SDOperand Result = getGlobalRetAddr(); + SDValue Result = getGlobalRetAddr(); ReplaceUses(Op, Result); return NULL; } case AlphaISD::DivCall: { - SDOperand Chain = CurDAG->getEntryNode(); - SDOperand N0 = Op.getOperand(0); - SDOperand N1 = Op.getOperand(1); - SDOperand N2 = Op.getOperand(2); + SDValue Chain = CurDAG->getEntryNode(); + SDValue N0 = Op.getOperand(0); + SDValue N1 = Op.getOperand(1); + SDValue N2 = Op.getOperand(2); AddToISelQueue(N0); AddToISelQueue(N1); AddToISelQueue(N2); Chain = CurDAG->getCopyToReg(Chain, Alpha::R24, N1, - SDOperand(0,0)); + SDValue(0,0)); Chain = CurDAG->getCopyToReg(Chain, Alpha::R25, N2, Chain.getValue(1)); Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, N0, @@ -289,12 +289,12 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) { CurDAG->getTargetNode(Alpha::JSRs, MVT::Other, MVT::Flag, Chain, Chain.getValue(1)); Chain = CurDAG->getCopyFromReg(Chain, Alpha::R27, MVT::i64, - SDOperand(CNode, 1)); + SDValue(CNode, 1)); return CurDAG->SelectNodeTo(N, Alpha::BISr, MVT::i64, Chain, Chain); } case ISD::READCYCLECOUNTER: { - SDOperand Chain = N->getOperand(0); + SDValue Chain = N->getOperand(0); AddToISelQueue(Chain); //Select chain return CurDAG->getTargetNode(Alpha::RPCC, MVT::i64, MVT::Other, Chain); @@ -304,7 +304,7 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) { uint64_t uval = cast<ConstantSDNode>(N)->getValue(); if (uval == 0) { - SDOperand Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), + SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), Alpha::R31, MVT::i64); ReplaceUses(Op, Result); return NULL; @@ -321,11 +321,11 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) { break; //(zext (LDAH (LDA))) //Else use the constant pool ConstantInt *C = ConstantInt::get(Type::Int64Ty, uval); - SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64); + SDValue CPI = CurDAG->getTargetConstantPool(C, MVT::i64); SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI, getGlobalBaseReg()); return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other, - CPI, SDOperand(Tmp, 0), CurDAG->getEntryNode()); + CPI, SDValue(Tmp, 0), CurDAG->getEntryNode()); } case ISD::TargetConstantFP: { ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N); @@ -371,13 +371,13 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) { case ISD::SETUO: Opc = Alpha::CMPTUN; break; }; - SDOperand tmp1 = N->getOperand(rev?1:0); - SDOperand tmp2 = N->getOperand(rev?0:1); + SDValue tmp1 = N->getOperand(rev?1:0); + SDValue tmp2 = N->getOperand(rev?0:1); AddToISelQueue(tmp1); AddToISelQueue(tmp2); SDNode *cmp = CurDAG->getTargetNode(Opc, MVT::f64, tmp1, tmp2); if (inv) - cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, MVT::f64, SDOperand(cmp, 0), + cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, MVT::f64, SDValue(cmp, 0), CurDAG->getRegister(Alpha::F31, MVT::f64)); switch(CC) { case ISD::SETUEQ: case ISD::SETULT: case ISD::SETULE: @@ -386,16 +386,16 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) { SDNode* cmp2 = CurDAG->getTargetNode(Alpha::CMPTUN, MVT::f64, tmp1, tmp2); cmp = CurDAG->getTargetNode(Alpha::ADDT, MVT::f64, - SDOperand(cmp2, 0), SDOperand(cmp, 0)); + SDValue(cmp2, 0), SDValue(cmp, 0)); break; } default: break; } - SDNode* LD = CurDAG->getTargetNode(Alpha::FTOIT, MVT::i64, SDOperand(cmp, 0)); + SDNode* LD = CurDAG->getTargetNode(Alpha::FTOIT, MVT::i64, SDValue(cmp, 0)); return CurDAG->getTargetNode(Alpha::CMPULT, MVT::i64, CurDAG->getRegister(Alpha::R31, MVT::i64), - SDOperand(LD,0)); + SDValue(LD,0)); } break; @@ -408,16 +408,16 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) { // so that things like this can be caught in fall though code //move int to fp bool isDouble = N->getValueType(0) == MVT::f64; - SDOperand cond = N->getOperand(0); - SDOperand TV = N->getOperand(1); - SDOperand FV = N->getOperand(2); + SDValue cond = N->getOperand(0); + SDValue TV = N->getOperand(1); + SDValue FV = N->getOperand(2); AddToISelQueue(cond); AddToISelQueue(TV); AddToISelQueue(FV); SDNode* LD = CurDAG->getTargetNode(Alpha::ITOFT, MVT::f64, cond); return CurDAG->getTargetNode(isDouble?Alpha::FCMOVNET:Alpha::FCMOVNES, - MVT::f64, FV, TV, SDOperand(LD,0)); + MVT::f64, FV, TV, SDValue(LD,0)); } break; @@ -442,8 +442,8 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) { if (get_zapImm(mask)) { AddToISelQueue(N->getOperand(0).getOperand(0)); - SDOperand Z = - SDOperand(CurDAG->getTargetNode(Alpha::ZAPNOTi, MVT::i64, + SDValue Z = + SDValue(CurDAG->getTargetNode(Alpha::ZAPNOTi, MVT::i64, N->getOperand(0).getOperand(0), getI64Imm(get_zapImm(mask))), 0); return CurDAG->getTargetNode(Alpha::SRLr, MVT::i64, Z, @@ -458,16 +458,16 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) { return SelectCode(Op); } -void AlphaDAGToDAGISel::SelectCALL(SDOperand Op) { +void AlphaDAGToDAGISel::SelectCALL(SDValue Op) { //TODO: add flag stuff to prevent nondeturministic breakage! SDNode *N = Op.Val; - SDOperand Chain = N->getOperand(0); - SDOperand Addr = N->getOperand(1); - SDOperand InFlag(0,0); // Null incoming flag value. + SDValue Chain = N->getOperand(0); + SDValue Addr = N->getOperand(1); + SDValue InFlag(0,0); // Null incoming flag value. AddToISelQueue(Chain); - std::vector<SDOperand> CallOperands; + std::vector<SDValue> CallOperands; std::vector<MVT> TypeOperands; //grab the arguments @@ -494,10 +494,10 @@ void AlphaDAGToDAGISel::SelectCALL(SDOperand Op) { } else assert(0 && "Unknown operand"); - SDOperand Ops[] = { CallOperands[i], getI64Imm((i - 6) * 8), + SDValue Ops[] = { CallOperands[i], getI64Imm((i - 6) * 8), CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64), Chain }; - Chain = SDOperand(CurDAG->getTargetNode(Opc, MVT::Other, Ops, 4), 0); + Chain = SDValue(CurDAG->getTargetNode(Opc, MVT::Other, Ops, 4), 0); } for (int i = 0; i < std::min(6, count); ++i) { if (TypeOperands[i].isInteger()) { @@ -513,21 +513,21 @@ void AlphaDAGToDAGISel::SelectCALL(SDOperand Op) { // Finally, once everything is in registers to pass to the call, emit the // call itself. if (Addr.getOpcode() == AlphaISD::GPRelLo) { - SDOperand GOT = getGlobalBaseReg(); + SDValue GOT = getGlobalBaseReg(); Chain = CurDAG->getCopyToReg(Chain, Alpha::R29, GOT, InFlag); InFlag = Chain.getValue(1); - Chain = SDOperand(CurDAG->getTargetNode(Alpha::BSR, MVT::Other, MVT::Flag, + Chain = SDValue(CurDAG->getTargetNode(Alpha::BSR, MVT::Other, MVT::Flag, Addr.getOperand(0), Chain, InFlag), 0); } else { AddToISelQueue(Addr); Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Addr, InFlag); InFlag = Chain.getValue(1); - Chain = SDOperand(CurDAG->getTargetNode(Alpha::JSR, MVT::Other, MVT::Flag, + Chain = SDValue(CurDAG->getTargetNode(Alpha::JSR, MVT::Other, MVT::Flag, Chain, InFlag), 0); } InFlag = Chain.getValue(1); - std::vector<SDOperand> CallResults; + std::vector<SDValue> CallResults; switch (N->getValueType(0).getSimpleVT()) { default: assert(0 && "Unexpected ret value!"); diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp index 0f7fd80..5128646 100644 --- a/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/lib/Target/Alpha/AlphaISelLowering.cpp @@ -146,7 +146,7 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) computeRegisterProperties(); } -MVT AlphaTargetLowering::getSetCCResultType(const SDOperand &) const { +MVT AlphaTargetLowering::getSetCCResultType(const SDValue &) const { return MVT::i64; } @@ -168,15 +168,15 @@ const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const { } } -static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) { +static SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) { MVT PtrVT = Op.getValueType(); JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); - SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); - SDOperand Zero = DAG.getConstant(0, PtrVT); + SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); + SDValue Zero = DAG.getConstant(0, PtrVT); - SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, JTI, + SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, JTI, DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64)); - SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, JTI, Hi); + SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, JTI, Hi); return Lo; } @@ -199,13 +199,13 @@ static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) { // //#define GP $29 // //#define SP $30 -static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, +static SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG, int &VarArgsBase, int &VarArgsOffset) { MachineFunction &MF = DAG.getMachineFunction(); MachineFrameInfo *MFI = MF.getFrameInfo(); - std::vector<SDOperand> ArgValues; - SDOperand Root = Op.getOperand(0); + std::vector<SDValue> ArgValues; + SDValue Root = Op.getOperand(0); AddLiveIn(MF, Alpha::R29, &Alpha::GPRCRegClass); //GP AddLiveIn(MF, Alpha::R26, &Alpha::GPRCRegClass); //RA @@ -216,9 +216,9 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21}; for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) { - SDOperand argt; + SDValue argt; MVT ObjectVT = Op.getValue(ArgNo).getValueType(); - SDOperand ArgVal; + SDValue ArgVal; if (ArgNo < 6) { switch (ObjectVT.getSimpleVT()) { @@ -246,7 +246,7 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, // Create the SelectionDAG nodes corresponding to a load //from this parameter - SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64); + SDValue FIN = DAG.getFrameIndex(FI, MVT::i64); ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0); } ArgValues.push_back(ArgVal); @@ -256,14 +256,14 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; if (isVarArg) { VarArgsOffset = (Op.Val->getNumValues()-1) * 8; - std::vector<SDOperand> LS; + std::vector<SDValue> LS; for (int i = 0; i < 6; ++i) { if (TargetRegisterInfo::isPhysicalRegister(args_int[i])) args_int[i] = AddLiveIn(MF, args_int[i], &Alpha::GPRCRegClass); - SDOperand argt = DAG.getCopyFromReg(Root, args_int[i], MVT::i64); + SDValue argt = DAG.getCopyFromReg(Root, args_int[i], MVT::i64); int FI = MFI->CreateFixedObject(8, -8 * (6 - i)); if (i == 0) VarArgsBase = FI; - SDOperand SDFI = DAG.getFrameIndex(FI, MVT::i64); + SDValue SDFI = DAG.getFrameIndex(FI, MVT::i64); LS.push_back(DAG.getStore(Root, argt, SDFI, NULL, 0)); if (TargetRegisterInfo::isPhysicalRegister(args_float[i])) @@ -285,18 +285,18 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, ArgValues.size()); } -static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { - SDOperand Copy = DAG.getCopyToReg(Op.getOperand(0), Alpha::R26, +static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) { + SDValue Copy = DAG.getCopyToReg(Op.getOperand(0), Alpha::R26, DAG.getNode(AlphaISD::GlobalRetAddr, MVT::i64), - SDOperand()); + SDValue()); switch (Op.getNumOperands()) { default: assert(0 && "Do not know how to return this many arguments!"); abort(); case 1: break; - //return SDOperand(); // ret void is legal + //return SDValue(); // ret void is legal case 3: { MVT ArgVT = Op.getOperand(1).getValueType(); unsigned ArgReg; @@ -315,11 +315,11 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { return DAG.getNode(AlphaISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); } -std::pair<SDOperand, SDOperand> -AlphaTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, +std::pair<SDValue, SDValue> +AlphaTargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt, bool isVarArg, unsigned CallingConv, bool isTailCall, - SDOperand Callee, ArgListTy &Args, + SDValue Callee, ArgListTy &Args, SelectionDAG &DAG) { int NumBytes = 0; if (Args.size() > 6) @@ -327,7 +327,7 @@ AlphaTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes, getPointerTy())); - std::vector<SDOperand> args_to_use; + std::vector<SDValue> args_to_use; for (unsigned i = 0, e = Args.size(); i != e; ++i) { switch (getValueType(Args[i].Ty).getSimpleVT()) { @@ -363,17 +363,17 @@ AlphaTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, RetVals.push_back(ActualRetTyVT); RetVals.push_back(MVT::Other); - std::vector<SDOperand> Ops; + std::vector<SDValue> Ops; Ops.push_back(Chain); Ops.push_back(Callee); Ops.insert(Ops.end(), args_to_use.begin(), args_to_use.end()); - SDOperand TheCall = DAG.getNode(AlphaISD::CALL, RetVals, &Ops[0], Ops.size()); + SDValue TheCall = DAG.getNode(AlphaISD::CALL, RetVals, &Ops[0], Ops.size()); Chain = TheCall.getValue(RetTyVT != MVT::isVoid); Chain = DAG.getCALLSEQ_END(Chain, DAG.getConstant(NumBytes, getPointerTy()), DAG.getConstant(0, getPointerTy()), - SDOperand()); - SDOperand RetVal = TheCall; + SDValue()); + SDValue RetVal = TheCall; if (RetTyVT != ActualRetTyVT) { ISD::NodeType AssertKind = ISD::DELETED_NODE; @@ -392,29 +392,29 @@ AlphaTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, return std::make_pair(RetVal, Chain); } -void AlphaTargetLowering::LowerVAARG(SDNode *N, SDOperand &Chain, - SDOperand &DataPtr, SelectionDAG &DAG) { +void AlphaTargetLowering::LowerVAARG(SDNode *N, SDValue &Chain, + SDValue &DataPtr, SelectionDAG &DAG) { Chain = N->getOperand(0); - SDOperand VAListP = N->getOperand(1); + SDValue VAListP = N->getOperand(1); const Value *VAListS = cast<SrcValueSDNode>(N->getOperand(2))->getValue(); - SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP, VAListS, 0); - SDOperand Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP, + SDValue Base = DAG.getLoad(MVT::i64, Chain, VAListP, VAListS, 0); + SDValue Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP, DAG.getConstant(8, MVT::i64)); - SDOperand Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1), + SDValue Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1), Tmp, NULL, 0, MVT::i32); DataPtr = DAG.getNode(ISD::ADD, MVT::i64, Base, Offset); if (N->getValueType(0).isFloatingPoint()) { //if fp && Offset < 6*8, then subtract 6*8 from DataPtr - SDOperand FPDataPtr = DAG.getNode(ISD::SUB, MVT::i64, DataPtr, + SDValue FPDataPtr = DAG.getNode(ISD::SUB, MVT::i64, DataPtr, DAG.getConstant(8*6, MVT::i64)); - SDOperand CC = DAG.getSetCC(MVT::i64, Offset, + SDValue CC = DAG.getSetCC(MVT::i64, Offset, DAG.getConstant(8*6, MVT::i64), ISD::SETLT); DataPtr = DAG.getNode(ISD::SELECT, MVT::i64, CC, FPDataPtr, DataPtr); } - SDOperand NewOffset = DAG.getNode(ISD::ADD, MVT::i64, Offset, + SDValue NewOffset = DAG.getNode(ISD::ADD, MVT::i64, Offset, DAG.getConstant(8, MVT::i64)); Chain = DAG.getTruncStore(Offset.getValue(1), NewOffset, Tmp, NULL, 0, MVT::i32); @@ -422,7 +422,7 @@ void AlphaTargetLowering::LowerVAARG(SDNode *N, SDOperand &Chain, /// LowerOperation - Provide custom lowering hooks for some operations. /// -SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { +SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { switch (Op.getOpcode()) { default: assert(0 && "Wasn't expecting to be able to lower this!"); case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG, @@ -435,16 +435,16 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { case ISD::SINT_TO_FP: { assert(Op.getOperand(0).getValueType() == MVT::i64 && "Unhandled SINT_TO_FP type in custom expander!"); - SDOperand LD; + SDValue LD; bool isDouble = Op.getValueType() == MVT::f64; LD = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0)); - SDOperand FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_, + SDValue FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_, isDouble?MVT::f64:MVT::f32, LD); return FP; } case ISD::FP_TO_SINT: { bool isDouble = Op.getOperand(0).getValueType() == MVT::f64; - SDOperand src = Op.getOperand(0); + SDValue src = Op.getOperand(0); if (!isDouble) //Promote src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, src); @@ -456,11 +456,11 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { case ISD::ConstantPool: { ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); Constant *C = CP->getConstVal(); - SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i64, CP->getAlignment()); + SDValue CPI = DAG.getTargetConstantPool(C, MVT::i64, CP->getAlignment()); - SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, CPI, + SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, CPI, DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64)); - SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, CPI, Hi); + SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, CPI, Hi); return Lo; } case ISD::GlobalTLSAddress: @@ -468,13 +468,13 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { case ISD::GlobalAddress: { GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); GlobalValue *GV = GSDN->getGlobal(); - SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset()); + SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset()); // if (!GV->hasWeakLinkage() && !GV->isDeclaration() && !GV->hasLinkOnceLinkage()) { if (GV->hasInternalLinkage()) { - SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, GA, + SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, GA, DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64)); - SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi); + SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi); return Lo; } else return DAG.getNode(AlphaISD::RelLit, MVT::i64, GA, @@ -492,7 +492,7 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { //Expand only on constant case if (Op.getOperand(1).getOpcode() == ISD::Constant) { MVT VT = Op.Val->getValueType(0); - SDOperand Tmp1 = Op.Val->getOpcode() == ISD::UREM ? + SDValue Tmp1 = Op.Val->getOpcode() == ISD::UREM ? BuildUDIV(Op.Val, DAG, NULL) : BuildSDIV(Op.Val, DAG, NULL); Tmp1 = DAG.getNode(ISD::MUL, VT, Tmp1, Op.getOperand(1)); @@ -513,7 +513,7 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { case ISD::UDIV: opstr = "__divqu"; break; case ISD::SDIV: opstr = "__divq"; break; } - SDOperand Tmp1 = Op.getOperand(0), + SDValue Tmp1 = Op.getOperand(0), Tmp2 = Op.getOperand(1), Addr = DAG.getExternalSymbol(opstr, MVT::i64); return DAG.getNode(AlphaISD::DivCall, MVT::i64, Addr, Tmp1, Tmp2); @@ -521,10 +521,10 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { break; case ISD::VAARG: { - SDOperand Chain, DataPtr; + SDValue Chain, DataPtr; LowerVAARG(Op.Val, Chain, DataPtr, DAG); - SDOperand Result; + SDValue Result; if (Op.getValueType() == MVT::i32) Result = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Chain, DataPtr, NULL, 0, MVT::i32); @@ -533,30 +533,30 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { return Result; } case ISD::VACOPY: { - SDOperand Chain = Op.getOperand(0); - SDOperand DestP = Op.getOperand(1); - SDOperand SrcP = Op.getOperand(2); + SDValue Chain = Op.getOperand(0); + SDValue DestP = Op.getOperand(1); + SDValue SrcP = Op.getOperand(2); const Value *DestS = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); const Value *SrcS = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); - SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP, SrcS, 0); - SDOperand Result = DAG.getStore(Val.getValue(1), Val, DestP, DestS, 0); - SDOperand NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP, + SDValue Val = DAG.getLoad(getPointerTy(), Chain, SrcP, SrcS, 0); + SDValue Result = DAG.getStore(Val.getValue(1), Val, DestP, DestS, 0); + SDValue NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP, DAG.getConstant(8, MVT::i64)); Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP, NULL,0, MVT::i32); - SDOperand NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP, + SDValue NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP, DAG.getConstant(8, MVT::i64)); return DAG.getTruncStore(Val.getValue(1), Val, NPD, NULL, 0, MVT::i32); } case ISD::VASTART: { - SDOperand Chain = Op.getOperand(0); - SDOperand VAListP = Op.getOperand(1); + SDValue Chain = Op.getOperand(0); + SDValue VAListP = Op.getOperand(1); const Value *VAListS = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); // vastart stores the address of the VarArgsBase and VarArgsOffset - SDOperand FR = DAG.getFrameIndex(VarArgsBase, MVT::i64); - SDOperand S1 = DAG.getStore(Chain, FR, VAListP, VAListS, 0); - SDOperand SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP, + SDValue FR = DAG.getFrameIndex(VarArgsBase, MVT::i64); + SDValue S1 = DAG.getStore(Chain, FR, VAListP, VAListS, 0); + SDValue SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP, DAG.getConstant(8, MVT::i64)); return DAG.getTruncStore(S1, DAG.getConstant(VarArgsOffset, MVT::i64), SA2, NULL, 0, MVT::i32); @@ -567,7 +567,7 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { case ISD::FRAMEADDR: break; } - return SDOperand(); + return SDValue(); } SDNode *AlphaTargetLowering::ReplaceNodeResults(SDNode *N, @@ -576,7 +576,7 @@ SDNode *AlphaTargetLowering::ReplaceNodeResults(SDNode *N, N->getOpcode() == ISD::VAARG && "Unknown node to custom promote!"); - SDOperand Chain, DataPtr; + SDValue Chain, DataPtr; LowerVAARG(N, Chain, DataPtr, DAG); return DAG.getLoad(N->getValueType(0), Chain, DataPtr, NULL, 0).Val; } diff --git a/lib/Target/Alpha/AlphaISelLowering.h b/lib/Target/Alpha/AlphaISelLowering.h index 1440908..770dde3 100644 --- a/lib/Target/Alpha/AlphaISelLowering.h +++ b/lib/Target/Alpha/AlphaISelLowering.h @@ -67,11 +67,11 @@ namespace llvm { explicit AlphaTargetLowering(TargetMachine &TM); /// getSetCCResultType - Get the SETCC result ValueType - virtual MVT getSetCCResultType(const SDOperand &) const; + virtual MVT getSetCCResultType(const SDValue &) const; /// LowerOperation - Provide custom lowering hooks for some operations. /// - virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); + virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); virtual SDNode *ReplaceNodeResults(SDNode *N, SelectionDAG &DAG); // Friendly names for dumps @@ -79,9 +79,9 @@ namespace llvm { /// LowerCallTo - This hook lowers an abstract call to a function into an /// actual call. - virtual std::pair<SDOperand, SDOperand> - LowerCallTo(SDOperand Chain, const Type *RetTy, bool RetSExt, bool RetZExt, - bool isVarArg, unsigned CC, bool isTailCall, SDOperand Callee, + virtual std::pair<SDValue, SDValue> + LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt, + bool isVarArg, unsigned CC, bool isTailCall, SDValue Callee, ArgListTy &Args, SelectionDAG &DAG); ConstraintType getConstraintType(const std::string &Constraint) const; @@ -97,7 +97,7 @@ namespace llvm { private: // Helpers for custom lowering. - void LowerVAARG(SDNode *N, SDOperand &Chain, SDOperand &DataPtr, + void LowerVAARG(SDNode *N, SDValue &Chain, SDValue &DataPtr, SelectionDAG &DAG); }; diff --git a/lib/Target/Alpha/AlphaInstrInfo.td b/lib/Target/Alpha/AlphaInstrInfo.td index 42bd8ed..5078893 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.td +++ b/lib/Target/Alpha/AlphaInstrInfo.td @@ -62,7 +62,7 @@ def LH16 : SDNodeXForm<imm, [{ //ldah part of constant (or more if too big) }]>; def iZAPX : SDNodeXForm<and, [{ // get imm to ZAPi ConstantSDNode *RHS = cast<ConstantSDNode>(N->getOperand(1)); - return getI64Imm(get_zapImm(SDOperand(), RHS->getValue())); + return getI64Imm(get_zapImm(SDValue(), RHS->getValue())); }]>; def nearP2X : SDNodeXForm<imm, [{ return getI64Imm(Log2_64(getNearPower2((uint64_t)N->getValue()))); diff --git a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp index 0e935ac..84a1bd8 100644 --- a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp +++ b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp @@ -151,7 +151,7 @@ namespace { } bool - isHighLow(const SDOperand &Op) + isHighLow(const SDValue &Op) { return (Op.getOpcode() == SPUISD::IndirectAddr && ((Op.getOperand(0).getOpcode() == SPUISD::Hi @@ -242,52 +242,52 @@ public: /// getI32Imm - Return a target constant with the specified value, of type /// i32. - inline SDOperand getI32Imm(uint32_t Imm) { + inline SDValue getI32Imm(uint32_t Imm) { return CurDAG->getTargetConstant(Imm, MVT::i32); } /// getI64Imm - Return a target constant with the specified value, of type /// i64. - inline SDOperand getI64Imm(uint64_t Imm) { + inline SDValue getI64Imm(uint64_t Imm) { return CurDAG->getTargetConstant(Imm, MVT::i64); } /// getSmallIPtrImm - Return a target constant of pointer type. - inline SDOperand getSmallIPtrImm(unsigned Imm) { + inline SDValue getSmallIPtrImm(unsigned Imm) { return CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy()); } /// Select - Convert the specified operand from a target-independent to a /// target-specific node if it hasn't already been changed. - SDNode *Select(SDOperand Op); + SDNode *Select(SDValue Op); //! Returns true if the address N is an A-form (local store) address - bool SelectAFormAddr(SDOperand Op, SDOperand N, SDOperand &Base, - SDOperand &Index); + bool SelectAFormAddr(SDValue Op, SDValue N, SDValue &Base, + SDValue &Index); //! D-form address predicate - bool SelectDFormAddr(SDOperand Op, SDOperand N, SDOperand &Base, - SDOperand &Index); + bool SelectDFormAddr(SDValue Op, SDValue N, SDValue &Base, + SDValue &Index); /// Alternate D-form address using i7 offset predicate - bool SelectDForm2Addr(SDOperand Op, SDOperand N, SDOperand &Disp, - SDOperand &Base); + bool SelectDForm2Addr(SDValue Op, SDValue N, SDValue &Disp, + SDValue &Base); /// D-form address selection workhorse - bool DFormAddressPredicate(SDOperand Op, SDOperand N, SDOperand &Disp, - SDOperand &Base, int minOffset, int maxOffset); + bool DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Disp, + SDValue &Base, int minOffset, int maxOffset); //! Address predicate if N can be expressed as an indexed [r+r] operation. - bool SelectXFormAddr(SDOperand Op, SDOperand N, SDOperand &Base, - SDOperand &Index); + bool SelectXFormAddr(SDValue Op, SDValue N, SDValue &Base, + SDValue &Index); /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for /// inline asm expressions. - virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op, + virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, - std::vector<SDOperand> &OutOps, + std::vector<SDValue> &OutOps, SelectionDAG &DAG) { - SDOperand Op0, Op1; + SDValue Op0, Op1; switch (ConstraintCode) { default: return true; case 'm': // memory @@ -358,11 +358,11 @@ SPUDAGToDAGISel::InstructionSelect(SelectionDAG &DAG) \arg Index The base address index */ bool -SPUDAGToDAGISel::SelectAFormAddr(SDOperand Op, SDOperand N, SDOperand &Base, - SDOperand &Index) { +SPUDAGToDAGISel::SelectAFormAddr(SDValue Op, SDValue N, SDValue &Base, + SDValue &Index) { // These match the addr256k operand type: MVT OffsVT = MVT::i16; - SDOperand Zero = CurDAG->getTargetConstant(0, OffsVT); + SDValue Zero = CurDAG->getTargetConstant(0, OffsVT); switch (N.getOpcode()) { case ISD::Constant: @@ -384,7 +384,7 @@ SPUDAGToDAGISel::SelectAFormAddr(SDOperand Op, SDOperand N, SDOperand &Base, // Just load from memory if there's only a single use of the location, // otherwise, this will get handled below with D-form offset addresses if (N.hasOneUse()) { - SDOperand Op0 = N.getOperand(0); + SDValue Op0 = N.getOperand(0); switch (Op0.getOpcode()) { case ISD::TargetConstantPool: case ISD::TargetJumpTable: @@ -410,8 +410,8 @@ SPUDAGToDAGISel::SelectAFormAddr(SDOperand Op, SDOperand N, SDOperand &Base, } bool -SPUDAGToDAGISel::SelectDForm2Addr(SDOperand Op, SDOperand N, SDOperand &Disp, - SDOperand &Base) { +SPUDAGToDAGISel::SelectDForm2Addr(SDValue Op, SDValue N, SDValue &Disp, + SDValue &Base) { const int minDForm2Offset = -(1 << 7); const int maxDForm2Offset = (1 << 7) - 1; return DFormAddressPredicate(Op, N, Disp, Base, minDForm2Offset, @@ -428,19 +428,19 @@ SPUDAGToDAGISel::SelectDForm2Addr(SDOperand Op, SDOperand N, SDOperand &Disp, displacement, [r+I10] (D-form address). \return true if \a N is a D-form address with \a Base and \a Index set - to non-empty SDOperand instances. + to non-empty SDValue instances. */ bool -SPUDAGToDAGISel::SelectDFormAddr(SDOperand Op, SDOperand N, SDOperand &Base, - SDOperand &Index) { +SPUDAGToDAGISel::SelectDFormAddr(SDValue Op, SDValue N, SDValue &Base, + SDValue &Index) { return DFormAddressPredicate(Op, N, Base, Index, SPUFrameInfo::minFrameOffset(), SPUFrameInfo::maxFrameOffset()); } bool -SPUDAGToDAGISel::DFormAddressPredicate(SDOperand Op, SDOperand N, SDOperand &Base, - SDOperand &Index, int minOffset, +SPUDAGToDAGISel::DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Base, + SDValue &Index, int minOffset, int maxOffset) { unsigned Opc = N.getOpcode(); MVT PtrTy = SPUtli.getPointerTy(); @@ -458,8 +458,8 @@ SPUDAGToDAGISel::DFormAddressPredicate(SDOperand Op, SDOperand N, SDOperand &Bas } } else if (Opc == ISD::ADD) { // Generated by getelementptr - const SDOperand Op0 = N.getOperand(0); - const SDOperand Op1 = N.getOperand(1); + const SDValue Op0 = N.getOperand(0); + const SDValue Op1 = N.getOperand(1); if ((Op0.getOpcode() == SPUISD::Hi && Op1.getOpcode() == SPUISD::Lo) || (Op1.getOpcode() == SPUISD::Hi && Op0.getOpcode() == SPUISD::Lo)) { @@ -511,8 +511,8 @@ SPUDAGToDAGISel::DFormAddressPredicate(SDOperand Op, SDOperand N, SDOperand &Bas } } else if (Opc == SPUISD::IndirectAddr) { // Indirect with constant offset -> D-Form address - const SDOperand Op0 = N.getOperand(0); - const SDOperand Op1 = N.getOperand(1); + const SDValue Op0 = N.getOperand(0); + const SDValue Op1 = N.getOperand(1); if (Op0.getOpcode() == SPUISD::Hi && Op1.getOpcode() == SPUISD::Lo) { @@ -522,7 +522,7 @@ SPUDAGToDAGISel::DFormAddressPredicate(SDOperand Op, SDOperand N, SDOperand &Bas return true; } else if (isa<ConstantSDNode>(Op0) || isa<ConstantSDNode>(Op1)) { int32_t offset = 0; - SDOperand idxOp; + SDValue idxOp; if (isa<ConstantSDNode>(Op1)) { ConstantSDNode *CN = cast<ConstantSDNode>(Op1); @@ -563,8 +563,8 @@ SPUDAGToDAGISel::DFormAddressPredicate(SDOperand Op, SDOperand N, SDOperand &Bas address. */ bool -SPUDAGToDAGISel::SelectXFormAddr(SDOperand Op, SDOperand N, SDOperand &Base, - SDOperand &Index) { +SPUDAGToDAGISel::SelectXFormAddr(SDValue Op, SDValue N, SDValue &Base, + SDValue &Index) { if (SelectAFormAddr(Op, N, Base, Index) || SelectDFormAddr(Op, N, Base, Index)) return false; @@ -579,13 +579,13 @@ SPUDAGToDAGISel::SelectXFormAddr(SDOperand Op, SDOperand N, SDOperand &Base, /*! */ SDNode * -SPUDAGToDAGISel::Select(SDOperand Op) { +SPUDAGToDAGISel::Select(SDValue Op) { SDNode *N = Op.Val; unsigned Opc = N->getOpcode(); int n_ops = -1; unsigned NewOpc; MVT OpVT = Op.getValueType(); - SDOperand Ops[8]; + SDValue Ops[8]; if (N->isMachineOpcode()) { return NULL; // Already selected. @@ -617,7 +617,7 @@ SPUDAGToDAGISel::Select(SDOperand Op) { } } else if (Opc == ISD::ZERO_EXTEND) { // (zero_extend:i16 (and:i8 <arg>, <const>)) - const SDOperand &Op1 = N->getOperand(0); + const SDValue &Op1 = N->getOperand(0); if (Op.getValueType() == MVT::i16 && Op1.getValueType() == MVT::i8) { if (Op1.getOpcode() == ISD::AND) { @@ -634,8 +634,8 @@ SPUDAGToDAGISel::Select(SDOperand Op) { } else if (Opc == SPUISD::LDRESULT) { // Custom select instructions for LDRESULT MVT VT = N->getValueType(0); - SDOperand Arg = N->getOperand(0); - SDOperand Chain = N->getOperand(1); + SDValue Arg = N->getOperand(0); + SDValue Chain = N->getOperand(1); SDNode *Result; const valtype_map_s *vtm = getValueTypeMapEntry(VT); @@ -649,7 +649,7 @@ SPUDAGToDAGISel::Select(SDOperand Op) { AddToISelQueue(Arg); Opc = vtm->ldresult_ins; if (vtm->ldresult_imm) { - SDOperand Zero = CurDAG->getTargetConstant(0, VT); + SDValue Zero = CurDAG->getTargetConstant(0, VT); AddToISelQueue(Zero); Result = CurDAG->getTargetNode(Opc, VT, MVT::Other, Arg, Zero, Chain); @@ -657,16 +657,16 @@ SPUDAGToDAGISel::Select(SDOperand Op) { Result = CurDAG->getTargetNode(Opc, MVT::Other, Arg, Arg, Chain); } - Chain = SDOperand(Result, 1); + Chain = SDValue(Result, 1); AddToISelQueue(Chain); return Result; } else if (Opc == SPUISD::IndirectAddr) { - SDOperand Op0 = Op.getOperand(0); + SDValue Op0 = Op.getOperand(0); if (Op0.getOpcode() == SPUISD::LDRESULT) { /* || Op0.getOpcode() == SPUISD::AFormAddr) */ // (IndirectAddr (LDRESULT, imm)) - SDOperand Op1 = Op.getOperand(1); + SDValue Op1 = Op.getOperand(1); MVT VT = Op.getValueType(); DEBUG(cerr << "CellSPU: IndirectAddr(LDRESULT, imm):\nOp0 = "); diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp index 607d0dc..2fd7251 100644 --- a/lib/Target/CellSPU/SPUISelLowering.cpp +++ b/lib/Target/CellSPU/SPUISelLowering.cpp @@ -85,7 +85,7 @@ namespace { address, external symbol, constant pool) or an A-form address. */ - bool isMemoryOperand(const SDOperand &Op) + bool isMemoryOperand(const SDValue &Op) { const unsigned Opc = Op.getOpcode(); return (Opc == ISD::GlobalAddress @@ -102,7 +102,7 @@ namespace { } //! Predicate that returns true if the operand is an indirect target - bool isIndirectOperand(const SDOperand &Op) + bool isIndirectOperand(const SDValue &Op) { const unsigned Opc = Op.getOpcode(); return (Opc == ISD::Register @@ -453,7 +453,7 @@ SPUTargetLowering::getTargetNodeName(unsigned Opcode) const return ((i != node_names.end()) ? i->second : 0); } -MVT SPUTargetLowering::getSetCCResultType(const SDOperand &Op) const { +MVT SPUTargetLowering::getSetCCResultType(const SDValue &Op) const { MVT VT = Op.getValueType(); if (VT.isInteger()) return VT; @@ -491,19 +491,19 @@ MVT SPUTargetLowering::getSetCCResultType(const SDOperand &Op) const { Both load and store lowering load a block of data aligned on a 16-byte boundary. This is the common aligned load code shared between both. */ -static SDOperand -AlignedLoad(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST, +static SDValue +AlignedLoad(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST, LSBaseSDNode *LSN, unsigned &alignment, int &alignOffs, int &prefSlotOffs, MVT &VT, bool &was16aligned) { MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); const valtype_map_s *vtm = getValueTypeMapEntry(VT); - SDOperand basePtr = LSN->getBasePtr(); - SDOperand chain = LSN->getChain(); + SDValue basePtr = LSN->getBasePtr(); + SDValue chain = LSN->getChain(); if (basePtr.getOpcode() == ISD::ADD) { - SDOperand Op1 = basePtr.Val->getOperand(1); + SDValue Op1 = basePtr.Val->getOperand(1); if (Op1.getOpcode() == ISD::Constant || Op1.getOpcode() == ISD::TargetConstant) { const ConstantSDNode *CN = cast<ConstantSDNode>(basePtr.getOperand(1)); @@ -518,7 +518,7 @@ AlignedLoad(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST, // Loading from memory, can we adjust alignment? if (basePtr.getOpcode() == SPUISD::AFormAddr) { - SDOperand APtr = basePtr.getOperand(0); + SDValue APtr = basePtr.getOperand(0); if (APtr.getOpcode() == ISD::TargetGlobalAddress) { GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(APtr); alignment = GSDN->getGlobal()->getAlignment(); @@ -574,21 +574,21 @@ AlignedLoad(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST, All CellSPU loads and stores are aligned to 16-byte boundaries, so for elements within a 16-byte block, we have to rotate to extract the requested element. */ -static SDOperand -LowerLOAD(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) { +static SDValue +LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { LoadSDNode *LN = cast<LoadSDNode>(Op); - SDOperand the_chain = LN->getChain(); + SDValue the_chain = LN->getChain(); MVT VT = LN->getMemoryVT(); MVT OpVT = Op.Val->getValueType(0); ISD::LoadExtType ExtType = LN->getExtensionType(); unsigned alignment = LN->getAlignment(); - SDOperand Ops[8]; + SDValue Ops[8]; switch (LN->getAddressingMode()) { case ISD::UNINDEXED: { int offset, rotamt; bool was16aligned; - SDOperand result = + SDValue result = AlignedLoad(Op, DAG, ST, LN,alignment, offset, rotamt, VT, was16aligned); if (result.Val == 0) @@ -652,7 +652,7 @@ LowerLOAD(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) { } SDVTList retvts = DAG.getVTList(OpVT, MVT::Other); - SDOperand retops[2] = { + SDValue retops[2] = { result, the_chain }; @@ -673,7 +673,7 @@ LowerLOAD(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) { /*NOTREACHED*/ } - return SDOperand(); + return SDValue(); } /// Custom lower stores for CellSPU @@ -682,10 +682,10 @@ LowerLOAD(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) { within a 16-byte block, we have to generate a shuffle to insert the requested element into its place, then store the resulting block. */ -static SDOperand -LowerSTORE(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) { +static SDValue +LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { StoreSDNode *SN = cast<StoreSDNode>(Op); - SDOperand Value = SN->getValue(); + SDValue Value = SN->getValue(); MVT VT = Value.getValueType(); MVT StVT = (!SN->isTruncatingStore() ? VT : SN->getMemoryVT()); MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); @@ -704,7 +704,7 @@ LowerSTORE(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) { stVecVT = MVT::getVectorVT(StVT, (128 / StVT.getSizeInBits())); vecVT = MVT::getVectorVT(VT, (128 / VT.getSizeInBits())); - SDOperand alignLoadVec = + SDValue alignLoadVec = AlignedLoad(Op, DAG, ST, SN, alignment, chunk_offset, slot_offset, VT, was16aligned); @@ -712,10 +712,10 @@ LowerSTORE(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) { return alignLoadVec; LoadSDNode *LN = cast<LoadSDNode>(alignLoadVec); - SDOperand basePtr = LN->getBasePtr(); - SDOperand the_chain = alignLoadVec.getValue(1); - SDOperand theValue = SN->getValue(); - SDOperand result; + SDValue basePtr = LN->getBasePtr(); + SDValue the_chain = alignLoadVec.getValue(1); + SDValue theValue = SN->getValue(); + SDValue result; if (StVT != VT && (theValue.getOpcode() == ISD::AssertZext @@ -727,9 +727,9 @@ LowerSTORE(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) { chunk_offset &= 0xf; - SDOperand insertEltOffs = DAG.getConstant(chunk_offset, PtrVT); - SDOperand insertEltPtr; - SDOperand insertEltOp; + SDValue insertEltOffs = DAG.getConstant(chunk_offset, PtrVT); + SDValue insertEltPtr; + SDValue insertEltOp; // If the base pointer is already a D-form address, then just create // a new D-form address with a slot offset and the orignal base pointer. @@ -772,73 +772,73 @@ LowerSTORE(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) { /*NOTREACHED*/ } - return SDOperand(); + return SDValue(); } /// Generate the address of a constant pool entry. -static SDOperand -LowerConstantPool(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) { +static SDValue +LowerConstantPool(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { MVT PtrVT = Op.getValueType(); ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); Constant *C = CP->getConstVal(); - SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment()); - SDOperand Zero = DAG.getConstant(0, PtrVT); + SDValue CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment()); + SDValue Zero = DAG.getConstant(0, PtrVT); const TargetMachine &TM = DAG.getTarget(); if (TM.getRelocationModel() == Reloc::Static) { if (!ST->usingLargeMem()) { - // Just return the SDOperand with the constant pool address in it. + // Just return the SDValue with the constant pool address in it. return DAG.getNode(SPUISD::AFormAddr, PtrVT, CPI, Zero); } else { - SDOperand Hi = DAG.getNode(SPUISD::Hi, PtrVT, CPI, Zero); - SDOperand Lo = DAG.getNode(SPUISD::Lo, PtrVT, CPI, Zero); + SDValue Hi = DAG.getNode(SPUISD::Hi, PtrVT, CPI, Zero); + SDValue Lo = DAG.getNode(SPUISD::Lo, PtrVT, CPI, Zero); return DAG.getNode(SPUISD::IndirectAddr, PtrVT, Hi, Lo); } } assert(0 && "LowerConstantPool: Relocation model other than static not supported."); - return SDOperand(); + return SDValue(); } -static SDOperand -LowerJumpTable(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) { +static SDValue +LowerJumpTable(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { MVT PtrVT = Op.getValueType(); JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); - SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); - SDOperand Zero = DAG.getConstant(0, PtrVT); + SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); + SDValue Zero = DAG.getConstant(0, PtrVT); const TargetMachine &TM = DAG.getTarget(); if (TM.getRelocationModel() == Reloc::Static) { if (!ST->usingLargeMem()) { return DAG.getNode(SPUISD::AFormAddr, PtrVT, JTI, Zero); } else { - SDOperand Hi = DAG.getNode(SPUISD::Hi, PtrVT, JTI, Zero); - SDOperand Lo = DAG.getNode(SPUISD::Lo, PtrVT, JTI, Zero); + SDValue Hi = DAG.getNode(SPUISD::Hi, PtrVT, JTI, Zero); + SDValue Lo = DAG.getNode(SPUISD::Lo, PtrVT, JTI, Zero); return DAG.getNode(SPUISD::IndirectAddr, PtrVT, Hi, Lo); } } assert(0 && "LowerJumpTable: Relocation model other than static not supported."); - return SDOperand(); + return SDValue(); } -static SDOperand -LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) { +static SDValue +LowerGlobalAddress(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { MVT PtrVT = Op.getValueType(); GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); GlobalValue *GV = GSDN->getGlobal(); - SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset()); + SDValue GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset()); const TargetMachine &TM = DAG.getTarget(); - SDOperand Zero = DAG.getConstant(0, PtrVT); + SDValue Zero = DAG.getConstant(0, PtrVT); if (TM.getRelocationModel() == Reloc::Static) { if (!ST->usingLargeMem()) { return DAG.getNode(SPUISD::AFormAddr, PtrVT, GA, Zero); } else { - SDOperand Hi = DAG.getNode(SPUISD::Hi, PtrVT, GA, Zero); - SDOperand Lo = DAG.getNode(SPUISD::Lo, PtrVT, GA, Zero); + SDValue Hi = DAG.getNode(SPUISD::Hi, PtrVT, GA, Zero); + SDValue Lo = DAG.getNode(SPUISD::Lo, PtrVT, GA, Zero); return DAG.getNode(SPUISD::IndirectAddr, PtrVT, Hi, Lo); } } else { @@ -848,7 +848,7 @@ LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) { /*NOTREACHED*/ } - return SDOperand(); + return SDValue(); } //! Custom lower i64 integer constants @@ -856,13 +856,13 @@ LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) { This code inserts all of the necessary juggling that needs to occur to load a 64-bit constant into a register. */ -static SDOperand -LowerConstant(SDOperand Op, SelectionDAG &DAG) { +static SDValue +LowerConstant(SDValue Op, SelectionDAG &DAG) { MVT VT = Op.getValueType(); ConstantSDNode *CN = cast<ConstantSDNode>(Op.Val); if (VT == MVT::i64) { - SDOperand T = DAG.getConstant(CN->getValue(), MVT::i64); + SDValue T = DAG.getConstant(CN->getValue(), MVT::i64); return DAG.getNode(SPUISD::EXTRACT_ELT0, VT, DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i64, T, T)); } else { @@ -873,12 +873,12 @@ LowerConstant(SDOperand Op, SelectionDAG &DAG) { /*NOTREACHED*/ } - return SDOperand(); + return SDValue(); } //! Custom lower double precision floating point constants -static SDOperand -LowerConstantFP(SDOperand Op, SelectionDAG &DAG) { +static SDValue +LowerConstantFP(SDValue Op, SelectionDAG &DAG) { MVT VT = Op.getValueType(); ConstantFPSDNode *FP = cast<ConstantFPSDNode>(Op.Val); @@ -891,14 +891,14 @@ LowerConstantFP(SDOperand Op, SelectionDAG &DAG) { LowerConstant(DAG.getConstant(dbits, MVT::i64), DAG)); } - return SDOperand(); + return SDValue(); } //! Lower MVT::i1, MVT::i8 brcond to a promoted type (MVT::i32, MVT::i16) -static SDOperand -LowerBRCOND(SDOperand Op, SelectionDAG &DAG) +static SDValue +LowerBRCOND(SDValue Op, SelectionDAG &DAG) { - SDOperand Cond = Op.getOperand(1); + SDValue Cond = Op.getOperand(1); MVT CondVT = Cond.getValueType(); MVT CondNVT; @@ -909,17 +909,17 @@ LowerBRCOND(SDOperand Op, SelectionDAG &DAG) DAG.getNode(ISD::ZERO_EXTEND, CondNVT, Op.getOperand(1)), Op.getOperand(2)); } else - return SDOperand(); // Unchanged + return SDValue(); // Unchanged } -static SDOperand -LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, int &VarArgsFrameIndex) +static SDValue +LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG, int &VarArgsFrameIndex) { MachineFunction &MF = DAG.getMachineFunction(); MachineFrameInfo *MFI = MF.getFrameInfo(); MachineRegisterInfo &RegInfo = MF.getRegInfo(); - SmallVector<SDOperand, 8> ArgValues; - SDOperand Root = Op.getOperand(0); + SmallVector<SDValue, 8> ArgValues; + SDValue Root = Op.getOperand(0); bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; const unsigned *ArgRegs = SPURegisterInfo::getArgRegs(); @@ -933,7 +933,7 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, int &VarArgsFrameIndex) // Add DAG nodes to load the arguments or copy them out of registers. for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) { - SDOperand ArgVal; + SDValue ArgVal; bool needsLoad = false; MVT ObjectVT = Op.getValue(ArgNo).getValueType(); unsigned ObjSize = ObjectVT.getSizeInBits()/8; @@ -1026,7 +1026,7 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, int &VarArgsFrameIndex) // that we ran out of physical registers of the appropriate type if (needsLoad) { int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); - SDOperand FIN = DAG.getFrameIndex(FI, PtrVT); + SDValue FIN = DAG.getFrameIndex(FI, PtrVT); ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0); ArgOffset += StackSlotSize; } @@ -1039,19 +1039,19 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, int &VarArgsFrameIndex) if (isVarArg) { VarArgsFrameIndex = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8, ArgOffset); - SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); + SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); // If this function is vararg, store any remaining integer argument regs to // their spots on the stack so that they may be loaded by deferencing the // result of va_next. - SmallVector<SDOperand, 8> MemOps; + SmallVector<SDValue, 8> MemOps; for (; ArgRegIdx != NumArgRegs; ++ArgRegIdx) { unsigned VReg = RegInfo.createVirtualRegister(&SPU::GPRCRegClass); RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg); - SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT); - SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); + SDValue Val = DAG.getCopyFromReg(Root, VReg, PtrVT); + SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); MemOps.push_back(Store); // Increment the address by four for the next argument to store - SDOperand PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); + SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); } if (!MemOps.empty()) @@ -1067,7 +1067,7 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, int &VarArgsFrameIndex) /// isLSAAddress - Return the immediate to use if the specified /// value is representable as a LSA address. -static SDNode *isLSAAddress(SDOperand Op, SelectionDAG &DAG) { +static SDNode *isLSAAddress(SDValue Op, SelectionDAG &DAG) { ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); if (!C) return 0; @@ -1080,14 +1080,14 @@ static SDNode *isLSAAddress(SDOperand Op, SelectionDAG &DAG) { } static -SDOperand -LowerCALL(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) { - SDOperand Chain = Op.getOperand(0); +SDValue +LowerCALL(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { + SDValue Chain = Op.getOperand(0); #if 0 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0; #endif - SDOperand Callee = Op.getOperand(4); + SDValue Callee = Op.getOperand(4); unsigned NumOps = (Op.getNumOperands() - 5) / 2; unsigned StackSlotSize = SPUFrameInfo::stackSlotSize(); const unsigned *ArgRegs = SPURegisterInfo::getArgRegs(); @@ -1104,7 +1104,7 @@ LowerCALL(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) { // Set up a copy of the stack pointer for use loading and storing any // arguments that may not fit in the registers available for argument // passing. - SDOperand StackPtr = DAG.getRegister(SPU::R1, MVT::i32); + SDValue StackPtr = DAG.getRegister(SPU::R1, MVT::i32); // Figure out which arguments are going to go in registers, and which in // memory. @@ -1112,16 +1112,16 @@ LowerCALL(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) { unsigned ArgRegIdx = 0; // Keep track of registers passing arguments - std::vector<std::pair<unsigned, SDOperand> > RegsToPass; + std::vector<std::pair<unsigned, SDValue> > RegsToPass; // And the arguments passed on the stack - SmallVector<SDOperand, 8> MemOpChains; + SmallVector<SDValue, 8> MemOpChains; for (unsigned i = 0; i != NumOps; ++i) { - SDOperand Arg = Op.getOperand(5+2*i); + SDValue Arg = Op.getOperand(5+2*i); // PtrOff will be used to store the current argument to the stack if a // register cannot be found for it. - SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); + SDValue PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff); switch (Arg.getValueType().getSimpleVT()) { @@ -1171,14 +1171,14 @@ LowerCALL(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) { // Build a sequence of copy-to-reg nodes chained together with token chain // and flag operands which copy the outgoing args into the appropriate regs. - SDOperand InFlag; + SDValue InFlag; for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, InFlag); InFlag = Chain.getValue(1); } - SmallVector<SDOperand, 8> Ops; + SmallVector<SDValue, 8> Ops; unsigned CallOpc = SPUISD::CALL; // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every @@ -1187,8 +1187,8 @@ LowerCALL(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) { if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { GlobalValue *GV = G->getGlobal(); MVT CalleeVT = Callee.getValueType(); - SDOperand Zero = DAG.getConstant(0, PtrVT); - SDOperand GA = DAG.getTargetGlobalAddress(GV, CalleeVT); + SDValue Zero = DAG.getConstant(0, PtrVT); + SDValue GA = DAG.getTargetGlobalAddress(GV, CalleeVT); if (!ST->usingLargeMem()) { // Turn calls to targets that are defined (i.e., have bodies) into BRSL @@ -1214,7 +1214,7 @@ LowerCALL(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) { else if (SDNode *Dest = isLSAAddress(Callee, DAG)) { // If this is an absolute destination address that appears to be a legal // local store address, use the munged value. - Callee = SDOperand(Dest, 0); + Callee = SDValue(Dest, 0); } Ops.push_back(Chain); @@ -1240,7 +1240,7 @@ LowerCALL(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) { if (Op.Val->getValueType(0) != MVT::Other) InFlag = Chain.getValue(1); - SDOperand ResultVals[3]; + SDValue ResultVals[3]; unsigned NumResults = 0; // If the call has results, copy the values out of the ret val registers. @@ -1291,12 +1291,12 @@ LowerCALL(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) { // Otherwise, merge everything together with a MERGE_VALUES node. ResultVals[NumResults++] = Chain; - SDOperand Res = DAG.getMergeValues(ResultVals, NumResults); + SDValue Res = DAG.getMergeValues(ResultVals, NumResults); return Res.getValue(Op.ResNo); } -static SDOperand -LowerRET(SDOperand Op, SelectionDAG &DAG, TargetMachine &TM) { +static SDValue +LowerRET(SDValue Op, SelectionDAG &DAG, TargetMachine &TM) { SmallVector<CCValAssign, 16> RVLocs; unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); @@ -1310,8 +1310,8 @@ LowerRET(SDOperand Op, SelectionDAG &DAG, TargetMachine &TM) { DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); } - SDOperand Chain = Op.getOperand(0); - SDOperand Flag; + SDValue Chain = Op.getOperand(0); + SDValue Flag; // Copy the result values into the output registers. for (unsigned i = 0; i != RVLocs.size(); ++i) { @@ -1334,7 +1334,7 @@ LowerRET(SDOperand Op, SelectionDAG &DAG, TargetMachine &TM) { static ConstantSDNode * getVecImm(SDNode *N) { - SDOperand OpVal(0, 0); + SDValue OpVal(0, 0); // Check to see if this buildvec has a single non-undef value in its elements. for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { @@ -1357,7 +1357,7 @@ getVecImm(SDNode *N) { /// get_vec_i18imm - Test if this vector is a vector filled with the same value /// and the value fits into an unsigned 18-bit constant, and if so, return the /// constant -SDOperand SPU::get_vec_u18imm(SDNode *N, SelectionDAG &DAG, +SDValue SPU::get_vec_u18imm(SDNode *N, SelectionDAG &DAG, MVT ValueType) { if (ConstantSDNode *CN = getVecImm(N)) { uint64_t Value = CN->getValue(); @@ -1366,20 +1366,20 @@ SDOperand SPU::get_vec_u18imm(SDNode *N, SelectionDAG &DAG, uint32_t upper = uint32_t(UValue >> 32); uint32_t lower = uint32_t(UValue); if (upper != lower) - return SDOperand(); + return SDValue(); Value = Value >> 32; } if (Value <= 0x3ffff) return DAG.getConstant(Value, ValueType); } - return SDOperand(); + return SDValue(); } /// get_vec_i16imm - Test if this vector is a vector filled with the same value /// and the value fits into a signed 16-bit constant, and if so, return the /// constant -SDOperand SPU::get_vec_i16imm(SDNode *N, SelectionDAG &DAG, +SDValue SPU::get_vec_i16imm(SDNode *N, SelectionDAG &DAG, MVT ValueType) { if (ConstantSDNode *CN = getVecImm(N)) { int64_t Value = CN->getSignExtended(); @@ -1388,7 +1388,7 @@ SDOperand SPU::get_vec_i16imm(SDNode *N, SelectionDAG &DAG, uint32_t upper = uint32_t(UValue >> 32); uint32_t lower = uint32_t(UValue); if (upper != lower) - return SDOperand(); + return SDValue(); Value = Value >> 32; } if (Value >= -(1 << 15) && Value <= ((1 << 15) - 1)) { @@ -1396,13 +1396,13 @@ SDOperand SPU::get_vec_i16imm(SDNode *N, SelectionDAG &DAG, } } - return SDOperand(); + return SDValue(); } /// get_vec_i10imm - Test if this vector is a vector filled with the same value /// and the value fits into a signed 10-bit constant, and if so, return the /// constant -SDOperand SPU::get_vec_i10imm(SDNode *N, SelectionDAG &DAG, +SDValue SPU::get_vec_i10imm(SDNode *N, SelectionDAG &DAG, MVT ValueType) { if (ConstantSDNode *CN = getVecImm(N)) { int64_t Value = CN->getSignExtended(); @@ -1411,14 +1411,14 @@ SDOperand SPU::get_vec_i10imm(SDNode *N, SelectionDAG &DAG, uint32_t upper = uint32_t(UValue >> 32); uint32_t lower = uint32_t(UValue); if (upper != lower) - return SDOperand(); + return SDValue(); Value = Value >> 32; } if (isS10Constant(Value)) return DAG.getConstant(Value, ValueType); } - return SDOperand(); + return SDValue(); } /// get_vec_i8imm - Test if this vector is a vector filled with the same value @@ -1428,7 +1428,7 @@ SDOperand SPU::get_vec_i10imm(SDNode *N, SelectionDAG &DAG, /// @note: The incoming vector is v16i8 because that's the only way we can load /// constant vectors. Thus, we test to see if the upper and lower bytes are the /// same value. -SDOperand SPU::get_vec_i8imm(SDNode *N, SelectionDAG &DAG, +SDValue SPU::get_vec_i8imm(SDNode *N, SelectionDAG &DAG, MVT ValueType) { if (ConstantSDNode *CN = getVecImm(N)) { int Value = (int) CN->getValue(); @@ -1441,13 +1441,13 @@ SDOperand SPU::get_vec_i8imm(SDNode *N, SelectionDAG &DAG, return DAG.getConstant(Value, ValueType); } - return SDOperand(); + return SDValue(); } /// get_ILHUvec_imm - Test if this vector is a vector filled with the same value /// and the value fits into a signed 16-bit constant, and if so, return the /// constant -SDOperand SPU::get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG, +SDValue SPU::get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG, MVT ValueType) { if (ConstantSDNode *CN = getVecImm(N)) { uint64_t Value = CN->getValue(); @@ -1457,25 +1457,25 @@ SDOperand SPU::get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG, return DAG.getConstant(Value >> 16, ValueType); } - return SDOperand(); + return SDValue(); } /// get_v4i32_imm - Catch-all for general 32-bit constant vectors -SDOperand SPU::get_v4i32_imm(SDNode *N, SelectionDAG &DAG) { +SDValue SPU::get_v4i32_imm(SDNode *N, SelectionDAG &DAG) { if (ConstantSDNode *CN = getVecImm(N)) { return DAG.getConstant((unsigned) CN->getValue(), MVT::i32); } - return SDOperand(); + return SDValue(); } /// get_v4i32_imm - Catch-all for general 64-bit constant vectors -SDOperand SPU::get_v2i64_imm(SDNode *N, SelectionDAG &DAG) { +SDValue SPU::get_v2i64_imm(SDNode *N, SelectionDAG &DAG) { if (ConstantSDNode *CN = getVecImm(N)) { return DAG.getConstant((unsigned) CN->getValue(), MVT::i64); } - return SDOperand(); + return SDValue(); } // If this is a vector of constants or undefs, get the bits. A bit in @@ -1490,7 +1490,7 @@ static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2], unsigned EltBitSize = BV->getOperand(0).getValueType().getSizeInBits(); for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { - SDOperand OpVal = BV->getOperand(i); + SDValue OpVal = BV->getOperand(i); unsigned PartNo = i >= e/2; // In the upper 128 bits? unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t. @@ -1589,7 +1589,7 @@ static bool isConstantSplat(const uint64_t Bits128[2], // selects to a single instruction, return Op. Otherwise, if we can codegen // this case more efficiently than a constant pool load, lower it to the // sequence of ops that should be used. -static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { +static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { MVT VT = Op.getValueType(); // If this is a vector of constants or undefs, get the bits. A bit in // UndefBits is set if the corresponding element of the vector is an @@ -1603,7 +1603,7 @@ static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { || !isConstantSplat(VectorBits, UndefBits, VT.getVectorElementType().getSizeInBits(), SplatBits, SplatUndef, SplatSize)) - return SDOperand(); // Not a constant vector, not a splat. + return SDValue(); // Not a constant vector, not a splat. switch (VT.getSimpleVT()) { default: @@ -1612,7 +1612,7 @@ static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { assert(SplatSize == 4 && "LowerBUILD_VECTOR: Unexpected floating point vector element."); // NOTE: pretend the constant is an integer. LLVM won't load FP constants - SDOperand T = DAG.getConstant(Value32, MVT::i32); + SDValue T = DAG.getConstant(Value32, MVT::i32); return DAG.getNode(ISD::BIT_CONVERT, MVT::v4f32, DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, T, T, T, T)); break; @@ -1622,7 +1622,7 @@ static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { assert(SplatSize == 8 && "LowerBUILD_VECTOR: 64-bit float vector element: unexpected size."); // NOTE: pretend the constant is an integer. LLVM won't load FP constants - SDOperand T = DAG.getConstant(f64val, MVT::i64); + SDValue T = DAG.getConstant(f64val, MVT::i64); return DAG.getNode(ISD::BIT_CONVERT, MVT::v2f64, DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i64, T, T)); break; @@ -1630,7 +1630,7 @@ static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { case MVT::v16i8: { // 8-bit constants have to be expanded to 16-bits unsigned short Value16 = SplatBits | (SplatBits << 8); - SDOperand Ops[8]; + SDValue Ops[8]; for (int i = 0; i < 8; ++i) Ops[i] = DAG.getConstant(Value16, MVT::i16); return DAG.getNode(ISD::BIT_CONVERT, VT, @@ -1642,14 +1642,14 @@ static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { Value16 = (unsigned short) (SplatBits & 0xffff); else Value16 = (unsigned short) (SplatBits | (SplatBits << 8)); - SDOperand T = DAG.getConstant(Value16, VT.getVectorElementType()); - SDOperand Ops[8]; + SDValue T = DAG.getConstant(Value16, VT.getVectorElementType()); + SDValue Ops[8]; for (int i = 0; i < 8; ++i) Ops[i] = T; return DAG.getNode(ISD::BUILD_VECTOR, VT, Ops, 8); } case MVT::v4i32: { unsigned int Value = SplatBits; - SDOperand T = DAG.getConstant(Value, VT.getVectorElementType()); + SDValue T = DAG.getConstant(Value, VT.getVectorElementType()); return DAG.getNode(ISD::BUILD_VECTOR, VT, T, T, T, T); } case MVT::v2i64: { @@ -1659,13 +1659,13 @@ static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { if (upper == lower) { // Magic constant that can be matched by IL, ILA, et. al. - SDOperand Val = DAG.getTargetConstant(val, MVT::i64); + SDValue Val = DAG.getTargetConstant(val, MVT::i64); return DAG.getNode(ISD::BUILD_VECTOR, VT, Val, Val); } else { - SDOperand LO32; - SDOperand HI32; - SmallVector<SDOperand, 16> ShufBytes; - SDOperand Result; + SDValue LO32; + SDValue HI32; + SmallVector<SDValue, 16> ShufBytes; + SDValue Result; bool upper_special, lower_special; // NOTE: This code creates common-case shuffle masks that can be easily @@ -1678,7 +1678,7 @@ static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { // Create lower vector if not a special pattern if (!lower_special) { - SDOperand LO32C = DAG.getConstant(lower, MVT::i32); + SDValue LO32C = DAG.getConstant(lower, MVT::i32); LO32 = DAG.getNode(ISD::BIT_CONVERT, VT, DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, LO32C, LO32C, LO32C, LO32C)); @@ -1686,7 +1686,7 @@ static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { // Create upper vector if not a special pattern if (!upper_special) { - SDOperand HI32C = DAG.getConstant(upper, MVT::i32); + SDValue HI32C = DAG.getConstant(upper, MVT::i32); HI32 = DAG.getNode(ISD::BIT_CONVERT, VT, DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, HI32C, HI32C, HI32C, HI32C)); @@ -1701,7 +1701,7 @@ static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { if (lower_special && upper_special) { // Unhappy situation... both upper and lower are special, so punt with // a target constant: - SDOperand Zero = DAG.getConstant(0, MVT::i32); + SDValue Zero = DAG.getConstant(0, MVT::i32); HI32 = LO32 = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Zero, Zero, Zero, Zero); } @@ -1709,7 +1709,7 @@ static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { for (int i = 0; i < 4; ++i) { uint64_t val = 0; for (int j = 0; j < 4; ++j) { - SDOperand V; + SDValue V; bool process_upper, process_lower; val <<= 8; process_upper = (upper_special && (i & 1) == 0); @@ -1739,7 +1739,7 @@ static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { } } - return SDOperand(); + return SDValue(); } /// LowerVECTOR_SHUFFLE - Lower a vector shuffle (V1, V2, V3) to something on @@ -1755,10 +1755,10 @@ static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { /// element move from V2 into V1. /// \note /// SPUISD::SHUFB is eventually selected as Cell's <i>shufb</i> instructions. -static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) { - SDOperand V1 = Op.getOperand(0); - SDOperand V2 = Op.getOperand(1); - SDOperand PermMask = Op.getOperand(2); +static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { + SDValue V1 = Op.getOperand(0); + SDValue V2 = Op.getOperand(1); + SDValue PermMask = Op.getOperand(2); if (V2.getOpcode() == ISD::UNDEF) V2 = V1; @@ -1806,10 +1806,10 @@ static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) { unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32CRegClass); MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); // Initialize temporary register to 0 - SDOperand InitTempReg = + SDValue InitTempReg = DAG.getCopyToReg(DAG.getEntryNode(), VReg, DAG.getConstant(0, PtrVT)); // Copy register's contents as index in INSERT_MASK: - SDOperand ShufMaskOp = + SDValue ShufMaskOp = DAG.getNode(SPUISD::INSERT_MASK, V1.getValueType(), DAG.getTargetConstant(V2Elt, MVT::i32), DAG.getCopyFromReg(InitTempReg, VReg, PtrVT)); @@ -1819,7 +1819,7 @@ static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) { // Convert the SHUFFLE_VECTOR mask's input element units to the actual bytes. unsigned BytesPerElement = EltVT.getSizeInBits()/8; - SmallVector<SDOperand, 16> ResultMask; + SmallVector<SDValue, 16> ResultMask; for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) { unsigned SrcElt; if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF) @@ -1833,21 +1833,21 @@ static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) { } } - SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, + SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, &ResultMask[0], ResultMask.size()); return DAG.getNode(SPUISD::SHUFB, V1.getValueType(), V1, V2, VPermMask); } } -static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) { - SDOperand Op0 = Op.getOperand(0); // Op0 = the scalar +static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) { + SDValue Op0 = Op.getOperand(0); // Op0 = the scalar if (Op0.Val->getOpcode() == ISD::Constant) { // For a constant, build the appropriate constant vector, which will // eventually simplify to a vector register load. ConstantSDNode *CN = cast<ConstantSDNode>(Op0.Val); - SmallVector<SDOperand, 16> ConstVecValues; + SmallVector<SDValue, 16> ConstVecValues; MVT VT; size_t n_copies; @@ -1863,7 +1863,7 @@ static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) { case MVT::v2f64: n_copies = 2; VT = MVT::f64; break; } - SDOperand CValue = DAG.getConstant(CN->getValue(), VT); + SDValue CValue = DAG.getConstant(CN->getValue(), VT); for (size_t j = 0; j < n_copies; ++j) ConstVecValues.push_back(CValue); @@ -1883,10 +1883,10 @@ static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) { } } - return SDOperand(); + return SDValue(); } -static SDOperand LowerVectorMUL(SDOperand Op, SelectionDAG &DAG) { +static SDValue LowerVectorMUL(SDValue Op, SelectionDAG &DAG) { switch (Op.getValueType().getSimpleVT()) { default: cerr << "CellSPU: Unknown vector multiplication, got " @@ -1896,12 +1896,12 @@ static SDOperand LowerVectorMUL(SDOperand Op, SelectionDAG &DAG) { /*NOTREACHED*/ case MVT::v4i32: { - SDOperand rA = Op.getOperand(0); - SDOperand rB = Op.getOperand(1); - SDOperand HiProd1 = DAG.getNode(SPUISD::MPYH, MVT::v4i32, rA, rB); - SDOperand HiProd2 = DAG.getNode(SPUISD::MPYH, MVT::v4i32, rB, rA); - SDOperand LoProd = DAG.getNode(SPUISD::MPYU, MVT::v4i32, rA, rB); - SDOperand Residual1 = DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd1); + SDValue rA = Op.getOperand(0); + SDValue rB = Op.getOperand(1); + SDValue HiProd1 = DAG.getNode(SPUISD::MPYH, MVT::v4i32, rA, rB); + SDValue HiProd2 = DAG.getNode(SPUISD::MPYH, MVT::v4i32, rB, rA); + SDValue LoProd = DAG.getNode(SPUISD::MPYU, MVT::v4i32, rA, rB); + SDValue Residual1 = DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd1); return DAG.getNode(ISD::ADD, MVT::v4i32, Residual1, HiProd2); break; @@ -1918,22 +1918,22 @@ static SDOperand LowerVectorMUL(SDOperand Op, SelectionDAG &DAG) { case MVT::v8i16: { MachineFunction &MF = DAG.getMachineFunction(); MachineRegisterInfo &RegInfo = MF.getRegInfo(); - SDOperand Chain = Op.getOperand(0); - SDOperand rA = Op.getOperand(0); - SDOperand rB = Op.getOperand(1); + SDValue Chain = Op.getOperand(0); + SDValue rA = Op.getOperand(0); + SDValue rB = Op.getOperand(1); unsigned FSMBIreg = RegInfo.createVirtualRegister(&SPU::VECREGRegClass); unsigned HiProdReg = RegInfo.createVirtualRegister(&SPU::VECREGRegClass); - SDOperand FSMBOp = + SDValue FSMBOp = DAG.getCopyToReg(Chain, FSMBIreg, DAG.getNode(SPUISD::SELECT_MASK, MVT::v8i16, DAG.getConstant(0xcccc, MVT::i16))); - SDOperand HHProd = + SDValue HHProd = DAG.getCopyToReg(FSMBOp, HiProdReg, DAG.getNode(SPUISD::MPYHH, MVT::v8i16, rA, rB)); - SDOperand HHProd_v4i32 = + SDValue HHProd_v4i32 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, DAG.getCopyFromReg(HHProd, HiProdReg, MVT::v4i32)); @@ -1952,68 +1952,68 @@ static SDOperand LowerVectorMUL(SDOperand Op, SelectionDAG &DAG) { // is to break it all apart, sign extend, and reassemble the various // intermediate products. case MVT::v16i8: { - SDOperand rA = Op.getOperand(0); - SDOperand rB = Op.getOperand(1); - SDOperand c8 = DAG.getConstant(8, MVT::i32); - SDOperand c16 = DAG.getConstant(16, MVT::i32); + SDValue rA = Op.getOperand(0); + SDValue rB = Op.getOperand(1); + SDValue c8 = DAG.getConstant(8, MVT::i32); + SDValue c16 = DAG.getConstant(16, MVT::i32); - SDOperand LLProd = + SDValue LLProd = DAG.getNode(SPUISD::MPY, MVT::v8i16, DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, rA), DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, rB)); - SDOperand rALH = DAG.getNode(SPUISD::VEC_SRA, MVT::v8i16, rA, c8); + SDValue rALH = DAG.getNode(SPUISD::VEC_SRA, MVT::v8i16, rA, c8); - SDOperand rBLH = DAG.getNode(SPUISD::VEC_SRA, MVT::v8i16, rB, c8); + SDValue rBLH = DAG.getNode(SPUISD::VEC_SRA, MVT::v8i16, rB, c8); - SDOperand LHProd = + SDValue LHProd = DAG.getNode(SPUISD::VEC_SHL, MVT::v8i16, DAG.getNode(SPUISD::MPY, MVT::v8i16, rALH, rBLH), c8); - SDOperand FSMBmask = DAG.getNode(SPUISD::SELECT_MASK, MVT::v8i16, + SDValue FSMBmask = DAG.getNode(SPUISD::SELECT_MASK, MVT::v8i16, DAG.getConstant(0x2222, MVT::i16)); - SDOperand LoProdParts = + SDValue LoProdParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, DAG.getNode(SPUISD::SELB, MVT::v8i16, LLProd, LHProd, FSMBmask)); - SDOperand LoProdMask = DAG.getConstant(0xffff, MVT::i32); + SDValue LoProdMask = DAG.getConstant(0xffff, MVT::i32); - SDOperand LoProd = + SDValue LoProd = DAG.getNode(ISD::AND, MVT::v4i32, LoProdParts, DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, LoProdMask, LoProdMask, LoProdMask, LoProdMask)); - SDOperand rAH = + SDValue rAH = DAG.getNode(SPUISD::VEC_SRA, MVT::v4i32, DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, rA), c16); - SDOperand rBH = + SDValue rBH = DAG.getNode(SPUISD::VEC_SRA, MVT::v4i32, DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, rB), c16); - SDOperand HLProd = + SDValue HLProd = DAG.getNode(SPUISD::MPY, MVT::v8i16, DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, rAH), DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, rBH)); - SDOperand HHProd_1 = + SDValue HHProd_1 = DAG.getNode(SPUISD::MPY, MVT::v8i16, DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, DAG.getNode(SPUISD::VEC_SRA, MVT::v4i32, rAH, c8)), DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, DAG.getNode(SPUISD::VEC_SRA, MVT::v4i32, rBH, c8))); - SDOperand HHProd = + SDValue HHProd = DAG.getNode(SPUISD::SELB, MVT::v8i16, HLProd, DAG.getNode(SPUISD::VEC_SHL, MVT::v8i16, HHProd_1, c8), FSMBmask); - SDOperand HiProd = + SDValue HiProd = DAG.getNode(SPUISD::VEC_SHL, MVT::v4i32, HHProd, c16); return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, @@ -2022,15 +2022,15 @@ static SDOperand LowerVectorMUL(SDOperand Op, SelectionDAG &DAG) { } } - return SDOperand(); + return SDValue(); } -static SDOperand LowerFDIVf32(SDOperand Op, SelectionDAG &DAG) { +static SDValue LowerFDIVf32(SDValue Op, SelectionDAG &DAG) { MachineFunction &MF = DAG.getMachineFunction(); MachineRegisterInfo &RegInfo = MF.getRegInfo(); - SDOperand A = Op.getOperand(0); - SDOperand B = Op.getOperand(1); + SDValue A = Op.getOperand(0); + SDValue B = Op.getOperand(1); MVT VT = Op.getValueType(); unsigned VRegBR, VRegC; @@ -2047,13 +2047,13 @@ static SDOperand LowerFDIVf32(SDOperand Op, SelectionDAG &DAG) { // Computes BRcpl = // (Floating Interpolate (FP Reciprocal Estimate B)) - SDOperand BRcpl = + SDValue BRcpl = DAG.getCopyToReg(DAG.getEntryNode(), VRegBR, DAG.getNode(SPUISD::FPInterp, VT, B, DAG.getNode(SPUISD::FPRecipEst, VT, B))); // Computes A * BRcpl and stores in a temporary register - SDOperand AxBRcpl = + SDValue AxBRcpl = DAG.getCopyToReg(BRcpl, VRegC, DAG.getNode(ISD::FMUL, VT, A, DAG.getCopyFromReg(BRcpl, VRegBR, VT))); @@ -2069,11 +2069,11 @@ static SDOperand LowerFDIVf32(SDOperand Op, SelectionDAG &DAG) { DAG.getCopyFromReg(AxBRcpl, VRegC, VT))))); } -static SDOperand LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) { +static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { MVT VT = Op.getValueType(); - SDOperand N = Op.getOperand(0); - SDOperand Elt = Op.getOperand(1); - SDOperand ShufMask[16]; + SDValue N = Op.getOperand(0); + SDValue Elt = Op.getOperand(1); + SDValue ShufMask[16]; ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt); assert(C != 0 && "LowerEXTRACT_VECTOR_ELT expecting constant SDNode"); @@ -2139,7 +2139,7 @@ static SDOperand LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) { ShufMask[i] = ShufMask[i % (prefslot_end + 1)]; } - SDOperand ShufMaskVec = + SDValue ShufMaskVec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, &ShufMask[0], sizeof(ShufMask) / sizeof(ShufMask[0])); @@ -2150,10 +2150,10 @@ static SDOperand LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) { } -static SDOperand LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) { - SDOperand VecOp = Op.getOperand(0); - SDOperand ValOp = Op.getOperand(1); - SDOperand IdxOp = Op.getOperand(2); +static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { + SDValue VecOp = Op.getOperand(0); + SDValue ValOp = Op.getOperand(1); + SDValue IdxOp = Op.getOperand(2); MVT VT = Op.getValueType(); ConstantSDNode *CN = cast<ConstantSDNode>(IdxOp); @@ -2161,9 +2161,9 @@ static SDOperand LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) { MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); // Use $2 because it's always 16-byte aligned and it's available: - SDOperand PtrBase = DAG.getRegister(SPU::R2, PtrVT); + SDValue PtrBase = DAG.getRegister(SPU::R2, PtrVT); - SDOperand result = + SDValue result = DAG.getNode(SPUISD::SHUFB, VT, DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, ValOp), VecOp, @@ -2176,9 +2176,9 @@ static SDOperand LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) { return result; } -static SDOperand LowerI8Math(SDOperand Op, SelectionDAG &DAG, unsigned Opc) +static SDValue LowerI8Math(SDValue Op, SelectionDAG &DAG, unsigned Opc) { - SDOperand N0 = Op.getOperand(0); // Everything has at least one operand + SDValue N0 = Op.getOperand(0); // Everything has at least one operand assert(Op.getValueType() == MVT::i8); switch (Opc) { @@ -2189,7 +2189,7 @@ static SDOperand LowerI8Math(SDOperand Op, SelectionDAG &DAG, unsigned Opc) case ISD::SUB: { // 8-bit subtraction: Promote the arguments up to 16-bits and truncate // the result: - SDOperand N1 = Op.getOperand(1); + SDValue N1 = Op.getOperand(1); N0 = (N0.getOpcode() != ISD::Constant ? DAG.getNode(ISD::SIGN_EXTEND, MVT::i16, N0) : DAG.getConstant(cast<ConstantSDNode>(N0)->getValue(), MVT::i16)); @@ -2201,7 +2201,7 @@ static SDOperand LowerI8Math(SDOperand Op, SelectionDAG &DAG, unsigned Opc) } case ISD::ROTR: case ISD::ROTL: { - SDOperand N1 = Op.getOperand(1); + SDValue N1 = Op.getOperand(1); unsigned N1Opc; N0 = (N0.getOpcode() != ISD::Constant ? DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, N0) @@ -2210,7 +2210,7 @@ static SDOperand LowerI8Math(SDOperand Op, SelectionDAG &DAG, unsigned Opc) N1 = (N1.getOpcode() != ISD::Constant ? DAG.getNode(N1Opc, MVT::i16, N1) : DAG.getConstant(cast<ConstantSDNode>(N1)->getValue(), MVT::i16)); - SDOperand ExpandArg = + SDValue ExpandArg = DAG.getNode(ISD::OR, MVT::i16, N0, DAG.getNode(ISD::SHL, MVT::i16, N0, DAG.getConstant(8, MVT::i16))); @@ -2219,7 +2219,7 @@ static SDOperand LowerI8Math(SDOperand Op, SelectionDAG &DAG, unsigned Opc) } case ISD::SRL: case ISD::SHL: { - SDOperand N1 = Op.getOperand(1); + SDValue N1 = Op.getOperand(1); unsigned N1Opc; N0 = (N0.getOpcode() != ISD::Constant ? DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, N0) @@ -2232,7 +2232,7 @@ static SDOperand LowerI8Math(SDOperand Op, SelectionDAG &DAG, unsigned Opc) DAG.getNode(Opc, MVT::i16, N0, N1)); } case ISD::SRA: { - SDOperand N1 = Op.getOperand(1); + SDValue N1 = Op.getOperand(1); unsigned N1Opc; N0 = (N0.getOpcode() != ISD::Constant ? DAG.getNode(ISD::SIGN_EXTEND, MVT::i16, N0) @@ -2245,7 +2245,7 @@ static SDOperand LowerI8Math(SDOperand Op, SelectionDAG &DAG, unsigned Opc) DAG.getNode(Opc, MVT::i16, N0, N1)); } case ISD::MUL: { - SDOperand N1 = Op.getOperand(1); + SDValue N1 = Op.getOperand(1); unsigned N1Opc; N0 = (N0.getOpcode() != ISD::Constant ? DAG.getNode(ISD::SIGN_EXTEND, MVT::i16, N0) @@ -2260,15 +2260,15 @@ static SDOperand LowerI8Math(SDOperand Op, SelectionDAG &DAG, unsigned Opc) } } - return SDOperand(); + return SDValue(); } -static SDOperand LowerI64Math(SDOperand Op, SelectionDAG &DAG, unsigned Opc) +static SDValue LowerI64Math(SDValue Op, SelectionDAG &DAG, unsigned Opc) { MVT VT = Op.getValueType(); MVT VecVT = MVT::getVectorVT(VT, (128 / VT.getSizeInBits())); - SDOperand Op0 = Op.getOperand(0); + SDValue Op0 = Op.getOperand(0); switch (Opc) { case ISD::ZERO_EXTEND: @@ -2284,7 +2284,7 @@ static SDOperand LowerI64Math(SDOperand Op, SelectionDAG &DAG, unsigned Opc) unsigned NewOpc = (Opc == ISD::SIGN_EXTEND ? SPUISD::ROTBYTES_RIGHT_S : SPUISD::ROTQUAD_RZ_BYTES); - SDOperand PromoteScalar = + SDValue PromoteScalar = DAG.getNode(SPUISD::PROMOTE_SCALAR, Op0VecVT, Op0); return DAG.getNode(SPUISD::EXTRACT_ELT0, VT, @@ -2297,11 +2297,11 @@ static SDOperand LowerI64Math(SDOperand Op, SelectionDAG &DAG, unsigned Opc) case ISD::ADD: { // Turn operands into vectors to satisfy type checking (shufb works on // vectors) - SDOperand Op0 = + SDValue Op0 = DAG.getNode(SPUISD::PROMOTE_SCALAR, MVT::v2i64, Op.getOperand(0)); - SDOperand Op1 = + SDValue Op1 = DAG.getNode(SPUISD::PROMOTE_SCALAR, MVT::v2i64, Op.getOperand(1)); - SmallVector<SDOperand, 16> ShufBytes; + SmallVector<SDValue, 16> ShufBytes; // Create the shuffle mask for "rotating" the borrow up one register slot // once the borrow is generated. @@ -2310,9 +2310,9 @@ static SDOperand LowerI64Math(SDOperand Op, SelectionDAG &DAG, unsigned Opc) ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, MVT::i32)); ShufBytes.push_back(DAG.getConstant(0x80808080, MVT::i32)); - SDOperand CarryGen = + SDValue CarryGen = DAG.getNode(SPUISD::CARRY_GENERATE, MVT::v2i64, Op0, Op1); - SDOperand ShiftedCarry = + SDValue ShiftedCarry = DAG.getNode(SPUISD::SHUFB, MVT::v2i64, CarryGen, CarryGen, DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, @@ -2326,11 +2326,11 @@ static SDOperand LowerI64Math(SDOperand Op, SelectionDAG &DAG, unsigned Opc) case ISD::SUB: { // Turn operands into vectors to satisfy type checking (shufb works on // vectors) - SDOperand Op0 = + SDValue Op0 = DAG.getNode(SPUISD::PROMOTE_SCALAR, MVT::v2i64, Op.getOperand(0)); - SDOperand Op1 = + SDValue Op1 = DAG.getNode(SPUISD::PROMOTE_SCALAR, MVT::v2i64, Op.getOperand(1)); - SmallVector<SDOperand, 16> ShufBytes; + SmallVector<SDValue, 16> ShufBytes; // Create the shuffle mask for "rotating" the borrow up one register slot // once the borrow is generated. @@ -2339,9 +2339,9 @@ static SDOperand LowerI64Math(SDOperand Op, SelectionDAG &DAG, unsigned Opc) ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, MVT::i32)); ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, MVT::i32)); - SDOperand BorrowGen = + SDValue BorrowGen = DAG.getNode(SPUISD::BORROW_GENERATE, MVT::v2i64, Op0, Op1); - SDOperand ShiftedBorrow = + SDValue ShiftedBorrow = DAG.getNode(SPUISD::SHUFB, MVT::v2i64, BorrowGen, BorrowGen, DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, @@ -2353,20 +2353,20 @@ static SDOperand LowerI64Math(SDOperand Op, SelectionDAG &DAG, unsigned Opc) } case ISD::SHL: { - SDOperand ShiftAmt = Op.getOperand(1); + SDValue ShiftAmt = Op.getOperand(1); MVT ShiftAmtVT = ShiftAmt.getValueType(); - SDOperand Op0Vec = DAG.getNode(SPUISD::PROMOTE_SCALAR, VecVT, Op0); - SDOperand MaskLower = + SDValue Op0Vec = DAG.getNode(SPUISD::PROMOTE_SCALAR, VecVT, Op0); + SDValue MaskLower = DAG.getNode(SPUISD::SELB, VecVT, Op0Vec, DAG.getConstant(0, VecVT), DAG.getNode(SPUISD::SELECT_MASK, VecVT, DAG.getConstant(0xff00ULL, MVT::i16))); - SDOperand ShiftAmtBytes = + SDValue ShiftAmtBytes = DAG.getNode(ISD::SRL, ShiftAmtVT, ShiftAmt, DAG.getConstant(3, ShiftAmtVT)); - SDOperand ShiftAmtBits = + SDValue ShiftAmtBits = DAG.getNode(ISD::AND, ShiftAmtVT, ShiftAmt, DAG.getConstant(7, ShiftAmtVT)); @@ -2380,13 +2380,13 @@ static SDOperand LowerI64Math(SDOperand Op, SelectionDAG &DAG, unsigned Opc) case ISD::SRL: { MVT VT = Op.getValueType(); - SDOperand ShiftAmt = Op.getOperand(1); + SDValue ShiftAmt = Op.getOperand(1); MVT ShiftAmtVT = ShiftAmt.getValueType(); - SDOperand ShiftAmtBytes = + SDValue ShiftAmtBytes = DAG.getNode(ISD::SRL, ShiftAmtVT, ShiftAmt, DAG.getConstant(3, ShiftAmtVT)); - SDOperand ShiftAmtBits = + SDValue ShiftAmtBits = DAG.getNode(ISD::AND, ShiftAmtVT, ShiftAmt, DAG.getConstant(7, ShiftAmtVT)); @@ -2399,9 +2399,9 @@ static SDOperand LowerI64Math(SDOperand Op, SelectionDAG &DAG, unsigned Opc) case ISD::SRA: { // Promote Op0 to vector - SDOperand Op0 = + SDValue Op0 = DAG.getNode(SPUISD::PROMOTE_SCALAR, MVT::v2i64, Op.getOperand(0)); - SDOperand ShiftAmt = Op.getOperand(1); + SDValue ShiftAmt = Op.getOperand(1); MVT ShiftVT = ShiftAmt.getValueType(); // Negate variable shift amounts @@ -2410,23 +2410,23 @@ static SDOperand LowerI64Math(SDOperand Op, SelectionDAG &DAG, unsigned Opc) DAG.getConstant(0, ShiftVT), ShiftAmt); } - SDOperand UpperHalfSign = + SDValue UpperHalfSign = DAG.getNode(SPUISD::EXTRACT_ELT0, MVT::i32, DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, DAG.getNode(SPUISD::VEC_SRA, MVT::v2i64, Op0, DAG.getConstant(31, MVT::i32)))); - SDOperand UpperHalfSignMask = + SDValue UpperHalfSignMask = DAG.getNode(SPUISD::SELECT_MASK, MVT::v2i64, UpperHalfSign); - SDOperand UpperLowerMask = + SDValue UpperLowerMask = DAG.getNode(SPUISD::SELECT_MASK, MVT::v2i64, DAG.getConstant(0xff00, MVT::i16)); - SDOperand UpperLowerSelect = + SDValue UpperLowerSelect = DAG.getNode(SPUISD::SELB, MVT::v2i64, UpperHalfSignMask, Op0, UpperLowerMask); - SDOperand RotateLeftBytes = + SDValue RotateLeftBytes = DAG.getNode(SPUISD::ROTBYTES_LEFT_BITS, MVT::v2i64, UpperLowerSelect, ShiftAmt); - SDOperand RotateLeftBits = + SDValue RotateLeftBits = DAG.getNode(SPUISD::ROTBYTES_LEFT, MVT::v2i64, RotateLeftBytes, ShiftAmt); @@ -2435,14 +2435,14 @@ static SDOperand LowerI64Math(SDOperand Op, SelectionDAG &DAG, unsigned Opc) } } - return SDOperand(); + return SDValue(); } //! Lower byte immediate operations for v16i8 vectors: -static SDOperand -LowerByteImmed(SDOperand Op, SelectionDAG &DAG) { - SDOperand ConstVec; - SDOperand Arg; +static SDValue +LowerByteImmed(SDValue Op, SelectionDAG &DAG) { + SDValue ConstVec; + SDValue Arg; MVT VT = Op.getValueType(); ConstVec = Op.getOperand(0); @@ -2469,8 +2469,8 @@ LowerByteImmed(SDOperand Op, SelectionDAG &DAG) { && isConstantSplat(VectorBits, UndefBits, VT.getVectorElementType().getSizeInBits(), SplatBits, SplatUndef, SplatSize)) { - SDOperand tcVec[16]; - SDOperand tc = DAG.getTargetConstant(SplatBits & 0xff, MVT::i8); + SDValue tcVec[16]; + SDValue tc = DAG.getTargetConstant(SplatBits & 0xff, MVT::i8); const size_t tcVecSize = sizeof(tcVec) / sizeof(tcVec[0]); // Turn the BUILD_VECTOR into a set of target constants: @@ -2482,11 +2482,11 @@ LowerByteImmed(SDOperand Op, SelectionDAG &DAG) { } } - return SDOperand(); + return SDValue(); } //! Lower i32 multiplication -static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG, MVT VT, +static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG, MVT VT, unsigned Opc) { switch (VT.getSimpleVT()) { default: @@ -2497,8 +2497,8 @@ static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG, MVT VT, /*NOTREACHED*/ case MVT::i32: { - SDOperand rA = Op.getOperand(0); - SDOperand rB = Op.getOperand(1); + SDValue rA = Op.getOperand(0); + SDValue rB = Op.getOperand(1); return DAG.getNode(ISD::ADD, MVT::i32, DAG.getNode(ISD::ADD, MVT::i32, @@ -2508,7 +2508,7 @@ static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG, MVT VT, } } - return SDOperand(); + return SDValue(); } //! Custom lowering for CTPOP (count population) @@ -2517,7 +2517,7 @@ static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG, MVT VT, operand. SPU has such an instruction, but it counts the number of ones per byte, which then have to be accumulated. */ -static SDOperand LowerCTPOP(SDOperand Op, SelectionDAG &DAG) { +static SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) { MVT VT = Op.getValueType(); MVT vecVT = MVT::getVectorVT(VT, (128 / VT.getSizeInBits())); @@ -2525,11 +2525,11 @@ static SDOperand LowerCTPOP(SDOperand Op, SelectionDAG &DAG) { default: assert(false && "Invalid value type!"); case MVT::i8: { - SDOperand N = Op.getOperand(0); - SDOperand Elt0 = DAG.getConstant(0, MVT::i32); + SDValue N = Op.getOperand(0); + SDValue Elt0 = DAG.getConstant(0, MVT::i32); - SDOperand Promote = DAG.getNode(SPUISD::PROMOTE_SCALAR, vecVT, N, N); - SDOperand CNTB = DAG.getNode(SPUISD::CNTB, vecVT, Promote); + SDValue Promote = DAG.getNode(SPUISD::PROMOTE_SCALAR, vecVT, N, N); + SDValue CNTB = DAG.getNode(SPUISD::CNTB, vecVT, Promote); return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i8, CNTB, Elt0); } @@ -2540,23 +2540,23 @@ static SDOperand LowerCTPOP(SDOperand Op, SelectionDAG &DAG) { unsigned CNTB_reg = RegInfo.createVirtualRegister(&SPU::R16CRegClass); - SDOperand N = Op.getOperand(0); - SDOperand Elt0 = DAG.getConstant(0, MVT::i16); - SDOperand Mask0 = DAG.getConstant(0x0f, MVT::i16); - SDOperand Shift1 = DAG.getConstant(8, MVT::i16); + SDValue N = Op.getOperand(0); + SDValue Elt0 = DAG.getConstant(0, MVT::i16); + SDValue Mask0 = DAG.getConstant(0x0f, MVT::i16); + SDValue Shift1 = DAG.getConstant(8, MVT::i16); - SDOperand Promote = DAG.getNode(SPUISD::PROMOTE_SCALAR, vecVT, N, N); - SDOperand CNTB = DAG.getNode(SPUISD::CNTB, vecVT, Promote); + SDValue Promote = DAG.getNode(SPUISD::PROMOTE_SCALAR, vecVT, N, N); + SDValue CNTB = DAG.getNode(SPUISD::CNTB, vecVT, Promote); // CNTB_result becomes the chain to which all of the virtual registers // CNTB_reg, SUM1_reg become associated: - SDOperand CNTB_result = + SDValue CNTB_result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, CNTB, Elt0); - SDOperand CNTB_rescopy = + SDValue CNTB_rescopy = DAG.getCopyToReg(CNTB_result, CNTB_reg, CNTB_result); - SDOperand Tmp1 = DAG.getCopyFromReg(CNTB_rescopy, CNTB_reg, MVT::i16); + SDValue Tmp1 = DAG.getCopyFromReg(CNTB_rescopy, CNTB_reg, MVT::i16); return DAG.getNode(ISD::AND, MVT::i16, DAG.getNode(ISD::ADD, MVT::i16, @@ -2573,39 +2573,39 @@ static SDOperand LowerCTPOP(SDOperand Op, SelectionDAG &DAG) { unsigned CNTB_reg = RegInfo.createVirtualRegister(&SPU::R32CRegClass); unsigned SUM1_reg = RegInfo.createVirtualRegister(&SPU::R32CRegClass); - SDOperand N = Op.getOperand(0); - SDOperand Elt0 = DAG.getConstant(0, MVT::i32); - SDOperand Mask0 = DAG.getConstant(0xff, MVT::i32); - SDOperand Shift1 = DAG.getConstant(16, MVT::i32); - SDOperand Shift2 = DAG.getConstant(8, MVT::i32); + SDValue N = Op.getOperand(0); + SDValue Elt0 = DAG.getConstant(0, MVT::i32); + SDValue Mask0 = DAG.getConstant(0xff, MVT::i32); + SDValue Shift1 = DAG.getConstant(16, MVT::i32); + SDValue Shift2 = DAG.getConstant(8, MVT::i32); - SDOperand Promote = DAG.getNode(SPUISD::PROMOTE_SCALAR, vecVT, N, N); - SDOperand CNTB = DAG.getNode(SPUISD::CNTB, vecVT, Promote); + SDValue Promote = DAG.getNode(SPUISD::PROMOTE_SCALAR, vecVT, N, N); + SDValue CNTB = DAG.getNode(SPUISD::CNTB, vecVT, Promote); // CNTB_result becomes the chain to which all of the virtual registers // CNTB_reg, SUM1_reg become associated: - SDOperand CNTB_result = + SDValue CNTB_result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, CNTB, Elt0); - SDOperand CNTB_rescopy = + SDValue CNTB_rescopy = DAG.getCopyToReg(CNTB_result, CNTB_reg, CNTB_result); - SDOperand Comp1 = + SDValue Comp1 = DAG.getNode(ISD::SRL, MVT::i32, DAG.getCopyFromReg(CNTB_rescopy, CNTB_reg, MVT::i32), Shift1); - SDOperand Sum1 = + SDValue Sum1 = DAG.getNode(ISD::ADD, MVT::i32, Comp1, DAG.getCopyFromReg(CNTB_rescopy, CNTB_reg, MVT::i32)); - SDOperand Sum1_rescopy = + SDValue Sum1_rescopy = DAG.getCopyToReg(CNTB_result, SUM1_reg, Sum1); - SDOperand Comp2 = + SDValue Comp2 = DAG.getNode(ISD::SRL, MVT::i32, DAG.getCopyFromReg(Sum1_rescopy, SUM1_reg, MVT::i32), Shift2); - SDOperand Sum2 = + SDValue Sum2 = DAG.getNode(ISD::ADD, MVT::i32, Comp2, DAG.getCopyFromReg(Sum1_rescopy, SUM1_reg, MVT::i32)); @@ -2616,13 +2616,13 @@ static SDOperand LowerCTPOP(SDOperand Op, SelectionDAG &DAG) { break; } - return SDOperand(); + return SDValue(); } /// LowerOperation - Provide custom lowering hooks for some operations. /// -SDOperand -SPUTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) +SDValue +SPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { unsigned Opc = (unsigned) Op.getOpcode(); MVT VT = Op.getValueType(); @@ -2718,14 +2718,14 @@ SPUTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) return LowerCTPOP(Op, DAG); } - return SDOperand(); + return SDValue(); } //===----------------------------------------------------------------------===// // Target Optimization Hooks //===----------------------------------------------------------------------===// -SDOperand +SDValue SPUTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { #if 0 @@ -2733,23 +2733,23 @@ SPUTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const #endif const SPUSubtarget *ST = SPUTM.getSubtargetImpl(); SelectionDAG &DAG = DCI.DAG; - SDOperand Op0 = N->getOperand(0); // everything has at least one operand - SDOperand Result; // Initially, NULL result + SDValue Op0 = N->getOperand(0); // everything has at least one operand + SDValue Result; // Initially, NULL result switch (N->getOpcode()) { default: break; case ISD::ADD: { - SDOperand Op1 = N->getOperand(1); + SDValue Op1 = N->getOperand(1); if (isa<ConstantSDNode>(Op1) && Op0.getOpcode() == SPUISD::IndirectAddr) { - SDOperand Op01 = Op0.getOperand(1); + SDValue Op01 = Op0.getOperand(1); if (Op01.getOpcode() == ISD::Constant || Op01.getOpcode() == ISD::TargetConstant) { // (add <const>, (SPUindirect <arg>, <const>)) -> // (SPUindirect <arg>, <const + const>) ConstantSDNode *CN0 = cast<ConstantSDNode>(Op1); ConstantSDNode *CN1 = cast<ConstantSDNode>(Op01); - SDOperand combinedConst = + SDValue combinedConst = DAG.getConstant(CN0->getValue() + CN1->getValue(), Op0.getValueType()); @@ -2762,14 +2762,14 @@ SPUTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const } } else if (isa<ConstantSDNode>(Op0) && Op1.getOpcode() == SPUISD::IndirectAddr) { - SDOperand Op11 = Op1.getOperand(1); + SDValue Op11 = Op1.getOperand(1); if (Op11.getOpcode() == ISD::Constant || Op11.getOpcode() == ISD::TargetConstant) { // (add (SPUindirect <arg>, <const>), <const>) -> // (SPUindirect <arg>, <const + const>) ConstantSDNode *CN0 = cast<ConstantSDNode>(Op0); ConstantSDNode *CN1 = cast<ConstantSDNode>(Op11); - SDOperand combinedConst = + SDValue combinedConst = DAG.getConstant(CN0->getValue() + CN1->getValue(), Op0.getValueType()); @@ -2827,7 +2827,7 @@ SPUTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const case SPUISD::VEC_SRA: case SPUISD::ROTQUAD_RZ_BYTES: case SPUISD::ROTQUAD_RZ_BITS: { - SDOperand Op1 = N->getOperand(1); + SDValue Op1 = N->getOperand(1); if (isa<ConstantSDNode>(Op1)) { // Kill degenerate vector shifts: @@ -2849,9 +2849,9 @@ SPUTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const // (SPUpromote_scalar (any|sign|zero_extend (SPUextract_elt0 <arg>))) -> // <arg> // but only if the SPUpromote_scalar and <arg> types match. - SDOperand Op00 = Op0.getOperand(0); + SDValue Op00 = Op0.getOperand(0); if (Op00.getOpcode() == SPUISD::EXTRACT_ELT0) { - SDOperand Op000 = Op00.getOperand(0); + SDValue Op000 = Op00.getOperand(0); if (Op000.getValueType() == N->getValueType(0)) { Result = Op000; } @@ -2932,7 +2932,7 @@ SPUTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, //! Compute used/known bits for a SPU operand void -SPUTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, +SPUTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, const APInt &Mask, APInt &KnownZero, APInt &KnownOne, @@ -2955,7 +2955,7 @@ SPUTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, #endif case SPUISD::PROMOTE_SCALAR: { - SDOperand Op0 = Op.getOperand(0); + SDValue Op0 = Op.getOperand(0); MVT Op0VT = Op0.getValueType(); unsigned Op0VTBits = Op0VT.getSizeInBits(); uint64_t InMask = Op0VT.getIntegerVTBitMask(); @@ -3007,9 +3007,9 @@ SPUTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, // LowerAsmOperandForConstraint void -SPUTargetLowering::LowerAsmOperandForConstraint(SDOperand Op, +SPUTargetLowering::LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter, - std::vector<SDOperand> &Ops, + std::vector<SDValue> &Ops, SelectionDAG &DAG) const { // Default, for the time being, to the base class handler TargetLowering::LowerAsmOperandForConstraint(Op, ConstraintLetter, Ops, DAG); diff --git a/lib/Target/CellSPU/SPUISelLowering.h b/lib/Target/CellSPU/SPUISelLowering.h index 5c41c29..814c9ba 100644 --- a/lib/Target/CellSPU/SPUISelLowering.h +++ b/lib/Target/CellSPU/SPUISelLowering.h @@ -78,18 +78,18 @@ namespace llvm { /// Predicates that are used for node matching: namespace SPU { - SDOperand get_vec_u18imm(SDNode *N, SelectionDAG &DAG, + SDValue get_vec_u18imm(SDNode *N, SelectionDAG &DAG, MVT ValueType); - SDOperand get_vec_i16imm(SDNode *N, SelectionDAG &DAG, + SDValue get_vec_i16imm(SDNode *N, SelectionDAG &DAG, MVT ValueType); - SDOperand get_vec_i10imm(SDNode *N, SelectionDAG &DAG, + SDValue get_vec_i10imm(SDNode *N, SelectionDAG &DAG, MVT ValueType); - SDOperand get_vec_i8imm(SDNode *N, SelectionDAG &DAG, + SDValue get_vec_i8imm(SDNode *N, SelectionDAG &DAG, MVT ValueType); - SDOperand get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG, + SDValue get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG, MVT ValueType); - SDOperand get_v4i32_imm(SDNode *N, SelectionDAG &DAG); - SDOperand get_v2i64_imm(SDNode *N, SelectionDAG &DAG); + SDValue get_v4i32_imm(SDNode *N, SelectionDAG &DAG); + SDValue get_v2i64_imm(SDNode *N, SelectionDAG &DAG); } class SPUTargetMachine; // forward dec'l. @@ -109,15 +109,15 @@ namespace llvm { virtual const char *getTargetNodeName(unsigned Opcode) const; /// getSetCCResultType - Return the ValueType for ISD::SETCC - virtual MVT getSetCCResultType(const SDOperand &) const; + virtual MVT getSetCCResultType(const SDValue &) const; /// LowerOperation - Provide custom lowering hooks for some operations. /// - virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); + virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); - virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; + virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; - virtual void computeMaskedBitsForTargetNode(const SDOperand Op, + virtual void computeMaskedBitsForTargetNode(const SDValue Op, const APInt &Mask, APInt &KnownZero, APInt &KnownOne, @@ -130,8 +130,8 @@ namespace llvm { getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const; - void LowerAsmOperandForConstraint(SDOperand Op, char ConstraintLetter, - std::vector<SDOperand> &Ops, + void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter, + std::vector<SDValue> &Ops, SelectionDAG &DAG) const; /// isLegalAddressImmediate - Return true if the integer value can be used diff --git a/lib/Target/CellSPU/SPUOperands.td b/lib/Target/CellSPU/SPUOperands.td index d17faac..d9baf45 100644 --- a/lib/Target/CellSPU/SPUOperands.td +++ b/lib/Target/CellSPU/SPUOperands.td @@ -16,7 +16,7 @@ def LO16 : SDNodeXForm<imm, [{ }]>; def LO16_vec : SDNodeXForm<scalar_to_vector, [{ - SDOperand OpVal(0, 0); + SDValue OpVal(0, 0); // Transformation function: get the low 16 bit immediate from a build_vector // node. @@ -43,7 +43,7 @@ def HI16 : SDNodeXForm<imm, [{ // Transformation function: shift the high 16 bit immediate from a build_vector // node into the low 16 bits, and return a 16-bit constant. def HI16_vec : SDNodeXForm<scalar_to_vector, [{ - SDOperand OpVal(0, 0); + SDValue OpVal(0, 0); assert(N->getOpcode() == ISD::BUILD_VECTOR && "HI16_vec got something other than a BUILD_VECTOR"); diff --git a/lib/Target/IA64/IA64ISelDAGToDAG.cpp b/lib/Target/IA64/IA64ISelDAGToDAG.cpp index 8f6840e..c5c3114 100644 --- a/lib/Target/IA64/IA64ISelDAGToDAG.cpp +++ b/lib/Target/IA64/IA64ISelDAGToDAG.cpp @@ -51,19 +51,19 @@ namespace { /// getI64Imm - Return a target constant with the specified value, of type /// i64. - inline SDOperand getI64Imm(uint64_t Imm) { + inline SDValue getI64Imm(uint64_t Imm) { return CurDAG->getTargetConstant(Imm, MVT::i64); } /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC /// base register. Return the virtual register that holds this value. - // SDOperand getGlobalBaseReg(); TODO: hmm + // SDValue getGlobalBaseReg(); TODO: hmm // Select - Convert the specified operand from a target-independent to a // target-specific node if it hasn't already been changed. - SDNode *Select(SDOperand N); + SDNode *Select(SDValue N); - SDNode *SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS, + SDNode *SelectIntImmediateExpr(SDValue LHS, SDValue RHS, unsigned OCHi, unsigned OCLo, bool IsArithmetic = false, bool Negate = false); @@ -71,12 +71,12 @@ namespace { /// SelectCC - Select a comparison of the specified values with the /// specified condition code, returning the CR# of the expression. - SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC); + SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC); /// SelectAddr - Given the specified address, return the two operands for a /// load/store instruction, and return true if it should be an indexed [r+r] /// operation. - bool SelectAddr(SDOperand Addr, SDOperand &Op1, SDOperand &Op2); + bool SelectAddr(SDValue Addr, SDValue &Op1, SDValue &Op2); /// InstructionSelect - This callback is invoked by /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. @@ -90,7 +90,7 @@ namespace { #include "IA64GenDAGISel.inc" private: - SDNode *SelectDIV(SDOperand Op); + SDNode *SelectDIV(SDValue Op); }; } @@ -104,11 +104,11 @@ void IA64DAGToDAGISel::InstructionSelect(SelectionDAG &DAG) { DAG.RemoveDeadNodes(); } -SDNode *IA64DAGToDAGISel::SelectDIV(SDOperand Op) { +SDNode *IA64DAGToDAGISel::SelectDIV(SDValue Op) { SDNode *N = Op.Val; - SDOperand Chain = N->getOperand(0); - SDOperand Tmp1 = N->getOperand(0); - SDOperand Tmp2 = N->getOperand(1); + SDValue Chain = N->getOperand(0); + SDValue Tmp1 = N->getOperand(0); + SDValue Tmp2 = N->getOperand(1); AddToISelQueue(Chain); AddToISelQueue(Tmp1); @@ -133,40 +133,40 @@ SDNode *IA64DAGToDAGISel::SelectDIV(SDOperand Op) { // TODO: check for integer divides by powers of 2 (or other simple patterns?) - SDOperand TmpPR, TmpPR2; - SDOperand TmpF1, TmpF2, TmpF3, TmpF4, TmpF5, TmpF6, TmpF7, TmpF8; - SDOperand TmpF9, TmpF10,TmpF11,TmpF12,TmpF13,TmpF14,TmpF15; + SDValue TmpPR, TmpPR2; + SDValue TmpF1, TmpF2, TmpF3, TmpF4, TmpF5, TmpF6, TmpF7, TmpF8; + SDValue TmpF9, TmpF10,TmpF11,TmpF12,TmpF13,TmpF14,TmpF15; SDNode *Result; // we'll need copies of F0 and F1 - SDOperand F0 = CurDAG->getRegister(IA64::F0, MVT::f64); - SDOperand F1 = CurDAG->getRegister(IA64::F1, MVT::f64); + SDValue F0 = CurDAG->getRegister(IA64::F0, MVT::f64); + SDValue F1 = CurDAG->getRegister(IA64::F1, MVT::f64); // OK, emit some code: if(!isFP) { // first, load the inputs into FP regs. TmpF1 = - SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp1), 0); + SDValue(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp1), 0); Chain = TmpF1.getValue(1); TmpF2 = - SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp2), 0); + SDValue(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp2), 0); Chain = TmpF2.getValue(1); // next, convert the inputs to FP if(isSigned) { TmpF3 = - SDOperand(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF1), 0); + SDValue(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF1), 0); Chain = TmpF3.getValue(1); TmpF4 = - SDOperand(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF2), 0); + SDValue(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF2), 0); Chain = TmpF4.getValue(1); } else { // is unsigned TmpF3 = - SDOperand(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF1), 0); + SDValue(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF1), 0); Chain = TmpF3.getValue(1); TmpF4 = - SDOperand(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF2), 0); + SDValue(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF2), 0); Chain = TmpF4.getValue(1); } @@ -179,39 +179,39 @@ SDNode *IA64DAGToDAGISel::SelectDIV(SDOperand Op) { // we start by computing an approximate reciprocal (good to 9 bits?) // note, this instruction writes _both_ TmpF5 (answer) and TmpPR (predicate) if(isFP) - TmpF5 = SDOperand(CurDAG->getTargetNode(IA64::FRCPAS0, MVT::f64, MVT::i1, + TmpF5 = SDValue(CurDAG->getTargetNode(IA64::FRCPAS0, MVT::f64, MVT::i1, TmpF3, TmpF4), 0); else - TmpF5 = SDOperand(CurDAG->getTargetNode(IA64::FRCPAS1, MVT::f64, MVT::i1, + TmpF5 = SDValue(CurDAG->getTargetNode(IA64::FRCPAS1, MVT::f64, MVT::i1, TmpF3, TmpF4), 0); TmpPR = TmpF5.getValue(1); Chain = TmpF5.getValue(2); - SDOperand minusB; + SDValue minusB; if(isModulus) { // for remainders, it'll be handy to have // copies of -input_b - minusB = SDOperand(CurDAG->getTargetNode(IA64::SUB, MVT::i64, + minusB = SDValue(CurDAG->getTargetNode(IA64::SUB, MVT::i64, CurDAG->getRegister(IA64::r0, MVT::i64), Tmp2), 0); Chain = minusB.getValue(1); } - SDOperand TmpE0, TmpY1, TmpE1, TmpY2; + SDValue TmpE0, TmpY1, TmpE1, TmpY2; - SDOperand OpsE0[] = { TmpF4, TmpF5, F1, TmpPR }; - TmpE0 = SDOperand(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64, + SDValue OpsE0[] = { TmpF4, TmpF5, F1, TmpPR }; + TmpE0 = SDValue(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64, OpsE0, 4), 0); Chain = TmpE0.getValue(1); - SDOperand OpsY1[] = { TmpF5, TmpE0, TmpF5, TmpPR }; - TmpY1 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64, + SDValue OpsY1[] = { TmpF5, TmpE0, TmpF5, TmpPR }; + TmpY1 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64, OpsY1, 4), 0); Chain = TmpY1.getValue(1); - SDOperand OpsE1[] = { TmpE0, TmpE0, F0, TmpPR }; - TmpE1 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64, + SDValue OpsE1[] = { TmpE0, TmpE0, F0, TmpPR }; + TmpE1 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64, OpsE1, 4), 0); Chain = TmpE1.getValue(1); - SDOperand OpsY2[] = { TmpY1, TmpE1, TmpY1, TmpPR }; - TmpY2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64, + SDValue OpsY2[] = { TmpY1, TmpE1, TmpY1, TmpPR }; + TmpY2 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64, OpsY2, 4), 0); Chain = TmpY2.getValue(1); @@ -219,53 +219,53 @@ SDNode *IA64DAGToDAGISel::SelectDIV(SDOperand Op) { if(isModulus) assert(0 && "Sorry, try another FORTRAN compiler."); - SDOperand TmpE2, TmpY3, TmpQ0, TmpR0; + SDValue TmpE2, TmpY3, TmpQ0, TmpR0; - SDOperand OpsE2[] = { TmpE1, TmpE1, F0, TmpPR }; - TmpE2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64, + SDValue OpsE2[] = { TmpE1, TmpE1, F0, TmpPR }; + TmpE2 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64, OpsE2, 4), 0); Chain = TmpE2.getValue(1); - SDOperand OpsY3[] = { TmpY2, TmpE2, TmpY2, TmpPR }; - TmpY3 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64, + SDValue OpsY3[] = { TmpY2, TmpE2, TmpY2, TmpPR }; + TmpY3 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64, OpsY3, 4), 0); Chain = TmpY3.getValue(1); - SDOperand OpsQ0[] = { Tmp1, TmpY3, F0, TmpPR }; + SDValue OpsQ0[] = { Tmp1, TmpY3, F0, TmpPR }; TmpQ0 = - SDOperand(CurDAG->getTargetNode(IA64::CFMADS1, MVT::f64, // double prec! + SDValue(CurDAG->getTargetNode(IA64::CFMADS1, MVT::f64, // double prec! OpsQ0, 4), 0); Chain = TmpQ0.getValue(1); - SDOperand OpsR0[] = { Tmp2, TmpQ0, Tmp1, TmpPR }; + SDValue OpsR0[] = { Tmp2, TmpQ0, Tmp1, TmpPR }; TmpR0 = - SDOperand(CurDAG->getTargetNode(IA64::CFNMADS1, MVT::f64, // double prec! + SDValue(CurDAG->getTargetNode(IA64::CFNMADS1, MVT::f64, // double prec! OpsR0, 4), 0); Chain = TmpR0.getValue(1); // we want Result to have the same target register as the frcpa, so // we two-address hack it. See the comment "for this to work..." on // page 48 of Intel application note #245415 - SDOperand Ops[] = { TmpF5, TmpY3, TmpR0, TmpQ0, TmpPR }; + SDValue Ops[] = { TmpF5, TmpY3, TmpR0, TmpQ0, TmpPR }; Result = CurDAG->getTargetNode(IA64::TCFMADS0, MVT::f64, // d.p. s0 rndg! Ops, 5); - Chain = SDOperand(Result, 1); + Chain = SDValue(Result, 1); return Result; // XXX: early exit! } else { // this is *not* an FP divide, so there's a bit left to do: - SDOperand TmpQ2, TmpR2, TmpQ3, TmpQ; + SDValue TmpQ2, TmpR2, TmpQ3, TmpQ; - SDOperand OpsQ2[] = { TmpF3, TmpY2, F0, TmpPR }; - TmpQ2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64, + SDValue OpsQ2[] = { TmpF3, TmpY2, F0, TmpPR }; + TmpQ2 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64, OpsQ2, 4), 0); Chain = TmpQ2.getValue(1); - SDOperand OpsR2[] = { TmpF4, TmpQ2, TmpF3, TmpPR }; - TmpR2 = SDOperand(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64, + SDValue OpsR2[] = { TmpF4, TmpQ2, TmpF3, TmpPR }; + TmpR2 = SDValue(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64, OpsR2, 4), 0); Chain = TmpR2.getValue(1); // we want TmpQ3 to have the same target register as the frcpa? maybe we // should two-address hack it. See the comment "for this to work..." on page // 48 of Intel application note #245415 - SDOperand OpsQ3[] = { TmpF5, TmpR2, TmpY2, TmpQ2, TmpPR }; - TmpQ3 = SDOperand(CurDAG->getTargetNode(IA64::TCFMAS1, MVT::f64, + SDValue OpsQ3[] = { TmpF5, TmpR2, TmpY2, TmpQ2, TmpPR }; + TmpQ3 = SDValue(CurDAG->getTargetNode(IA64::TCFMAS1, MVT::f64, OpsQ3, 5), 0); Chain = TmpQ3.getValue(1); @@ -274,27 +274,27 @@ SDNode *IA64DAGToDAGISel::SelectDIV(SDOperand Op) { // arguments. Other fun bugs may also appear, e.g. 0/x = x, not 0. if(isSigned) - TmpQ = SDOperand(CurDAG->getTargetNode(IA64::FCVTFXTRUNCS1, + TmpQ = SDValue(CurDAG->getTargetNode(IA64::FCVTFXTRUNCS1, MVT::f64, TmpQ3), 0); else - TmpQ = SDOperand(CurDAG->getTargetNode(IA64::FCVTFXUTRUNCS1, + TmpQ = SDValue(CurDAG->getTargetNode(IA64::FCVTFXUTRUNCS1, MVT::f64, TmpQ3), 0); Chain = TmpQ.getValue(1); if(isModulus) { - SDOperand FPminusB = - SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, minusB), 0); + SDValue FPminusB = + SDValue(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, minusB), 0); Chain = FPminusB.getValue(1); - SDOperand Remainder = - SDOperand(CurDAG->getTargetNode(IA64::XMAL, MVT::f64, + SDValue Remainder = + SDValue(CurDAG->getTargetNode(IA64::XMAL, MVT::f64, TmpQ, FPminusB, TmpF1), 0); Chain = Remainder.getValue(1); Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, Remainder); - Chain = SDOperand(Result, 1); + Chain = SDValue(Result, 1); } else { // just an integer divide Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, TmpQ); - Chain = SDOperand(Result, 1); + Chain = SDValue(Result, 1); } return Result; @@ -303,7 +303,7 @@ SDNode *IA64DAGToDAGISel::SelectDIV(SDOperand Op) { // Select - Convert the specified operand from a target-independent to a // target-specific node if it hasn't already been changed. -SDNode *IA64DAGToDAGISel::Select(SDOperand Op) { +SDNode *IA64DAGToDAGISel::Select(SDValue Op) { SDNode *N = Op.Val; if (N->isMachineOpcode()) return NULL; // Already selected. @@ -312,8 +312,8 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) { default: break; case IA64ISD::BRCALL: { // XXX: this is also a hack! - SDOperand Chain = N->getOperand(0); - SDOperand InFlag; // Null incoming flag value. + SDValue Chain = N->getOperand(0); + SDValue InFlag; // Null incoming flag value. AddToISelQueue(Chain); if(N->getNumOperands()==3) { // we have an incoming chain, callee and flag @@ -322,7 +322,7 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) { } unsigned CallOpcode; - SDOperand CallOperand; + SDValue CallOperand; // if we can call directly, do so if (GlobalAddressSDNode *GASD = @@ -338,22 +338,22 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) { // otherwise we need to load the function descriptor, // load the branch target (function)'s entry point and GP, // branch (call) then restore the GP - SDOperand FnDescriptor = N->getOperand(1); + SDValue FnDescriptor = N->getOperand(1); AddToISelQueue(FnDescriptor); // load the branch target's entry point [mem] and // GP value [mem+8] - SDOperand targetEntryPoint= - SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64, MVT::Other, + SDValue targetEntryPoint= + SDValue(CurDAG->getTargetNode(IA64::LD8, MVT::i64, MVT::Other, FnDescriptor, CurDAG->getEntryNode()), 0); Chain = targetEntryPoint.getValue(1); - SDOperand targetGPAddr= - SDOperand(CurDAG->getTargetNode(IA64::ADDS, MVT::i64, + SDValue targetGPAddr= + SDValue(CurDAG->getTargetNode(IA64::ADDS, MVT::i64, FnDescriptor, CurDAG->getConstant(8, MVT::i64)), 0); Chain = targetGPAddr.getValue(1); - SDOperand targetGP = - SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64,MVT::Other, + SDValue targetGP = + SDValue(CurDAG->getTargetNode(IA64::LD8, MVT::i64,MVT::Other, targetGPAddr, CurDAG->getEntryNode()), 0); Chain = targetGP.getValue(1); @@ -368,14 +368,14 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) { // Finally, once everything is setup, emit the call itself if(InFlag.Val) - Chain = SDOperand(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag, + Chain = SDValue(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag, CallOperand, InFlag), 0); else // there might be no arguments - Chain = SDOperand(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag, + Chain = SDValue(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag, CallOperand, Chain), 0); InFlag = Chain.getValue(1); - std::vector<SDOperand> CallResults; + std::vector<SDValue> CallResults; CallResults.push_back(Chain); CallResults.push_back(InFlag); @@ -386,7 +386,7 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) { } case IA64ISD::GETFD: { - SDOperand Input = N->getOperand(0); + SDValue Input = N->getOperand(0); AddToISelQueue(Input); return CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Input); } @@ -399,9 +399,9 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) { return SelectDIV(Op); case ISD::TargetConstantFP: { - SDOperand Chain = CurDAG->getEntryNode(); // this is a constant, so.. + SDValue Chain = CurDAG->getEntryNode(); // this is a constant, so.. - SDOperand V; + SDValue V; ConstantFPSDNode* N2 = cast<ConstantFPSDNode>(N); if (N2->getValueAPF().isPosZero()) { V = CurDAG->getCopyFromReg(Chain, IA64::F0, MVT::f64); @@ -411,7 +411,7 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) { } else assert(0 && "Unexpected FP constant!"); - ReplaceUses(SDOperand(N, 0), V); + ReplaceUses(SDValue(N, 0), V); return 0; } @@ -429,7 +429,7 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) { // (ia64 doesn't need one) ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N); Constant *C = CP->getConstVal(); - SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64, + SDValue CPI = CurDAG->getTargetConstantPool(C, MVT::i64, CP->getAlignment()); return CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, // ? CurDAG->getRegister(IA64::r1, MVT::i64), CPI); @@ -437,9 +437,9 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) { case ISD::GlobalAddress: { GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal(); - SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64); - SDOperand Tmp = - SDOperand(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, + SDValue GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64); + SDValue Tmp = + SDValue(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, CurDAG->getRegister(IA64::r1, MVT::i64), GA), 0); return CurDAG->getTargetNode(IA64::LD8, MVT::i64, MVT::Other, Tmp, @@ -448,10 +448,10 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) { /* XXX case ISD::ExternalSymbol: { - SDOperand EA = CurDAG->getTargetExternalSymbol( + SDValue EA = CurDAG->getTargetExternalSymbol( cast<ExternalSymbolSDNode>(N)->getSymbol(), MVT::i64); - SDOperand Tmp = CurDAG->getTargetNode(IA64::ADDL_EA, MVT::i64, + SDValue Tmp = CurDAG->getTargetNode(IA64::ADDL_EA, MVT::i64, CurDAG->getRegister(IA64::r1, MVT::i64), EA); @@ -461,8 +461,8 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) { case ISD::LOAD: { // FIXME: load -1, not 1, for bools? LoadSDNode *LD = cast<LoadSDNode>(N); - SDOperand Chain = LD->getChain(); - SDOperand Address = LD->getBasePtr(); + SDValue Chain = LD->getChain(); + SDValue Address = LD->getBasePtr(); AddToISelQueue(Chain); AddToISelQueue(Address); @@ -478,7 +478,7 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) { Opc = IA64::LD1; // first we load a byte, then compare for != 0 if(N->getValueType(0) == MVT::i1) { // XXX: early exit! return CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other, - SDOperand(CurDAG->getTargetNode(Opc, MVT::i64, Address), 0), + SDValue(CurDAG->getTargetNode(Opc, MVT::i64, Address), 0), CurDAG->getRegister(IA64::r0, MVT::i64), Chain); } @@ -501,8 +501,8 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) { case ISD::STORE: { StoreSDNode *ST = cast<StoreSDNode>(N); - SDOperand Address = ST->getBasePtr(); - SDOperand Chain = ST->getChain(); + SDValue Address = ST->getBasePtr(); + SDValue Chain = ST->getChain(); AddToISelQueue(Address); AddToISelQueue(Chain); @@ -513,13 +513,13 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) { case MVT::i1: { // this is a bool Opc = IA64::ST1; // we store either 0 or 1 as a byte // first load zero! - SDOperand Initial = CurDAG->getCopyFromReg(Chain, IA64::r0, MVT::i64); + SDValue Initial = CurDAG->getCopyFromReg(Chain, IA64::r0, MVT::i64); Chain = Initial.getValue(1); // then load 1 into the same reg iff the predicate to store is 1 - SDOperand Tmp = ST->getValue(); + SDValue Tmp = ST->getValue(); AddToISelQueue(Tmp); Tmp = - SDOperand(CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial, + SDValue(CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial, CurDAG->getTargetConstant(1, MVT::i64), Tmp), 0); return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain); @@ -537,16 +537,16 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) { } } - SDOperand N1 = N->getOperand(1); - SDOperand N2 = N->getOperand(2); + SDValue N1 = N->getOperand(1); + SDValue N2 = N->getOperand(2); AddToISelQueue(N1); AddToISelQueue(N2); return CurDAG->SelectNodeTo(N, Opc, MVT::Other, N2, N1, Chain); } case ISD::BRCOND: { - SDOperand Chain = N->getOperand(0); - SDOperand CC = N->getOperand(1); + SDValue Chain = N->getOperand(0); + SDValue CC = N->getOperand(1); AddToISelQueue(Chain); AddToISelQueue(CC); MachineBasicBlock *Dest = @@ -561,14 +561,14 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) { int64_t Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue(); unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ? IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP; - SDOperand N0 = N->getOperand(0); + SDValue N0 = N->getOperand(0); AddToISelQueue(N0); return CurDAG->SelectNodeTo(N, Opc, MVT::Other, getI64Imm(Amt), N0); } case ISD::BR: // FIXME: we don't need long branches all the time! - SDOperand N0 = N->getOperand(0); + SDValue N0 = N->getOperand(0); AddToISelQueue(N0); return CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other, N->getOperand(1), N0); diff --git a/lib/Target/IA64/IA64ISelLowering.cpp b/lib/Target/IA64/IA64ISelLowering.cpp index fa04672..87c81bf 100644 --- a/lib/Target/IA64/IA64ISelLowering.cpp +++ b/lib/Target/IA64/IA64ISelLowering.cpp @@ -140,12 +140,12 @@ const char *IA64TargetLowering::getTargetNodeName(unsigned Opcode) const { } } -MVT IA64TargetLowering::getSetCCResultType(const SDOperand &) const { +MVT IA64TargetLowering::getSetCCResultType(const SDValue &) const { return MVT::i1; } void IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG, - SmallVectorImpl<SDOperand> &ArgValues) { + SmallVectorImpl<SDValue> &ArgValues) { // // add beautiful description of IA64 stack frame format // here (from intel 24535803.pdf most likely) @@ -177,7 +177,7 @@ void IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG, for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { - SDOperand newroot, argt; + SDValue newroot, argt; if(count < 8) { // need to fix this logic? maybe. switch (getValueType(I->getType()).getSimpleVT()) { @@ -229,7 +229,7 @@ void IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG, // Create the SelectionDAG nodes corresponding to a load //from this parameter - SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64); + SDValue FIN = DAG.getFrameIndex(FI, MVT::i64); argt = newroot = DAG.getLoad(getValueType(I->getType()), DAG.getEntryNode(), FIN, NULL, 0); } @@ -302,11 +302,11 @@ void IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG, } } -std::pair<SDOperand, SDOperand> -IA64TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, +std::pair<SDValue, SDValue> +IA64TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt, bool isVarArg, unsigned CallingConv, - bool isTailCall, SDOperand Callee, + bool isTailCall, SDValue Callee, ArgListTy &Args, SelectionDAG &DAG) { MachineFunction &MF = DAG.getMachineFunction(); @@ -335,17 +335,17 @@ IA64TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy())); - SDOperand StackPtr; - std::vector<SDOperand> Stores; - std::vector<SDOperand> Converts; - std::vector<SDOperand> RegValuesToPass; + SDValue StackPtr; + std::vector<SDValue> Stores; + std::vector<SDValue> Converts; + std::vector<SDValue> RegValuesToPass; unsigned ArgOffset = 16; for (unsigned i = 0, e = Args.size(); i != e; ++i) { - SDOperand Val = Args[i].Node; + SDValue Val = Args[i].Node; MVT ObjectVT = Val.getValueType(); - SDOperand ValToStore(0, 0), ValToConvert(0, 0); + SDValue ValToStore(0, 0), ValToConvert(0, 0); unsigned ObjSize=8; switch (ObjectVT.getSimpleVT()) { default: assert(0 && "unexpected argument type!"); @@ -391,7 +391,7 @@ IA64TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, if(!StackPtr.Val) { StackPtr = DAG.getRegister(IA64::r12, MVT::i64); } - SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); + SDValue PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); PtrOff = DAG.getNode(ISD::ADD, MVT::i64, StackPtr, PtrOff); Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0)); ArgOffset += ObjSize; @@ -416,16 +416,16 @@ IA64TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, IA64::F12, IA64::F13, IA64::F14, IA64::F15 }; - SDOperand InFlag; + SDValue InFlag; // save the current GP, SP and RP : FIXME: do we need to do all 3 always? - SDOperand GPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r1, MVT::i64, InFlag); + SDValue GPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r1, MVT::i64, InFlag); Chain = GPBeforeCall.getValue(1); InFlag = Chain.getValue(2); - SDOperand SPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r12, MVT::i64, InFlag); + SDValue SPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r12, MVT::i64, InFlag); Chain = SPBeforeCall.getValue(1); InFlag = Chain.getValue(2); - SDOperand RPBeforeCall = DAG.getCopyFromReg(Chain, IA64::rp, MVT::i64, InFlag); + SDValue RPBeforeCall = DAG.getCopyFromReg(Chain, IA64::rp, MVT::i64, InFlag); Chain = RPBeforeCall.getValue(1); InFlag = Chain.getValue(2); @@ -464,7 +464,7 @@ IA64TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, */ std::vector<MVT> NodeTys; - std::vector<SDOperand> CallOperands; + std::vector<SDValue> CallOperands; NodeTys.push_back(MVT::Other); // Returns a chain NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. CallOperands.push_back(Chain); @@ -494,17 +494,17 @@ IA64TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, RetVals.push_back(MVT::Flag); MVT RetTyVT = getValueType(RetTy); - SDOperand RetVal; + SDValue RetVal; if (RetTyVT != MVT::isVoid) { switch (RetTyVT.getSimpleVT()) { default: assert(0 && "Unknown value type to return!"); case MVT::i1: { // bools are just like other integers (returned in r8) // we *could* fall through to the truncate below, but this saves a // few redundant predicate ops - SDOperand boolInR8 = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64,InFlag); + SDValue boolInR8 = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64,InFlag); InFlag = boolInR8.getValue(2); Chain = boolInR8.getValue(1); - SDOperand zeroReg = DAG.getCopyFromReg(Chain, IA64::r0, MVT::i64, InFlag); + SDValue zeroReg = DAG.getCopyFromReg(Chain, IA64::r0, MVT::i64, InFlag); InFlag = zeroReg.getValue(2); Chain = zeroReg.getValue(1); @@ -546,18 +546,18 @@ IA64TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, Chain = DAG.getCALLSEQ_END(Chain, DAG.getConstant(NumBytes, getPointerTy()), DAG.getConstant(0, getPointerTy()), - SDOperand()); + SDValue()); return std::make_pair(RetVal, Chain); } -SDOperand IA64TargetLowering:: -LowerOperation(SDOperand Op, SelectionDAG &DAG) { +SDValue IA64TargetLowering:: +LowerOperation(SDValue Op, SelectionDAG &DAG) { switch (Op.getOpcode()) { default: assert(0 && "Should not custom lower this!"); case ISD::GlobalTLSAddress: assert(0 && "TLS not implemented for IA64."); case ISD::RET: { - SDOperand AR_PFSVal, Copy; + SDValue AR_PFSVal, Copy; switch(Op.getNumOperands()) { default: @@ -575,22 +575,22 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) { AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), VirtGPR, MVT::i64); Copy = DAG.getCopyToReg(AR_PFSVal.getValue(1), ArgReg, Op.getOperand(1), - SDOperand()); + SDValue()); AR_PFSVal = DAG.getCopyToReg(Copy.getValue(0), IA64::AR_PFS, AR_PFSVal, Copy.getValue(1)); return DAG.getNode(IA64ISD::RET_FLAG, MVT::Other, AR_PFSVal, AR_PFSVal.getValue(1)); } } - return SDOperand(); + return SDValue(); } case ISD::VAARG: { MVT VT = getPointerTy(); const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); - SDOperand VAList = DAG.getLoad(VT, Op.getOperand(0), Op.getOperand(1), + SDValue VAList = DAG.getLoad(VT, Op.getOperand(0), Op.getOperand(1), SV, 0); // Increment the pointer, VAList, to the next vaarg - SDOperand VAIncr = DAG.getNode(ISD::ADD, VT, VAList, + SDValue VAIncr = DAG.getNode(ISD::ADD, VT, VAList, DAG.getConstant(VT.getSizeInBits()/8, VT)); // Store the incremented VAList to the legalized pointer @@ -602,7 +602,7 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) { case ISD::VASTART: { // vastart just stores the address of the VarArgsFrameIndex slot into the // memory location argument. - SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64); + SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64); const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0); } @@ -610,5 +610,5 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) { case ISD::RETURNADDR: break; case ISD::FRAMEADDR: break; } - return SDOperand(); + return SDValue(); } diff --git a/lib/Target/IA64/IA64ISelLowering.h b/lib/Target/IA64/IA64ISelLowering.h index 54f6c2e..b7508f7 100644 --- a/lib/Target/IA64/IA64ISelLowering.h +++ b/lib/Target/IA64/IA64ISelLowering.h @@ -49,24 +49,24 @@ namespace llvm { const char *getTargetNodeName(unsigned Opcode) const; /// getSetCCResultType: return ISD::SETCC's result type. - virtual MVT getSetCCResultType(const SDOperand &) const; + virtual MVT getSetCCResultType(const SDValue &) const; /// LowerArguments - This hook must be implemented to indicate how we should /// lower the arguments for the specified function, into the specified DAG. virtual void LowerArguments(Function &F, SelectionDAG &DAG, - SmallVectorImpl<SDOperand> &ArgValues); + SmallVectorImpl<SDValue> &ArgValues); /// LowerCallTo - This hook lowers an abstract call to a function into an /// actual call. - virtual std::pair<SDOperand, SDOperand> - LowerCallTo(SDOperand Chain, const Type *RetTy, + virtual std::pair<SDValue, SDValue> + LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt, bool isVarArg, unsigned CC, bool isTailCall, - SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG); + SDValue Callee, ArgListTy &Args, SelectionDAG &DAG); /// LowerOperation - for custom lowering specific ops /// (currently, only "ret void") - virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); + virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); }; } diff --git a/lib/Target/Mips/MipsISelDAGToDAG.cpp b/lib/Target/Mips/MipsISelDAGToDAG.cpp index 388f5be..f463d3a 100644 --- a/lib/Target/Mips/MipsISelDAGToDAG.cpp +++ b/lib/Target/Mips/MipsISelDAGToDAG.cpp @@ -78,17 +78,17 @@ private: // Include the pieces autogenerated from the target description. #include "MipsGenDAGISel.inc" - SDOperand getGlobalBaseReg(); - SDNode *Select(SDOperand N); + SDValue getGlobalBaseReg(); + SDNode *Select(SDValue N); // Complex Pattern. - bool SelectAddr(SDOperand Op, SDOperand N, - SDOperand &Base, SDOperand &Offset); + bool SelectAddr(SDValue Op, SDValue N, + SDValue &Base, SDValue &Offset); // getI32Imm - Return a target constant with the specified // value, of type i32. - inline SDOperand getI32Imm(unsigned Imm) { + inline SDValue getI32Imm(unsigned Imm) { return CurDAG->getTargetConstant(Imm, MVT::i32); } @@ -124,7 +124,7 @@ InstructionSelect(SelectionDAG &SD) /// getGlobalBaseReg - Output the instructions required to put the /// GOT address into a register. -SDOperand MipsDAGToDAGISel::getGlobalBaseReg() { +SDValue MipsDAGToDAGISel::getGlobalBaseReg() { MachineFunction* MF = BB->getParent(); unsigned GP = 0; for(MachineRegisterInfo::livein_iterator ii = MF->getRegInfo().livein_begin(), @@ -141,7 +141,7 @@ SDOperand MipsDAGToDAGISel::getGlobalBaseReg() { /// ComplexPattern used on MipsInstrInfo /// Used on Mips Load/Store instructions bool MipsDAGToDAGISel:: -SelectAddr(SDOperand Op, SDOperand Addr, SDOperand &Offset, SDOperand &Base) +SelectAddr(SDValue Op, SDValue Addr, SDValue &Offset, SDValue &Base) { // if Address is FI, get the TargetFrameIndex. if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) { @@ -191,7 +191,7 @@ SelectAddr(SDOperand Op, SDOperand Addr, SDOperand &Offset, SDOperand &Base) /// Select instructions not customized! Used for /// expanded, promoted and normal instructions SDNode* MipsDAGToDAGISel:: -Select(SDOperand N) +Select(SDValue N) { SDNode *Node = N.Val; unsigned Opcode = Node->getOpcode(); @@ -225,7 +225,7 @@ Select(SDOperand N) case ISD::SUBE: case ISD::ADDE: { - SDOperand InFlag = Node->getOperand(2), CmpLHS; + SDValue InFlag = Node->getOperand(2), CmpLHS; unsigned Opc = InFlag.getOpcode(), MOp; assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) || @@ -240,20 +240,20 @@ Select(SDOperand N) MOp = Mips::SUBu; } - SDOperand Ops[] = { CmpLHS, InFlag.getOperand(1) }; + SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) }; - SDOperand LHS = Node->getOperand(0); - SDOperand RHS = Node->getOperand(1); + SDValue LHS = Node->getOperand(0); + SDValue RHS = Node->getOperand(1); AddToISelQueue(LHS); AddToISelQueue(RHS); MVT VT = LHS.getValueType(); SDNode *Carry = CurDAG->getTargetNode(Mips::SLTu, VT, Ops, 2); SDNode *AddCarry = CurDAG->getTargetNode(Mips::ADDu, VT, - SDOperand(Carry,0), RHS); + SDValue(Carry,0), RHS); return CurDAG->SelectNodeTo(N.Val, MOp, VT, MVT::Flag, - LHS, SDOperand(AddCarry,0)); + LHS, SDValue(AddCarry,0)); } /// Mul/Div with two results @@ -261,8 +261,8 @@ Select(SDOperand N) case ISD::UDIVREM: case ISD::SMUL_LOHI: case ISD::UMUL_LOHI: { - SDOperand Op1 = Node->getOperand(0); - SDOperand Op2 = Node->getOperand(1); + SDValue Op1 = Node->getOperand(0); + SDValue Op2 = Node->getOperand(1); AddToISelQueue(Op1); AddToISelQueue(Op2); @@ -274,17 +274,17 @@ Select(SDOperand N) SDNode *Node = CurDAG->getTargetNode(Op, MVT::Flag, Op1, Op2); - SDOperand InFlag = SDOperand(Node, 0); + SDValue InFlag = SDValue(Node, 0); SDNode *Lo = CurDAG->getTargetNode(Mips::MFLO, MVT::i32, MVT::Flag, InFlag); - InFlag = SDOperand(Lo,1); + InFlag = SDValue(Lo,1); SDNode *Hi = CurDAG->getTargetNode(Mips::MFHI, MVT::i32, InFlag); if (!N.getValue(0).use_empty()) - ReplaceUses(N.getValue(0), SDOperand(Lo,0)); + ReplaceUses(N.getValue(0), SDValue(Lo,0)); if (!N.getValue(1).use_empty()) - ReplaceUses(N.getValue(1), SDOperand(Hi,0)); + ReplaceUses(N.getValue(1), SDValue(Hi,0)); return NULL; } @@ -293,15 +293,15 @@ Select(SDOperand N) case ISD::MUL: case ISD::MULHS: case ISD::MULHU: { - SDOperand MulOp1 = Node->getOperand(0); - SDOperand MulOp2 = Node->getOperand(1); + SDValue MulOp1 = Node->getOperand(0); + SDValue MulOp2 = Node->getOperand(1); AddToISelQueue(MulOp1); AddToISelQueue(MulOp2); unsigned MulOp = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT); SDNode *MulNode = CurDAG->getTargetNode(MulOp, MVT::Flag, MulOp1, MulOp2); - SDOperand InFlag = SDOperand(MulNode, 0); + SDValue InFlag = SDValue(MulNode, 0); if (MulOp == ISD::MUL) return CurDAG->getTargetNode(Mips::MFLO, MVT::i32, InFlag); @@ -314,8 +314,8 @@ Select(SDOperand N) case ISD::UREM: case ISD::SDIV: case ISD::UDIV: { - SDOperand Op1 = Node->getOperand(0); - SDOperand Op2 = Node->getOperand(1); + SDValue Op1 = Node->getOperand(0); + SDValue Op2 = Node->getOperand(1); AddToISelQueue(Op1); AddToISelQueue(Op2); @@ -329,13 +329,13 @@ Select(SDOperand N) } SDNode *Node = CurDAG->getTargetNode(Op, MVT::Flag, Op1, Op2); - SDOperand InFlag = SDOperand(Node, 0); + SDValue InFlag = SDValue(Node, 0); return CurDAG->getTargetNode(MOp, MVT::i32, InFlag); } // Get target GOT address. case ISD::GLOBAL_OFFSET_TABLE: { - SDOperand Result = getGlobalBaseReg(); + SDValue Result = getGlobalBaseReg(); ReplaceUses(N, Result); return NULL; } @@ -347,21 +347,21 @@ Select(SDOperand N) case MipsISD::JmpLink: { if (TM.getRelocationModel() == Reloc::PIC_) { //bool isCodeLarge = (TM.getCodeModel() == CodeModel::Large); - SDOperand Chain = Node->getOperand(0); - SDOperand Callee = Node->getOperand(1); + SDValue Chain = Node->getOperand(0); + SDValue Callee = Node->getOperand(1); AddToISelQueue(Chain); - SDOperand T9Reg = CurDAG->getRegister(Mips::T9, MVT::i32); - SDOperand InFlag(0, 0); + SDValue T9Reg = CurDAG->getRegister(Mips::T9, MVT::i32); + SDValue InFlag(0, 0); if ( (isa<GlobalAddressSDNode>(Callee)) || (isa<ExternalSymbolSDNode>(Callee)) ) { /// Direct call for global addresses and external symbols - SDOperand GPReg = CurDAG->getRegister(Mips::GP, MVT::i32); + SDValue GPReg = CurDAG->getRegister(Mips::GP, MVT::i32); // Use load to get GOT target - SDOperand Ops[] = { Callee, GPReg, Chain }; - SDOperand Load = SDOperand(CurDAG->getTargetNode(Mips::LW, MVT::i32, + SDValue Ops[] = { Callee, GPReg, Chain }; + SDValue Load = SDValue(CurDAG->getTargetNode(Mips::LW, MVT::i32, MVT::Other, Ops, 3), 0); Chain = Load.getValue(1); AddToISelQueue(Chain); @@ -377,10 +377,10 @@ Select(SDOperand N) // Emit Jump and Link Register SDNode *ResNode = CurDAG->getTargetNode(Mips::JALR, MVT::Other, MVT::Flag, T9Reg, Chain); - Chain = SDOperand(ResNode, 0); - InFlag = SDOperand(ResNode, 1); - ReplaceUses(SDOperand(Node, 0), Chain); - ReplaceUses(SDOperand(Node, 1), InFlag); + Chain = SDValue(ResNode, 0); + InFlag = SDValue(ResNode, 1); + ReplaceUses(SDValue(Node, 0), Chain); + ReplaceUses(SDValue(Node, 1), InFlag); return ResNode; } } diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp index d6e5ecc..0ba62b3 100644 --- a/lib/Target/Mips/MipsISelLowering.cpp +++ b/lib/Target/Mips/MipsISelLowering.cpp @@ -132,13 +132,13 @@ MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM) } -MVT MipsTargetLowering::getSetCCResultType(const SDOperand &) const { +MVT MipsTargetLowering::getSetCCResultType(const SDValue &) const { return MVT::i32; } -SDOperand MipsTargetLowering:: -LowerOperation(SDOperand Op, SelectionDAG &DAG) +SDValue MipsTargetLowering:: +LowerOperation(SDValue Op, SelectionDAG &DAG) { switch (Op.getOpcode()) { @@ -151,7 +151,7 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) case ISD::ConstantPool: return LowerConstantPool(Op, DAG); case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); } - return SDOperand(); + return SDValue(); } MachineBasicBlock * @@ -268,105 +268,105 @@ bool MipsTargetLowering::IsGlobalInSmallSection(GlobalValue *GV) //===----------------------------------------------------------------------===// // Misc Lower Operation implementation //===----------------------------------------------------------------------===// -SDOperand MipsTargetLowering:: -LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) +SDValue MipsTargetLowering:: +LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) { GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); - SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32); + SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32); if (!Subtarget->hasABICall()) { if (isa<Function>(GV)) return GA; const MVT *VTs = DAG.getNodeValueTypes(MVT::i32); - SDOperand Ops[] = { GA }; + SDValue Ops[] = { GA }; if (IsGlobalInSmallSection(GV)) { // %gp_rel relocation - SDOperand GPRelNode = DAG.getNode(MipsISD::GPRel, VTs, 1, Ops, 1); - SDOperand GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i32); + SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, VTs, 1, Ops, 1); + SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i32); return DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode); } // %hi/%lo relocation - SDOperand HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1); - SDOperand Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA); + SDValue HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1); + SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA); return DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo); } else { // Abicall relocations, TODO: make this cleaner. - SDOperand ResNode = DAG.getLoad(MVT::i32, DAG.getEntryNode(), GA, NULL, 0); + SDValue ResNode = DAG.getLoad(MVT::i32, DAG.getEntryNode(), GA, NULL, 0); // On functions and global targets not internal linked only // a load from got/GP is necessary for PIC to work. if (!GV->hasInternalLinkage() || isa<Function>(GV)) return ResNode; - SDOperand Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA); + SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA); return DAG.getNode(ISD::ADD, MVT::i32, ResNode, Lo); } assert(0 && "Dont know how to handle GlobalAddress"); - return SDOperand(0,0); + return SDValue(0,0); } -SDOperand MipsTargetLowering:: -LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) +SDValue MipsTargetLowering:: +LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) { assert(0 && "TLS not implemented for MIPS."); - return SDOperand(); // Not reached + return SDValue(); // Not reached } -SDOperand MipsTargetLowering:: -LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) +SDValue MipsTargetLowering:: +LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { - SDOperand LHS = Op.getOperand(0); - SDOperand RHS = Op.getOperand(1); - SDOperand True = Op.getOperand(2); - SDOperand False = Op.getOperand(3); - SDOperand CC = Op.getOperand(4); + SDValue LHS = Op.getOperand(0); + SDValue RHS = Op.getOperand(1); + SDValue True = Op.getOperand(2); + SDValue False = Op.getOperand(3); + SDValue CC = Op.getOperand(4); const MVT *VTs = DAG.getNodeValueTypes(MVT::i32); - SDOperand Ops[] = { LHS, RHS, CC }; - SDOperand SetCCRes = DAG.getNode(ISD::SETCC, VTs, 1, Ops, 3); + SDValue Ops[] = { LHS, RHS, CC }; + SDValue SetCCRes = DAG.getNode(ISD::SETCC, VTs, 1, Ops, 3); return DAG.getNode(MipsISD::SelectCC, True.getValueType(), SetCCRes, True, False); } -SDOperand MipsTargetLowering:: -LowerJumpTable(SDOperand Op, SelectionDAG &DAG) +SDValue MipsTargetLowering:: +LowerJumpTable(SDValue Op, SelectionDAG &DAG) { - SDOperand ResNode; - SDOperand HiPart; + SDValue ResNode; + SDValue HiPart; MVT PtrVT = Op.getValueType(); JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); - SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); + SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { const MVT *VTs = DAG.getNodeValueTypes(MVT::i32); - SDOperand Ops[] = { JTI }; + SDValue Ops[] = { JTI }; HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1); } else // Emit Load from Global Pointer HiPart = DAG.getLoad(MVT::i32, DAG.getEntryNode(), JTI, NULL, 0); - SDOperand Lo = DAG.getNode(MipsISD::Lo, MVT::i32, JTI); + SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, JTI); ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo); return ResNode; } -SDOperand MipsTargetLowering:: -LowerConstantPool(SDOperand Op, SelectionDAG &DAG) +SDValue MipsTargetLowering:: +LowerConstantPool(SDValue Op, SelectionDAG &DAG) { - SDOperand ResNode; + SDValue ResNode; ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); Constant *C = N->getConstVal(); - SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment()); + SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment()); // gp_rel relocation if (!Subtarget->hasABICall() && IsInSmallSection(getTargetData()->getABITypeSize(C->getType()))) { - SDOperand GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP); - SDOperand GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i32); + SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP); + SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i32); ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode); } else { // %hi/%lo relocation - SDOperand HiPart = DAG.getNode(MipsISD::Hi, MVT::i32, CP); - SDOperand Lo = DAG.getNode(MipsISD::Lo, MVT::i32, CP); + SDValue HiPart = DAG.getNode(MipsISD::Hi, MVT::i32, CP); + SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, CP); ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo); } @@ -391,8 +391,8 @@ LowerConstantPool(SDOperand Op, SelectionDAG &DAG) //===----------------------------------------------------------------------===// /// Mips custom CALL implementation -SDOperand MipsTargetLowering:: -LowerCALL(SDOperand Op, SelectionDAG &DAG) +SDValue MipsTargetLowering:: +LowerCALL(SDValue Op, SelectionDAG &DAG) { unsigned CallingConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); @@ -410,13 +410,13 @@ LowerCALL(SDOperand Op, SelectionDAG &DAG) /// regs to (physical regs)/(stack frame), CALLSEQ_START and /// CALLSEQ_END are emitted. /// TODO: isVarArg, isTailCall. -SDOperand MipsTargetLowering:: -LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC) +SDValue MipsTargetLowering:: +LowerCCCCallTo(SDValue Op, SelectionDAG &DAG, unsigned CC) { MachineFunction &MF = DAG.getMachineFunction(); - SDOperand Chain = Op.getOperand(0); - SDOperand Callee = Op.getOperand(4); + SDValue Chain = Op.getOperand(0); + SDValue Callee = Op.getOperand(4); bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; MachineFrameInfo *MFI = MF.getFrameInfo(); @@ -440,8 +440,8 @@ LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC) getPointerTy())); // With EABI is it possible to have 16 args on registers. - SmallVector<std::pair<unsigned, SDOperand>, 16> RegsToPass; - SmallVector<SDOperand, 8> MemOpChains; + SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass; + SmallVector<SDValue, 8> MemOpChains; // First/LastArgStackLoc contains the first/last // "at stack" argument location. @@ -453,7 +453,7 @@ LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC) CCValAssign &VA = ArgLocs[i]; // Arguments start after the 5 first operands of ISD::CALL - SDOperand Arg = Op.getOperand(5+2*VA.getValNo()); + SDValue Arg = Op.getOperand(5+2*VA.getValNo()); // Promote the value if needed. switch (VA.getLocInfo()) { @@ -488,7 +488,7 @@ LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC) int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8, LastArgStackLoc); - SDOperand PtrOff = DAG.getFrameIndex(FI,getPointerTy()); + SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy()); // emit ISD::STORE whichs stores the // parameter value to a stack Location @@ -505,7 +505,7 @@ LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC) // chain and flag operands which copy the outgoing args into registers. // The InFlag in necessary since all emited instructions must be // stuck together. - SDOperand InFlag; + SDValue InFlag; for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, InFlag); @@ -526,7 +526,7 @@ LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC) // // Returns a chain & a flag for retval copy to use. SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); - SmallVector<SDOperand, 8> Ops; + SmallVector<SDValue, 8> Ops; Ops.push_back(Chain); Ops.push_back(Callee); @@ -570,17 +570,17 @@ LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC) // Reload GP value. FI = MipsFI->getGPFI(); - SDOperand FIN = DAG.getFrameIndex(FI,getPointerTy()); - SDOperand GPLoad = DAG.getLoad(MVT::i32, Chain, FIN, NULL, 0); + SDValue FIN = DAG.getFrameIndex(FI,getPointerTy()); + SDValue GPLoad = DAG.getLoad(MVT::i32, Chain, FIN, NULL, 0); Chain = GPLoad.getValue(1); Chain = DAG.getCopyToReg(Chain, DAG.getRegister(Mips::GP, MVT::i32), - GPLoad, SDOperand(0,0)); + GPLoad, SDValue(0,0)); InFlag = Chain.getValue(1); } // Handle result values, copying them out of physregs into vregs that we // return. - return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo); + return SDValue(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo); } /// LowerCallResult - Lower the result values of an ISD::CALL into the @@ -589,7 +589,7 @@ LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC) /// being lowered. Returns a SDNode with the same number of values as the /// ISD::CALL. SDNode *MipsTargetLowering:: -LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall, +LowerCallResult(SDValue Chain, SDValue InFlag, SDNode *TheCall, unsigned CallingConv, SelectionDAG &DAG) { bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0; @@ -599,7 +599,7 @@ LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall, CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs); CCInfo.AnalyzeCallResult(TheCall, RetCC_Mips); - SmallVector<SDOperand, 8> ResultVals; + SmallVector<SDValue, 8> ResultVals; // Copy all of the result registers out of their specified physreg. for (unsigned i = 0; i != RVLocs.size(); ++i) { @@ -621,8 +621,8 @@ LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall, //===----------------------------------------------------------------------===// /// Mips custom FORMAL_ARGUMENTS implementation -SDOperand MipsTargetLowering:: -LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) +SDValue MipsTargetLowering:: +LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) { unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); switch(CC) @@ -638,10 +638,10 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) /// virtual registers and generate load operations for /// arguments places on the stack. /// TODO: isVarArg -SDOperand MipsTargetLowering:: -LowerCCCArguments(SDOperand Op, SelectionDAG &DAG) +SDValue MipsTargetLowering:: +LowerCCCArguments(SDValue Op, SelectionDAG &DAG) { - SDOperand Root = Op.getOperand(0); + SDValue Root = Op.getOperand(0); MachineFunction &MF = DAG.getMachineFunction(); MachineFrameInfo *MFI = MF.getFrameInfo(); MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); @@ -659,8 +659,8 @@ LowerCCCArguments(SDOperand Op, SelectionDAG &DAG) CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs); CCInfo.AnalyzeFormalArguments(Op.Val, CC_Mips); - SmallVector<SDOperand, 16> ArgValues; - SDOperand StackPtr; + SmallVector<SDValue, 16> ArgValues; + SDValue StackPtr; unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16); @@ -689,7 +689,7 @@ LowerCCCArguments(SDOperand Op, SelectionDAG &DAG) // Transform the arguments stored on // physical registers into virtual ones unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC); - SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT); + SDValue ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT); // If this is an 8 or 16-bit value, it is really passed promoted // to 32 bits. Insert an assert[sz]ext to capture this, then @@ -722,7 +722,7 @@ LowerCCCArguments(SDOperand Op, SelectionDAG &DAG) // Arguments are always 32-bit. int FI = MFI->CreateFixedObject(4, 0); MipsFI->recordStoreVarArgsFI(FI, -(4+(i*4))); - SDOperand PtrOff = DAG.getFrameIndex(FI, getPointerTy()); + SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy()); // emit ISD::STORE whichs stores the // parameter value to a stack Location @@ -748,7 +748,7 @@ LowerCCCArguments(SDOperand Op, SelectionDAG &DAG) (FirstStackArgLoc + VA.getLocMemOffset()))); // Create load nodes to retrieve arguments from the stack - SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy()); + SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0)); } } @@ -762,7 +762,7 @@ LowerCCCArguments(SDOperand Op, SelectionDAG &DAG) Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32)); MipsFI->setSRetReturnReg(Reg); } - SDOperand Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]); + SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]); Root = DAG.getNode(ISD::TokenFactor, MVT::Other, Copy, Root); } @@ -777,8 +777,8 @@ LowerCCCArguments(SDOperand Op, SelectionDAG &DAG) // Return Value Calling Convention Implementation //===----------------------------------------------------------------------===// -SDOperand MipsTargetLowering:: -LowerRET(SDOperand Op, SelectionDAG &DAG) +SDValue MipsTargetLowering:: +LowerRET(SDValue Op, SelectionDAG &DAG) { // CCValAssign - represent the assignment of // the return value to a location @@ -801,8 +801,8 @@ LowerRET(SDOperand Op, SelectionDAG &DAG) } // The chain is always operand #0 - SDOperand Chain = Op.getOperand(0); - SDOperand Flag; + SDValue Chain = Op.getOperand(0); + SDValue Flag; // Copy the result values into the output registers. for (unsigned i = 0; i != RVLocs.size(); ++i) { @@ -829,7 +829,7 @@ LowerRET(SDOperand Op, SelectionDAG &DAG) if (!Reg) assert(0 && "sret virtual register not created in the entry block"); - SDOperand Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy()); + SDValue Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy()); Chain = DAG.getCopyToReg(Chain, Mips::V0, Val, Flag); Flag = Chain.getValue(1); diff --git a/lib/Target/Mips/MipsISelLowering.h b/lib/Target/Mips/MipsISelLowering.h index 9c9a455..ccc7981 100644 --- a/lib/Target/Mips/MipsISelLowering.h +++ b/lib/Target/Mips/MipsISelLowering.h @@ -66,36 +66,36 @@ namespace llvm { explicit MipsTargetLowering(MipsTargetMachine &TM); /// LowerOperation - Provide custom lowering hooks for some operations. - virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); + virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); /// getTargetNodeName - This method returns the name of a target specific // DAG node. virtual const char *getTargetNodeName(unsigned Opcode) const; /// getSetCCResultType - get the ISD::SETCC result ValueType - MVT getSetCCResultType(const SDOperand &) const; + MVT getSetCCResultType(const SDValue &) const; private: // Subtarget Info const MipsSubtarget *Subtarget; // Lower Operand helpers - SDOperand LowerCCCArguments(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC); - SDNode *LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode*TheCall, + SDValue LowerCCCArguments(SDValue Op, SelectionDAG &DAG); + SDValue LowerCCCCallTo(SDValue Op, SelectionDAG &DAG, unsigned CC); + SDNode *LowerCallResult(SDValue Chain, SDValue InFlag, SDNode*TheCall, unsigned CallingConv, SelectionDAG &DAG); bool IsGlobalInSmallSection(GlobalValue *GV); bool IsInSmallSection(unsigned Size); // Lower Operand specifics - SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG); + SDValue LowerRET(SDValue Op, SelectionDAG &DAG); + SDValue LowerCALL(SDValue Op, SelectionDAG &DAG); + SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG); + SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG); + SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG); + SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG); + SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG); + SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG); virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB); diff --git a/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp b/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp index 509ba83..ba002bd 100644 --- a/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp +++ b/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp @@ -71,20 +71,20 @@ private: // Include the pieces autogenerated from the target description. #include "PIC16GenDAGISel.inc" - SDNode *Select(SDOperand N); + SDNode *Select(SDValue N); // Select addressing mode. currently assume base + offset addr mode. - bool SelectAM(SDOperand Op, SDOperand N, SDOperand &Base, SDOperand &Offset); - bool SelectDirectAM(SDOperand Op, SDOperand N, SDOperand &Base, - SDOperand &Offset); - bool StoreInDirectAM(SDOperand Op, SDOperand N, SDOperand &fsr); - bool LoadFSR(SDOperand Op, SDOperand N, SDOperand &Base, SDOperand &Offset); - bool LoadNothing(SDOperand Op, SDOperand N, SDOperand &Base, - SDOperand &Offset); + bool SelectAM(SDValue Op, SDValue N, SDValue &Base, SDValue &Offset); + bool SelectDirectAM(SDValue Op, SDValue N, SDValue &Base, + SDValue &Offset); + bool StoreInDirectAM(SDValue Op, SDValue N, SDValue &fsr); + bool LoadFSR(SDValue Op, SDValue N, SDValue &Base, SDValue &Offset); + bool LoadNothing(SDValue Op, SDValue N, SDValue &Base, + SDValue &Offset); // getI8Imm - Return a target constant with the specified // value, of type i8. - inline SDOperand getI8Imm(unsigned Imm) { + inline SDValue getI8Imm(unsigned Imm) { return CurDAG->getTargetConstant(Imm, MVT::i8); } @@ -118,7 +118,7 @@ void PIC16DAGToDAGISel::InstructionSelect(SelectionDAG &SD) bool PIC16DAGToDAGISel:: -SelectDirectAM (SDOperand Op, SDOperand N, SDOperand &Base, SDOperand &Offset) +SelectDirectAM (SDValue Op, SDValue N, SDValue &Base, SDValue &Offset) { GlobalAddressSDNode *GA; ConstantSDNode *GC; @@ -160,7 +160,7 @@ SelectDirectAM (SDOperand Op, SDOperand N, SDOperand &Base, SDOperand &Offset) // FIXME: must also account for preinc/predec/postinc/postdec. bool PIC16DAGToDAGISel:: -StoreInDirectAM (SDOperand Op, SDOperand N, SDOperand &fsr) +StoreInDirectAM (SDValue Op, SDValue N, SDValue &fsr) { RegisterSDNode *Reg; if (N.getOpcode() == ISD::LOAD) { @@ -186,7 +186,7 @@ StoreInDirectAM (SDOperand Op, SDOperand N, SDOperand &fsr) } bool PIC16DAGToDAGISel:: -LoadFSR (SDOperand Op, SDOperand N, SDOperand &Base, SDOperand &Offset) +LoadFSR (SDValue Op, SDValue N, SDValue &Base, SDValue &Offset) { GlobalAddressSDNode *GA; @@ -207,7 +207,7 @@ LoadFSR (SDOperand Op, SDOperand N, SDOperand &Base, SDOperand &Offset) // LoadNothing - Don't thake this seriously, it will change. bool PIC16DAGToDAGISel:: -LoadNothing (SDOperand Op, SDOperand N, SDOperand &Base, SDOperand &Offset) +LoadNothing (SDValue Op, SDValue N, SDValue &Base, SDValue &Offset) { GlobalAddressSDNode *GA; if (N.getOpcode() == ISD::GlobalAddress) { @@ -225,7 +225,7 @@ LoadNothing (SDOperand Op, SDOperand N, SDOperand &Base, SDOperand &Offset) /// Select - Select instructions not customized! Used for /// expanded, promoted and normal instructions. -SDNode* PIC16DAGToDAGISel::Select(SDOperand N) +SDNode* PIC16DAGToDAGISel::Select(SDValue N) { SDNode *Node = N.Val; unsigned Opcode = Node->getOpcode(); diff --git a/lib/Target/PIC16/PIC16ISelLowering.cpp b/lib/Target/PIC16/PIC16ISelLowering.cpp index 78936b8..fe22f2e 100644 --- a/lib/Target/PIC16/PIC16ISelLowering.cpp +++ b/lib/Target/PIC16/PIC16ISelLowering.cpp @@ -159,7 +159,7 @@ PIC16TargetLowering(PIC16TargetMachine &TM): TargetLowering(TM) } -SDOperand PIC16TargetLowering:: LowerOperation(SDOperand Op, SelectionDAG &DAG) +SDValue PIC16TargetLowering:: LowerOperation(SDValue Op, SelectionDAG &DAG) { SDVTList VTList16 = DAG.getVTList(MVT::i16, MVT::i16, MVT::Other); switch (Op.getOpcode()) { @@ -195,7 +195,7 @@ SDOperand PIC16TargetLowering:: LowerOperation(SDOperand Op, SelectionDAG &DAG) DOUT << "==== lowering BR_CC\n"; return LowerBR_CC(Op, DAG); } // end switch. - return SDOperand(); + return SDValue(); } @@ -203,21 +203,21 @@ SDOperand PIC16TargetLowering:: LowerOperation(SDOperand Op, SelectionDAG &DAG) // Lower helper functions //===----------------------------------------------------------------------===// -SDOperand PIC16TargetLowering::LowerBR_CC(SDOperand Op, SelectionDAG &DAG) +SDValue PIC16TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) { MVT VT = Op.getValueType(); - SDOperand Chain = Op.getOperand(0); + SDValue Chain = Op.getOperand(0); ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); - SDOperand LHS = Op.getOperand(2); - SDOperand RHS = Op.getOperand(3); - SDOperand JumpVal = Op.getOperand(4); - SDOperand Result; + SDValue LHS = Op.getOperand(2); + SDValue RHS = Op.getOperand(3); + SDValue JumpVal = Op.getOperand(4); + SDValue Result; unsigned cmpOpcode; unsigned branchOpcode; - SDOperand branchOperand; + SDValue branchOperand; - SDOperand StatusReg = DAG.getRegister(PIC16::STATUSREG, MVT::i8); - SDOperand CPUReg = DAG.getRegister(PIC16::WREG, MVT::i8); + SDValue StatusReg = DAG.getRegister(PIC16::STATUSREG, MVT::i8); + SDValue CPUReg = DAG.getRegister(PIC16::WREG, MVT::i8); switch(CC) { default: assert(0 && "This condition code is not handled yet!!"); @@ -263,7 +263,7 @@ SDOperand PIC16TargetLowering::LowerBR_CC(SDOperand Op, SelectionDAG &DAG) } // End of Switch SDVTList VTList = DAG.getVTList(MVT::i8, MVT::Flag); - SDOperand CmpValue = DAG.getNode(cmpOpcode, VTList, LHS, RHS).getValue(1); + SDValue CmpValue = DAG.getNode(cmpOpcode, VTList, LHS, RHS).getValue(1); Result = DAG.getNode(branchOpcode, VT, Chain, JumpVal, branchOperand, StatusReg, CmpValue); return Result; @@ -276,23 +276,23 @@ SDOperand PIC16TargetLowering::LowerBR_CC(SDOperand Op, SelectionDAG &DAG) // LowerGlobalAddress - Create a constant pool entry for global value // and wrap it in a wrapper node. -SDOperand -PIC16TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) +SDValue +PIC16TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) { MVT PtrVT = getPointerTy(); GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); GlobalValue *GV = GSDN->getGlobal(); // FIXME: for now only do the ram. - SDOperand CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2); - SDOperand CPBank = DAG.getNode(PIC16ISD::SetBank, MVT::i8, CPAddr); + SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2); + SDValue CPBank = DAG.getNode(PIC16ISD::SetBank, MVT::i8, CPAddr); CPAddr = DAG.getNode(PIC16ISD::Wrapper, MVT::i8, CPAddr,CPBank); return CPAddr; } -SDOperand -PIC16TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) +SDValue +PIC16TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) { switch(Op.getNumOperands()) { default: @@ -300,12 +300,12 @@ PIC16TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) abort(); case 1: - return SDOperand(); // ret void is legal + return SDValue(); // ret void is legal } } -SDOperand -PIC16TargetLowering::LowerFrameIndex(SDOperand N, SelectionDAG &DAG) +SDValue +PIC16TargetLowering::LowerFrameIndex(SDValue N, SelectionDAG &DAG) { if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N)) { return DAG.getTargetFrameIndex(FIN->getIndex(), MVT::i32); @@ -314,17 +314,17 @@ PIC16TargetLowering::LowerFrameIndex(SDOperand N, SelectionDAG &DAG) return N; } -SDOperand +SDValue PIC16TargetLowering::LowerLOAD(SDNode *N, SelectionDAG &DAG, DAGCombinerInfo &DCI) const { - SDOperand Outs[2]; - SDOperand TF; //TokenFactor - SDOperand OutChains[2]; - SDOperand Chain = N->getOperand(0); - SDOperand Src = N->getOperand(1); - SDOperand retVal; + SDValue Outs[2]; + SDValue TF; //TokenFactor + SDValue OutChains[2]; + SDValue Chain = N->getOperand(0); + SDValue Src = N->getOperand(1); + SDValue retVal; SDVTList VTList; // If this load is directly stored, replace the load value with the stored @@ -332,7 +332,7 @@ PIC16TargetLowering::LowerLOAD(SDNode *N, // FIXME: Handle store large -> read small portion. // FIXME: Handle TRUNCSTORE/LOADEXT LoadSDNode *LD = cast<LoadSDNode>(N); - SDOperand Ptr = LD->getBasePtr(); + SDValue Ptr = LD->getBasePtr(); if (LD->getExtensionType() == ISD::NON_EXTLOAD) { if (ISD::isNON_TRUNCStore(Chain.Val)) { StoreSDNode *PrevST = cast<StoreSDNode>(Chain); @@ -343,9 +343,9 @@ PIC16TargetLowering::LowerLOAD(SDNode *N, } if (N->getValueType(0) != MVT::i16) - return SDOperand(); + return SDValue(); - SDOperand toWorklist; + SDValue toWorklist; Outs[0] = DAG.getLoad(MVT::i8, Chain, Src, NULL, 0); toWorklist = DAG.getNode(ISD::ADD, MVT::i16, Src, DAG.getConstant(1, MVT::i16)); @@ -367,17 +367,17 @@ PIC16TargetLowering::LowerLOAD(SDNode *N, return retVal; } -SDOperand +SDValue PIC16TargetLowering::LowerADDSUB(SDNode *N, SelectionDAG &DAG, DAGCombinerInfo &DCI) const { bool changed = false; int i; - SDOperand LoOps[3], HiOps[3]; - SDOperand OutOps[3]; // [0]:left, [1]:right, [2]:carry - SDOperand InOp[2]; - SDOperand retVal; - SDOperand as1,as2; + SDValue LoOps[3], HiOps[3]; + SDValue OutOps[3]; // [0]:left, [1]:right, [2]:carry + SDValue InOp[2]; + SDValue retVal; + SDValue as1,as2; SDVTList VTList; unsigned AS = 0, ASE = 0, ASC=0; @@ -427,7 +427,7 @@ PIC16TargetLowering::LowerADDSUB(SDNode *N, SelectionDAG &DAG, for (i = 0; i < 2; i++) { if (InOp[i].getOpcode() == ISD::GlobalAddress) { // We don't want to lower subs/adds with global address yet. - return SDOperand(); + return SDValue(); } else if (InOp[i].getOpcode() == ISD::Constant) { changed = true; @@ -443,7 +443,7 @@ PIC16TargetLowering::LowerADDSUB(SDNode *N, SelectionDAG &DAG, changed = true; // LowerLOAD returns a Package node or it may combine and return // anything else. - SDOperand lowered = LowerLOAD(InOp[i].Val, DAG, DCI); + SDValue lowered = LowerLOAD(InOp[i].Val, DAG, DCI); // So If LowerLOAD returns something other than Package, // then just call ADD again. @@ -462,7 +462,7 @@ PIC16TargetLowering::LowerADDSUB(SDNode *N, SelectionDAG &DAG, changed = true; // Must call LowerADDSUB recursively here, // LowerADDSUB returns a Package node. - SDOperand lowered = LowerADDSUB(InOp[i].Val, DAG, DCI); + SDValue lowered = LowerADDSUB(InOp[i].Val, DAG, DCI); LoOps[i] = lowered.getOperand(0); HiOps[i] = lowered.getOperand(1); @@ -533,11 +533,11 @@ PIC16TargetLowering::LowerADDSUB(SDNode *N, SelectionDAG &DAG, //===----------------------------------------------------------------------===// // FORMAL_ARGUMENTS Calling Convention Implementation //===----------------------------------------------------------------------===// -SDOperand PIC16TargetLowering:: -LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) +SDValue PIC16TargetLowering:: +LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) { - SmallVector<SDOperand, 8> ArgValues; - SDOperand Root = Op.getOperand(0); + SmallVector<SDValue, 8> ArgValues; + SDValue Root = Op.getOperand(0); // Return the new list of results. // FIXME: Just copy right now. @@ -560,7 +560,7 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) // Target Optimization Hooks //===----------------------------------------------------------------------===// -SDOperand PIC16TargetLowering::PerformDAGCombine(SDNode *N, +SDValue PIC16TargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { int i; @@ -573,14 +573,14 @@ SDOperand PIC16TargetLowering::PerformDAGCombine(SDNode *N, case PIC16ISD::Package: DOUT << "==== combining PIC16ISD::Package\n"; - return SDOperand(); + return SDValue(); case ISD::ADD: case ISD::SUB: if ((N->getOperand(0).getOpcode() == ISD::GlobalAddress) || (N->getOperand(0).getOpcode() == ISD::FrameIndex)) { // Do not touch pointer adds. - return SDOperand (); + return SDValue (); } break; @@ -589,11 +589,11 @@ SDOperand PIC16TargetLowering::PerformDAGCombine(SDNode *N, case ISD::SUBE : case ISD::SUBC : if (N->getValueType(0) == MVT::i16) { - SDOperand retVal = LowerADDSUB(N, DAG,DCI); + SDValue retVal = LowerADDSUB(N, DAG,DCI); // LowerADDSUB has already combined the result, // so we just return nothing to avoid assertion failure from llvm // if N has been deleted already. - return SDOperand(); + return SDValue(); } else if (N->getValueType(0) == MVT::i8) { // Sanity check .... @@ -609,12 +609,12 @@ SDOperand PIC16TargetLowering::PerformDAGCombine(SDNode *N, // FIXME: split this large chunk of code. case ISD::STORE : { - SDOperand Chain = N->getOperand(0); - SDOperand Src = N->getOperand(1); - SDOperand Dest = N->getOperand(2); + SDValue Chain = N->getOperand(0); + SDValue Src = N->getOperand(1); + SDValue Dest = N->getOperand(2); unsigned int DstOff = 0; int NUM_STORES = 0; - SDOperand Stores[6]; + SDValue Stores[6]; // if source operand is expected to be extended to // some higher type then - remove this extension @@ -652,10 +652,10 @@ SDOperand PIC16TargetLowering::PerformDAGCombine(SDNode *N, //create direct addressing a = b Chain = Src.getOperand(0); for (i=0; i<NUM_STORES; i++) { - SDOperand ADN = DAG.getNode(ISD::ADD, MVT::i16, Src.getOperand(1), + SDValue ADN = DAG.getNode(ISD::ADD, MVT::i16, Src.getOperand(1), DAG.getConstant(DstOff, MVT::i16)); - SDOperand LDN = DAG.getLoad(MVT::i8, Chain, ADN, NULL, 0); - SDOperand DSTADDR = DAG.getNode(ISD::ADD, MVT::i16, Dest, + SDValue LDN = DAG.getLoad(MVT::i8, Chain, ADN, NULL, 0); + SDValue DSTADDR = DAG.getNode(ISD::ADD, MVT::i16, Dest, DAG.getConstant(DstOff, MVT::i16)); Stores[i] = DAG.getStore(Chain, LDN, DSTADDR, NULL, 0); Chain = Stores[i]; @@ -670,8 +670,8 @@ SDOperand PIC16TargetLowering::PerformDAGCombine(SDNode *N, //create direct addressing a = CONST CST = dyn_cast<ConstantSDNode>(Src); for (i = 0; i < NUM_STORES; i++) { - SDOperand CNST = DAG.getConstant(CST->getValue() >> i*8, MVT::i8); - SDOperand ADN = DAG.getNode(ISD::ADD, MVT::i16, Dest, + SDValue CNST = DAG.getConstant(CST->getValue() >> i*8, MVT::i8); + SDValue ADN = DAG.getNode(ISD::ADD, MVT::i16, Dest, DAG.getConstant(DstOff, MVT::i16)); Stores[i] = DAG.getStore(Chain, CNST, ADN, NULL, 0); Chain = Stores[i]; @@ -686,11 +686,11 @@ SDOperand PIC16TargetLowering::PerformDAGCombine(SDNode *N, // Create indirect addressing. CST = dyn_cast<ConstantSDNode>(Src); Chain = Dest.getOperand(0); - SDOperand Load; + SDValue Load; Load = DAG.getLoad(MVT::i16, Chain,Dest.getOperand(1), NULL, 0); Chain = Load.getValue(1); for (i=0; i<NUM_STORES; i++) { - SDOperand CNST = DAG.getConstant(CST->getValue() >> i*8, MVT::i8); + SDValue CNST = DAG.getConstant(CST->getValue() >> i*8, MVT::i8); Stores[i] = DAG.getStore(Chain, CNST, Load, NULL, 0); Chain = Stores[i]; DstOff += 1; @@ -701,11 +701,11 @@ SDOperand PIC16TargetLowering::PerformDAGCombine(SDNode *N, } else if (isa<LoadSDNode>(Dest) && isa<GlobalAddressSDNode>(Src)) { // GlobalAddressSDNode *GAD = dyn_cast<GlobalAddressSDNode>(Src); - return SDOperand(); + return SDValue(); } else if (Src.getOpcode() == PIC16ISD::Package) { StoreSDNode *st = dyn_cast<StoreSDNode>(N); - SDOperand toWorkList, retVal; + SDValue toWorkList, retVal; Chain = N->getOperand(0); if (st->isTruncatingStore()) { @@ -739,7 +739,7 @@ SDOperand PIC16TargetLowering::PerformDAGCombine(SDNode *N, case ISD::LOAD : { - SDOperand Ptr = N->getOperand(1); + SDValue Ptr = N->getOperand(1); if (Ptr.getOpcode() == PIC16ISD::Package) { assert (0 && "not implemented yet"); } @@ -747,20 +747,20 @@ SDOperand PIC16TargetLowering::PerformDAGCombine(SDNode *N, break; } // end switch. - return SDOperand(); + return SDValue(); } //===----------------------------------------------------------------------===// // Utility functions //===----------------------------------------------------------------------===// -const SDOperand *PIC16TargetLowering:: -findLoadi8(const SDOperand &Src, SelectionDAG &DAG) const +const SDValue *PIC16TargetLowering:: +findLoadi8(const SDValue &Src, SelectionDAG &DAG) const { unsigned int i; if ((Src.getOpcode() == ISD::LOAD) && (Src.getValueType() == MVT::i8)) return &Src; for (i=0; i<Src.getNumOperands(); i++) { - const SDOperand *retVal = findLoadi8(Src.getOperand(i),DAG); + const SDValue *retVal = findLoadi8(Src.getOperand(i),DAG); if (retVal) return retVal; } diff --git a/lib/Target/PIC16/PIC16ISelLowering.h b/lib/Target/PIC16/PIC16ISelLowering.h index 41650ee..c31d344 100644 --- a/lib/Target/PIC16/PIC16ISelLowering.h +++ b/lib/Target/PIC16/PIC16ISelLowering.h @@ -64,28 +64,28 @@ namespace llvm { explicit PIC16TargetLowering(PIC16TargetMachine &TM); /// LowerOperation - Provide custom lowering hooks for some operations. - virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); + virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); - SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerFrameIndex(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG); + SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG); + SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG); + SDValue LowerRET(SDValue Op, SelectionDAG &DAG); + SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG); + SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG); - SDOperand RemoveHiLo(SDNode *, SelectionDAG &DAG, + SDValue RemoveHiLo(SDNode *, SelectionDAG &DAG, DAGCombinerInfo &DCI) const; - SDOperand LowerADDSUB(SDNode *, SelectionDAG &DAG, + SDValue LowerADDSUB(SDNode *, SelectionDAG &DAG, DAGCombinerInfo &DCI) const; - SDOperand LowerLOAD(SDNode *, SelectionDAG &DAG, + SDValue LowerLOAD(SDNode *, SelectionDAG &DAG, DAGCombinerInfo &DCI) const; /// getTargetNodeName - This method returns the name of a target specific // DAG node. virtual const char *getTargetNodeName(unsigned Opcode) const; - virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; + virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; // utility function. - const SDOperand *findLoadi8(const SDOperand &Src, SelectionDAG &DAG) const; + const SDValue *findLoadi8(const SDValue &Src, SelectionDAG &DAG) const; }; } // namespace llvm diff --git a/lib/Target/PowerPC/PPCHazardRecognizers.cpp b/lib/Target/PowerPC/PPCHazardRecognizers.cpp index 717ce60..480e277 100644 --- a/lib/Target/PowerPC/PPCHazardRecognizers.cpp +++ b/lib/Target/PowerPC/PPCHazardRecognizers.cpp @@ -86,7 +86,7 @@ PPCHazardRecognizer970::GetInstrType(unsigned Opcode, /// isLoadOfStoredAddress - If we have a load from the previously stored pointer /// as indicated by StorePtr1/StorePtr2/StoreSize, return true. bool PPCHazardRecognizer970:: -isLoadOfStoredAddress(unsigned LoadSize, SDOperand Ptr1, SDOperand Ptr2) const { +isLoadOfStoredAddress(unsigned LoadSize, SDValue Ptr1, SDValue Ptr2) const { for (unsigned i = 0, e = NumStores; i != e; ++i) { // Handle exact and commuted addresses. if (Ptr1 == StorePtr1[i] && Ptr2 == StorePtr2[i]) diff --git a/lib/Target/PowerPC/PPCHazardRecognizers.h b/lib/Target/PowerPC/PPCHazardRecognizers.h index 8ec25ae..7ba2e6e 100644 --- a/lib/Target/PowerPC/PPCHazardRecognizers.h +++ b/lib/Target/PowerPC/PPCHazardRecognizers.h @@ -41,7 +41,7 @@ class PPCHazardRecognizer970 : public HazardRecognizer { // // This is null if we haven't seen a store yet. We keep track of both // operands of the store here, since we support [r+r] and [r+i] addressing. - SDOperand StorePtr1[4], StorePtr2[4]; + SDValue StorePtr1[4], StorePtr2[4]; unsigned StoreSize[4]; unsigned NumStores; @@ -64,7 +64,7 @@ private: bool &isLoad, bool &isStore); bool isLoadOfStoredAddress(unsigned LoadSize, - SDOperand Ptr1, SDOperand Ptr2) const; + SDValue Ptr1, SDValue Ptr2) const; }; } // end namespace llvm diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index fb27999..65ab4d2 100644 --- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -61,18 +61,18 @@ namespace { /// getI32Imm - Return a target constant with the specified value, of type /// i32. - inline SDOperand getI32Imm(unsigned Imm) { + inline SDValue getI32Imm(unsigned Imm) { return CurDAG->getTargetConstant(Imm, MVT::i32); } /// getI64Imm - Return a target constant with the specified value, of type /// i64. - inline SDOperand getI64Imm(uint64_t Imm) { + inline SDValue getI64Imm(uint64_t Imm) { return CurDAG->getTargetConstant(Imm, MVT::i64); } /// getSmallIPtrImm - Return a target constant of pointer type. - inline SDOperand getSmallIPtrImm(unsigned Imm) { + inline SDValue getSmallIPtrImm(unsigned Imm) { return CurDAG->getTargetConstant(Imm, PPCLowering.getPointerTy()); } @@ -94,25 +94,25 @@ namespace { // Select - Convert the specified operand from a target-independent to a // target-specific node if it hasn't already been changed. - SDNode *Select(SDOperand Op); + SDNode *Select(SDValue Op); SDNode *SelectBitfieldInsert(SDNode *N); /// SelectCC - Select a comparison of the specified values with the /// specified condition code, returning the CR# of the expression. - SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC); + SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC); /// SelectAddrImm - Returns true if the address N can be represented by /// a base register plus a signed 16-bit displacement [r+imm]. - bool SelectAddrImm(SDOperand Op, SDOperand N, SDOperand &Disp, - SDOperand &Base) { + bool SelectAddrImm(SDValue Op, SDValue N, SDValue &Disp, + SDValue &Base) { return PPCLowering.SelectAddressRegImm(N, Disp, Base, *CurDAG); } /// SelectAddrImmOffs - Return true if the operand is valid for a preinc /// immediate field. Because preinc imms have already been validated, just /// accept it. - bool SelectAddrImmOffs(SDOperand Op, SDOperand N, SDOperand &Out) const { + bool SelectAddrImmOffs(SDValue Op, SDValue N, SDValue &Out) const { Out = N; return true; } @@ -120,33 +120,33 @@ namespace { /// SelectAddrIdx - Given the specified addressed, check to see if it can be /// represented as an indexed [r+r] operation. Returns false if it can /// be represented by [r+imm], which are preferred. - bool SelectAddrIdx(SDOperand Op, SDOperand N, SDOperand &Base, - SDOperand &Index) { + bool SelectAddrIdx(SDValue Op, SDValue N, SDValue &Base, + SDValue &Index) { return PPCLowering.SelectAddressRegReg(N, Base, Index, *CurDAG); } /// SelectAddrIdxOnly - Given the specified addressed, force it to be /// represented as an indexed [r+r] operation. - bool SelectAddrIdxOnly(SDOperand Op, SDOperand N, SDOperand &Base, - SDOperand &Index) { + bool SelectAddrIdxOnly(SDValue Op, SDValue N, SDValue &Base, + SDValue &Index) { return PPCLowering.SelectAddressRegRegOnly(N, Base, Index, *CurDAG); } /// SelectAddrImmShift - Returns true if the address N can be represented by /// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable /// for use by STD and friends. - bool SelectAddrImmShift(SDOperand Op, SDOperand N, SDOperand &Disp, - SDOperand &Base) { + bool SelectAddrImmShift(SDValue Op, SDValue N, SDValue &Disp, + SDValue &Base) { return PPCLowering.SelectAddressRegImmShift(N, Disp, Base, *CurDAG); } /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for /// inline asm expressions. - virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op, + virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, - std::vector<SDOperand> &OutOps, + std::vector<SDValue> &OutOps, SelectionDAG &DAG) { - SDOperand Op0, Op1; + SDValue Op0, Op1; switch (ConstraintCode) { default: return true; case 'm': // memory @@ -170,8 +170,8 @@ namespace { return false; } - SDOperand BuildSDIVSequence(SDNode *N); - SDOperand BuildUDIVSequence(SDNode *N); + SDValue BuildSDIVSequence(SDNode *N); + SDValue BuildUDIVSequence(SDNode *N); /// InstructionSelect - This callback is invoked by /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. @@ -197,7 +197,7 @@ namespace { #include "PPCGenDAGISel.inc" private: - SDNode *SelectSETCC(SDOperand Op); + SDNode *SelectSETCC(SDValue Op); }; } @@ -313,7 +313,7 @@ static bool isIntS16Immediate(SDNode *N, short &Imm) { return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue(); } -static bool isIntS16Immediate(SDOperand Op, short &Imm) { +static bool isIntS16Immediate(SDValue Op, short &Imm) { return isIntS16Immediate(Op.Val, Imm); } @@ -340,7 +340,7 @@ static bool isInt64Immediate(SDNode *N, uint64_t &Imm) { // isInt32Immediate - This method tests to see if a constant operand. // If so Imm will receive the 32 bit value. -static bool isInt32Immediate(SDOperand N, unsigned &Imm) { +static bool isInt32Immediate(SDValue N, unsigned &Imm) { return isInt32Immediate(N.Val, Imm); } @@ -418,8 +418,8 @@ bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask, /// SelectBitfieldInsert - turn an or of two masked values into /// the rotate left word immediate then mask insert (rlwimi) instruction. SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) { - SDOperand Op0 = N->getOperand(0); - SDOperand Op1 = N->getOperand(1); + SDValue Op0 = N->getOperand(0); + SDValue Op1 = N->getOperand(1); APInt LKZ, LKO, RKZ, RKO; CurDAG->ComputeMaskedBits(Op0, APInt::getAllOnesValue(32), LKZ, LKO); @@ -458,7 +458,7 @@ SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) { unsigned MB, ME; if (InsertMask && isRunOfOnes(InsertMask, MB, ME)) { - SDOperand Tmp1, Tmp2, Tmp3; + SDValue Tmp1, Tmp2, Tmp3; bool DisjointMask = (TargetMask ^ InsertMask) == 0xFFFFFFFF; if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) && @@ -481,7 +481,7 @@ SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) { AddToISelQueue(Tmp3); AddToISelQueue(Op1); SH &= 31; - SDOperand Ops[] = { Tmp3, Op1, getI32Imm(SH), getI32Imm(MB), + SDValue Ops[] = { Tmp3, Op1, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) }; return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Ops, 5); } @@ -491,7 +491,7 @@ SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) { /// SelectCC - Select a comparison of the specified values with the specified /// condition code, returning the CR# of the expression. -SDOperand PPCDAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS, +SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC) { // Always select the LHS. AddToISelQueue(LHS); @@ -503,11 +503,11 @@ SDOperand PPCDAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS, if (isInt32Immediate(RHS, Imm)) { // SETEQ/SETNE comparison with 16-bit immediate, fold it. if (isUInt16(Imm)) - return SDOperand(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, LHS, + return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, LHS, getI32Imm(Imm & 0xFFFF)), 0); // If this is a 16-bit signed immediate, fold it. if (isInt16((int)Imm)) - return SDOperand(CurDAG->getTargetNode(PPC::CMPWI, MVT::i32, LHS, + return SDValue(CurDAG->getTargetNode(PPC::CMPWI, MVT::i32, LHS, getI32Imm(Imm & 0xFFFF)), 0); // For non-equality comparisons, the default code would materialize the @@ -519,21 +519,21 @@ SDOperand PPCDAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS, // xoris r0,r3,0x1234 // cmplwi cr0,r0,0x5678 // beq cr0,L6 - SDOperand Xor(CurDAG->getTargetNode(PPC::XORIS, MVT::i32, LHS, + SDValue Xor(CurDAG->getTargetNode(PPC::XORIS, MVT::i32, LHS, getI32Imm(Imm >> 16)), 0); - return SDOperand(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, Xor, + return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, Xor, getI32Imm(Imm & 0xFFFF)), 0); } Opc = PPC::CMPLW; } else if (ISD::isUnsignedIntSetCC(CC)) { if (isInt32Immediate(RHS, Imm) && isUInt16(Imm)) - return SDOperand(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, LHS, + return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, LHS, getI32Imm(Imm & 0xFFFF)), 0); Opc = PPC::CMPLW; } else { short SImm; if (isIntS16Immediate(RHS, SImm)) - return SDOperand(CurDAG->getTargetNode(PPC::CMPWI, MVT::i32, LHS, + return SDValue(CurDAG->getTargetNode(PPC::CMPWI, MVT::i32, LHS, getI32Imm((int)SImm & 0xFFFF)), 0); Opc = PPC::CMPW; @@ -544,11 +544,11 @@ SDOperand PPCDAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS, if (isInt64Immediate(RHS.Val, Imm)) { // SETEQ/SETNE comparison with 16-bit immediate, fold it. if (isUInt16(Imm)) - return SDOperand(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, LHS, + return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, LHS, getI32Imm(Imm & 0xFFFF)), 0); // If this is a 16-bit signed immediate, fold it. if (isInt16(Imm)) - return SDOperand(CurDAG->getTargetNode(PPC::CMPDI, MVT::i64, LHS, + return SDValue(CurDAG->getTargetNode(PPC::CMPDI, MVT::i64, LHS, getI32Imm(Imm & 0xFFFF)), 0); // For non-equality comparisons, the default code would materialize the @@ -561,22 +561,22 @@ SDOperand PPCDAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS, // cmpldi cr0,r0,0x5678 // beq cr0,L6 if (isUInt32(Imm)) { - SDOperand Xor(CurDAG->getTargetNode(PPC::XORIS8, MVT::i64, LHS, + SDValue Xor(CurDAG->getTargetNode(PPC::XORIS8, MVT::i64, LHS, getI64Imm(Imm >> 16)), 0); - return SDOperand(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, Xor, + return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, Xor, getI64Imm(Imm & 0xFFFF)), 0); } } Opc = PPC::CMPLD; } else if (ISD::isUnsignedIntSetCC(CC)) { if (isInt64Immediate(RHS.Val, Imm) && isUInt16(Imm)) - return SDOperand(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, LHS, + return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, LHS, getI64Imm(Imm & 0xFFFF)), 0); Opc = PPC::CMPLD; } else { short SImm; if (isIntS16Immediate(RHS, SImm)) - return SDOperand(CurDAG->getTargetNode(PPC::CMPDI, MVT::i64, LHS, + return SDValue(CurDAG->getTargetNode(PPC::CMPDI, MVT::i64, LHS, getI64Imm(SImm & 0xFFFF)), 0); Opc = PPC::CMPD; @@ -588,7 +588,7 @@ SDOperand PPCDAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS, Opc = PPC::FCMPUD; } AddToISelQueue(RHS); - return SDOperand(CurDAG->getTargetNode(Opc, MVT::i32, LHS, RHS), 0); + return SDValue(CurDAG->getTargetNode(Opc, MVT::i32, LHS, RHS), 0); } static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) { @@ -653,7 +653,7 @@ static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert, int &Other) { return 0; } -SDNode *PPCDAGToDAGISel::SelectSETCC(SDOperand Op) { +SDNode *PPCDAGToDAGISel::SelectSETCC(SDValue Op) { SDNode *N = Op.Val; unsigned Imm; ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get(); @@ -662,64 +662,64 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDOperand Op) { // Check for those cases here. // setcc op, 0 if (Imm == 0) { - SDOperand Op = N->getOperand(0); + SDValue Op = N->getOperand(0); AddToISelQueue(Op); switch (CC) { default: break; case ISD::SETEQ: { - Op = SDOperand(CurDAG->getTargetNode(PPC::CNTLZW, MVT::i32, Op), 0); - SDOperand Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) }; + Op = SDValue(CurDAG->getTargetNode(PPC::CNTLZW, MVT::i32, Op), 0); + SDValue Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) }; return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); } case ISD::SETNE: { - SDOperand AD = - SDOperand(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag, + SDValue AD = + SDValue(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag, Op, getI32Imm(~0U)), 0); return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, AD.getValue(1)); } case ISD::SETLT: { - SDOperand Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; + SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); } case ISD::SETGT: { - SDOperand T = - SDOperand(CurDAG->getTargetNode(PPC::NEG, MVT::i32, Op), 0); - T = SDOperand(CurDAG->getTargetNode(PPC::ANDC, MVT::i32, T, Op), 0); - SDOperand Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; + SDValue T = + SDValue(CurDAG->getTargetNode(PPC::NEG, MVT::i32, Op), 0); + T = SDValue(CurDAG->getTargetNode(PPC::ANDC, MVT::i32, T, Op), 0); + SDValue Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); } } } else if (Imm == ~0U) { // setcc op, -1 - SDOperand Op = N->getOperand(0); + SDValue Op = N->getOperand(0); AddToISelQueue(Op); switch (CC) { default: break; case ISD::SETEQ: - Op = SDOperand(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag, + Op = SDValue(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag, Op, getI32Imm(1)), 0); return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, - SDOperand(CurDAG->getTargetNode(PPC::LI, MVT::i32, + SDValue(CurDAG->getTargetNode(PPC::LI, MVT::i32, getI32Imm(0)), 0), Op.getValue(1)); case ISD::SETNE: { - Op = SDOperand(CurDAG->getTargetNode(PPC::NOR, MVT::i32, Op, Op), 0); + Op = SDValue(CurDAG->getTargetNode(PPC::NOR, MVT::i32, Op, Op), 0); SDNode *AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag, Op, getI32Imm(~0U)); - return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDOperand(AD, 0), - Op, SDOperand(AD, 1)); + return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0), + Op, SDValue(AD, 1)); } case ISD::SETLT: { - SDOperand AD = SDOperand(CurDAG->getTargetNode(PPC::ADDI, MVT::i32, Op, + SDValue AD = SDValue(CurDAG->getTargetNode(PPC::ADDI, MVT::i32, Op, getI32Imm(1)), 0); - SDOperand AN = SDOperand(CurDAG->getTargetNode(PPC::AND, MVT::i32, AD, + SDValue AN = SDValue(CurDAG->getTargetNode(PPC::AND, MVT::i32, AD, Op), 0); - SDOperand Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; + SDValue Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); } case ISD::SETGT: { - SDOperand Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; - Op = SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0); + SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; + Op = SDValue(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0); return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, getI32Imm(1)); } @@ -730,30 +730,30 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDOperand Op) { bool Inv; int OtherCondIdx; unsigned Idx = getCRIdxForSetCC(CC, Inv, OtherCondIdx); - SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC); - SDOperand IntCR; + SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC); + SDValue IntCR; // Force the ccreg into CR7. - SDOperand CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32); + SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32); - SDOperand InFlag(0, 0); // Null incoming flag value. + SDValue InFlag(0, 0); // Null incoming flag value. CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), CR7Reg, CCReg, InFlag).getValue(1); if (PPCSubTarget.isGigaProcessor() && OtherCondIdx == -1) - IntCR = SDOperand(CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CR7Reg, + IntCR = SDValue(CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CR7Reg, CCReg), 0); else - IntCR = SDOperand(CurDAG->getTargetNode(PPC::MFCR, MVT::i32, CCReg), 0); + IntCR = SDValue(CurDAG->getTargetNode(PPC::MFCR, MVT::i32, CCReg), 0); - SDOperand Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31), + SDValue Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31), getI32Imm(31), getI32Imm(31) }; if (OtherCondIdx == -1 && !Inv) return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); // Get the specified bit. - SDOperand Tmp = - SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0); + SDValue Tmp = + SDValue(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0); if (Inv) { assert(OtherCondIdx == -1 && "Can't have split plus negation"); return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1)); @@ -764,8 +764,8 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDOperand Op) { // Get the other bit of the comparison. Ops[1] = getI32Imm((32-(3-OtherCondIdx)) & 31); - SDOperand OtherCond = - SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0); + SDValue OtherCond = + SDValue(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0); return CurDAG->SelectNodeTo(N, PPC::OR, MVT::i32, Tmp, OtherCond); } @@ -773,7 +773,7 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDOperand Op) { // Select - Convert the specified operand from a target-independent to a // target-specific node if it hasn't already been changed. -SDNode *PPCDAGToDAGISel::Select(SDOperand Op) { +SDNode *PPCDAGToDAGISel::Select(SDValue Op) { SDNode *N = Op.Val; if (N->isMachineOpcode()) return NULL; // Already selected. @@ -824,7 +824,7 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) { Result = CurDAG->getTargetNode(OpC, MVT::i64, getI32Imm(Hi)); // And Lo bits. Result = CurDAG->getTargetNode(PPC::ORI8, MVT::i64, - SDOperand(Result, 0), getI32Imm(Lo)); + SDValue(Result, 0), getI32Imm(Lo)); } else { // Just the Hi bits. Result = CurDAG->getTargetNode(PPC::LIS8, MVT::i64, getI32Imm(Hi)); @@ -836,18 +836,18 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) { // Shift for next step if the upper 32-bits were not zero. if (Imm) { Result = CurDAG->getTargetNode(PPC::RLDICR, MVT::i64, - SDOperand(Result, 0), + SDValue(Result, 0), getI32Imm(Shift), getI32Imm(63 - Shift)); } // Add in the last bits as required. if ((Hi = (Remainder >> 16) & 0xFFFF)) { Result = CurDAG->getTargetNode(PPC::ORIS8, MVT::i64, - SDOperand(Result, 0), getI32Imm(Hi)); + SDValue(Result, 0), getI32Imm(Hi)); } if ((Lo = Remainder & 0xFFFF)) { Result = CurDAG->getTargetNode(PPC::ORI8, MVT::i64, - SDOperand(Result, 0), getI32Imm(Lo)); + SDValue(Result, 0), getI32Imm(Lo)); } return Result; @@ -862,7 +862,7 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) { case ISD::FrameIndex: { int FI = cast<FrameIndexSDNode>(N)->getIndex(); - SDOperand TFI = CurDAG->getTargetFrameIndex(FI, Op.getValueType()); + SDValue TFI = CurDAG->getTargetFrameIndex(FI, Op.getValueType()); unsigned Opc = Op.getValueType() == MVT::i32 ? PPC::ADDI : PPC::ADDI8; if (N->hasOneUse()) return CurDAG->SelectNodeTo(N, Opc, Op.getValueType(), TFI, @@ -872,7 +872,7 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) { } case PPCISD::MFCR: { - SDOperand InFlag = N->getOperand(1); + SDValue InFlag = N->getOperand(1); AddToISelQueue(InFlag); // Use MFOCRF if supported. if (PPCSubTarget.isGigaProcessor()) @@ -890,21 +890,21 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) { // sra/addze rather than having to handle sdiv ourselves. oh well. unsigned Imm; if (isInt32Immediate(N->getOperand(1), Imm)) { - SDOperand N0 = N->getOperand(0); + SDValue N0 = N->getOperand(0); AddToISelQueue(N0); if ((signed)Imm > 0 && isPowerOf2_32(Imm)) { SDNode *Op = CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag, N0, getI32Imm(Log2_32(Imm))); return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, - SDOperand(Op, 0), SDOperand(Op, 1)); + SDValue(Op, 0), SDValue(Op, 1)); } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) { SDNode *Op = CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag, N0, getI32Imm(Log2_32(-Imm))); - SDOperand PT = - SDOperand(CurDAG->getTargetNode(PPC::ADDZE, MVT::i32, - SDOperand(Op, 0), SDOperand(Op, 1)), + SDValue PT = + SDValue(CurDAG->getTargetNode(PPC::ADDZE, MVT::i32, + SDValue(Op, 0), SDValue(Op, 1)), 0); return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT); } @@ -923,7 +923,7 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) { if (LD->getAddressingMode() != ISD::PRE_INC) break; - SDOperand Offset = LD->getOffset(); + SDValue Offset = LD->getOffset(); if (isa<ConstantSDNode>(Offset) || Offset.getOpcode() == ISD::TargetGlobalAddress) { @@ -954,12 +954,12 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) { } } - SDOperand Chain = LD->getChain(); - SDOperand Base = LD->getBasePtr(); + SDValue Chain = LD->getChain(); + SDValue Base = LD->getBasePtr(); AddToISelQueue(Chain); AddToISelQueue(Base); AddToISelQueue(Offset); - SDOperand Ops[] = { Offset, Base, Chain }; + SDValue Ops[] = { Offset, Base, Chain }; // FIXME: PPC64 return CurDAG->getTargetNode(Opcode, LD->getValueType(0), PPCLowering.getPointerTy(), @@ -976,9 +976,9 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) { // with a mask, emit rlwinm if (isInt32Immediate(N->getOperand(1), Imm) && isRotateAndMask(N->getOperand(0).Val, Imm, false, SH, MB, ME)) { - SDOperand Val = N->getOperand(0).getOperand(0); + SDValue Val = N->getOperand(0).getOperand(0); AddToISelQueue(Val); - SDOperand Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) }; + SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) }; return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); } // If this is just a masked value where the input is not handled above, and @@ -986,15 +986,15 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) { if (isInt32Immediate(N->getOperand(1), Imm) && isRunOfOnes(Imm, MB, ME) && N->getOperand(0).getOpcode() != ISD::ROTL) { - SDOperand Val = N->getOperand(0); + SDValue Val = N->getOperand(0); AddToISelQueue(Val); - SDOperand Ops[] = { Val, getI32Imm(0), getI32Imm(MB), getI32Imm(ME) }; + SDValue Ops[] = { Val, getI32Imm(0), getI32Imm(MB), getI32Imm(ME) }; return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); } // AND X, 0 -> 0, not "rlwinm 32". if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) { AddToISelQueue(N->getOperand(1)); - ReplaceUses(SDOperand(N, 0), N->getOperand(1)); + ReplaceUses(SDValue(N, 0), N->getOperand(1)); return NULL; } // ISD::OR doesn't get all the bitfield insertion fun. @@ -1007,7 +1007,7 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) { if (isRunOfOnes(Imm, MB, ME)) { AddToISelQueue(N->getOperand(0).getOperand(0)); AddToISelQueue(N->getOperand(0).getOperand(1)); - SDOperand Ops[] = { N->getOperand(0).getOperand(0), + SDValue Ops[] = { N->getOperand(0).getOperand(0), N->getOperand(0).getOperand(1), getI32Imm(0), getI32Imm(MB),getI32Imm(ME) }; return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Ops, 5); @@ -1029,7 +1029,7 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) { if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) && isRotateAndMask(N, Imm, true, SH, MB, ME)) { AddToISelQueue(N->getOperand(0).getOperand(0)); - SDOperand Ops[] = { N->getOperand(0).getOperand(0), + SDValue Ops[] = { N->getOperand(0).getOperand(0), getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) }; return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); } @@ -1042,7 +1042,7 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) { if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) && isRotateAndMask(N, Imm, true, SH, MB, ME)) { AddToISelQueue(N->getOperand(0).getOperand(0)); - SDOperand Ops[] = { N->getOperand(0).getOperand(0), + SDValue Ops[] = { N->getOperand(0).getOperand(0), getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) }; return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); } @@ -1066,11 +1066,11 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) { CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag, N->getOperand(0), getI32Imm(~0U)); return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, - SDOperand(Tmp, 0), N->getOperand(0), - SDOperand(Tmp, 1)); + SDValue(Tmp, 0), N->getOperand(0), + SDValue(Tmp, 1)); } - SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC); + SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC); unsigned BROpc = getPredicateForSetCC(CC); unsigned SelectCCOp; @@ -1087,7 +1087,7 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) { AddToISelQueue(N->getOperand(2)); AddToISelQueue(N->getOperand(3)); - SDOperand Ops[] = { CCReg, N->getOperand(2), N->getOperand(3), + SDValue Ops[] = { CCReg, N->getOperand(2), N->getOperand(3), getI32Imm(BROpc) }; return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops, 4); } @@ -1098,28 +1098,28 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) { // Op #3 is the Dest MBB AddToISelQueue(N->getOperand(4)); // Op #4 is the Flag. // Prevent PPC::PRED_* from being selected into LI. - SDOperand Pred = + SDValue Pred = getI32Imm(cast<ConstantSDNode>(N->getOperand(1))->getValue()); - SDOperand Ops[] = { Pred, N->getOperand(2), N->getOperand(3), + SDValue Ops[] = { Pred, N->getOperand(2), N->getOperand(3), N->getOperand(0), N->getOperand(4) }; return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 5); } case ISD::BR_CC: { AddToISelQueue(N->getOperand(0)); ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); - SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC); - SDOperand Ops[] = { getI32Imm(getPredicateForSetCC(CC)), CondCode, + SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC); + SDValue Ops[] = { getI32Imm(getPredicateForSetCC(CC)), CondCode, N->getOperand(4), N->getOperand(0) }; return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 4); } case ISD::BRIND: { // FIXME: Should custom lower this. - SDOperand Chain = N->getOperand(0); - SDOperand Target = N->getOperand(1); + SDValue Chain = N->getOperand(0); + SDValue Target = N->getOperand(1); AddToISelQueue(Chain); AddToISelQueue(Target); unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8; - Chain = SDOperand(CurDAG->getTargetNode(Opc, MVT::Other, Target, + Chain = SDValue(CurDAG->getTargetNode(Opc, MVT::Other, Target, Chain), 0); return CurDAG->SelectNodeTo(N, PPC::BCTR, MVT::Other, Chain); } diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index e8e1659..1fe2e8c 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -422,7 +422,7 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { } -MVT PPCTargetLowering::getSetCCResultType(const SDOperand &) const { +MVT PPCTargetLowering::getSetCCResultType(const SDValue &) const { return MVT::i32; } @@ -432,7 +432,7 @@ MVT PPCTargetLowering::getSetCCResultType(const SDOperand &) const { //===----------------------------------------------------------------------===// /// isFloatingPointZero - Return true if this is 0.0 or -0.0. -static bool isFloatingPointZero(SDOperand Op) { +static bool isFloatingPointZero(SDValue Op) { if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) return CFP->getValueAPF().isZero(); else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) { @@ -446,7 +446,7 @@ static bool isFloatingPointZero(SDOperand Op) { /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return /// true if Op is undef or if it matches the specified value. -static bool isConstantOrUndef(SDOperand Op, unsigned Val) { +static bool isConstantOrUndef(SDValue Op, unsigned Val) { return Op.getOpcode() == ISD::UNDEF || cast<ConstantSDNode>(Op)->getValue() == Val; } @@ -567,7 +567,7 @@ bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) { // This is a splat operation if each element of the permute is the same, and // if the value doesn't reference the second vector. unsigned ElementBase = 0; - SDOperand Elt = N->getOperand(0); + SDValue Elt = N->getOperand(0); if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt)) ElementBase = EltV->getValue(); else @@ -617,8 +617,8 @@ unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) { /// by using a vspltis[bhw] instruction of the specified element size, return /// the constant being splatted. The ByteSize field indicates the number of /// bytes of each element [124] -> [bhw]. -SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { - SDOperand OpVal(0, 0); +SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { + SDValue OpVal(0, 0); // If ByteSize of the splat is bigger than the element size of the // build_vector, then we have a case where we are checking for a splat where @@ -627,20 +627,20 @@ SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { unsigned EltSize = 16/N->getNumOperands(); if (EltSize < ByteSize) { unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval. - SDOperand UniquedVals[4]; + SDValue UniquedVals[4]; assert(Multiple > 1 && Multiple <= 4 && "How can this happen?"); // See if all of the elements in the buildvector agree across. for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; // If the element isn't a constant, bail fully out. - if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand(); + if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue(); if (UniquedVals[i&(Multiple-1)].Val == 0) UniquedVals[i&(Multiple-1)] = N->getOperand(i); else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i)) - return SDOperand(); // no match. + return SDValue(); // no match. } // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains @@ -673,7 +673,7 @@ SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { return DAG.getTargetConstant(Val, MVT::i32); } - return SDOperand(); + return SDValue(); } // Check to see if this buildvec has a single non-undef value in its elements. @@ -682,10 +682,10 @@ SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { if (OpVal.Val == 0) OpVal = N->getOperand(i); else if (OpVal != N->getOperand(i)) - return SDOperand(); + return SDValue(); } - if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def. + if (OpVal.Val == 0) return SDValue(); // All UNDEF: use implicit def. unsigned ValSizeInBytes = 0; uint64_t Value = 0; @@ -701,7 +701,7 @@ SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { // If the splat value is larger than the element value, then we can never do // this splat. The only case that we could fit the replicated bits into our // immediate field for would be zero, and we prefer to use vxor for it. - if (ValSizeInBytes < ByteSize) return SDOperand(); + if (ValSizeInBytes < ByteSize) return SDValue(); // If the element value is larger than the splat value, cut it in half and // check to see if the two halves are equal. Continue doing this until we @@ -712,7 +712,7 @@ SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { // If the top half equals the bottom half, we're still ok. if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) != (Value & ((1 << (8*ValSizeInBytes))-1))) - return SDOperand(); + return SDValue(); } // Properly sign extend the value. @@ -720,12 +720,12 @@ SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { int MaskVal = ((int)Value << ShAmt) >> ShAmt; // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros. - if (MaskVal == 0) return SDOperand(); + if (MaskVal == 0) return SDValue(); // Finally, if this value fits in a 5 bit sext field, return it if (((MaskVal << (32-5)) >> (32-5)) == MaskVal) return DAG.getTargetConstant(MaskVal, MVT::i32); - return SDOperand(); + return SDValue(); } //===----------------------------------------------------------------------===// @@ -746,7 +746,7 @@ static bool isIntS16Immediate(SDNode *N, short &Imm) { else return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue(); } -static bool isIntS16Immediate(SDOperand Op, short &Imm) { +static bool isIntS16Immediate(SDValue Op, short &Imm) { return isIntS16Immediate(Op.Val, Imm); } @@ -754,8 +754,8 @@ static bool isIntS16Immediate(SDOperand Op, short &Imm) { /// SelectAddressRegReg - Given the specified addressed, check to see if it /// can be represented as an indexed [r+r] operation. Returns false if it /// can be more efficiently represented with [r+imm]. -bool PPCTargetLowering::SelectAddressRegReg(SDOperand N, SDOperand &Base, - SDOperand &Index, +bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base, + SDValue &Index, SelectionDAG &DAG) { short imm = 0; if (N.getOpcode() == ISD::ADD) { @@ -802,8 +802,8 @@ bool PPCTargetLowering::SelectAddressRegReg(SDOperand N, SDOperand &Base, /// Returns true if the address N can be represented by a base register plus /// a signed 16-bit displacement [r+imm], and if it is not better /// represented as reg+reg. -bool PPCTargetLowering::SelectAddressRegImm(SDOperand N, SDOperand &Disp, - SDOperand &Base, SelectionDAG &DAG){ +bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp, + SDValue &Base, SelectionDAG &DAG){ // If this can be more profitably realized as r+r, fail. if (SelectAddressRegReg(N, Disp, Base, DAG)) return false; @@ -871,7 +871,7 @@ bool PPCTargetLowering::SelectAddressRegImm(SDOperand N, SDOperand &Disp, Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32); unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; - Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0); + Base = SDValue(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0); return true; } } @@ -886,8 +886,8 @@ bool PPCTargetLowering::SelectAddressRegImm(SDOperand N, SDOperand &Disp, /// SelectAddressRegRegOnly - Given the specified addressed, force it to be /// represented as an indexed [r+r] operation. -bool PPCTargetLowering::SelectAddressRegRegOnly(SDOperand N, SDOperand &Base, - SDOperand &Index, +bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base, + SDValue &Index, SelectionDAG &DAG) { // Check to see if we can easily represent this as an [r+r] address. This // will fail if it thinks that the address is more profitably represented as @@ -913,8 +913,8 @@ bool PPCTargetLowering::SelectAddressRegRegOnly(SDOperand N, SDOperand &Base, /// SelectAddressRegImmShift - Returns true if the address N can be /// represented by a base register plus a signed 14-bit displacement /// [r+imm*4]. Suitable for use by STD and friends. -bool PPCTargetLowering::SelectAddressRegImmShift(SDOperand N, SDOperand &Disp, - SDOperand &Base, +bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp, + SDValue &Base, SelectionDAG &DAG) { // If this can be more profitably realized as r+r, fail. if (SelectAddressRegReg(N, Disp, Base, DAG)) @@ -982,7 +982,7 @@ bool PPCTargetLowering::SelectAddressRegImmShift(SDOperand N, SDOperand &Disp, Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32); unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; - Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0); + Base = SDValue(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0); return true; } } @@ -1000,14 +1000,14 @@ bool PPCTargetLowering::SelectAddressRegImmShift(SDOperand N, SDOperand &Disp, /// getPreIndexedAddressParts - returns true by value, base pointer and /// offset pointer and addressing mode by reference if the node's address /// can be legally represented as pre-indexed load / store address. -bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base, - SDOperand &Offset, +bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, + SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) { // Disabled by default for now. if (!EnablePPCPreinc) return false; - SDOperand Ptr; + SDValue Ptr; MVT VT; if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { Ptr = LD->getBasePtr(); @@ -1054,18 +1054,18 @@ bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base, // LowerOperation implementation //===----------------------------------------------------------------------===// -SDOperand PPCTargetLowering::LowerConstantPool(SDOperand Op, +SDValue PPCTargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) { MVT PtrVT = Op.getValueType(); ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); Constant *C = CP->getConstVal(); - SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment()); - SDOperand Zero = DAG.getConstant(0, PtrVT); + SDValue CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment()); + SDValue Zero = DAG.getConstant(0, PtrVT); const TargetMachine &TM = DAG.getTarget(); - SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero); - SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero); + SDValue Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero); + SDValue Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero); // If this is a non-darwin platform, we don't support non-static relo models // yet. @@ -1086,16 +1086,16 @@ SDOperand PPCTargetLowering::LowerConstantPool(SDOperand Op, return Lo; } -SDOperand PPCTargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) { +SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) { MVT PtrVT = Op.getValueType(); JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); - SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); - SDOperand Zero = DAG.getConstant(0, PtrVT); + SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); + SDValue Zero = DAG.getConstant(0, PtrVT); const TargetMachine &TM = DAG.getTarget(); - SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero); - SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero); + SDValue Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero); + SDValue Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero); // If this is a non-darwin platform, we don't support non-static relo models // yet. @@ -1116,27 +1116,27 @@ SDOperand PPCTargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) { return Lo; } -SDOperand PPCTargetLowering::LowerGlobalTLSAddress(SDOperand Op, +SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) { assert(0 && "TLS not implemented for PPC."); - return SDOperand(); // Not reached + return SDValue(); // Not reached } -SDOperand PPCTargetLowering::LowerGlobalAddress(SDOperand Op, +SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) { MVT PtrVT = Op.getValueType(); GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); GlobalValue *GV = GSDN->getGlobal(); - SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset()); + SDValue GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset()); // If it's a debug information descriptor, don't mess with it. if (DAG.isVerifiedDebugInfoDesc(Op)) return GA; - SDOperand Zero = DAG.getConstant(0, PtrVT); + SDValue Zero = DAG.getConstant(0, PtrVT); const TargetMachine &TM = DAG.getTarget(); - SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero); - SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero); + SDValue Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero); + SDValue Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero); // If this is a non-darwin platform, we don't support non-static relo models // yet. @@ -1163,7 +1163,7 @@ SDOperand PPCTargetLowering::LowerGlobalAddress(SDOperand Op, return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0); } -SDOperand PPCTargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG) { +SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) { ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); // If we're comparing for equality to zero, expose the fact that this is @@ -1172,14 +1172,14 @@ SDOperand PPCTargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG) { if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { if (C->isNullValue() && CC == ISD::SETEQ) { MVT VT = Op.getOperand(0).getValueType(); - SDOperand Zext = Op.getOperand(0); + SDValue Zext = Op.getOperand(0); if (VT.bitsLT(MVT::i32)) { VT = MVT::i32; Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0)); } unsigned Log2b = Log2_32(VT.getSizeInBits()); - SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext); - SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz, + SDValue Clz = DAG.getNode(ISD::CTLZ, VT, Zext); + SDValue Scc = DAG.getNode(ISD::SRL, VT, Clz, DAG.getConstant(Log2b, MVT::i32)); return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc); } @@ -1187,7 +1187,7 @@ SDOperand PPCTargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG) { // optimized. FIXME: revisit this when we can custom lower all setcc // optimizations. if (C->isAllOnesValue() || C->isNullValue()) - return SDOperand(); + return SDValue(); } // If we have an integer seteq/setne, turn it into a compare against zero @@ -1198,14 +1198,14 @@ SDOperand PPCTargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG) { MVT LHSVT = Op.getOperand(0).getValueType(); if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) { MVT VT = Op.getValueType(); - SDOperand Sub = DAG.getNode(ISD::XOR, LHSVT, Op.getOperand(0), + SDValue Sub = DAG.getNode(ISD::XOR, LHSVT, Op.getOperand(0), Op.getOperand(1)); return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC); } - return SDOperand(); + return SDValue(); } -SDOperand PPCTargetLowering::LowerVAARG(SDOperand Op, SelectionDAG &DAG, +SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG, int VarArgsFrameIndex, int VarArgsStackOffset, unsigned VarArgsNumGPR, @@ -1213,10 +1213,10 @@ SDOperand PPCTargetLowering::LowerVAARG(SDOperand Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget) { assert(0 && "VAARG in ELF32 ABI not implemented yet!"); - return SDOperand(); // Not reached + return SDValue(); // Not reached } -SDOperand PPCTargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG, +SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG, int VarArgsFrameIndex, int VarArgsStackOffset, unsigned VarArgsNumGPR, @@ -1227,7 +1227,7 @@ SDOperand PPCTargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG, // vastart just stores the address of the VarArgsFrameIndex slot into the // memory location argument. MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); - SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); + SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0); } @@ -1257,41 +1257,41 @@ SDOperand PPCTargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG, // } va_list[1]; - SDOperand ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i8); - SDOperand ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i8); + SDValue ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i8); + SDValue ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i8); MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); - SDOperand StackOffsetFI = DAG.getFrameIndex(VarArgsStackOffset, PtrVT); - SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); + SDValue StackOffsetFI = DAG.getFrameIndex(VarArgsStackOffset, PtrVT); + SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); uint64_t FrameOffset = PtrVT.getSizeInBits()/8; - SDOperand ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT); + SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT); uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1; - SDOperand ConstStackOffset = DAG.getConstant(StackOffset, PtrVT); + SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT); uint64_t FPROffset = 1; - SDOperand ConstFPROffset = DAG.getConstant(FPROffset, PtrVT); + SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT); const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); // Store first byte : number of int regs - SDOperand firstStore = DAG.getStore(Op.getOperand(0), ArgGPR, + SDValue firstStore = DAG.getStore(Op.getOperand(0), ArgGPR, Op.getOperand(1), SV, 0); uint64_t nextOffset = FPROffset; - SDOperand nextPtr = DAG.getNode(ISD::ADD, PtrVT, Op.getOperand(1), + SDValue nextPtr = DAG.getNode(ISD::ADD, PtrVT, Op.getOperand(1), ConstFPROffset); // Store second byte : number of float regs - SDOperand secondStore = + SDValue secondStore = DAG.getStore(firstStore, ArgFPR, nextPtr, SV, nextOffset); nextOffset += StackOffset; nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstStackOffset); // Store second word : arguments given on stack - SDOperand thirdStore = + SDValue thirdStore = DAG.getStore(secondStore, StackOffsetFI, nextPtr, SV, nextOffset); nextOffset += FrameOffset; nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstFrameOffset); @@ -1324,7 +1324,7 @@ static const unsigned *GetFPR(const PPCSubtarget &Subtarget) { /// CalculateStackSlotSize - Calculates the size reserved for this argument on /// the stack. -static unsigned CalculateStackSlotSize(SDOperand Arg, SDOperand Flag, +static unsigned CalculateStackSlotSize(SDValue Arg, SDValue Flag, bool isVarArg, unsigned PtrByteSize) { MVT ArgVT = Arg.getValueType(); ISD::ArgFlagsTy Flags = cast<ARG_FLAGSSDNode>(Flag)->getArgFlags(); @@ -1336,8 +1336,8 @@ static unsigned CalculateStackSlotSize(SDOperand Arg, SDOperand Flag, return ArgSize; } -SDOperand -PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, +SDValue +PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG, int &VarArgsFrameIndex, int &VarArgsStackOffset, @@ -1349,8 +1349,8 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, MachineFunction &MF = DAG.getMachineFunction(); MachineFrameInfo *MFI = MF.getFrameInfo(); MachineRegisterInfo &RegInfo = MF.getRegInfo(); - SmallVector<SDOperand, 8> ArgValues; - SDOperand Root = Op.getOperand(0); + SmallVector<SDValue, 8> ArgValues; + SDValue Root = Op.getOperand(0); bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); @@ -1449,10 +1449,10 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, // represented with two words (long long or double) must be copied to an // even GPR_idx value or to an even ArgOffset value. - SmallVector<SDOperand, 8> MemOps; + SmallVector<SDValue, 8> MemOps; unsigned nAltivecParamsAtEnd = 0; for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) { - SDOperand ArgVal; + SDValue ArgVal; bool needsLoad = false; MVT ObjectVT = Op.getValue(ArgNo).getValueType(); unsigned ObjSize = ObjectVT.getSizeInBits()/8; @@ -1497,14 +1497,14 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, } // The value of the object is its address. int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset); - SDOperand FIN = DAG.getFrameIndex(FI, PtrVT); + SDValue FIN = DAG.getFrameIndex(FI, PtrVT); ArgValues.push_back(FIN); if (ObjSize==1 || ObjSize==2) { if (GPR_idx != Num_GPR_Regs) { unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); RegInfo.addLiveIn(GPR[GPR_idx], VReg); - SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT); - SDOperand Store = DAG.getTruncStore(Val.getValue(1), Val, FIN, + SDValue Val = DAG.getCopyFromReg(Root, VReg, PtrVT); + SDValue Store = DAG.getTruncStore(Val.getValue(1), Val, FIN, NULL, 0, ObjSize==1 ? MVT::i8 : MVT::i16 ); MemOps.push_back(Store); ++GPR_idx; @@ -1522,9 +1522,9 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); RegInfo.addLiveIn(GPR[GPR_idx], VReg); int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset); - SDOperand FIN = DAG.getFrameIndex(FI, PtrVT); - SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT); - SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); + SDValue FIN = DAG.getFrameIndex(FI, PtrVT); + SDValue Val = DAG.getCopyFromReg(Root, VReg, PtrVT); + SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); MemOps.push_back(Store); ++GPR_idx; if (isMachoABI) ArgOffset += PtrByteSize; @@ -1658,7 +1658,7 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset + (ArgSize - ObjSize), isImmutable); - SDOperand FIN = DAG.getFrameIndex(FI, PtrVT); + SDValue FIN = DAG.getFrameIndex(FI, PtrVT); ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0); } @@ -1708,17 +1708,17 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, VarArgsFrameIndex = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8, depth); - SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); + SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); // In ELF 32 ABI, the fixed integer arguments of a variadic function are // stored to the VarArgsFrameIndex on the stack. if (isELF32_ABI) { for (GPR_idx = 0; GPR_idx != VarArgsNumGPR; ++GPR_idx) { - SDOperand Val = DAG.getRegister(GPR[GPR_idx], PtrVT); - SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0); + SDValue Val = DAG.getRegister(GPR[GPR_idx], PtrVT); + SDValue Store = DAG.getStore(Root, Val, FIN, NULL, 0); MemOps.push_back(Store); // Increment the address by four for the next argument to store - SDOperand PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); + SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); } } @@ -1734,11 +1734,11 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); RegInfo.addLiveIn(GPR[GPR_idx], VReg); - SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT); - SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); + SDValue Val = DAG.getCopyFromReg(Root, VReg, PtrVT); + SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); MemOps.push_back(Store); // Increment the address by four for the next argument to store - SDOperand PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); + SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); } @@ -1746,11 +1746,11 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, // on the stack. if (isELF32_ABI) { for (FPR_idx = 0; FPR_idx != VarArgsNumFPR; ++FPR_idx) { - SDOperand Val = DAG.getRegister(FPR[FPR_idx], MVT::f64); - SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0); + SDValue Val = DAG.getRegister(FPR[FPR_idx], MVT::f64); + SDValue Store = DAG.getStore(Root, Val, FIN, NULL, 0); MemOps.push_back(Store); // Increment the address by eight for the next argument to store - SDOperand PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, + SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, PtrVT); FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); } @@ -1760,11 +1760,11 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass); RegInfo.addLiveIn(FPR[FPR_idx], VReg); - SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::f64); - SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); + SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::f64); + SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); MemOps.push_back(Store); // Increment the address by eight for the next argument to store - SDOperand PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, + SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, PtrVT); FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); } @@ -1789,7 +1789,7 @@ CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG, bool isMachoABI, bool isVarArg, unsigned CC, - SDOperand Call, + SDValue Call, unsigned &nAltivecParamsAtEnd) { // Count how many bytes are to be pushed on the stack, including the linkage // area, and parameter passing area. We start with 24/48 bytes, which is @@ -1806,8 +1806,8 @@ CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG, // 16-byte aligned. nAltivecParamsAtEnd = 0; for (unsigned i = 0; i != NumOps; ++i) { - SDOperand Arg = Call.getOperand(5+2*i); - SDOperand Flag = Call.getOperand(5+2*i+1); + SDValue Arg = Call.getOperand(5+2*i); + SDValue Flag = Call.getOperand(5+2*i+1); MVT ArgVT = Arg.getValueType(); // Varargs Altivec parameters are padded to a 16 byte boundary. if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 || @@ -1871,8 +1871,8 @@ static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool IsTailCall, /// calling conventions match, currently only fastcc supports tail calls, and /// the function CALL is immediatly followed by a RET. bool -PPCTargetLowering::IsEligibleForTailCallOptimization(SDOperand Call, - SDOperand Ret, +PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Call, + SDValue Ret, SelectionDAG& DAG) const { // Variable argument functions are not supported. if (!PerformTailCallOpt || @@ -1890,7 +1890,7 @@ PPCTargetLowering::IsEligibleForTailCallOptimization(SDOperand Call, if (Flags.isByVal()) return false; } - SDOperand Callee = Call.getOperand(4); + SDValue Callee = Call.getOperand(4); // Non PIC/GOT tail calls are supported. if (getTargetMachine().getRelocationModel() != Reloc::PIC_) return true; @@ -1908,7 +1908,7 @@ PPCTargetLowering::IsEligibleForTailCallOptimization(SDOperand Call, /// isCallCompatibleAddress - Return the immediate to use if the specified /// 32-bit value is representable in the immediate field of a BxA instruction. -static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) { +static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) { ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); if (!C) return 0; @@ -1924,8 +1924,8 @@ static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) { namespace { struct TailCallArgumentInfo { - SDOperand Arg; - SDOperand FrameIdxOp; + SDValue Arg; + SDValue FrameIdxOp; int FrameIdx; TailCallArgumentInfo() : FrameIdx(0) {} @@ -1936,12 +1936,12 @@ struct TailCallArgumentInfo { /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot. static void StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG, - SDOperand Chain, + SDValue Chain, const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs, - SmallVector<SDOperand, 8> &MemOpChains) { + SmallVector<SDValue, 8> &MemOpChains) { for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) { - SDOperand Arg = TailCallArgs[i].Arg; - SDOperand FIN = TailCallArgs[i].FrameIdxOp; + SDValue Arg = TailCallArgs[i].Arg; + SDValue FIN = TailCallArgs[i].FrameIdxOp; int FI = TailCallArgs[i].FrameIdx; // Store relative to framepointer. MemOpChains.push_back(DAG.getStore(Chain, Arg, FIN, @@ -1952,11 +1952,11 @@ StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG, /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to /// the appropriate stack slot for the tail call optimized function call. -static SDOperand EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, +static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, MachineFunction &MF, - SDOperand Chain, - SDOperand OldRetAddr, - SDOperand OldFP, + SDValue Chain, + SDValue OldRetAddr, + SDValue OldFP, int SPDiff, bool isPPC64, bool isMachoABI) { @@ -1972,10 +1972,10 @@ static SDOperand EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc); MVT VT = isPPC64 ? MVT::i64 : MVT::i32; - SDOperand NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT); + SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT); Chain = DAG.getStore(Chain, OldRetAddr, NewRetAddrFrIdx, PseudoSourceValue::getFixedStack(NewRetAddr), 0); - SDOperand NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT); + SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT); Chain = DAG.getStore(Chain, OldFP, NewFramePtrIdx, PseudoSourceValue::getFixedStack(NewFPIdx), 0); } @@ -1986,13 +1986,13 @@ static SDOperand EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, /// the position of the argument. static void CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64, - SDOperand Arg, int SPDiff, unsigned ArgOffset, + SDValue Arg, int SPDiff, unsigned ArgOffset, SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) { int Offset = ArgOffset + SPDiff; uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8; int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset); MVT VT = isPPC64 ? MVT::i64 : MVT::i32; - SDOperand FIN = DAG.getFrameIndex(FI, VT); + SDValue FIN = DAG.getFrameIndex(FI, VT); TailCallArgumentInfo Info; Info.Arg = Arg; Info.FrameIdxOp = FIN; @@ -2003,20 +2003,20 @@ CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64, /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address /// stack slot. Returns the chain as result and the loaded frame pointers in /// LROpOut/FPOpout. Used when tail calling. -SDOperand PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG, +SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG, int SPDiff, - SDOperand Chain, - SDOperand &LROpOut, - SDOperand &FPOpOut) { + SDValue Chain, + SDValue &LROpOut, + SDValue &FPOpOut) { if (SPDiff) { // Load the LR and FP stack slot for later adjusting. MVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32; LROpOut = getReturnAddrFrameIndex(DAG); LROpOut = DAG.getLoad(VT, Chain, LROpOut, NULL, 0); - Chain = SDOperand(LROpOut.Val, 1); + Chain = SDValue(LROpOut.Val, 1); FPOpOut = getFramePointerFrameIndex(DAG); FPOpOut = DAG.getLoad(VT, Chain, FPOpOut, NULL, 0); - Chain = SDOperand(FPOpOut.Val, 1); + Chain = SDValue(FPOpOut.Val, 1); } return Chain; } @@ -2027,11 +2027,11 @@ SDOperand PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG, /// a byval function parameter. /// Sometimes what we are copying is the end of a larger object, the part that /// does not fit in registers. -static SDOperand -CreateCopyOfByValArgument(SDOperand Src, SDOperand Dst, SDOperand Chain, +static SDValue +CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, unsigned Size) { - SDOperand SizeNode = DAG.getConstant(Size, MVT::i32); + SDValue SizeNode = DAG.getConstant(Size, MVT::i32); return DAG.getMemcpy(Chain, Dst, Src, SizeNode, Flags.getByValAlign(), false, NULL, 0, NULL, 0); } @@ -2039,15 +2039,15 @@ CreateCopyOfByValArgument(SDOperand Src, SDOperand Dst, SDOperand Chain, /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of /// tail calls. static void -LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDOperand Chain, - SDOperand Arg, SDOperand PtrOff, int SPDiff, +LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, + SDValue Arg, SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64, bool isTailCall, - bool isVector, SmallVector<SDOperand, 8> &MemOpChains, + bool isVector, SmallVector<SDValue, 8> &MemOpChains, SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) { MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); if (!isTailCall) { if (isVector) { - SDOperand StackPtr; + SDValue StackPtr; if (isPPC64) StackPtr = DAG.getRegister(PPC::X1, MVT::i64); else @@ -2061,15 +2061,15 @@ LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDOperand Chain, TailCallArguments); } -SDOperand PPCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG, +SDValue PPCTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget, TargetMachine &TM) { - SDOperand Chain = Op.getOperand(0); + SDValue Chain = Op.getOperand(0); bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0 && CC == CallingConv::Fast && PerformTailCallOpt; - SDOperand Callee = Op.getOperand(4); + SDValue Callee = Op.getOperand(4); unsigned NumOps = (Op.getNumOperands() - 5) / 2; bool isMachoABI = Subtarget.isMachoABI(); @@ -2083,7 +2083,7 @@ SDOperand PPCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG, // args_to_use will accumulate outgoing args for the PPCISD::CALL case in // SelectExpr to use to put the arguments in the appropriate registers. - std::vector<SDOperand> args_to_use; + std::vector<SDValue> args_to_use; // Mark this function as potentially containing a function that contains a // tail call. As a consequence the frame pointer will be used for dynamicalloc @@ -2110,17 +2110,17 @@ SDOperand PPCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG, // These operations are automatically eliminated by the prolog/epilog pass Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes, PtrVT)); - SDOperand CallSeqStart = Chain; + SDValue CallSeqStart = Chain; // Load the return address and frame pointer so it can be move somewhere else // later. - SDOperand LROp, FPOp; + SDValue LROp, FPOp; Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp); // Set up a copy of the stack pointer for use loading and storing any // arguments that may not fit in the registers available for argument // passing. - SDOperand StackPtr; + SDValue StackPtr; if (isPPC64) StackPtr = DAG.getRegister(PPC::X1, MVT::i64); else @@ -2153,13 +2153,13 @@ SDOperand PPCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG, const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; - std::vector<std::pair<unsigned, SDOperand> > RegsToPass; + std::vector<std::pair<unsigned, SDValue> > RegsToPass; SmallVector<TailCallArgumentInfo, 8> TailCallArguments; - SmallVector<SDOperand, 8> MemOpChains; + SmallVector<SDValue, 8> MemOpChains; for (unsigned i = 0; i != NumOps; ++i) { bool inMem = false; - SDOperand Arg = Op.getOperand(5+2*i); + SDValue Arg = Op.getOperand(5+2*i); ISD::ArgFlagsTy Flags = cast<ARG_FLAGSSDNode>(Op.getOperand(5+2*i+1))->getArgFlags(); // See if next argument requires stack alignment in ELF @@ -2167,7 +2167,7 @@ SDOperand PPCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG, // PtrOff will be used to store the current argument to the stack if a // register cannot be found for it. - SDOperand PtrOff; + SDValue PtrOff; // Stack align in ELF 32 if (isELF32_ABI && Align) @@ -2195,20 +2195,20 @@ SDOperand PPCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG, // Everything else is passed left-justified. MVT VT = (Size==1) ? MVT::i8 : MVT::i16; if (GPR_idx != NumGPRs) { - SDOperand Load = DAG.getExtLoad(ISD::EXTLOAD, PtrVT, Chain, Arg, + SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, PtrVT, Chain, Arg, NULL, 0, VT); MemOpChains.push_back(Load.getValue(1)); RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); if (isMachoABI) ArgOffset += PtrByteSize; } else { - SDOperand Const = DAG.getConstant(4 - Size, PtrOff.getValueType()); - SDOperand AddPtr = DAG.getNode(ISD::ADD, PtrVT, PtrOff, Const); - SDOperand MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr, + SDValue Const = DAG.getConstant(4 - Size, PtrOff.getValueType()); + SDValue AddPtr = DAG.getNode(ISD::ADD, PtrVT, PtrOff, Const); + SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr, CallSeqStart.Val->getOperand(0), Flags, DAG, Size); // This must go outside the CALLSEQ_START..END. - SDOperand NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, + SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, CallSeqStart.Val->getOperand(1)); DAG.ReplaceAllUsesWith(CallSeqStart.Val, NewCallSeqStart.Val); Chain = CallSeqStart = NewCallSeqStart; @@ -2219,20 +2219,20 @@ SDOperand PPCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG, // Copy entire object into memory. There are cases where gcc-generated // code assumes it is there, even if it could be put entirely into // registers. (This is not what the doc says.) - SDOperand MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff, + SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff, CallSeqStart.Val->getOperand(0), Flags, DAG, Size); // This must go outside the CALLSEQ_START..END. - SDOperand NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, + SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, CallSeqStart.Val->getOperand(1)); DAG.ReplaceAllUsesWith(CallSeqStart.Val, NewCallSeqStart.Val); Chain = CallSeqStart = NewCallSeqStart; // And copy the pieces of it that fit into registers. for (unsigned j=0; j<Size; j+=PtrByteSize) { - SDOperand Const = DAG.getConstant(j, PtrOff.getValueType()); - SDOperand AddArg = DAG.getNode(ISD::ADD, PtrVT, Arg, Const); + SDValue Const = DAG.getConstant(j, PtrOff.getValueType()); + SDValue AddArg = DAG.getNode(ISD::ADD, PtrVT, Arg, Const); if (GPR_idx != NumGPRs) { - SDOperand Load = DAG.getLoad(PtrVT, Chain, AddArg, NULL, 0); + SDValue Load = DAG.getLoad(PtrVT, Chain, AddArg, NULL, 0); MemOpChains.push_back(Load.getValue(1)); RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); if (isMachoABI) @@ -2273,20 +2273,20 @@ SDOperand PPCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG, RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg)); if (isVarArg) { - SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0); + SDValue Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0); MemOpChains.push_back(Store); // Float varargs are always shadowed in available integer registers if (GPR_idx != NumGPRs) { - SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0); + SDValue Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0); MemOpChains.push_back(Load.getValue(1)); if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); } if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){ - SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType()); + SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType()); PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour); - SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0); + SDValue Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0); MemOpChains.push_back(Load.getValue(1)); if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); @@ -2338,10 +2338,10 @@ SDOperand PPCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG, // entirely in R registers. Maybe later. PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, DAG.getConstant(ArgOffset, PtrVT)); - SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0); + SDValue Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0); MemOpChains.push_back(Store); if (VR_idx != NumVRs) { - SDOperand Load = DAG.getLoad(MVT::v4f32, Store, PtrOff, NULL, 0); + SDValue Load = DAG.getLoad(MVT::v4f32, Store, PtrOff, NULL, 0); MemOpChains.push_back(Load.getValue(1)); RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load)); } @@ -2349,9 +2349,9 @@ SDOperand PPCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG, for (unsigned i=0; i<16; i+=PtrByteSize) { if (GPR_idx == NumGPRs) break; - SDOperand Ix = DAG.getNode(ISD::ADD, PtrVT, PtrOff, + SDValue Ix = DAG.getNode(ISD::ADD, PtrVT, PtrOff, DAG.getConstant(i, PtrVT)); - SDOperand Load = DAG.getLoad(PtrVT, Store, Ix, NULL, 0); + SDValue Load = DAG.getLoad(PtrVT, Store, Ix, NULL, 0); MemOpChains.push_back(Load.getValue(1)); RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); } @@ -2384,12 +2384,12 @@ SDOperand PPCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG, ArgOffset = ((ArgOffset+15)/16)*16; ArgOffset += 12*16; for (unsigned i = 0; i != NumOps; ++i) { - SDOperand Arg = Op.getOperand(5+2*i); + SDValue Arg = Op.getOperand(5+2*i); MVT ArgType = Arg.getValueType(); if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 || ArgType==MVT::v8i16 || ArgType==MVT::v16i8) { if (++j > NumVRs) { - SDOperand PtrOff; + SDValue PtrOff; // We are emitting Altivec params in order. LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, isPPC64, isTailCall, true, MemOpChains, @@ -2406,7 +2406,7 @@ SDOperand PPCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG, // Build a sequence of copy-to-reg nodes chained together with token chain // and flag operands which copy the outgoing args into the appropriate regs. - SDOperand InFlag; + SDValue InFlag; for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, InFlag); @@ -2415,7 +2415,7 @@ SDOperand PPCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG, // With the ELF 32 ABI, set CR6 to true if this is a vararg call. if (isVarArg && isELF32_ABI) { - SDOperand SetCR(DAG.getTargetNode(PPC::CRSET, MVT::i32), 0); + SDValue SetCR(DAG.getTargetNode(PPC::CRSET, MVT::i32), 0); Chain = DAG.getCopyToReg(Chain, PPC::CR1EQ, SetCR, InFlag); InFlag = Chain.getValue(1); } @@ -2423,9 +2423,9 @@ SDOperand PPCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG, // Emit a sequence of copyto/copyfrom virtual registers for arguments that // might overwrite each other in case of tail call optimization. if (isTailCall) { - SmallVector<SDOperand, 8> MemOpChains2; + SmallVector<SDValue, 8> MemOpChains2; // Do not flag preceeding copytoreg stuff together with the following stuff. - InFlag = SDOperand(); + InFlag = SDValue(); StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments, MemOpChains2); if (!MemOpChains2.empty()) @@ -2439,7 +2439,7 @@ SDOperand PPCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG, // Emit callseq_end just before tailcall node. if (isTailCall) { - SmallVector<SDOperand, 8> CallSeqOps; + SmallVector<SDValue, 8> CallSeqOps; SDVTList CallSeqNodeTys = DAG.getVTList(MVT::Other, MVT::Flag); CallSeqOps.push_back(Chain); CallSeqOps.push_back(DAG.getIntPtrConstant(NumBytes)); @@ -2455,7 +2455,7 @@ SDOperand PPCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG, NodeTys.push_back(MVT::Other); // Returns a chain NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. - SmallVector<SDOperand, 8> Ops; + SmallVector<SDValue, 8> Ops; unsigned CallOpc = isMachoABI? PPCISD::CALL_Macho : PPCISD::CALL_ELF; // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every @@ -2467,11 +2467,11 @@ SDOperand PPCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG, Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType()); else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) // If this is an absolute destination address, use the munged value. - Callee = SDOperand(Dest, 0); + Callee = SDValue(Dest, 0); else { // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair // to do the call, we can't use PPCISD::CALL. - SDOperand MTCTROps[] = {Chain, Callee, InFlag}; + SDValue MTCTROps[] = {Chain, Callee, InFlag}; Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+(InFlag.Val!=0)); InFlag = Chain.getValue(1); @@ -2523,7 +2523,7 @@ SDOperand PPCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG, "Flag must be set. Depend on flag being set in LowerRET"); Chain = DAG.getNode(PPCISD::TAILCALL, Op.Val->getVTList(), &Ops[0], Ops.size()); - return SDOperand(Chain.Val, Op.ResNo); + return SDValue(Chain.Val, Op.ResNo); } Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size()); @@ -2536,7 +2536,7 @@ SDOperand PPCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG, if (Op.Val->getValueType(0) != MVT::Other) InFlag = Chain.getValue(1); - SmallVector<SDOperand, 16> ResultVals; + SmallVector<SDValue, 16> ResultVals; SmallVector<CCValAssign, 16> RVLocs; unsigned CallerCC = DAG.getMachineFunction().getFunction()->getCallingConv(); CCState CCInfo(CallerCC, isVarArg, TM, RVLocs); @@ -2558,12 +2558,12 @@ SDOperand PPCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG, // Otherwise, merge everything together with a MERGE_VALUES node. ResultVals.push_back(Chain); - SDOperand Res = DAG.getMergeValues(Op.Val->getVTList(), &ResultVals[0], + SDValue Res = DAG.getMergeValues(Op.Val->getVTList(), &ResultVals[0], ResultVals.size()); return Res.getValue(Op.ResNo); } -SDOperand PPCTargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG, +SDValue PPCTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG, TargetMachine &TM) { SmallVector<CCValAssign, 16> RVLocs; unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); @@ -2578,13 +2578,13 @@ SDOperand PPCTargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG, DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); } - SDOperand Chain = Op.getOperand(0); + SDValue Chain = Op.getOperand(0); Chain = GetPossiblePreceedingTailCall(Chain, PPCISD::TAILCALL); if (Chain.getOpcode() == PPCISD::TAILCALL) { - SDOperand TailCall = Chain; - SDOperand TargetAddress = TailCall.getOperand(1); - SDOperand StackAdjustment = TailCall.getOperand(2); + SDValue TailCall = Chain; + SDValue TargetAddress = TailCall.getOperand(1); + SDValue StackAdjustment = TailCall.getOperand(2); assert(((TargetAddress.getOpcode() == ISD::Register && cast<RegisterSDNode>(TargetAddress)->getReg() == PPC::CTR) || @@ -2596,7 +2596,7 @@ SDOperand PPCTargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG, assert(StackAdjustment.getOpcode() == ISD::Constant && "Expecting a const value"); - SmallVector<SDOperand,8> Operands; + SmallVector<SDValue,8> Operands; Operands.push_back(Chain.getOperand(0)); Operands.push_back(TargetAddress); Operands.push_back(StackAdjustment); @@ -2609,7 +2609,7 @@ SDOperand PPCTargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG, Operands.size()); } - SDOperand Flag; + SDValue Flag; // Copy the result values into the output registers. for (unsigned i = 0; i != RVLocs.size(); ++i) { @@ -2625,7 +2625,7 @@ SDOperand PPCTargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG, return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain); } -SDOperand PPCTargetLowering::LowerSTACKRESTORE(SDOperand Op, SelectionDAG &DAG, +SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget) { // When we pop the dynamic allocation we need to restore the SP link. @@ -2635,14 +2635,14 @@ SDOperand PPCTargetLowering::LowerSTACKRESTORE(SDOperand Op, SelectionDAG &DAG, // Construct the stack pointer operand. bool IsPPC64 = Subtarget.isPPC64(); unsigned SP = IsPPC64 ? PPC::X1 : PPC::R1; - SDOperand StackPtr = DAG.getRegister(SP, PtrVT); + SDValue StackPtr = DAG.getRegister(SP, PtrVT); // Get the operands for the STACKRESTORE. - SDOperand Chain = Op.getOperand(0); - SDOperand SaveSP = Op.getOperand(1); + SDValue Chain = Op.getOperand(0); + SDValue SaveSP = Op.getOperand(1); // Load the old link SP. - SDOperand LoadLinkSP = DAG.getLoad(PtrVT, Chain, StackPtr, NULL, 0); + SDValue LoadLinkSP = DAG.getLoad(PtrVT, Chain, StackPtr, NULL, 0); // Restore the stack pointer. Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), SP, SaveSP); @@ -2653,7 +2653,7 @@ SDOperand PPCTargetLowering::LowerSTACKRESTORE(SDOperand Op, SelectionDAG &DAG, -SDOperand +SDValue PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const { MachineFunction &MF = DAG.getMachineFunction(); bool IsPPC64 = PPCSubTarget.isPPC64(); @@ -2677,7 +2677,7 @@ PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const { return DAG.getFrameIndex(RASI, PtrVT); } -SDOperand +SDValue PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const { MachineFunction &MF = DAG.getMachineFunction(); bool IsPPC64 = PPCSubTarget.isPPC64(); @@ -2702,34 +2702,34 @@ PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const { return DAG.getFrameIndex(FPSI, PtrVT); } -SDOperand PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDOperand Op, +SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget) { // Get the inputs. - SDOperand Chain = Op.getOperand(0); - SDOperand Size = Op.getOperand(1); + SDValue Chain = Op.getOperand(0); + SDValue Size = Op.getOperand(1); // Get the corect type for pointers. MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); // Negate the size. - SDOperand NegSize = DAG.getNode(ISD::SUB, PtrVT, + SDValue NegSize = DAG.getNode(ISD::SUB, PtrVT, DAG.getConstant(0, PtrVT), Size); // Construct a node for the frame pointer save index. - SDOperand FPSIdx = getFramePointerFrameIndex(DAG); + SDValue FPSIdx = getFramePointerFrameIndex(DAG); // Build a DYNALLOC node. - SDOperand Ops[3] = { Chain, NegSize, FPSIdx }; + SDValue Ops[3] = { Chain, NegSize, FPSIdx }; SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other); return DAG.getNode(PPCISD::DYNALLOC, VTs, Ops, 3); } -SDOperand PPCTargetLowering::LowerAtomicLOAD_ADD(SDOperand Op, SelectionDAG &DAG) { +SDValue PPCTargetLowering::LowerAtomicLOAD_ADD(SDValue Op, SelectionDAG &DAG) { MVT VT = Op.Val->getValueType(0); - SDOperand Chain = Op.getOperand(0); - SDOperand Ptr = Op.getOperand(1); - SDOperand Incr = Op.getOperand(2); + SDValue Chain = Op.getOperand(0); + SDValue Ptr = Op.getOperand(1); + SDValue Incr = Op.getOperand(2); SDVTList VTs = DAG.getVTList(VT, MVT::Other); - SDOperand Ops[] = { + SDValue Ops[] = { Chain, Ptr, Incr, @@ -2737,15 +2737,15 @@ SDOperand PPCTargetLowering::LowerAtomicLOAD_ADD(SDOperand Op, SelectionDAG &DAG return DAG.getNode(PPCISD::ATOMIC_LOAD_ADD, VTs, Ops, 3); } -SDOperand PPCTargetLowering::LowerAtomicCMP_SWAP(SDOperand Op, SelectionDAG &DAG) { +SDValue PPCTargetLowering::LowerAtomicCMP_SWAP(SDValue Op, SelectionDAG &DAG) { MVT VT = Op.Val->getValueType(0); - SDOperand Chain = Op.getOperand(0); - SDOperand Ptr = Op.getOperand(1); - SDOperand NewVal = Op.getOperand(2); - SDOperand OldVal = Op.getOperand(3); + SDValue Chain = Op.getOperand(0); + SDValue Ptr = Op.getOperand(1); + SDValue NewVal = Op.getOperand(2); + SDValue OldVal = Op.getOperand(3); SDVTList VTs = DAG.getVTList(VT, MVT::Other); - SDOperand Ops[] = { + SDValue Ops[] = { Chain, Ptr, OldVal, @@ -2754,14 +2754,14 @@ SDOperand PPCTargetLowering::LowerAtomicCMP_SWAP(SDOperand Op, SelectionDAG &DAG return DAG.getNode(PPCISD::ATOMIC_CMP_SWAP, VTs, Ops, 4); } -SDOperand PPCTargetLowering::LowerAtomicSWAP(SDOperand Op, SelectionDAG &DAG) { +SDValue PPCTargetLowering::LowerAtomicSWAP(SDValue Op, SelectionDAG &DAG) { MVT VT = Op.Val->getValueType(0); - SDOperand Chain = Op.getOperand(0); - SDOperand Ptr = Op.getOperand(1); - SDOperand NewVal = Op.getOperand(2); + SDValue Chain = Op.getOperand(0); + SDValue Ptr = Op.getOperand(1); + SDValue NewVal = Op.getOperand(2); SDVTList VTs = DAG.getVTList(VT, MVT::Other); - SDOperand Ops[] = { + SDValue Ops[] = { Chain, Ptr, NewVal, @@ -2771,21 +2771,21 @@ SDOperand PPCTargetLowering::LowerAtomicSWAP(SDOperand Op, SelectionDAG &DAG) { /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when /// possible. -SDOperand PPCTargetLowering::LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) { +SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { // Not FP? Not a fsel. if (!Op.getOperand(0).getValueType().isFloatingPoint() || !Op.getOperand(2).getValueType().isFloatingPoint()) - return SDOperand(); + return SDValue(); ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); // Cannot handle SETEQ/SETNE. - if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand(); + if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDValue(); MVT ResVT = Op.getValueType(); MVT CmpVT = Op.getOperand(0).getValueType(); - SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); - SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3); + SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); + SDValue TV = Op.getOperand(2), FV = Op.getOperand(3); // If the RHS of the comparison is a 0.0, we don't need to do the // subtraction at all. @@ -2815,7 +2815,7 @@ SDOperand PPCTargetLowering::LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) { DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV); } - SDOperand Cmp; + SDValue Cmp; switch (CC) { default: break; // SETUO etc aren't handled by fsel. case ISD::SETULT: @@ -2847,17 +2847,17 @@ SDOperand PPCTargetLowering::LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) { Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); } - return SDOperand(); + return SDValue(); } // FIXME: Split this code up when LegalizeDAGTypes lands. -SDOperand PPCTargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) { +SDValue PPCTargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) { assert(Op.getOperand(0).getValueType().isFloatingPoint()); - SDOperand Src = Op.getOperand(0); + SDValue Src = Op.getOperand(0); if (Src.getValueType() == MVT::f32) Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src); - SDOperand Tmp; + SDValue Tmp; switch (Op.getValueType().getSimpleVT()) { default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!"); case MVT::i32: @@ -2869,10 +2869,10 @@ SDOperand PPCTargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) { } // Convert the FP value to an int value through memory. - SDOperand FIPtr = DAG.CreateStackTemporary(MVT::f64); + SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64); // Emit a store to the stack slot. - SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Tmp, FIPtr, NULL, 0); + SDValue Chain = DAG.getStore(DAG.getEntryNode(), Tmp, FIPtr, NULL, 0); // Result is a load from the stack slot. If loading 4 bytes, make sure to // add in a bias. @@ -2882,20 +2882,20 @@ SDOperand PPCTargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) { return DAG.getLoad(Op.getValueType(), Chain, FIPtr, NULL, 0); } -SDOperand PPCTargetLowering::LowerFP_ROUND_INREG(SDOperand Op, +SDValue PPCTargetLowering::LowerFP_ROUND_INREG(SDValue Op, SelectionDAG &DAG) { assert(Op.getValueType() == MVT::ppcf128); SDNode *Node = Op.Val; assert(Node->getOperand(0).getValueType() == MVT::ppcf128); assert(Node->getOperand(0).Val->getOpcode() == ISD::BUILD_PAIR); - SDOperand Lo = Node->getOperand(0).Val->getOperand(0); - SDOperand Hi = Node->getOperand(0).Val->getOperand(1); + SDValue Lo = Node->getOperand(0).Val->getOperand(0); + SDValue Hi = Node->getOperand(0).Val->getOperand(1); // This sequence changes FPSCR to do round-to-zero, adds the two halves // of the long double, and puts FPSCR back the way it was. We do not // actually model FPSCR. std::vector<MVT> NodeTys; - SDOperand Ops[4], Result, MFFSreg, InFlag, FPreg; + SDValue Ops[4], Result, MFFSreg, InFlag, FPreg; NodeTys.push_back(MVT::f64); // Return register NodeTys.push_back(MVT::Flag); // Returns a flag for later insns @@ -2941,14 +2941,14 @@ SDOperand PPCTargetLowering::LowerFP_ROUND_INREG(SDOperand Op, return DAG.getNode(ISD::BUILD_PAIR, Lo.getValueType(), FPreg, FPreg); } -SDOperand PPCTargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { +SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) { // Don't handle ppc_fp128 here; let it be lowered to a libcall. if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64) - return SDOperand(); + return SDValue(); if (Op.getOperand(0).getValueType() == MVT::i64) { - SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0)); - SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits); + SDValue Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0)); + SDValue FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits); if (Op.getValueType() == MVT::f32) FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0)); return FP; @@ -2963,28 +2963,28 @@ SDOperand PPCTargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); int FrameIdx = FrameInfo->CreateStackObject(8, 8); MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); - SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); + SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); - SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32, + SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32, Op.getOperand(0)); // STD the extended value into the stack slot. MachineMemOperand MO(PseudoSourceValue::getFixedStack(FrameIdx), MachineMemOperand::MOStore, 0, 8, 8); - SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other, + SDValue Store = DAG.getNode(PPCISD::STD_32, MVT::Other, DAG.getEntryNode(), Ext64, FIdx, DAG.getMemOperand(MO)); // Load the value as a double. - SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0); + SDValue Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0); // FCFID it and return it. - SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld); + SDValue FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld); if (Op.getValueType() == MVT::f32) FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0)); return FP; } -SDOperand PPCTargetLowering::LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG) { +SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) { /* The rounding mode is in bits 30:31 of FPSR, and has the following settings: @@ -3008,29 +3008,29 @@ SDOperand PPCTargetLowering::LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG) { MVT VT = Op.getValueType(); MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); std::vector<MVT> NodeTys; - SDOperand MFFSreg, InFlag; + SDValue MFFSreg, InFlag; // Save FP Control Word to register NodeTys.push_back(MVT::f64); // return register NodeTys.push_back(MVT::Flag); // unused in this context - SDOperand Chain = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0); + SDValue Chain = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0); // Save FP register to stack slot int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); - SDOperand StackSlot = DAG.getFrameIndex(SSFI, PtrVT); - SDOperand Store = DAG.getStore(DAG.getEntryNode(), Chain, + SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT); + SDValue Store = DAG.getStore(DAG.getEntryNode(), Chain, StackSlot, NULL, 0); // Load FP Control Word from low 32 bits of stack slot. - SDOperand Four = DAG.getConstant(4, PtrVT); - SDOperand Addr = DAG.getNode(ISD::ADD, PtrVT, StackSlot, Four); - SDOperand CWD = DAG.getLoad(MVT::i32, Store, Addr, NULL, 0); + SDValue Four = DAG.getConstant(4, PtrVT); + SDValue Addr = DAG.getNode(ISD::ADD, PtrVT, StackSlot, Four); + SDValue CWD = DAG.getLoad(MVT::i32, Store, Addr, NULL, 0); // Transform as necessary - SDOperand CWD1 = + SDValue CWD1 = DAG.getNode(ISD::AND, MVT::i32, CWD, DAG.getConstant(3, MVT::i32)); - SDOperand CWD2 = + SDValue CWD2 = DAG.getNode(ISD::SRL, MVT::i32, DAG.getNode(ISD::AND, MVT::i32, DAG.getNode(ISD::XOR, MVT::i32, @@ -3038,14 +3038,14 @@ SDOperand PPCTargetLowering::LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG) { DAG.getConstant(3, MVT::i32)), DAG.getConstant(1, MVT::i8)); - SDOperand RetVal = + SDValue RetVal = DAG.getNode(ISD::XOR, MVT::i32, CWD1, CWD2); return DAG.getNode((VT.getSizeInBits() < 16 ? ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal); } -SDOperand PPCTargetLowering::LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG) { +SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) { MVT VT = Op.getValueType(); unsigned BitWidth = VT.getSizeInBits(); assert(Op.getNumOperands() == 3 && @@ -3054,26 +3054,26 @@ SDOperand PPCTargetLowering::LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG) { // Expand into a bunch of logical ops. Note that these ops // depend on the PPC behavior for oversized shift amounts. - SDOperand Lo = Op.getOperand(0); - SDOperand Hi = Op.getOperand(1); - SDOperand Amt = Op.getOperand(2); + SDValue Lo = Op.getOperand(0); + SDValue Hi = Op.getOperand(1); + SDValue Amt = Op.getOperand(2); MVT AmtVT = Amt.getValueType(); - SDOperand Tmp1 = DAG.getNode(ISD::SUB, AmtVT, + SDValue Tmp1 = DAG.getNode(ISD::SUB, AmtVT, DAG.getConstant(BitWidth, AmtVT), Amt); - SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, VT, Hi, Amt); - SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, VT, Lo, Tmp1); - SDOperand Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3); - SDOperand Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt, + SDValue Tmp2 = DAG.getNode(PPCISD::SHL, VT, Hi, Amt); + SDValue Tmp3 = DAG.getNode(PPCISD::SRL, VT, Lo, Tmp1); + SDValue Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3); + SDValue Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt, DAG.getConstant(-BitWidth, AmtVT)); - SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, VT, Lo, Tmp5); - SDOperand OutHi = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6); - SDOperand OutLo = DAG.getNode(PPCISD::SHL, VT, Lo, Amt); - SDOperand OutOps[] = { OutLo, OutHi }; + SDValue Tmp6 = DAG.getNode(PPCISD::SHL, VT, Lo, Tmp5); + SDValue OutHi = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6); + SDValue OutLo = DAG.getNode(PPCISD::SHL, VT, Lo, Amt); + SDValue OutOps[] = { OutLo, OutHi }; return DAG.getMergeValues(OutOps, 2); } -SDOperand PPCTargetLowering::LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) { +SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) { MVT VT = Op.getValueType(); unsigned BitWidth = VT.getSizeInBits(); assert(Op.getNumOperands() == 3 && @@ -3082,26 +3082,26 @@ SDOperand PPCTargetLowering::LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) { // Expand into a bunch of logical ops. Note that these ops // depend on the PPC behavior for oversized shift amounts. - SDOperand Lo = Op.getOperand(0); - SDOperand Hi = Op.getOperand(1); - SDOperand Amt = Op.getOperand(2); + SDValue Lo = Op.getOperand(0); + SDValue Hi = Op.getOperand(1); + SDValue Amt = Op.getOperand(2); MVT AmtVT = Amt.getValueType(); - SDOperand Tmp1 = DAG.getNode(ISD::SUB, AmtVT, + SDValue Tmp1 = DAG.getNode(ISD::SUB, AmtVT, DAG.getConstant(BitWidth, AmtVT), Amt); - SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, VT, Lo, Amt); - SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, VT, Hi, Tmp1); - SDOperand Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3); - SDOperand Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt, + SDValue Tmp2 = DAG.getNode(PPCISD::SRL, VT, Lo, Amt); + SDValue Tmp3 = DAG.getNode(PPCISD::SHL, VT, Hi, Tmp1); + SDValue Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3); + SDValue Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt, DAG.getConstant(-BitWidth, AmtVT)); - SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, VT, Hi, Tmp5); - SDOperand OutLo = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6); - SDOperand OutHi = DAG.getNode(PPCISD::SRL, VT, Hi, Amt); - SDOperand OutOps[] = { OutLo, OutHi }; + SDValue Tmp6 = DAG.getNode(PPCISD::SRL, VT, Hi, Tmp5); + SDValue OutLo = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6); + SDValue OutHi = DAG.getNode(PPCISD::SRL, VT, Hi, Amt); + SDValue OutOps[] = { OutLo, OutHi }; return DAG.getMergeValues(OutOps, 2); } -SDOperand PPCTargetLowering::LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) { +SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) { MVT VT = Op.getValueType(); unsigned BitWidth = VT.getSizeInBits(); assert(Op.getNumOperands() == 3 && @@ -3109,23 +3109,23 @@ SDOperand PPCTargetLowering::LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) { "Unexpected SRA!"); // Expand into a bunch of logical ops, followed by a select_cc. - SDOperand Lo = Op.getOperand(0); - SDOperand Hi = Op.getOperand(1); - SDOperand Amt = Op.getOperand(2); + SDValue Lo = Op.getOperand(0); + SDValue Hi = Op.getOperand(1); + SDValue Amt = Op.getOperand(2); MVT AmtVT = Amt.getValueType(); - SDOperand Tmp1 = DAG.getNode(ISD::SUB, AmtVT, + SDValue Tmp1 = DAG.getNode(ISD::SUB, AmtVT, DAG.getConstant(BitWidth, AmtVT), Amt); - SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, VT, Lo, Amt); - SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, VT, Hi, Tmp1); - SDOperand Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3); - SDOperand Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt, + SDValue Tmp2 = DAG.getNode(PPCISD::SRL, VT, Lo, Amt); + SDValue Tmp3 = DAG.getNode(PPCISD::SHL, VT, Hi, Tmp1); + SDValue Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3); + SDValue Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt, DAG.getConstant(-BitWidth, AmtVT)); - SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, VT, Hi, Tmp5); - SDOperand OutHi = DAG.getNode(PPCISD::SRA, VT, Hi, Amt); - SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, AmtVT), + SDValue Tmp6 = DAG.getNode(PPCISD::SRA, VT, Hi, Tmp5); + SDValue OutHi = DAG.getNode(PPCISD::SRA, VT, Hi, Amt); + SDValue OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, AmtVT), Tmp4, Tmp6, ISD::SETLE); - SDOperand OutOps[] = { OutLo, OutHi }; + SDValue OutOps[] = { OutLo, OutHi }; return DAG.getMergeValues(OutOps, 2); } @@ -3145,7 +3145,7 @@ static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2], unsigned EltBitSize = BV->getOperand(0).getValueType().getSizeInBits(); for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { - SDOperand OpVal = BV->getOperand(i); + SDValue OpVal = BV->getOperand(i); unsigned PartNo = i >= e/2; // In the upper 128 bits? unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t. @@ -3229,7 +3229,7 @@ static bool isConstantSplat(const uint64_t Bits128[2], /// BuildSplatI - Build a canonical splati of Val with an element size of /// SplatSize. Cast the result to VT. -static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT VT, +static SDValue BuildSplatI(int Val, unsigned SplatSize, MVT VT, SelectionDAG &DAG) { assert(Val >= -16 && Val <= 15 && "vsplti is out of range!"); @@ -3246,17 +3246,17 @@ static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT VT, MVT CanonicalVT = VTys[SplatSize-1]; // Build a canonical splat for this value. - SDOperand Elt = DAG.getConstant(Val, CanonicalVT.getVectorElementType()); - SmallVector<SDOperand, 8> Ops; + SDValue Elt = DAG.getConstant(Val, CanonicalVT.getVectorElementType()); + SmallVector<SDValue, 8> Ops; Ops.assign(CanonicalVT.getVectorNumElements(), Elt); - SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT, + SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT, &Ops[0], Ops.size()); return DAG.getNode(ISD::BIT_CONVERT, ReqVT, Res); } /// BuildIntrinsicOp - Return a binary operator intrinsic node with the /// specified intrinsic ID. -static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS, +static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS, SelectionDAG &DAG, MVT DestVT = MVT::Other) { if (DestVT == MVT::Other) DestVT = LHS.getValueType(); @@ -3266,8 +3266,8 @@ static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS, /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the /// specified intrinsic ID. -static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1, - SDOperand Op2, SelectionDAG &DAG, +static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1, + SDValue Op2, SelectionDAG &DAG, MVT DestVT = MVT::Other) { if (DestVT == MVT::Other) DestVT = Op0.getValueType(); return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT, @@ -3277,16 +3277,16 @@ static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1, /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified /// amount. The result has the specified value type. -static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt, +static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt, MVT VT, SelectionDAG &DAG) { // Force LHS/RHS to be the right type. LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS); RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS); - SDOperand Ops[16]; + SDValue Ops[16]; for (unsigned i = 0; i != 16; ++i) Ops[i] = DAG.getConstant(i+Amt, MVT::i8); - SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS, + SDValue T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS, DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops,16)); return DAG.getNode(ISD::BIT_CONVERT, VT, T); } @@ -3296,7 +3296,7 @@ static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt, // selects to a single instruction, return Op. Otherwise, if we can codegen // this case more efficiently than a constant pool load, lower it to the // sequence of ops that should be used. -SDOperand PPCTargetLowering::LowerBUILD_VECTOR(SDOperand Op, +SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { // If this is a vector of constants or undefs, get the bits. A bit in // UndefBits is set if the corresponding element of the vector is an @@ -3305,7 +3305,7 @@ SDOperand PPCTargetLowering::LowerBUILD_VECTOR(SDOperand Op, uint64_t VectorBits[2]; uint64_t UndefBits[2]; if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits)) - return SDOperand(); // Not a constant vector. + return SDValue(); // Not a constant vector. // If this is a splat (repetition) of a value across the whole vector, return // the smallest size that splats it. For example, "0x01010101010101..." is a @@ -3321,7 +3321,7 @@ SDOperand PPCTargetLowering::LowerBUILD_VECTOR(SDOperand Op, if (SplatBits == 0) { // Canonicalize all zero vectors to be v4i32. if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) { - SDOperand Z = DAG.getConstant(0, MVT::i32); + SDValue Z = DAG.getConstant(0, MVT::i32); Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z); Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z); } @@ -3339,7 +3339,7 @@ SDOperand PPCTargetLowering::LowerBUILD_VECTOR(SDOperand Op, // If this value is in the range [-32,30] and is even, use: // tmp = VSPLTI[bhw], result = add tmp, tmp if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) { - SDOperand Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG); + SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG); Res = DAG.getNode(ISD::ADD, Res.getValueType(), Res, Res); return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); } @@ -3349,10 +3349,10 @@ SDOperand PPCTargetLowering::LowerBUILD_VECTOR(SDOperand Op, // for fneg/fabs. if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) { // Make -1 and vspltisw -1: - SDOperand OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG); + SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG); // Make the VSLW intrinsic, computing 0x8000_0000. - SDOperand Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV, + SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV, OnesV, DAG); // xor by OnesV to invert it. @@ -3378,7 +3378,7 @@ SDOperand PPCTargetLowering::LowerBUILD_VECTOR(SDOperand Op, // vsplti + shl self. if (SextVal == (i << (int)TypeShiftAmt)) { - SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); + SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); static const unsigned IIDs[] = { // Intrinsic to use for each size. Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0, Intrinsic::ppc_altivec_vslw @@ -3389,7 +3389,7 @@ SDOperand PPCTargetLowering::LowerBUILD_VECTOR(SDOperand Op, // vsplti + srl self. if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { - SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); + SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); static const unsigned IIDs[] = { // Intrinsic to use for each size. Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0, Intrinsic::ppc_altivec_vsrw @@ -3400,7 +3400,7 @@ SDOperand PPCTargetLowering::LowerBUILD_VECTOR(SDOperand Op, // vsplti + sra self. if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { - SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); + SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); static const unsigned IIDs[] = { // Intrinsic to use for each size. Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0, Intrinsic::ppc_altivec_vsraw @@ -3412,7 +3412,7 @@ SDOperand PPCTargetLowering::LowerBUILD_VECTOR(SDOperand Op, // vsplti + rol self. if (SextVal == (int)(((unsigned)i << TypeShiftAmt) | ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) { - SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); + SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); static const unsigned IIDs[] = { // Intrinsic to use for each size. Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0, Intrinsic::ppc_altivec_vrlw @@ -3423,17 +3423,17 @@ SDOperand PPCTargetLowering::LowerBUILD_VECTOR(SDOperand Op, // t = vsplti c, result = vsldoi t, t, 1 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) { - SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); + SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG); } // t = vsplti c, result = vsldoi t, t, 2 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) { - SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); + SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG); } // t = vsplti c, result = vsldoi t, t, 3 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) { - SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); + SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG); } } @@ -3442,27 +3442,27 @@ SDOperand PPCTargetLowering::LowerBUILD_VECTOR(SDOperand Op, // Odd, in range [17,31]: (vsplti C)-(vsplti -16). if (SextVal >= 0 && SextVal <= 31) { - SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG); - SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG); + SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG); + SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG); LHS = DAG.getNode(ISD::SUB, LHS.getValueType(), LHS, RHS); return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS); } // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16). if (SextVal >= -31 && SextVal <= 0) { - SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG); - SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG); + SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG); + SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG); LHS = DAG.getNode(ISD::ADD, LHS.getValueType(), LHS, RHS); return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS); } } - return SDOperand(); + return SDValue(); } /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit /// the specified operations to build the shuffle. -static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS, - SDOperand RHS, SelectionDAG &DAG) { +static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, + SDValue RHS, SelectionDAG &DAG) { unsigned OpNum = (PFEntry >> 26) & 0x0F; unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1); unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); @@ -3486,7 +3486,7 @@ static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS, return RHS; } - SDOperand OpLHS, OpRHS; + SDValue OpLHS, OpRHS; OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG); OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG); @@ -3528,7 +3528,7 @@ static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS, case OP_VSLDOI12: return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG); } - SDOperand Ops[16]; + SDValue Ops[16]; for (unsigned i = 0; i != 16; ++i) Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i8); @@ -3540,11 +3540,11 @@ static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS, /// is a shuffle we can handle in a single instruction, return it. Otherwise, /// return the code it can be lowered into. Worst case, it can always be /// lowered into a vperm. -SDOperand PPCTargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, +SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { - SDOperand V1 = Op.getOperand(0); - SDOperand V2 = Op.getOperand(1); - SDOperand PermMask = Op.getOperand(2); + SDValue V1 = Op.getOperand(0); + SDValue V2 = Op.getOperand(1); + SDValue PermMask = Op.getOperand(2); // Cases that are handled by instructions that take permute immediates // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be @@ -3642,7 +3642,7 @@ SDOperand PPCTargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, MVT EltVT = V1.getValueType().getVectorElementType(); unsigned BytesPerElement = EltVT.getSizeInBits()/8; - SmallVector<SDOperand, 16> ResultMask; + SmallVector<SDValue, 16> ResultMask; for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) { unsigned SrcElt; if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF) @@ -3655,7 +3655,7 @@ SDOperand PPCTargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, MVT::i8)); } - SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, + SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, &ResultMask[0], ResultMask.size()); return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask); } @@ -3663,7 +3663,7 @@ SDOperand PPCTargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an /// altivec comparison. If it is, return true and fill in Opc/isDot with /// information about the intrinsic. -static bool getAltivecCompareInfo(SDOperand Intrin, int &CompareOpc, +static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc, bool &isDot) { unsigned IntrinsicID = cast<ConstantSDNode>(Intrin.getOperand(0))->getValue(); CompareOpc = -1; @@ -3705,25 +3705,25 @@ static bool getAltivecCompareInfo(SDOperand Intrin, int &CompareOpc, /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom /// lower, do it, otherwise return null. -SDOperand PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op, +SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) { // If this is a lowered altivec predicate compare, CompareOpc is set to the // opcode number of the comparison. int CompareOpc; bool isDot; if (!getAltivecCompareInfo(Op, CompareOpc, isDot)) - return SDOperand(); // Don't custom lower most intrinsics. + return SDValue(); // Don't custom lower most intrinsics. // If this is a non-dot comparison, make the VCMP node and we are done. if (!isDot) { - SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(), + SDValue Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(), Op.getOperand(1), Op.getOperand(2), DAG.getConstant(CompareOpc, MVT::i32)); return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp); } // Create the PPCISD altivec 'dot' comparison node. - SDOperand Ops[] = { + SDValue Ops[] = { Op.getOperand(2), // LHS Op.getOperand(3), // RHS DAG.getConstant(CompareOpc, MVT::i32) @@ -3731,11 +3731,11 @@ SDOperand PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op, std::vector<MVT> VTs; VTs.push_back(Op.getOperand(2).getValueType()); VTs.push_back(MVT::Flag); - SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3); + SDValue CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3); // Now that we have the comparison, emit a copy from the CR to a GPR. // This is flagged to the above dot comparison. - SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32, + SDValue Flags = DAG.getNode(PPCISD::MFCR, MVT::i32, DAG.getRegister(PPC::CR6, MVT::i32), CompNode.getValue(1)); @@ -3772,29 +3772,29 @@ SDOperand PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op, return Flags; } -SDOperand PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDOperand Op, +SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) { // Create a stack slot that is 16-byte aligned. MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); int FrameIdx = FrameInfo->CreateStackObject(16, 16); MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); - SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); + SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); // Store the input value into Value#0 of the stack slot. - SDOperand Store = DAG.getStore(DAG.getEntryNode(), + SDValue Store = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0), FIdx, NULL, 0); // Load it out. return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0); } -SDOperand PPCTargetLowering::LowerMUL(SDOperand Op, SelectionDAG &DAG) { +SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) { if (Op.getValueType() == MVT::v4i32) { - SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); + SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); - SDOperand Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG); - SDOperand Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt. + SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG); + SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt. - SDOperand RHSSwap = // = vrlw RHS, 16 + SDValue RHSSwap = // = vrlw RHS, 16 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG); // Shrinkify inputs to v8i16. @@ -3804,36 +3804,36 @@ SDOperand PPCTargetLowering::LowerMUL(SDOperand Op, SelectionDAG &DAG) { // Low parts multiplied together, generating 32-bit results (we ignore the // top parts). - SDOperand LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh, + SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh, LHS, RHS, DAG, MVT::v4i32); - SDOperand HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm, + SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm, LHS, RHSSwap, Zero, DAG, MVT::v4i32); // Shift the high parts up 16 bits. HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG); return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd); } else if (Op.getValueType() == MVT::v8i16) { - SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); + SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); - SDOperand Zero = BuildSplatI(0, 1, MVT::v8i16, DAG); + SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG); return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm, LHS, RHS, Zero, DAG); } else if (Op.getValueType() == MVT::v16i8) { - SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); + SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); // Multiply the even 8-bit parts, producing 16-bit sums. - SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub, + SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub, LHS, RHS, DAG, MVT::v8i16); EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts); // Multiply the odd 8-bit parts, producing 16-bit sums. - SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub, + SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub, LHS, RHS, DAG, MVT::v8i16); OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts); // Merge the results together. - SDOperand Ops[16]; + SDValue Ops[16]; for (unsigned i = 0; i != 8; ++i) { Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8); Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8); @@ -3848,7 +3848,7 @@ SDOperand PPCTargetLowering::LowerMUL(SDOperand Op, SelectionDAG &DAG) { /// LowerOperation - Provide custom lowering hooks for some operations. /// -SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { +SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { switch (Op.getOpcode()) { default: assert(0 && "Wasn't expecting to be able to lower this!"); case ISD::ConstantPool: return LowerConstantPool(Op, DAG); @@ -3902,14 +3902,14 @@ SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); } - return SDOperand(); + return SDValue(); } SDNode *PPCTargetLowering::ReplaceNodeResults(SDNode *N, SelectionDAG &DAG) { switch (N->getOpcode()) { default: assert(0 && "Wasn't expecting to be able to lower this!"); case ISD::FP_TO_SINT: { - SDOperand Res = LowerFP_TO_SINT(SDOperand(N, 0), DAG); + SDValue Res = LowerFP_TO_SINT(SDValue(N, 0), DAG); // Use MERGE_VALUES to drop the chain result value and get a node with one // result. This requires turning off getMergeValues simplification, since // otherwise it will give us Res back. @@ -4127,7 +4127,7 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, // Target Optimization Hooks //===----------------------------------------------------------------------===// -SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N, +SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { TargetMachine &TM = getTargetMachine(); SelectionDAG &DAG = DCI.DAG; @@ -4161,7 +4161,7 @@ SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N, // type must be i64. if (N->getOperand(0).getValueType() == MVT::i64 && N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) { - SDOperand Val = N->getOperand(0).getOperand(0); + SDValue Val = N->getOperand(0).getOperand(0); if (Val.getValueType() == MVT::f32) { Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val); DCI.AddToWorklist(Val.Val); @@ -4191,7 +4191,7 @@ SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N, N->getOperand(1).getOpcode() == ISD::FP_TO_SINT && N->getOperand(1).getValueType() == MVT::i32 && N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) { - SDOperand Val = N->getOperand(1).getOperand(0); + SDValue Val = N->getOperand(1).getOperand(0); if (Val.getValueType() == MVT::f32) { Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val); DCI.AddToWorklist(Val.Val); @@ -4210,7 +4210,7 @@ SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N, N->getOperand(1).Val->hasOneUse() && (N->getOperand(1).getValueType() == MVT::i32 || N->getOperand(1).getValueType() == MVT::i16)) { - SDOperand BSwapOp = N->getOperand(1).getOperand(0); + SDValue BSwapOp = N->getOperand(1).getOperand(0); // Do an any-extend to 32-bits if this is a half-word input. if (BSwapOp.getValueType() == MVT::i16) BSwapOp = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BSwapOp); @@ -4225,23 +4225,23 @@ SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N, if (ISD::isNON_EXTLoad(N->getOperand(0).Val) && N->getOperand(0).hasOneUse() && (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) { - SDOperand Load = N->getOperand(0); + SDValue Load = N->getOperand(0); LoadSDNode *LD = cast<LoadSDNode>(Load); // Create the byte-swapping load. std::vector<MVT> VTs; VTs.push_back(MVT::i32); VTs.push_back(MVT::Other); - SDOperand MO = DAG.getMemOperand(LD->getMemOperand()); - SDOperand Ops[] = { + SDValue MO = DAG.getMemOperand(LD->getMemOperand()); + SDValue Ops[] = { LD->getChain(), // Chain LD->getBasePtr(), // Ptr MO, // MemOperand DAG.getValueType(N->getValueType(0)) // VT }; - SDOperand BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4); + SDValue BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4); // If this is an i16 load, insert the truncate. - SDOperand ResVal = BSLoad; + SDValue ResVal = BSLoad; if (N->getValueType(0) == MVT::i16) ResVal = DAG.getNode(ISD::TRUNCATE, MVT::i16, BSLoad); @@ -4254,7 +4254,7 @@ SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N, DCI.CombineTo(Load.Val, ResVal, BSLoad.getValue(1)); // Return N so it doesn't get rechecked! - return SDOperand(N, 0); + return SDValue(N, 0); } break; @@ -4295,7 +4295,7 @@ SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N, assert(UI != VCMPoNode->use_end() && "Didn't find user!"); SDNode *User = *UI; for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { - if (User->getOperand(i) == SDOperand(VCMPoNode, 1)) { + if (User->getOperand(i) == SDValue(VCMPoNode, 1)) { FlagUser = User; break; } @@ -4305,7 +4305,7 @@ SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N, // If the user is a MFCR instruction, we know this is safe. Otherwise we // give up for right now. if (FlagUser->getOpcode() == PPCISD::MFCR) - return SDOperand(VCMPoNode, 0); + return SDValue(VCMPoNode, 0); } break; } @@ -4315,7 +4315,7 @@ SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N, // lowering is done pre-legalize, because the legalizer lowers the predicate // compare down to code that is difficult to reassemble. ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); - SDOperand LHS = N->getOperand(2), RHS = N->getOperand(3); + SDValue LHS = N->getOperand(2), RHS = N->getOperand(3); int CompareOpc; bool isDot; @@ -4339,14 +4339,14 @@ SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N, // Create the PPCISD altivec 'dot' comparison node. std::vector<MVT> VTs; - SDOperand Ops[] = { + SDValue Ops[] = { LHS.getOperand(2), // LHS of compare LHS.getOperand(3), // RHS of compare DAG.getConstant(CompareOpc, MVT::i32) }; VTs.push_back(LHS.getOperand(2).getValueType()); VTs.push_back(MVT::Flag); - SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3); + SDValue CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3); // Unpack the result based on how the target uses it. PPC::Predicate CompOpc; @@ -4375,14 +4375,14 @@ SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N, } } - return SDOperand(); + return SDValue(); } //===----------------------------------------------------------------------===// // Inline Assembly Support //===----------------------------------------------------------------------===// -void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, +void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, const APInt &Mask, APInt &KnownZero, APInt &KnownOne, @@ -4469,10 +4469,10 @@ PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops /// vector. If it is invalid, don't add anything to Ops. -void PPCTargetLowering::LowerAsmOperandForConstraint(SDOperand Op, char Letter, - std::vector<SDOperand>&Ops, +void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op, char Letter, + std::vector<SDValue>&Ops, SelectionDAG &DAG) const { - SDOperand Result(0,0); + SDValue Result(0,0); switch (Letter) { default: break; case 'I': @@ -4579,16 +4579,16 @@ bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const { return false; } -SDOperand PPCTargetLowering::LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) { +SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) { // Depths > 0 not supported yet! if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0) - return SDOperand(); + return SDValue(); MachineFunction &MF = DAG.getMachineFunction(); PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); // Just load the return address off the stack. - SDOperand RetAddrFI = getReturnAddrFrameIndex(DAG); + SDValue RetAddrFI = getReturnAddrFrameIndex(DAG); // Make sure the function really does not optimize away the store of the RA // to the stack. @@ -4596,10 +4596,10 @@ SDOperand PPCTargetLowering::LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) { return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0); } -SDOperand PPCTargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) { +SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { // Depths > 0 not supported yet! if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0) - return SDOperand(); + return SDValue(); MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); bool isPPC64 = PtrVT == MVT::i64; diff --git a/lib/Target/PowerPC/PPCISelLowering.h b/lib/Target/PowerPC/PPCISelLowering.h index 7f6d445..75f4e13 100644 --- a/lib/Target/PowerPC/PPCISelLowering.h +++ b/lib/Target/PowerPC/PPCISelLowering.h @@ -215,7 +215,7 @@ namespace llvm { /// formed by using a vspltis[bhw] instruction of the specified element /// size, return the constant being splatted. The ByteSize field indicates /// the number of bytes of each element [124] -> [bhw]. - SDOperand get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG); + SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG); } class PPCTargetLowering : public TargetLowering { @@ -236,49 +236,49 @@ namespace llvm { virtual const char *getTargetNodeName(unsigned Opcode) const; /// getSetCCResultType - Return the ISD::SETCC ValueType - virtual MVT getSetCCResultType(const SDOperand &) const; + virtual MVT getSetCCResultType(const SDValue &) const; /// getPreIndexedAddressParts - returns true by value, base pointer and /// offset pointer and addressing mode by reference if the node's address /// can be legally represented as pre-indexed load / store address. - virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base, - SDOperand &Offset, + virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, + SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG); /// SelectAddressRegReg - Given the specified addressed, check to see if it /// can be represented as an indexed [r+r] operation. Returns false if it /// can be more efficiently represented with [r+imm]. - bool SelectAddressRegReg(SDOperand N, SDOperand &Base, SDOperand &Index, + bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG); /// SelectAddressRegImm - Returns true if the address N can be represented /// by a base register plus a signed 16-bit displacement [r+imm], and if it /// is not better represented as reg+reg. - bool SelectAddressRegImm(SDOperand N, SDOperand &Disp, SDOperand &Base, + bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG); /// SelectAddressRegRegOnly - Given the specified addressed, force it to be /// represented as an indexed [r+r] operation. - bool SelectAddressRegRegOnly(SDOperand N, SDOperand &Base, SDOperand &Index, + bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG); /// SelectAddressRegImmShift - Returns true if the address N can be /// represented by a base register plus a signed 14-bit displacement /// [r+imm*4]. Suitable for use by STD and friends. - bool SelectAddressRegImmShift(SDOperand N, SDOperand &Disp, SDOperand &Base, + bool SelectAddressRegImmShift(SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG); /// LowerOperation - Provide custom lowering hooks for some operations. /// - virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); + virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); virtual SDNode *ReplaceNodeResults(SDNode *N, SelectionDAG &DAG); - virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; + virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; - virtual void computeMaskedBitsForTargetNode(const SDOperand Op, + virtual void computeMaskedBitsForTargetNode(const SDValue Op, const APInt &Mask, APInt &KnownZero, APInt &KnownOne, @@ -300,9 +300,9 @@ namespace llvm { /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops /// vector. If it is invalid, don't add anything to Ops. - virtual void LowerAsmOperandForConstraint(SDOperand Op, + virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter, - std::vector<SDOperand> &Ops, + std::vector<SDValue> &Ops, SelectionDAG &DAG) const; /// isLegalAddressingMode - Return true if the addressing mode represented @@ -321,63 +321,63 @@ namespace llvm { /// IsEligibleForTailCallOptimization - Check whether the call is eligible /// for tail call optimization. Target which want to do tail call /// optimization should implement this function. - virtual bool IsEligibleForTailCallOptimization(SDOperand Call, - SDOperand Ret, + virtual bool IsEligibleForTailCallOptimization(SDValue Call, + SDValue Ret, SelectionDAG &DAG) const; private: - SDOperand getFramePointerFrameIndex(SelectionDAG & DAG) const; - SDOperand getReturnAddrFrameIndex(SelectionDAG & DAG) const; + SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const; + SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const; - SDOperand EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG, + SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG, int SPDiff, - SDOperand Chain, - SDOperand &LROpOut, - SDOperand &FPOpOut); - - SDOperand LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG, + SDValue Chain, + SDValue &LROpOut, + SDValue &FPOpOut); + + SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG); + SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG); + SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG); + SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG); + SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG); + SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG); + SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG); + SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, int VarArgsFrameIndex, int VarArgsStackOffset, unsigned VarArgsNumGPR, unsigned VarArgsNumFPR, const PPCSubtarget &Subtarget); - SDOperand LowerVAARG(SDOperand Op, SelectionDAG &DAG, int VarArgsFrameIndex, + SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG, int VarArgsFrameIndex, int VarArgsStackOffset, unsigned VarArgsNumGPR, unsigned VarArgsNumFPR, const PPCSubtarget &Subtarget); - SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, + SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG, int &VarArgsFrameIndex, int &VarArgsStackOffset, unsigned &VarArgsNumGPR, unsigned &VarArgsNumFPR, const PPCSubtarget &Subtarget); - SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG, + SDValue LowerCALL(SDValue Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget, TargetMachine &TM); - SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG, TargetMachine &TM); - SDOperand LowerSTACKRESTORE(SDOperand Op, SelectionDAG &DAG, + SDValue LowerRET(SDValue Op, SelectionDAG &DAG, TargetMachine &TM); + SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget); - SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG, + SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget); - SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerAtomicLOAD_ADD(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerAtomicCMP_SWAP(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerAtomicSWAP(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerFP_ROUND_INREG(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG); + SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG); + SDValue LowerAtomicLOAD_ADD(SDValue Op, SelectionDAG &DAG); + SDValue LowerAtomicCMP_SWAP(SDValue Op, SelectionDAG &DAG); + SDValue LowerAtomicSWAP(SDValue Op, SelectionDAG &DAG); + SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG); + SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG); + SDValue LowerFP_ROUND_INREG(SDValue Op, SelectionDAG &DAG); + SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG); + SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG); + SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG); + SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG); + SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG); + SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG); + SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG); + SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG); + SDValue LowerMUL(SDValue Op, SelectionDAG &DAG); }; } diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp index d1d2b5b..7d2d11e 100644 --- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp +++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp @@ -40,12 +40,12 @@ public: Subtarget(TM.getSubtarget<SparcSubtarget>()) { } - SDNode *Select(SDOperand Op); + SDNode *Select(SDValue Op); // Complex Pattern Selectors. - bool SelectADDRrr(SDOperand Op, SDOperand N, SDOperand &R1, SDOperand &R2); - bool SelectADDRri(SDOperand Op, SDOperand N, SDOperand &Base, - SDOperand &Offset); + bool SelectADDRrr(SDValue Op, SDValue N, SDValue &R1, SDValue &R2); + bool SelectADDRri(SDValue Op, SDValue N, SDValue &Base, + SDValue &Offset); /// InstructionSelect - This callback is invoked by /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. @@ -70,8 +70,8 @@ void SparcDAGToDAGISel::InstructionSelect(SelectionDAG &DAG) { DAG.RemoveDeadNodes(); } -bool SparcDAGToDAGISel::SelectADDRri(SDOperand Op, SDOperand Addr, - SDOperand &Base, SDOperand &Offset) { +bool SparcDAGToDAGISel::SelectADDRri(SDValue Op, SDValue Addr, + SDValue &Base, SDValue &Offset) { if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) { Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); Offset = CurDAG->getTargetConstant(0, MVT::i32); @@ -111,8 +111,8 @@ bool SparcDAGToDAGISel::SelectADDRri(SDOperand Op, SDOperand Addr, return true; } -bool SparcDAGToDAGISel::SelectADDRrr(SDOperand Op, SDOperand Addr, - SDOperand &R1, SDOperand &R2) { +bool SparcDAGToDAGISel::SelectADDRrr(SDValue Op, SDValue Addr, + SDValue &R1, SDValue &R2) { if (Addr.getOpcode() == ISD::FrameIndex) return false; if (Addr.getOpcode() == ISD::TargetExternalSymbol || Addr.getOpcode() == ISD::TargetGlobalAddress) @@ -135,7 +135,7 @@ bool SparcDAGToDAGISel::SelectADDRrr(SDOperand Op, SDOperand Addr, return true; } -SDNode *SparcDAGToDAGISel::Select(SDOperand Op) { +SDNode *SparcDAGToDAGISel::Select(SDValue Op) { SDNode *N = Op.Val; if (N->isMachineOpcode()) return NULL; // Already selected. @@ -145,20 +145,20 @@ SDNode *SparcDAGToDAGISel::Select(SDOperand Op) { case ISD::SDIV: case ISD::UDIV: { // FIXME: should use a custom expander to expose the SRA to the dag. - SDOperand DivLHS = N->getOperand(0); - SDOperand DivRHS = N->getOperand(1); + SDValue DivLHS = N->getOperand(0); + SDValue DivRHS = N->getOperand(1); AddToISelQueue(DivLHS); AddToISelQueue(DivRHS); // Set the Y register to the high-part. - SDOperand TopPart; + SDValue TopPart; if (N->getOpcode() == ISD::SDIV) { - TopPart = SDOperand(CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS, + TopPart = SDValue(CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS, CurDAG->getTargetConstant(31, MVT::i32)), 0); } else { TopPart = CurDAG->getRegister(SP::G0, MVT::i32); } - TopPart = SDOperand(CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart, + TopPart = SDValue(CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart, CurDAG->getRegister(SP::G0, MVT::i32)), 0); // FIXME: Handle div by immediate. @@ -169,15 +169,15 @@ SDNode *SparcDAGToDAGISel::Select(SDOperand Op) { case ISD::MULHU: case ISD::MULHS: { // FIXME: Handle mul by immediate. - SDOperand MulLHS = N->getOperand(0); - SDOperand MulRHS = N->getOperand(1); + SDValue MulLHS = N->getOperand(0); + SDValue MulRHS = N->getOperand(1); AddToISelQueue(MulLHS); AddToISelQueue(MulRHS); unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr; SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag, MulLHS, MulRHS); // The high part is in the Y register. - return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1)); + return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDValue(Mul, 1)); return NULL; } } diff --git a/lib/Target/Sparc/SparcISelLowering.cpp b/lib/Target/Sparc/SparcISelLowering.cpp index 342caf8..e0c4335 100644 --- a/lib/Target/Sparc/SparcISelLowering.cpp +++ b/lib/Target/Sparc/SparcISelLowering.cpp @@ -30,7 +30,7 @@ using namespace llvm; #include "SparcGenCallingConv.inc" -static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { +static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) { // CCValAssign - represent the assignment of the return value to locations. SmallVector<CCValAssign, 16> RVLocs; unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); @@ -50,8 +50,8 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); } - SDOperand Chain = Op.getOperand(0); - SDOperand Flag; + SDValue Chain = Op.getOperand(0); + SDValue Flag; // Copy the result values into the output registers. for (unsigned i = 0; i != RVLocs.size(); ++i) { @@ -76,7 +76,7 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { /// in FP registers for fastcc functions. void SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG, - SmallVectorImpl<SDOperand> &ArgValues) { + SmallVectorImpl<SDValue> &ArgValues) { MachineFunction &MF = DAG.getMachineFunction(); MachineRegisterInfo &RegInfo = MF.getRegInfo(); @@ -87,8 +87,8 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG, const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6; unsigned ArgOffset = 68; - SDOperand Root = DAG.getRoot(); - std::vector<SDOperand> OutChains; + SDValue Root = DAG.getRoot(); + std::vector<SDValue> OutChains; for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { MVT ObjectVT = getValueType(I->getType()); @@ -105,7 +105,7 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG, } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); MF.getRegInfo().addLiveIn(*CurArgReg++, VReg); - SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); + SDValue Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); if (ObjectVT != MVT::i32) { unsigned AssertOp = ISD::AssertSext; Arg = DAG.getNode(AssertOp, MVT::i32, Arg, @@ -115,8 +115,8 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG, ArgValues.push_back(Arg); } else { int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); - SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); - SDOperand Load; + SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); + SDValue Load; if (ObjectVT == MVT::i32) { Load = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0); } else { @@ -143,14 +143,14 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG, // FP value is passed in an integer register. unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); MF.getRegInfo().addLiveIn(*CurArgReg++, VReg); - SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); + SDValue Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg); ArgValues.push_back(Arg); } else { int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); - SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); - SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, NULL, 0); + SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); + SDValue Load = DAG.getLoad(MVT::f32, Root, FIPtr, NULL, 0); ArgValues.push_back(Load); } ArgOffset += 4; @@ -163,30 +163,30 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG, if (CurArgReg < ArgRegEnd) ++CurArgReg; ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); } else { - SDOperand HiVal; + SDValue HiVal; if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); MF.getRegInfo().addLiveIn(*CurArgReg++, VRegHi); HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32); } else { int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); - SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); + SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0); } - SDOperand LoVal; + SDValue LoVal; if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR unsigned VRegLo = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); MF.getRegInfo().addLiveIn(*CurArgReg++, VRegLo); LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32); } else { int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4); - SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); + SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0); } // Compose the two halves together into an i64 unit. - SDOperand WholeValue = + SDValue WholeValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal); // If we want a double, do a bit convert. @@ -208,10 +208,10 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG, for (; CurArgReg != ArgRegEnd; ++CurArgReg) { unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); MF.getRegInfo().addLiveIn(*CurArgReg, VReg); - SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); + SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); - SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); + SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); OutChains.push_back(DAG.getStore(DAG.getRoot(), Arg, FIPtr, NULL, 0)); ArgOffset += 4; @@ -223,10 +223,10 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG, &OutChains[0], OutChains.size())); } -static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) { +static SDValue LowerCALL(SDValue Op, SelectionDAG &DAG) { unsigned CallingConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); - SDOperand Chain = Op.getOperand(0); - SDOperand Callee = Op.getOperand(4); + SDValue Chain = Op.getOperand(0); + SDValue Callee = Op.getOperand(4); bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; #if 0 @@ -270,8 +270,8 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) { Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize)); - SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass; - SmallVector<SDOperand, 8> MemOpChains; + SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; + SmallVector<SDValue, 8> MemOpChains; #if 0 // Walk the register/memloc assignments, inserting copies/loads. @@ -279,7 +279,7 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) { CCValAssign &VA = ArgLocs[i]; // Arguments start after the 5 first operands of ISD::CALL - SDOperand Arg = Op.getOperand(5+2*VA.getValNo()); + SDValue Arg = Op.getOperand(5+2*VA.getValNo()); // Promote the value if needed. switch (VA.getLocInfo()) { @@ -306,9 +306,9 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) { assert(VA.isMemLoc()); // Create a store off the stack pointer for this argument. - SDOperand StackPtr = DAG.getRegister(SP::O6, MVT::i32); + SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); // FIXME: VERIFY THAT 68 IS RIGHT. - SDOperand PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+68); + SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+68); PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); } @@ -320,9 +320,9 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) { unsigned ArgOffset = 68; for (unsigned i = 5, e = Op.getNumOperands(); i != e; i += 2) { - SDOperand Val = Op.getOperand(i); + SDValue Val = Op.getOperand(i); MVT ObjectVT = Val.getValueType(); - SDOperand ValToStore(0, 0); + SDValue ValToStore(0, 0); unsigned ObjSize; switch (ObjectVT.getSimpleVT()) { default: assert(0 && "Unhandled argument type!"); @@ -358,9 +358,9 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) { } // Split the value into top and bottom part. Top part goes in a reg. - SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, + SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, DAG.getConstant(1, MVT::i32)); - SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, + SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, DAG.getConstant(0, MVT::i32)); RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Hi)); @@ -375,8 +375,8 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) { } if (ValToStore.Val) { - SDOperand StackPtr = DAG.getRegister(SP::O6, MVT::i32); - SDOperand PtrOff = DAG.getConstant(ArgOffset, MVT::i32); + SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); + SDValue PtrOff = DAG.getConstant(ArgOffset, MVT::i32); PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); MemOpChains.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0)); } @@ -393,7 +393,7 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) { // chain and flag operands which copy the outgoing args into registers. // The InFlag in necessary since all emited instructions must be // stuck together. - SDOperand InFlag; + SDValue InFlag; for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { unsigned Reg = RegsToPass[i].first; // Remap I0->I7 -> O0->O7. @@ -415,7 +415,7 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) { std::vector<MVT> NodeTys; NodeTys.push_back(MVT::Other); // Returns a chain NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. - SDOperand Ops[] = { Chain, Callee, InFlag }; + SDValue Ops[] = { Chain, Callee, InFlag }; Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops, InFlag.Val ? 3 : 2); InFlag = Chain.getValue(1); @@ -429,7 +429,7 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) { CCState RVInfo(CallingConv, isVarArg, DAG.getTarget(), RVLocs); RVInfo.AnalyzeCallResult(Op.Val, RetCC_Sparc32); - SmallVector<SDOperand, 8> ResultVals; + SmallVector<SDValue, 8> ResultVals; // Copy all of the result registers out of their specified physreg. for (unsigned i = 0; i != RVLocs.size(); ++i) { @@ -650,7 +650,7 @@ const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const { /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to /// be zero. Op is expected to be a target specific node. Used by DAG /// combiner. -void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, +void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, const APInt &Mask, APInt &KnownZero, APInt &KnownOne, @@ -679,7 +679,7 @@ void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, // Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition. -static void LookThroughSetCC(SDOperand &LHS, SDOperand &RHS, +static void LookThroughSetCC(SDValue &LHS, SDValue &RHS, ISD::CondCode CC, unsigned &SPCC) { if (isa<ConstantSDNode>(RHS) && cast<ConstantSDNode>(RHS)->getValue() == 0 && CC == ISD::SETNE && @@ -691,50 +691,50 @@ static void LookThroughSetCC(SDOperand &LHS, SDOperand &RHS, isa<ConstantSDNode>(LHS.getOperand(1)) && cast<ConstantSDNode>(LHS.getOperand(0))->getValue() == 1 && cast<ConstantSDNode>(LHS.getOperand(1))->getValue() == 0) { - SDOperand CMPCC = LHS.getOperand(3); + SDValue CMPCC = LHS.getOperand(3); SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getValue(); LHS = CMPCC.getOperand(0); RHS = CMPCC.getOperand(1); } } -static SDOperand LowerGLOBALADDRESS(SDOperand Op, SelectionDAG &DAG) { +static SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) { GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); - SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32); - SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA); - SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA); + SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32); + SDValue Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA); + SDValue Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA); return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); } -static SDOperand LowerCONSTANTPOOL(SDOperand Op, SelectionDAG &DAG) { +static SDValue LowerCONSTANTPOOL(SDValue Op, SelectionDAG &DAG) { ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); Constant *C = N->getConstVal(); - SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment()); - SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP); - SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP); + SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment()); + SDValue Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP); + SDValue Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP); return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); } -static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) { +static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) { // Convert the fp value to integer in an FP register. assert(Op.getValueType() == MVT::i32); Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0)); return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); } -static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { +static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) { assert(Op.getOperand(0).getValueType() == MVT::i32); - SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0)); + SDValue Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0)); // Convert the int value to FP in an FP register. return DAG.getNode(SPISD::ITOF, Op.getValueType(), Tmp); } -static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG) { - SDOperand Chain = Op.getOperand(0); +static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) { + SDValue Chain = Op.getOperand(0); ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); - SDOperand LHS = Op.getOperand(2); - SDOperand RHS = Op.getOperand(3); - SDOperand Dest = Op.getOperand(4); + SDValue LHS = Op.getOperand(2); + SDValue RHS = Op.getOperand(3); + SDValue Dest = Op.getOperand(4); unsigned Opc, SPCC = ~0U; // If this is a br_cc of a "setcc", and if the setcc got lowered into @@ -742,12 +742,12 @@ static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG) { LookThroughSetCC(LHS, RHS, CC, SPCC); // Get the condition flag. - SDOperand CompareFlag; + SDValue CompareFlag; if (LHS.getValueType() == MVT::i32) { std::vector<MVT> VTs; VTs.push_back(MVT::i32); VTs.push_back(MVT::Flag); - SDOperand Ops[2] = { LHS, RHS }; + SDValue Ops[2] = { LHS, RHS }; CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1); if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); Opc = SPISD::BRICC; @@ -760,24 +760,24 @@ static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG) { DAG.getConstant(SPCC, MVT::i32), CompareFlag); } -static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) { - SDOperand LHS = Op.getOperand(0); - SDOperand RHS = Op.getOperand(1); +static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { + SDValue LHS = Op.getOperand(0); + SDValue RHS = Op.getOperand(1); ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); - SDOperand TrueVal = Op.getOperand(2); - SDOperand FalseVal = Op.getOperand(3); + SDValue TrueVal = Op.getOperand(2); + SDValue FalseVal = Op.getOperand(3); unsigned Opc, SPCC = ~0U; // If this is a select_cc of a "setcc", and if the setcc got lowered into // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. LookThroughSetCC(LHS, RHS, CC, SPCC); - SDOperand CompareFlag; + SDValue CompareFlag; if (LHS.getValueType() == MVT::i32) { std::vector<MVT> VTs; VTs.push_back(LHS.getValueType()); // subcc returns a value VTs.push_back(MVT::Flag); - SDOperand Ops[2] = { LHS, RHS }; + SDValue Ops[2] = { LHS, RHS }; CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1); Opc = SPISD::SELECT_ICC; if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); @@ -790,11 +790,11 @@ static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) { DAG.getConstant(SPCC, MVT::i32), CompareFlag); } -static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG, +static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, SparcTargetLowering &TLI) { // vastart just stores the address of the VarArgsFrameIndex slot into the // memory location argument. - SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32, + SDValue Offset = DAG.getNode(ISD::ADD, MVT::i32, DAG.getRegister(SP::I6, MVT::i32), DAG.getConstant(TLI.getVarArgsFrameOffset(), MVT::i32)); @@ -802,15 +802,15 @@ static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG, return DAG.getStore(Op.getOperand(0), Offset, Op.getOperand(1), SV, 0); } -static SDOperand LowerVAARG(SDOperand Op, SelectionDAG &DAG) { +static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) { SDNode *Node = Op.Val; MVT VT = Node->getValueType(0); - SDOperand InChain = Node->getOperand(0); - SDOperand VAListPtr = Node->getOperand(1); + SDValue InChain = Node->getOperand(0); + SDValue VAListPtr = Node->getOperand(1); const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); - SDOperand VAList = DAG.getLoad(MVT::i32, InChain, VAListPtr, SV, 0); + SDValue VAList = DAG.getLoad(MVT::i32, InChain, VAListPtr, SV, 0); // Increment the pointer, VAList, to the next vaarg - SDOperand NextPtr = DAG.getNode(ISD::ADD, MVT::i32, VAList, + SDValue NextPtr = DAG.getNode(ISD::ADD, MVT::i32, VAList, DAG.getConstant(VT.getSizeInBits()/8, MVT::i32)); // Store the incremented VAList to the legalized pointer @@ -822,41 +822,41 @@ static SDOperand LowerVAARG(SDOperand Op, SelectionDAG &DAG) { return DAG.getLoad(VT, InChain, VAList, NULL, 0); // Otherwise, load it as i64, then do a bitconvert. - SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, NULL, 0); + SDValue V = DAG.getLoad(MVT::i64, InChain, VAList, NULL, 0); // Bit-Convert the value to f64. - SDOperand Ops[2] = { + SDValue Ops[2] = { DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V), V.getValue(1) }; return DAG.getMergeValues(Ops, 2); } -static SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG) { - SDOperand Chain = Op.getOperand(0); // Legalize the chain. - SDOperand Size = Op.getOperand(1); // Legalize the size. +static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) { + SDValue Chain = Op.getOperand(0); // Legalize the chain. + SDValue Size = Op.getOperand(1); // Legalize the size. unsigned SPReg = SP::O6; - SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, MVT::i32); - SDOperand NewSP = DAG.getNode(ISD::SUB, MVT::i32, SP, Size); // Value + SDValue SP = DAG.getCopyFromReg(Chain, SPReg, MVT::i32); + SDValue NewSP = DAG.getNode(ISD::SUB, MVT::i32, SP, Size); // Value Chain = DAG.getCopyToReg(SP.getValue(1), SPReg, NewSP); // Output chain // The resultant pointer is actually 16 words from the bottom of the stack, // to provide a register spill area. - SDOperand NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP, + SDValue NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP, DAG.getConstant(96, MVT::i32)); - SDOperand Ops[2] = { NewVal, Chain }; + SDValue Ops[2] = { NewVal, Chain }; return DAG.getMergeValues(Ops, 2); } -SDOperand SparcTargetLowering:: -LowerOperation(SDOperand Op, SelectionDAG &DAG) { +SDValue SparcTargetLowering:: +LowerOperation(SDValue Op, SelectionDAG &DAG) { switch (Op.getOpcode()) { default: assert(0 && "Should not custom lower this!"); // Frame & Return address. Currently unimplemented - case ISD::RETURNADDR: return SDOperand(); - case ISD::FRAMEADDR: return SDOperand(); + case ISD::RETURNADDR: return SDValue(); + case ISD::FRAMEADDR: return SDValue(); case ISD::GlobalTLSAddress: assert(0 && "TLS not implemented for Sparc."); case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG); diff --git a/lib/Target/Sparc/SparcISelLowering.h b/lib/Target/Sparc/SparcISelLowering.h index 2257304..ac3a7c0 100644 --- a/lib/Target/Sparc/SparcISelLowering.h +++ b/lib/Target/Sparc/SparcISelLowering.h @@ -43,14 +43,14 @@ namespace llvm { int VarArgsFrameOffset; // Frame offset to start of varargs area. public: SparcTargetLowering(TargetMachine &TM); - virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); + virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); int getVarArgsFrameOffset() const { return VarArgsFrameOffset; } /// computeMaskedBitsForTargetNode - Determine which of the bits specified /// in Mask are known to be either zero or one and return them in the /// KnownZero/KnownOne bitsets. - virtual void computeMaskedBitsForTargetNode(const SDOperand Op, + virtual void computeMaskedBitsForTargetNode(const SDValue Op, const APInt &Mask, APInt &KnownZero, APInt &KnownOne, @@ -58,7 +58,7 @@ namespace llvm { unsigned Depth = 0) const; virtual void LowerArguments(Function &F, SelectionDAG &DAG, - SmallVectorImpl<SDOperand> &ArgValues); + SmallVectorImpl<SDValue> &ArgValues); virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB); diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp index 03aa74c..e9fefcb 100644 --- a/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -50,7 +50,7 @@ STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor"); namespace { /// X86ISelAddressMode - This corresponds to X86AddressMode, but uses - /// SDOperand's instead of register numbers for the leaves of the matched + /// SDValue's instead of register numbers for the leaves of the matched /// tree. struct X86ISelAddressMode { enum { @@ -59,13 +59,13 @@ namespace { } BaseType; struct { // This is really a union, discriminated by BaseType! - SDOperand Reg; + SDValue Reg; int FrameIndex; } Base; bool isRIPRel; // RIP as base? unsigned Scale; - SDOperand IndexReg; + SDValue IndexReg; unsigned Disp; GlobalValue *GV; Constant *CP; @@ -143,38 +143,38 @@ namespace { #include "X86GenDAGISel.inc" private: - SDNode *Select(SDOperand N); + SDNode *Select(SDValue N); - bool MatchAddress(SDOperand N, X86ISelAddressMode &AM, + bool MatchAddress(SDValue N, X86ISelAddressMode &AM, bool isRoot = true, unsigned Depth = 0); - bool MatchAddressBase(SDOperand N, X86ISelAddressMode &AM, + bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM, bool isRoot, unsigned Depth); - bool SelectAddr(SDOperand Op, SDOperand N, SDOperand &Base, - SDOperand &Scale, SDOperand &Index, SDOperand &Disp); - bool SelectLEAAddr(SDOperand Op, SDOperand N, SDOperand &Base, - SDOperand &Scale, SDOperand &Index, SDOperand &Disp); - bool SelectScalarSSELoad(SDOperand Op, SDOperand Pred, - SDOperand N, SDOperand &Base, SDOperand &Scale, - SDOperand &Index, SDOperand &Disp, - SDOperand &InChain, SDOperand &OutChain); - bool TryFoldLoad(SDOperand P, SDOperand N, - SDOperand &Base, SDOperand &Scale, - SDOperand &Index, SDOperand &Disp); + bool SelectAddr(SDValue Op, SDValue N, SDValue &Base, + SDValue &Scale, SDValue &Index, SDValue &Disp); + bool SelectLEAAddr(SDValue Op, SDValue N, SDValue &Base, + SDValue &Scale, SDValue &Index, SDValue &Disp); + bool SelectScalarSSELoad(SDValue Op, SDValue Pred, + SDValue N, SDValue &Base, SDValue &Scale, + SDValue &Index, SDValue &Disp, + SDValue &InChain, SDValue &OutChain); + bool TryFoldLoad(SDValue P, SDValue N, + SDValue &Base, SDValue &Scale, + SDValue &Index, SDValue &Disp); void PreprocessForRMW(SelectionDAG &DAG); void PreprocessForFPConvert(SelectionDAG &DAG); /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for /// inline asm expressions. - virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op, + virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, - std::vector<SDOperand> &OutOps, + std::vector<SDValue> &OutOps, SelectionDAG &DAG); void EmitSpecialCodeForMain(MachineBasicBlock *BB, MachineFrameInfo *MFI); - inline void getAddressOperands(X86ISelAddressMode &AM, SDOperand &Base, - SDOperand &Scale, SDOperand &Index, - SDOperand &Disp) { + inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base, + SDValue &Scale, SDValue &Index, + SDValue &Disp) { Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ? CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, TLI.getPointerTy()) : AM.Base.Reg; @@ -196,19 +196,19 @@ namespace { /// getI8Imm - Return a target constant with the specified value, of type /// i8. - inline SDOperand getI8Imm(unsigned Imm) { + inline SDValue getI8Imm(unsigned Imm) { return CurDAG->getTargetConstant(Imm, MVT::i8); } /// getI16Imm - Return a target constant with the specified value, of type /// i16. - inline SDOperand getI16Imm(unsigned Imm) { + inline SDValue getI16Imm(unsigned Imm) { return CurDAG->getTargetConstant(Imm, MVT::i16); } /// getI32Imm - Return a target constant with the specified value, of type /// i32. - inline SDOperand getI32Imm(unsigned Imm) { + inline SDValue getI32Imm(unsigned Imm) { return CurDAG->getTargetConstant(Imm, MVT::i32); } @@ -218,7 +218,7 @@ namespace { /// getTruncate - return an SDNode that implements a subreg based truncate /// of the specified operand to the the specified value type. - SDNode *getTruncate(SDOperand N0, MVT VT); + SDNode *getTruncate(SDValue N0, MVT VT); #ifndef NDEBUG unsigned Indent; @@ -233,7 +233,7 @@ static SDNode *findFlagUse(SDNode *N) { for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { SDNode *User = *I; for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { - SDOperand Op = User->getOperand(i); + SDValue Op = User->getOperand(i); if (Op.Val == N && Op.ResNo == FlagResNo) return User; } @@ -352,9 +352,9 @@ bool X86DAGToDAGISel::CanBeFoldedBy(SDNode *N, SDNode *U, SDNode *Root) const { /// MoveBelowTokenFactor - Replace TokenFactor operand with load's chain operand /// and move load below the TokenFactor. Replace store's chain operand with /// load's chain result. -static void MoveBelowTokenFactor(SelectionDAG &DAG, SDOperand Load, - SDOperand Store, SDOperand TF) { - std::vector<SDOperand> Ops; +static void MoveBelowTokenFactor(SelectionDAG &DAG, SDValue Load, + SDValue Store, SDValue TF) { + std::vector<SDValue> Ops; for (unsigned i = 0, e = TF.Val->getNumOperands(); i != e; ++i) if (Load.Val == TF.Val->getOperand(i).Val) Ops.push_back(Load.Val->getOperand(0)); @@ -368,8 +368,8 @@ static void MoveBelowTokenFactor(SelectionDAG &DAG, SDOperand Load, /// isRMWLoad - Return true if N is a load that's part of RMW sub-DAG. /// -static bool isRMWLoad(SDOperand N, SDOperand Chain, SDOperand Address, - SDOperand &Load) { +static bool isRMWLoad(SDValue N, SDValue Chain, SDValue Address, + SDValue &Load) { if (N.getOpcode() == ISD::BIT_CONVERT) N = N.getOperand(0); @@ -437,19 +437,19 @@ void X86DAGToDAGISel::PreprocessForRMW(SelectionDAG &DAG) { E = DAG.allnodes_end(); I != E; ++I) { if (!ISD::isNON_TRUNCStore(I)) continue; - SDOperand Chain = I->getOperand(0); + SDValue Chain = I->getOperand(0); if (Chain.Val->getOpcode() != ISD::TokenFactor) continue; - SDOperand N1 = I->getOperand(1); - SDOperand N2 = I->getOperand(2); + SDValue N1 = I->getOperand(1); + SDValue N2 = I->getOperand(2); if ((N1.getValueType().isFloatingPoint() && !N1.getValueType().isVector()) || !N1.hasOneUse()) continue; bool RModW = false; - SDOperand Load; + SDValue Load; unsigned Opcode = N1.Val->getOpcode(); switch (Opcode) { case ISD::ADD: @@ -460,8 +460,8 @@ void X86DAGToDAGISel::PreprocessForRMW(SelectionDAG &DAG) { case ISD::ADDC: case ISD::ADDE: case ISD::VECTOR_SHUFFLE: { - SDOperand N10 = N1.getOperand(0); - SDOperand N11 = N1.getOperand(1); + SDValue N10 = N1.getOperand(0); + SDValue N11 = N1.getOperand(1); RModW = isRMWLoad(N10, Chain, N2, Load); if (!RModW) RModW = isRMWLoad(N11, Chain, N2, Load); @@ -477,14 +477,14 @@ void X86DAGToDAGISel::PreprocessForRMW(SelectionDAG &DAG) { case ISD::SUBE: case X86ISD::SHLD: case X86ISD::SHRD: { - SDOperand N10 = N1.getOperand(0); + SDValue N10 = N1.getOperand(0); RModW = isRMWLoad(N10, Chain, N2, Load); break; } } if (RModW) { - MoveBelowTokenFactor(DAG, Load, SDOperand(I, 0), Chain); + MoveBelowTokenFactor(DAG, Load, SDValue(I, 0), Chain); ++NumLoadMoved; } } @@ -533,12 +533,12 @@ void X86DAGToDAGISel::PreprocessForFPConvert(SelectionDAG &DAG) { else MemVT = SrcIsSSE ? SrcVT : DstVT; - SDOperand MemTmp = DAG.CreateStackTemporary(MemVT); + SDValue MemTmp = DAG.CreateStackTemporary(MemVT); // FIXME: optimize the case where the src/dest is a load or store? - SDOperand Store = DAG.getTruncStore(DAG.getEntryNode(), N->getOperand(0), + SDValue Store = DAG.getTruncStore(DAG.getEntryNode(), N->getOperand(0), MemTmp, NULL, 0, MemVT); - SDOperand Result = DAG.getExtLoad(ISD::EXTLOAD, DstVT, Store, MemTmp, + SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, DstVT, Store, MemTmp, NULL, 0, MemVT); // We're about to replace all uses of the FP_ROUND/FP_EXTEND with the @@ -546,7 +546,7 @@ void X86DAGToDAGISel::PreprocessForFPConvert(SelectionDAG &DAG) { // anything below the conversion could be folded into other existing nodes. // To avoid invalidating 'I', back it up to the convert node. --I; - DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result); + DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result); // Now that we did that, the node is dead. Increment the iterator to the // next node to process, then delete N. @@ -674,7 +674,7 @@ void X86DAGToDAGISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) { /// MatchAddress - Add the specified node to the specified addressing mode, /// returning true if it cannot be done. This just pattern matches for the /// addressing mode. -bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM, +bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM, bool isRoot, unsigned Depth) { // Limit recursion. if (Depth > 5) @@ -719,7 +719,7 @@ bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM, // been picked, we can't fit the result available in the register in the // addressing mode. Duplicate GlobalAddress or ConstantPool as displacement. if (!AlreadySelected || (AM.Base.Reg.Val && AM.IndexReg.Val)) { - SDOperand N0 = N.getOperand(0); + SDValue N0 = N.getOperand(0); if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) { GlobalValue *GV = G->getGlobal(); AM.GV = GV; @@ -765,7 +765,7 @@ bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM, unsigned Val = CN->getValue(); if (Val == 1 || Val == 2 || Val == 3) { AM.Scale = 1 << Val; - SDOperand ShVal = N.Val->getOperand(0); + SDValue ShVal = N.Val->getOperand(0); // Okay, we know that we have a scale by now. However, if the scaled // value is an add of something and a constant, we can fold the @@ -804,8 +804,8 @@ bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM, if (CN->getValue() == 3 || CN->getValue() == 5 || CN->getValue() == 9) { AM.Scale = unsigned(CN->getValue())-1; - SDOperand MulVal = N.Val->getOperand(0); - SDOperand Reg; + SDValue MulVal = N.Val->getOperand(0); + SDValue Reg; // Okay, we know that we have a scale by now. However, if the scaled // value is an add of something and a constant, we can fold the @@ -869,7 +869,7 @@ bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM, // Handle "(x << C1) & C2" as "(X & (C2>>C1)) << C1" if safe and if this // allows us to fold the shift into this addressing mode. if (AlreadySelected) break; - SDOperand Shift = N.getOperand(0); + SDValue Shift = N.getOperand(0); if (Shift.getOpcode() != ISD::SHL) break; // Scale must not be used already. @@ -894,9 +894,9 @@ bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM, break; // Get the new AND mask, this folds to a constant. - SDOperand NewANDMask = CurDAG->getNode(ISD::SRL, N.getValueType(), - SDOperand(C2, 0), SDOperand(C1, 0)); - SDOperand NewAND = CurDAG->getNode(ISD::AND, N.getValueType(), + SDValue NewANDMask = CurDAG->getNode(ISD::SRL, N.getValueType(), + SDValue(C2, 0), SDValue(C1, 0)); + SDValue NewAND = CurDAG->getNode(ISD::AND, N.getValueType(), Shift.getOperand(0), NewANDMask); NewANDMask.Val->setNodeId(Shift.Val->getNodeId()); NewAND.Val->setNodeId(N.Val->getNodeId()); @@ -912,7 +912,7 @@ bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM, /// MatchAddressBase - Helper for MatchAddress. Add the specified node to the /// specified addressing mode without any further recursion. -bool X86DAGToDAGISel::MatchAddressBase(SDOperand N, X86ISelAddressMode &AM, +bool X86DAGToDAGISel::MatchAddressBase(SDValue N, X86ISelAddressMode &AM, bool isRoot, unsigned Depth) { // Is the base register already occupied? if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base.Reg.Val) { @@ -936,9 +936,9 @@ bool X86DAGToDAGISel::MatchAddressBase(SDOperand N, X86ISelAddressMode &AM, /// SelectAddr - returns true if it is able pattern match an addressing mode. /// It returns the operands which make up the maximal addressing mode it can /// match by reference. -bool X86DAGToDAGISel::SelectAddr(SDOperand Op, SDOperand N, SDOperand &Base, - SDOperand &Scale, SDOperand &Index, - SDOperand &Disp) { +bool X86DAGToDAGISel::SelectAddr(SDValue Op, SDValue N, SDValue &Base, + SDValue &Scale, SDValue &Index, + SDValue &Disp) { X86ISelAddressMode AM; if (MatchAddress(N, AM)) return false; @@ -958,7 +958,7 @@ bool X86DAGToDAGISel::SelectAddr(SDOperand Op, SDOperand N, SDOperand &Base, /// isZeroNode - Returns true if Elt is a constant zero or a floating point /// constant +0.0. -static inline bool isZeroNode(SDOperand Elt) { +static inline bool isZeroNode(SDValue Elt) { return ((isa<ConstantSDNode>(Elt) && cast<ConstantSDNode>(Elt)->getValue() == 0) || (isa<ConstantFPSDNode>(Elt) && @@ -969,11 +969,11 @@ static inline bool isZeroNode(SDOperand Elt) { /// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to /// match a load whose top elements are either undef or zeros. The load flavor /// is derived from the type of N, which is either v4f32 or v2f64. -bool X86DAGToDAGISel::SelectScalarSSELoad(SDOperand Op, SDOperand Pred, - SDOperand N, SDOperand &Base, - SDOperand &Scale, SDOperand &Index, - SDOperand &Disp, SDOperand &InChain, - SDOperand &OutChain) { +bool X86DAGToDAGISel::SelectScalarSSELoad(SDValue Op, SDValue Pred, + SDValue N, SDValue &Base, + SDValue &Scale, SDValue &Index, + SDValue &Disp, SDValue &InChain, + SDValue &OutChain) { if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) { InChain = N.getOperand(0).getValue(1); if (ISD::isNON_EXTLoad(InChain.Val) && @@ -1001,7 +1001,7 @@ bool X86DAGToDAGISel::SelectScalarSSELoad(SDOperand Op, SDOperand Pred, if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp)) return false; OutChain = LD->getChain(); - InChain = SDOperand(LD, 1); + InChain = SDValue(LD, 1); return true; } return false; @@ -1010,9 +1010,9 @@ bool X86DAGToDAGISel::SelectScalarSSELoad(SDOperand Op, SDOperand Pred, /// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing /// mode it matches can be cost effectively emitted as an LEA instruction. -bool X86DAGToDAGISel::SelectLEAAddr(SDOperand Op, SDOperand N, - SDOperand &Base, SDOperand &Scale, - SDOperand &Index, SDOperand &Disp) { +bool X86DAGToDAGISel::SelectLEAAddr(SDValue Op, SDValue N, + SDValue &Base, SDValue &Scale, + SDValue &Index, SDValue &Disp) { X86ISelAddressMode AM; if (MatchAddress(N, AM)) return false; @@ -1061,9 +1061,9 @@ bool X86DAGToDAGISel::SelectLEAAddr(SDOperand Op, SDOperand N, return false; } -bool X86DAGToDAGISel::TryFoldLoad(SDOperand P, SDOperand N, - SDOperand &Base, SDOperand &Scale, - SDOperand &Index, SDOperand &Disp) { +bool X86DAGToDAGISel::TryFoldLoad(SDValue P, SDValue N, + SDValue &Base, SDValue &Scale, + SDValue &Index, SDValue &Disp) { if (ISD::isNON_EXTLoad(N.Val) && N.hasOneUse() && CanBeFoldedBy(N.Val, P.Val, P.Val)) @@ -1111,8 +1111,8 @@ static SDNode *FindCallStartFromCall(SDNode *Node) { return FindCallStartFromCall(Node->getOperand(0).Val); } -SDNode *X86DAGToDAGISel::getTruncate(SDOperand N0, MVT VT) { - SDOperand SRIdx; +SDNode *X86DAGToDAGISel::getTruncate(SDValue N0, MVT VT) { + SDValue SRIdx; switch (VT.getSimpleVT()) { default: assert(0 && "Unknown truncate!"); case MVT::i8: @@ -1130,7 +1130,7 @@ SDNode *X86DAGToDAGISel::getTruncate(SDOperand N0, MVT VT) { Opc = X86::MOV32to32_; break; } - N0 = SDOperand(CurDAG->getTargetNode(Opc, N0VT, MVT::Flag, N0), 0); + N0 = SDValue(CurDAG->getTargetNode(Opc, N0VT, MVT::Flag, N0), 0); return CurDAG->getTargetNode(X86::EXTRACT_SUBREG, VT, N0, SRIdx, N0.getValue(1)); } @@ -1146,7 +1146,7 @@ SDNode *X86DAGToDAGISel::getTruncate(SDOperand N0, MVT VT) { } -SDNode *X86DAGToDAGISel::Select(SDOperand N) { +SDNode *X86DAGToDAGISel::Select(SDValue N) { SDNode *Node = N.Val; MVT NVT = Node->getValueType(0); unsigned Opc, MOpc; @@ -1183,13 +1183,13 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) { if (TM.getCodeModel() != CodeModel::Small) break; MVT PtrVT = TLI.getPointerTy(); - SDOperand N0 = N.getOperand(0); - SDOperand N1 = N.getOperand(1); + SDValue N0 = N.getOperand(0); + SDValue N1 = N.getOperand(1); if (N.Val->getValueType(0) == PtrVT && N0.getOpcode() == X86ISD::Wrapper && N1.getOpcode() == ISD::Constant) { unsigned Offset = (unsigned)cast<ConstantSDNode>(N1)->getValue(); - SDOperand C(0, 0); + SDValue C(0, 0); // TODO: handle ExternalSymbolSDNode. if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0.getOperand(0))) { @@ -1204,7 +1204,7 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) { if (C.Val) { if (Subtarget->is64Bit()) { - SDOperand Ops[] = { CurDAG->getRegister(0, PtrVT), getI8Imm(1), + SDValue Ops[] = { CurDAG->getRegister(0, PtrVT), getI8Imm(1), CurDAG->getRegister(0, PtrVT), C }; return CurDAG->SelectNodeTo(N.Val, X86::LEA64r, MVT::i64, Ops, 4); } else @@ -1218,8 +1218,8 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) { case ISD::SMUL_LOHI: case ISD::UMUL_LOHI: { - SDOperand N0 = Node->getOperand(0); - SDOperand N1 = Node->getOperand(1); + SDValue N0 = Node->getOperand(0); + SDValue N1 = Node->getOperand(1); bool isSigned = Opcode == ISD::SMUL_LOHI; if (!isSigned) @@ -1248,7 +1248,7 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) { case MVT::i64: LoReg = X86::RAX; HiReg = X86::RDX; break; } - SDOperand Tmp0, Tmp1, Tmp2, Tmp3; + SDValue Tmp0, Tmp1, Tmp2, Tmp3; bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3); // multiplty is commmutative if (!foldedLoad) { @@ -1258,8 +1258,8 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) { } AddToISelQueue(N0); - SDOperand InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), LoReg, - N0, SDOperand()).getValue(1); + SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), LoReg, + N0, SDValue()).getValue(1); if (foldedLoad) { AddToISelQueue(N1.getOperand(0)); @@ -1267,21 +1267,21 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) { AddToISelQueue(Tmp1); AddToISelQueue(Tmp2); AddToISelQueue(Tmp3); - SDOperand Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N1.getOperand(0), InFlag }; + SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N1.getOperand(0), InFlag }; SDNode *CNode = CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Ops, 6); - InFlag = SDOperand(CNode, 1); + InFlag = SDValue(CNode, 1); // Update the chain. - ReplaceUses(N1.getValue(1), SDOperand(CNode, 0)); + ReplaceUses(N1.getValue(1), SDValue(CNode, 0)); } else { AddToISelQueue(N1); InFlag = - SDOperand(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0); + SDValue(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0); } // Copy the low half of the result, if it is needed. if (!N.getValue(0).use_empty()) { - SDOperand Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), + SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), LoReg, NVT, InFlag); InFlag = Result.getValue(2); ReplaceUses(N.getValue(0), Result); @@ -1293,18 +1293,18 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) { } // Copy the high half of the result, if it is needed. if (!N.getValue(1).use_empty()) { - SDOperand Result; + SDValue Result; if (HiReg == X86::AH && Subtarget->is64Bit()) { // Prevent use of AH in a REX instruction by referencing AX instead. // Shift it down 8 bits. Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), X86::AX, MVT::i16, InFlag); InFlag = Result.getValue(2); - Result = SDOperand(CurDAG->getTargetNode(X86::SHR16ri, MVT::i16, Result, + Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, MVT::i16, Result, CurDAG->getTargetConstant(8, MVT::i8)), 0); // Then truncate it down to i8. - SDOperand SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1 - Result = SDOperand(CurDAG->getTargetNode(X86::EXTRACT_SUBREG, + SDValue SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1 + Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG, MVT::i8, Result, SRIdx), 0); } else { Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), @@ -1328,8 +1328,8 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) { case ISD::SDIVREM: case ISD::UDIVREM: { - SDOperand N0 = Node->getOperand(0); - SDOperand N1 = Node->getOperand(1); + SDValue N0 = Node->getOperand(0); + SDValue N1 = Node->getOperand(1); bool isSigned = Opcode == ISD::SDIVREM; if (!isSigned) @@ -1375,46 +1375,46 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) { break; } - SDOperand Tmp0, Tmp1, Tmp2, Tmp3; + SDValue Tmp0, Tmp1, Tmp2, Tmp3; bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3); - SDOperand InFlag; + SDValue InFlag; if (NVT == MVT::i8 && !isSigned) { // Special case for div8, just use a move with zero extension to AX to // clear the upper 8 bits (AH). - SDOperand Tmp0, Tmp1, Tmp2, Tmp3, Move, Chain; + SDValue Tmp0, Tmp1, Tmp2, Tmp3, Move, Chain; if (TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3)) { - SDOperand Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N0.getOperand(0) }; + SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N0.getOperand(0) }; AddToISelQueue(N0.getOperand(0)); AddToISelQueue(Tmp0); AddToISelQueue(Tmp1); AddToISelQueue(Tmp2); AddToISelQueue(Tmp3); Move = - SDOperand(CurDAG->getTargetNode(X86::MOVZX16rm8, MVT::i16, MVT::Other, + SDValue(CurDAG->getTargetNode(X86::MOVZX16rm8, MVT::i16, MVT::Other, Ops, 5), 0); Chain = Move.getValue(1); ReplaceUses(N0.getValue(1), Chain); } else { AddToISelQueue(N0); Move = - SDOperand(CurDAG->getTargetNode(X86::MOVZX16rr8, MVT::i16, N0), 0); + SDValue(CurDAG->getTargetNode(X86::MOVZX16rr8, MVT::i16, N0), 0); Chain = CurDAG->getEntryNode(); } - Chain = CurDAG->getCopyToReg(Chain, X86::AX, Move, SDOperand()); + Chain = CurDAG->getCopyToReg(Chain, X86::AX, Move, SDValue()); InFlag = Chain.getValue(1); } else { AddToISelQueue(N0); InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), - LoReg, N0, SDOperand()).getValue(1); + LoReg, N0, SDValue()).getValue(1); if (isSigned) { // Sign extend the low part into the high part. InFlag = - SDOperand(CurDAG->getTargetNode(SExtOpcode, MVT::Flag, InFlag), 0); + SDValue(CurDAG->getTargetNode(SExtOpcode, MVT::Flag, InFlag), 0); } else { // Zero out the high part, effectively zero extending the input. - SDOperand ClrNode = SDOperand(CurDAG->getTargetNode(ClrOpcode, NVT), 0); + SDValue ClrNode = SDValue(CurDAG->getTargetNode(ClrOpcode, NVT), 0); InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), HiReg, ClrNode, InFlag).getValue(1); } @@ -1426,21 +1426,21 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) { AddToISelQueue(Tmp1); AddToISelQueue(Tmp2); AddToISelQueue(Tmp3); - SDOperand Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N1.getOperand(0), InFlag }; + SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N1.getOperand(0), InFlag }; SDNode *CNode = CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Ops, 6); - InFlag = SDOperand(CNode, 1); + InFlag = SDValue(CNode, 1); // Update the chain. - ReplaceUses(N1.getValue(1), SDOperand(CNode, 0)); + ReplaceUses(N1.getValue(1), SDValue(CNode, 0)); } else { AddToISelQueue(N1); InFlag = - SDOperand(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0); + SDValue(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0); } // Copy the division (low) result, if it is needed. if (!N.getValue(0).use_empty()) { - SDOperand Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), + SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), LoReg, NVT, InFlag); InFlag = Result.getValue(2); ReplaceUses(N.getValue(0), Result); @@ -1452,18 +1452,18 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) { } // Copy the remainder (high) result, if it is needed. if (!N.getValue(1).use_empty()) { - SDOperand Result; + SDValue Result; if (HiReg == X86::AH && Subtarget->is64Bit()) { // Prevent use of AH in a REX instruction by referencing AX instead. // Shift it down 8 bits. Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), X86::AX, MVT::i16, InFlag); InFlag = Result.getValue(2); - Result = SDOperand(CurDAG->getTargetNode(X86::SHR16ri, MVT::i16, Result, + Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, MVT::i16, Result, CurDAG->getTargetConstant(8, MVT::i8)), 0); // Then truncate it down to i8. - SDOperand SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1 - Result = SDOperand(CurDAG->getTargetNode(X86::EXTRACT_SUBREG, + SDValue SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1 + Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG, MVT::i8, Result, SRIdx), 0); } else { Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), @@ -1490,7 +1490,7 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) { if (NVT == MVT::i8) break; - SDOperand N0 = Node->getOperand(0); + SDValue N0 = Node->getOperand(0); // Get the subregsiter index for the type to extend. MVT N0VT = N0.getValueType(); unsigned Idx = (N0VT == MVT::i32) ? X86::SUBREG_32BIT : @@ -1503,9 +1503,9 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) { // If we have an index, generate an insert_subreg into undef. AddToISelQueue(N0); - SDOperand Undef = - SDOperand(CurDAG->getTargetNode(X86::IMPLICIT_DEF, NVT), 0); - SDOperand SRIdx = CurDAG->getTargetConstant(Idx, MVT::i32); + SDValue Undef = + SDValue(CurDAG->getTargetNode(X86::IMPLICIT_DEF, NVT), 0); + SDValue SRIdx = CurDAG->getTargetConstant(Idx, MVT::i32); SDNode *ResNode = CurDAG->getTargetNode(X86::INSERT_SUBREG, NVT, Undef, N0, SRIdx); @@ -1519,11 +1519,11 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) { } case ISD::SIGN_EXTEND_INREG: { - SDOperand N0 = Node->getOperand(0); + SDValue N0 = Node->getOperand(0); AddToISelQueue(N0); MVT SVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); - SDOperand TruncOp = SDOperand(getTruncate(N0, SVT), 0); + SDValue TruncOp = SDValue(getTruncate(N0, SVT), 0); unsigned Opc = 0; switch (NVT.getSimpleVT()) { default: assert(0 && "Unknown sign_extend_inreg!"); @@ -1564,7 +1564,7 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) { } case ISD::TRUNCATE: { - SDOperand Input = Node->getOperand(0); + SDValue Input = Node->getOperand(0); AddToISelQueue(Node->getOperand(0)); SDNode *ResNode = getTruncate(Input, NVT); @@ -1581,9 +1581,9 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) { case ISD::DECLARE: { // Handle DECLARE nodes here because the second operand may have been // wrapped in X86ISD::Wrapper. - SDOperand Chain = Node->getOperand(0); - SDOperand N1 = Node->getOperand(1); - SDOperand N2 = Node->getOperand(2); + SDValue Chain = Node->getOperand(0); + SDValue N1 = Node->getOperand(1); + SDValue N2 = Node->getOperand(2); if (!isa<FrameIndexSDNode>(N1)) break; int FI = cast<FrameIndexSDNode>(N1)->getIndex(); @@ -1594,10 +1594,10 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) { isa<GlobalAddressSDNode>(N2.getOperand(0))) { GlobalValue *GV = cast<GlobalAddressSDNode>(N2.getOperand(0))->getGlobal(); - SDOperand Tmp1 = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); - SDOperand Tmp2 = CurDAG->getTargetGlobalAddress(GV, TLI.getPointerTy()); + SDValue Tmp1 = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); + SDValue Tmp2 = CurDAG->getTargetGlobalAddress(GV, TLI.getPointerTy()); AddToISelQueue(Chain); - SDOperand Ops[] = { Tmp1, Tmp2, Chain }; + SDValue Ops[] = { Tmp1, Tmp2, Chain }; return CurDAG->getTargetNode(TargetInstrInfo::DECLARE, MVT::Other, Ops, 3); } @@ -1621,9 +1621,9 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) { } bool X86DAGToDAGISel:: -SelectInlineAsmMemoryOperand(const SDOperand &Op, char ConstraintCode, - std::vector<SDOperand> &OutOps, SelectionDAG &DAG){ - SDOperand Op0, Op1, Op2, Op3; +SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, + std::vector<SDValue> &OutOps, SelectionDAG &DAG){ + SDValue Op0, Op1, Op2, Op3; switch (ConstraintCode) { case 'o': // offsetable ?? case 'v': // not offsetable ?? diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index ed0773d..6f8b1ec 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -41,7 +41,7 @@ using namespace llvm; // Forward declarations. -static SDOperand getMOVLMask(unsigned NumElems, SelectionDAG &DAG); +static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG); X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) : TargetLowering(TM) { @@ -755,7 +755,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) } -MVT X86TargetLowering::getSetCCResultType(const SDOperand &) const { +MVT X86TargetLowering::getSetCCResultType(const SDValue &) const { return MVT::i8; } @@ -818,7 +818,7 @@ X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align, /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC /// jumptable. -SDOperand X86TargetLowering::getPICJumpTableRelocBase(SDOperand Table, +SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const { if (usesGlobalOffsetTable()) return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy()); @@ -834,7 +834,7 @@ SDOperand X86TargetLowering::getPICJumpTableRelocBase(SDOperand Table, #include "X86GenCallingConv.inc" /// LowerRET - Lower an ISD::RET node. -SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) { +SDValue X86TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) { assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args"); SmallVector<CCValAssign, 16> RVLocs; @@ -850,14 +850,14 @@ SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) { if (RVLocs[i].isRegLoc()) DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); } - SDOperand Chain = Op.getOperand(0); + SDValue Chain = Op.getOperand(0); // Handle tail call return. Chain = GetPossiblePreceedingTailCall(Chain, X86ISD::TAILCALL); if (Chain.getOpcode() == X86ISD::TAILCALL) { - SDOperand TailCall = Chain; - SDOperand TargetAddress = TailCall.getOperand(1); - SDOperand StackAdjustment = TailCall.getOperand(2); + SDValue TailCall = Chain; + SDValue TargetAddress = TailCall.getOperand(1); + SDValue StackAdjustment = TailCall.getOperand(2); assert(((TargetAddress.getOpcode() == ISD::Register && (cast<RegisterSDNode>(TargetAddress)->getReg() == X86::ECX || cast<RegisterSDNode>(TargetAddress)->getReg() == X86::R9)) || @@ -867,7 +867,7 @@ SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) { assert(StackAdjustment.getOpcode() == ISD::Constant && "Expecting a const value"); - SmallVector<SDOperand,8> Operands; + SmallVector<SDValue,8> Operands; Operands.push_back(Chain.getOperand(0)); Operands.push_back(TargetAddress); Operands.push_back(StackAdjustment); @@ -881,9 +881,9 @@ SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) { } // Regular return. - SDOperand Flag; + SDValue Flag; - SmallVector<SDOperand, 6> RetOps; + SmallVector<SDValue, 6> RetOps; RetOps.push_back(Chain); // Operand #0 = Chain (updated below) // Operand #1 = Bytes To Pop RetOps.push_back(DAG.getConstant(getBytesToPopOnReturn(), MVT::i16)); @@ -892,7 +892,7 @@ SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) { for (unsigned i = 0; i != RVLocs.size(); ++i) { CCValAssign &VA = RVLocs[i]; assert(VA.isRegLoc() && "Can only return in registers!"); - SDOperand ValToCopy = Op.getOperand(i*2+1); + SDValue ValToCopy = Op.getOperand(i*2+1); // Returns in ST0/ST1 are handled specially: these are pushed as operands to // the RET instruction and handled by the FP Stackifier. @@ -924,7 +924,7 @@ SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) { Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); FuncInfo->setSRetReturnReg(Reg); } - SDOperand Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy()); + SDValue Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy()); Chain = DAG.getCopyToReg(Chain, X86::RAX, Val, Flag); Flag = Chain.getValue(1); @@ -946,7 +946,7 @@ SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) { /// being lowered. The returns a SDNode with the same number of values as the /// ISD::CALL. SDNode *X86TargetLowering:: -LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall, +LowerCallResult(SDValue Chain, SDValue InFlag, SDNode *TheCall, unsigned CallingConv, SelectionDAG &DAG) { // Assign locations to each value returned by this call. @@ -955,7 +955,7 @@ LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall, CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs); CCInfo.AnalyzeCallResult(TheCall, RetCC_X86); - SmallVector<SDOperand, 8> ResultVals; + SmallVector<SDValue, 8> ResultVals; // Copy all of the result registers out of their specified physreg. for (unsigned i = 0; i != RVLocs.size(); ++i) { @@ -971,7 +971,7 @@ LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall, Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(), CopyVT, InFlag).getValue(1); - SDOperand Val = Chain.getValue(0); + SDValue Val = Chain.getValue(0); InFlag = Chain.getValue(2); if (CopyVT != RVLocs[i].getValVT()) { @@ -1015,7 +1015,7 @@ static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg, /// CallIsStructReturn - Determines whether a CALL node uses struct return /// semantics. -static bool CallIsStructReturn(SDOperand Op) { +static bool CallIsStructReturn(SDValue Op) { unsigned NumOps = (Op.getNumOperands() - 5) / 2; if (!NumOps) return false; @@ -1025,7 +1025,7 @@ static bool CallIsStructReturn(SDOperand Op) { /// ArgsAreStructReturn - Determines whether a FORMAL_ARGUMENTS node uses struct /// return semantics. -static bool ArgsAreStructReturn(SDOperand Op) { +static bool ArgsAreStructReturn(SDValue Op) { unsigned NumArgs = Op.Val->getNumValues() - 1; if (!NumArgs) return false; @@ -1036,7 +1036,7 @@ static bool ArgsAreStructReturn(SDOperand Op) { /// IsCalleePop - Determines whether a CALL or FORMAL_ARGUMENTS node requires /// the callee to pop its own arguments. Callee pop is necessary to support tail /// calls. -bool X86TargetLowering::IsCalleePop(SDOperand Op) { +bool X86TargetLowering::IsCalleePop(SDValue Op) { bool IsVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; if (IsVarArg) return false; @@ -1055,7 +1055,7 @@ bool X86TargetLowering::IsCalleePop(SDOperand Op) { /// CCAssignFnForNode - Selects the correct CCAssignFn for a CALL or /// FORMAL_ARGUMENTS node. -CCAssignFn *X86TargetLowering::CCAssignFnForNode(SDOperand Op) const { +CCAssignFn *X86TargetLowering::CCAssignFnForNode(SDValue Op) const { unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); if (Subtarget->is64Bit()) { @@ -1080,7 +1080,7 @@ CCAssignFn *X86TargetLowering::CCAssignFnForNode(SDOperand Op) const { /// NameDecorationForFORMAL_ARGUMENTS - Selects the appropriate decoration to /// apply to a MachineFunction containing a given FORMAL_ARGUMENTS node. NameDecorationStyle -X86TargetLowering::NameDecorationForFORMAL_ARGUMENTS(SDOperand Op) { +X86TargetLowering::NameDecorationForFORMAL_ARGUMENTS(SDValue Op) { unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); if (CC == CallingConv::X86_FastCall) return FastCall; @@ -1111,19 +1111,19 @@ X86TargetLowering::CallRequiresFnAddressInReg(bool Is64Bit, bool IsTailCall) { /// by "Src" to address "Dst" with size and alignment information specified by /// the specific parameter attribute. The copy will be passed as a byval /// function parameter. -static SDOperand -CreateCopyOfByValArgument(SDOperand Src, SDOperand Dst, SDOperand Chain, +static SDValue +CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG) { - SDOperand SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); + SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); return DAG.getMemcpy(Chain, Dst, Src, SizeNode, Flags.getByValAlign(), /*AlwaysInline=*/true, NULL, 0, NULL, 0); } -SDOperand X86TargetLowering::LowerMemArgument(SDOperand Op, SelectionDAG &DAG, +SDValue X86TargetLowering::LowerMemArgument(SDValue Op, SelectionDAG &DAG, const CCValAssign &VA, MachineFrameInfo *MFI, unsigned CC, - SDOperand Root, unsigned i) { + SDValue Root, unsigned i) { // Create the nodes corresponding to a load from this parameter slot. ISD::ArgFlagsTy Flags = cast<ARG_FLAGSSDNode>(Op.getOperand(3 + i))->getArgFlags(); @@ -1136,15 +1136,15 @@ SDOperand X86TargetLowering::LowerMemArgument(SDOperand Op, SelectionDAG &DAG, // could be overwritten by lowering of arguments in case of a tail call. int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8, VA.getLocMemOffset(), isImmutable); - SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy()); + SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); if (Flags.isByVal()) return FIN; return DAG.getLoad(VA.getValVT(), Root, FIN, PseudoSourceValue::getFixedStack(FI), 0); } -SDOperand -X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) { +SDValue +X86TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) { MachineFunction &MF = DAG.getMachineFunction(); X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); @@ -1158,7 +1158,7 @@ X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) { FuncInfo->setDecorationStyle(NameDecorationForFORMAL_ARGUMENTS(Op)); MachineFrameInfo *MFI = MF.getFrameInfo(); - SDOperand Root = Op.getOperand(0); + SDValue Root = Op.getOperand(0); bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; unsigned CC = MF.getFunction()->getCallingConv(); bool Is64Bit = Subtarget->is64Bit(); @@ -1172,7 +1172,7 @@ X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) { CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs); CCInfo.AnalyzeFormalArguments(Op.Val, CCAssignFnForNode(Op)); - SmallVector<SDOperand, 8> ArgValues; + SmallVector<SDValue, 8> ArgValues; unsigned LastVal = ~0U; for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { CCValAssign &VA = ArgLocs[i]; @@ -1215,7 +1215,7 @@ X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) { } unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC); - SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT); + SDValue ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT); // If this is an 8 or 16-bit value, it is really passed promoted to 32 // bits. Insert an assert[sz]ext to capture this, then truncate to the @@ -1259,7 +1259,7 @@ X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) { Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); FuncInfo->setSRetReturnReg(Reg); } - SDOperand Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]); + SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]); Root = DAG.getNode(ISD::TokenFactor, MVT::Other, Copy, Root); } @@ -1316,15 +1316,15 @@ X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) { TotalNumXMMRegs * 16, 16); // Store the integer parameter registers. - SmallVector<SDOperand, 8> MemOps; - SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy()); - SDOperand FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN, + SmallVector<SDValue, 8> MemOps; + SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy()); + SDValue FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN, DAG.getIntPtrConstant(VarArgsGPOffset)); for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) { unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs], X86::GR64RegisterClass); - SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i64); - SDOperand Store = + SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::i64); + SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0); MemOps.push_back(Store); @@ -1338,8 +1338,8 @@ X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) { for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) { unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs], X86::VR128RegisterClass); - SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32); - SDOperand Store = + SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32); + SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0); MemOps.push_back(Store); @@ -1387,14 +1387,14 @@ X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) { ArgValues.size()).getValue(Op.ResNo); } -SDOperand -X86TargetLowering::LowerMemOpCallTo(SDOperand Op, SelectionDAG &DAG, - const SDOperand &StackPtr, +SDValue +X86TargetLowering::LowerMemOpCallTo(SDValue Op, SelectionDAG &DAG, + const SDValue &StackPtr, const CCValAssign &VA, - SDOperand Chain, - SDOperand Arg) { + SDValue Chain, + SDValue Arg) { unsigned LocMemOffset = VA.getLocMemOffset(); - SDOperand PtrOff = DAG.getIntPtrConstant(LocMemOffset); + SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff); ISD::ArgFlagsTy Flags = cast<ARG_FLAGSSDNode>(Op.getOperand(6+2*VA.getValNo()))->getArgFlags(); @@ -1407,10 +1407,10 @@ X86TargetLowering::LowerMemOpCallTo(SDOperand Op, SelectionDAG &DAG, /// EmitTailCallLoadRetAddr - Emit a load of return adress if tail call /// optimization is performed and it is required. -SDOperand +SDValue X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, - SDOperand &OutRetAddr, - SDOperand Chain, + SDValue &OutRetAddr, + SDValue Chain, bool IsTailCall, bool Is64Bit, int FPDiff) { @@ -1421,14 +1421,14 @@ X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, OutRetAddr = getReturnAddressFrameIndex(DAG); // Load the "old" Return address. OutRetAddr = DAG.getLoad(VT, Chain,OutRetAddr, NULL, 0); - return SDOperand(OutRetAddr.Val, 1); + return SDValue(OutRetAddr.Val, 1); } /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call /// optimization is performed and it is required (FPDiff!=0). -static SDOperand +static SDValue EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, - SDOperand Chain, SDOperand RetAddrFrIdx, + SDValue Chain, SDValue RetAddrFrIdx, bool Is64Bit, int FPDiff) { // Store the return address to the appropriate stack slot. if (!FPDiff) return Chain; @@ -1437,20 +1437,20 @@ EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, int NewReturnAddrFI = MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize); MVT VT = Is64Bit ? MVT::i64 : MVT::i32; - SDOperand NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT); + SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT); Chain = DAG.getStore(Chain, RetAddrFrIdx, NewRetAddrFrIdx, PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0); return Chain; } -SDOperand X86TargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) { +SDValue X86TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) { MachineFunction &MF = DAG.getMachineFunction(); - SDOperand Chain = Op.getOperand(0); + SDValue Chain = Op.getOperand(0); unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; bool IsTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0 && CC == CallingConv::Fast && PerformTailCallOpt; - SDOperand Callee = Op.getOperand(4); + SDValue Callee = Op.getOperand(4); bool Is64Bit = Subtarget->is64Bit(); bool IsStructRet = CallIsStructReturn(Op); @@ -1489,20 +1489,20 @@ SDOperand X86TargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) { Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes)); - SDOperand RetAddrFrIdx; + SDValue RetAddrFrIdx; // Load return adress for tail calls. Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, IsTailCall, Is64Bit, FPDiff); - SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass; - SmallVector<SDOperand, 8> MemOpChains; - SDOperand StackPtr; + SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; + SmallVector<SDValue, 8> MemOpChains; + SDValue StackPtr; // Walk the register/memloc assignments, inserting copies/loads. In the case // of tail call optimization arguments are handle later. for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { CCValAssign &VA = ArgLocs[i]; - SDOperand Arg = Op.getOperand(5+2*VA.getValNo()); + SDValue Arg = Op.getOperand(5+2*VA.getValNo()); bool isByVal = cast<ARG_FLAGSSDNode>(Op.getOperand(6+2*VA.getValNo()))-> getArgFlags().isByVal(); @@ -1565,7 +1565,7 @@ SDOperand X86TargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) { // Build a sequence of copy-to-reg nodes chained together with token chain // and flag operands which copy the outgoing args into registers. - SDOperand InFlag; + SDValue InFlag; // Tail call byval lowering might overwrite argument registers so in case of // tail call optimization the copies to registers are lowered later. if (!IsTailCall) @@ -1624,17 +1624,17 @@ SDOperand X86TargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) { // For tail calls lower the arguments to the 'real' stack slot. if (IsTailCall) { - SmallVector<SDOperand, 8> MemOpChains2; - SDOperand FIN; + SmallVector<SDValue, 8> MemOpChains2; + SDValue FIN; int FI = 0; // Do not flag preceeding copytoreg stuff together with the following stuff. - InFlag = SDOperand(); + InFlag = SDValue(); for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { CCValAssign &VA = ArgLocs[i]; if (!VA.isRegLoc()) { assert(VA.isMemLoc()); - SDOperand Arg = Op.getOperand(5+2*VA.getValNo()); - SDOperand FlagsOp = Op.getOperand(6+2*VA.getValNo()); + SDValue Arg = Op.getOperand(5+2*VA.getValNo()); + SDValue FlagsOp = Op.getOperand(6+2*VA.getValNo()); ISD::ArgFlagsTy Flags = cast<ARG_FLAGSSDNode>(FlagsOp)->getArgFlags(); // Create frame index. @@ -1645,7 +1645,7 @@ SDOperand X86TargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) { if (Flags.isByVal()) { // Copy relative to framepointer. - SDOperand Source = DAG.getIntPtrConstant(VA.getLocMemOffset()); + SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset()); if (StackPtr.Val == 0) StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy()); Source = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, Source); @@ -1671,7 +1671,7 @@ SDOperand X86TargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) { InFlag); InFlag = Chain.getValue(1); } - InFlag =SDOperand(); + InFlag =SDValue(); // Store the return address to the appropriate stack slot. Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit, @@ -1701,7 +1701,7 @@ SDOperand X86TargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) { // Returns a chain & a flag for retval copy to use. SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); - SmallVector<SDOperand, 8> Ops; + SmallVector<SDValue, 8> Ops; if (IsTailCall) { Ops.push_back(Chain); @@ -1748,7 +1748,7 @@ SDOperand X86TargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) { Chain = DAG.getNode(X86ISD::TAILCALL, Op.Val->getVTList(), &Ops[0], Ops.size()); - return SDOperand(Chain.Val, Op.ResNo); + return SDValue(Chain.Val, Op.ResNo); } Chain = DAG.getNode(X86ISD::CALL, NodeTys, &Ops[0], Ops.size()); @@ -1775,7 +1775,7 @@ SDOperand X86TargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) { // Handle result values, copying them out of physregs into vregs that we // return. - return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo); + return SDValue(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo); } @@ -1839,8 +1839,8 @@ unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, /// following the call is a return. A function is eligible if caller/callee /// calling conventions match, currently only fastcc supports tail calls, and /// the function CALL is immediatly followed by a RET. -bool X86TargetLowering::IsEligibleForTailCallOptimization(SDOperand Call, - SDOperand Ret, +bool X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Call, + SDValue Ret, SelectionDAG& DAG) const { if (!PerformTailCallOpt) return false; @@ -1850,7 +1850,7 @@ bool X86TargetLowering::IsEligibleForTailCallOptimization(SDOperand Call, unsigned CallerCC = MF.getFunction()->getCallingConv(); unsigned CalleeCC = cast<ConstantSDNode>(Call.getOperand(1))->getValue(); if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) { - SDOperand Callee = Call.getOperand(4); + SDValue Callee = Call.getOperand(4); // On x86/32Bit PIC/GOT tail calls are supported. if (getTargetMachine().getRelocationModel() != Reloc::PIC_ || !Subtarget->isPICStyleGOT()|| !Subtarget->is64Bit()) @@ -1872,7 +1872,7 @@ bool X86TargetLowering::IsEligibleForTailCallOptimization(SDOperand Call, //===----------------------------------------------------------------------===// -SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) { +SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) { MachineFunction &MF = DAG.getMachineFunction(); X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); int ReturnAddrIndex = FuncInfo->getRAIndex(); @@ -1897,7 +1897,7 @@ SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) { /// translation. X86CC is the translated CondCode. LHS/RHS are modified as /// needed. static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP, - unsigned &X86CC, SDOperand &LHS, SDOperand &RHS, + unsigned &X86CC, SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) { X86CC = X86::COND_INVALID; if (!isFP) { @@ -1989,7 +1989,7 @@ static bool hasFPCMov(unsigned X86CC) { /// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return /// true if Op is undef or if its value falls within the specified range (L, H]. -static bool isUndefOrInRange(SDOperand Op, unsigned Low, unsigned Hi) { +static bool isUndefOrInRange(SDValue Op, unsigned Low, unsigned Hi) { if (Op.getOpcode() == ISD::UNDEF) return true; @@ -1999,7 +1999,7 @@ static bool isUndefOrInRange(SDOperand Op, unsigned Low, unsigned Hi) { /// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return /// true if Op is undef or if its value equal to the specified value. -static bool isUndefOrEqual(SDOperand Op, unsigned Val) { +static bool isUndefOrEqual(SDValue Op, unsigned Val) { if (Op.getOpcode() == ISD::UNDEF) return true; return cast<ConstantSDNode>(Op)->getValue() == Val; @@ -2015,7 +2015,7 @@ bool X86::isPSHUFDMask(SDNode *N) { // Check if the value doesn't reference the second vector. for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { - SDOperand Arg = N->getOperand(i); + SDValue Arg = N->getOperand(i); if (Arg.getOpcode() == ISD::UNDEF) continue; assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); if (cast<ConstantSDNode>(Arg)->getValue() >= e) @@ -2035,7 +2035,7 @@ bool X86::isPSHUFHWMask(SDNode *N) { // Lower quadword copied in order. for (unsigned i = 0; i != 4; ++i) { - SDOperand Arg = N->getOperand(i); + SDValue Arg = N->getOperand(i); if (Arg.getOpcode() == ISD::UNDEF) continue; assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); if (cast<ConstantSDNode>(Arg)->getValue() != i) @@ -2044,7 +2044,7 @@ bool X86::isPSHUFHWMask(SDNode *N) { // Upper quadword shuffled. for (unsigned i = 4; i != 8; ++i) { - SDOperand Arg = N->getOperand(i); + SDValue Arg = N->getOperand(i); if (Arg.getOpcode() == ISD::UNDEF) continue; assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); @@ -2185,7 +2185,7 @@ bool X86::isMOVHPMask(SDNode *N) { return false; for (unsigned i = 0; i < NumElems/2; ++i) { - SDOperand Arg = N->getOperand(i + NumElems/2); + SDValue Arg = N->getOperand(i + NumElems/2); if (!isUndefOrEqual(Arg, i + NumElems)) return false; } @@ -2201,8 +2201,8 @@ bool static isUNPCKLMask(SDOperandPtr Elts, unsigned NumElts, return false; for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) { - SDOperand BitI = Elts[i]; - SDOperand BitI1 = Elts[i+1]; + SDValue BitI = Elts[i]; + SDValue BitI1 = Elts[i+1]; if (!isUndefOrEqual(BitI, j)) return false; if (V2IsSplat) { @@ -2230,8 +2230,8 @@ bool static isUNPCKHMask(SDOperandPtr Elts, unsigned NumElts, return false; for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) { - SDOperand BitI = Elts[i]; - SDOperand BitI1 = Elts[i+1]; + SDValue BitI = Elts[i]; + SDValue BitI1 = Elts[i+1]; if (!isUndefOrEqual(BitI, j + NumElts/2)) return false; if (V2IsSplat) { @@ -2262,8 +2262,8 @@ bool X86::isUNPCKL_v_undef_Mask(SDNode *N) { return false; for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) { - SDOperand BitI = N->getOperand(i); - SDOperand BitI1 = N->getOperand(i+1); + SDValue BitI = N->getOperand(i); + SDValue BitI1 = N->getOperand(i+1); if (!isUndefOrEqual(BitI, j)) return false; @@ -2285,8 +2285,8 @@ bool X86::isUNPCKH_v_undef_Mask(SDNode *N) { return false; for (unsigned i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) { - SDOperand BitI = N->getOperand(i); - SDOperand BitI1 = N->getOperand(i + 1); + SDValue BitI = N->getOperand(i); + SDValue BitI1 = N->getOperand(i + 1); if (!isUndefOrEqual(BitI, j)) return false; @@ -2333,7 +2333,7 @@ static bool isCommutedMOVL(SDOperandPtr Ops, unsigned NumOps, return false; for (unsigned i = 1; i < NumOps; ++i) { - SDOperand Arg = Ops[i]; + SDValue Arg = Ops[i]; if (!(isUndefOrEqual(Arg, i+NumOps) || (V2IsUndef && isUndefOrInRange(Arg, NumOps, NumOps*2)) || (V2IsSplat && isUndefOrEqual(Arg, NumOps)))) @@ -2360,7 +2360,7 @@ bool X86::isMOVSHDUPMask(SDNode *N) { // Expect 1, 1, 3, 3 for (unsigned i = 0; i < 2; ++i) { - SDOperand Arg = N->getOperand(i); + SDValue Arg = N->getOperand(i); if (Arg.getOpcode() == ISD::UNDEF) continue; assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); @@ -2369,7 +2369,7 @@ bool X86::isMOVSHDUPMask(SDNode *N) { bool HasHi = false; for (unsigned i = 2; i < 4; ++i) { - SDOperand Arg = N->getOperand(i); + SDValue Arg = N->getOperand(i); if (Arg.getOpcode() == ISD::UNDEF) continue; assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); @@ -2391,7 +2391,7 @@ bool X86::isMOVSLDUPMask(SDNode *N) { // Expect 0, 0, 2, 2 for (unsigned i = 0; i < 2; ++i) { - SDOperand Arg = N->getOperand(i); + SDValue Arg = N->getOperand(i); if (Arg.getOpcode() == ISD::UNDEF) continue; assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); @@ -2400,7 +2400,7 @@ bool X86::isMOVSLDUPMask(SDNode *N) { bool HasHi = false; for (unsigned i = 2; i < 4; ++i) { - SDOperand Arg = N->getOperand(i); + SDValue Arg = N->getOperand(i); if (Arg.getOpcode() == ISD::UNDEF) continue; assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); @@ -2430,10 +2430,10 @@ static bool isSplatMask(SDNode *N) { // This is a splat operation if each element of the permute is the same, and // if the value doesn't reference the second vector. unsigned NumElems = N->getNumOperands(); - SDOperand ElementBase; + SDValue ElementBase; unsigned i = 0; for (; i != NumElems; ++i) { - SDOperand Elt = N->getOperand(i); + SDValue Elt = N->getOperand(i); if (isa<ConstantSDNode>(Elt)) { ElementBase = Elt; break; @@ -2444,7 +2444,7 @@ static bool isSplatMask(SDNode *N) { return false; for (; i != NumElems; ++i) { - SDOperand Arg = N->getOperand(i); + SDValue Arg = N->getOperand(i); if (Arg.getOpcode() == ISD::UNDEF) continue; assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); if (Arg != ElementBase) return false; @@ -2485,7 +2485,7 @@ unsigned X86::getShuffleSHUFImmediate(SDNode *N) { unsigned Mask = 0; for (unsigned i = 0; i < NumOperands; ++i) { unsigned Val = 0; - SDOperand Arg = N->getOperand(NumOperands-i-1); + SDValue Arg = N->getOperand(NumOperands-i-1); if (Arg.getOpcode() != ISD::UNDEF) Val = cast<ConstantSDNode>(Arg)->getValue(); if (Val >= NumOperands) Val -= NumOperands; @@ -2505,7 +2505,7 @@ unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) { // 8 nodes, but we only care about the last 4. for (unsigned i = 7; i >= 4; --i) { unsigned Val = 0; - SDOperand Arg = N->getOperand(i); + SDValue Arg = N->getOperand(i); if (Arg.getOpcode() != ISD::UNDEF) Val = cast<ConstantSDNode>(Arg)->getValue(); Mask |= (Val - 4); @@ -2524,7 +2524,7 @@ unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) { // 8 nodes, but we only care about the first 4. for (int i = 3; i >= 0; --i) { unsigned Val = 0; - SDOperand Arg = N->getOperand(i); + SDValue Arg = N->getOperand(i); if (Arg.getOpcode() != ISD::UNDEF) Val = cast<ConstantSDNode>(Arg)->getValue(); Mask |= Val; @@ -2546,7 +2546,7 @@ static bool isPSHUFHW_PSHUFLWMask(SDNode *N) { // Lower quadword shuffled. for (unsigned i = 0; i != 4; ++i) { - SDOperand Arg = N->getOperand(i); + SDValue Arg = N->getOperand(i); if (Arg.getOpcode() == ISD::UNDEF) continue; assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); @@ -2556,7 +2556,7 @@ static bool isPSHUFHW_PSHUFLWMask(SDNode *N) { // Upper quadword shuffled. for (unsigned i = 4; i != 8; ++i) { - SDOperand Arg = N->getOperand(i); + SDValue Arg = N->getOperand(i); if (Arg.getOpcode() == ISD::UNDEF) continue; assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); @@ -2569,17 +2569,17 @@ static bool isPSHUFHW_PSHUFLWMask(SDNode *N) { /// CommuteVectorShuffle - Swap vector_shuffle operands as well as /// values in ther permute mask. -static SDOperand CommuteVectorShuffle(SDOperand Op, SDOperand &V1, - SDOperand &V2, SDOperand &Mask, +static SDValue CommuteVectorShuffle(SDValue Op, SDValue &V1, + SDValue &V2, SDValue &Mask, SelectionDAG &DAG) { MVT VT = Op.getValueType(); MVT MaskVT = Mask.getValueType(); MVT EltVT = MaskVT.getVectorElementType(); unsigned NumElems = Mask.getNumOperands(); - SmallVector<SDOperand, 8> MaskVec; + SmallVector<SDValue, 8> MaskVec; for (unsigned i = 0; i != NumElems; ++i) { - SDOperand Arg = Mask.getOperand(i); + SDValue Arg = Mask.getOperand(i); if (Arg.getOpcode() == ISD::UNDEF) { MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT)); continue; @@ -2600,13 +2600,13 @@ static SDOperand CommuteVectorShuffle(SDOperand Op, SDOperand &V1, /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming /// the two vector operands have swapped position. static -SDOperand CommuteVectorShuffleMask(SDOperand Mask, SelectionDAG &DAG) { +SDValue CommuteVectorShuffleMask(SDValue Mask, SelectionDAG &DAG) { MVT MaskVT = Mask.getValueType(); MVT EltVT = MaskVT.getVectorElementType(); unsigned NumElems = Mask.getNumOperands(); - SmallVector<SDOperand, 8> MaskVec; + SmallVector<SDValue, 8> MaskVec; for (unsigned i = 0; i != NumElems; ++i) { - SDOperand Arg = Mask.getOperand(i); + SDValue Arg = Mask.getOperand(i); if (Arg.getOpcode() == ISD::UNDEF) { MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT)); continue; @@ -2685,7 +2685,7 @@ static bool isSplatVector(SDNode *N) { if (N->getOpcode() != ISD::BUILD_VECTOR) return false; - SDOperand SplatValue = N->getOperand(0); + SDValue SplatValue = N->getOperand(0); for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) if (N->getOperand(i) != SplatValue) return false; @@ -2698,12 +2698,12 @@ static bool isUndefShuffle(SDNode *N) { if (N->getOpcode() != ISD::VECTOR_SHUFFLE) return false; - SDOperand V1 = N->getOperand(0); - SDOperand V2 = N->getOperand(1); - SDOperand Mask = N->getOperand(2); + SDValue V1 = N->getOperand(0); + SDValue V2 = N->getOperand(1); + SDValue Mask = N->getOperand(2); unsigned NumElems = Mask.getNumOperands(); for (unsigned i = 0; i != NumElems; ++i) { - SDOperand Arg = Mask.getOperand(i); + SDValue Arg = Mask.getOperand(i); if (Arg.getOpcode() != ISD::UNDEF) { unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); if (Val < NumElems && V1.getOpcode() != ISD::UNDEF) @@ -2717,7 +2717,7 @@ static bool isUndefShuffle(SDNode *N) { /// isZeroNode - Returns true if Elt is a constant zero or a floating point /// constant +0.0. -static inline bool isZeroNode(SDOperand Elt) { +static inline bool isZeroNode(SDValue Elt) { return ((isa<ConstantSDNode>(Elt) && cast<ConstantSDNode>(Elt)->getValue() == 0) || (isa<ConstantFPSDNode>(Elt) && @@ -2730,12 +2730,12 @@ static bool isZeroShuffle(SDNode *N) { if (N->getOpcode() != ISD::VECTOR_SHUFFLE) return false; - SDOperand V1 = N->getOperand(0); - SDOperand V2 = N->getOperand(1); - SDOperand Mask = N->getOperand(2); + SDValue V1 = N->getOperand(0); + SDValue V2 = N->getOperand(1); + SDValue Mask = N->getOperand(2); unsigned NumElems = Mask.getNumOperands(); for (unsigned i = 0; i != NumElems; ++i) { - SDOperand Arg = Mask.getOperand(i); + SDValue Arg = Mask.getOperand(i); if (Arg.getOpcode() == ISD::UNDEF) continue; @@ -2761,20 +2761,20 @@ static bool isZeroShuffle(SDNode *N) { /// getZeroVector - Returns a vector of specified type with all zero elements. /// -static SDOperand getZeroVector(MVT VT, bool HasSSE2, SelectionDAG &DAG) { +static SDValue getZeroVector(MVT VT, bool HasSSE2, SelectionDAG &DAG) { assert(VT.isVector() && "Expected a vector type"); // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest // type. This ensures they get CSE'd. - SDOperand Vec; + SDValue Vec; if (VT.getSizeInBits() == 64) { // MMX - SDOperand Cst = DAG.getTargetConstant(0, MVT::i32); + SDValue Cst = DAG.getTargetConstant(0, MVT::i32); Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst); } else if (HasSSE2) { // SSE2 - SDOperand Cst = DAG.getTargetConstant(0, MVT::i32); + SDValue Cst = DAG.getTargetConstant(0, MVT::i32); Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst); } else { // SSE1 - SDOperand Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); + SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4f32, Cst, Cst, Cst, Cst); } return DAG.getNode(ISD::BIT_CONVERT, VT, Vec); @@ -2782,13 +2782,13 @@ static SDOperand getZeroVector(MVT VT, bool HasSSE2, SelectionDAG &DAG) { /// getOnesVector - Returns a vector of specified type with all bits set. /// -static SDOperand getOnesVector(MVT VT, SelectionDAG &DAG) { +static SDValue getOnesVector(MVT VT, SelectionDAG &DAG) { assert(VT.isVector() && "Expected a vector type"); // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest // type. This ensures they get CSE'd. - SDOperand Cst = DAG.getTargetConstant(~0U, MVT::i32); - SDOperand Vec; + SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); + SDValue Vec; if (VT.getSizeInBits() == 64) // MMX Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst); else // SSE @@ -2799,14 +2799,14 @@ static SDOperand getOnesVector(MVT VT, SelectionDAG &DAG) { /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements /// that point to V2 points to its first element. -static SDOperand NormalizeMask(SDOperand Mask, SelectionDAG &DAG) { +static SDValue NormalizeMask(SDValue Mask, SelectionDAG &DAG) { assert(Mask.getOpcode() == ISD::BUILD_VECTOR); bool Changed = false; - SmallVector<SDOperand, 8> MaskVec; + SmallVector<SDValue, 8> MaskVec; unsigned NumElems = Mask.getNumOperands(); for (unsigned i = 0; i != NumElems; ++i) { - SDOperand Arg = Mask.getOperand(i); + SDValue Arg = Mask.getOperand(i); if (Arg.getOpcode() != ISD::UNDEF) { unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); if (Val > NumElems) { @@ -2825,11 +2825,11 @@ static SDOperand NormalizeMask(SDOperand Mask, SelectionDAG &DAG) { /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd /// operation of specified width. -static SDOperand getMOVLMask(unsigned NumElems, SelectionDAG &DAG) { +static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG) { MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); MVT BaseVT = MaskVT.getVectorElementType(); - SmallVector<SDOperand, 8> MaskVec; + SmallVector<SDValue, 8> MaskVec; MaskVec.push_back(DAG.getConstant(NumElems, BaseVT)); for (unsigned i = 1; i != NumElems; ++i) MaskVec.push_back(DAG.getConstant(i, BaseVT)); @@ -2838,10 +2838,10 @@ static SDOperand getMOVLMask(unsigned NumElems, SelectionDAG &DAG) { /// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation /// of specified width. -static SDOperand getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) { +static SDValue getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) { MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); MVT BaseVT = MaskVT.getVectorElementType(); - SmallVector<SDOperand, 8> MaskVec; + SmallVector<SDValue, 8> MaskVec; for (unsigned i = 0, e = NumElems/2; i != e; ++i) { MaskVec.push_back(DAG.getConstant(i, BaseVT)); MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT)); @@ -2851,11 +2851,11 @@ static SDOperand getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) { /// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation /// of specified width. -static SDOperand getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) { +static SDValue getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) { MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); MVT BaseVT = MaskVT.getVectorElementType(); unsigned Half = NumElems/2; - SmallVector<SDOperand, 8> MaskVec; + SmallVector<SDValue, 8> MaskVec; for (unsigned i = 0; i != Half; ++i) { MaskVec.push_back(DAG.getConstant(i + Half, BaseVT)); MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT)); @@ -2866,11 +2866,11 @@ static SDOperand getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) { /// getSwapEltZeroMask - Returns a vector_shuffle mask for a shuffle that swaps /// element #0 of a vector with the specified index, leaving the rest of the /// elements in place. -static SDOperand getSwapEltZeroMask(unsigned NumElems, unsigned DestElt, +static SDValue getSwapEltZeroMask(unsigned NumElems, unsigned DestElt, SelectionDAG &DAG) { MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); MVT BaseVT = MaskVT.getVectorElementType(); - SmallVector<SDOperand, 8> MaskVec; + SmallVector<SDValue, 8> MaskVec; // Element #0 of the result gets the elt we are replacing. MaskVec.push_back(DAG.getConstant(DestElt, BaseVT)); for (unsigned i = 1; i != NumElems; ++i) @@ -2879,13 +2879,13 @@ static SDOperand getSwapEltZeroMask(unsigned NumElems, unsigned DestElt, } /// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32. -static SDOperand PromoteSplat(SDOperand Op, SelectionDAG &DAG, bool HasSSE2) { +static SDValue PromoteSplat(SDValue Op, SelectionDAG &DAG, bool HasSSE2) { MVT PVT = HasSSE2 ? MVT::v4i32 : MVT::v4f32; MVT VT = Op.getValueType(); if (PVT == VT) return Op; - SDOperand V1 = Op.getOperand(0); - SDOperand Mask = Op.getOperand(2); + SDValue V1 = Op.getOperand(0); + SDValue Mask = Op.getOperand(2); unsigned NumElems = Mask.getNumOperands(); // Special handling of v4f32 -> v4i32. if (VT != MVT::v4f32) { @@ -2898,7 +2898,7 @@ static SDOperand PromoteSplat(SDOperand Op, SelectionDAG &DAG, bool HasSSE2) { } V1 = DAG.getNode(ISD::BIT_CONVERT, PVT, V1); - SDOperand Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, PVT, V1, + SDValue Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, PVT, V1, DAG.getNode(ISD::UNDEF, PVT), Mask); return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle); } @@ -2907,22 +2907,22 @@ static SDOperand PromoteSplat(SDOperand Op, SelectionDAG &DAG, bool HasSSE2) { /// vector of zero or undef vector. This produces a shuffle where the low /// element of V2 is swizzled into the zero/undef vector, landing at element /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3). -static SDOperand getShuffleVectorZeroOrUndef(SDOperand V2, unsigned Idx, +static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, bool isZero, bool HasSSE2, SelectionDAG &DAG) { MVT VT = V2.getValueType(); - SDOperand V1 = isZero + SDValue V1 = isZero ? getZeroVector(VT, HasSSE2, DAG) : DAG.getNode(ISD::UNDEF, VT); unsigned NumElems = V2.getValueType().getVectorNumElements(); MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); MVT EVT = MaskVT.getVectorElementType(); - SmallVector<SDOperand, 16> MaskVec; + SmallVector<SDValue, 16> MaskVec; for (unsigned i = 0; i != NumElems; ++i) if (i == Idx) // If this is the insertion idx, put the low elt of V2 here. MaskVec.push_back(DAG.getConstant(NumElems, EVT)); else MaskVec.push_back(DAG.getConstant(i, EVT)); - SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, + SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size()); return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask); } @@ -2930,18 +2930,18 @@ static SDOperand getShuffleVectorZeroOrUndef(SDOperand V2, unsigned Idx, /// getNumOfConsecutiveZeros - Return the number of elements in a result of /// a shuffle that is zero. static -unsigned getNumOfConsecutiveZeros(SDOperand Op, SDOperand Mask, +unsigned getNumOfConsecutiveZeros(SDValue Op, SDValue Mask, unsigned NumElems, bool Low, SelectionDAG &DAG) { unsigned NumZeros = 0; for (unsigned i = 0; i < NumElems; ++i) { unsigned Index = Low ? i : NumElems-i-1; - SDOperand Idx = Mask.getOperand(Index); + SDValue Idx = Mask.getOperand(Index); if (Idx.getOpcode() == ISD::UNDEF) { ++NumZeros; continue; } - SDOperand Elt = DAG.getShuffleScalarElt(Op.Val, Index); + SDValue Elt = DAG.getShuffleScalarElt(Op.Val, Index); if (Elt.Val && isZeroNode(Elt)) ++NumZeros; else @@ -2952,8 +2952,8 @@ unsigned getNumOfConsecutiveZeros(SDOperand Op, SDOperand Mask, /// isVectorShift - Returns true if the shuffle can be implemented as a /// logical left or right shift of a vector. -static bool isVectorShift(SDOperand Op, SDOperand Mask, SelectionDAG &DAG, - bool &isLeft, SDOperand &ShVal, unsigned &ShAmt) { +static bool isVectorShift(SDValue Op, SDValue Mask, SelectionDAG &DAG, + bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { unsigned NumElems = Mask.getNumOperands(); isLeft = true; @@ -2969,7 +2969,7 @@ static bool isVectorShift(SDOperand Op, SDOperand Mask, SelectionDAG &DAG, bool SeenV2 = false; for (unsigned i = NumZeros; i < NumElems; ++i) { unsigned Val = isLeft ? (i - NumZeros) : i; - SDOperand Idx = Mask.getOperand(isLeft ? i : (i - NumZeros)); + SDValue Idx = Mask.getOperand(isLeft ? i : (i - NumZeros)); if (Idx.getOpcode() == ISD::UNDEF) continue; unsigned Index = cast<ConstantSDNode>(Idx)->getValue(); @@ -2993,13 +2993,13 @@ static bool isVectorShift(SDOperand Op, SDOperand Mask, SelectionDAG &DAG, /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. /// -static SDOperand LowerBuildVectorv16i8(SDOperand Op, unsigned NonZeros, +static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, unsigned NumNonZero, unsigned NumZero, SelectionDAG &DAG, TargetLowering &TLI) { if (NumNonZero > 8) - return SDOperand(); + return SDValue(); - SDOperand V(0, 0); + SDValue V(0, 0); bool First = true; for (unsigned i = 0; i < 16; ++i) { bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; @@ -3012,7 +3012,7 @@ static SDOperand LowerBuildVectorv16i8(SDOperand Op, unsigned NonZeros, } if ((i & 1) != 0) { - SDOperand ThisElt(0, 0), LastElt(0, 0); + SDValue ThisElt(0, 0), LastElt(0, 0); bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; if (LastIsNonZero) { LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1)); @@ -3037,13 +3037,13 @@ static SDOperand LowerBuildVectorv16i8(SDOperand Op, unsigned NonZeros, /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. /// -static SDOperand LowerBuildVectorv8i16(SDOperand Op, unsigned NonZeros, +static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, unsigned NumNonZero, unsigned NumZero, SelectionDAG &DAG, TargetLowering &TLI) { if (NumNonZero > 4) - return SDOperand(); + return SDValue(); - SDOperand V(0, 0); + SDValue V(0, 0); bool First = true; for (unsigned i = 0; i < 8; ++i) { bool isNonZero = (NonZeros & (1 << i)) != 0; @@ -3065,7 +3065,7 @@ static SDOperand LowerBuildVectorv8i16(SDOperand Op, unsigned NonZeros, /// getVShift - Return a vector logical shift node. /// -static SDOperand getVShift(bool isLeft, MVT VT, SDOperand SrcOp, +static SDValue getVShift(bool isLeft, MVT VT, SDValue SrcOp, unsigned NumBits, SelectionDAG &DAG, const TargetLowering &TLI) { bool isMMX = VT.getSizeInBits() == 64; @@ -3077,8 +3077,8 @@ static SDOperand getVShift(bool isLeft, MVT VT, SDOperand SrcOp, DAG.getConstant(NumBits, TLI.getShiftAmountTy()))); } -SDOperand -X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { +SDValue +X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { // All zero's are handled with pxor, all one's are handled with pcmpeqd. if (ISD::isBuildVectorAllZeros(Op.Val) || ISD::isBuildVectorAllOnes(Op.Val)) { // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to @@ -3101,9 +3101,9 @@ X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { unsigned NumNonZero = 0; unsigned NonZeros = 0; bool IsAllConstants = true; - SmallSet<SDOperand, 8> Values; + SmallSet<SDValue, 8> Values; for (unsigned i = 0; i < NumElems; ++i) { - SDOperand Elt = Op.getOperand(i); + SDValue Elt = Op.getOperand(i); if (Elt.getOpcode() == ISD::UNDEF) continue; Values.insert(Elt); @@ -3126,7 +3126,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { // Special case for single non-zero, non-undef, element. if (NumNonZero == 1 && NumElems <= 4) { unsigned Idx = CountTrailingZeros_32(NonZeros); - SDOperand Item = Op.getOperand(Idx); + SDValue Item = Op.getOperand(Idx); // If this is an insertion of an i64 value on x86-32, and if the top bits of // the value are obviously zero, truncate the value to i32 and do the @@ -3150,7 +3150,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { // Now we have our 32-bit value zero extended in the low element of // a vector. If Idx != 0, swizzle it into place. if (Idx != 0) { - SDOperand Ops[] = { + SDValue Ops[] = { Item, DAG.getNode(ISD::UNDEF, Item.getValueType()), getSwapEltZeroMask(VecElts, Idx, DAG) }; @@ -3184,7 +3184,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { } if (IsAllConstants) // Otherwise, it's better to do a constpool load. - return SDOperand(); + return SDValue(); // Otherwise, if this is a vector with i32 or f32 elements, and the element // is a non-constant being inserted into an element other than the low one, @@ -3199,10 +3199,10 @@ X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { Subtarget->hasSSE2(), DAG); MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); MVT MaskEVT = MaskVT.getVectorElementType(); - SmallVector<SDOperand, 8> MaskVec; + SmallVector<SDValue, 8> MaskVec; for (unsigned i = 0; i < NumElems; i++) MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT)); - SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, + SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size()); return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Item, DAG.getNode(ISD::UNDEF, VT), Mask); @@ -3211,41 +3211,41 @@ X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { // Splat is obviously ok. Let legalizer expand it to a shuffle. if (Values.size() == 1) - return SDOperand(); + return SDValue(); // A vector full of immediates; various special cases are already // handled, so this is best done with a single constant-pool load. if (IsAllConstants) - return SDOperand(); + return SDValue(); // Let legalizer expand 2-wide build_vectors. if (EVTBits == 64) { if (NumNonZero == 1) { // One half is zero or undef. unsigned Idx = CountTrailingZeros_32(NonZeros); - SDOperand V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, + SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(Idx)); return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget->hasSSE2(), DAG); } - return SDOperand(); + return SDValue(); } // If element VT is < 32 bits, convert it to inserts into a zero vector. if (EVTBits == 8 && NumElems == 16) { - SDOperand V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, + SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, *this); if (V.Val) return V; } if (EVTBits == 16 && NumElems == 8) { - SDOperand V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, + SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, *this); if (V.Val) return V; } // If element VT is == 32 bits, turn it into a number of shuffles. - SmallVector<SDOperand, 8> V; + SmallVector<SDValue, 8> V; V.resize(NumElems); if (NumElems == 4 && NumZero > 0) { for (unsigned i = 0; i < 4; ++i) { @@ -3279,7 +3279,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); MVT EVT = MaskVT.getVectorElementType(); - SmallVector<SDOperand, 8> MaskVec; + SmallVector<SDValue, 8> MaskVec; bool Reverse = (NonZeros & 0x3) == 2; for (unsigned i = 0; i < 2; ++i) if (Reverse) @@ -3292,7 +3292,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT)); else MaskVec.push_back(DAG.getConstant(i+NumElems, EVT)); - SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, + SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size()); return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[0], V[1], ShufMask); } @@ -3303,7 +3303,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> - SDOperand UnpckMask = getUnpacklMask(NumElems, DAG); + SDValue UnpckMask = getUnpacklMask(NumElems, DAG); for (unsigned i = 0; i < NumElems; ++i) V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i)); NumElems >>= 1; @@ -3316,24 +3316,24 @@ X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { return V[0]; } - return SDOperand(); + return SDValue(); } static -SDOperand LowerVECTOR_SHUFFLEv8i16(SDOperand V1, SDOperand V2, - SDOperand PermMask, SelectionDAG &DAG, +SDValue LowerVECTOR_SHUFFLEv8i16(SDValue V1, SDValue V2, + SDValue PermMask, SelectionDAG &DAG, TargetLowering &TLI) { - SDOperand NewV; + SDValue NewV; MVT MaskVT = MVT::getIntVectorWithNumElements(8); MVT MaskEVT = MaskVT.getVectorElementType(); MVT PtrVT = TLI.getPointerTy(); - SmallVector<SDOperand, 8> MaskElts(PermMask.Val->op_begin(), + SmallVector<SDValue, 8> MaskElts(PermMask.Val->op_begin(), PermMask.Val->op_end()); // First record which half of which vector the low elements come from. SmallVector<unsigned, 4> LowQuad(4); for (unsigned i = 0; i < 4; ++i) { - SDOperand Elt = MaskElts[i]; + SDValue Elt = MaskElts[i]; if (Elt.getOpcode() == ISD::UNDEF) continue; unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue(); @@ -3352,7 +3352,7 @@ SDOperand LowerVECTOR_SHUFFLEv8i16(SDOperand V1, SDOperand V2, // Record which half of which vector the high elements come from. SmallVector<unsigned, 4> HighQuad(4); for (unsigned i = 4; i < 8; ++i) { - SDOperand Elt = MaskElts[i]; + SDValue Elt = MaskElts[i]; if (Elt.getOpcode() == ISD::UNDEF) continue; unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue(); @@ -3371,7 +3371,7 @@ SDOperand LowerVECTOR_SHUFFLEv8i16(SDOperand V1, SDOperand V2, // If it's possible to sort parts of either half with PSHUF{H|L}W, then do it. if (BestLowQuad != -1 || BestHighQuad != -1) { // First sort the 4 chunks in order using shufpd. - SmallVector<SDOperand, 8> MaskVec; + SmallVector<SDValue, 8> MaskVec; if (BestLowQuad != -1) MaskVec.push_back(DAG.getConstant(BestLowQuad, MVT::i32)); else @@ -3380,7 +3380,7 @@ SDOperand LowerVECTOR_SHUFFLEv8i16(SDOperand V1, SDOperand V2, MaskVec.push_back(DAG.getConstant(BestHighQuad, MVT::i32)); else MaskVec.push_back(DAG.getConstant(1, MVT::i32)); - SDOperand Mask= DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, &MaskVec[0],2); + SDValue Mask= DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, &MaskVec[0],2); NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64, DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V1), DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V2), Mask); @@ -3393,7 +3393,7 @@ SDOperand LowerVECTOR_SHUFFLEv8i16(SDOperand V1, SDOperand V2, MaskVec.clear(); bool AnyOutOrder = false; for (unsigned i = 0; i != 4; ++i) { - SDOperand Elt = MaskElts[i]; + SDValue Elt = MaskElts[i]; if (Elt.getOpcode() == ISD::UNDEF) { MaskVec.push_back(Elt); InOrder.set(i); @@ -3411,7 +3411,7 @@ SDOperand LowerVECTOR_SHUFFLEv8i16(SDOperand V1, SDOperand V2, if (AnyOutOrder) { for (unsigned i = 4; i != 8; ++i) MaskVec.push_back(DAG.getConstant(i, MaskEVT)); - SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8); + SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8); NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask); } } @@ -3423,7 +3423,7 @@ SDOperand LowerVECTOR_SHUFFLEv8i16(SDOperand V1, SDOperand V2, MaskVec.push_back(DAG.getConstant(i, MaskEVT)); bool AnyOutOrder = false; for (unsigned i = 4; i != 8; ++i) { - SDOperand Elt = MaskElts[i]; + SDValue Elt = MaskElts[i]; if (Elt.getOpcode() == ISD::UNDEF) { MaskVec.push_back(Elt); InOrder.set(i); @@ -3439,7 +3439,7 @@ SDOperand LowerVECTOR_SHUFFLEv8i16(SDOperand V1, SDOperand V2, } } if (AnyOutOrder) { - SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8); + SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8); NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask); } } @@ -3448,9 +3448,9 @@ SDOperand LowerVECTOR_SHUFFLEv8i16(SDOperand V1, SDOperand V2, for (unsigned i = 0; i != 8; ++i) { if (InOrder[i]) continue; - SDOperand Elt = MaskElts[i]; + SDValue Elt = MaskElts[i]; unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue(); - SDOperand ExtOp = (EltIdx < 8) + SDValue ExtOp = (EltIdx < 8) ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1, DAG.getConstant(EltIdx, PtrVT)) : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2, @@ -3468,10 +3468,10 @@ SDOperand LowerVECTOR_SHUFFLEv8i16(SDOperand V1, SDOperand V2, unsigned V1FromV1 = 0; unsigned V2InOrder = 0; unsigned V2FromV2 = 0; - SmallVector<SDOperand, 8> V1Elts; - SmallVector<SDOperand, 8> V2Elts; + SmallVector<SDValue, 8> V1Elts; + SmallVector<SDValue, 8> V2Elts; for (unsigned i = 0; i < 8; ++i) { - SDOperand Elt = MaskElts[i]; + SDValue Elt = MaskElts[i]; if (Elt.getOpcode() == ISD::UNDEF) { V1Elts.push_back(Elt); V2Elts.push_back(Elt); @@ -3509,9 +3509,9 @@ SDOperand LowerVECTOR_SHUFFLEv8i16(SDOperand V1, SDOperand V2, if (V1FromV1) { // If there are elements that are from V1 but out of place, // then first sort them in place - SmallVector<SDOperand, 8> MaskVec; + SmallVector<SDValue, 8> MaskVec; for (unsigned i = 0; i < 8; ++i) { - SDOperand Elt = V1Elts[i]; + SDValue Elt = V1Elts[i]; if (Elt.getOpcode() == ISD::UNDEF) { MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT)); continue; @@ -3522,19 +3522,19 @@ SDOperand LowerVECTOR_SHUFFLEv8i16(SDOperand V1, SDOperand V2, else MaskVec.push_back(DAG.getConstant(EltIdx, MaskEVT)); } - SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8); + SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8); V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, V1, V1, Mask); } NewV = V1; for (unsigned i = 0; i < 8; ++i) { - SDOperand Elt = V1Elts[i]; + SDValue Elt = V1Elts[i]; if (Elt.getOpcode() == ISD::UNDEF) continue; unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue(); if (EltIdx < 8) continue; - SDOperand ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2, + SDValue ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2, DAG.getConstant(EltIdx - 8, PtrVT)); NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp, DAG.getConstant(i, PtrVT)); @@ -3544,11 +3544,11 @@ SDOperand LowerVECTOR_SHUFFLEv8i16(SDOperand V1, SDOperand V2, // All elements are from V1. NewV = V1; for (unsigned i = 0; i < 8; ++i) { - SDOperand Elt = V1Elts[i]; + SDValue Elt = V1Elts[i]; if (Elt.getOpcode() == ISD::UNDEF) continue; unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue(); - SDOperand ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1, + SDValue ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1, DAG.getConstant(EltIdx, PtrVT)); NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp, DAG.getConstant(i, PtrVT)); @@ -3563,9 +3563,9 @@ SDOperand LowerVECTOR_SHUFFLEv8i16(SDOperand V1, SDOperand V2, /// the right sequence. e.g. /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15> static -SDOperand RewriteAsNarrowerShuffle(SDOperand V1, SDOperand V2, +SDValue RewriteAsNarrowerShuffle(SDValue V1, SDValue V2, MVT VT, - SDOperand PermMask, SelectionDAG &DAG, + SDValue PermMask, SelectionDAG &DAG, TargetLowering &TLI) { unsigned NumElems = PermMask.getNumOperands(); unsigned NewWidth = (NumElems == 4) ? 2 : 4; @@ -3587,18 +3587,18 @@ SDOperand RewriteAsNarrowerShuffle(SDOperand V1, SDOperand V2, NewVT = MVT::v2f64; } unsigned Scale = NumElems / NewWidth; - SmallVector<SDOperand, 8> MaskVec; + SmallVector<SDValue, 8> MaskVec; for (unsigned i = 0; i < NumElems; i += Scale) { unsigned StartIdx = ~0U; for (unsigned j = 0; j < Scale; ++j) { - SDOperand Elt = PermMask.getOperand(i+j); + SDValue Elt = PermMask.getOperand(i+j); if (Elt.getOpcode() == ISD::UNDEF) continue; unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue(); if (StartIdx == ~0U) StartIdx = EltIdx - (EltIdx % Scale); if (EltIdx != StartIdx + j) - return SDOperand(); + return SDValue(); } if (StartIdx == ~0U) MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEltVT)); @@ -3615,8 +3615,8 @@ SDOperand RewriteAsNarrowerShuffle(SDOperand V1, SDOperand V2, /// getVZextMovL - Return a zero-extending vector move low node. /// -static SDOperand getVZextMovL(MVT VT, MVT OpVT, - SDOperand SrcOp, SelectionDAG &DAG, +static SDValue getVZextMovL(MVT VT, MVT OpVT, + SDValue SrcOp, SelectionDAG &DAG, const X86Subtarget *Subtarget) { if (VT == MVT::v2f64 || VT == MVT::v4f32) { LoadSDNode *LD = NULL; @@ -3647,18 +3647,18 @@ static SDOperand getVZextMovL(MVT VT, MVT OpVT, /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of /// shuffles. -static SDOperand -LowerVECTOR_SHUFFLE_4wide(SDOperand V1, SDOperand V2, - SDOperand PermMask, MVT VT, SelectionDAG &DAG) { +static SDValue +LowerVECTOR_SHUFFLE_4wide(SDValue V1, SDValue V2, + SDValue PermMask, MVT VT, SelectionDAG &DAG) { MVT MaskVT = PermMask.getValueType(); MVT MaskEVT = MaskVT.getVectorElementType(); SmallVector<std::pair<int, int>, 8> Locs; Locs.reserve(4); - SmallVector<SDOperand, 8> Mask1(4, DAG.getNode(ISD::UNDEF, MaskEVT)); + SmallVector<SDValue, 8> Mask1(4, DAG.getNode(ISD::UNDEF, MaskEVT)); unsigned NumHi = 0; unsigned NumLo = 0; for (unsigned i = 0; i != 4; ++i) { - SDOperand Elt = PermMask.getOperand(i); + SDValue Elt = PermMask.getOperand(i); if (Elt.getOpcode() == ISD::UNDEF) { Locs[i] = std::make_pair(-1, -1); } else { @@ -3685,7 +3685,7 @@ LowerVECTOR_SHUFFLE_4wide(SDOperand V1, SDOperand V2, DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &Mask1[0], Mask1.size())); - SmallVector<SDOperand, 8> Mask2(4, DAG.getNode(ISD::UNDEF, MaskEVT)); + SmallVector<SDValue, 8> Mask2(4, DAG.getNode(ISD::UNDEF, MaskEVT)); for (unsigned i = 0; i != 4; ++i) { if (Locs[i].first == -1) continue; @@ -3716,7 +3716,7 @@ LowerVECTOR_SHUFFLE_4wide(SDOperand V1, SDOperand V2, // Find the element from V2. unsigned HiIndex; for (HiIndex = 0; HiIndex < 3; ++HiIndex) { - SDOperand Elt = PermMask.getOperand(HiIndex); + SDValue Elt = PermMask.getOperand(HiIndex); if (Elt.getOpcode() == ISD::UNDEF) continue; unsigned Val = cast<ConstantSDNode>(Elt)->getValue(); @@ -3756,9 +3756,9 @@ LowerVECTOR_SHUFFLE_4wide(SDOperand V1, SDOperand V2, // Break it into (shuffle shuffle_hi, shuffle_lo). Locs.clear(); - SmallVector<SDOperand,8> LoMask(4, DAG.getNode(ISD::UNDEF, MaskEVT)); - SmallVector<SDOperand,8> HiMask(4, DAG.getNode(ISD::UNDEF, MaskEVT)); - SmallVector<SDOperand,8> *MaskPtr = &LoMask; + SmallVector<SDValue,8> LoMask(4, DAG.getNode(ISD::UNDEF, MaskEVT)); + SmallVector<SDValue,8> HiMask(4, DAG.getNode(ISD::UNDEF, MaskEVT)); + SmallVector<SDValue,8> *MaskPtr = &LoMask; unsigned MaskIdx = 0; unsigned LoIdx = 0; unsigned HiIdx = 2; @@ -3769,7 +3769,7 @@ LowerVECTOR_SHUFFLE_4wide(SDOperand V1, SDOperand V2, LoIdx = 0; HiIdx = 2; } - SDOperand Elt = PermMask.getOperand(i); + SDValue Elt = PermMask.getOperand(i); if (Elt.getOpcode() == ISD::UNDEF) { Locs[i] = std::make_pair(-1, -1); } else if (cast<ConstantSDNode>(Elt)->getValue() < 4) { @@ -3783,13 +3783,13 @@ LowerVECTOR_SHUFFLE_4wide(SDOperand V1, SDOperand V2, } } - SDOperand LoShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, + SDValue LoShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &LoMask[0], LoMask.size())); - SDOperand HiShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, + SDValue HiShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &HiMask[0], HiMask.size())); - SmallVector<SDOperand, 8> MaskOps; + SmallVector<SDValue, 8> MaskOps; for (unsigned i = 0; i != 4; ++i) { if (Locs[i].first == -1) { MaskOps.push_back(DAG.getNode(ISD::UNDEF, MaskEVT)); @@ -3803,11 +3803,11 @@ LowerVECTOR_SHUFFLE_4wide(SDOperand V1, SDOperand V2, &MaskOps[0], MaskOps.size())); } -SDOperand -X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) { - SDOperand V1 = Op.getOperand(0); - SDOperand V2 = Op.getOperand(1); - SDOperand PermMask = Op.getOperand(2); +SDValue +X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { + SDValue V1 = Op.getOperand(0); + SDValue V2 = Op.getOperand(1); + SDValue PermMask = Op.getOperand(2); MVT VT = Op.getValueType(); unsigned NumElems = PermMask.getNumOperands(); bool isMMX = VT.getSizeInBits() == 64; @@ -3836,26 +3836,26 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) { // If the shuffle can be profitably rewritten as a narrower shuffle, then // do it! if (VT == MVT::v8i16 || VT == MVT::v16i8) { - SDOperand NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this); + SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this); if (NewOp.Val) return DAG.getNode(ISD::BIT_CONVERT, VT, LowerVECTOR_SHUFFLE(NewOp, DAG)); } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) { // FIXME: Figure out a cleaner way to do this. // Try to make use of movq to zero out the top part. if (ISD::isBuildVectorAllZeros(V2.Val)) { - SDOperand NewOp = RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, + SDValue NewOp = RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this); if (NewOp.Val) { - SDOperand NewV1 = NewOp.getOperand(0); - SDOperand NewV2 = NewOp.getOperand(1); - SDOperand NewMask = NewOp.getOperand(2); + SDValue NewV1 = NewOp.getOperand(0); + SDValue NewV2 = NewOp.getOperand(1); + SDValue NewMask = NewOp.getOperand(2); if (isCommutedMOVL(NewMask.Val, true, false)) { NewOp = CommuteVectorShuffle(NewOp, NewV1, NewV2, NewMask, DAG); return getVZextMovL(VT, NewOp.getValueType(), NewV2, DAG, Subtarget); } } } else if (ISD::isBuildVectorAllZeros(V1.Val)) { - SDOperand NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, + SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this); if (NewOp.Val && X86::isMOVLMask(NewOp.getOperand(2).Val)) return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1), @@ -3866,7 +3866,7 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) { // Check if this can be converted into a logical shift. bool isLeft = false; unsigned ShAmt = 0; - SDOperand ShVal; + SDValue ShVal; bool isShift = isVectorShift(Op, PermMask, DAG, isLeft, ShVal, ShAmt); if (isShift && ShVal.hasOneUse()) { // If the shifted value has multiple uses, it may be cheaper to use @@ -3925,7 +3925,7 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) { // V2 is a splat, so the mask may be malformed. That is, it may point // to any V2 element. The instruction selectior won't like this. Get // a corrected mask and commute to form a proper MOVS{S|D}. - SDOperand NewMask = getMOVLMask(NumElems, DAG); + SDValue NewMask = getMOVLMask(NumElems, DAG); if (NewMask.Val != PermMask.Val) Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask); } @@ -3942,13 +3942,13 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) { // Normalize mask so all entries that point to V2 points to its first // element then try to match unpck{h|l} again. If match, return a // new vector_shuffle with the corrected mask. - SDOperand NewMask = NormalizeMask(PermMask, DAG); + SDValue NewMask = NormalizeMask(PermMask, DAG); if (NewMask.Val != PermMask.Val) { if (X86::isUNPCKLMask(PermMask.Val, true)) { - SDOperand NewMask = getUnpacklMask(NumElems, DAG); + SDValue NewMask = getUnpacklMask(NumElems, DAG); return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask); } else if (X86::isUNPCKHMask(PermMask.Val, true)) { - SDOperand NewMask = getUnpackhMask(NumElems, DAG); + SDValue NewMask = getUnpackhMask(NumElems, DAG); return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask); } } @@ -4005,7 +4005,7 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) { // Handle v8i16 specifically since SSE can do byte extraction and insertion. if (VT == MVT::v8i16) { - SDOperand NewOp = LowerVECTOR_SHUFFLEv8i16(V1, V2, PermMask, DAG, *this); + SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(V1, V2, PermMask, DAG, *this); if (NewOp.Val) return NewOp; } @@ -4014,23 +4014,23 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) { if (NumElems == 4 && !isMMX) return LowerVECTOR_SHUFFLE_4wide(V1, V2, PermMask, VT, DAG); - return SDOperand(); + return SDValue(); } -SDOperand -X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDOperand Op, +SDValue +X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) { MVT VT = Op.getValueType(); if (VT.getSizeInBits() == 8) { - SDOperand Extract = DAG.getNode(X86ISD::PEXTRB, MVT::i32, + SDValue Extract = DAG.getNode(X86ISD::PEXTRB, MVT::i32, Op.getOperand(0), Op.getOperand(1)); - SDOperand Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract, + SDValue Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract, DAG.getValueType(VT)); return DAG.getNode(ISD::TRUNCATE, VT, Assert); } else if (VT.getSizeInBits() == 16) { - SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, MVT::i32, + SDValue Extract = DAG.getNode(X86ISD::PEXTRW, MVT::i32, Op.getOperand(0), Op.getOperand(1)); - SDOperand Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract, + SDValue Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract, DAG.getValueType(VT)); return DAG.getNode(ISD::TRUNCATE, VT, Assert); } else if (VT == MVT::f32) { @@ -4038,28 +4038,28 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDOperand Op, // the result back to FR32 register. It's only worth matching if the // result has a single use which is a store or a bitcast to i32. if (!Op.hasOneUse()) - return SDOperand(); + return SDValue(); SDNode *User = *Op.Val->use_begin(); if (User->getOpcode() != ISD::STORE && (User->getOpcode() != ISD::BIT_CONVERT || User->getValueType(0) != MVT::i32)) - return SDOperand(); - SDOperand Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, + return SDValue(); + SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Op.getOperand(0)), Op.getOperand(1)); return DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Extract); } - return SDOperand(); + return SDValue(); } -SDOperand -X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) { +SDValue +X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { if (!isa<ConstantSDNode>(Op.getOperand(1))) - return SDOperand(); + return SDValue(); if (Subtarget->hasSSE41()) { - SDOperand Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG); + SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG); if (Res.Val) return Res; } @@ -4067,7 +4067,7 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) { MVT VT = Op.getValueType(); // TODO: handle v16i8. if (VT.getSizeInBits() == 16) { - SDOperand Vec = Op.getOperand(0); + SDValue Vec = Op.getOperand(0); unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); if (Idx == 0) return DAG.getNode(ISD::TRUNCATE, MVT::i16, @@ -4076,9 +4076,9 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) { Op.getOperand(1))); // Transform it so it match pextrw which produces a 32-bit result. MVT EVT = (MVT::SimpleValueType)(VT.getSimpleVT()+1); - SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, EVT, + SDValue Extract = DAG.getNode(X86ISD::PEXTRW, EVT, Op.getOperand(0), Op.getOperand(1)); - SDOperand Assert = DAG.getNode(ISD::AssertZext, EVT, Extract, + SDValue Assert = DAG.getNode(ISD::AssertZext, EVT, Extract, DAG.getValueType(VT)); return DAG.getNode(ISD::TRUNCATE, VT, Assert); } else if (VT.getSizeInBits() == 32) { @@ -4087,7 +4087,7 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) { return Op; // SHUFPS the element to the lowest double word, then movss. MVT MaskVT = MVT::getIntVectorWithNumElements(4); - SmallVector<SDOperand, 8> IdxVec; + SmallVector<SDValue, 8> IdxVec; IdxVec. push_back(DAG.getConstant(Idx, MaskVT.getVectorElementType())); IdxVec. @@ -4096,9 +4096,9 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) { push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType())); IdxVec. push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType())); - SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, + SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &IdxVec[0], IdxVec.size()); - SDOperand Vec = Op.getOperand(0); + SDValue Vec = Op.getOperand(0); Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(), Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask); return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec, @@ -4115,30 +4115,30 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) { // Note if the lower 64 bits of the result of the UNPCKHPD is then stored // to a f64mem, the whole operation is folded into a single MOVHPDmr. MVT MaskVT = MVT::getIntVectorWithNumElements(2); - SmallVector<SDOperand, 8> IdxVec; + SmallVector<SDValue, 8> IdxVec; IdxVec.push_back(DAG.getConstant(1, MaskVT.getVectorElementType())); IdxVec. push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType())); - SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, + SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &IdxVec[0], IdxVec.size()); - SDOperand Vec = Op.getOperand(0); + SDValue Vec = Op.getOperand(0); Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(), Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask); return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec, DAG.getIntPtrConstant(0)); } - return SDOperand(); + return SDValue(); } -SDOperand -X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDOperand Op, SelectionDAG &DAG){ +SDValue +X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){ MVT VT = Op.getValueType(); MVT EVT = VT.getVectorElementType(); - SDOperand N0 = Op.getOperand(0); - SDOperand N1 = Op.getOperand(1); - SDOperand N2 = Op.getOperand(2); + SDValue N0 = Op.getOperand(0); + SDValue N1 = Op.getOperand(1); + SDValue N2 = Op.getOperand(2); if ((EVT.getSizeInBits() == 8) || (EVT.getSizeInBits() == 16)) { unsigned Opc = (EVT.getSizeInBits() == 8) ? X86ISD::PINSRB @@ -4162,11 +4162,11 @@ X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDOperand Op, SelectionDAG &DAG){ N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getValue() << 4); return DAG.getNode(X86ISD::INSERTPS, VT, N0, N1, N2); } - return SDOperand(); + return SDValue(); } -SDOperand -X86TargetLowering::LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) { +SDValue +X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { MVT VT = Op.getValueType(); MVT EVT = VT.getVectorElementType(); @@ -4174,11 +4174,11 @@ X86TargetLowering::LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) { return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); if (EVT == MVT::i8) - return SDOperand(); + return SDValue(); - SDOperand N0 = Op.getOperand(0); - SDOperand N1 = Op.getOperand(1); - SDOperand N2 = Op.getOperand(2); + SDValue N0 = Op.getOperand(0); + SDValue N1 = Op.getOperand(1); + SDValue N2 = Op.getOperand(2); if (EVT.getSizeInBits() == 16) { // Transform it so it match pinsrw which expects a 16-bit value in a GR32 @@ -4189,18 +4189,18 @@ X86TargetLowering::LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) { N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getValue()); return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2); } - return SDOperand(); + return SDValue(); } -SDOperand -X86TargetLowering::LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) { +SDValue +X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) { if (Op.getValueType() == MVT::v2f32) return DAG.getNode(ISD::BIT_CONVERT, MVT::v2f32, DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2i32, DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op.getOperand(0)))); - SDOperand AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0)); + SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0)); MVT VT = MVT::v2i32; switch (Op.getValueType().getSimpleVT()) { default: break; @@ -4219,10 +4219,10 @@ X86TargetLowering::LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) { // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only // be used to form addressing mode. These wrapped nodes will be selected // into MOV32ri. -SDOperand -X86TargetLowering::LowerConstantPool(SDOperand Op, SelectionDAG &DAG) { +SDValue +X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) { ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); - SDOperand Result = DAG.getTargetConstantPool(CP->getConstVal(), + SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(), CP->getAlignment()); Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result); @@ -4237,10 +4237,10 @@ X86TargetLowering::LowerConstantPool(SDOperand Op, SelectionDAG &DAG) { return Result; } -SDOperand -X86TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) { +SDValue +X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) { GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); - SDOperand Result = DAG.getTargetGlobalAddress(GV, getPointerTy()); + SDValue Result = DAG.getTargetGlobalAddress(GV, getPointerTy()); Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result); // With PIC, the address is actually $g + Offset. if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && @@ -4263,22 +4263,22 @@ X86TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) { } // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit -static SDOperand +static SDValue LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, const MVT PtrVT) { - SDOperand InFlag; - SDOperand Chain = DAG.getCopyToReg(DAG.getEntryNode(), X86::EBX, + SDValue InFlag; + SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), X86::EBX, DAG.getNode(X86ISD::GlobalBaseReg, PtrVT), InFlag); InFlag = Chain.getValue(1); // emit leal symbol@TLSGD(,%ebx,1), %eax SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag); - SDOperand TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), + SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0), GA->getOffset()); - SDOperand Ops[] = { Chain, TGA, InFlag }; - SDOperand Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 3); + SDValue Ops[] = { Chain, TGA, InFlag }; + SDValue Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 3); InFlag = Result.getValue(2); Chain = Result.getValue(1); @@ -4288,7 +4288,7 @@ LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, InFlag = Chain.getValue(1); NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); - SDOperand Ops1[] = { Chain, + SDValue Ops1[] = { Chain, DAG.getTargetExternalSymbol("___tls_get_addr", PtrVT), DAG.getRegister(X86::EAX, PtrVT), @@ -4301,18 +4301,18 @@ LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, } // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit -static SDOperand +static SDValue LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, const MVT PtrVT) { - SDOperand InFlag, Chain; + SDValue InFlag, Chain; // emit leaq symbol@TLSGD(%rip), %rdi SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag); - SDOperand TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), + SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0), GA->getOffset()); - SDOperand Ops[] = { DAG.getEntryNode(), TGA}; - SDOperand Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 2); + SDValue Ops[] = { DAG.getEntryNode(), TGA}; + SDValue Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 2); Chain = Result.getValue(1); InFlag = Result.getValue(2); @@ -4322,7 +4322,7 @@ LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, InFlag = Chain.getValue(1); NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); - SDOperand Ops1[] = { Chain, + SDValue Ops1[] = { Chain, DAG.getTargetExternalSymbol("___tls_get_addr", PtrVT), DAG.getRegister(X86::RDI, PtrVT), @@ -4335,16 +4335,16 @@ LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or // "local exec" model. -static SDOperand LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, +static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, const MVT PtrVT) { // Get the Thread Pointer - SDOperand ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER, PtrVT); + SDValue ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER, PtrVT); // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial // exec) - SDOperand TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), + SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0), GA->getOffset()); - SDOperand Offset = DAG.getNode(X86ISD::Wrapper, PtrVT, TGA); + SDValue Offset = DAG.getNode(X86ISD::Wrapper, PtrVT, TGA); if (GA->getGlobal()->isDeclaration()) // initial exec TLS model Offset = DAG.getLoad(PtrVT, DAG.getEntryNode(), Offset, @@ -4355,8 +4355,8 @@ static SDOperand LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset); } -SDOperand -X86TargetLowering::LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) { +SDValue +X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) { // TODO: implement the "local dynamic" model // TODO: implement the "initial exec"model for pic executables assert(Subtarget->isTargetELF() && @@ -4374,10 +4374,10 @@ X86TargetLowering::LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) { } } -SDOperand -X86TargetLowering::LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG) { +SDValue +X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) { const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); - SDOperand Result = DAG.getTargetExternalSymbol(Sym, getPointerTy()); + SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy()); Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result); // With PIC, the address is actually $g + Offset. if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && @@ -4390,9 +4390,9 @@ X86TargetLowering::LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG) { return Result; } -SDOperand X86TargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) { +SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) { JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); - SDOperand Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy()); + SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy()); Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result); // With PIC, the address is actually $g + Offset. if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && @@ -4407,19 +4407,19 @@ SDOperand X86TargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) { /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and /// take a 2 x i32 value to shift plus a shift amount. -SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) { +SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) { assert(Op.getNumOperands() == 3 && "Not a double-shift!"); MVT VT = Op.getValueType(); unsigned VTBits = VT.getSizeInBits(); bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; - SDOperand ShOpLo = Op.getOperand(0); - SDOperand ShOpHi = Op.getOperand(1); - SDOperand ShAmt = Op.getOperand(2); - SDOperand Tmp1 = isSRA ? + SDValue ShOpLo = Op.getOperand(0); + SDValue ShOpHi = Op.getOperand(1); + SDValue ShAmt = Op.getOperand(2); + SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, VT, ShOpHi, DAG.getConstant(VTBits - 1, MVT::i8)) : DAG.getConstant(0, VT); - SDOperand Tmp2, Tmp3; + SDValue Tmp2, Tmp3; if (Op.getOpcode() == ISD::SHL_PARTS) { Tmp2 = DAG.getNode(X86ISD::SHLD, VT, ShOpHi, ShOpLo, ShAmt); Tmp3 = DAG.getNode(ISD::SHL, VT, ShOpLo, ShAmt); @@ -4428,15 +4428,15 @@ SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) { Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, VT, ShOpHi, ShAmt); } - SDOperand AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt, + SDValue AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt, DAG.getConstant(VTBits, MVT::i8)); - SDOperand Cond = DAG.getNode(X86ISD::CMP, VT, + SDValue Cond = DAG.getNode(X86ISD::CMP, VT, AndNode, DAG.getConstant(0, MVT::i8)); - SDOperand Hi, Lo; - SDOperand CC = DAG.getConstant(X86::COND_NE, MVT::i8); - SDOperand Ops0[4] = { Tmp2, Tmp3, CC, Cond }; - SDOperand Ops1[4] = { Tmp3, Tmp1, CC, Cond }; + SDValue Hi, Lo; + SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8); + SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond }; + SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; if (Op.getOpcode() == ISD::SHL_PARTS) { Hi = DAG.getNode(X86ISD::CMOV, VT, Ops0, 4); @@ -4446,27 +4446,27 @@ SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) { Hi = DAG.getNode(X86ISD::CMOV, VT, Ops1, 4); } - SDOperand Ops[2] = { Lo, Hi }; + SDValue Ops[2] = { Lo, Hi }; return DAG.getMergeValues(Ops, 2); } -SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { +SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) { MVT SrcVT = Op.getOperand(0).getValueType(); assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 && "Unknown SINT_TO_FP to lower!"); // These are really Legal; caller falls through into that case. if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) - return SDOperand(); + return SDValue(); if (SrcVT == MVT::i64 && Op.getValueType() != MVT::f80 && Subtarget->is64Bit()) - return SDOperand(); + return SDValue(); unsigned Size = SrcVT.getSizeInBits()/8; MachineFunction &MF = DAG.getMachineFunction(); int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size); - SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); - SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0), + SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); + SDValue Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0), StackSlot, PseudoSourceValue::getFixedStack(SSFI), 0); @@ -4477,25 +4477,25 @@ SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag); else Tys = DAG.getVTList(Op.getValueType(), MVT::Other); - SmallVector<SDOperand, 8> Ops; + SmallVector<SDValue, 8> Ops; Ops.push_back(Chain); Ops.push_back(StackSlot); Ops.push_back(DAG.getValueType(SrcVT)); - SDOperand Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, + SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, Tys, &Ops[0], Ops.size()); if (useSSE) { Chain = Result.getValue(1); - SDOperand InFlag = Result.getValue(2); + SDValue InFlag = Result.getValue(2); // FIXME: Currently the FST is flagged to the FILD_FLAG. This // shouldn't be necessary except that RFP cannot be live across // multiple blocks. When stackifier is fixed, they can be uncoupled. MachineFunction &MF = DAG.getMachineFunction(); int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); - SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); + SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); Tys = DAG.getVTList(MVT::Other); - SmallVector<SDOperand, 8> Ops; + SmallVector<SDValue, 8> Ops; Ops.push_back(Chain); Ops.push_back(Result); Ops.push_back(StackSlot); @@ -4509,8 +4509,8 @@ SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { return Result; } -std::pair<SDOperand,SDOperand> X86TargetLowering:: -FP_TO_SINTHelper(SDOperand Op, SelectionDAG &DAG) { +std::pair<SDValue,SDValue> X86TargetLowering:: +FP_TO_SINTHelper(SDValue Op, SelectionDAG &DAG) { assert(Op.getValueType().getSimpleVT() <= MVT::i64 && Op.getValueType().getSimpleVT() >= MVT::i16 && "Unknown FP_TO_SINT to lower!"); @@ -4518,18 +4518,18 @@ FP_TO_SINTHelper(SDOperand Op, SelectionDAG &DAG) { // These are really Legal. if (Op.getValueType() == MVT::i32 && isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) - return std::make_pair(SDOperand(), SDOperand()); + return std::make_pair(SDValue(), SDValue()); if (Subtarget->is64Bit() && Op.getValueType() == MVT::i64 && Op.getOperand(0).getValueType() != MVT::f80) - return std::make_pair(SDOperand(), SDOperand()); + return std::make_pair(SDValue(), SDValue()); // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary // stack slot. MachineFunction &MF = DAG.getMachineFunction(); unsigned MemSize = Op.getValueType().getSizeInBits()/8; int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize); - SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); + SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); unsigned Opc; switch (Op.getValueType().getSimpleVT()) { default: assert(0 && "Invalid FP_TO_SINT to lower!"); @@ -4538,14 +4538,14 @@ FP_TO_SINTHelper(SDOperand Op, SelectionDAG &DAG) { case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; } - SDOperand Chain = DAG.getEntryNode(); - SDOperand Value = Op.getOperand(0); + SDValue Chain = DAG.getEntryNode(); + SDValue Value = Op.getOperand(0); if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) { assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!"); Chain = DAG.getStore(Chain, Value, StackSlot, PseudoSourceValue::getFixedStack(SSFI), 0); SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); - SDOperand Ops[] = { + SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType()) }; Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3); @@ -4555,30 +4555,30 @@ FP_TO_SINTHelper(SDOperand Op, SelectionDAG &DAG) { } // Build the FP_TO_INT*_IN_MEM - SDOperand Ops[] = { Chain, Value, StackSlot }; - SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops, 3); + SDValue Ops[] = { Chain, Value, StackSlot }; + SDValue FIST = DAG.getNode(Opc, MVT::Other, Ops, 3); return std::make_pair(FIST, StackSlot); } -SDOperand X86TargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) { - std::pair<SDOperand,SDOperand> Vals = FP_TO_SINTHelper(Op, DAG); - SDOperand FIST = Vals.first, StackSlot = Vals.second; - if (FIST.Val == 0) return SDOperand(); +SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) { + std::pair<SDValue,SDValue> Vals = FP_TO_SINTHelper(Op, DAG); + SDValue FIST = Vals.first, StackSlot = Vals.second; + if (FIST.Val == 0) return SDValue(); // Load the result. return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0); } SDNode *X86TargetLowering::ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG) { - std::pair<SDOperand,SDOperand> Vals = FP_TO_SINTHelper(SDOperand(N, 0), DAG); - SDOperand FIST = Vals.first, StackSlot = Vals.second; + std::pair<SDValue,SDValue> Vals = FP_TO_SINTHelper(SDValue(N, 0), DAG); + SDValue FIST = Vals.first, StackSlot = Vals.second; if (FIST.Val == 0) return 0; MVT VT = N->getValueType(0); // Return a load from the stack slot. - SDOperand Res = DAG.getLoad(VT, FIST, StackSlot, NULL, 0); + SDValue Res = DAG.getLoad(VT, FIST, StackSlot, NULL, 0); // Use MERGE_VALUES to drop the chain result value and get a node with one // result. This requires turning off getMergeValues simplification, since @@ -4586,7 +4586,7 @@ SDNode *X86TargetLowering::ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG) { return DAG.getMergeValues(&Res, 1, false).Val; } -SDOperand X86TargetLowering::LowerFABS(SDOperand Op, SelectionDAG &DAG) { +SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) { MVT VT = Op.getValueType(); MVT EltVT = VT; if (VT.isVector()) @@ -4604,14 +4604,14 @@ SDOperand X86TargetLowering::LowerFABS(SDOperand Op, SelectionDAG &DAG) { CV.push_back(C); } Constant *C = ConstantVector::get(CV); - SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); - SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, + SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); + SDValue Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, PseudoSourceValue::getConstantPool(), 0, false, 16); return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask); } -SDOperand X86TargetLowering::LowerFNEG(SDOperand Op, SelectionDAG &DAG) { +SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) { MVT VT = Op.getValueType(); MVT EltVT = VT; unsigned EltNum = 1; @@ -4632,8 +4632,8 @@ SDOperand X86TargetLowering::LowerFNEG(SDOperand Op, SelectionDAG &DAG) { CV.push_back(C); } Constant *C = ConstantVector::get(CV); - SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); - SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, + SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); + SDValue Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, PseudoSourceValue::getConstantPool(), 0, false, 16); if (VT.isVector()) { @@ -4646,9 +4646,9 @@ SDOperand X86TargetLowering::LowerFNEG(SDOperand Op, SelectionDAG &DAG) { } } -SDOperand X86TargetLowering::LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) { - SDOperand Op0 = Op.getOperand(0); - SDOperand Op1 = Op.getOperand(1); +SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) { + SDValue Op0 = Op.getOperand(0); + SDValue Op1 = Op.getOperand(1); MVT VT = Op.getValueType(); MVT SrcVT = Op1.getValueType(); @@ -4678,11 +4678,11 @@ SDOperand X86TargetLowering::LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) { CV.push_back(ConstantFP::get(APFloat(APInt(32, 0)))); } Constant *C = ConstantVector::get(CV); - SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); - SDOperand Mask1 = DAG.getLoad(SrcVT, DAG.getEntryNode(), CPIdx, + SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); + SDValue Mask1 = DAG.getLoad(SrcVT, DAG.getEntryNode(), CPIdx, PseudoSourceValue::getConstantPool(), 0, false, 16); - SDOperand SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1); + SDValue SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1); // Shift sign bit right or left if the two operands have different types. if (SrcVT.bitsGT(VT)) { @@ -4708,21 +4708,21 @@ SDOperand X86TargetLowering::LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) { } C = ConstantVector::get(CV); CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); - SDOperand Mask2 = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, + SDValue Mask2 = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, PseudoSourceValue::getConstantPool(), 0, false, 16); - SDOperand Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2); + SDValue Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2); // Or the value with the sign bit. return DAG.getNode(X86ISD::FOR, VT, Val, SignBit); } -SDOperand X86TargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG) { +SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) { assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); - SDOperand Cond; - SDOperand Op0 = Op.getOperand(0); - SDOperand Op1 = Op.getOperand(1); - SDOperand CC = Op.getOperand(2); + SDValue Cond; + SDValue Op0 = Op.getOperand(0); + SDValue Op1 = Op.getOperand(1); + SDValue CC = Op.getOperand(2); ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); unsigned X86CC; @@ -4740,27 +4740,27 @@ SDOperand X86TargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG) { switch (SetCCOpcode) { default: assert(false && "Illegal floating point SetCC!"); case ISD::SETOEQ: { // !PF & ZF - SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, MVT::i8, + SDValue Tmp1 = DAG.getNode(X86ISD::SETCC, MVT::i8, DAG.getConstant(X86::COND_NP, MVT::i8), Cond); - SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8, + SDValue Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8, DAG.getConstant(X86::COND_E, MVT::i8), Cond); return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2); } case ISD::SETUNE: { // PF | !ZF - SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, MVT::i8, + SDValue Tmp1 = DAG.getNode(X86ISD::SETCC, MVT::i8, DAG.getConstant(X86::COND_P, MVT::i8), Cond); - SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8, + SDValue Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8, DAG.getConstant(X86::COND_NE, MVT::i8), Cond); return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2); } } } -SDOperand X86TargetLowering::LowerVSETCC(SDOperand Op, SelectionDAG &DAG) { - SDOperand Cond; - SDOperand Op0 = Op.getOperand(0); - SDOperand Op1 = Op.getOperand(1); - SDOperand CC = Op.getOperand(2); +SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) { + SDValue Cond; + SDValue Op0 = Op.getOperand(0); + SDValue Op1 = Op.getOperand(1); + SDValue CC = Op.getOperand(2); MVT VT = Op.getValueType(); ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); @@ -4798,13 +4798,13 @@ SDOperand X86TargetLowering::LowerVSETCC(SDOperand Op, SelectionDAG &DAG) { // In the two special cases we can't handle, emit two comparisons. if (SSECC == 8) { if (SetCCOpcode == ISD::SETUEQ) { - SDOperand UNORD, EQ; + SDValue UNORD, EQ; UNORD = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(3, MVT::i8)); EQ = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(0, MVT::i8)); return DAG.getNode(ISD::OR, VT, UNORD, EQ); } else if (SetCCOpcode == ISD::SETONE) { - SDOperand ORD, NEQ; + SDValue ORD, NEQ; ORD = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(7, MVT::i8)); NEQ = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(4, MVT::i8)); return DAG.getNode(ISD::AND, VT, ORD, NEQ); @@ -4849,32 +4849,32 @@ SDOperand X86TargetLowering::LowerVSETCC(SDOperand Op, SelectionDAG &DAG) { // bits of the inputs before performing those operations. if (FlipSigns) { MVT EltVT = VT.getVectorElementType(); - SDOperand SignBit = DAG.getConstant(EltVT.getIntegerVTSignBit(), EltVT); - std::vector<SDOperand> SignBits(VT.getVectorNumElements(), SignBit); - SDOperand SignVec = DAG.getNode(ISD::BUILD_VECTOR, VT, &SignBits[0], + SDValue SignBit = DAG.getConstant(EltVT.getIntegerVTSignBit(), EltVT); + std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit); + SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, VT, &SignBits[0], SignBits.size()); Op0 = DAG.getNode(ISD::XOR, VT, Op0, SignVec); Op1 = DAG.getNode(ISD::XOR, VT, Op1, SignVec); } - SDOperand Result = DAG.getNode(Opc, VT, Op0, Op1); + SDValue Result = DAG.getNode(Opc, VT, Op0, Op1); // If the logical-not of the result is required, perform that now. if (Invert) { MVT EltVT = VT.getVectorElementType(); - SDOperand NegOne = DAG.getConstant(EltVT.getIntegerVTBitMask(), EltVT); - std::vector<SDOperand> NegOnes(VT.getVectorNumElements(), NegOne); - SDOperand NegOneV = DAG.getNode(ISD::BUILD_VECTOR, VT, &NegOnes[0], + SDValue NegOne = DAG.getConstant(EltVT.getIntegerVTBitMask(), EltVT); + std::vector<SDValue> NegOnes(VT.getVectorNumElements(), NegOne); + SDValue NegOneV = DAG.getNode(ISD::BUILD_VECTOR, VT, &NegOnes[0], NegOnes.size()); Result = DAG.getNode(ISD::XOR, VT, Result, NegOneV); } return Result; } -SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) { +SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) { bool addTest = true; - SDOperand Cond = Op.getOperand(0); - SDOperand CC; + SDValue Cond = Op.getOperand(0); + SDValue CC; if (Cond.getOpcode() == ISD::SETCC) Cond = LowerSETCC(Cond, DAG); @@ -4884,7 +4884,7 @@ SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) { if (Cond.getOpcode() == X86ISD::SETCC) { CC = Cond.getOperand(0); - SDOperand Cmp = Cond.getOperand(1); + SDValue Cmp = Cond.getOperand(1); unsigned Opc = Cmp.getOpcode(); MVT VT = Op.getValueType(); @@ -4908,7 +4908,7 @@ SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) { const MVT *VTs = DAG.getNodeValueTypes(Op.getValueType(), MVT::Flag); - SmallVector<SDOperand, 4> Ops; + SmallVector<SDValue, 4> Ops; // X86ISD::CMOV means set the result (which is operand 1) to the RHS if // condition is true. Ops.push_back(Op.getOperand(2)); @@ -4918,12 +4918,12 @@ SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) { return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size()); } -SDOperand X86TargetLowering::LowerBRCOND(SDOperand Op, SelectionDAG &DAG) { +SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) { bool addTest = true; - SDOperand Chain = Op.getOperand(0); - SDOperand Cond = Op.getOperand(1); - SDOperand Dest = Op.getOperand(2); - SDOperand CC; + SDValue Chain = Op.getOperand(0); + SDValue Cond = Op.getOperand(1); + SDValue Dest = Op.getOperand(2); + SDValue CC; if (Cond.getOpcode() == ISD::SETCC) Cond = LowerSETCC(Cond, DAG); @@ -4933,7 +4933,7 @@ SDOperand X86TargetLowering::LowerBRCOND(SDOperand Op, SelectionDAG &DAG) { if (Cond.getOpcode() == X86ISD::SETCC) { CC = Cond.getOperand(0); - SDOperand Cmp = Cond.getOperand(1); + SDValue Cmp = Cond.getOperand(1); unsigned Opc = Cmp.getOpcode(); if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || @@ -4957,18 +4957,18 @@ SDOperand X86TargetLowering::LowerBRCOND(SDOperand Op, SelectionDAG &DAG) { // bytes in one go. Touching the stack at 4K increments is necessary to ensure // that the guard pages used by the OS virtual memory manager are allocated in // correct sequence. -SDOperand -X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDOperand Op, +SDValue +X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) { assert(Subtarget->isTargetCygMing() && "This should be used only on Cygwin/Mingw targets"); // Get the inputs. - SDOperand Chain = Op.getOperand(0); - SDOperand Size = Op.getOperand(1); + SDValue Chain = Op.getOperand(0); + SDValue Size = Op.getOperand(1); // FIXME: Ensure alignment here - SDOperand Flag; + SDValue Flag; MVT IntPtr = getPointerTy(); MVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32; @@ -4979,7 +4979,7 @@ X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDOperand Op, Flag = Chain.getValue(1); SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); - SDOperand Ops[] = { Chain, + SDValue Ops[] = { Chain, DAG.getTargetExternalSymbol("_alloca", IntPtr), DAG.getRegister(X86::EAX, IntPtr), DAG.getRegister(X86StackPtr, SPTy), @@ -4994,15 +4994,15 @@ X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDOperand Op, Chain = DAG.getCopyFromReg(Chain, X86StackPtr, SPTy).getValue(1); - SDOperand Ops1[2] = { Chain.getValue(0), Chain }; + SDValue Ops1[2] = { Chain.getValue(0), Chain }; return DAG.getMergeValues(Ops1, 2); } -SDOperand +SDValue X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, - SDOperand Chain, - SDOperand Dst, SDOperand Src, - SDOperand Size, unsigned Align, + SDValue Chain, + SDValue Dst, SDValue Src, + SDValue Size, unsigned Align, const Value *DstSV, uint64_t DstSVOff) { ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); @@ -5012,7 +5012,7 @@ X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, if ((Align & 3) == 0 || !ConstantSize || ConstantSize->getValue() > getSubtarget()->getMaxInlineSizeThreshold()) { - SDOperand InFlag(0, 0); + SDValue InFlag(0, 0); // Check to see if there is a specialized entry-point for memory zeroing. ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src); @@ -5027,7 +5027,7 @@ X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, Args.push_back(Entry); Entry.Node = Size; Args.push_back(Entry); - std::pair<SDOperand,SDOperand> CallResult = + std::pair<SDValue,SDValue> CallResult = LowerCallTo(Chain, Type::VoidTy, false, false, false, CallingConv::C, false, DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG); @@ -5035,13 +5035,13 @@ X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, } // Otherwise have the target-independent code call memset. - return SDOperand(); + return SDValue(); } uint64_t SizeVal = ConstantSize->getValue(); - SDOperand InFlag(0, 0); + SDValue InFlag(0, 0); MVT AVT; - SDOperand Count; + SDValue Count; ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src); unsigned BytesLeft = 0; bool TwoRepStos = false; @@ -5098,7 +5098,7 @@ X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, InFlag = Chain.getValue(1); SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); - SmallVector<SDOperand, 8> Ops; + SmallVector<SDValue, 8> Ops; Ops.push_back(Chain); Ops.push_back(DAG.getValueType(AVT)); Ops.push_back(InFlag); @@ -5108,7 +5108,7 @@ X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, InFlag = Chain.getValue(1); Count = Size; MVT CVT = Count.getValueType(); - SDOperand Left = DAG.getNode(ISD::AND, CVT, Count, + SDValue Left = DAG.getNode(ISD::AND, CVT, Count, DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT)); Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX, Left, InFlag); @@ -5137,11 +5137,11 @@ X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, return Chain; } -SDOperand +SDValue X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, - SDOperand Chain, - SDOperand Dst, SDOperand Src, - SDOperand Size, unsigned Align, + SDValue Chain, + SDValue Dst, SDValue Src, + SDValue Size, unsigned Align, bool AlwaysInline, const Value *DstSV, uint64_t DstSVOff, const Value *SrcSV, uint64_t SrcSVOff){ @@ -5150,10 +5150,10 @@ X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, // within a subtarget-specific limit. ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); if (!ConstantSize) - return SDOperand(); + return SDValue(); uint64_t SizeVal = ConstantSize->getValue(); if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold()) - return SDOperand(); + return SDValue(); MVT AVT; unsigned BytesLeft = 0; @@ -5168,10 +5168,10 @@ X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, unsigned UBytes = AVT.getSizeInBits() / 8; unsigned CountVal = SizeVal / UBytes; - SDOperand Count = DAG.getIntPtrConstant(CountVal); + SDValue Count = DAG.getIntPtrConstant(CountVal); BytesLeft = SizeVal % UBytes; - SDOperand InFlag(0, 0); + SDValue InFlag(0, 0); Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX, Count, InFlag); InFlag = Chain.getValue(1); @@ -5183,13 +5183,13 @@ X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, InFlag = Chain.getValue(1); SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); - SmallVector<SDOperand, 8> Ops; + SmallVector<SDValue, 8> Ops; Ops.push_back(Chain); Ops.push_back(DAG.getValueType(AVT)); Ops.push_back(InFlag); - SDOperand RepMovs = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size()); + SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size()); - SmallVector<SDOperand, 4> Results; + SmallVector<SDValue, 4> Results; Results.push_back(RepMovs); if (BytesLeft) { // Handle the last 1 - 7 bytes. @@ -5214,26 +5214,26 @@ X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, /// Expand the result of: i64,outchain = READCYCLECOUNTER inchain SDNode *X86TargetLowering::ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG){ SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); - SDOperand TheChain = N->getOperand(0); - SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheChain, 1); + SDValue TheChain = N->getOperand(0); + SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheChain, 1); if (Subtarget->is64Bit()) { - SDOperand rax = DAG.getCopyFromReg(rd, X86::RAX, MVT::i64, rd.getValue(1)); - SDOperand rdx = DAG.getCopyFromReg(rax.getValue(1), X86::RDX, + SDValue rax = DAG.getCopyFromReg(rd, X86::RAX, MVT::i64, rd.getValue(1)); + SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), X86::RDX, MVT::i64, rax.getValue(2)); - SDOperand Tmp = DAG.getNode(ISD::SHL, MVT::i64, rdx, + SDValue Tmp = DAG.getNode(ISD::SHL, MVT::i64, rdx, DAG.getConstant(32, MVT::i8)); - SDOperand Ops[] = { + SDValue Ops[] = { DAG.getNode(ISD::OR, MVT::i64, rax, Tmp), rdx.getValue(1) }; return DAG.getMergeValues(Ops, 2).Val; } - SDOperand eax = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1)); - SDOperand edx = DAG.getCopyFromReg(eax.getValue(1), X86::EDX, + SDValue eax = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1)); + SDValue edx = DAG.getCopyFromReg(eax.getValue(1), X86::EDX, MVT::i32, eax.getValue(2)); // Use a buildpair to merge the two 32-bit values into a 64-bit one. - SDOperand Ops[] = { eax, edx }; + SDValue Ops[] = { eax, edx }; Ops[0] = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Ops, 2); // Use a MERGE_VALUES to return the value and chain. @@ -5241,13 +5241,13 @@ SDNode *X86TargetLowering::ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG){ return DAG.getMergeValues(Ops, 2).Val; } -SDOperand X86TargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG) { +SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) { const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); if (!Subtarget->is64Bit()) { // vastart just stores the address of the VarArgsFrameIndex slot into the // memory location argument. - SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); + SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV, 0); } @@ -5256,10 +5256,10 @@ SDOperand X86TargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG) { // fp_offset (48 - 48 + 8 * 16) // overflow_arg_area (point to parameters coming in memory). // reg_save_area - SmallVector<SDOperand, 8> MemOps; - SDOperand FIN = Op.getOperand(1); + SmallVector<SDValue, 8> MemOps; + SDValue FIN = Op.getOperand(1); // Store gp_offset - SDOperand Store = DAG.getStore(Op.getOperand(0), + SDValue Store = DAG.getStore(Op.getOperand(0), DAG.getConstant(VarArgsGPOffset, MVT::i32), FIN, SV, 0); MemOps.push_back(Store); @@ -5273,36 +5273,36 @@ SDOperand X86TargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG) { // Store ptr to overflow_arg_area FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4)); - SDOperand OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); + SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV, 0); MemOps.push_back(Store); // Store ptr to reg_save_area. FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(8)); - SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy()); + SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy()); Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV, 0); MemOps.push_back(Store); return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size()); } -SDOperand X86TargetLowering::LowerVAARG(SDOperand Op, SelectionDAG &DAG) { +SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) { // X86-64 va_list is a struct { i32, i32, i8*, i8* }. assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!"); - SDOperand Chain = Op.getOperand(0); - SDOperand SrcPtr = Op.getOperand(1); - SDOperand SrcSV = Op.getOperand(2); + SDValue Chain = Op.getOperand(0); + SDValue SrcPtr = Op.getOperand(1); + SDValue SrcSV = Op.getOperand(2); assert(0 && "VAArgInst is not yet implemented for x86-64!"); abort(); - return SDOperand(); + return SDValue(); } -SDOperand X86TargetLowering::LowerVACOPY(SDOperand Op, SelectionDAG &DAG) { +SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) { // X86-64 va_list is a struct { i32, i32, i8*, i8* }. assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!"); - SDOperand Chain = Op.getOperand(0); - SDOperand DstPtr = Op.getOperand(1); - SDOperand SrcPtr = Op.getOperand(2); + SDValue Chain = Op.getOperand(0); + SDValue DstPtr = Op.getOperand(1); + SDValue SrcPtr = Op.getOperand(2); const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); @@ -5311,11 +5311,11 @@ SDOperand X86TargetLowering::LowerVACOPY(SDOperand Op, SelectionDAG &DAG) { DstSV, 0, SrcSV, 0); } -SDOperand -X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) { +SDValue +X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) { unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue(); switch (IntNo) { - default: return SDOperand(); // Don't custom lower most intrinsics. + default: return SDValue(); // Don't custom lower most intrinsics. // Comparison intrinsics. case Intrinsic::x86_sse_comieq_ss: case Intrinsic::x86_sse_comilt_ss: @@ -5408,12 +5408,12 @@ X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) { } unsigned X86CC; - SDOperand LHS = Op.getOperand(1); - SDOperand RHS = Op.getOperand(2); + SDValue LHS = Op.getOperand(1); + SDValue RHS = Op.getOperand(2); translateX86CC(CC, true, X86CC, LHS, RHS, DAG); - SDOperand Cond = DAG.getNode(Opc, MVT::i32, LHS, RHS); - SDOperand SetCC = DAG.getNode(X86ISD::SETCC, MVT::i8, + SDValue Cond = DAG.getNode(Opc, MVT::i32, LHS, RHS); + SDValue SetCC = DAG.getNode(X86ISD::SETCC, MVT::i8, DAG.getConstant(X86CC, MVT::i8), Cond); return DAG.getNode(ISD::ANY_EXTEND, MVT::i32, SetCC); } @@ -5436,9 +5436,9 @@ X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) { case Intrinsic::x86_mmx_psrli_q: case Intrinsic::x86_mmx_psrai_w: case Intrinsic::x86_mmx_psrai_d: { - SDOperand ShAmt = Op.getOperand(2); + SDValue ShAmt = Op.getOperand(2); if (isa<ConstantSDNode>(ShAmt)) - return SDOperand(); + return SDValue(); unsigned NewIntNo = 0; MVT ShAmtVT = MVT::v4i32; @@ -5509,49 +5509,49 @@ X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) { } } -SDOperand X86TargetLowering::LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) { +SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) { // Depths > 0 not supported yet! if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0) - return SDOperand(); + return SDValue(); // Just load the return address - SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG); + SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0); } -SDOperand X86TargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) { +SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { // Depths > 0 not supported yet! if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0) - return SDOperand(); + return SDValue(); - SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG); + SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); return DAG.getNode(ISD::SUB, getPointerTy(), RetAddrFI, DAG.getIntPtrConstant(!Subtarget->is64Bit() ? 4 : 8)); } -SDOperand X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDOperand Op, +SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) { // Is not yet supported on x86-64 if (Subtarget->is64Bit()) - return SDOperand(); + return SDValue(); return DAG.getIntPtrConstant(8); } -SDOperand X86TargetLowering::LowerEH_RETURN(SDOperand Op, SelectionDAG &DAG) +SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) { assert(!Subtarget->is64Bit() && "Lowering of eh_return builtin is not supported yet on x86-64"); MachineFunction &MF = DAG.getMachineFunction(); - SDOperand Chain = Op.getOperand(0); - SDOperand Offset = Op.getOperand(1); - SDOperand Handler = Op.getOperand(2); + SDValue Chain = Op.getOperand(0); + SDValue Offset = Op.getOperand(1); + SDValue Handler = Op.getOperand(2); - SDOperand Frame = DAG.getRegister(RegInfo->getFrameRegister(MF), + SDValue Frame = DAG.getRegister(RegInfo->getFrameRegister(MF), getPointerTy()); - SDOperand StoreAddr = DAG.getNode(ISD::SUB, getPointerTy(), Frame, + SDValue StoreAddr = DAG.getNode(ISD::SUB, getPointerTy(), Frame, DAG.getIntPtrConstant(-4UL)); StoreAddr = DAG.getNode(ISD::ADD, getPointerTy(), StoreAddr, Offset); Chain = DAG.getStore(Chain, Handler, StoreAddr, NULL, 0); @@ -5562,12 +5562,12 @@ SDOperand X86TargetLowering::LowerEH_RETURN(SDOperand Op, SelectionDAG &DAG) Chain, DAG.getRegister(X86::ECX, getPointerTy())); } -SDOperand X86TargetLowering::LowerTRAMPOLINE(SDOperand Op, +SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) { - SDOperand Root = Op.getOperand(0); - SDOperand Trmp = Op.getOperand(1); // trampoline - SDOperand FPtr = Op.getOperand(2); // nested function - SDOperand Nest = Op.getOperand(3); // 'nest' parameter value + SDValue Root = Op.getOperand(0); + SDValue Trmp = Op.getOperand(1); // trampoline + SDValue FPtr = Op.getOperand(2); // nested function + SDValue Nest = Op.getOperand(3); // 'nest' parameter value const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); @@ -5575,7 +5575,7 @@ SDOperand X86TargetLowering::LowerTRAMPOLINE(SDOperand Op, ((X86TargetMachine&)getTargetMachine()).getInstrInfo(); if (Subtarget->is64Bit()) { - SDOperand OutChains[6]; + SDValue OutChains[6]; // Large code-model. @@ -5589,7 +5589,7 @@ SDOperand X86TargetLowering::LowerTRAMPOLINE(SDOperand Op, // Load the pointer to the nested function into R11. unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 - SDOperand Addr = Trmp; + SDValue Addr = Trmp; OutChains[0] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr, TrmpAddr, 0); @@ -5617,7 +5617,7 @@ SDOperand X86TargetLowering::LowerTRAMPOLINE(SDOperand Op, OutChains[5] = DAG.getStore(Root, DAG.getConstant(ModRM, MVT::i8), Addr, TrmpAddr, 22); - SDOperand Ops[] = + SDValue Ops[] = { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 6) }; return DAG.getMergeValues(Ops, 2); } else { @@ -5663,8 +5663,8 @@ SDOperand X86TargetLowering::LowerTRAMPOLINE(SDOperand Op, break; } - SDOperand OutChains[4]; - SDOperand Addr, Disp; + SDValue OutChains[4]; + SDValue Addr, Disp; Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(10, MVT::i32)); Disp = DAG.getNode(ISD::SUB, MVT::i32, FPtr, Addr); @@ -5685,13 +5685,13 @@ SDOperand X86TargetLowering::LowerTRAMPOLINE(SDOperand Op, Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(6, MVT::i32)); OutChains[3] = DAG.getStore(Root, Disp, Addr, TrmpAddr, 6, false, 1); - SDOperand Ops[] = + SDValue Ops[] = { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 4) }; return DAG.getMergeValues(Ops, 2); } } -SDOperand X86TargetLowering::LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG) { +SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) { /* The rounding mode is in bits 11:10 of FPSR, and has the following settings: @@ -5719,27 +5719,27 @@ SDOperand X86TargetLowering::LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG) { // Save FP Control Word to stack slot int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment); - SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); + SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); - SDOperand Chain = DAG.getNode(X86ISD::FNSTCW16m, MVT::Other, + SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, MVT::Other, DAG.getEntryNode(), StackSlot); // Load FP Control Word from stack slot - SDOperand CWD = DAG.getLoad(MVT::i16, Chain, StackSlot, NULL, 0); + SDValue CWD = DAG.getLoad(MVT::i16, Chain, StackSlot, NULL, 0); // Transform as necessary - SDOperand CWD1 = + SDValue CWD1 = DAG.getNode(ISD::SRL, MVT::i16, DAG.getNode(ISD::AND, MVT::i16, CWD, DAG.getConstant(0x800, MVT::i16)), DAG.getConstant(11, MVT::i8)); - SDOperand CWD2 = + SDValue CWD2 = DAG.getNode(ISD::SRL, MVT::i16, DAG.getNode(ISD::AND, MVT::i16, CWD, DAG.getConstant(0x400, MVT::i16)), DAG.getConstant(9, MVT::i8)); - SDOperand RetVal = + SDValue RetVal = DAG.getNode(ISD::AND, MVT::i16, DAG.getNode(ISD::ADD, MVT::i16, DAG.getNode(ISD::OR, MVT::i16, CWD1, CWD2), @@ -5751,7 +5751,7 @@ SDOperand X86TargetLowering::LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG) { ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal); } -SDOperand X86TargetLowering::LowerCTLZ(SDOperand Op, SelectionDAG &DAG) { +SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) { MVT VT = Op.getValueType(); MVT OpVT = VT; unsigned NumBits = VT.getSizeInBits(); @@ -5768,7 +5768,7 @@ SDOperand X86TargetLowering::LowerCTLZ(SDOperand Op, SelectionDAG &DAG) { Op = DAG.getNode(X86ISD::BSR, VTs, Op); // If src is zero (i.e. bsr sets ZF), returns NumBits. - SmallVector<SDOperand, 4> Ops; + SmallVector<SDValue, 4> Ops; Ops.push_back(Op); Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT)); Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8)); @@ -5783,7 +5783,7 @@ SDOperand X86TargetLowering::LowerCTLZ(SDOperand Op, SelectionDAG &DAG) { return Op; } -SDOperand X86TargetLowering::LowerCTTZ(SDOperand Op, SelectionDAG &DAG) { +SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) { MVT VT = Op.getValueType(); MVT OpVT = VT; unsigned NumBits = VT.getSizeInBits(); @@ -5799,7 +5799,7 @@ SDOperand X86TargetLowering::LowerCTTZ(SDOperand Op, SelectionDAG &DAG) { Op = DAG.getNode(X86ISD::BSF, VTs, Op); // If src is zero (i.e. bsf sets ZF), returns NumBits. - SmallVector<SDOperand, 4> Ops; + SmallVector<SDValue, 4> Ops; Ops.push_back(Op); Ops.push_back(DAG.getConstant(NumBits, OpVT)); Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8)); @@ -5811,7 +5811,7 @@ SDOperand X86TargetLowering::LowerCTTZ(SDOperand Op, SelectionDAG &DAG) { return Op; } -SDOperand X86TargetLowering::LowerCMP_SWAP(SDOperand Op, SelectionDAG &DAG) { +SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) { MVT T = Op.getValueType(); unsigned Reg = 0; unsigned size = 0; @@ -5825,19 +5825,19 @@ SDOperand X86TargetLowering::LowerCMP_SWAP(SDOperand Op, SelectionDAG &DAG) { if (Subtarget->is64Bit()) { Reg = X86::RAX; size = 8; } else //Should go away when LowerType stuff lands - return SDOperand(ExpandATOMIC_CMP_SWAP(Op.Val, DAG), 0); + return SDValue(ExpandATOMIC_CMP_SWAP(Op.Val, DAG), 0); break; }; - SDOperand cpIn = DAG.getCopyToReg(Op.getOperand(0), Reg, - Op.getOperand(3), SDOperand()); - SDOperand Ops[] = { cpIn.getValue(0), + SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), Reg, + Op.getOperand(3), SDValue()); + SDValue Ops[] = { cpIn.getValue(0), Op.getOperand(1), Op.getOperand(2), DAG.getTargetConstant(size, MVT::i8), cpIn.getValue(1) }; SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); - SDOperand Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, Tys, Ops, 5); - SDOperand cpOut = + SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, Tys, Ops, 5); + SDValue cpOut = DAG.getCopyFromReg(Result.getValue(0), Reg, T, Result.getValue(1)); return cpOut; } @@ -5845,16 +5845,16 @@ SDOperand X86TargetLowering::LowerCMP_SWAP(SDOperand Op, SelectionDAG &DAG) { SDNode* X86TargetLowering::ExpandATOMIC_CMP_SWAP(SDNode* Op, SelectionDAG &DAG) { MVT T = Op->getValueType(0); assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap"); - SDOperand cpInL, cpInH; + SDValue cpInL, cpInH; cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(3), DAG.getConstant(0, MVT::i32)); cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(3), DAG.getConstant(1, MVT::i32)); cpInL = DAG.getCopyToReg(Op->getOperand(0), X86::EAX, - cpInL, SDOperand()); + cpInL, SDValue()); cpInH = DAG.getCopyToReg(cpInL.getValue(0), X86::EDX, cpInH, cpInL.getValue(1)); - SDOperand swapInL, swapInH; + SDValue swapInL, swapInH; swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(2), DAG.getConstant(0, MVT::i32)); swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(2), @@ -5863,25 +5863,25 @@ SDNode* X86TargetLowering::ExpandATOMIC_CMP_SWAP(SDNode* Op, SelectionDAG &DAG) swapInL, cpInH.getValue(1)); swapInH = DAG.getCopyToReg(swapInL.getValue(0), X86::ECX, swapInH, swapInL.getValue(1)); - SDOperand Ops[] = { swapInH.getValue(0), + SDValue Ops[] = { swapInH.getValue(0), Op->getOperand(1), swapInH.getValue(1)}; SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); - SDOperand Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, Tys, Ops, 3); - SDOperand cpOutL = DAG.getCopyFromReg(Result.getValue(0), X86::EAX, MVT::i32, + SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, Tys, Ops, 3); + SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), X86::EAX, MVT::i32, Result.getValue(1)); - SDOperand cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), X86::EDX, MVT::i32, + SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), X86::EDX, MVT::i32, cpOutL.getValue(2)); - SDOperand OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; - SDOperand ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OpsF, 2); - SDOperand Vals[2] = { ResultVal, cpOutH.getValue(1) }; + SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; + SDValue ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OpsF, 2); + SDValue Vals[2] = { ResultVal, cpOutH.getValue(1) }; return DAG.getMergeValues(Vals, 2).Val; } SDNode* X86TargetLowering::ExpandATOMIC_LOAD_SUB(SDNode* Op, SelectionDAG &DAG) { MVT T = Op->getValueType(0); assert (T == MVT::i32 && "Only know how to expand i32 Atomic Load Sub"); - SDOperand negOp = DAG.getNode(ISD::SUB, T, + SDValue negOp = DAG.getNode(ISD::SUB, T, DAG.getConstant(0, T), Op->getOperand(2)); return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, Op->getOperand(0), Op->getOperand(1), negOp, @@ -5891,7 +5891,7 @@ SDNode* X86TargetLowering::ExpandATOMIC_LOAD_SUB(SDNode* Op, SelectionDAG &DAG) /// LowerOperation - Provide custom lowering hooks for some operations. /// -SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { +SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { switch (Op.getOpcode()) { default: assert(0 && "Should not custom lower this!"); case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); @@ -5937,7 +5937,7 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { // FIXME: REMOVE THIS WHEN LegalizeDAGTypes lands. case ISD::READCYCLECOUNTER: - return SDOperand(ExpandREADCYCLECOUNTER(Op.Val, DAG), 0); + return SDValue(ExpandREADCYCLECOUNTER(Op.Val, DAG), 0); } } @@ -6092,7 +6092,7 @@ bool X86TargetLowering::isTruncateFree(MVT VT1, MVT VT2) const { /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values /// are assumed to be legal. bool -X86TargetLowering::isShuffleMaskLegal(SDOperand Mask, MVT VT) const { +X86TargetLowering::isShuffleMaskLegal(SDValue Mask, MVT VT) const { // Only do shuffles on 128-bit vector types for now. if (VT.getSizeInBits() == 64) return false; return (Mask.Val->getNumOperands() <= 4 || @@ -6107,7 +6107,7 @@ X86TargetLowering::isShuffleMaskLegal(SDOperand Mask, MVT VT) const { } bool -X86TargetLowering::isVectorClearMaskLegal(const std::vector<SDOperand> &BVOps, +X86TargetLowering::isVectorClearMaskLegal(const std::vector<SDValue> &BVOps, MVT EVT, SelectionDAG &DAG) const { unsigned NumElts = BVOps.size(); // Only do shuffles on 128-bit vector types for now. @@ -6484,7 +6484,7 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, // X86 Optimization Hooks //===----------------------------------------------------------------------===// -void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, +void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, const APInt &Mask, APInt &KnownZero, APInt &KnownOne, @@ -6531,21 +6531,21 @@ static bool isBaseAlignmentOfN(unsigned N, SDNode *Base, return false; } -static bool EltsFromConsecutiveLoads(SDNode *N, SDOperand PermMask, +static bool EltsFromConsecutiveLoads(SDNode *N, SDValue PermMask, unsigned NumElems, MVT EVT, SDNode *&Base, SelectionDAG &DAG, MachineFrameInfo *MFI, const TargetLowering &TLI) { Base = NULL; for (unsigned i = 0; i < NumElems; ++i) { - SDOperand Idx = PermMask.getOperand(i); + SDValue Idx = PermMask.getOperand(i); if (Idx.getOpcode() == ISD::UNDEF) { if (!Base) return false; continue; } - SDOperand Elt = DAG.getShuffleScalarElt(N, i); + SDValue Elt = DAG.getShuffleScalarElt(N, i); if (!Elt.Val || (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.Val))) return false; @@ -6569,17 +6569,17 @@ static bool EltsFromConsecutiveLoads(SDNode *N, SDOperand PermMask, /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load /// if the load addresses are consecutive, non-overlapping, and in the right /// order. -static SDOperand PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, +static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, const TargetLowering &TLI) { MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); MVT VT = N->getValueType(0); MVT EVT = VT.getVectorElementType(); - SDOperand PermMask = N->getOperand(2); + SDValue PermMask = N->getOperand(2); unsigned NumElems = PermMask.getNumOperands(); SDNode *Base = NULL; if (!EltsFromConsecutiveLoads(N, PermMask, NumElems, EVT, Base, DAG, MFI, TLI)) - return SDOperand(); + return SDValue(); LoadSDNode *LD = cast<LoadSDNode>(Base); if (isBaseAlignmentOfN(16, Base->getOperand(1).Val, TLI)) @@ -6591,14 +6591,14 @@ static SDOperand PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, } /// PerformBuildVectorCombine - build_vector 0,(load i64 / f64) -> movq / movsd. -static SDOperand PerformBuildVectorCombine(SDNode *N, SelectionDAG &DAG, +static SDValue PerformBuildVectorCombine(SDNode *N, SelectionDAG &DAG, const X86Subtarget *Subtarget, const TargetLowering &TLI) { unsigned NumOps = N->getNumOperands(); // Ignore single operand BUILD_VECTOR. if (NumOps == 1) - return SDOperand(); + return SDValue(); MVT VT = N->getValueType(0); MVT EVT = VT.getVectorElementType(); @@ -6606,20 +6606,20 @@ static SDOperand PerformBuildVectorCombine(SDNode *N, SelectionDAG &DAG, // We are looking for load i64 and zero extend. We want to transform // it before legalizer has a chance to expand it. Also look for i64 // BUILD_PAIR bit casted to f64. - return SDOperand(); + return SDValue(); // This must be an insertion into a zero vector. - SDOperand HighElt = N->getOperand(1); + SDValue HighElt = N->getOperand(1); if (!isZeroNode(HighElt)) - return SDOperand(); + return SDValue(); // Value must be a load. SDNode *Base = N->getOperand(0).Val; if (!isa<LoadSDNode>(Base)) { if (Base->getOpcode() != ISD::BIT_CONVERT) - return SDOperand(); + return SDValue(); Base = Base->getOperand(0).Val; if (!isa<LoadSDNode>(Base)) - return SDOperand(); + return SDValue(); } // Transform it into VZEXT_LOAD addr. @@ -6627,23 +6627,23 @@ static SDOperand PerformBuildVectorCombine(SDNode *N, SelectionDAG &DAG, // Load must not be an extload. if (LD->getExtensionType() != ISD::NON_EXTLOAD) - return SDOperand(); + return SDValue(); return DAG.getNode(X86ISD::VZEXT_LOAD, VT, LD->getChain(), LD->getBasePtr()); } /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes. -static SDOperand PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, +static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, const X86Subtarget *Subtarget) { - SDOperand Cond = N->getOperand(0); + SDValue Cond = N->getOperand(0); // If we have SSE[12] support, try to form min/max nodes. if (Subtarget->hasSSE2() && (N->getValueType(0) == MVT::f32 || N->getValueType(0) == MVT::f64)) { if (Cond.getOpcode() == ISD::SETCC) { // Get the LHS/RHS of the select. - SDOperand LHS = N->getOperand(1); - SDOperand RHS = N->getOperand(2); + SDValue LHS = N->getOperand(1); + SDValue RHS = N->getOperand(2); ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); unsigned Opcode = 0; @@ -6701,11 +6701,11 @@ static SDOperand PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, } - return SDOperand(); + return SDValue(); } /// PerformSTORECombine - Do target-specific dag combines on STORE nodes. -static SDOperand PerformSTORECombine(SDNode *N, SelectionDAG &DAG, +static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, const X86Subtarget *Subtarget) { // Turn load->store of MMX types into GPR load/stores. This avoids clobbering // the FP state in cases where an emms may be missing. @@ -6720,7 +6720,7 @@ static SDOperand PerformSTORECombine(SDNode *N, SelectionDAG &DAG, SDNode* LdVal = St->getValue().Val; LoadSDNode *Ld = 0; int TokenFactorIndex = -1; - SmallVector<SDOperand, 8> Ops; + SmallVector<SDValue, 8> Ops; SDNode* ChainVal = St->getChain().Val; // Must be a store of a load. We currently handle two cases: the load // is a direct child, and it's under an intervening TokenFactor. It is @@ -6740,11 +6740,11 @@ static SDOperand PerformSTORECombine(SDNode *N, SelectionDAG &DAG, if (Ld) { // If we are a 64-bit capable x86, lower to a single movq load/store pair. if (Subtarget->is64Bit()) { - SDOperand NewLd = DAG.getLoad(MVT::i64, Ld->getChain(), + SDValue NewLd = DAG.getLoad(MVT::i64, Ld->getChain(), Ld->getBasePtr(), Ld->getSrcValue(), Ld->getSrcValueOffset(), Ld->isVolatile(), Ld->getAlignment()); - SDOperand NewChain = NewLd.getValue(1); + SDValue NewChain = NewLd.getValue(1); if (TokenFactorIndex != -1) { Ops.push_back(NewChain); NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], @@ -6756,19 +6756,19 @@ static SDOperand PerformSTORECombine(SDNode *N, SelectionDAG &DAG, } // Otherwise, lower to two 32-bit copies. - SDOperand LoAddr = Ld->getBasePtr(); - SDOperand HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr, + SDValue LoAddr = Ld->getBasePtr(); + SDValue HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr, DAG.getConstant(4, MVT::i32)); - SDOperand LoLd = DAG.getLoad(MVT::i32, Ld->getChain(), LoAddr, + SDValue LoLd = DAG.getLoad(MVT::i32, Ld->getChain(), LoAddr, Ld->getSrcValue(), Ld->getSrcValueOffset(), Ld->isVolatile(), Ld->getAlignment()); - SDOperand HiLd = DAG.getLoad(MVT::i32, Ld->getChain(), HiAddr, + SDValue HiLd = DAG.getLoad(MVT::i32, Ld->getChain(), HiAddr, Ld->getSrcValue(), Ld->getSrcValueOffset()+4, Ld->isVolatile(), MinAlign(Ld->getAlignment(), 4)); - SDOperand NewChain = LoLd.getValue(1); + SDValue NewChain = LoLd.getValue(1); if (TokenFactorIndex != -1) { Ops.push_back(LoLd); Ops.push_back(HiLd); @@ -6780,22 +6780,22 @@ static SDOperand PerformSTORECombine(SDNode *N, SelectionDAG &DAG, HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr, DAG.getConstant(4, MVT::i32)); - SDOperand LoSt = DAG.getStore(NewChain, LoLd, LoAddr, + SDValue LoSt = DAG.getStore(NewChain, LoLd, LoAddr, St->getSrcValue(), St->getSrcValueOffset(), St->isVolatile(), St->getAlignment()); - SDOperand HiSt = DAG.getStore(NewChain, HiLd, HiAddr, + SDValue HiSt = DAG.getStore(NewChain, HiLd, HiAddr, St->getSrcValue(), St->getSrcValueOffset()+4, St->isVolatile(), MinAlign(St->getAlignment(), 4)); return DAG.getNode(ISD::TokenFactor, MVT::Other, LoSt, HiSt); } } - return SDOperand(); + return SDValue(); } /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and /// X86ISD::FXOR nodes. -static SDOperand PerformFORCombine(SDNode *N, SelectionDAG &DAG) { +static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) { assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); // F[X]OR(0.0, x) -> x // F[X]OR(x, 0.0) -> x @@ -6805,11 +6805,11 @@ static SDOperand PerformFORCombine(SDNode *N, SelectionDAG &DAG) { if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) if (C->getValueAPF().isPosZero()) return N->getOperand(0); - return SDOperand(); + return SDValue(); } /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes. -static SDOperand PerformFANDCombine(SDNode *N, SelectionDAG &DAG) { +static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) { // FAND(0.0, x) -> 0.0 // FAND(x, 0.0) -> 0.0 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) @@ -6818,11 +6818,11 @@ static SDOperand PerformFANDCombine(SDNode *N, SelectionDAG &DAG) { if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) if (C->getValueAPF().isPosZero()) return N->getOperand(1); - return SDOperand(); + return SDValue(); } -SDOperand X86TargetLowering::PerformDAGCombine(SDNode *N, +SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { SelectionDAG &DAG = DCI.DAG; switch (N->getOpcode()) { @@ -6837,7 +6837,7 @@ SDOperand X86TargetLowering::PerformDAGCombine(SDNode *N, case X86ISD::FAND: return PerformFANDCombine(N, DAG); } - return SDOperand(); + return SDValue(); } //===----------------------------------------------------------------------===// @@ -6887,11 +6887,11 @@ LowerXConstraint(MVT ConstraintVT) const { /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops /// vector. If it is invalid, don't add anything to Ops. -void X86TargetLowering::LowerAsmOperandForConstraint(SDOperand Op, +void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, char Constraint, - std::vector<SDOperand>&Ops, + std::vector<SDValue>&Ops, SelectionDAG &DAG) const { - SDOperand Result(0, 0); + SDValue Result(0, 0); switch (Constraint) { default: break; diff --git a/lib/Target/X86/X86ISelLowering.h b/lib/Target/X86/X86ISelLowering.h index 125a30d..8632f3c 100644 --- a/lib/Target/X86/X86ISelLowering.h +++ b/lib/Target/X86/X86ISelLowering.h @@ -325,7 +325,7 @@ namespace llvm { /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC /// jumptable. - SDOperand getPICJumpTableRelocBase(SDOperand Table, + SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const; // Return the number of bytes that a function should pop when it returns (in @@ -357,7 +357,7 @@ namespace llvm { /// LowerOperation - Provide custom lowering hooks for some operations. /// - virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); + virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); /// ReplaceNodeResults - Replace a node with an illegal result type /// with a new node built out of custom code. @@ -365,7 +365,7 @@ namespace llvm { virtual SDNode *ReplaceNodeResults(SDNode *N, SelectionDAG &DAG); - virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; + virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB); @@ -376,12 +376,12 @@ namespace llvm { virtual const char *getTargetNodeName(unsigned Opcode) const; /// getSetCCResultType - Return the ISD::SETCC ValueType - virtual MVT getSetCCResultType(const SDOperand &) const; + virtual MVT getSetCCResultType(const SDValue &) const; /// computeMaskedBitsForTargetNode - Determine which of the bits specified /// in Mask are known to be either zero or one and return them in the /// KnownZero/KnownOne bitsets. - virtual void computeMaskedBitsForTargetNode(const SDOperand Op, + virtual void computeMaskedBitsForTargetNode(const SDValue Op, const APInt &Mask, APInt &KnownZero, APInt &KnownOne, @@ -391,7 +391,7 @@ namespace llvm { virtual bool isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) const; - SDOperand getReturnAddressFrameIndex(SelectionDAG &DAG); + SDValue getReturnAddressFrameIndex(SelectionDAG &DAG); ConstraintType getConstraintType(const std::string &Constraint) const; @@ -403,9 +403,9 @@ namespace llvm { /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops /// vector. If it is invalid, don't add anything to Ops. - virtual void LowerAsmOperandForConstraint(SDOperand Op, + virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter, - std::vector<SDOperand> &Ops, + std::vector<SDValue> &Ops, SelectionDAG &DAG) const; /// getRegForInlineAsmConstraint - Given a physical register constraint @@ -430,13 +430,13 @@ namespace llvm { /// support *some* VECTOR_SHUFFLE operations, those with specific masks. /// By default, if a target supports the VECTOR_SHUFFLE node, all mask /// values are assumed to be legal. - virtual bool isShuffleMaskLegal(SDOperand Mask, MVT VT) const; + virtual bool isShuffleMaskLegal(SDValue Mask, MVT VT) const; /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is /// used by Targets can use this to indicate if there is a suitable /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant /// pool entry. - virtual bool isVectorClearMaskLegal(const std::vector<SDOperand> &BVOps, + virtual bool isVectorClearMaskLegal(const std::vector<SDValue> &BVOps, MVT EVT, SelectionDAG &DAG) const; /// ShouldShrinkFPConstant - If true, then instruction selection should @@ -452,8 +452,8 @@ namespace llvm { /// IsEligibleForTailCallOptimization - Check whether the call is eligible /// for tail call optimization. Target which want to do tail call /// optimization should implement this function. - virtual bool IsEligibleForTailCallOptimization(SDOperand Call, - SDOperand Ret, + virtual bool IsEligibleForTailCallOptimization(SDValue Call, + SDValue Ret, SelectionDAG &DAG) const; virtual const X86Subtarget* getSubtarget() { @@ -483,87 +483,87 @@ namespace llvm { bool X86ScalarSSEf32; bool X86ScalarSSEf64; - SDNode *LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode*TheCall, + SDNode *LowerCallResult(SDValue Chain, SDValue InFlag, SDNode*TheCall, unsigned CallingConv, SelectionDAG &DAG); - SDOperand LowerMemArgument(SDOperand Op, SelectionDAG &DAG, + SDValue LowerMemArgument(SDValue Op, SelectionDAG &DAG, const CCValAssign &VA, MachineFrameInfo *MFI, - unsigned CC, SDOperand Root, unsigned i); + unsigned CC, SDValue Root, unsigned i); - SDOperand LowerMemOpCallTo(SDOperand Op, SelectionDAG &DAG, - const SDOperand &StackPtr, - const CCValAssign &VA, SDOperand Chain, - SDOperand Arg); + SDValue LowerMemOpCallTo(SDValue Op, SelectionDAG &DAG, + const SDValue &StackPtr, + const CCValAssign &VA, SDValue Chain, + SDValue Arg); // Call lowering helpers. - bool IsCalleePop(SDOperand Op); + bool IsCalleePop(SDValue Op); bool CallRequiresGOTPtrInReg(bool Is64Bit, bool IsTailCall); bool CallRequiresFnAddressInReg(bool Is64Bit, bool IsTailCall); - SDOperand EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDOperand &OutRetAddr, - SDOperand Chain, bool IsTailCall, bool Is64Bit, + SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr, + SDValue Chain, bool IsTailCall, bool Is64Bit, int FPDiff); - CCAssignFn *CCAssignFnForNode(SDOperand Op) const; - NameDecorationStyle NameDecorationForFORMAL_ARGUMENTS(SDOperand Op); + CCAssignFn *CCAssignFnForNode(SDValue Op) const; + NameDecorationStyle NameDecorationForFORMAL_ARGUMENTS(SDValue Op); unsigned GetAlignedArgumentStackSize(unsigned StackSize, SelectionDAG &DAG); - std::pair<SDOperand,SDOperand> FP_TO_SINTHelper(SDOperand Op, + std::pair<SDValue,SDValue> FP_TO_SINTHelper(SDValue Op, SelectionDAG &DAG); - SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerEXTRACT_VECTOR_ELT_SSE4(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerINSERT_VECTOR_ELT_SSE4(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerShift(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerFABS(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerFNEG(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerVSETCC(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerSELECT(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerBRCOND(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerMEMSET(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerVAARG(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerVACOPY(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerFRAME_TO_ARGS_OFFSET(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerEH_RETURN(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerTRAMPOLINE(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerCTLZ(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerCTTZ(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerCMP_SWAP(SDOperand Op, SelectionDAG &DAG); + SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG); + SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG); + SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG); + SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG); + SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG); + SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG); + SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG); + SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG); + SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG); + SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG); + SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG); + SDValue LowerShift(SDValue Op, SelectionDAG &DAG); + SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG); + SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG); + SDValue LowerFABS(SDValue Op, SelectionDAG &DAG); + SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG); + SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG); + SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG); + SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG); + SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG); + SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG); + SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG); + SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG); + SDValue LowerCALL(SDValue Op, SelectionDAG &DAG); + SDValue LowerRET(SDValue Op, SelectionDAG &DAG); + SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG); + SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG); + SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG); + SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG); + SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG); + SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG); + SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG); + SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG); + SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG); + SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG); + SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG); + SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG); + SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG); + SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG); + SDValue LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG); SDNode *ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG); SDNode *ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG); SDNode *ExpandATOMIC_CMP_SWAP(SDNode *N, SelectionDAG &DAG); SDNode *ExpandATOMIC_LOAD_SUB(SDNode *N, SelectionDAG &DAG); - SDOperand EmitTargetCodeForMemset(SelectionDAG &DAG, - SDOperand Chain, - SDOperand Dst, SDOperand Src, - SDOperand Size, unsigned Align, + SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, + SDValue Chain, + SDValue Dst, SDValue Src, + SDValue Size, unsigned Align, const Value *DstSV, uint64_t DstSVOff); - SDOperand EmitTargetCodeForMemcpy(SelectionDAG &DAG, - SDOperand Chain, - SDOperand Dst, SDOperand Src, - SDOperand Size, unsigned Align, + SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, + SDValue Chain, + SDValue Dst, SDValue Src, + SDValue Size, unsigned Align, bool AlwaysInline, const Value *DstSV, uint64_t DstSVOff, const Value *SrcSV, uint64_t SrcSVOff); diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index 8cf268e..61dcfa9 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -2262,12 +2262,12 @@ X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, const TargetOperandInfo &TOI = TID.OpInfo[Index]; const TargetRegisterClass *RC = TOI.isLookupPtrRegClass() ? getPointerRegClass() : RI.getRegClass(TOI.RegClass); - std::vector<SDOperand> AddrOps; - std::vector<SDOperand> BeforeOps; - std::vector<SDOperand> AfterOps; + std::vector<SDValue> AddrOps; + std::vector<SDValue> BeforeOps; + std::vector<SDValue> AfterOps; unsigned NumOps = N->getNumOperands(); for (unsigned i = 0; i != NumOps-1; ++i) { - SDOperand Op = N->getOperand(i); + SDValue Op = N->getOperand(i); if (i >= Index && i < Index+4) AddrOps.push_back(Op); else if (i < Index) @@ -2275,7 +2275,7 @@ X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, else if (i > Index) AfterOps.push_back(Op); } - SDOperand Chain = N->getOperand(NumOps-1); + SDValue Chain = N->getOperand(NumOps-1); AddrOps.push_back(Chain); // Emit the load instruction. @@ -2306,7 +2306,7 @@ X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, VTs.push_back(VT); } if (Load) - BeforeOps.push_back(SDOperand(Load, 0)); + BeforeOps.push_back(SDValue(Load, 0)); std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps)); SDNode *NewNode= DAG.getTargetNode(Opc, VTs, &BeforeOps[0], BeforeOps.size()); NewNodes.push_back(NewNode); @@ -2314,7 +2314,7 @@ X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, // Emit the store instruction. if (FoldedStore) { AddrOps.pop_back(); - AddrOps.push_back(SDOperand(NewNode, 0)); + AddrOps.push_back(SDValue(NewNode, 0)); AddrOps.push_back(Chain); bool isAligned = (RI.getStackAlignment() >= 16) || RI.needsStackRealignment(MF); |