diff options
Diffstat (limited to 'test/CodeGen/ARM/vld1.ll')
| -rw-r--r-- | test/CodeGen/ARM/vld1.ll | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/vld1.ll b/test/CodeGen/ARM/vld1.ll index 16bd832..c886125 100644 --- a/test/CodeGen/ARM/vld1.ll +++ b/test/CodeGen/ARM/vld1.ll @@ -16,6 +16,18 @@ define <4 x i16> @vld1i16(i16* %A) nounwind { ret <4 x i16> %tmp1 } +;Check for a post-increment updating load. +define <4 x i16> @vld1i16_update(i16** %ptr) nounwind { +;CHECK: vld1i16_update: +;CHECK: vld1.16 {d16}, [r1]! + %A = load i16** %ptr + %tmp0 = bitcast i16* %A to i8* + %tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16(i8* %tmp0, i32 1) + %tmp2 = getelementptr i16* %A, i32 4 + store i16* %tmp2, i16** %ptr + ret <4 x i16> %tmp1 +} + define <2 x i32> @vld1i32(i32* %A) nounwind { ;CHECK: vld1i32: ;CHECK: vld1.32 @@ -24,6 +36,18 @@ define <2 x i32> @vld1i32(i32* %A) nounwind { ret <2 x i32> %tmp1 } +;Check for a post-increment updating load with register increment. +define <2 x i32> @vld1i32_update(i32** %ptr, i32 %inc) nounwind { +;CHECK: vld1i32_update: +;CHECK: vld1.32 {d16}, [r2], r1 + %A = load i32** %ptr + %tmp0 = bitcast i32* %A to i8* + %tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32(i8* %tmp0, i32 1) + %tmp2 = getelementptr i32* %A, i32 %inc + store i32* %tmp2, i32** %ptr + ret <2 x i32> %tmp1 +} + define <2 x float> @vld1f(float* %A) nounwind { ;CHECK: vld1f: ;CHECK: vld1.32 @@ -48,6 +72,17 @@ define <16 x i8> @vld1Qi8(i8* %A) nounwind { ret <16 x i8> %tmp1 } +;Check for a post-increment updating load. +define <16 x i8> @vld1Qi8_update(i8** %ptr) nounwind { +;CHECK: vld1Qi8_update: +;CHECK: vld1.8 {d16, d17}, [r1, :64]! + %A = load i8** %ptr + %tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %A, i32 8) + %tmp2 = getelementptr i8* %A, i32 16 + store i8* %tmp2, i8** %ptr + ret <16 x i8> %tmp1 +} + define <8 x i16> @vld1Qi16(i16* %A) nounwind { ;CHECK: vld1Qi16: ;Check the alignment value. Max for this instruction is 128 bits: |