diff options
Diffstat (limited to 'test/CodeGen/Alpha')
42 files changed, 855 insertions, 0 deletions
diff --git a/test/CodeGen/Alpha/2005-07-12-TwoMallocCalls.ll b/test/CodeGen/Alpha/2005-07-12-TwoMallocCalls.ll new file mode 100644 index 0000000..87d9928 --- /dev/null +++ b/test/CodeGen/Alpha/2005-07-12-TwoMallocCalls.ll @@ -0,0 +1,17 @@ +; There should be exactly two calls here (memset and malloc), no more. +; RUN: llc < %s -march=alpha | grep jsr | count 2 + +%typedef.bc_struct = type opaque +declare void @llvm.memset.i64(i8*, i8, i64, i32) + +define i1 @l12_l94_bc_divide_endif_2E_3_2E_ce(i32* %tmp.71.reload, i32 %scale2.1.3, i32 %extra.0, %typedef.bc_struct* %n1, %typedef.bc_struct* %n2, i32* %tmp.92.reload, i32 %tmp.94.reload, i32* %tmp.98.reload, i32 %tmp.100.reload, i8** %tmp.112.out, i32* %tmp.157.out, i8** %tmp.158.out) { +newFuncRoot: + %tmp.120 = add i32 %extra.0, 2 ; <i32> [#uses=1] + %tmp.122 = add i32 %tmp.120, %tmp.94.reload ; <i32> [#uses=1] + %tmp.123 = add i32 %tmp.122, %tmp.100.reload ; <i32> [#uses=2] + %tmp.112 = malloc i8, i32 %tmp.123 ; <i8*> [#uses=1] + %tmp.137 = zext i32 %tmp.123 to i64 ; <i64> [#uses=1] + tail call void @llvm.memset.i64( i8* %tmp.112, i8 0, i64 %tmp.137, i32 0 ) + ret i1 true +} + diff --git a/test/CodeGen/Alpha/2005-12-12-MissingFCMov.ll b/test/CodeGen/Alpha/2005-12-12-MissingFCMov.ll new file mode 100644 index 0000000..4b3d022 --- /dev/null +++ b/test/CodeGen/Alpha/2005-12-12-MissingFCMov.ll @@ -0,0 +1,40 @@ +; This shouldn't crash +; RUN: llc < %s -march=alpha + +@.str_4 = external global [44 x i8] ; <[44 x i8]*> [#uses=0] + +declare void @printf(i32, ...) + +define void @main() { +entry: + %tmp.11861 = icmp slt i64 0, 1 ; <i1> [#uses=1] + %tmp.19466 = icmp slt i64 0, 1 ; <i1> [#uses=1] + %tmp.21571 = icmp slt i64 0, 1 ; <i1> [#uses=1] + %tmp.36796 = icmp slt i64 0, 1 ; <i1> [#uses=1] + br i1 %tmp.11861, label %loopexit.2, label %no_exit.2 + +no_exit.2: ; preds = %entry + ret void + +loopexit.2: ; preds = %entry + br i1 %tmp.19466, label %loopexit.3, label %no_exit.3.preheader + +no_exit.3.preheader: ; preds = %loopexit.2 + ret void + +loopexit.3: ; preds = %loopexit.2 + br i1 %tmp.21571, label %no_exit.6, label %no_exit.4 + +no_exit.4: ; preds = %loopexit.3 + ret void + +no_exit.6: ; preds = %no_exit.6, %loopexit.3 + %tmp.30793 = icmp sgt i64 0, 0 ; <i1> [#uses=1] + br i1 %tmp.30793, label %loopexit.6, label %no_exit.6 + +loopexit.6: ; preds = %no_exit.6 + %Z.1 = select i1 %tmp.36796, double 1.000000e+00, double 0x3FEFFF7CEDE74EAE; <double> [#uses=2] + tail call void (i32, ...)* @printf( i32 0, i64 0, i64 0, i64 0, double 1.000000e+00, double 1.000000e+00, double %Z.1, double %Z.1 ) + ret void +} + diff --git a/test/CodeGen/Alpha/2006-01-18-MissedGlobal.ll b/test/CodeGen/Alpha/2006-01-18-MissedGlobal.ll new file mode 100644 index 0000000..65d2a8d --- /dev/null +++ b/test/CodeGen/Alpha/2006-01-18-MissedGlobal.ll @@ -0,0 +1,27 @@ +; The global symbol should be legalized +; RUN: llc < %s -march=alpha + +target datalayout = "e-p:64:64" + %struct.LIST_HELP = type { %struct.LIST_HELP*, i8* } + %struct._IO_FILE = type { i32, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, %struct._IO_marker*, %struct._IO_FILE*, i32, i32, i64, i16, i8, [1 x i8], i8*, i64, i8*, i8*, i32, [44 x i8] } + %struct._IO_marker = type { %struct._IO_marker*, %struct._IO_FILE*, i32 } +@clause_SORT = external global [21 x %struct.LIST_HELP*] ; <[21 x %struct.LIST_HELP*]*> [#uses=0] +@ia_in = external global %struct._IO_FILE* ; <%struct._IO_FILE**> [#uses=1] +@multvec_j = external global [100 x i32] ; <[100 x i32]*> [#uses=0] + +define void @main(i32 %argc) { +clock_Init.exit: + %tmp.5.i575 = load i32* null ; <i32> [#uses=1] + %tmp.309 = icmp eq i32 %tmp.5.i575, 0 ; <i1> [#uses=1] + br i1 %tmp.309, label %UnifiedReturnBlock, label %then.17 + +then.17: ; preds = %clock_Init.exit + store %struct._IO_FILE* null, %struct._IO_FILE** @ia_in + %savedstack = call i8* @llvm.stacksave( ) ; <i8*> [#uses=0] + ret void + +UnifiedReturnBlock: ; preds = %clock_Init.exit + ret void +} + +declare i8* @llvm.stacksave() diff --git a/test/CodeGen/Alpha/2006-01-26-VaargBreak.ll b/test/CodeGen/Alpha/2006-01-26-VaargBreak.ll new file mode 100644 index 0000000..45587f0 --- /dev/null +++ b/test/CodeGen/Alpha/2006-01-26-VaargBreak.ll @@ -0,0 +1,14 @@ +; This shouldn't crash +; RUN: llc < %s -march=alpha + +target datalayout = "e-p:64:64" +target triple = "alphaev6-unknown-linux-gnu" +deplibs = [ "c", "crtend", "stdc++" ] + %struct.__va_list_tag = type { i8*, i32 } + +define i32 @emit_library_call_value(i32 %nargs, ...) { +entry: + %tmp.223 = va_arg %struct.__va_list_tag* null, i32 ; <i32> [#uses=1] + ret i32 %tmp.223 +} + diff --git a/test/CodeGen/Alpha/2006-04-04-zextload.ll b/test/CodeGen/Alpha/2006-04-04-zextload.ll new file mode 100644 index 0000000..2b28903 --- /dev/null +++ b/test/CodeGen/Alpha/2006-04-04-zextload.ll @@ -0,0 +1,34 @@ +; RUN: llc < %s -march=alpha + +target datalayout = "e-p:64:64" +target triple = "alphaev67-unknown-linux-gnu" + %llvm.dbg.compile_unit.type = type { i32, { }*, i32, i32, i8*, i8*, i8* } + %struct._Callback_list = type { %struct._Callback_list*, void (i32, %struct.ios_base*, i32)*, i32, i32 } + %struct._Impl = type { i32, %struct.facet**, i64, %struct.facet**, i8** } + %struct._Words = type { i8*, i64 } + %"struct.__codecvt_abstract_base<char,char,__mbstate_t>" = type { %struct.facet } + %"struct.basic_streambuf<char,std::char_traits<char> >" = type { i32 (...)**, i8*, i8*, i8*, i8*, i8*, i8*, %struct.locale } + %struct.facet = type { i32 (...)**, i32 } + %struct.ios_base = type { i32 (...)**, i64, i64, i32, i32, i32, %struct._Callback_list*, %struct._Words, [8 x %struct._Words], i32, %struct._Words*, %struct.locale } + %struct.locale = type { %struct._Impl* } + %"struct.ostreambuf_iterator<char,std::char_traits<char> >" = type { %"struct.basic_streambuf<char,std::char_traits<char> >"*, i1 } +@llvm.dbg.compile_unit1047 = external global %llvm.dbg.compile_unit.type ; <%llvm.dbg.compile_unit.type*> [#uses=1] + +define void @_ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE15_M_insert_floatIdEES3_S3_RSt8ios_baseccT_() { +entry: + %tmp234 = icmp eq i8 0, 0 ; <i1> [#uses=1] + br i1 %tmp234, label %cond_next243, label %cond_true235 + +cond_true235: ; preds = %entry + ret void + +cond_next243: ; preds = %entry + %tmp428 = load i64* null ; <i64> [#uses=1] + %tmp428.upgrd.1 = trunc i64 %tmp428 to i32 ; <i32> [#uses=1] + %tmp429 = alloca i8, i32 %tmp428.upgrd.1 ; <i8*> [#uses=0] + call void @llvm.dbg.stoppoint( i32 1146, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit1047 to { }*) ) + unreachable +} + +declare void @llvm.dbg.stoppoint(i32, i32, { }*) + diff --git a/test/CodeGen/Alpha/2006-07-03-ASMFormalLowering.ll b/test/CodeGen/Alpha/2006-07-03-ASMFormalLowering.ll new file mode 100644 index 0000000..5d31bc3 --- /dev/null +++ b/test/CodeGen/Alpha/2006-07-03-ASMFormalLowering.ll @@ -0,0 +1,18 @@ +; RUN: llc < %s -march=alpha + +target datalayout = "e-p:64:64" +target triple = "alphaev67-unknown-linux-gnu" + +define i32 @_ZN9__gnu_cxx18__exchange_and_addEPVii(i32* %__mem, i32 %__val) { +entry: + %__tmp = alloca i32, align 4 ; <i32*> [#uses=1] + %tmp3 = call i32 asm sideeffect "\0A$$Lxadd_0:\0A\09ldl_l $0,$3\0A\09addl $0,$4,$1\0A\09stl_c $1,$2\0A\09beq $1,$$Lxadd_0\0A\09mb", "=&r,=*&r,=*m,m,r"( i32* %__tmp, i32* %__mem, i32* %__mem, i32 %__val ) ; <i32> [#uses=1] + ret i32 %tmp3 +} + +define void @_ZN9__gnu_cxx12__atomic_addEPVii(i32* %__mem, i32 %__val) { +entry: + %tmp2 = call i32 asm sideeffect "\0A$$Ladd_1:\0A\09ldl_l $0,$2\0A\09addl $0,$3,$0\0A\09stl_c $0,$1\0A\09beq $0,$$Ladd_1\0A\09mb", "=&r,=*m,m,r"( i32* %__mem, i32* %__mem, i32 %__val ) ; <i32> [#uses=0] + ret void +} + diff --git a/test/CodeGen/Alpha/2006-11-01-vastart.ll b/test/CodeGen/Alpha/2006-11-01-vastart.ll new file mode 100644 index 0000000..14e0bcc --- /dev/null +++ b/test/CodeGen/Alpha/2006-11-01-vastart.ll @@ -0,0 +1,15 @@ +; RUN: llc < %s -march=alpha + +target datalayout = "e-p:64:64" +target triple = "alphaev67-unknown-linux-gnu" + %struct.va_list = type { i8*, i32, i32 } + +define void @yyerror(i32, ...) { +entry: + %va.upgrd.1 = bitcast %struct.va_list* null to i8* ; <i8*> [#uses=1] + call void @llvm.va_start( i8* %va.upgrd.1 ) + ret void +} + +declare void @llvm.va_start(i8*) + diff --git a/test/CodeGen/Alpha/2007-11-27-mulneg3.ll b/test/CodeGen/Alpha/2007-11-27-mulneg3.ll new file mode 100644 index 0000000..b537e25 --- /dev/null +++ b/test/CodeGen/Alpha/2007-11-27-mulneg3.ll @@ -0,0 +1,13 @@ +; RUN: llc < %s -march=alpha + +;FIXME: this should produce no mul inst. But not crashing will have to do for now + +; ModuleID = 'Output/bugpoint-train/bugpoint-reduced-simplified.bc' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-f128:128:128" +target triple = "alphaev6-unknown-linux-gnu" + +define fastcc i32 @getcount(i32 %s) { +cond_next43: ; preds = %bb27 + %tmp431 = mul i32 %s, -3 + ret i32 %tmp431 +} diff --git a/test/CodeGen/Alpha/2008-11-10-smul_lohi.ll b/test/CodeGen/Alpha/2008-11-10-smul_lohi.ll new file mode 100644 index 0000000..1a4b40e --- /dev/null +++ b/test/CodeGen/Alpha/2008-11-10-smul_lohi.ll @@ -0,0 +1,22 @@ +; RUN: llc < %s -march=alpha + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-f128:128:128" +target triple = "alphaev6-unknown-linux-gnu" + +define i64 @__mulvdi3(i64 %a, i64 %b) nounwind { +entry: + %0 = sext i64 %a to i128 ; <i128> [#uses=1] + %1 = sext i64 %b to i128 ; <i128> [#uses=1] + %2 = mul i128 %1, %0 ; <i128> [#uses=2] + %3 = lshr i128 %2, 64 ; <i128> [#uses=1] + %4 = trunc i128 %3 to i64 ; <i64> [#uses=1] + %5 = trunc i128 %2 to i64 ; <i64> [#uses=1] + %6 = icmp eq i64 %4, 0 ; <i1> [#uses=1] + br i1 %6, label %bb1, label %bb + +bb: ; preds = %entry + unreachable + +bb1: ; preds = %entry + ret i64 %5 +} diff --git a/test/CodeGen/Alpha/2008-11-12-Add128.ll b/test/CodeGen/Alpha/2008-11-12-Add128.ll new file mode 100644 index 0000000..8b9b603 --- /dev/null +++ b/test/CodeGen/Alpha/2008-11-12-Add128.ll @@ -0,0 +1,14 @@ +; RUN: llc < %s +; PR3044 +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-f128:128:128" +target triple = "alphaev6-unknown-linux-gnu" + +define i128 @__mulvti3(i128 %u, i128 %v) nounwind { +entry: + %0 = load i128* null, align 16 ; <i128> [#uses=1] + %1 = load i64* null, align 8 ; <i64> [#uses=1] + %2 = zext i64 %1 to i128 ; <i128> [#uses=1] + %3 = add i128 %2, %0 ; <i128> [#uses=1] + store i128 %3, i128* null, align 16 + unreachable +} diff --git a/test/CodeGen/Alpha/2009-07-16-PromoteFloatCompare.ll b/test/CodeGen/Alpha/2009-07-16-PromoteFloatCompare.ll new file mode 100644 index 0000000..cfbf7fc --- /dev/null +++ b/test/CodeGen/Alpha/2009-07-16-PromoteFloatCompare.ll @@ -0,0 +1,6 @@ +; RUN: llc < %s -march=alpha + +define i1 @a(float %x) { + %r = fcmp ult float %x, 1.0 + ret i1 %r +} diff --git a/test/CodeGen/Alpha/add.ll b/test/CodeGen/Alpha/add.ll new file mode 100644 index 0000000..24a7418 --- /dev/null +++ b/test/CodeGen/Alpha/add.ll @@ -0,0 +1,179 @@ +;test all the shifted and signextending adds and subs with and without consts +; +; RUN: llc < %s -march=alpha -o %t.s +; RUN: grep { addl} %t.s | count 2 +; RUN: grep { addq} %t.s | count 2 +; RUN: grep { subl} %t.s | count 2 +; RUN: grep { subq} %t.s | count 1 +; +; RUN: grep {lda \$0,-100(\$16)} %t.s | count 1 +; RUN: grep {s4addl} %t.s | count 2 +; RUN: grep {s8addl} %t.s | count 2 +; RUN: grep {s4addq} %t.s | count 2 +; RUN: grep {s8addq} %t.s | count 2 +; +; RUN: grep {s4subl} %t.s | count 2 +; RUN: grep {s8subl} %t.s | count 2 +; RUN: grep {s4subq} %t.s | count 2 +; RUN: grep {s8subq} %t.s | count 2 + + +define i32 @al(i32 signext %x.s, i32 signext %y.s) signext { +entry: + %tmp.3.s = add i32 %y.s, %x.s ; <i32> [#uses=1] + ret i32 %tmp.3.s +} + +define i32 @ali(i32 signext %x.s) signext { +entry: + %tmp.3.s = add i32 100, %x.s ; <i32> [#uses=1] + ret i32 %tmp.3.s +} + +define i64 @aq(i64 signext %x.s, i64 signext %y.s) signext { +entry: + %tmp.3.s = add i64 %y.s, %x.s ; <i64> [#uses=1] + ret i64 %tmp.3.s +} + +define i64 @aqi(i64 %x.s) { +entry: + %tmp.3.s = add i64 100, %x.s ; <i64> [#uses=1] + ret i64 %tmp.3.s +} + +define i32 @sl(i32 signext %x.s, i32 signext %y.s) signext { +entry: + %tmp.3.s = sub i32 %y.s, %x.s ; <i32> [#uses=1] + ret i32 %tmp.3.s +} + +define i32 @sli(i32 signext %x.s) signext { +entry: + %tmp.3.s = sub i32 %x.s, 100 ; <i32> [#uses=1] + ret i32 %tmp.3.s +} + +define i64 @sq(i64 %x.s, i64 %y.s) { +entry: + %tmp.3.s = sub i64 %y.s, %x.s ; <i64> [#uses=1] + ret i64 %tmp.3.s +} + +define i64 @sqi(i64 %x.s) { +entry: + %tmp.3.s = sub i64 %x.s, 100 ; <i64> [#uses=1] + ret i64 %tmp.3.s +} + +define i32 @a4l(i32 signext %x.s, i32 signext %y.s) signext { +entry: + %tmp.1.s = shl i32 %y.s, 2 ; <i32> [#uses=1] + %tmp.3.s = add i32 %tmp.1.s, %x.s ; <i32> [#uses=1] + ret i32 %tmp.3.s +} + +define i32 @a8l(i32 signext %x.s, i32 signext %y.s) signext { +entry: + %tmp.1.s = shl i32 %y.s, 3 ; <i32> [#uses=1] + %tmp.3.s = add i32 %tmp.1.s, %x.s ; <i32> [#uses=1] + ret i32 %tmp.3.s +} + +define i64 @a4q(i64 %x.s, i64 %y.s) { +entry: + %tmp.1.s = shl i64 %y.s, 2 ; <i64> [#uses=1] + %tmp.3.s = add i64 %tmp.1.s, %x.s ; <i64> [#uses=1] + ret i64 %tmp.3.s +} + +define i64 @a8q(i64 %x.s, i64 %y.s) { +entry: + %tmp.1.s = shl i64 %y.s, 3 ; <i64> [#uses=1] + %tmp.3.s = add i64 %tmp.1.s, %x.s ; <i64> [#uses=1] + ret i64 %tmp.3.s +} + +define i32 @a4li(i32 signext %y.s) signext { +entry: + %tmp.1.s = shl i32 %y.s, 2 ; <i32> [#uses=1] + %tmp.3.s = add i32 100, %tmp.1.s ; <i32> [#uses=1] + ret i32 %tmp.3.s +} + +define i32 @a8li(i32 signext %y.s) signext { +entry: + %tmp.1.s = shl i32 %y.s, 3 ; <i32> [#uses=1] + %tmp.3.s = add i32 100, %tmp.1.s ; <i32> [#uses=1] + ret i32 %tmp.3.s +} + +define i64 @a4qi(i64 %y.s) { +entry: + %tmp.1.s = shl i64 %y.s, 2 ; <i64> [#uses=1] + %tmp.3.s = add i64 100, %tmp.1.s ; <i64> [#uses=1] + ret i64 %tmp.3.s +} + +define i64 @a8qi(i64 %y.s) { +entry: + %tmp.1.s = shl i64 %y.s, 3 ; <i64> [#uses=1] + %tmp.3.s = add i64 100, %tmp.1.s ; <i64> [#uses=1] + ret i64 %tmp.3.s +} + +define i32 @s4l(i32 signext %x.s, i32 signext %y.s) signext { +entry: + %tmp.1.s = shl i32 %y.s, 2 ; <i32> [#uses=1] + %tmp.3.s = sub i32 %tmp.1.s, %x.s ; <i32> [#uses=1] + ret i32 %tmp.3.s +} + +define i32 @s8l(i32 signext %x.s, i32 signext %y.s) signext { +entry: + %tmp.1.s = shl i32 %y.s, 3 ; <i32> [#uses=1] + %tmp.3.s = sub i32 %tmp.1.s, %x.s ; <i32> [#uses=1] + ret i32 %tmp.3.s +} + +define i64 @s4q(i64 %x.s, i64 %y.s) { +entry: + %tmp.1.s = shl i64 %y.s, 2 ; <i64> [#uses=1] + %tmp.3.s = sub i64 %tmp.1.s, %x.s ; <i64> [#uses=1] + ret i64 %tmp.3.s +} + +define i64 @s8q(i64 %x.s, i64 %y.s) { +entry: + %tmp.1.s = shl i64 %y.s, 3 ; <i64> [#uses=1] + %tmp.3.s = sub i64 %tmp.1.s, %x.s ; <i64> [#uses=1] + ret i64 %tmp.3.s +} + +define i32 @s4li(i32 signext %y.s) signext { +entry: + %tmp.1.s = shl i32 %y.s, 2 ; <i32> [#uses=1] + %tmp.3.s = sub i32 %tmp.1.s, 100 ; <i32> [#uses=1] + ret i32 %tmp.3.s +} + +define i32 @s8li(i32 signext %y.s) signext { +entry: + %tmp.1.s = shl i32 %y.s, 3 ; <i32> [#uses=1] + %tmp.3.s = sub i32 %tmp.1.s, 100 ; <i32> [#uses=1] + ret i32 %tmp.3.s +} + +define i64 @s4qi(i64 %y.s) { +entry: + %tmp.1.s = shl i64 %y.s, 2 ; <i64> [#uses=1] + %tmp.3.s = sub i64 %tmp.1.s, 100 ; <i64> [#uses=1] + ret i64 %tmp.3.s +} + +define i64 @s8qi(i64 %y.s) { +entry: + %tmp.1.s = shl i64 %y.s, 3 ; <i64> [#uses=1] + %tmp.3.s = sub i64 %tmp.1.s, 100 ; <i64> [#uses=1] + ret i64 %tmp.3.s +} diff --git a/test/CodeGen/Alpha/add128.ll b/test/CodeGen/Alpha/add128.ll new file mode 100644 index 0000000..fa3b949 --- /dev/null +++ b/test/CodeGen/Alpha/add128.ll @@ -0,0 +1,9 @@ +;test for ADDC and ADDE expansion +; +; RUN: llc < %s -march=alpha + +define i128 @add128(i128 %x, i128 %y) { +entry: + %tmp = add i128 %y, %x + ret i128 %tmp +} diff --git a/test/CodeGen/Alpha/bic.ll b/test/CodeGen/Alpha/bic.ll new file mode 100644 index 0000000..9f00350 --- /dev/null +++ b/test/CodeGen/Alpha/bic.ll @@ -0,0 +1,9 @@ +; Make sure this testcase codegens to the bic instruction +; RUN: llc < %s -march=alpha | grep {bic} + +define i64 @bar(i64 %x, i64 %y) { +entry: + %tmp.1 = xor i64 %x, -1 ; <i64> [#uses=1] + %tmp.2 = and i64 %y, %tmp.1 ; <i64> [#uses=1] + ret i64 %tmp.2 +} diff --git a/test/CodeGen/Alpha/bsr.ll b/test/CodeGen/Alpha/bsr.ll new file mode 100644 index 0000000..14f6b46 --- /dev/null +++ b/test/CodeGen/Alpha/bsr.ll @@ -0,0 +1,12 @@ +; Make sure this testcase codegens the bsr instruction +; RUN: llc < %s -march=alpha | grep bsr + +define internal i64 @abc(i32 %x) { + %tmp.2 = add i32 %x, -1 ; <i32> [#uses=1] + %tmp.0 = call i64 @abc( i32 %tmp.2 ) ; <i64> [#uses=1] + %tmp.5 = add i32 %x, -2 ; <i32> [#uses=1] + %tmp.3 = call i64 @abc( i32 %tmp.5 ) ; <i64> [#uses=1] + %tmp.6 = add i64 %tmp.0, %tmp.3 ; <i64> [#uses=1] + ret i64 %tmp.6 +} + diff --git a/test/CodeGen/Alpha/call_adj.ll b/test/CodeGen/Alpha/call_adj.ll new file mode 100644 index 0000000..24e97a9 --- /dev/null +++ b/test/CodeGen/Alpha/call_adj.ll @@ -0,0 +1,13 @@ +;All this should do is not crash +;RUN: llc < %s -march=alpha + +target datalayout = "e-p:64:64" +target triple = "alphaev67-unknown-linux-gnu" + +define void @_ZNSt13basic_filebufIcSt11char_traitsIcEE22_M_convert_to_externalEPcl(i32 %f) { +entry: + %tmp49 = alloca i8, i32 %f ; <i8*> [#uses=0] + %tmp = call i32 null( i8* null, i8* null, i8* null, i8* null, i8* null, i8* null, i8* null ) ; <i32> [#uses=0] + ret void +} + diff --git a/test/CodeGen/Alpha/cmov.ll b/test/CodeGen/Alpha/cmov.ll new file mode 100644 index 0000000..9b655f0 --- /dev/null +++ b/test/CodeGen/Alpha/cmov.ll @@ -0,0 +1,23 @@ +; RUN: llc < %s -march=alpha | not grep cmovlt +; RUN: llc < %s -march=alpha | grep cmoveq + +define i64 @cmov_lt(i64 %a, i64 %c) { +entry: + %tmp.1 = icmp slt i64 %c, 0 ; <i1> [#uses=1] + %retval = select i1 %tmp.1, i64 %a, i64 10 ; <i64> [#uses=1] + ret i64 %retval +} + +define i64 @cmov_const(i64 %a, i64 %b, i64 %c) { +entry: + %tmp.1 = icmp slt i64 %a, %b ; <i1> [#uses=1] + %retval = select i1 %tmp.1, i64 %c, i64 10 ; <i64> [#uses=1] + ret i64 %retval +} + +define i64 @cmov_lt2(i64 %a, i64 %c) { +entry: + %tmp.1 = icmp sgt i64 %c, 0 ; <i1> [#uses=1] + %retval = select i1 %tmp.1, i64 10, i64 %a ; <i64> [#uses=1] + ret i64 %retval +} diff --git a/test/CodeGen/Alpha/cmpbge.ll b/test/CodeGen/Alpha/cmpbge.ll new file mode 100644 index 0000000..e88d2ee --- /dev/null +++ b/test/CodeGen/Alpha/cmpbge.ll @@ -0,0 +1,16 @@ +; RUN: llc < %s -march=alpha | grep cmpbge | count 2 + +define i1 @test1(i64 %A, i64 %B) { + %C = and i64 %A, 255 ; <i64> [#uses=1] + %D = and i64 %B, 255 ; <i64> [#uses=1] + %E = icmp uge i64 %C, %D ; <i1> [#uses=1] + ret i1 %E +} + +define i1 @test2(i64 %a, i64 %B) { + %A = shl i64 %a, 1 ; <i64> [#uses=1] + %C = and i64 %A, 254 ; <i64> [#uses=1] + %D = and i64 %B, 255 ; <i64> [#uses=1] + %E = icmp uge i64 %C, %D ; <i1> [#uses=1] + ret i1 %E +} diff --git a/test/CodeGen/Alpha/ctlz.ll b/test/CodeGen/Alpha/ctlz.ll new file mode 100644 index 0000000..aa1588a --- /dev/null +++ b/test/CodeGen/Alpha/ctlz.ll @@ -0,0 +1,14 @@ +; Make sure this testcase codegens to the ctlz instruction +; RUN: llc < %s -march=alpha -mcpu=ev67 | grep -i ctlz +; RUN: llc < %s -march=alpha -mattr=+CIX | grep -i ctlz +; RUN: llc < %s -march=alpha -mcpu=ev6 | not grep -i ctlz +; RUN: llc < %s -march=alpha -mattr=-CIX | not grep -i ctlz + +declare i8 @llvm.ctlz.i8(i8) + +define i32 @bar(i8 %x) { +entry: + %tmp.1 = call i8 @llvm.ctlz.i8( i8 %x ) + %tmp.2 = sext i8 %tmp.1 to i32 + ret i32 %tmp.2 +} diff --git a/test/CodeGen/Alpha/ctlz_e.ll b/test/CodeGen/Alpha/ctlz_e.ll new file mode 100644 index 0000000..230e096 --- /dev/null +++ b/test/CodeGen/Alpha/ctlz_e.ll @@ -0,0 +1,11 @@ +; Make sure this testcase does not use ctpop +; RUN: llc < %s -march=alpha | not grep -i ctpop + +declare i64 @llvm.ctlz.i64(i64) + +define i64 @bar(i64 %x) { +entry: + %tmp.1 = call i64 @llvm.ctlz.i64( i64 %x ) ; <i64> [#uses=1] + ret i64 %tmp.1 +} + diff --git a/test/CodeGen/Alpha/ctpop.ll b/test/CodeGen/Alpha/ctpop.ll new file mode 100644 index 0000000..f887882 --- /dev/null +++ b/test/CodeGen/Alpha/ctpop.ll @@ -0,0 +1,17 @@ +; Make sure this testcase codegens to the ctpop instruction +; RUN: llc < %s -march=alpha -mcpu=ev67 | grep -i ctpop +; RUN: llc < %s -march=alpha -mattr=+CIX | \ +; RUN: grep -i ctpop +; RUN: llc < %s -march=alpha -mcpu=ev6 | \ +; RUN: not grep -i ctpop +; RUN: llc < %s -march=alpha -mattr=-CIX | \ +; RUN: not grep -i ctpop + +declare i64 @llvm.ctpop.i64(i64) + +define i64 @bar(i64 %x) { +entry: + %tmp.1 = call i64 @llvm.ctpop.i64( i64 %x ) ; <i64> [#uses=1] + ret i64 %tmp.1 +} + diff --git a/test/CodeGen/Alpha/dg.exp b/test/CodeGen/Alpha/dg.exp new file mode 100644 index 0000000..fb9f710 --- /dev/null +++ b/test/CodeGen/Alpha/dg.exp @@ -0,0 +1,5 @@ +load_lib llvm.exp + +if { [llvm_supports_target Alpha] } { + RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll}]] +} diff --git a/test/CodeGen/Alpha/eqv.ll b/test/CodeGen/Alpha/eqv.ll new file mode 100644 index 0000000..b3413d6 --- /dev/null +++ b/test/CodeGen/Alpha/eqv.ll @@ -0,0 +1,10 @@ +; Make sure this testcase codegens to the eqv instruction +; RUN: llc < %s -march=alpha | grep eqv + +define i64 @bar(i64 %x, i64 %y) { +entry: + %tmp.1 = xor i64 %x, -1 ; <i64> [#uses=1] + %tmp.2 = xor i64 %y, %tmp.1 ; <i64> [#uses=1] + ret i64 %tmp.2 +} + diff --git a/test/CodeGen/Alpha/i32_sub_1.ll b/test/CodeGen/Alpha/i32_sub_1.ll new file mode 100644 index 0000000..ffeafbd --- /dev/null +++ b/test/CodeGen/Alpha/i32_sub_1.ll @@ -0,0 +1,9 @@ +; Make sure this testcase codegens to the ctpop instruction +; RUN: llc < %s -march=alpha | grep -i {subl \$16,1,\$0} + + +define i32 @foo(i32 signext %x) signext { +entry: + %tmp.1 = add i32 %x, -1 ; <int> [#uses=1] + ret i32 %tmp.1 +} diff --git a/test/CodeGen/Alpha/illegal-element-type.ll b/test/CodeGen/Alpha/illegal-element-type.ll new file mode 100644 index 0000000..4cf80de --- /dev/null +++ b/test/CodeGen/Alpha/illegal-element-type.ll @@ -0,0 +1,23 @@ +; RUN: llc < %s -mtriple=alphaev6-unknown-linux-gnu + +define void @foo() { +entry: + br label %bb + +bb: ; preds = %bb, %entry + br i1 false, label %bb26, label %bb + +bb19: ; preds = %bb26 + ret void + +bb26: ; preds = %bb + br i1 false, label %bb30, label %bb19 + +bb30: ; preds = %bb26 + br label %bb45 + +bb45: ; preds = %bb45, %bb30 + %V.0 = phi <8 x i16> [ %tmp42, %bb45 ], [ zeroinitializer, %bb30 ] ; <<8 x i16>> [#uses=1] + %tmp42 = mul <8 x i16> zeroinitializer, %V.0 ; <<8 x i16>> [#uses=1] + br label %bb45 +} diff --git a/test/CodeGen/Alpha/jmp_table.ll b/test/CodeGen/Alpha/jmp_table.ll new file mode 100644 index 0000000..917c932 --- /dev/null +++ b/test/CodeGen/Alpha/jmp_table.ll @@ -0,0 +1,99 @@ +; try to check that we have the most important instructions, which shouldn't +; appear otherwise +; RUN: llc < %s -march=alpha | grep jmp +; RUN: llc < %s -march=alpha | grep gprel32 +; RUN: llc < %s -march=alpha | grep ldl +; RUN: llc < %s -march=alpha | grep rodata +; END. + +target datalayout = "e-p:64:64" +target triple = "alphaev67-unknown-linux-gnu" +@str = internal constant [2 x i8] c"1\00" ; <[2 x i8]*> [#uses=1] +@str1 = internal constant [2 x i8] c"2\00" ; <[2 x i8]*> [#uses=1] +@str2 = internal constant [2 x i8] c"3\00" ; <[2 x i8]*> [#uses=1] +@str3 = internal constant [2 x i8] c"4\00" ; <[2 x i8]*> [#uses=1] +@str4 = internal constant [2 x i8] c"5\00" ; <[2 x i8]*> [#uses=1] +@str5 = internal constant [2 x i8] c"6\00" ; <[2 x i8]*> [#uses=1] +@str6 = internal constant [2 x i8] c"7\00" ; <[2 x i8]*> [#uses=1] +@str7 = internal constant [2 x i8] c"8\00" ; <[2 x i8]*> [#uses=1] + +define i32 @main(i32 %x, i8** %y) { +entry: + %x_addr = alloca i32 ; <i32*> [#uses=2] + %y_addr = alloca i8** ; <i8***> [#uses=1] + %retval = alloca i32, align 4 ; <i32*> [#uses=2] + %tmp = alloca i32, align 4 ; <i32*> [#uses=2] + %foo = alloca i8*, align 8 ; <i8**> [#uses=9] + %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] + store i32 %x, i32* %x_addr + store i8** %y, i8*** %y_addr + %tmp.upgrd.1 = load i32* %x_addr ; <i32> [#uses=1] + switch i32 %tmp.upgrd.1, label %bb15 [ + i32 1, label %bb + i32 2, label %bb1 + i32 3, label %bb3 + i32 4, label %bb5 + i32 5, label %bb7 + i32 6, label %bb9 + i32 7, label %bb11 + i32 8, label %bb13 + ] + +bb: ; preds = %entry + %tmp.upgrd.2 = getelementptr [2 x i8]* @str, i32 0, i64 0 ; <i8*> [#uses=1] + store i8* %tmp.upgrd.2, i8** %foo + br label %bb16 + +bb1: ; preds = %entry + %tmp2 = getelementptr [2 x i8]* @str1, i32 0, i64 0 ; <i8*> [#uses=1] + store i8* %tmp2, i8** %foo + br label %bb16 + +bb3: ; preds = %entry + %tmp4 = getelementptr [2 x i8]* @str2, i32 0, i64 0 ; <i8*> [#uses=1] + store i8* %tmp4, i8** %foo + br label %bb16 + +bb5: ; preds = %entry + %tmp6 = getelementptr [2 x i8]* @str3, i32 0, i64 0 ; <i8*> [#uses=1] + store i8* %tmp6, i8** %foo + br label %bb16 + +bb7: ; preds = %entry + %tmp8 = getelementptr [2 x i8]* @str4, i32 0, i64 0 ; <i8*> [#uses=1] + store i8* %tmp8, i8** %foo + br label %bb16 + +bb9: ; preds = %entry + %tmp10 = getelementptr [2 x i8]* @str5, i32 0, i64 0 ; <i8*> [#uses=1] + store i8* %tmp10, i8** %foo + br label %bb16 + +bb11: ; preds = %entry + %tmp12 = getelementptr [2 x i8]* @str6, i32 0, i64 0 ; <i8*> [#uses=1] + store i8* %tmp12, i8** %foo + br label %bb16 + +bb13: ; preds = %entry + %tmp14 = getelementptr [2 x i8]* @str7, i32 0, i64 0 ; <i8*> [#uses=1] + store i8* %tmp14, i8** %foo + br label %bb16 + +bb15: ; preds = %entry + br label %bb16 + +bb16: ; preds = %bb15, %bb13, %bb11, %bb9, %bb7, %bb5, %bb3, %bb1, %bb + %tmp17 = load i8** %foo ; <i8*> [#uses=1] + %tmp18 = call i32 (...)* @print( i8* %tmp17 ) ; <i32> [#uses=0] + store i32 0, i32* %tmp + %tmp19 = load i32* %tmp ; <i32> [#uses=1] + store i32 %tmp19, i32* %retval + br label %return + +return: ; preds = %bb16 + %retval.upgrd.3 = load i32* %retval ; <i32> [#uses=1] + ret i32 %retval.upgrd.3 +} + +declare i32 @print(...) + diff --git a/test/CodeGen/Alpha/mb.ll b/test/CodeGen/Alpha/mb.ll new file mode 100644 index 0000000..93e8b1b --- /dev/null +++ b/test/CodeGen/Alpha/mb.ll @@ -0,0 +1,8 @@ +; RUN: llc < %s -march=alpha | grep mb + +declare void @llvm.memory.barrier( i1 , i1 , i1 , i1 , i1) + +define void @test() { + call void @llvm.memory.barrier( i1 true, i1 true, i1 true, i1 true , i1 true) + ret void +} diff --git a/test/CodeGen/Alpha/mul128.ll b/test/CodeGen/Alpha/mul128.ll new file mode 100644 index 0000000..daf8409 --- /dev/null +++ b/test/CodeGen/Alpha/mul128.ll @@ -0,0 +1,7 @@ +; RUN: llc < %s -march=alpha + +define i128 @__mulvdi3(i128 %a, i128 %b) nounwind { +entry: + %r = mul i128 %a, %b + ret i128 %r +} diff --git a/test/CodeGen/Alpha/mul5.ll b/test/CodeGen/Alpha/mul5.ll new file mode 100644 index 0000000..4075dd6 --- /dev/null +++ b/test/CodeGen/Alpha/mul5.ll @@ -0,0 +1,33 @@ +; Make sure this testcase does not use mulq +; RUN: llc < %s -march=alpha | not grep -i mul + +define i64 @foo1(i64 %x) { +entry: + %tmp.1 = mul i64 %x, 9 ; <i64> [#uses=1] + ret i64 %tmp.1 +} + +define i64 @foo3(i64 %x) { +entry: + %tmp.1 = mul i64 %x, 259 ; <i64> [#uses=1] + ret i64 %tmp.1 +} + +define i64 @foo4l(i64 %x) { +entry: + %tmp.1 = mul i64 %x, 260 ; <i64> [#uses=1] + ret i64 %tmp.1 +} + +define i64 @foo8l(i64 %x) { +entry: + %tmp.1 = mul i64 %x, 768 ; <i64> [#uses=1] + ret i64 %tmp.1 +} + +define i64 @bar(i64 %x) { +entry: + %tmp.1 = mul i64 %x, 5 ; <i64> [#uses=1] + ret i64 %tmp.1 +} + diff --git a/test/CodeGen/Alpha/neg1.ll b/test/CodeGen/Alpha/neg1.ll new file mode 100644 index 0000000..0db767f --- /dev/null +++ b/test/CodeGen/Alpha/neg1.ll @@ -0,0 +1,7 @@ +; Make sure this testcase codegens to the lda -1 instruction +; RUN: llc < %s -march=alpha | grep {\\-1} + +define i64 @bar() { +entry: + ret i64 -1 +} diff --git a/test/CodeGen/Alpha/not.ll b/test/CodeGen/Alpha/not.ll new file mode 100644 index 0000000..4f0a5c2 --- /dev/null +++ b/test/CodeGen/Alpha/not.ll @@ -0,0 +1,8 @@ +; Make sure this testcase codegens to the ornot instruction +; RUN: llc < %s -march=alpha | grep eqv + +define i64 @bar(i64 %x) { +entry: + %tmp.1 = xor i64 %x, -1 ; <i64> [#uses=1] + ret i64 %tmp.1 +} diff --git a/test/CodeGen/Alpha/ornot.ll b/test/CodeGen/Alpha/ornot.ll new file mode 100644 index 0000000..f930e34 --- /dev/null +++ b/test/CodeGen/Alpha/ornot.ll @@ -0,0 +1,10 @@ +; Make sure this testcase codegens to the ornot instruction +; RUN: llc < %s -march=alpha | grep ornot + +define i64 @bar(i64 %x, i64 %y) { +entry: + %tmp.1 = xor i64 %x, -1 ; <i64> [#uses=1] + %tmp.2 = or i64 %y, %tmp.1 ; <i64> [#uses=1] + ret i64 %tmp.2 +} + diff --git a/test/CodeGen/Alpha/private.ll b/test/CodeGen/Alpha/private.ll new file mode 100644 index 0000000..26076e0 --- /dev/null +++ b/test/CodeGen/Alpha/private.ll @@ -0,0 +1,21 @@ +; Test to make sure that the 'private' is used correctly. +; +; RUN: llc < %s -march=alpha > %t +; RUN: grep \\\$foo: %t +; RUN: grep bsr.*\\\$\\\$foo %t +; RUN: grep \\\$baz: %t +; RUN: grep ldah.*\\\$baz %t + +declare void @foo() + +define private void @foo() { + ret void +} + +@baz = private global i32 4 + +define i32 @bar() { + call void @foo() + %1 = load i32* @baz, align 4 + ret i32 %1 +} diff --git a/test/CodeGen/Alpha/rpcc.ll b/test/CodeGen/Alpha/rpcc.ll new file mode 100644 index 0000000..d6665b5 --- /dev/null +++ b/test/CodeGen/Alpha/rpcc.ll @@ -0,0 +1,9 @@ +; RUN: llc < %s -march=alpha | grep rpcc + +declare i64 @llvm.readcyclecounter() + +define i64 @foo() { +entry: + %tmp.1 = call i64 @llvm.readcyclecounter( ) ; <i64> [#uses=1] + ret i64 %tmp.1 +} diff --git a/test/CodeGen/Alpha/srl_and.ll b/test/CodeGen/Alpha/srl_and.ll new file mode 100644 index 0000000..3042ef3 --- /dev/null +++ b/test/CodeGen/Alpha/srl_and.ll @@ -0,0 +1,10 @@ +; Make sure this testcase codegens to the zapnot instruction +; RUN: llc < %s -march=alpha | grep zapnot + +define i64 @foo(i64 %y) { +entry: + %tmp = lshr i64 %y, 3 ; <i64> [#uses=1] + %tmp2 = and i64 %tmp, 8191 ; <i64> [#uses=1] + ret i64 %tmp2 +} + diff --git a/test/CodeGen/Alpha/sub128.ll b/test/CodeGen/Alpha/sub128.ll new file mode 100644 index 0000000..d26404b --- /dev/null +++ b/test/CodeGen/Alpha/sub128.ll @@ -0,0 +1,9 @@ +;test for SUBC and SUBE expansion +; +; RUN: llc < %s -march=alpha + +define i128 @sub128(i128 %x, i128 %y) { +entry: + %tmp = sub i128 %y, %x + ret i128 %tmp +} diff --git a/test/CodeGen/Alpha/weak.ll b/test/CodeGen/Alpha/weak.ll new file mode 100644 index 0000000..ff04de9 --- /dev/null +++ b/test/CodeGen/Alpha/weak.ll @@ -0,0 +1,16 @@ +; RUN: llc < %s -march=alpha | grep .weak.*f +; RUN: llc < %s -march=alpha | grep .weak.*h + +define weak i32 @f() { +entry: + unreachable +} + +define void @g() { +entry: + tail call void @h( ) + ret void +} + +declare extern_weak void @h() + diff --git a/test/CodeGen/Alpha/wmb.ll b/test/CodeGen/Alpha/wmb.ll new file mode 100644 index 0000000..a3e2ccf --- /dev/null +++ b/test/CodeGen/Alpha/wmb.ll @@ -0,0 +1,8 @@ +; RUN: llc < %s -march=alpha | grep wmb + +declare void @llvm.memory.barrier( i1 , i1 , i1 , i1 , i1) + +define void @test() { + call void @llvm.memory.barrier( i1 false, i1 false, i1 false, i1 true , i1 true) + ret void +} diff --git a/test/CodeGen/Alpha/zapnot.ll b/test/CodeGen/Alpha/zapnot.ll new file mode 100644 index 0000000..d00984a --- /dev/null +++ b/test/CodeGen/Alpha/zapnot.ll @@ -0,0 +1,9 @@ +; Make sure this testcase codegens to the bic instruction +; RUN: llc < %s -march=alpha | grep zapnot + + +define i16 @foo(i64 %y) zeroext { +entry: + %tmp.1 = trunc i64 %y to i16 ; <ushort> [#uses=1] + ret i16 %tmp.1 +} diff --git a/test/CodeGen/Alpha/zapnot2.ll b/test/CodeGen/Alpha/zapnot2.ll new file mode 100644 index 0000000..cd3caae --- /dev/null +++ b/test/CodeGen/Alpha/zapnot2.ll @@ -0,0 +1,9 @@ +; Make sure this testcase codegens to the zapnot instruction +; RUN: llc < %s -march=alpha | grep zapnot + +define i64 @bar(i64 %x) { +entry: + %tmp.1 = and i64 %x, 16711935 ; <i64> [#uses=1] + ret i64 %tmp.1 +} + diff --git a/test/CodeGen/Alpha/zapnot3.ll b/test/CodeGen/Alpha/zapnot3.ll new file mode 100644 index 0000000..f02961f --- /dev/null +++ b/test/CodeGen/Alpha/zapnot3.ll @@ -0,0 +1,15 @@ +; RUN: llc < %s -march=alpha | grep zapnot + +;demanded bits mess up this mask in a hard to fix way +;define i64 @foo(i64 %y) { +; %tmp = and i64 %y, 65535 +; %tmp2 = shr i64 %tmp, i8 3 +; ret i64 %tmp2 +;} + +define i64 @foo2(i64 %y) { + %tmp = lshr i64 %y, 3 ; <i64> [#uses=1] + %tmp2 = and i64 %tmp, 8191 ; <i64> [#uses=1] + ret i64 %tmp2 +} + diff --git a/test/CodeGen/Alpha/zapnot4.ll b/test/CodeGen/Alpha/zapnot4.ll new file mode 100644 index 0000000..89beeef --- /dev/null +++ b/test/CodeGen/Alpha/zapnot4.ll @@ -0,0 +1,7 @@ +; RUN: llc < %s -march=alpha | grep zapnot + +define i64 @foo(i64 %y) { + %tmp = shl i64 %y, 3 ; <i64> [#uses=1] + %tmp2 = and i64 %tmp, 65535 ; <i64> [#uses=1] + ret i64 %tmp2 +} |