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-rw-r--r--test/CodeGen/Mips/msa/elm_insv.ll138
1 files changed, 78 insertions, 60 deletions
diff --git a/test/CodeGen/Mips/msa/elm_insv.ll b/test/CodeGen/Mips/msa/elm_insv.ll
index fa7ceaf..c746e52 100644
--- a/test/CodeGen/Mips/msa/elm_insv.ll
+++ b/test/CodeGen/Mips/msa/elm_insv.ll
@@ -1,8 +1,14 @@
; Test the MSA element insertion intrinsics that are encoded with the ELM
; instruction format.
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | \
+; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS32
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | \
+; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS32
+; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \
+; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS64
+; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \
+; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS64
@llvm_mips_insert_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_insert_b_ARG3 = global i32 27, align 16
@@ -19,12 +25,12 @@ entry:
declare <16 x i8> @llvm.mips.insert.b(<16 x i8>, i32, i32) nounwind
-; CHECK: llvm_mips_insert_b_test:
-; CHECK-DAG: lw [[R1:\$[0-9]+]], 0(
-; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0(
-; CHECK-DAG: insert.b [[R2]][1], [[R1]]
-; CHECK-DAG: st.b [[R2]], 0(
-; CHECK: .size llvm_mips_insert_b_test
+; MIPS-ANY: llvm_mips_insert_b_test:
+; MIPS-ANY-DAG: lw [[R1:\$[0-9]+]], 0(
+; MIPS-ANY-DAG: ld.b [[R2:\$w[0-9]+]], 0(
+; MIPS-ANY-DAG: insert.b [[R2]][1], [[R1]]
+; MIPS-ANY-DAG: st.b [[R2]], 0(
+; MIPS-ANY: .size llvm_mips_insert_b_test
;
@llvm_mips_insert_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
@llvm_mips_insert_h_ARG3 = global i32 27, align 16
@@ -41,12 +47,12 @@ entry:
declare <8 x i16> @llvm.mips.insert.h(<8 x i16>, i32, i32) nounwind
-; CHECK: llvm_mips_insert_h_test:
-; CHECK-DAG: lw [[R1:\$[0-9]+]], 0(
-; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0(
-; CHECK-DAG: insert.h [[R2]][1], [[R1]]
-; CHECK-DAG: st.h [[R2]], 0(
-; CHECK: .size llvm_mips_insert_h_test
+; MIPS-ANY: llvm_mips_insert_h_test:
+; MIPS-ANY-DAG: lw [[R1:\$[0-9]+]], 0(
+; MIPS-ANY-DAG: ld.h [[R2:\$w[0-9]+]], 0(
+; MIPS-ANY-DAG: insert.h [[R2]][1], [[R1]]
+; MIPS-ANY-DAG: st.h [[R2]], 0(
+; MIPS-ANY: .size llvm_mips_insert_h_test
;
@llvm_mips_insert_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
@llvm_mips_insert_w_ARG3 = global i32 27, align 16
@@ -63,12 +69,12 @@ entry:
declare <4 x i32> @llvm.mips.insert.w(<4 x i32>, i32, i32) nounwind
-; CHECK: llvm_mips_insert_w_test:
-; CHECK-DAG: lw [[R1:\$[0-9]+]], 0(
-; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0(
-; CHECK-DAG: insert.w [[R2]][1], [[R1]]
-; CHECK-DAG: st.w [[R2]], 0(
-; CHECK: .size llvm_mips_insert_w_test
+; MIPS-ANY: llvm_mips_insert_w_test:
+; MIPS-ANY-DAG: lw [[R1:\$[0-9]+]], 0(
+; MIPS-ANY-DAG: ld.w [[R2:\$w[0-9]+]], 0(
+; MIPS-ANY-DAG: insert.w [[R2]][1], [[R1]]
+; MIPS-ANY-DAG: st.w [[R2]], 0(
+; MIPS-ANY: .size llvm_mips_insert_w_test
;
@llvm_mips_insert_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
@llvm_mips_insert_d_ARG3 = global i64 27, align 16
@@ -85,14 +91,18 @@ entry:
declare <2 x i64> @llvm.mips.insert.d(<2 x i64>, i32, i64) nounwind
-; CHECK: llvm_mips_insert_d_test:
-; CHECK-DAG: lw [[R1:\$[0-9]+]], 0(
-; CHECK-DAG: lw [[R2:\$[0-9]+]], 4(
-; CHECK-DAG: ld.w [[R3:\$w[0-9]+]],
-; CHECK-DAG: insert.w [[R3]][2], [[R1]]
-; CHECK-DAG: insert.w [[R3]][3], [[R2]]
-; CHECK-DAG: st.w [[R3]],
-; CHECK: .size llvm_mips_insert_d_test
+; MIPS-ANY: llvm_mips_insert_d_test:
+; MIPS32-DAG: lw [[R1:\$[0-9]+]], 0(
+; MIPS32-DAG: lw [[R2:\$[0-9]+]], 4(
+; MIPS64-DAG: ld [[R1:\$[0-9]+]], 0(
+; MIPS32-DAG: ld.w [[R3:\$w[0-9]+]],
+; MIPS64-DAG: ld.d [[W1:\$w[0-9]+]],
+; MIPS32-DAG: insert.w [[R3]][2], [[R1]]
+; MIPS32-DAG: insert.w [[R3]][3], [[R2]]
+; MIPS64-DAG: insert.d [[W1]][1], [[R1]]
+; MIPS32-DAG: st.w [[R3]],
+; MIPS64-DAG: st.d [[W1]],
+; MIPS-ANY: .size llvm_mips_insert_d_test
;
@llvm_mips_insve_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_insve_b_ARG3 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
@@ -109,14 +119,16 @@ entry:
declare <16 x i8> @llvm.mips.insve.b(<16 x i8>, i32, <16 x i8>) nounwind
-; CHECK: llvm_mips_insve_b_test:
-; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_insve_b_ARG1)(
-; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_insve_b_ARG3)(
-; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0([[R1]])
-; CHECK-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R2]])
-; CHECK-DAG: insve.b [[R3]][1], [[R4]][0]
-; CHECK-DAG: st.b [[R3]],
-; CHECK: .size llvm_mips_insve_b_test
+; MIPS-ANY: llvm_mips_insve_b_test:
+; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_insve_b_ARG1)(
+; MIPS32-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_insve_b_ARG3)(
+; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_insve_b_ARG1)(
+; MIPS64-DAG: ld [[R2:\$[0-9]+]], %got_disp(llvm_mips_insve_b_ARG3)(
+; MIPS-ANY-DAG: ld.b [[R3:\$w[0-9]+]], 0([[R1]])
+; MIPS-ANY-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R2]])
+; MIPS-ANY-DAG: insve.b [[R3]][1], [[R4]][0]
+; MIPS-ANY-DAG: st.b [[R3]],
+; MIPS-ANY: .size llvm_mips_insve_b_test
;
@llvm_mips_insve_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
@llvm_mips_insve_h_ARG3 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
@@ -133,14 +145,16 @@ entry:
declare <8 x i16> @llvm.mips.insve.h(<8 x i16>, i32, <8 x i16>) nounwind
-; CHECK: llvm_mips_insve_h_test:
-; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_insve_h_ARG1)(
-; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_insve_h_ARG3)(
-; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], 0([[R1]])
-; CHECK-DAG: ld.h [[R4:\$w[0-9]+]], 0([[R2]])
-; CHECK-DAG: insve.h [[R3]][1], [[R4]][0]
-; CHECK-DAG: st.h [[R3]],
-; CHECK: .size llvm_mips_insve_h_test
+; MIPS-ANY: llvm_mips_insve_h_test:
+; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_insve_h_ARG1)(
+; MIPS32-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_insve_h_ARG3)(
+; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_insve_h_ARG1)(
+; MIPS64-DAG: ld [[R2:\$[0-9]+]], %got_disp(llvm_mips_insve_h_ARG3)(
+; MIPS-ANY-DAG: ld.h [[R3:\$w[0-9]+]], 0([[R1]])
+; MIPS-ANY-DAG: ld.h [[R4:\$w[0-9]+]], 0([[R2]])
+; MIPS-ANY-DAG: insve.h [[R3]][1], [[R4]][0]
+; MIPS-ANY-DAG: st.h [[R3]],
+; MIPS-ANY: .size llvm_mips_insve_h_test
;
@llvm_mips_insve_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
@llvm_mips_insve_w_ARG3 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
@@ -157,14 +171,16 @@ entry:
declare <4 x i32> @llvm.mips.insve.w(<4 x i32>, i32, <4 x i32>) nounwind
-; CHECK: llvm_mips_insve_w_test:
-; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_insve_w_ARG1)(
-; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_insve_w_ARG3)(
-; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0([[R1]])
-; CHECK-DAG: ld.w [[R4:\$w[0-9]+]], 0([[R2]])
-; CHECK-DAG: insve.w [[R3]][1], [[R4]][0]
-; CHECK-DAG: st.w [[R3]],
-; CHECK: .size llvm_mips_insve_w_test
+; MIPS-ANY: llvm_mips_insve_w_test:
+; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_insve_w_ARG1)(
+; MIPS32-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_insve_w_ARG3)(
+; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_insve_w_ARG1)(
+; MIPS64-DAG: ld [[R2:\$[0-9]+]], %got_disp(llvm_mips_insve_w_ARG3)(
+; MIPS-ANY-DAG: ld.w [[R3:\$w[0-9]+]], 0([[R1]])
+; MIPS-ANY-DAG: ld.w [[R4:\$w[0-9]+]], 0([[R2]])
+; MIPS-ANY-DAG: insve.w [[R3]][1], [[R4]][0]
+; MIPS-ANY-DAG: st.w [[R3]],
+; MIPS-ANY: .size llvm_mips_insve_w_test
;
@llvm_mips_insve_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
@llvm_mips_insve_d_ARG3 = global <2 x i64> <i64 2, i64 3>, align 16
@@ -181,12 +197,14 @@ entry:
declare <2 x i64> @llvm.mips.insve.d(<2 x i64>, i32, <2 x i64>) nounwind
-; CHECK: llvm_mips_insve_d_test:
-; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_insve_d_ARG1)(
-; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_insve_d_ARG3)(
-; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0([[R1]])
-; CHECK-DAG: ld.d [[R4:\$w[0-9]+]], 0([[R2]])
-; CHECK-DAG: insve.d [[R3]][1], [[R4]][0]
-; CHECK-DAG: st.d [[R3]],
-; CHECK: .size llvm_mips_insve_d_test
+; MIPS-ANY: llvm_mips_insve_d_test:
+; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_insve_d_ARG1)(
+; MIPS32-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_insve_d_ARG3)(
+; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_insve_d_ARG1)(
+; MIPS64-DAG: ld [[R2:\$[0-9]+]], %got_disp(llvm_mips_insve_d_ARG3)(
+; MIPS-ANY-DAG: ld.d [[R3:\$w[0-9]+]], 0([[R1]])
+; MIPS-ANY-DAG: ld.d [[R4:\$w[0-9]+]], 0([[R2]])
+; MIPS-ANY-DAG: insve.d [[R3]][1], [[R4]][0]
+; MIPS-ANY-DAG: st.d [[R3]],
+; MIPS-ANY: .size llvm_mips_insve_d_test
;
generated by cgit v1.1 at 2024-12-22 15:47:20 +0000