diff options
Diffstat (limited to 'test/CodeGen/PowerPC/mcm-4.ll')
| -rw-r--r-- | test/CodeGen/PowerPC/mcm-4.ll | 20 |
1 files changed, 18 insertions, 2 deletions
diff --git a/test/CodeGen/PowerPC/mcm-4.ll b/test/CodeGen/PowerPC/mcm-4.ll index 73dd902..e4ceb3a 100644 --- a/test/CodeGen/PowerPC/mcm-4.ll +++ b/test/CodeGen/PowerPC/mcm-4.ll @@ -1,5 +1,7 @@ -; RUN: llc -mcpu=pwr7 -O0 -code-model=medium -fast-isel=false <%s | FileCheck -check-prefix=MEDIUM %s -; RUN: llc -mcpu=pwr7 -O0 -code-model=large -fast-isel=false <%s | FileCheck -check-prefix=LARGE %s +; RUN: llc -mcpu=pwr7 -O0 -code-model=medium -fast-isel=false -mattr=-vsx <%s | FileCheck -check-prefix=MEDIUM %s +; RUN: llc -mcpu=pwr7 -O0 -code-model=medium -fast-isel=false -mattr=+vsx <%s | FileCheck -check-prefix=MEDIUM-VSX %s +; RUN: llc -mcpu=pwr7 -O0 -code-model=large -fast-isel=false -mattr=-vsx <%s | FileCheck -check-prefix=LARGE %s +; RUN: llc -mcpu=pwr7 -O0 -code-model=large -fast-isel=false -mattr=+vsx <%s | FileCheck -check-prefix=LARGE-VSX %s ; Test correct code generation for medium and large code model ; for loading a value from the constant pool (TOC-relative). @@ -19,9 +21,23 @@ entry: ; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l ; MEDIUM: lfd {{[0-9]+}}, 0([[REG2]]) +; MEDIUM-VSX: [[VAR:[a-z0-9A-Z_.]+]]: +; MEDIUM-VSX: .quad 4562098671269285104 +; MEDIUM-VSX-LABEL: test_double_const: +; MEDIUM-VSX: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha +; MEDIUM-VSX: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l +; MEDIUM-VSX: lxsdx {{[0-9]+}}, 0, [[REG2]] + ; LARGE: [[VAR:[a-z0-9A-Z_.]+]]: ; LARGE: .quad 4562098671269285104 ; LARGE-LABEL: test_double_const: ; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha ; LARGE: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]]) ; LARGE: lfd {{[0-9]+}}, 0([[REG2]]) + +; LARGE-VSX: [[VAR:[a-z0-9A-Z_.]+]]: +; LARGE-VSX: .quad 4562098671269285104 +; LARGE-VSX-LABEL: test_double_const: +; LARGE-VSX: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha +; LARGE-VSX: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]]) +; LARGE-VSX: lxsdx {{[0-9]+}}, 0, [[REG2]] |