diff options
Diffstat (limited to 'test/CodeGen/R600/add_i64.ll')
| -rw-r--r-- | test/CodeGen/R600/add_i64.ll | 39 |
1 files changed, 32 insertions, 7 deletions
diff --git a/test/CodeGen/R600/add_i64.ll b/test/CodeGen/R600/add_i64.ll index 303a1cb..7081b07 100644 --- a/test/CodeGen/R600/add_i64.ll +++ b/test/CodeGen/R600/add_i64.ll @@ -1,14 +1,13 @@ -; XFAIL: * -; This will fail until i64 add is enabled +; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI %s -; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck --check-prefix=SI %s - -declare i32 @llvm.SI.tid() readnone +declare i32 @llvm.r600.read.tidig.x() readnone ; SI-LABEL: @test_i64_vreg: +; SI: V_ADD_I32 +; SI: V_ADDC_U32 define void @test_i64_vreg(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %inA, i64 addrspace(1)* noalias %inB) { - %tid = call i32 @llvm.SI.tid() readnone + %tid = call i32 @llvm.r600.read.tidig.x() readnone %a_ptr = getelementptr i64 addrspace(1)* %inA, i32 %tid %b_ptr = getelementptr i64 addrspace(1)* %inB, i32 %tid %a = load i64 addrspace(1)* %a_ptr @@ -20,6 +19,8 @@ define void @test_i64_vreg(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noa ; Check that the SGPR add operand is correctly moved to a VGPR. ; SI-LABEL: @sgpr_operand: +; SI: V_ADD_I32 +; SI: V_ADDC_U32 define void @sgpr_operand(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i64 addrspace(1)* noalias %in_bar, i64 %a) { %foo = load i64 addrspace(1)* %in, align 8 %result = add i64 %foo, %a @@ -31,6 +32,8 @@ define void @sgpr_operand(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noal ; SGPR as other operand. ; ; SI-LABEL: @sgpr_operand_reversed: +; SI: V_ADD_I32 +; SI: V_ADDC_U32 define void @sgpr_operand_reversed(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i64 %a) { %foo = load i64 addrspace(1)* %in, align 8 %result = add i64 %a, %foo @@ -40,6 +43,10 @@ define void @sgpr_operand_reversed(i64 addrspace(1)* noalias %out, i64 addrspace ; SI-LABEL: @test_v2i64_sreg: +; SI: S_ADD_I32 +; SI: S_ADDC_U32 +; SI: S_ADD_I32 +; SI: S_ADDC_U32 define void @test_v2i64_sreg(<2 x i64> addrspace(1)* noalias %out, <2 x i64> %a, <2 x i64> %b) { %result = add <2 x i64> %a, %b store <2 x i64> %result, <2 x i64> addrspace(1)* %out @@ -47,8 +54,12 @@ define void @test_v2i64_sreg(<2 x i64> addrspace(1)* noalias %out, <2 x i64> %a, } ; SI-LABEL: @test_v2i64_vreg: +; SI: V_ADD_I32 +; SI: V_ADDC_U32 +; SI: V_ADD_I32 +; SI: V_ADDC_U32 define void @test_v2i64_vreg(<2 x i64> addrspace(1)* noalias %out, <2 x i64> addrspace(1)* noalias %inA, <2 x i64> addrspace(1)* noalias %inB) { - %tid = call i32 @llvm.SI.tid() readnone + %tid = call i32 @llvm.r600.read.tidig.x() readnone %a_ptr = getelementptr <2 x i64> addrspace(1)* %inA, i32 %tid %b_ptr = getelementptr <2 x i64> addrspace(1)* %inB, i32 %tid %a = load <2 x i64> addrspace(1)* %a_ptr @@ -57,3 +68,17 @@ define void @test_v2i64_vreg(<2 x i64> addrspace(1)* noalias %out, <2 x i64> add store <2 x i64> %result, <2 x i64> addrspace(1)* %out ret void } + +; SI-LABEL: @trunc_i64_add_to_i32 +; SI: S_LOAD_DWORD [[SREG0:s[0-9]+]], +; SI: S_LOAD_DWORD [[SREG1:s[0-9]+]], +; SI: S_ADD_I32 [[SRESULT:s[0-9]+]], [[SREG1]], [[SREG0]] +; SI-NOT: ADDC +; SI: V_MOV_B32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]] +; SI: BUFFER_STORE_DWORD [[VRESULT]], +define void @trunc_i64_add_to_i32(i32 addrspace(1)* %out, i64 %a, i64 %b) { + %add = add i64 %b, %a + %trunc = trunc i64 %add to i32 + store i32 %trunc, i32 addrspace(1)* %out, align 8 + ret void +} |