diff options
Diffstat (limited to 'test/CodeGen/R600')
84 files changed, 86 insertions, 86 deletions
diff --git a/test/CodeGen/R600/128bit-kernel-args.ll b/test/CodeGen/R600/128bit-kernel-args.ll index 5c14270..3c4fcf7 100644 --- a/test/CodeGen/R600/128bit-kernel-args.ll +++ b/test/CodeGen/R600/128bit-kernel-args.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK -; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK ; R600-CHECK: @v4i32_kernel_arg ; R600-CHECK-DAG: MOV {{[* ]*}}T[[GPR:[0-9]]].X, KC0[3].Y diff --git a/test/CodeGen/R600/32-bit-local-address-space.ll b/test/CodeGen/R600/32-bit-local-address-space.ll index d19a82e..8c96ec3 100644 --- a/test/CodeGen/R600/32-bit-local-address-space.ll +++ b/test/CodeGen/R600/32-bit-local-address-space.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s ; On Southern Islands GPUs the local address space(3) uses 32-bit pointers and ; the global address space(1) uses 64-bit pointers. These tests check to make sure diff --git a/test/CodeGen/R600/64bit-kernel-args.ll b/test/CodeGen/R600/64bit-kernel-args.ll index 34a0a87..49291e0 100644 --- a/test/CodeGen/R600/64bit-kernel-args.ll +++ b/test/CodeGen/R600/64bit-kernel-args.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=r600 -mcpu=tahiti | FileCheck %s --check-prefix=SI-CHECK +; RUN: llc < %s -march=r600 -mcpu=tahiti -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK ; SI-CHECK: @f64_kernel_arg ; SI-CHECK-DAG: S_LOAD_DWORDX2 SGPR{{[0-9]}}_SGPR{{[0-9]}}, SGPR0_SGPR1, 9 diff --git a/test/CodeGen/R600/add.ll b/test/CodeGen/R600/add.ll index 16f7f97..23e62d7 100644 --- a/test/CodeGen/R600/add.ll +++ b/test/CodeGen/R600/add.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s -; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s ;EG-CHECK: @test2 ;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} diff --git a/test/CodeGen/R600/and.ll b/test/CodeGen/R600/and.ll index dbb6eef..bafb934 100644 --- a/test/CodeGen/R600/and.ll +++ b/test/CodeGen/R600/and.ll @@ -1,5 +1,5 @@ ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s -;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s ;EG-CHECK: @test2 ;EG-CHECK: AND_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} diff --git a/test/CodeGen/R600/atomic_load_add.ll b/test/CodeGen/R600/atomic_load_add.ll index 054d9cd..0bc48a3 100644 --- a/test/CodeGen/R600/atomic_load_add.ll +++ b/test/CodeGen/R600/atomic_load_add.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK -; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK ; R600-CHECK-LABEL: @atomic_add_local ; R600-CHECK: LDS_ADD * diff --git a/test/CodeGen/R600/atomic_load_sub.ll b/test/CodeGen/R600/atomic_load_sub.ll index e256f07..e4a6829 100644 --- a/test/CodeGen/R600/atomic_load_sub.ll +++ b/test/CodeGen/R600/atomic_load_sub.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK -; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK ; R600-CHECK-LABEL: @atomic_sub_local ; R600-CHECK: LDS_SUB * diff --git a/test/CodeGen/R600/bfi_int.ll b/test/CodeGen/R600/bfi_int.ll index cdccdfa..d4dc379 100644 --- a/test/CodeGen/R600/bfi_int.ll +++ b/test/CodeGen/R600/bfi_int.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600-CHECK %s -; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck --check-prefix=SI-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s ; BFI_INT Definition pattern from ISA docs ; (y & x) | (z & ~x) diff --git a/test/CodeGen/R600/bitcast.ll b/test/CodeGen/R600/bitcast.ll index 399444b..bccc416 100644 --- a/test/CodeGen/R600/bitcast.ll +++ b/test/CodeGen/R600/bitcast.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s ; This test just checks that the compiler doesn't crash. ; CHECK-LABEL: @v32i8_to_v8i32 diff --git a/test/CodeGen/R600/build_vector.ll b/test/CodeGen/R600/build_vector.ll index 9b738a2..9967761 100644 --- a/test/CodeGen/R600/build_vector.ll +++ b/test/CodeGen/R600/build_vector.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK -; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK ; R600-CHECK: @build_vector2 ; R600-CHECK: MOV diff --git a/test/CodeGen/R600/elf.ll b/test/CodeGen/R600/elf.ll index f460f13..9385150 100644 --- a/test/CodeGen/R600/elf.ll +++ b/test/CodeGen/R600/elf.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=r600 -mcpu=SI -filetype=obj | llvm-readobj -s - | FileCheck --check-prefix=ELF-CHECK %s -; RUN: llc < %s -march=r600 -mcpu=SI -o - | FileCheck --check-prefix=CONFIG-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs -filetype=obj | llvm-readobj -s - | FileCheck --check-prefix=ELF-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs -o - | FileCheck --check-prefix=CONFIG-CHECK %s ; ELF-CHECK: Format: ELF32 ; ELF-CHECK: Name: .AMDGPU.config diff --git a/test/CodeGen/R600/fabs.ll b/test/CodeGen/R600/fabs.ll index 78ffd57..d318c42 100644 --- a/test/CodeGen/R600/fabs.ll +++ b/test/CodeGen/R600/fabs.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK -; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK ; DAGCombiner will transform: ; (fabs (f32 bitcast (i32 a))) => (f32 bitcast (and (i32 a), 0x7FFFFFFF)) diff --git a/test/CodeGen/R600/fadd.ll b/test/CodeGen/R600/fadd.ll index 91bfdbc..f467bb7 100644 --- a/test/CodeGen/R600/fadd.ll +++ b/test/CodeGen/R600/fadd.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK -; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK ; R600-CHECK: @fadd_f32 ; R600-CHECK: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].W diff --git a/test/CodeGen/R600/fadd64.ll b/test/CodeGen/R600/fadd64.ll index 130302f..d272aaa 100644 --- a/test/CodeGen/R600/fadd64.ll +++ b/test/CodeGen/R600/fadd64.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=r600 -mcpu=tahiti | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=tahiti -verify-machineinstrs | FileCheck %s ; CHECK: @fadd_f64 ; CHECK: V_ADD_F64 {{VGPR[0-9]+_VGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+}} diff --git a/test/CodeGen/R600/fcmp64.ll b/test/CodeGen/R600/fcmp64.ll index 8f2513b..a24bd82 100644 --- a/test/CodeGen/R600/fcmp64.ll +++ b/test/CodeGen/R600/fcmp64.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=r600 -mcpu=tahiti | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=tahiti -verify-machineinstrs | FileCheck %s ; CHECK: @flt_f64 ; CHECK: V_CMP_LT_F64_e64 {{SGPR[0-9]+_SGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+}} diff --git a/test/CodeGen/R600/fconst64.ll b/test/CodeGen/R600/fconst64.ll index 2402a9c..7433c56 100644 --- a/test/CodeGen/R600/fconst64.ll +++ b/test/CodeGen/R600/fconst64.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=r600 -mcpu=tahiti | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=tahiti -verify-machineinstrs | FileCheck %s ; CHECK: @fconst_f64 ; CHECK: V_MOV_B32_e32 {{VGPR[0-9]+}}, 0.000000e+00 diff --git a/test/CodeGen/R600/fdiv.ll b/test/CodeGen/R600/fdiv.ll index 090cedf..3d21524 100644 --- a/test/CodeGen/R600/fdiv.ll +++ b/test/CodeGen/R600/fdiv.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK -; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK ; These tests check that fdiv is expanded correctly and also test that the ; scheduler is scheduling the RECIP_IEEE and MUL_IEEE instructions in separate diff --git a/test/CodeGen/R600/fdiv64.ll b/test/CodeGen/R600/fdiv64.ll index 76c5ca3..80ed3f2 100644 --- a/test/CodeGen/R600/fdiv64.ll +++ b/test/CodeGen/R600/fdiv64.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=r600 -mcpu=tahiti | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=tahiti -verify-machineinstrs | FileCheck %s ; CHECK: @fdiv_f64 ; CHECK: V_RCP_F64_e32 {{VGPR[0-9]+_VGPR[0-9]+}} diff --git a/test/CodeGen/R600/fma.ll b/test/CodeGen/R600/fma.ll index afef970..cac679e 100644 --- a/test/CodeGen/R600/fma.ll +++ b/test/CodeGen/R600/fma.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s ; CHECK: @fma_f32 ; CHECK: V_FMA_F32 {{VGPR[0-9]+, VGPR[0-9]+, VGPR[0-9]+, VGPR[0-9]+}} diff --git a/test/CodeGen/R600/fmul.ll b/test/CodeGen/R600/fmul.ll index 4a7d6cd..2a7825f 100644 --- a/test/CodeGen/R600/fmul.ll +++ b/test/CodeGen/R600/fmul.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK -; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK ; R600-CHECK: @fmul_f32 ; R600-CHECK: MUL_IEEE {{\** *}}{{T[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].W diff --git a/test/CodeGen/R600/fmul64.ll b/test/CodeGen/R600/fmul64.ll index 8a57d4a..d0ee5c8 100644 --- a/test/CodeGen/R600/fmul64.ll +++ b/test/CodeGen/R600/fmul64.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=r600 -mcpu=tahiti | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=tahiti -verify-machineinstrs | FileCheck %s ; CHECK: @fmul_f64 ; CHECK: V_MUL_F64 {{VGPR[0-9]+_VGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+}} diff --git a/test/CodeGen/R600/fmuladd.ll b/test/CodeGen/R600/fmuladd.ll index ac379f4..02cd8c1 100644 --- a/test/CodeGen/R600/fmuladd.ll +++ b/test/CodeGen/R600/fmuladd.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s ; CHECK: @fmuladd_f32 ; CHECK: V_MAD_F32 {{VGPR[0-9]+, VGPR[0-9]+, VGPR[0-9]+, VGPR[0-9]+}} diff --git a/test/CodeGen/R600/fp64_to_sint.ll b/test/CodeGen/R600/fp64_to_sint.ll index 42f9f34..185e21c 100644 --- a/test/CodeGen/R600/fp64_to_sint.ll +++ b/test/CodeGen/R600/fp64_to_sint.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=CHECK +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=CHECK ; CHECK: @fp64_to_sint ; CHECK: V_CVT_I32_F64_e32 diff --git a/test/CodeGen/R600/fp_to_sint.ll b/test/CodeGen/R600/fp_to_sint.ll index cecf0f9..8302b4f 100644 --- a/test/CodeGen/R600/fp_to_sint.ll +++ b/test/CodeGen/R600/fp_to_sint.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK -; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK ; R600-CHECK: @fp_to_sint_v2i32 ; R600-CHECK: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}} diff --git a/test/CodeGen/R600/fp_to_uint.ll b/test/CodeGen/R600/fp_to_uint.ll index 8d3f79a..77db43b 100644 --- a/test/CodeGen/R600/fp_to_uint.ll +++ b/test/CodeGen/R600/fp_to_uint.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK -; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK ; R600-CHECK: @fp_to_uint_v2i32 ; R600-CHECK: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}} diff --git a/test/CodeGen/R600/fpext.ll b/test/CodeGen/R600/fpext.ll index e02c19c..143ee79 100644 --- a/test/CodeGen/R600/fpext.ll +++ b/test/CodeGen/R600/fpext.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=CHECK +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=CHECK ; CHECK: @fpext ; CHECK: V_CVT_F64_F32_e32 diff --git a/test/CodeGen/R600/fptrunc.ll b/test/CodeGen/R600/fptrunc.ll index 2a10f63..20a8c00 100644 --- a/test/CodeGen/R600/fptrunc.ll +++ b/test/CodeGen/R600/fptrunc.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=CHECK +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=CHECK ; CHECK: @fptrunc ; CHECK: V_CVT_F32_F64_e32 diff --git a/test/CodeGen/R600/fsqrt.ll b/test/CodeGen/R600/fsqrt.ll index 2613805..81a38c0 100644 --- a/test/CodeGen/R600/fsqrt.ll +++ b/test/CodeGen/R600/fsqrt.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=r600 -mcpu=tahiti | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=tahiti -verify-machineinstrs | FileCheck %s ; CHECK: @fsqrt_f32 ; CHECK: V_SQRT_F32_e32 {{VGPR[0-9]+, VGPR[0-9]+}} diff --git a/test/CodeGen/R600/fsub.ll b/test/CodeGen/R600/fsub.ll index 850d3ee..4f74efb 100644 --- a/test/CodeGen/R600/fsub.ll +++ b/test/CodeGen/R600/fsub.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK -; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK ; R600-CHECK: @fsub_f32 ; R600-CHECK: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, -KC0[2].W diff --git a/test/CodeGen/R600/fsub64.ll b/test/CodeGen/R600/fsub64.ll index fa59dcc..56c5c0c 100644 --- a/test/CodeGen/R600/fsub64.ll +++ b/test/CodeGen/R600/fsub64.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=r600 -mcpu=tahiti | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=tahiti -verify-machineinstrs | FileCheck %s ; CHECK: @fsub_f64 ; CHECK: V_ADD_F64 {{VGPR[0-9]+_VGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+}}, 0, 0, 0, 0, 2 diff --git a/test/CodeGen/R600/imm.ll b/test/CodeGen/R600/imm.ll index 979efb0..c782646 100644 --- a/test/CodeGen/R600/imm.ll +++ b/test/CodeGen/R600/imm.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s ; Use a 64-bit value with lo bits that can be represented as an inline constant ; CHECK: @i64_imm_inline_lo diff --git a/test/CodeGen/R600/indirect-addressing-si.ll b/test/CodeGen/R600/indirect-addressing-si.ll index ba5de22..9f4a595 100644 --- a/test/CodeGen/R600/indirect-addressing-si.ll +++ b/test/CodeGen/R600/indirect-addressing-si.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s ; Tests for indirect addressing on SI, which is implemented using dynamic ; indexing of vectors. diff --git a/test/CodeGen/R600/llvm.AMDGPU.imax.ll b/test/CodeGen/R600/llvm.AMDGPU.imax.ll index 3e854c8..1336f4e 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.imax.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.imax.ll @@ -1,4 +1,4 @@ -;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s ;CHECK: V_MAX_I32_e32 diff --git a/test/CodeGen/R600/llvm.AMDGPU.imin.ll b/test/CodeGen/R600/llvm.AMDGPU.imin.ll index e227bf8..3435ea4 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.imin.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.imin.ll @@ -1,4 +1,4 @@ -;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s ;CHECK: V_MIN_I32_e32 diff --git a/test/CodeGen/R600/llvm.AMDGPU.trunc.ll b/test/CodeGen/R600/llvm.AMDGPU.trunc.ll index b9be9c6..e6bb2c4 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.trunc.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.trunc.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600-CHECK %s -; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s ; R600-CHECK: @amdgpu_trunc ; R600-CHECK: TRUNC T{{[0-9]+\.[XYZW]}}, KC0[2].Z diff --git a/test/CodeGen/R600/llvm.AMDGPU.umax.ll b/test/CodeGen/R600/llvm.AMDGPU.umax.ll index 7699c04..4cfa133 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.umax.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.umax.ll @@ -1,4 +1,4 @@ -;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s ;CHECK: V_MAX_U32_e32 diff --git a/test/CodeGen/R600/llvm.AMDGPU.umin.ll b/test/CodeGen/R600/llvm.AMDGPU.umin.ll index a911ad9..14af051 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.umin.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.umin.ll @@ -1,4 +1,4 @@ -;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s ;CHECK: V_MIN_U32_e32 diff --git a/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll b/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll index e45722c..0438ecc 100644 --- a/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll +++ b/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll @@ -1,4 +1,4 @@ -;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s ;CHECK: S_MOV_B32 ;CHECK-NEXT: V_INTERP_MOV_F32 diff --git a/test/CodeGen/R600/llvm.SI.imageload.ll b/test/CodeGen/R600/llvm.SI.imageload.ll index 5cf9e0a..29c6ff3 100644 --- a/test/CodeGen/R600/llvm.SI.imageload.ll +++ b/test/CodeGen/R600/llvm.SI.imageload.ll @@ -1,4 +1,4 @@ -;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s ;CHECK-DAG: IMAGE_LOAD {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 15, 0, 0, -1 ;CHECK-DAG: IMAGE_LOAD_MIP {{VGPR[0-9]+_VGPR[0-9]+}}, 3, 0, 0, 0 diff --git a/test/CodeGen/R600/llvm.SI.resinfo.ll b/test/CodeGen/R600/llvm.SI.resinfo.ll index 9b8d161..b41cccf 100644 --- a/test/CodeGen/R600/llvm.SI.resinfo.ll +++ b/test/CodeGen/R600/llvm.SI.resinfo.ll @@ -1,4 +1,4 @@ -;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s ;CHECK: IMAGE_GET_RESINFO {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 15, 0, 0, -1 ;CHECK: IMAGE_GET_RESINFO {{VGPR[0-9]+_VGPR[0-9]+}}, 3, 0, 0, 0 diff --git a/test/CodeGen/R600/llvm.SI.sample.ll b/test/CodeGen/R600/llvm.SI.sample.ll index 2651b99..633ff0a 100644 --- a/test/CodeGen/R600/llvm.SI.sample.ll +++ b/test/CodeGen/R600/llvm.SI.sample.ll @@ -1,4 +1,4 @@ -;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s ;CHECK-DAG: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 15 ;CHECK-DAG: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+}}, 3 diff --git a/test/CodeGen/R600/llvm.SI.sampled.ll b/test/CodeGen/R600/llvm.SI.sampled.ll index d43b378..33c5a8c 100644 --- a/test/CodeGen/R600/llvm.SI.sampled.ll +++ b/test/CodeGen/R600/llvm.SI.sampled.ll @@ -1,4 +1,4 @@ -;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s ;CHECK-DAG: IMAGE_SAMPLE_D {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 15 ;CHECK-DAG: IMAGE_SAMPLE_D {{VGPR[0-9]+_VGPR[0-9]+}}, 3 diff --git a/test/CodeGen/R600/llvm.SI.tbuffer.store.ll b/test/CodeGen/R600/llvm.SI.tbuffer.store.ll index 92d16c5..3f088a2 100644 --- a/test/CodeGen/R600/llvm.SI.tbuffer.store.ll +++ b/test/CodeGen/R600/llvm.SI.tbuffer.store.ll @@ -1,4 +1,4 @@ -;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s ;CHECK_LABEL: @test1 ;CHECK: TBUFFER_STORE_FORMAT_XYZW {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 32, -1, 0, -1, 0, 14, 4, {{VGPR[0-9]+}}, {{SGPR[0-9]+_SGPR[0-9]+_SGPR[0-9]+_SGPR[0-9]+}}, -1, 0, 0 diff --git a/test/CodeGen/R600/llvm.SI.tid.ll b/test/CodeGen/R600/llvm.SI.tid.ll index 238d9f2..fe17304 100644 --- a/test/CodeGen/R600/llvm.SI.tid.ll +++ b/test/CodeGen/R600/llvm.SI.tid.ll @@ -1,4 +1,4 @@ -;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s ;CHECK: V_MBCNT_LO_U32_B32_e64 ;CHECK: V_MBCNT_HI_U32_B32_e32 diff --git a/test/CodeGen/R600/llvm.floor.ll b/test/CodeGen/R600/llvm.floor.ll index ce011f7..f7071cd 100644 --- a/test/CodeGen/R600/llvm.floor.ll +++ b/test/CodeGen/R600/llvm.floor.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK -; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK ; R600-CHECK: @f32 ; R600-CHECK: FLOOR diff --git a/test/CodeGen/R600/llvm.rint.ll b/test/CodeGen/R600/llvm.rint.ll index c1bbc23..c174b33 100644 --- a/test/CodeGen/R600/llvm.rint.ll +++ b/test/CodeGen/R600/llvm.rint.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK -; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK ; R600-CHECK: @f32 ; R600-CHECK: RNDNE diff --git a/test/CodeGen/R600/load.ll b/test/CodeGen/R600/load.ll index 8829ff5..f8d5e11 100644 --- a/test/CodeGen/R600/load.ll +++ b/test/CodeGen/R600/load.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600-CHECK %s ; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck --check-prefix=R600-CHECK %s -; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck --check-prefix=SI-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s ;===------------------------------------------------------------------------===; ; GLOBAL ADDRESS SPACE diff --git a/test/CodeGen/R600/load.vec.ll b/test/CodeGen/R600/load.vec.ll index 8cba0b6..413738e5 100644 --- a/test/CodeGen/R600/load.vec.ll +++ b/test/CodeGen/R600/load.vec.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s -; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck --check-prefix=SI-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s ; load a v2i32 value from the global address space. ; EG-CHECK: @load_v2i32 diff --git a/test/CodeGen/R600/load64.ll b/test/CodeGen/R600/load64.ll index 3b4a8f8..0c158bb 100644 --- a/test/CodeGen/R600/load64.ll +++ b/test/CodeGen/R600/load64.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=r600 -mcpu=tahiti | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=tahiti -verify-machineinstrs | FileCheck %s ; load a f64 value from the global address space. ; CHECK: @load_f64 diff --git a/test/CodeGen/R600/local-memory-two-objects.ll b/test/CodeGen/R600/local-memory-two-objects.ll index fcf3577..99a8651 100644 --- a/test/CodeGen/R600/local-memory-two-objects.ll +++ b/test/CodeGen/R600/local-memory-two-objects.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s -; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s @local_memory_two_objects.local_mem0 = internal addrspace(3) unnamed_addr global [4 x i32] zeroinitializer, align 4 @local_memory_two_objects.local_mem1 = internal addrspace(3) unnamed_addr global [4 x i32] zeroinitializer, align 4 diff --git a/test/CodeGen/R600/local-memory.ll b/test/CodeGen/R600/local-memory.ll index bd0d59c..b0b00bb 100644 --- a/test/CodeGen/R600/local-memory.ll +++ b/test/CodeGen/R600/local-memory.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s -; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s @local_memory.local_mem = internal addrspace(3) unnamed_addr global [16 x i32] zeroinitializer, align 4 diff --git a/test/CodeGen/R600/lshl.ll b/test/CodeGen/R600/lshl.ll index 806e681..06736c0 100644 --- a/test/CodeGen/R600/lshl.ll +++ b/test/CodeGen/R600/lshl.ll @@ -1,4 +1,4 @@ -;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s ;CHECK: V_LSHL_B32_e64 VGPR{{[0-9]}}, SGPR{{[0-9]}}, 1 diff --git a/test/CodeGen/R600/lshr.ll b/test/CodeGen/R600/lshr.ll index cfbcc34..5b1620b 100644 --- a/test/CodeGen/R600/lshr.ll +++ b/test/CodeGen/R600/lshr.ll @@ -1,4 +1,4 @@ -;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s ;CHECK: V_LSHR_B32_e64 {{VGPR[0-9]}}, SGPR{{[0-9]}}, 1 diff --git a/test/CodeGen/R600/mad_int24.ll b/test/CodeGen/R600/mad_int24.ll index ce42ae7..df063ec 100644 --- a/test/CodeGen/R600/mad_int24.ll +++ b/test/CodeGen/R600/mad_int24.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG-CHECK ; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=CM-CHECK -; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK ; EG-CHECK: @i32_mad24 ; Signed 24-bit multiply is not supported on pre-Cayman GPUs. diff --git a/test/CodeGen/R600/mad_uint24.ll b/test/CodeGen/R600/mad_uint24.ll index 00aa64a..7fba50c 100644 --- a/test/CodeGen/R600/mad_uint24.ll +++ b/test/CodeGen/R600/mad_uint24.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG-CHECK ; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG-CHECK -; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK ; EG-CHECK: @u32_mad24 ; EG-CHECK: MULADD_UINT24 {{[* ]*}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, KC0[2].W, KC0[3].X diff --git a/test/CodeGen/R600/mul.ll b/test/CodeGen/R600/mul.ll index 18a17b6..17222e7 100644 --- a/test/CodeGen/R600/mul.ll +++ b/test/CodeGen/R600/mul.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s -; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s ; mul24 and mad24 are affected diff --git a/test/CodeGen/R600/mul_int24.ll b/test/CodeGen/R600/mul_int24.ll index 16ae760..66a1a9e 100644 --- a/test/CodeGen/R600/mul_int24.ll +++ b/test/CodeGen/R600/mul_int24.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG-CHECK ; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=CM-CHECK -; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK ; EG-CHECK: @i32_mul24 ; Signed 24-bit multiply is not supported on pre-Cayman GPUs. diff --git a/test/CodeGen/R600/mul_uint24.ll b/test/CodeGen/R600/mul_uint24.ll index b1a7f94..2244bbd 100644 --- a/test/CodeGen/R600/mul_uint24.ll +++ b/test/CodeGen/R600/mul_uint24.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG-CHECK ; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG-CHECK -; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK ; EG-CHECK: @u32_mul24 ; EG-CHECK: MUL_UINT24 {{[* ]*}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, KC0[2].W diff --git a/test/CodeGen/R600/mulhu.ll b/test/CodeGen/R600/mulhu.ll index eb379d1..6938277 100644 --- a/test/CodeGen/R600/mulhu.ll +++ b/test/CodeGen/R600/mulhu.ll @@ -1,4 +1,4 @@ -;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s ;CHECK: V_MOV_B32_e32 VGPR{{[0-9]+}}, -1431655765 ;CHECK: V_MUL_HI_U32 VGPR0, {{[SV]GPR[0-9]+}}, {{VGPR[0-9]+}} diff --git a/test/CodeGen/R600/or.ll b/test/CodeGen/R600/or.ll index 4a4e892..3db892a 100644 --- a/test/CodeGen/R600/or.ll +++ b/test/CodeGen/R600/or.ll @@ -1,5 +1,5 @@ ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s -;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s ; EG-CHECK: @or_v2i32 ; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} diff --git a/test/CodeGen/R600/rotr.ll b/test/CodeGen/R600/rotr.ll index c3995b6..c01b057 100644 --- a/test/CodeGen/R600/rotr.ll +++ b/test/CodeGen/R600/rotr.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood -o - | FileCheck --check-prefix=R600-CHECK %s -; RUN: llc < %s -march=r600 -mcpu=SI -o - | FileCheck --check-prefix=SI-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s ; R600-CHECK: @rotr ; R600-CHECK: BIT_ALIGN_INT diff --git a/test/CodeGen/R600/seto.ll b/test/CodeGen/R600/seto.ll index 19716f8..72007e6 100644 --- a/test/CodeGen/R600/seto.ll +++ b/test/CodeGen/R600/seto.ll @@ -1,4 +1,4 @@ -;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s ;CHECK: V_CMP_O_F32_e64 SGPR0_SGPR1, {{[SV]GPR[0-9]+, [SV]GPR[0-9]+}}, 0, 0, 0, 0 diff --git a/test/CodeGen/R600/setuo.ll b/test/CodeGen/R600/setuo.ll index 929dbb1..a9cadfa 100644 --- a/test/CodeGen/R600/setuo.ll +++ b/test/CodeGen/R600/setuo.ll @@ -1,4 +1,4 @@ -;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s ;CHECK: V_CMP_U_F32_e64 SGPR0_SGPR1, {{[SV]GPR[0-9]+, [SV]GPR[0-9]+}}, 0, 0, 0, 0 diff --git a/test/CodeGen/R600/sgpr-copy.ll b/test/CodeGen/R600/sgpr-copy.ll index 67837a3..768ffa6 100644 --- a/test/CodeGen/R600/sgpr-copy.ll +++ b/test/CodeGen/R600/sgpr-copy.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s ; This test checks that no VGPR to SGPR copies are created by the register ; allocator. diff --git a/test/CodeGen/R600/shl.ll b/test/CodeGen/R600/shl.ll index d99e325..7e8a591 100644 --- a/test/CodeGen/R600/shl.ll +++ b/test/CodeGen/R600/shl.ll @@ -1,5 +1,5 @@ ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s -;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s ;EG-CHECK: @shl_v2i32 ;EG-CHECK: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} diff --git a/test/CodeGen/R600/short-args.ll b/test/CodeGen/R600/short-args.ll index 20d0ae4..8882978 100644 --- a/test/CodeGen/R600/short-args.ll +++ b/test/CodeGen/R600/short-args.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG-CHECK ; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG-CHECK -; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK ; EG-CHECK: @i8_arg ; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z diff --git a/test/CodeGen/R600/si-lod-bias.ll b/test/CodeGen/R600/si-lod-bias.ll index 9371272..d2fb8ed 100644 --- a/test/CodeGen/R600/si-lod-bias.ll +++ b/test/CodeGen/R600/si-lod-bias.ll @@ -1,4 +1,4 @@ -;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s ; This shader has the potential to generated illeagal VGPR to SGPR copies if ; the wrong register class is used for the REG_SEQUENCE instructions. diff --git a/test/CodeGen/R600/si-vector-hang.ll b/test/CodeGen/R600/si-vector-hang.ll index 226e5db..093234f 100644 --- a/test/CodeGen/R600/si-vector-hang.ll +++ b/test/CodeGen/R600/si-vector-hang.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s ; CHECK: @test_8_min_char ; CHECK: BUFFER_STORE_BYTE diff --git a/test/CodeGen/R600/sign_extend.ll b/test/CodeGen/R600/sign_extend.ll index e4ef534..1212cee 100644 --- a/test/CodeGen/R600/sign_extend.ll +++ b/test/CodeGen/R600/sign_extend.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s ; CHECK: V_ASHR define void @test(i64 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) { diff --git a/test/CodeGen/R600/sint_to_fp.ll b/test/CodeGen/R600/sint_to_fp.ll index 4e88494..9241799 100644 --- a/test/CodeGen/R600/sint_to_fp.ll +++ b/test/CodeGen/R600/sint_to_fp.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK -; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK ; R600-CHECK: @sint_to_fp_v2i32 ; R600-CHECK-DAG: INT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[2].W diff --git a/test/CodeGen/R600/sint_to_fp64.ll b/test/CodeGen/R600/sint_to_fp64.ll index 37f67c9..5abc9d1 100644 --- a/test/CodeGen/R600/sint_to_fp64.ll +++ b/test/CodeGen/R600/sint_to_fp64.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=CHECK +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=CHECK ; CHECK: @sint_to_fp64 ; CHECK: V_CVT_F64_I32_e32 diff --git a/test/CodeGen/R600/sra.ll b/test/CodeGen/R600/sra.ll index 5220a96..fbf4fec 100644 --- a/test/CodeGen/R600/sra.ll +++ b/test/CodeGen/R600/sra.ll @@ -1,5 +1,5 @@ ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s -;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s ;EG-CHECK: @ashr_v2i32 ;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} diff --git a/test/CodeGen/R600/srl.ll b/test/CodeGen/R600/srl.ll index d1dcd7f..62d9601 100644 --- a/test/CodeGen/R600/srl.ll +++ b/test/CodeGen/R600/srl.ll @@ -1,5 +1,5 @@ ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s -;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s ;EG-CHECK: @lshr_v2i32 ;EG-CHECK: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} diff --git a/test/CodeGen/R600/store.ll b/test/CodeGen/R600/store.ll index f70faa0..a4c025a 100644 --- a/test/CodeGen/R600/store.ll +++ b/test/CodeGen/R600/store.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s ; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck --check-prefix=CM-CHECK %s -; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s ;===------------------------------------------------------------------------===; ; Global Address Space diff --git a/test/CodeGen/R600/sub.ll b/test/CodeGen/R600/sub.ll index c7fed03..2f6d32df 100644 --- a/test/CodeGen/R600/sub.ll +++ b/test/CodeGen/R600/sub.ll @@ -1,5 +1,5 @@ ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s -;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s ;EG-CHECK: @test2 ;EG-CHECK: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} diff --git a/test/CodeGen/R600/trunc.ll b/test/CodeGen/R600/trunc.ll index d94d4fe..1fbe720 100644 --- a/test/CodeGen/R600/trunc.ll +++ b/test/CodeGen/R600/trunc.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI %s +; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG %s diff --git a/test/CodeGen/R600/udiv.ll b/test/CodeGen/R600/udiv.ll index 08fe2ef..19c0185 100644 --- a/test/CodeGen/R600/udiv.ll +++ b/test/CodeGen/R600/udiv.ll @@ -1,5 +1,5 @@ ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s -;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s ;The code generated by udiv is long and complex and may frequently change. ;The goal of this test is to make sure the ISel doesn't fail when it gets diff --git a/test/CodeGen/R600/uint_to_fp.ll b/test/CodeGen/R600/uint_to_fp.ll index faac77a..3f6e4c8 100644 --- a/test/CodeGen/R600/uint_to_fp.ll +++ b/test/CodeGen/R600/uint_to_fp.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK -; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK ; R600-CHECK: @uint_to_fp_v2i32 ; R600-CHECK-DAG: UINT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[2].W diff --git a/test/CodeGen/R600/urecip.ll b/test/CodeGen/R600/urecip.ll index dad02dd..e808e3d 100644 --- a/test/CodeGen/R600/urecip.ll +++ b/test/CodeGen/R600/urecip.ll @@ -1,4 +1,4 @@ -;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s ;CHECK: V_RCP_IFLAG_F32_e32 diff --git a/test/CodeGen/R600/urem.ll b/test/CodeGen/R600/urem.ll index cf3474c..8045145 100644 --- a/test/CodeGen/R600/urem.ll +++ b/test/CodeGen/R600/urem.ll @@ -1,5 +1,5 @@ ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s -;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s ;The code generated by urem is long and complex and may frequently change. ;The goal of this test is to make sure the ISel doesn't fail when it gets diff --git a/test/CodeGen/R600/vselect.ll b/test/CodeGen/R600/vselect.ll index ee17e0f..dca7b06 100644 --- a/test/CodeGen/R600/vselect.ll +++ b/test/CodeGen/R600/vselect.ll @@ -1,5 +1,5 @@ ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s -;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck --check-prefix=SI-CHECK %s +;RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s ;EG-CHECK: @test_select_v2i32 ;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} diff --git a/test/CodeGen/R600/work-item-intrinsics.ll b/test/CodeGen/R600/work-item-intrinsics.ll index d5fe79f..d2acc5a 100644 --- a/test/CodeGen/R600/work-item-intrinsics.ll +++ b/test/CodeGen/R600/work-item-intrinsics.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600-CHECK %s -; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck --check-prefix=SI-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s ; R600-CHECK: @ngroups_x ; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] diff --git a/test/CodeGen/R600/xor.ll b/test/CodeGen/R600/xor.ll index fa5cb20..a337bdf 100644 --- a/test/CodeGen/R600/xor.ll +++ b/test/CodeGen/R600/xor.ll @@ -1,5 +1,5 @@ ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s -;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s ;EG-CHECK: @xor_v2i32 ;EG-CHECK: XOR_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} diff --git a/test/CodeGen/R600/zero_extend.ll b/test/CodeGen/R600/zero_extend.ll index e0b9c31..e2c7474 100644 --- a/test/CodeGen/R600/zero_extend.ll +++ b/test/CodeGen/R600/zero_extend.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK -; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK ; R600-CHECK: @test ; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW |