diff options
Diffstat (limited to 'test/MC/Disassembler/AArch64/neon-instructions.txt')
| -rw-r--r-- | test/MC/Disassembler/AArch64/neon-instructions.txt | 195 |
1 files changed, 97 insertions, 98 deletions
diff --git a/test/MC/Disassembler/AArch64/neon-instructions.txt b/test/MC/Disassembler/AArch64/neon-instructions.txt index 863730a..3590668 100644 --- a/test/MC/Disassembler/AArch64/neon-instructions.txt +++ b/test/MC/Disassembler/AArch64/neon-instructions.txt @@ -1,4 +1,5 @@ # RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -disassemble < %s | FileCheck %s #------------------------------------------------------------------------------ # Vector Integer Add/Sub @@ -87,7 +88,7 @@ # Vector Bitwise OR - immedidate #------------------------------------------------------------------------------ # CHECK: movi v31.4s, #0xff, lsl #24 -# CHECK: mvni v0.2s, #0x0 +# CHECK: mvni v0.2s, #{{0x0|0}} # CHECK: bic v15.4h, #0xf, lsl #8 # CHECK: orr v16.8h, #0x1f 0xff 0x67 0x07 0x4f @@ -132,10 +133,8 @@ # Vector Move - register #------------------------------------------------------------------------------ -# FIXME: these should print as "mov", but TableGen can't handle it. - -# CHECK: orr v1.16b, v15.16b, v15.16b -# CHECK: orr v25.8b, v4.8b, v4.8b +# CHECK: mov v1.16b, v15.16b +# CHECK: mov v25.8b, v4.8b 0xe1 0x1d 0xaf 0x4e 0x99 0x1c 0xa4 0x0e @@ -246,31 +245,31 @@ #---------------------------------------------------------------------- # Vector Compare Mask Equal to Zero (Integer) #---------------------------------------------------------------------- -# CHECK: cmeq v31.16b, v15.16b, #0x0 +# CHECK: cmeq v31.16b, v15.16b, #{{0x0|0}} 0xff 0x99 0x20 0x4e #---------------------------------------------------------------------- # Vector Compare Mask Greater Than or Equal to Zero (Signed Integer) #---------------------------------------------------------------------- -# CHECK: cmge v3.8b, v15.8b, #0x0 +# CHECK: cmge v3.8b, v15.8b, #{{0x0|0}} 0xe3 0x89 0x20 0x2e #---------------------------------------------------------------------- # Vector Compare Mask Greater Than Zero (Signed Integer) #---------------------------------------------------------------------- -# CHECK: cmgt v22.2s, v9.2s, #0x0 +# CHECK: cmgt v22.2s, v9.2s, #{{0x0|0}} 0x36 0x89 0xa0 0x0e #---------------------------------------------------------------------- # Vector Compare Mask Less Than or Equal To Zero (Signed Integer) #---------------------------------------------------------------------- -# CHECK: cmle v5.2d, v14.2d, #0x0 +# CHECK: cmle v5.2d, v14.2d, #{{0x0|0}} 0xc5 0x99 0xe0 0x6e #---------------------------------------------------------------------- # Vector Compare Mask Less Than Zero (Signed Integer) #---------------------------------------------------------------------- -# CHECK: cmlt v13.8h, v11.8h, #0x0 +# CHECK: cmlt v13.8h, v11.8h, #{{0x0|0}} 0x6d 0xa9 0x60 0x4e #---------------------------------------------------------------------- @@ -1559,7 +1558,7 @@ #---------------------------------------------------------------------- # Scalar Compare Bitwise Equal To Zero #---------------------------------------------------------------------- -# CHECK: cmeq d20, d21, #0x0 +# CHECK: cmeq d20, d21, #{{0x0|0}} 0xb4,0x9a,0xe0,0x5e #---------------------------------------------------------------------- @@ -1578,7 +1577,7 @@ #---------------------------------------------------------------------- # Scalar Compare Signed Greather Than Or Equal To Zero #---------------------------------------------------------------------- -# CHECK: cmge d20, d21, #0x0 +# CHECK: cmge d20, d21, #{{0x0|0}} 0xb4,0x8a,0xe0,0x7e #---------------------------------------------------------------------- @@ -1596,19 +1595,19 @@ #---------------------------------------------------------------------- # Scalar Compare Signed Greater Than Zero #---------------------------------------------------------------------- -# CHECK: cmgt d20, d21, #0x0 +# CHECK: cmgt d20, d21, #{{0x0|0}} 0xb4,0x8a,0xe0,0x5e #---------------------------------------------------------------------- # Scalar Compare Signed Less Than Or Equal To Zero #---------------------------------------------------------------------- -# CHECK: cmle d20, d21, #0x0 +# CHECK: cmle d20, d21, #{{0x0|0}} 0xb4,0x9a,0xe0,0x7e #---------------------------------------------------------------------- # Scalar Compare Less Than Zero #---------------------------------------------------------------------- -# CHECK: cmlt d20, d21, #0x0 +# CHECK: cmlt d20, d21, #{{0x0|0}} 0xb4,0xaa,0xe0,0x5e #---------------------------------------------------------------------- @@ -2008,34 +2007,34 @@ #---------------------------------------------------------------------- # Vector load/store multiple N-element structure #---------------------------------------------------------------------- -# CHECK: ld1 {v0.16b}, [x0] -# CHECK: ld1 {v15.8h, v16.8h}, [x15] -# CHECK: ld1 {v31.4s, v0.4s, v1.4s}, [sp] -# CHECK: ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] +# CHECK: ld1 { v0.16b }, [x0] +# CHECK: ld1 { v15.8h, v16.8h }, [x15] +# CHECK: ld1 { v31.4s, v0.4s, v1.4s }, [sp] +# CHECK: ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] 0x00,0x70,0x40,0x4c 0xef,0xa5,0x40,0x4c 0xff,0x6b,0x40,0x4c 0x00,0x2c,0x40,0x4c -# CHECK: ld2 {v0.8b, v1.8b}, [x0] -# CHECK: ld3 {v15.4h, v16.4h, v17.4h}, [x15] -# CHECK: ld4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] +# CHECK: ld2 { v0.8b, v1.8b }, [x0] +# CHECK: ld3 { v15.4h, v16.4h, v17.4h }, [x15] +# CHECK: ld4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] 0x00,0x80,0x40,0x0c 0xef,0x45,0x40,0x0c 0xff,0x0b,0x40,0x0c -# CHECK: st1 {v0.16b}, [x0] -# CHECK: st1 {v15.8h, v16.8h}, [x15] -# CHECK: st1 {v31.4s, v0.4s, v1.4s}, [sp] -# CHECK: st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] +# CHECK: st1 { v0.16b }, [x0] +# CHECK: st1 { v15.8h, v16.8h }, [x15] +# CHECK: st1 { v31.4s, v0.4s, v1.4s }, [sp] +# CHECK: st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] 0x00,0x70,0x00,0x4c 0xef,0xa5,0x00,0x4c 0xff,0x6b,0x00,0x4c 0x00,0x2c,0x00,0x4c -# CHECK: st2 {v0.8b, v1.8b}, [x0] -# CHECK: st3 {v15.4h, v16.4h, v17.4h}, [x15] -# CHECK: st4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] +# CHECK: st2 { v0.8b, v1.8b }, [x0] +# CHECK: st3 { v15.4h, v16.4h, v17.4h }, [x15] +# CHECK: st4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] 0x00,0x80,0x00,0x0c 0xef,0x45,0x00,0x0c 0xff,0x0b,0x00,0x0c @@ -2043,35 +2042,35 @@ #---------------------------------------------------------------------- # Vector load/store multiple N-element structure (post-index) #---------------------------------------------------------------------- -# CHECK: ld1 {v15.8h}, [x15], x2 -# CHECK: ld1 {v31.4s, v0.4s}, [sp], #32 -# CHECK: ld1 {v0.2d, v1.2d, v2.2d}, [x0], #48 -# CHECK: ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 +# CHECK: ld1 { v15.8h }, [x15], x2 +# CHECK: ld1 { v31.4s, v0.4s }, [sp], #32 +# CHECK: ld1 { v0.2d, v1.2d, v2.2d }, [x0], #48 +# CHECK: ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3 0xef,0x75,0xc2,0x4c 0xff,0xab,0xdf,0x4c 0x00,0x6c,0xdf,0x4c 0x00,0x20,0xc3,0x0c -# CHECK: ld2 {v0.16b, v1.16b}, [x0], x1 -# CHECK: ld3 {v15.8h, v16.8h, v17.8h}, [x15], x2 -# CHECK: ld4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 +# CHECK: ld2 { v0.16b, v1.16b }, [x0], x1 +# CHECK: ld3 { v15.8h, v16.8h, v17.8h }, [x15], x2 +# CHECK: ld4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64 0x00,0x80,0xc1,0x4c 0xef,0x45,0xc2,0x4c 0xff,0x0b,0xdf,0x4c -# CHECK: st1 {v15.8h}, [x15], x2 -# CHECK: st1 {v31.4s, v0.4s}, [sp], #32 -# CHECK: st1 {v0.2d, v1.2d, v2.2d}, [x0], #48 -# CHECK: st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 +# CHECK: st1 { v15.8h }, [x15], x2 +# CHECK: st1 { v31.4s, v0.4s }, [sp], #32 +# CHECK: st1 { v0.2d, v1.2d, v2.2d }, [x0], #48 +# CHECK: st1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3 0xef,0x75,0x82,0x4c 0xff,0xab,0x9f,0x4c 0x00,0x6c,0x9f,0x4c 0x00,0x20,0x83,0x0c -# CHECK: st2 {v0.16b, v1.16b}, [x0], x1 -# CHECK: st3 {v15.8h, v16.8h, v17.8h}, [x15], x2 -# CHECK: st4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 +# CHECK: st2 { v0.16b, v1.16b }, [x0], x1 +# CHECK: st3 { v15.8h, v16.8h, v17.8h }, [x15], x2 +# CHECK: st4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64 0x00,0x80,0x81,0x4c 0xef,0x45,0x82,0x4c 0xff,0x0b,0x9f,0x4c @@ -2080,14 +2079,14 @@ # Vector load single N-element structure to all lane of N # consecutive registers (N = 1,2,3,4) #---------------------------------------------------------------------- -# CHECK: ld1r {v0.16b}, [x0] -# CHECK: ld1r {v15.8h}, [x15] -# CHECK: ld2r {v31.4s, v0.4s}, [sp] -# CHECK: ld2r {v0.2d, v1.2d}, [x0] -# CHECK: ld3r {v0.8b, v1.8b, v2.8b}, [x0] -# CHECK: ld3r {v15.4h, v16.4h, v17.4h}, [x15] -# CHECK: ld4r {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] -# CHECK: ld4r {v31.1d, v0.1d, v1.1d, v2.1d}, [sp] +# CHECK: ld1r { v0.16b }, [x0] +# CHECK: ld1r { v15.8h }, [x15] +# CHECK: ld2r { v31.4s, v0.4s }, [sp] +# CHECK: ld2r { v0.2d, v1.2d }, [x0] +# CHECK: ld3r { v0.8b, v1.8b, v2.8b }, [x0] +# CHECK: ld3r { v15.4h, v16.4h, v17.4h }, [x15] +# CHECK: ld4r { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] +# CHECK: ld4r { v31.1d, v0.1d, v1.1d, v2.1d }, [sp] 0x00,0xc0,0x40,0x4d 0xef,0xc5,0x40,0x4d 0xff,0xcb,0x60,0x4d @@ -2101,14 +2100,14 @@ # Vector load/store single N-element structure to/from one lane of N # consecutive registers (N = 1,2,3,4) #---------------------------------------------------------------------- -# CHECK: ld1 {v0.b}[9], [x0] -# CHECK: ld2 {v15.h, v16.h}[7], [x15] -# CHECK: ld3 {v31.s, v0.s, v1.s}[3], [sp] -# CHECK: ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0] -# CHECK: st1 {v0.d}[1], [x0] -# CHECK: st2 {v31.s, v0.s}[3], [sp] -# CHECK: st3 {v15.h, v16.h, v17.h}[7], [x15] -# CHECK: st4 {v0.b, v1.b, v2.b, v3.b}[9], [x0] +# CHECK: ld1 { v0.b }[9], [x0] +# CHECK: ld2 { v15.h, v16.h }[7], [x15] +# CHECK: ld3 { v31.s, v0.s, v1.s }[3], [sp] +# CHECK: ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0] +# CHECK: st1 { v0.d }[1], [x0] +# CHECK: st2 { v31.s, v0.s }[3], [sp] +# CHECK: st3 { v15.h, v16.h, v17.h }[7], [x15] +# CHECK: st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0] 0x00,0x04,0x40,0x4d 0xef,0x59,0x60,0x4d 0xff,0xb3,0x40,0x4d @@ -2122,14 +2121,14 @@ # Post-index of vector load single N-element structure to all lane of N # consecutive registers (N = 1,2,3,4) #---------------------------------------------------------------------- -# CHECK: ld1r {v0.16b}, [x0], #1 -# CHECK: ld1r {v15.8h}, [x15], #2 -# CHECK: ld2r {v31.4s, v0.4s}, [sp], #8 -# CHECK: ld2r {v0.2d, v1.2d}, [x0], #16 -# CHECK: ld3r {v0.8b, v1.8b, v2.8b}, [x0], #3 -# CHECK: ld3r {v15.4h, v16.4h, v17.4h}, [x15], #6 -# CHECK: ld4r {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], x30 -# CHECK: ld4r {v31.1d, v0.1d, v1.1d, v2.1d}, [sp], x7 +# CHECK: ld1r { v0.16b }, [x0], #1 +# CHECK: ld1r { v15.8h }, [x15], #2 +# CHECK: ld2r { v31.4s, v0.4s }, [sp], #8 +# CHECK: ld2r { v0.2d, v1.2d }, [x0], #16 +# CHECK: ld3r { v0.8b, v1.8b, v2.8b }, [x0], #3 +# CHECK: ld3r { v15.4h, v16.4h, v17.4h }, [x15], #6 +# CHECK: ld4r { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], x30 +# CHECK: ld4r { v31.1d, v0.1d, v1.1d, v2.1d }, [sp], x7 0x00,0xc0,0xdf,0x4d 0xef,0xc5,0xdf,0x4d 0xff,0xcb,0xff,0x4d @@ -2143,15 +2142,15 @@ # Post-index of vector load/store single N-element structure to/from # one lane of N consecutive registers (N = 1,2,3,4) #---------------------------------------------------------------------- -# CHECK: ld1 {v0.b}[9], [x0], #1 -# CHECK: ld2 {v15.h, v16.h}[7], [x15], #4 -# CHECK: ld3 {v31.s, v0.s, v1.s}[3], [sp], x3 -# CHECK: ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0], #32 -# CHECK: ld4 {v0.h, v1.h, v2.h, v3.h}[7], [x0], x0 -# CHECK: st1 {v0.d}[1], [x0], #8 -# CHECK: st2 {v31.s, v0.s}[3], [sp], #8 -# CHECK: st3 {v15.h, v16.h, v17.h}[7], [x15], #6 -# CHECK: st4 {v0.b, v1.b, v2.b, v3.b}[9], [x0], x5 +# CHECK: ld1 { v0.b }[9], [x0], #1 +# CHECK: ld2 { v15.h, v16.h }[7], [x15], #4 +# CHECK: ld3 { v31.s, v0.s, v1.s }[3], [sp], x3 +# CHECK: ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], #32 +# CHECK: ld4 { v0.h, v1.h, v2.h, v3.h }[7], [x0], x0 +# CHECK: st1 { v0.d }[1], [x0], #8 +# CHECK: st2 { v31.s, v0.s }[3], [sp], #8 +# CHECK: st3 { v15.h, v16.h, v17.h }[7], [x15], #6 +# CHECK: st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0], x5 0x00,0x04,0xdf,0x4d 0xef,0x59,0xff,0x4d 0xff,0xb3,0xc3,0x4d @@ -2167,8 +2166,8 @@ #---------------------------------------------------------------------- 0x20,0x18,0x02,0x2e 0x20,0x18,0x02,0x6e -# CHECK: ext v0.8b, v1.8b, v2.8b, #0x3 -# CHECK: ext v0.16b, v1.16b, v2.16b, #0x3 +# CHECK: ext v0.8b, v1.8b, v2.8b, #{{0x3|3}} +# CHECK: ext v0.16b, v1.16b, v2.16b, #{{0x3|3}} #---------------------------------------------------------------------- # unzip with 3 same vectors to get primary result @@ -2481,10 +2480,10 @@ #---------------------------------------------------------------------- #Duplicate element (scalar) #---------------------------------------------------------------------- -# CHECK: dup b0, v0.b[15] -# CHECK: dup h2, v31.h[5] -# CHECK: dup s17, v2.s[2] -# CHECK: dup d6, v12.d[1] +# CHECK: {{dup|mov}} b0, v0.b[15] +# CHECK: {{dup|mov}} h2, v31.h[5] +# CHECK: {{dup|mov}} s17, v2.s[2] +# CHECK: {{dup|mov}} d6, v12.d[1] 0x00 0x04 0x1f 0x5e 0xe2 0x07 0x16 0x5e 0x51 0x04 0x14 0x5e @@ -2497,37 +2496,37 @@ 0xf0,0x23,0x02,0x0e 0x20,0x40,0x02,0x0e 0xf0,0x62,0x02,0x0e -# CHECK: tbl v0.8b, {v1.16b}, v2.8b -# CHECK: tbl v16.8b, {v31.16b, v0.16b}, v2.8b -# CHECK: tbl v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b -# CHECK: tbl v16.8b, {v23.16b, v24.16b, v25.16b, v26.16b}, v2.8b +# CHECK: tbl v0.8b, { v1.16b }, v2.8b +# CHECK: tbl v16.8b, { v31.16b, v0.16b }, v2.8b +# CHECK: tbl v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b +# CHECK: tbl v16.8b, { v23.16b, v24.16b, v25.16b, v26.16b }, v2.8b 0x20,0x00,0x02,0x4e 0xf0,0x23,0x02,0x4e 0x20,0x40,0x02,0x4e 0xe0,0x63,0x02,0x4e -# CHECK: tbl v0.16b, {v1.16b}, v2.16b -# CHECK: tbl v16.16b, {v31.16b, v0.16b}, v2.16b -# CHECK: tbl v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b -# CHECK: tbl v0.16b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.16b +# CHECK: tbl v0.16b, { v1.16b }, v2.16b +# CHECK: tbl v16.16b, { v31.16b, v0.16b }, v2.16b +# CHECK: tbl v0.16b, { v1.16b, v2.16b, v3.16b }, v2.16b +# CHECK: tbl v0.16b, { v31.16b, v0.16b, v1.16b, v2.16b }, v2.16b 0x20,0x10,0x02,0x0e 0xf0,0x33,0x02,0x0e 0x20,0x50,0x02,0x0e 0xf0,0x72,0x02,0x0e -# CHECK: tbx v0.8b, {v1.16b}, v2.8b -# CHECK: tbx v16.8b, {v31.16b, v0.16b}, v2.8b -# CHECK: tbx v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b -# CHECK: tbx v16.8b, {v23.16b, v24.16b, v25.16b, v26.16b}, v2.8b +# CHECK: tbx v0.8b, { v1.16b }, v2.8b +# CHECK: tbx v16.8b, { v31.16b, v0.16b }, v2.8b +# CHECK: tbx v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b +# CHECK: tbx v16.8b, { v23.16b, v24.16b, v25.16b, v26.16b }, v2.8b 0x20,0x10,0x02,0x4e 0xf0,0x33,0x02,0x4e 0x20,0x50,0x02,0x4e 0xf0,0x73,0x02,0x4e -# CHECK: tbx v0.16b, {v1.16b}, v2.16b -# CHECK: tbx v16.16b, {v31.16b, v0.16b}, v2.16b -# CHECK: tbx v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b -# CHECK: tbx v16.16b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.16b +# CHECK: tbx v0.16b, { v1.16b }, v2.16b +# CHECK: tbx v16.16b, { v31.16b, v0.16b }, v2.16b +# CHECK: tbx v0.16b, { v1.16b, v2.16b, v3.16b }, v2.16b +# CHECK: tbx v16.16b, { v31.16b, v0.16b, v1.16b, v2.16b }, v2.16b #---------------------------------------------------------------------- # Scalar Floating-point Convert To Lower Precision Narrow, Rounding To |