diff options
Diffstat (limited to 'test/MC/Disassembler/ARM')
| -rw-r--r-- | test/MC/Disassembler/ARM/armv8.1a.txt | 16 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/thumb-v8.1a.txt | 12 |
2 files changed, 28 insertions, 0 deletions
diff --git a/test/MC/Disassembler/ARM/armv8.1a.txt b/test/MC/Disassembler/ARM/armv8.1a.txt index de0c89e..929643b 100644 --- a/test/MC/Disassembler/ARM/armv8.1a.txt +++ b/test/MC/Disassembler/ARM/armv8.1a.txt @@ -34,3 +34,19 @@ # CHECK-V8: [0x42,0x0f,0x92,0xf3] # CHECK-V8: warning: invalid instruction encoding # CHECK-V8: [0x42,0x0f,0xa1,0xf2] + +# The SETPAN(v8.1a) and TST(v8) instructions occupy the same space, but SETPAN +# uses the encoding for the invalid NV predicate operand. This test checks that +# the disassembler is correctly disambiguating and decoding these instructions. + +[0x00 0x00 0x10 0xf1] +# CHECK: setpan #0 + +[0x00 0x02 0x10 0xf1] +# CHECK: setpan #1 + +[0x00 0x00 0x10 0xe1] +# CHECK: tst r0, r0 + +[0x00 0x02 0x10 0xe1] +# CHECK: tst r0, r0, lsl #4 diff --git a/test/MC/Disassembler/ARM/thumb-v8.1a.txt b/test/MC/Disassembler/ARM/thumb-v8.1a.txt index 10fea46..3de8c27 100644 --- a/test/MC/Disassembler/ARM/thumb-v8.1a.txt +++ b/test/MC/Disassembler/ARM/thumb-v8.1a.txt @@ -96,3 +96,15 @@ # CHECK-V8: warning: invalid instruction encoding # CHECK-V8: [0xa2,0xff,0x42,0x0f] # CHECK-V8: ^ + +[0x10,0xb6] +# CHECK-V81a: setpan #0 +# CHECK-V8: warning: invalid instruction encoding +# CHECK-V8: [0x10,0xb6] +# CHECK-V8: ^ + +[0x18,0xb6] +# CHECK-V81a: setpan #1 +# CHECK-V8: warning: invalid instruction encoding +# CHECK-V8: [0x18,0xb6] +# CHECK-V8: ^ |