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* Add full bss data support for darwin tls variables.Eric Christopher2010-05-223-3/+53
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104414 91177308-0d34-0410-b5e6-96231b3b80d8
* Collect variable information during endFunction() instead of beginFunction().Devang Patel2010-05-221-12/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104412 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new section and accessor for TLS data.Eric Christopher2010-05-221-0/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104411 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up extra whitespace.Bob Wilson2010-05-211-1/+0
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* Make this LookAheadLimit, not the uninitialized LookAheadLeft.Eric Christopher2010-05-211-1/+1
| | | | | | | Evan please verify! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104408 91177308-0d34-0410-b5e6-96231b3b80d8
* add a noteChris Lattner2010-05-211-0/+15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104404 91177308-0d34-0410-b5e6-96231b3b80d8
* Expand on comment.Eric Christopher2010-05-211-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104396 91177308-0d34-0410-b5e6-96231b3b80d8
* Added retl for 32-bit x86 and added retq for 64-bit x86.Kevin Enderby2010-05-213-0/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104394 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix comment and whitespace.Eric Christopher2010-05-211-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104392 91177308-0d34-0410-b5e6-96231b3b80d8
* expand on the llvm ir bitcode dox. Patch by Peter Housel!Chris Lattner2010-05-211-7/+339
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104391 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow machine cse to cse instructions which define physical registers. ↵Evan Cheng2010-05-211-27/+81
| | | | | | Controlled by option -machine-cse-phys-defs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104385 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix section attribute name.Eric Christopher2010-05-211-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104381 91177308-0d34-0410-b5e6-96231b3b80d8
* Change CodeGen/ARM/2009-11-02-NegativeLane.ll to use 16-bit vector elementsBob Wilson2010-05-212-7/+14
| | | | | | | | | so that it will continue to test what it was meant to test when I commit a separate change for better support of BUILD_VECTOR and VECTOR_SHUFFLE for Neon. Fix a DAG combiner crash exposed by this test change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104380 91177308-0d34-0410-b5e6-96231b3b80d8
* - Change MachineInstr::findRegisterDefOperandIdx so it can also look for defsEvan Cheng2010-05-218-28/+43
| | | | | | | | | | | that are aliases of the specified register. - Rename modifiesRegister to definesRegister since it's looking a def of the specific register or one of its super-registers. It's not looking for def of a sub-register or alias that could change the specified register. - Added modifiesRegister to look for defs of aliases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104377 91177308-0d34-0410-b5e6-96231b3b80d8
* Add MachineInstr::readsWritesVirtualRegister() to determine if an instructionJakob Stoklund Olesen2010-05-212-12/+26
| | | | | | | | | | reads or writes a register. This takes partial redefines and undef uses into account. Don't actually use it yet. That caused miscompiles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104372 91177308-0d34-0410-b5e6-96231b3b80d8
* SimplifyDevang Patel2010-05-211-44/+23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104338 91177308-0d34-0410-b5e6-96231b3b80d8
* Previous commit message should refer to 104308.Dale Johannesen2010-05-211-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104337 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix two bugs in 104348:Dale Johannesen2010-05-211-3/+9
| | | | | | | | | Case where MMX is disabled wasn't handled right. MMX->MMX bitconverts are Legal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104336 91177308-0d34-0410-b5e6-96231b3b80d8
* added an assertion to MCObjectWriter::WriteBytes to catch misuse of the ↵Nathan Jeffords2010-05-211-0/+2
| | | | | | | | ZeroFillSize parameter If the size of the string is greater than the zero fill size, the function will attempt to write a very large string of zeros to the object file (~4GB on 32 bit platforms). This assertion will catch the scenario and crash the program before the write occurs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104334 91177308-0d34-0410-b5e6-96231b3b80d8
* now that fp reg kill insertion stuff happens as a separateChris Lattner2010-05-212-38/+58
| | | | | | | | | | | | | | | | | | | pass after isel instead of being interlaced with it, we can trust that all the code for a function has been isel'd before it is run. The practical impact of this is that we can scan for machine instr phis instead of doing a fuzzy match on the LLVM BB for phi nodes. Doing the fuzzy match required knowing when isel would produce an fp reg stack phi which was gross. It was also wrong in cases where select got lowered to a branch tree because cmovs aren't available (PR6828). Just do the scan on machine phis which is simpler, faster and more correct. This fixes PR6828. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104333 91177308-0d34-0410-b5e6-96231b3b80d8
* Use less evil form of switch stmt.Chris Lattner2010-05-211-2/+4
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* use continue to reduce nesting.Chris Lattner2010-05-211-14/+17
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* pull a nested loop of this pass out to its own function,Chris Lattner2010-05-211-42/+55
| | | | | | | eliminating the gymnastics around the ContainsFPCode var. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104328 91177308-0d34-0410-b5e6-96231b3b80d8
* modernize this pass a bit, fit in 80 columns.Chris Lattner2010-05-211-6/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104326 91177308-0d34-0410-b5e6-96231b3b80d8
* constify accessor.Chris Lattner2010-05-212-2/+3
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* Revert "Use MachineInstr::readsWritesVirtualRegister to determine if a ↵Jakob Stoklund Olesen2010-05-213-34/+58
| | | | | | | | register is read." This reverts r104322. I think it was causing miscompilations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104323 91177308-0d34-0410-b5e6-96231b3b80d8
* Use MachineInstr::readsWritesVirtualRegister to determine if a register is read.Jakob Stoklund Olesen2010-05-213-58/+34
| | | | | | This correctly handles partial redefines and undef uses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104322 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach VirtRegRewriter to handle spilling in instructions that have multipleJakob Stoklund Olesen2010-05-212-1/+52
| | | | | | | | | | | | | definitions of the virtual register. This happens when spilling the registers produced by REG_SEQUENCE: %reg1047:5<def>, %reg1047:6<def>, %reg1047:7<def> = VLD3d8 %reg1033, 0, pred:14, pred:%reg0 The rewriter would spill the register multiple times, dead store elimination tried to keep up, but ended up cutting the branch it was sitting on. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104321 91177308-0d34-0410-b5e6-96231b3b80d8
* If the first definition of a virtual register is a partial redef, add anJakob Stoklund Olesen2010-05-213-7/+24
| | | | | | | <imp-def> operand for the full register. This ensures that the full physical register is marked live after register allocation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104320 91177308-0d34-0410-b5e6-96231b3b80d8
* Currently, createMachOStreamer() is invoked directly in llvm-mc whichMatt Fleming2010-05-213-1/+68
| | | | | | | | | | | isn't ideal if we want to be able to use another object file format. Add a createObjectStreamer() factory method so that the correct object file streamer can be instantiated for a given target triple. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104318 91177308-0d34-0410-b5e6-96231b3b80d8
* Split out the x86_32 an x86_64 ELF backends as they handle ELFMatt Fleming2010-05-211-2/+14
| | | | | | | | differently. This will make adding ELF support easier in the long run. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104317 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for parsing the ELF .type assembler directive.Matt Fleming2010-05-214-1/+52
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* Removed scaleNumbering method declaration from LiveInterval (not defined, ↵Lang Hames2010-05-211-4/+0
| | | | | | not used). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104311 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix i64->f64 conversion, x86-64, -no-sse. A bitDale Johannesen2010-05-213-0/+45
| | | | | | | | | tricky since there's a 3rd 64-bit type, MMX vectors. PR 7135. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104308 91177308-0d34-0410-b5e6-96231b3b80d8
* Change ARM scheduling default to list-hybrid if the target supports floating ↵Evan Cheng2010-05-219-15/+18
| | | | | | point instructions (and is not using soft float). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104307 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename -pre-RA-sched=hybrid to -pre-RA-sched=list-hybrid.Evan Cheng2010-05-211-1/+1
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* Remove dead option.Daniel Dunbar2010-05-211-3/+0
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* Simplify.Devang Patel2010-05-211-16/+8
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* Fix __crashreport_info__ declaration.Daniel Dunbar2010-05-201-2/+2
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* Allow targets more controls on what nodes are scheduled by reg pressure, ↵Evan Cheng2010-05-208-16/+52
| | | | | | what for latency in hybrid mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104293 91177308-0d34-0410-b5e6-96231b3b80d8
* DominatorTree.getNode can return null for unreachable blocks.Dan Gohman2010-05-201-1/+1
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* Minor code cleanups.Dan Gohman2010-05-201-8/+7
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* Print a space after the colon.Mikhail Glushenkov2010-05-201-2/+2
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* Make Solve check its own post-condition, to reduce clutter in theDan Gohman2010-05-201-1/+2
| | | | | | | top-level LSRInstance logic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104278 91177308-0d34-0410-b5e6-96231b3b80d8
* Add comments.Dan Gohman2010-05-201-0/+16
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* MC/X86: Add movq alias for movabsq, to allow matching 64-bit immediates with ↵Daniel Dunbar2010-05-202-0/+27
| | | | | | movq. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104275 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename variable. add comment.Devang Patel2010-05-202-3/+6
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* More code cleanups. Use iterators instead of indices when indicesDan Gohman2010-05-201-22/+24
| | | | | | | aren't needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104273 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Model i64i32imm properly, as a subclass of all immediates.Daniel Dunbar2010-05-203-2/+29
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* X86: Fix immediate type of FOO64i32 operations.Daniel Dunbar2010-05-201-10/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104271 91177308-0d34-0410-b5e6-96231b3b80d8
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