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* Support for building/using tblgen for Windows SDK.Raphael2011-01-133-16/+32
| | | | Change-Id: I174939e0acb4bc3bea368c8a8e8435384bcc8d48
* Move global inline options to local makefile for libbcc.so.Jing Yu2010-12-071-1/+8
| | | | | | | | | | We plan to remove the global inline options for better inline tuning. Blindly removing global inline options for libbcc.so may increase certain code size. To be conservative, we simply copy the global inline options into local makefile for libbcc.so. Change-Id: I30ca5ef67602be51c9b83fa52e8c3ced423694ea
* Fix Android.mk'sShih-wei Liao2010-12-042-71/+56
| | | | Change-Id: I4de9583db7f8d47bdda444804aecaeb71c5dfcb8
* Refactor Android.mkShih-wei Liao2010-12-041-37/+48
| | | | Change-Id: I9a0fbb7f96b8d1f7b7047c19b8d7fd99a6bddf51
* Merge "Fix typo: X86 -> ARM."Shih-wei Liao2010-11-281-1/+2
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| * Fix typo: X86 -> ARM.Logan2010-11-281-1/+2
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* | Enabling bcc to do host-side cross-compile. So we can soon do a build-time ↵Shih-wei Liao2010-10-252-2/+30
|/ | | | | | preopt, similar to dexopt. Change-Id: I82085a058bfc61a0dfcf6394e59f12986b728c76
* PR8359: The ARM backend may end up allocating registers D16 to D31 whenBob Wilson2010-10-234-3/+11
| | | | | | | | "-mattr=+vfp3" is specified. However, this will not work for hardware that only supports 16 registers. Add a new flag to support -"mattr=+vfp3,+d16". Patch by Jan Voung! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116310 91177308-0d34-0410-b5e6-96231b3b80d8
* Falsify the enable-assertion.Shih-wei Liao2010-10-222-1/+51
| | | | Change-Id: I3c19e4b09fa8e4bd7832b409f9fe50f5b75922a6
* Add target build of libLLVMLinker.Zonr Chang2010-10-222-4/+21
| | | | | | | | Adding LOCAL_MODULE_TAGS := optional, for it to pass the tag checking. This increase ~24KB on libbcc.so. Change-Id: I3dcfeb3aa843d597050663752caacf7545e09ff0
* Fix Bug #3092270. Make clang and llvm agree on v128.Shih-wei Liao2010-10-131-1/+1
| | | | Change-Id: I50deafde09216b09ce6cb8762b31601fb62b6a51
* Fix VFP register encoding.Zonr Chang2010-10-111-9/+12
| | | | | | | | A VFP register in Rd/Rn/Rm is encoded as (Vd:D)/(Vn:N)/(Vm:M) if it's a single-precision register, (D:Vd)/(N:Vn)/(M:Vn) if it's a double-precision register. Change-Id: Ib6c2ea23328b5e71012ea8b1375c38700100c96b
* Include $(CLANG_ROOT_PATH)/include in llvm-host-build.mk using tblgen.Zonr Chang2010-10-081-2/+3
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* Add some missing files for host build.Zonr Chang2010-10-083-3/+13
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* To get address mode's S-bit, we should use ">=" instead of "!=".Shih-wei Liao2010-09-151-1/+1
| | | | | | This is in order to prevent missing S bit in ARM code generation. Change-Id: Ieac28c6a2409c1c0d2d0c46a2b01a34c47841970
* 1. Better support for access constant entry (add emitLEApcrelInstruction)Shih-wei Liao2010-09-153-37/+118
| | | | | | | | | 2. Add suppport to emit ConstantVector and ConstantArray 3. emitLEApcrelInstruction uses PC relative mode add/sub and the offset need to be encoded in so_imm (A5.2.4 Modified immediate constants in ARM instructions) Change-Id: Id7a933dddbd7e80289bf5befa48a054dc765a644
* Add README.android to describe the Android-specific LLVM changes that we ↵Shih-wei Liao2010-09-151-0/+39
| | | | | | | | | can't push upstream. Some of them are to-dos that when they are done, there will no longer be merge conflicts with upstream. Change-Id: I5a754dd389af05bb7c151468ceb347e06e025247
* Merge commit 'refs/changes/82/67782/1' of ↵Shih-wei Liao2010-09-141-1/+1
|\ | | | | | | ssh://android-git.corp.google.com:29418/platform/external/llvm into update_llvm
| * Potential fix for b/2988615.Shih-wei Liao2010-09-131-1/+1
| | | | | | | | Change-Id: Ia15a1f5e25360dac4ca4bfecc35cb1aa6b6db1b8
* | Apply changes on LLVM r112364 after merge.Shih-wei Liao2010-09-1123-75/+137
| | | | | | | | Change-Id: I9688675d46dca0d564206616c40b005669269010
* | Merge commit '69494cf8102cf872e9cb76662e9960be7c112112' into HEADShih-wei Liao2010-09-102090-55095/+117131
|\ \ | |/ |/| | | | | | | | | | | | | | | | | Conflicts: lib/CodeGen/AsmPrinter/AsmPrinter.cpp lib/Target/ARM/ARMCodeEmitter.cpp lib/Target/ARM/ARMJITInfo.cpp lib/Target/ARM/ARMRelocations.h lib/Transforms/IPO/MergeFunctions.cpp Change-Id: I23d40983717e072fa49334c1fa54f2cf961476c7
| * Update ocaml test.Benjamin Kramer2010-08-281-6/+0
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112364 91177308-0d34-0410-b5e6-96231b3b80d8
| * Remove unions from the ocaml bindings.Benjamin Kramer2010-08-283-43/+0
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112363 91177308-0d34-0410-b5e6-96231b3b80d8
| * Use pseudo instructions for VST1 and VST2.Bob Wilson2010-08-284-113/+110
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112357 91177308-0d34-0410-b5e6-96231b3b80d8
| * remove unions from LLVM IR. They are severely buggy and notChris Lattner2010-08-2833-822/+35
| | | | | | | | | | | | | | being actively maintained, improved, or extended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112356 91177308-0d34-0410-b5e6-96231b3b80d8
| * remove the ABCD and SSI passes. They don't have any clients thatChris Lattner2010-08-2815-1836/+0
| | | | | | | | | | | | | | | | I'm aware of, aren't maintained, and LVI will be replacing their value. nlewycky approved this on irc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112355 91177308-0d34-0410-b5e6-96231b3b80d8
| * remove dead protoChris Lattner2010-08-281-1/+0
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112354 91177308-0d34-0410-b5e6-96231b3b80d8
| * more dead thing zapping.Chris Lattner2010-08-281-17/+1
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112353 91177308-0d34-0410-b5e6-96231b3b80d8
| * zap dead methodChris Lattner2010-08-281-2/+0
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112352 91177308-0d34-0410-b5e6-96231b3b80d8
| * for completeness, allow undef also.Chris Lattner2010-08-281-0/+3
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112351 91177308-0d34-0410-b5e6-96231b3b80d8
| * squish dead code.Chris Lattner2010-08-282-20/+9
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112350 91177308-0d34-0410-b5e6-96231b3b80d8
| * zap dead codeChris Lattner2010-08-281-10/+0
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112349 91177308-0d34-0410-b5e6-96231b3b80d8
| * Clean up the logic of vector shuffles -> vector shifts.Bruno Cardoso Lopes2010-08-281-46/+180
| | | | | | | | | | | | | | | | | | | | Also teach this logic how to handle target specific shuffles if needed, this is necessary while searching recursively for zeroed scalar elements in vector shuffle operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112348 91177308-0d34-0410-b5e6-96231b3b80d8
| * handle the constant case of vector insertion. For somethingChris Lattner2010-08-282-3/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | like this: struct S { float A, B, C, D; }; struct S g; struct S bar() { struct S A = g; ++A.B; A.A = 42; return A; } we now generate: _bar: ## @bar ## BB#0: ## %entry movq _g@GOTPCREL(%rip), %rax movss 12(%rax), %xmm0 pshufd $16, %xmm0, %xmm0 movss 4(%rax), %xmm2 movss 8(%rax), %xmm1 pshufd $16, %xmm1, %xmm1 unpcklps %xmm0, %xmm1 addss LCPI1_0(%rip), %xmm2 pshufd $16, %xmm2, %xmm2 movss LCPI1_1(%rip), %xmm0 pshufd $16, %xmm0, %xmm0 unpcklps %xmm2, %xmm0 ret instead of: _bar: ## @bar ## BB#0: ## %entry movq _g@GOTPCREL(%rip), %rax movss 12(%rax), %xmm0 pshufd $16, %xmm0, %xmm0 movss 4(%rax), %xmm2 movss 8(%rax), %xmm1 pshufd $16, %xmm1, %xmm1 unpcklps %xmm0, %xmm1 addss LCPI1_0(%rip), %xmm2 movd %xmm2, %eax shlq $32, %rax addq $1109917696, %rax ## imm = 0x42280000 movd %rax, %xmm0 ret git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112345 91177308-0d34-0410-b5e6-96231b3b80d8
| * Straighten out any triple strings passed on the command line beforeDuncan Sands2010-08-284-4/+6
| | | | | | | | | | | | | | they hit the rest of the system. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112344 91177308-0d34-0410-b5e6-96231b3b80d8
| * optimize bitcasts from large integers to vector into vectorChris Lattner2010-08-283-11/+160
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | element insertion from the pieces that feed into the vector. This handles a pattern that occurs frequently due to code generated for the x86-64 abi. We now compile something like this: struct S { float A, B, C, D; }; struct S g; struct S bar() { struct S A = g; ++A.A; ++A.C; return A; } into all nice vector operations: _bar: ## @bar ## BB#0: ## %entry movq _g@GOTPCREL(%rip), %rax movss LCPI1_0(%rip), %xmm1 movss (%rax), %xmm0 addss %xmm1, %xmm0 pshufd $16, %xmm0, %xmm0 movss 4(%rax), %xmm2 movss 12(%rax), %xmm3 pshufd $16, %xmm2, %xmm2 unpcklps %xmm2, %xmm0 addss 8(%rax), %xmm1 pshufd $16, %xmm1, %xmm1 pshufd $16, %xmm3, %xmm2 unpcklps %xmm2, %xmm1 ret instead of icky integer operations: _bar: ## @bar movq _g@GOTPCREL(%rip), %rax movss LCPI1_0(%rip), %xmm1 movss (%rax), %xmm0 addss %xmm1, %xmm0 movd %xmm0, %ecx movl 4(%rax), %edx movl 12(%rax), %esi shlq $32, %rdx addq %rcx, %rdx movd %rdx, %xmm0 addss 8(%rax), %xmm1 movd %xmm1, %eax shlq $32, %rsi addq %rax, %rsi movd %rsi, %xmm1 ret This resolves rdar://8360454 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112343 91177308-0d34-0410-b5e6-96231b3b80d8
| * Completely disable tail calls when fast-isel is enabled, as fast-iselDan Gohman2010-08-282-4/+15
| | | | | | | | | | | | | | doesn't currently support dealing with this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112341 91177308-0d34-0410-b5e6-96231b3b80d8
| * Trim a #include.Dan Gohman2010-08-281-3/+0
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112340 91177308-0d34-0410-b5e6-96231b3b80d8
| * Fix an index calculation thinko.Dan Gohman2010-08-281-1/+1
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112337 91177308-0d34-0410-b5e6-96231b3b80d8
| * We don't need to custom-select VLDMQ and VSTMQ anymore.Bob Wilson2010-08-282-42/+7
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112336 91177308-0d34-0410-b5e6-96231b3b80d8
| * Update CMake build. Add newline at end of file.Benjamin Kramer2010-08-282-1/+2
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112332 91177308-0d34-0410-b5e6-96231b3b80d8
| * When merging Thumb2 loads/stores, do not give up when the offset is one ofBob Wilson2010-08-271-10/+7
| | | | | | | | | | | | | | | | | | the special values that for ARM would be used with IB or DA modes. Fall through and consider materializing a new base address is it would be profitable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112329 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add a prototype of a new peephole optimizing pass that uses LazyValue info ↵Owen Anderson2010-08-276-0/+165
| | | | | | | | | | | | | | | | | | to simplify PHIs and select's. This pass addresses the missed optimizations from PR2581 and PR4420. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112325 91177308-0d34-0410-b5e6-96231b3b80d8
| * Improve the precision of getConstant().Owen Anderson2010-08-271-0/+5
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112323 91177308-0d34-0410-b5e6-96231b3b80d8
| * Change ARM VFP VLDM/VSTM instructions to use addressing mode #4, just likeBob Wilson2010-08-2711-167/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | all the other LDM/STM instructions. This fixes asm printer crashes when compiling with -O0. I've changed one of the NEON tests (vst3.ll) to run with -O0 to check this in the future. Prior to this change VLDM/VSTM used addressing mode #5, but not really. The offset field was used to hold a count of the number of registers being loaded or stored, and the AM5 opcode field was expanded to specify the IA or DB mode, instead of the standard ADD/SUB specifier. Much of the backend was not aware of these special cases. The crashes occured when rewriting a frameindex caused the AM5 offset field to be changed so that it did not have a valid submode. I don't know exactly what changed to expose this now. Maybe we've never done much with -O0 and NEON. Regardless, there's no longer any reason to keep a count of the VLDM/VSTM registers, so we can use addressing mode #4 and clean things up in a lot of places. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112322 91177308-0d34-0410-b5e6-96231b3b80d8
| * tidy up test.Chris Lattner2010-08-271-1/+2
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112321 91177308-0d34-0410-b5e6-96231b3b80d8
| * no really, fix the test.Chris Lattner2010-08-271-1/+1
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112317 91177308-0d34-0410-b5e6-96231b3b80d8
| * fix this test. It's not clear what it's really testing.Chris Lattner2010-08-271-1/+1
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112316 91177308-0d34-0410-b5e6-96231b3b80d8
| * Enhance the shift propagator to handle the case when you have:Chris Lattner2010-08-272-22/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A = shl x, 42 ... B = lshr ..., 38 which can be transformed into: A = shl x, 4 ... iff we can prove that the would-be-shifted-in bits are already zero. This eliminates two shifts in the testcase and allows eliminate of the whole i128 chain in the real example. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112314 91177308-0d34-0410-b5e6-96231b3b80d8
| * Simplify.Devang Patel2010-08-271-4/+1
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112305 91177308-0d34-0410-b5e6-96231b3b80d8
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