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* MIsched: cleanup code. Use isBoundaryNode().Andrew Trick2013-01-291-2/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173775 91177308-0d34-0410-b5e6-96231b3b80d8
* Use const reference instead of vector copying.Jakub Staszak2013-01-251-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173497 91177308-0d34-0410-b5e6-96231b3b80d8
* MIsched: Print block name. No functionality.Andrew Trick2013-01-251-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173433 91177308-0d34-0410-b5e6-96231b3b80d8
* MachineScheduler support for viewGraph.Andrew Trick2013-01-251-1/+88
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173432 91177308-0d34-0410-b5e6-96231b3b80d8
* MIsched: Improve the interface to SchedDFS analysis (subtrees).Andrew Trick2013-01-251-29/+33
| | | | | | | Allow the strategy to select SchedDFS. Allow the results of SchedDFS to affect initialization of the scheduler state. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173425 91177308-0d34-0410-b5e6-96231b3b80d8
* MISched: Add SchedDFSResult to ScheduleDAGMI to formalize theAndrew Trick2013-01-251-25/+55
| | | | | | interface and allow other strategies to select it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173413 91177308-0d34-0410-b5e6-96231b3b80d8
* MachineScheduler: enable biasCriticalPath for all DAGs.Andrew Trick2013-01-241-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173318 91177308-0d34-0410-b5e6-96231b3b80d8
* Follow-up typo correction from building the wrong branch.Andrew Trick2013-01-111-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172224 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix typo from r170452. Affects -enable-misched heuristics.Andrew Trick2013-01-111-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172223 91177308-0d34-0410-b5e6-96231b3b80d8
* MIsched: add an ILP window property to machine model.Andrew Trick2013-01-091-10/+2
| | | | | | | | | | This was an experimental option, but needs to be defined per-target. e.g. PPC A2 needs to aggressively hide latency. I converted some in-order scheduling tests to A2. Hal is working on more test cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171946 91177308-0d34-0410-b5e6-96231b3b80d8
* MISched: Cleanup, redundant statement.Andrew Trick2012-12-181-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170453 91177308-0d34-0410-b5e6-96231b3b80d8
* MISched: Heuristics, compare latency more precisely. It matters more for ↵Andrew Trick2012-12-181-43/+38
| | | | | | some targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170452 91177308-0d34-0410-b5e6-96231b3b80d8
* MISched: Remove SchedRemainder::IsResourceLimited. I don't know how to ↵Andrew Trick2012-12-181-3/+0
| | | | | | compute it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170451 91177308-0d34-0410-b5e6-96231b3b80d8
* MISched: cleanup, use the proper iterator type.Andrew Trick2012-12-181-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170450 91177308-0d34-0410-b5e6-96231b3b80d8
* MISched: minor improvement, initialize remaining resources before the first ↵Andrew Trick2012-12-181-0/+10
| | | | | | scheduling decision. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170449 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-5/+4
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: Fix RegisterPressureTracker handling of DebugVals.Andrew Trick2012-12-011-0/+4
| | | | | | | Assertion failed: (TopRPTracker.getPos() == RegionBegin && "bad initial Top tracker"). rdar://12790302. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169072 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: fix RegionBegin when DebugValues get shuffled to the top.Andrew Trick2012-12-011-0/+2
| | | | | | | | assert (RemainingInstrs == 0 && "Instruction count mismatch!") rdar://12776937. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169069 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: Recompute priority queue when DFSResults are updated.Benjamin Kramer2012-11-291-0/+2
| | | | | | | | This was found by MSVC10's STL debug mode on a test from the test suite. Sadly std::is_heap isn't standard so there is no way to assert this without writing our own heap verify, which looks like overkill to me. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168885 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: Analysis that partitions the DAG into subtrees.Andrew Trick2012-11-281-15/+56
| | | | | | | | | | | This is a simple, cheap infrastructure for analyzing the shape of a DAG. It recognizes uniform DAGs that take the shape of bottom-up subtrees, such as the included matrix multiplication example. This is useful for heuristics that balance register pressure with ILP. Two canonical expressions of the heuristic are implemented in scheduling modes: -misched-ilpmin and -misched-ilpmax. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168773 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: rename ScheduleDAGILP to ScheduleDFS to prepare for other heuristics.Andrew Trick2012-11-281-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168772 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: Debug output fix. Use an always valid iterator.Andrew Trick2012-11-281-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168767 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: Allow subtargets to enable misched and dependent options.Andrew Trick2012-11-131-2/+2
| | | | | | | | | | | | This allows me to begin enabling (or backing out) misched by default for one subtarget at a time. To run misched we typically want to: - Disable SelectionDAG scheduling (use the source order scheduler) - Enable more aggressive coalescing (until we decide to always run the coalescer this way) - Enable MachineScheduler pass itself. Disabling PostRA sched may follow for some subtargets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167826 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: rename interfaceto avoid gcc warningsAndrew Trick2012-11-121-2/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167753 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: Target-independent support for MacroFusion.Andrew Trick2012-11-121-5/+61
| | | | | | | | | Uses the infrastructure from r167742 to support clustering instructure that the target processor can "fuse". e.g. cmp+jmp. Next step: target hook implementations with test cases, and enable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167744 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: Target-independent support for load/store clustering.Andrew Trick2012-11-121-12/+176
| | | | | | | | | | This infrastructure is generally useful for any target that wants to strongly prefer two instructions to be adjacent after scheduling. A following checkin will add target-specific hooks with unit tests. Then this feature will be enabled by default with misched. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167742 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: Infrastructure for weak DAG edges.Andrew Trick2012-11-121-8/+18
| | | | | | | | This adds support for weak DAG edges to the general scheduling infrastructure in preparation for MachineScheduler support for heuristics based on weak edges. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167738 91177308-0d34-0410-b5e6-96231b3b80d8
* Silence GCC warning about falling off the end of a non-void function.Benjamin Kramer2012-11-091-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167618 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: Heuristics based on the machine model.Andrew Trick2012-11-071-146/+762
| | | | | | | | | | | | | | misched is disabled by default. With -enable-misched, these heuristics balance the schedule to simultaneously avoid saturating processor resources, expose ILP, and minimize register pressure. I've been analyzing the performance of these heuristics on everything in the llvm test suite in addition to a few other benchmarks. I would like each heuristic check to be verified by a unit test, but I'm still trying to figure out the best way to do that. The heuristics are still in considerable flux, but as they are refined we should be rigorous about unit testing the improvements. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167527 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: Rename RemainingCount to avoid confusion with remaining resources.Andrew Trick2012-11-061-6/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167443 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: Added handleMove support for updating all kill flags, not just for ↵Andrew Trick2012-10-161-1/+1
| | | | | | | | | allocatable regs. This is a medium term workaround until we have a more robust solution in the form of a register liveness utility for postRA passes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166001 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: ILP scheduler for experimental heuristics.Andrew Trick2012-10-151-20/+104
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165950 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: Use the TargetSchedModel interface wherever possible.Andrew Trick2012-10-101-10/+20
| | | | | | | | Allows the new machine model to be used for NumMicroOps and OutputLatency. Allows the HazardRecognizer to be disabled along with itineraries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165603 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: avoid scheduling an instruction twice.Andrew Trick2012-10-081-25/+29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165416 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: add a hook for custom DAG postprocessing.Andrew Trick2012-09-141-0/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163915 91177308-0d34-0410-b5e6-96231b3b80d8
* Release build: guard dump functions withManman Ren2012-09-111-1/+1
| | | | | | | | | "#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)" No functional change. Update r163339. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163653 91177308-0d34-0410-b5e6-96231b3b80d8
* Reorganize MachineScheduler interfaces and publish them in the header.Andrew Trick2012-09-111-256/+100
| | | | | | | | | | | | | | The Hexagon target decided to use a lot of functionality from the target-independent scheduler. That's fine, and other targets should be able to do the same. This reorg and API update makes that easy. For the record, ScheduleDAGMI was not meant to be subclassed. Instead, new scheduling algorithms should be able to implement MachineSchedStrategy and be done. But if need be, it's nice to be able to extend ScheduleDAGMI, so I also made that easier. The target scheduler is somewhat more apt to break that way though. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163580 91177308-0d34-0410-b5e6-96231b3b80d8
* Release build: guard dump functions with "ifndef NDEBUG"Manman Ren2012-09-061-0/+2
| | | | | | | No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163339 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify the computeOperandLatency API.Andrew Trick2012-08-231-10/+8
| | | | | | | | | The logic for recomputing latency based on a ScheduleDAG edge was shady. This bypasses the problem by requiring the client to provide operand indices. This ensures consistent use of the machine model's API. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162420 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a getName function to MachineFunction. Use it in places that previously ↵Craig Topper2012-08-221-1/+1
| | | | | | did getFunction()->getName(). Remove includes of Function.h that are no longer needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162347 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a typo (the the => the)Sylvestre Ledru2012-07-231-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160621 91177308-0d34-0410-b5e6-96231b3b80d8
* I'm introducing a new machine model to simultaneously allow simpleAndrew Trick2012-07-071-1/+2
| | | | | | | | | | | | | | | | | | | | | | | subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159891 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: allow NULL InstrItineraries.Andrew Trick2012-07-021-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159599 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: avoid scheduling instructions that can't be dispatched.Andrew Trick2012-06-291-6/+29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159408 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: count micro-ops toward the issue limit.Andrew Trick2012-06-291-10/+19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159407 91177308-0d34-0410-b5e6-96231b3b80d8
* Guard private fields that are unused in Release builds with #ifndef NDEBUG.Benjamin Kramer2012-06-161-1/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158608 91177308-0d34-0410-b5e6-96231b3b80d8
* Move RegisterClassInfo.h.Andrew Trick2012-06-061-1/+1
| | | | | | | Allow targets to access this API. It's required for RegisterPressure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158102 91177308-0d34-0410-b5e6-96231b3b80d8
* Move RegisterPressure.h.Andrew Trick2012-06-061-1/+1
| | | | | | | Make it a general utility for use by Targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158097 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: API for minimum vs. expected latency.Andrew Trick2012-06-051-31/+81
| | | | | | | Minimum latency determines per-cycle scheduling groups. Expected latency determines critical path and cost. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158021 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: comments from code review.Andrew Trick2012-06-051-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157975 91177308-0d34-0410-b5e6-96231b3b80d8
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