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path: root/lib/Target/ARM/ARMISelDAGToDAG.cpp
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* Convert some VTBL and VTBX instructions to use pseudo instructions prior toBob Wilson2010-09-131-14/+7
* Switch all the NEON vld-lane and vst-lane instructions over to the newBob Wilson2010-09-131-171/+60
* remove some dead code. t2addrmode_imm8s4 is never used in a Chris Lattner2010-09-051-30/+0
* Finish converting the rest of the NEON VLD instructions to use pseudo-Bob Wilson2010-09-031-93/+52
* Convert VLD1 and VLD2 instructions to use pseudo-instructions untilBob Wilson2010-09-021-35/+46
* temporarily revert r112664, it is causing a decoding conflict, and Chris Lattner2010-09-011-97/+0
* We have a chance for an optimization. Consider this code:Bill Wendling2010-08-311-0/+97
* Use pseudo instructions for VST1 and VST2.Bob Wilson2010-08-281-97/+33
* We don't need to custom-select VLDMQ and VSTMQ anymore.Bob Wilson2010-08-281-38/+1
* Change ARM VFP VLDM/VSTM instructions to use addressing mode #4, just likeBob Wilson2010-08-271-8/+8
* Use pseudo instructions for VST3.Bob Wilson2010-08-261-9/+9
* Use pseudo instructions for VST1d64Q.Bob Wilson2010-08-261-3/+2
* Start converting NEON load/stores to use pseudo instructions, beginning hereBob Wilson2010-08-251-13/+31
* Don't call tablegen'ed Predicate_* functions in the ARM target.Jakob Stoklund Olesen2010-08-171-3/+13
* Add -disable-shifter-op to disable isel of shifter ops. On Cortex-a9 the shif...Evan Cheng2010-07-301-0/+11
* Also use REG_SEQUENCE for VTBX instructions.Bob Wilson2010-07-071-15/+26
* Use REG_SEQUENCE nodes to make the table registers for VTBL instructions beBob Wilson2010-07-061-1/+58
* Remove an unused and a pointless variable.Duncan Sands2010-06-291-3/+0
* Eliminate unnecessary uses of getZExtValue().Dan Gohman2010-06-181-1/+1
* Remove the hidden "neon-reg-sequence" option. The reg sequences are workingBob Wilson2010-06-161-262/+155
* For NEON vectors with 32- or 64-bit elements, select BUILD_VECTORs andBob Wilson2010-06-041-12/+52
* Early implementation of tail call for ARM.Dale Johannesen2010-06-031-0/+1
* Clean up 80 column violations. No functional change.Jim Grosbach2010-06-021-6/+8
* Add the cc_out operand for t2RSBrs instructions. I missed this when I changedBob Wilson2010-05-281-2/+2
* Fix a few places that depended on the numeric value of subreg indices.Jakob Stoklund Olesen2010-05-241-0/+5
* Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enumsJakob Stoklund Olesen2010-05-241-49/+49
* Target instruction selection should copy memoperands.Evan Cheng2010-05-191-3/+11
* Turn on -neon-reg-sequence by default.Evan Cheng2010-05-171-1/+2
* Model vst lane instructions with REG_SEQUENCE.Evan Cheng2010-05-161-7/+75
* Model 128-bit vld lane with REG_SEQUENCE.Evan Cheng2010-05-151-19/+44
* Model 64-bit lane vld with REG_SEQUENCE.Evan Cheng2010-05-151-6/+28
* Model VST*_UPD and VST*oddUPD pair with REG_SEQUENCE.Evan Cheng2010-05-141-25/+68
* Model VLD*_UPD and VLD*odd_UPD pair with REG_SEQUENCE.Evan Cheng2010-05-141-16/+59
* Fix comments.Evan Cheng2010-05-141-2/+2
* Model some vst3 and vst4 with reg_sequence.Evan Cheng2010-05-111-5/+39
* Model some vld3 instructions with REG_SEQUENCE.Evan Cheng2010-05-101-1/+34
* Model vld2 / vst2 with reg_sequence.Evan Cheng2010-05-101-15/+84
* Add a missing break statement to fix unintentional fall-throughBob Wilson2010-05-061-4/+3
* Fix unintentional fallthrough. Patch by Edmund Grimley-Evans <Edmund.Grimley-...Jim Grosbach2010-05-061-1/+2
* Model CONCAT_VECTORS of two 64-bit values as a REG_SEQUENCE.Evan Cheng2010-05-051-1/+28
* With -neon-reg-sequence, models forming a Q register from a pair of consecuti...Evan Cheng2010-05-041-2/+11
* Update ARM DAGtoDAG for matching UBFX instruction for unsigned bitfieldJim Grosbach2010-04-221-6/+40
* Use const qualifiers with TargetLowering. This eliminates severalDan Gohman2010-04-171-1/+0
* Use getAL() rather than a major constant.Evan Cheng2010-04-161-9/+9
* Use default lowering of DYNAMIC_STACKALLOC. As far as I can tell, ARM isle is...Evan Cheng2010-04-151-58/+0
* ARM SelectDYN_ALLOC should emit a copy from SP rather than referencing SP dir...Evan Cheng2010-04-151-1/+1
* Fix VLDMQ and VSTMQ instructions to use the correct encoding and address modes.Bob Wilson2010-03-231-0/+29
* Change VST1 instructions for loading Q register values to operate on pairsBob Wilson2010-03-231-9/+21
* Change VLD1 instructions for loading Q register values to operate on pairsBob Wilson2010-03-231-10/+21
* Rename some VLD1/VST1 instructions to match the implementation, i.e., theBob Wilson2010-03-221-4/+4
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