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path: root/lib/Target/ARM/ARMInstrThumb.td
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* Rename ConstantSDNode::getValue to getZExtValue, for consistencyDan Gohman2008-09-121-11/+11
* More refactoring.Evan Cheng2008-08-291-45/+0
* This commit changes:Chris Lattner2008-01-171-4/+0
* get def use info more correct.Chris Lattner2008-01-101-2/+3
* Only mark instructions that load a single value without extension as isSimple...Evan Cheng2008-01-071-5/+6
* rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.Chris Lattner2008-01-061-4/+4
* rename isStore -> mayStore to more accurately reflect what it captures.Chris Lattner2008-01-061-2/+2
* remove explicit isStore flags that are now inferrable.Chris Lattner2008-01-061-1/+1
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
* Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stackBill Wendling2007-11-131-3/+3
* Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead.Evan Cheng2007-09-111-2/+4
* Initial JIT support for ARM by Raul Fernandes Herbster.Evan Cheng2007-08-071-1/+1
* No more noResults.Evan Cheng2007-07-211-3/+3
* Change instruction description to split OperandList into OutOperandList andEvan Cheng2007-07-191-104/+107
* Remove clobbersPred. Add an OptionalDefOperand to instructions which have the...Evan Cheng2007-07-101-1/+0
* No need for ccop anymore.Evan Cheng2007-07-061-2/+2
* Each ARM use predicate operand is now made up of two components. The new comp...Evan Cheng2007-07-051-2/+4
* Revert the earlier change that removed the M_REMATERIALIZABLE machineDan Gohman2007-06-261-0/+1
* Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoadDan Gohman2007-06-191-1/+0
* Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.Evan Cheng2007-06-191-0/+1
* tBcc is not a barrier.Evan Cheng2007-06-081-1/+1
* Mark these instructions clobbersPred. They modify the condition code register.Evan Cheng2007-06-061-0/+1
* ARM::tB is also predicable.Evan Cheng2007-05-161-2/+5
* Add PredicateOperand to all ARM instructions that have the condition field.Evan Cheng2007-05-151-1/+13
* Switch BCC, MOVCCr, etc. to PredicateOperand.Evan Cheng2007-05-081-2/+2
* Doh. PC displacement is between the constantpool and the add instruction.Evan Cheng2007-05-011-1/+1
* ARM TLS: implement "general dynamic", "initial exec" and "local exec" models.Lauro Ramos Venancio2007-04-271-0/+12
* Back out previous check-in. Incorrect.Evan Cheng2007-04-271-6/+2
* tLEApcrel is a AddrModeTs, i.e. pc relative.Evan Cheng2007-04-271-2/+6
* - Divides the comparisons in two types: comparisons that only use N and ZLauro Ramos Venancio2007-04-021-2/+17
* Can't re-materialize mov r, imm in thumb since mov would clobber the conditio...Evan Cheng2007-03-291-1/+1
* bugfix: sometimes the spiller puts a load between the "mov lr, pc" and "bx" o...Lauro Ramos Venancio2007-03-271-5/+3
* bugfix: When the source register of CALL_NOLINK was LR, the following code wa...Lauro Ramos Venancio2007-03-201-3/+5
* Fix naming inconsistencies.Evan Cheng2007-03-191-4/+4
* Special LDR instructions to load from non-pc-relative constantpools. These areEvan Cheng2007-03-191-0/+5
* Constant generation instructions are re-materializable.Evan Cheng2007-03-191-0/+1
* Spill / restore should avoid modifying the condition register.Evan Cheng2007-02-071-0/+10
* .set pc relative displacement bug: label should be moved down one instructionEvan Cheng2007-02-011-6/+6
* Special epilogue for vararg functions. We cannot do a pop to pc becauseEvan Cheng2007-02-011-1/+4
* Thumb asm syntax does not want 's' suffix for flag setting opcodes.Evan Cheng2007-01-311-2/+2
* - Fix codegen for pc relative constant (e.g. JT) in thumb mode:Evan Cheng2007-01-301-16/+5
* Change the operand orders to t_addrmode_s* to make it easier to morphEvan Cheng2007-01-301-3/+3
* Use BL to implement Thumb far jumps.Evan Cheng2007-01-301-0/+3
* Thumb jumptable support.Evan Cheng2007-01-271-1/+21
* Thumb add / sub with carry.Evan Cheng2007-01-271-1/+17
* Represent tADDspi and tSUBspi as two-address instructions.Evan Cheng2007-01-261-4/+4
* extload -> zextloadEvan Cheng2007-01-261-0/+5
* Use PC relative ldr to load from a constantpool in Thumb mode.Evan Cheng2007-01-241-1/+5
* - Reorg Thumb load / store instructions. Combine each rr and ri pair ofEvan Cheng2007-01-231-73/+55
* ARM backend contribution from Apple.Evan Cheng2007-01-191-0/+513