summaryrefslogtreecommitdiffstats
path: root/lib/Target/ARM/ARMSchedule.td
Commit message (Expand)AuthorAgeFilesLines
* For each instruction itinerary class, specify the number of micro-ops eachEvan Cheng2010-09-091-5/+5
* Fix LDM_RET schedule itinery.Evan Cheng2010-09-081-0/+1
* Make processor FUs unique for given itinerary. This extends the limit of 32Anton Korobeynikov2010-04-181-15/+1
* Split A8/A9 itins - they already were too big.Anton Korobeynikov2010-04-071-1/+2
* Fix itins for VABAAnton Korobeynikov2010-04-071-0/+2
* VHADD differs from VHSUB at least on A9 - the former reads both operands in t...Anton Korobeynikov2010-04-071-0/+2
* Define new itin classes for ARM <-> VFP reg moves to distinguish from NEON op...Anton Korobeynikov2010-04-071-0/+4
* Add new itin classes for FP16 <-> FP32 conversions and make uise of them for A9.Anton Korobeynikov2010-04-071-0/+2
* Make use of new reserved/required scheduling stuff: introduce VFP and NEON lo...Anton Korobeynikov2010-04-071-0/+2
* Finish scheduling itineraries for NEON.David Goodwin2009-09-251-4/+30
* Make the end-of-itinerary mark explicit. Some cleanup.David Goodwin2009-09-241-84/+1
* Checkpoint NEON scheduling itineraries.David Goodwin2009-09-231-1/+31
* Add Cortex-A8 VFP model.David Goodwin2009-09-211-10/+68
* Update Cortex-A8 instruction itineraries for integer instructions.David Goodwin2009-08-191-17/+91
* Turn on if-conversion for thumb2.Evan Cheng2009-08-151-2/+4
* Finalize itineraries for cortex-a8 integer multiplyDavid Goodwin2009-08-131-2/+6
* Allow a zero cycle stage to reserve/require a FU without advancing the cycle ...David Goodwin2009-08-111-5/+10
* Checkpoint scheduling itinerary changes.David Goodwin2009-08-101-6/+14
* Add fake v7 itineraries for now.Evan Cheng2009-07-211-0/+1
* Latency information for ARM v6. It's rough and not yet hooked up. Right now ...Evan Cheng2009-06-191-0/+35