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path: root/lib/Target/X86/X86InstrSSE.td
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* Recommitting PALIGNR shift width fixes.Sean Callanan2009-11-201-8/+8
* Reverting PALIGNR fix until I figure out how thisSean Callanan2009-11-201-8/+8
* Fixed PALIGNR to take 8-bit rotations in all cases.Sean Callanan2009-11-201-8/+8
* Re-apply 89011. It's not to be blamed.Evan Cheng2009-11-171-3/+3
* Revert 89011. Buildbot thinks it might be breaking stuff.Evan Cheng2009-11-171-3/+3
* A few more instructions that should be marked re-materializable.Evan Cheng2009-11-171-3/+3
* - Check memoperand alignment instead of checking stack alignment. Most load /...Evan Cheng2009-11-161-1/+1
* x86 vector shuffle cleanup/fixes:Nate Begeman2009-11-071-29/+7
* Fix a couple of shuffle patterns to use movhlps insteadEric Christopher2009-11-071-9/+9
* Rename usesCustomDAGSchedInserter to usesCustomInserter, and update aDan Gohman2009-10-291-6/+5
* X86 palignr intrinsics immediate field is in bits. ISel must transform it int...Evan Cheng2009-10-281-24/+29
* Add support for matching shuffle patterns with palignr.Nate Begeman2009-10-191-0/+33
* Add support for rematerializing FsFLD0SS and FsFLD0SD as constant-poolDan Gohman2009-09-211-2/+4
* Added a variety of floating-point and SSE instructions.Sean Callanan2009-09-161-0/+21
* Fixed PCMPESTRM128 to have opcode 0x60 instead of 0x62, as specified by theSean Callanan2009-08-201-2/+2
* Implement sse4.2 string/text processing instructions:Eric Christopher2009-08-181-0/+117
* Add 'isCodeGenOnly' bit to Instruction .td records.Daniel Dunbar2009-08-111-4/+6
* Fix up whitespace, remove commented out code.Eric Christopher2009-08-101-29/+14
* llvm-mc/AsmMatcher: Change assembler parser match classes to their own recordDaniel Dunbar2009-08-101-2/+2
* Extend comment on ParserMatchClass .td field, and add some missingDaniel Dunbar2009-08-091-0/+2
* Add crc32 instruction and intrinsics. Add a new class of prefixEric Christopher2009-08-081-0/+72
* Whitespace and 80-col cleanup.Eric Christopher2009-07-311-153/+167
* Add a new register class to describe operands that can't be SP,Dan Gohman2009-07-301-2/+2
* Add support for gcc __builtin_ia32_ptest{z,c,nzc} intrinsics. LowerEric Christopher2009-07-291-2/+11
* Update insertps handling based on feedback. Move to a v4f32 styleEric Christopher2009-07-241-14/+10
* Support insertps via the intrinsic and add a couple of simpleEric Christopher2009-07-231-2/+14
* Fix for PR2484: add an SSE1 pattern for a shuffle we normally prefer to Eli Friedman2009-06-191-0/+6
* Fix an obvious typo.Eli Friedman2009-06-061-1/+1
* The MONITOR and MWAIT instructions have insufficient information forBill Wendling2009-05-281-2/+2
* Fix MOVMSKPDrr encoding.Evan Cheng2009-05-281-1/+1
* Fix PSIGND encoding bug. Patch by Sean Callanan.Evan Cheng2009-05-281-1/+1
* "The instructions MMX_PSADBWrm and MMX_PSADBWrr have opcode 0b11100000 (e0), butBill Wendling2009-05-281-1/+1
* Fix sfence jit encoding. Patch by Sean Callanan.Evan Cheng2009-05-271-1/+1
* 80 col violations.Evan Cheng2009-05-121-2/+4
* Fix infinite recursion in the C++ code which handles movddup by making it unn...Nate Begeman2009-04-291-3/+13
* 2nd attempt, fixing SSE4.1 issues and implementing feedback from duncan.Nate Begeman2009-04-271-319/+225
* Revert 69952. Causes testsuite failures on linux x86-64.Rafael Espindola2009-04-241-225/+319
* PR2957Nate Begeman2009-04-241-319/+225
* Re-apply 68552.Rafael Espindola2009-04-081-4/+4
* Temporarily revert r68552. This was causing a failure in the self-hosting LLVMBill Wendling2009-04-071-4/+4
* Reduce code duplication on the TLS implementation.Rafael Espindola2009-04-071-4/+4
* ADDS{D|S}rr_Int and MULS{D|S}rr_Int are not commutable. The users of these in...Evan Cheng2009-02-261-8/+4
* Generate better code for v8i16 shuffles on SSE2Nate Begeman2009-02-231-0/+8
* Handle llvm.x86.sse2.maskmov.dqu in 64-bit.Evan Cheng2009-02-101-0/+5
* A few more isAsCheapAsAMove.Evan Cheng2009-02-051-0/+4
* The memory alignment requirement on some of the mov{h|l}p{d|s} patterns are 1...Evan Cheng2009-01-281-18/+16
* Whitespace and other minor adjustments to make SSE instructions haveDan Gohman2009-01-091-26/+32
* Fixed x86 code generation of multiple for v2i64. It was incorrect for SSE4.1.Mon P Wang2008-12-181-4/+2
* Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning.Dan Gohman2008-12-031-16/+16
* Mark x86's V_SET0 and V_SETALLONES with isSimpleLoad, and teach X86'sDan Gohman2008-12-031-2/+6