| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Expand PPC64 atomic load and store | Hal Finkel | 2012-12-25 | 1 | -0/+2 |
| * | X86: Shave off one shuffle from the pcmpeqq sequence for SSE2 by making use o... | Benjamin Kramer | 2012-12-25 | 1 | -6/+4 |
| * | X86: Custom lower <2 x i64> eq and ne when SSE41 is not available. | Benjamin Kramer | 2012-12-25 | 1 | -2/+24 |
| * | VCVTSS2SD requires a strict alignment. Thanks Elena. | Nadav Rotem | 2012-12-25 | 1 | -2/+2 |
| * | Quiet gcc's -Wparenthesis warning. No functionality change. | Nick Lewycky | 2012-12-24 | 1 | -1/+1 |
| * | Use a std::string rather than a dynamically allocated char* buffer. | Benjamin Kramer | 2012-12-24 | 2 | -21/+6 |
| * | CostModel: We have API for checking the costs of known shuffles. This patch adds | Nadav Rotem | 2012-12-24 | 1 | -1/+2 |
| * | Some x86 instructions can load/store one of the operands to memory. On SSE, t... | Nadav Rotem | 2012-12-24 | 1 | -260/+260 |
| * | Change the codegen Cost Model API for shuffeles. This patch removes the API f... | Nadav Rotem | 2012-12-24 | 1 | -1/+2 |
| * | CostModel: Change the default target-independent implementation for finding | Nadav Rotem | 2012-12-23 | 1 | -3/+13 |
| * | whitespace | Nadav Rotem | 2012-12-23 | 1 | -28/+0 |
| * | Rename a function. | Nadav Rotem | 2012-12-23 | 1 | -4/+4 |
| * | Loop Vectorizer: Update the cost model of scatter/gather operations and make | Nadav Rotem | 2012-12-23 | 2 | -9/+2 |
| * | X86: Turn mul of <4 x i32> into pmuludq when no SSE4.1 is available. | Benjamin Kramer | 2012-12-22 | 1 | -5/+29 |
| * | X86: Emit vector sext as shuffle + sra if vpmovsx is not available. | Benjamin Kramer | 2012-12-22 | 1 | -8/+39 |
| * | In some cases, due to scheduling constraints we copy the EFLAGS. | Nadav Rotem | 2012-12-21 | 2 | -1/+21 |
| * | [mips] Refactor subword-swap, EXT/INS, load-effective-address and read-hardware | Akira Hatanaka | 2012-12-21 | 3 | -54/+73 |
| * | [mips] Refactor SYNC and multiply/divide instructions. | Akira Hatanaka | 2012-12-21 | 3 | -54/+59 |
| * | [mips] Refactor BAL instructions. | Akira Hatanaka | 2012-12-21 | 2 | -10/+40 |
| * | [mips] Fix encoding of BAL instruction. Also, fix assembler test case which | Akira Hatanaka | 2012-12-21 | 1 | -1/+1 |
| * | [mips] Refactor jump, jump register, jump-and-link and nop instructions. | Akira Hatanaka | 2012-12-21 | 3 | -41/+50 |
| * | [mips] Refactor load/store left/right and load-link and store-conditional | Akira Hatanaka | 2012-12-21 | 2 | -79/+52 |
| * | [mips] Refactor load/store instructions. | Akira Hatanaka | 2012-12-21 | 2 | -62/+34 |
| * | [mips] Remove unnecessary isPseudo parameter. | Akira Hatanaka | 2012-12-21 | 1 | -24/+16 |
| * | [mips] Refactor LUI instruction. | Akira Hatanaka | 2012-12-21 | 3 | -6/+17 |
| * | [mips] Refactor count leading zero or one instructions. | Akira Hatanaka | 2012-12-21 | 3 | -20/+29 |
| * | [mips] Refactor sign-extension-in-register instructions. | Akira Hatanaka | 2012-12-21 | 3 | -11/+21 |
| * | [mips] Refactor instructions which copy from and to HI/LO registers. | Akira Hatanaka | 2012-12-21 | 3 | -22/+35 |
| * | [mips] Refactor logical NOR instructions. | Akira Hatanaka | 2012-12-21 | 2 | -7/+6 |
| * | [mips] Move instruction definitions in MipsInstrInfo.td. | Akira Hatanaka | 2012-12-21 | 1 | -37/+39 |
| * | R600: Coding style - remove empty spaces from the beginning of functions | Tom Stellard | 2012-12-21 | 3 | -35/+0 |
| * | R600: Fix MAX_UINT definition | Tom Stellard | 2012-12-21 | 1 | -1/+1 |
| * | R600: Add SHADOWCUBE to TEX_SHADOW pattern | Tom Stellard | 2012-12-21 | 1 | -1/+1 |
| * | Cleanup compiler warnings on discarding type qualifiers in casts. Switch to C... | Benjamin Kramer | 2012-12-21 | 2 | -6/+10 |
| * | X86: Match pmin/pmax as a target specific dag combine. This occurs during vec... | Benjamin Kramer | 2012-12-21 | 1 | -0/+77 |
| * | Remove duplicate includes. | Roman Divacky | 2012-12-21 | 4 | -4/+0 |
| * | R600: Expand vec4 INT <-> FP conversions | Tom Stellard | 2012-12-21 | 1 | -0/+4 |
| * | X86: Match the SSE/AVX min/max vector ops using a custom node instead of intr... | Benjamin Kramer | 2012-12-21 | 5 | -97/+171 |
| * | Add a missing "virtual" keyword. | Nadav Rotem | 2012-12-21 | 1 | -2/+2 |
| * | Add ARM cortex-r5 subtarget. | Quentin Colombet | 2012-12-21 | 2 | -1/+13 |
| * | Improve the X86 cost model for loads and stores. | Nadav Rotem | 2012-12-21 | 2 | -0/+28 |
| * | BB-Vectorizer: Check the cost of the store pointer type | Nadav Rotem | 2012-12-21 | 1 | -0/+1 |
| * | Call llvm_unreachable instead of assert. | Reed Kotler | 2012-12-21 | 1 | -1/+1 |
| * | Add an MF argument to MI::copyImplicitOps(). | Jakob Stoklund Olesen | 2012-12-20 | 4 | -5/+5 |
| * | MachineInstrBuilderize ARM. | Jakob Stoklund Olesen | 2012-12-20 | 1 | -3/+4 |
| * | MachineInstrBuilderize NVPTX. | Jakob Stoklund Olesen | 2012-12-20 | 1 | -39/+30 |
| * | Revert "Adding support for llvm.arm.neon.vaddl[su].* and" | Bob Wilson | 2012-12-20 | 3 | -66/+4 |
| * | On some ARM cpus, flags setting movs with shifter operand, i.e. lsl, lsr, asr, | Evan Cheng | 2012-12-20 | 4 | -77/+103 |
| * | Remove MCTargetAsmLexer and its derived classes now that edis, | Roman Divacky | 2012-12-20 | 9 | -418/+0 |
| * | Adding support for llvm.arm.neon.vaddl[su].* and | Renato Golin | 2012-12-20 | 3 | -4/+66 |
