external_llvm.git - Android's llvm

	Commit message (Expand)	Author	Age	Files	Lines
*	Properly emit ctors / dtors with priorities into desired sections	Anton Korobeynikov	2012-01-25	2	-2/+37
*	ARM assemly parsing and validation of IT instruction.	Jim Grosbach	2012-01-25	2	-3/+14
*	fix a bug I introduced in r148929, this is not a splat!	Chris Lattner	2012-01-25	1	-1/+5
*	Custom lower PSIGN and PSHUFB intrinsics to their corresponding target specif...	Craig Topper	2012-01-25	4	-74/+49
*	use ConstantVector::getSplat in a few places.	Chris Lattner	2012-01-25	1	-24/+14
*	Custom lower phadd and phsub intrinsics to target specific nodes. Remove the ...	Craig Topper	2012-01-25	3	-63/+70
*	Remove AVX 256-bit unaligned load intrinsics. 128-bit versions had been remov...	Craig Topper	2012-01-25	1	-4/+0
*	Mark 64-bit register RA_64 unused too.	Akira Hatanaka	2012-01-25	1	-4/+5
*	Modify MipsFrameLowering::emitPrologue and emitEpilogue.	Akira Hatanaka	2012-01-25	1	-78/+68
*	Modify MipsRegisterInfo::eliminateFrameIndex to use MipsAnalyzeImmediate to	Akira Hatanaka	2012-01-25	1	-12/+34
*	Merge intrinsic pattern and no pattern versions of VCVTSD2SI intruction defin...	Craig Topper	2012-01-25	1	-24/+5
*	MipsAnalyzeImmediate.h: Fix to add DataTypes.h for msvc.	NAKAMURA Takumi	2012-01-25	1	-0/+1
*	Target/Mips: Unbreak CMake build.	NAKAMURA Takumi	2012-01-25	1	-0/+1
*	Lower 64-bit immediates using MipsAnalyzeImmediate that has just been added.	Akira Hatanaka	2012-01-25	2	-31/+42
*	Add class MipsAnalyzeImmediate which comes up with an instruction sequence to	Akira Hatanaka	2012-01-25	2	-0/+215
*	NEON VLD4(all lanes) assembly parsing and encoding.	Jim Grosbach	2012-01-25	4	-2/+215
*	Tidy up. Rename VLD4DUP patterns for consistency.	Jim Grosbach	2012-01-24	1	-6/+6
*	NEON VLD3(all lanes) assembly parsing and encoding.	Jim Grosbach	2012-01-24	4	-6/+212
*	Sign-extend 32-bit integer arguments when they are passed in 64-bit registers,	Akira Hatanaka	2012-01-24	1	-1/+4
*	Pass CCState by reference.	Akira Hatanaka	2012-01-24	1	-1/+1
*	Pattern for f32 to i64 conversion.	Akira Hatanaka	2012-01-24	1	-0/+1
*	Intel Syntax: Extend special hand coded logic, to recognize special instructi...	Devang Patel	2012-01-24	1	-5/+15
*	64-bit sign extension in register instructions.	Akira Hatanaka	2012-01-24	2	-5/+10
*	NEON VST4(one lane) assembly parsing and encoding.	Jim Grosbach	2012-01-24	2	-0/+148
*	Widen the instruction encoder that TblGen emits to a 64 bits, which should ac...	Owen Anderson	2012-01-24	7	-7/+7
*	NEON VLD4(one lane) assembly parsing and encoding.	Jim Grosbach	2012-01-24	2	-0/+245
*	NEON Two-operand assembly aliases for VSRA.	Jim Grosbach	2012-01-24	1	-0/+39
*	NEON Two-operand assembly aliases for VSLI.	Jim Grosbach	2012-01-24	1	-0/+19
*	NEON Two-operand assembly aliases for VSRI.	Jim Grosbach	2012-01-24	1	-0/+19
*	NEON add correct predicates for some asm aliases.	Jim Grosbach	2012-01-24	2	-18/+27
*	C++, CBE, and TLOF support for ConstantDataSequential	Chris Lattner	2012-01-24	3	-19/+123
*	ZERO_EXTEND operation is optimized for AVX.	Elena Demikhovsky	2012-01-24	1	-2/+37
*	Use correct register class for am2offset register operands.	Anton Korobeynikov	2012-01-24	1	-2/+2
*	Add comments near load pattern fragments indicating that all integer vector l...	Craig Topper	2012-01-24	1	-0/+6
*	NEON VST4(multiple 4 element structures) assembly parsing.	Jim Grosbach	2012-01-24	2	-0/+157
*	NEON VLD4(multiple 4 element structures) assembly parsing.	Jim Grosbach	2012-01-24	4	-0/+179
*	Tidy up. Remove some vertical space for readability.	Jim Grosbach	2012-01-24	1	-344/+121
*	Revert r148686 (and r148694, a fix to it) due to a serious layering	Chandler Carruth	2012-01-24	2	-5/+7
*	Fix typo.	Jim Grosbach	2012-01-24	1	-2/+2
*	NEON VST3(single element from one lane) assembly parsing.	Jim Grosbach	2012-01-24	2	-0/+176
*	Fix typo.	Devang Patel	2012-01-23	1	-1/+1
*	NEON VST3(multiple 3-element structures) assembly parsing.	Jim Grosbach	2012-01-23	2	-20/+206
*	NEON VLD3(multiple 3-element structures) assembly parsing.	Jim Grosbach	2012-01-23	4	-6/+220
*	Add missed mayStore flag to STREXD / t2STREXD	Anton Korobeynikov	2012-01-23	2	-6/+5
*	Intel syntax: Robustify parsing of memory operand's displacement experssion.	Devang Patel	2012-01-23	1	-2/+7
*	NEON VLD3 lane-indexed assembly parsing and encoding.	Jim Grosbach	2012-01-23	2	-0/+267
*	Intel syntax: Parse memory operand with empty base reg, e.g. DWORD PTR [4*RDI]	Devang Patel	2012-01-23	1	-6/+16
*	Simplify some NEON assembly pseudo definitions.	Jim Grosbach	2012-01-23	3	-396/+177
*	Intel syntax: Parse segment registers.	Devang Patel	2012-01-23	1	-4/+16
*	ARMAsmPrinter.cpp: Try to fix up r148686. EnableARMEHABI was also here.	NAKAMURA Takumi	2012-01-23	1	-2/+3