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* Remove getEHExceptionRegister and getEHHandlerRegister.Rafael Espindola2013-10-0712-72/+0
* ARM: allow cortex-m0 to use hint instructionsTim Northover2013-10-075-9/+22
* Remove some instructions that seem to only exist to trick the filtering check...Craig Topper2013-10-071-12/+0
* Remove FsMOVAPSrr and friends. They have no patterns and are no longer select...Craig Topper2013-10-072-29/+4
* Teach X86 asm parser that VMOVAPSrr and other VEX-encoded register to registe...Craig Topper2013-10-072-1/+50
* Add disassembler support for long encodings for INC/DEC in 32-bit mode.Craig Topper2013-10-071-1/+15
* X86: Don't fold spills into SSE operations if the stack is unaligned.Benjamin Kramer2013-10-061-0/+4
* AVX-512: added scalar convert instructions and intrinsics.Elena Demikhovsky2013-10-063-13/+189
* [Sparc] Do not emit nop after fcmp* instruction with V9.Venkatraman Govindaraju2013-10-062-7/+22
* AVX-512: fixed shuffle loweringElena Demikhovsky2013-10-062-1/+15
* [Sparc] Custom lower addc/adde/subc/sube on i64 in sparc64.Venkatraman Govindaraju2013-10-062-7/+55
* [Sparc] Use addxcc/subxcc for adde/sube instead of addx/subx.Venkatraman Govindaraju2013-10-061-4/+4
* Add TBM instructions to loading folding tables.Craig Topper2013-10-051-1/+21
* Rename this feature to "cx16" to match gcc's flag name. Apparently these stringsNick Lewycky2013-10-051-1/+1
* Remove underscores from TBM instruction names for consistency with other inst...Craig Topper2013-10-051-24/+24
* Remove unneeded TBM intrinsics. The arithmetic/logical operation patterns are...Craig Topper2013-10-051-39/+20
* Add an additional pattern for BLCI since opt can turn (not (add x, 1)) into (...Craig Topper2013-10-051-0/+6
* Remove some really nasty uses of hasRawTextSupport.Rafael Espindola2013-10-0510-173/+125
* Implement aarch64 neon instruction set AdvSIMD (Across).Jiangning Liu2013-10-052-0/+144
* [Sparc] Use correct alignment while loading/storing fp128 values.Venkatraman Govindaraju2013-10-051-4/+13
* [Sparc] Respect hasHardQuad parameter correctly when lowering SINT_TO_FP with...Venkatraman Govindaraju2013-10-051-1/+1
* [Sparc] Correct the floating point conditional code mapping in GetOppositeBra...Venkatraman Govindaraju2013-10-041-8/+8
* forgot to remove this file as wellJack Carter2013-10-041-53/+0
* reverting per requestJack Carter2013-10-044-42/+4
* Support tblockaddr for static compilation in Mips16.Reed Kotler2013-10-041-1/+4
* [MC][AsmParser] Hook for post assembly file processingJack Carter2013-10-045-4/+95
* [mips] Fix a bug in MipsLongBranch::replaceBranch, which was erasingAkira Hatanaka2013-10-041-0/+5
* ARM: optimizeSelect has to consider the previous register classMatthias Braun2013-10-041-4/+9
* ARM: do not add a regmask for TAILJUMPsMatthias Braun2013-10-041-16/+18
* ARM: preserve undef flag in pseudo instruction expandersMatthias Braun2013-10-041-19/+14
* Implement aarch64 neon instruction set AdvSIMD (3V elem).Jiangning Liu2013-10-046-53/+937
* AVX-512: Fixed encoding of VMOVQ instruction.Elena Demikhovsky2013-10-031-3/+3
* [ARM] Warn on deprecated IT blocks in v8 AArch32 assembly.Amara Emerson2013-10-037-78/+126
* Replace C++ style comment with a C style comment to satisfy some of the build...Craig Topper2013-10-031-1/+1
* Remove comma from the end of an enum.Craig Topper2013-10-031-1/+1
* Add XOP disassembler support. Fixes PR13933.Craig Topper2013-10-035-125/+238
* Add patterns for selecting TBM instructions from logical operations. Patch fr...Craig Topper2013-10-032-32/+98
* R600: Add a ldptr intrinsic to support MSAA.Vincent Lejeune2013-10-023-1/+10
* AVX-512: fixed a bug in getLoadStoreRegOpcode() for AVX-512 targetElena Demikhovsky2013-10-022-8/+5
* AVX-512: Added TB prefix to all instructions without prefixes,Elena Demikhovsky2013-10-022-20/+18
* R600: add a pass that merges clauses.Vincent Lejeune2013-10-017-2/+232
* R600: Put PRED_X instruction in its own clauseVincent Lejeune2013-10-011-0/+8
* R600: Enable -verify-machineinstrs in some tests.Vincent Lejeune2013-10-015-9/+19
* [SystemZ] Add comparisons of high words and memoryRichard Sandiford2013-10-013-2/+30
* [SystemZ] Add comparisons of large immediates using high wordsRichard Sandiford2013-10-012-2/+20
* [SystemZ] Add immediate addition involving high wordsRichard Sandiford2013-10-014-2/+76
* [SystemZ] Extend test-under-mask support to high GR32sRichard Sandiford2013-10-014-8/+27
* [SystemZ] Extend 32-bit RISBG optimizations to high wordsRichard Sandiford2013-10-011-8/+16
* [SystemZ] Extend pseudo conditional 8- and 16-bit stores to high wordsRichard Sandiford2013-10-012-6/+22
* ARM: support interrupt attributeTim Northover2013-10-018-21/+148
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