| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Debug Info Testing: updated to use NULL instead of "i32 0" in a few fields. | Manman Ren | 2013-09-06 | 16 | -65/+65 |
| * | R600: Add support for LDS atomic subtract | Aaron Watry | 2013-09-06 | 1 | -0/+23 |
| * | Debug Info Testing: Updated to use null instead of "i32 0" for containing-type | Manman Ren | 2013-09-06 | 3 | -27/+27 |
| * | SelectionDAG: create correct BooleanContent constants | Tim Northover | 2013-09-06 | 1 | -0/+61 |
| * | [SystemZ] Tweak integer comparison code | Richard Sandiford | 2013-09-06 | 1 | -0/+101 |
| * | [SystemZ] Use XC for a memset of 0 | Richard Sandiford | 2013-09-06 | 1 | -42/+26 |
| * | Teach CodeGenPrepare about address spaces | Matt Arsenault | 2013-09-06 | 1 | -0/+30 |
| * | [X86] Perform VSELECT DAG combines also before DAG type legalization. | Juergen Ributzka | 2013-09-05 | 1 | -2/+1 |
| * | R600: Fix i64 to i32 trunc on SI | Matt Arsenault | 2013-09-05 | 1 | -0/+19 |
| * | R600: Add support for local memory atomic add | Tom Stellard | 2013-09-05 | 1 | -0/+23 |
| * | R600: Expand SELECT nodes rather than custom lowering them | Tom Stellard | 2013-09-05 | 1 | -0/+46 |
| * | R600: Fix incorrect LDS size calculation | Tom Stellard | 2013-09-05 | 1 | -0/+26 |
| * | R600/SI: Don't emit S_WQM_B64 instruction for compute shaders | Tom Stellard | 2013-09-05 | 2 | -0/+14 |
| * | [ARMv8] Implement the new DMB/DSB operands. | Joey Gouly | 2013-09-05 | 1 | -0/+16 |
| * | Reverting 190043 for now. | Tilmann Scheller | 2013-09-05 | 1 | -76/+0 |
| * | ARM: Add GPR register class excluding LR for use with the ADR instruction. | Tilmann Scheller | 2013-09-05 | 1 | -0/+76 |
| * | [SystemZ] Add NC, OC and XC | Richard Sandiford | 2013-09-05 | 3 | -0/+511 |
| * | [Sparc] Correctly handle call to functions with ReturnsTwice attribute. | Venkatraman Govindaraju | 2013-09-05 | 1 | -0/+70 |
| * | mi-sched: Force bottom up scheduling for generic targets. | Andrew Trick | 2013-09-04 | 2 | -16/+11 |
| * | Expand and rewrite comment. | Eric Christopher | 2013-09-04 | 1 | -3/+4 |
| * | Change swift/vldm test case to be less dependent on allocation order | Arnold Schwaighofer | 2013-09-04 | 1 | -16/+16 |
| * | R600: Use shared op optimization when checking cycle compatibility | Vincent Lejeune | 2013-09-04 | 1 | -0/+38 |
| * | R600: Non vector only instruction can be scheduled on trans unit | Vincent Lejeune | 2013-09-04 | 24 | -127/+239 |
| * | R600: Remove fmul.v4f32.ll test which is redundant with fmul.ll | Vincent Lejeune | 2013-09-04 | 1 | -15/+0 |
| * | Swift: Only build vldm/vstm with q register aligned register lists | Arnold Schwaighofer | 2013-09-04 | 1 | -0/+28 |
| * | Fix scheduling for vldm/vstm instructions that load/store more than 32 bytes ... | Silviu Baranga | 2013-09-04 | 1 | -0/+71 |
| * | [Sparc] Fix an assertion failure while lowering fcmp on long double. | Venkatraman Govindaraju | 2013-09-04 | 1 | -0/+20 |
| * | Inplement aarch64 neon instructions in AdvSIMD(shift). About 24 shift instruc... | Hao Liu | 2013-09-04 | 1 | -0/+1524 |
| * | Revert "Revert "ARM: Improve pattern for isel mul of vector by scalar."" | Jim Grosbach | 2013-09-03 | 1 | -0/+18 |
| * | [SystemZ] Add support for TMHH, TMHL, TMLH and TMLL | Richard Sandiford | 2013-09-03 | 1 | -0/+352 |
| * | [Sparc] Add support for soft long double (fp128). | Venkatraman Govindaraju | 2013-09-03 | 1 | -19/+55 |
| * | [Sparc] Implement spill and load for long double(f128) registers. | Venkatraman Govindaraju | 2013-09-02 | 1 | -0/+15 |
| * | ARM: Default to the Swift CPU when targeting armv7s/thumbv7s. | Tilmann Scheller | 2013-09-02 | 1 | -1/+1 |
| * | Revert 189756 for now, it doesn't match what rdar://14871821 really wants. | Tilmann Scheller | 2013-09-02 | 2 | -3/+3 |
| * | ARM: Default to Swift when compiling for iOS 6 or later. | Tilmann Scheller | 2013-09-02 | 2 | -3/+3 |
| * | FileCheck-ize three tests of llvm/test/CodeGen/X86/h-register(s). | NAKAMURA Takumi | 2013-09-02 | 3 | -5/+56 |
| * | llvm/test/CodeGen/X86: Update tests with -mattr=-bmi not to take BMI, corresp... | NAKAMURA Takumi | 2013-09-02 | 5 | -7/+7 |
| * | Create BEXTR instructions for (and ((sra or srl) x, imm), (2**size - 1)). Fix... | Craig Topper | 2013-09-02 | 1 | -0/+25 |
| * | AVX-512: gather-scatter tests; added foldable instructions; | Elena Demikhovsky | 2013-09-02 | 1 | -14/+16 |
| * | AVX-512: Added GATHER and SCATTER instructions. | Elena Demikhovsky | 2013-09-01 | 1 | -0/+223 |
| * | Make sure we don't generate stubs for any of these functions because they | Reed Kotler | 2013-09-01 | 1 | -15/+13 |
| * | [PowerPC] Call support for fast-isel. | Bill Schmidt | 2013-08-30 | 2 | -0/+166 |
| * | Fix a problem with dual mips16/mips32 mode. When the underlying processor | Reed Kotler | 2013-08-30 | 1 | -0/+38 |
| * | [PowerPC] Add handling for conversions to fast-isel. | Bill Schmidt | 2013-08-30 | 1 | -0/+305 |
| * | Teach X86 backend to create BMI2 BZHI instructions from (and X, (add (shl 1, ... | Craig Topper | 2013-08-30 | 1 | -0/+45 |
| * | Revert "ARM: Improve pattern for isel mul of vector by scalar." | Michael Gottesman | 2013-08-30 | 1 | -18/+0 |
| * | mi-sched: improve the generic register pressure comparison. | Andrew Trick | 2013-08-30 | 3 | -17/+15 |
| * | mi-sched: Precompute a PressureDiff for each instruction, adjust for liveness... | Andrew Trick | 2013-08-30 | 3 | -4/+6 |
| * | [PowerPC] Handle selection of compare instructions in fast-isel. | Bill Schmidt | 2013-08-30 | 1 | -0/+289 |
| * | [PowerPC] Miscellaneous fast-isel test cases. | Bill Schmidt | 2013-08-30 | 4 | -0/+131 |
