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* Debug Info Testing: updated to use NULL instead of "i32 0" in a few fields.Manman Ren2013-09-0616-65/+65
| | | | | | | | | Field 2 of DIType (Context), field 9 of DIDerivedType (TypeDerivedFrom), field 12 of DICompositeType (ContainingType), fields 2, 7, 12 of DISubprogram (Context, Type, ContainingType). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190205 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add support for LDS atomic subtractAaron Watry2013-09-061-0/+23
| | | | | | | Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190200 91177308-0d34-0410-b5e6-96231b3b80d8
* Debug Info Testing: Updated to use null instead of "i32 0" for containing-typeManman Ren2013-09-063-27/+27
| | | | | | | | | field of DICompositeType. This will help the follow-on patch of using DITypeRef for containing-type field. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190187 91177308-0d34-0410-b5e6-96231b3b80d8
* SelectionDAG: create correct BooleanContent constantsTim Northover2013-09-061-0/+61
| | | | | | | | | | | | | | | Occasionally DAGCombiner can spot that a SETCC operation is completely redundant and reduce it to "all true" or "all false". If this happens to a vector, the value produced has to take account of what a normal comparison would have produced, which may be an all-1s bitmask. The fix in SelectionDAG.cpp is tested, however, as far as I can see the code in TargetLowering.cpp is possibly unreachable and almost certainly irrelevant when triggered so there are no tests. However, I believe it's still clearly the right change and may save someone else some hassle if it suddenly becomes reachable. So I'm doing it anyway. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190147 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Tweak integer comparison codeRichard Sandiford2013-09-061-0/+101
| | | | | | | | | | | | | | | | | | | | The architecture has many comparison instructions, including some that extend one of the operands. The signed comparison instructions use sign extensions and the unsigned comparison instructions use zero extensions. In cases where we had a free choice between signed or unsigned comparisons, we were trying to decide at lowering time which would best fit the available instructions, taking things like extension type into account. The code to do that was getting increasingly hairy and was also making some bad decisions. E.g. when comparing the result of two LLCs, it is better to use CR rather than CLR, since CR can be fused with a branch while CLR can't. This patch removes the lowering code and instead adds an operand to integer comparisons to say whether signed comparison is required, whether unsigned comparison is required, or whether either is OK. We can then leave the choice of instruction up to the normal isel code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190138 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Use XC for a memset of 0Richard Sandiford2013-09-061-42/+26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190130 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach CodeGenPrepare about address spacesMatt Arsenault2013-09-061-0/+30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190112 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] Perform VSELECT DAG combines also before DAG type legalization.Juergen Ributzka2013-09-051-2/+1
| | | | | | | | | | | | | If the DAG already has only legal types, then the second round of DAG combines is skipped. In this case VSELECT+SETCC patterns that match a more efficient instruction (e.g. min/max) are never recognized. This fix allows VSELECT+SETCC combines if the types are already legal before DAG type legalization. Reviewer: Nadav git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190105 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix i64 to i32 trunc on SIMatt Arsenault2013-09-051-0/+19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190091 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add support for local memory atomic addTom Stellard2013-09-051-0/+23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190080 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Expand SELECT nodes rather than custom lowering themTom Stellard2013-09-051-0/+46
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190079 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix incorrect LDS size calculationTom Stellard2013-09-051-0/+26
| | | | | | | GlobalAdderss nodes that appeared in more than one basic block were being counted twice. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190078 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Don't emit S_WQM_B64 instruction for compute shadersTom Stellard2013-09-052-0/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190077 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Implement the new DMB/DSB operands.Joey Gouly2013-09-051-0/+16
| | | | | | | | | This removes the custom ISD Node: MEMBARRIER and replaces it with an intrinsic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190055 91177308-0d34-0410-b5e6-96231b3b80d8
* Reverting 190043 for now.Tilmann Scheller2013-09-051-76/+0
| | | | | | | | | Solution is not sufficient to prevent 'mov pc, lr' being emitted for jump table code. Test case doesn't trigger the added functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190047 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Add GPR register class excluding LR for use with the ADR instruction.Tilmann Scheller2013-09-051-0/+76
| | | | | | | | | | This improves code generation for jump tables by avoiding the emission of "mov pc, lr" which could fool the processor into believing this is a return from a function causing mispredicts. The code generation logic for jump tables uses ADR to materialize the address of the jump target. Patch by Daniel Stewart! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190043 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add NC, OC and XCRichard Sandiford2013-09-053-0/+511
| | | | | | | | For now these are just used to handle scalar ANDs, ORs and XORs in which all operands are memory. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190041 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Correctly handle call to functions with ReturnsTwice attribute.Venkatraman Govindaraju2013-09-051-0/+70
| | | | | | | | | | | | | | In sparc, setjmp stores only the registers %fp, %sp, %i7 and %o7. longjmp restores the stack, and the callee-saved registers (all local/in registers: %i0-%i7, %l0-%l7) using the stored %fp and register windows. However, this does not guarantee that the longjmp will restore the registers, as they were when the setjmp was called. This is because these registers may be clobbered after returning from setjmp, but before calling longjmp. This patch prevents the registers %i0-%i5, %l0-l7 to live across the setjmp call using the register mask. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190033 91177308-0d34-0410-b5e6-96231b3b80d8
* mi-sched: Force bottom up scheduling for generic targets.Andrew Trick2013-09-042-16/+11
| | | | | | | | | Fast register pressure tracking currently only takes effect during bottom up scheduling. Forcing this is a bit faster and simpler for targets that don't have many scheduling constraints and don't need top-down scheduling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190014 91177308-0d34-0410-b5e6-96231b3b80d8
* Expand and rewrite comment.Eric Christopher2013-09-041-3/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189998 91177308-0d34-0410-b5e6-96231b3b80d8
* Change swift/vldm test case to be less dependent on allocation orderArnold Schwaighofer2013-09-041-16/+16
| | | | | | | 'Force' values in registers using the calling convention. Now, we only depend on the calling convention and that the allocator performs copy coalescing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189985 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Use shared op optimization when checking cycle compatibilityVincent Lejeune2013-09-041-0/+38
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189981 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Non vector only instruction can be scheduled on trans unitVincent Lejeune2013-09-0424-127/+239
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189980 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Remove fmul.v4f32.ll test which is redundant with fmul.llVincent Lejeune2013-09-041-15/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189978 91177308-0d34-0410-b5e6-96231b3b80d8
* Swift: Only build vldm/vstm with q register aligned register listsArnold Schwaighofer2013-09-041-0/+28
| | | | | | | | Unaligned vldm/vstm need more uops and therefore are slower in general on swift. radar://14522102 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189961 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix scheduling for vldm/vstm instructions that load/store more than 32 bytes ↵Silviu Baranga2013-09-041-0/+71
| | | | | | on Cortex-A9. This also makes the existing code more compact. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189958 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Fix an assertion failure while lowering fcmp on long double.Venkatraman Govindaraju2013-09-041-0/+20
| | | | | | | | This assertion is triggered because an integer constant is created with wrong type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189948 91177308-0d34-0410-b5e6-96231b3b80d8
* Inplement aarch64 neon instructions in AdvSIMD(shift). About 24 shift ↵Hao Liu2013-09-041-0/+1524
| | | | | | | | | | | instructions: sshr,ushr,ssra,usra,srshr,urshr,srsra,ursra,sri,shl,sli,sqshlu,sqshl,uqshl,shrn,sqrshrun,sqshrn,uqshr,sqrshrn,uqrshrn,sshll,ushll and 4 convert instructions: scvtf,ucvtf,fcvtzs,fcvtzu git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189925 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Revert "ARM: Improve pattern for isel mul of vector by scalar.""Jim Grosbach2013-09-031-0/+18
| | | | | | | | | This reverts commit r189648. Fixes for the previously failing clang-side arm_neon_intrinsics test cases will be checked in separately. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189841 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add support for TMHH, TMHL, TMLH and TMLLRichard Sandiford2013-09-031-0/+352
| | | | | | | | | | For now this just handles simple comparisons of an ANDed value with zero. The CC value provides enough information to do any comparison for a 2-bit mask, and some nonzero comparisons with more populated masks, but that's all future work. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189819 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Add support for soft long double (fp128).Venkatraman Govindaraju2013-09-031-19/+55
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189780 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Implement spill and load for long double(f128) registers.Venkatraman Govindaraju2013-09-021-0/+15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189768 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Default to the Swift CPU when targeting armv7s/thumbv7s.Tilmann Scheller2013-09-021-1/+1
| | | | | | | | | | Test cases adjusted accordingly. This fixes rdar://14871821. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189766 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 189756 for now, it doesn't match what rdar://14871821 really wants.Tilmann Scheller2013-09-022-3/+3
| | | | | | | What we really want is to enable Swift by default for *v7s triples (and there already seems to be some logic which attempts to do that). In that case the iOS version doesn't matter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189763 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Default to Swift when compiling for iOS 6 or later.Tilmann Scheller2013-09-022-3/+3
| | | | | | | | | | Test cases adjusted accordingly. This fixes rdar://14871821. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189756 91177308-0d34-0410-b5e6-96231b3b80d8
* FileCheck-ize three tests of llvm/test/CodeGen/X86/h-register(s).NAKAMURA Takumi2013-09-023-5/+56
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189755 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm/test/CodeGen/X86: Update tests with -mattr=-bmi not to take BMI, ↵NAKAMURA Takumi2013-09-025-7/+7
| | | | | | | | corresponding to Craig's r189742. AMD Piledriver builder detected failures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189754 91177308-0d34-0410-b5e6-96231b3b80d8
* Create BEXTR instructions for (and ((sra or srl) x, imm), (2**size - 1)). ↵Craig Topper2013-09-021-0/+25
| | | | | | Fixes PR17028. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189742 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: gather-scatter tests; added foldable instructions;Elena Demikhovsky2013-09-021-14/+16
| | | | | | | Specify GATHER/SCATTER as heavy instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189736 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added GATHER and SCATTER instructions.Elena Demikhovsky2013-09-011-0/+223
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189729 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure we don't generate stubs for any of these functions because theyReed Kotler2013-09-011-15/+13
| | | | | | | | | | | don't exist in libc. This is really not the right way to solve this problem; but it's not clear to me at this time exactly what is the right way. If we create stubs here, they will cause link errors because these functions do not exist in libc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189727 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Call support for fast-isel.Bill Schmidt2013-08-302-0/+166
| | | | | | | | | | This patch adds fast-isel support for calls (but not intrinsic calls or varargs calls). It also removes a badly-formed assert. There are some new tests just for calls, and also for folding loads into arguments on calls to avoid extra extends. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189701 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a problem with dual mips16/mips32 mode. When the underlying processorReed Kotler2013-08-301-0/+38
| | | | | | | | | | | | | | | has hard float, when you compile the mips32 code you have to make sure that it knows to compile any mips32 routines as hard float. I need to clean up the way mips16 hard float is specified but I need to first think through all the details. Mips16 always has a form of soft float, the difference being whether the underlying hardware has floating point. So it's not really necessary to pass the -soft-float to llvm since soft-float is always true for mips16 by virtue of the fact that it will not register floating point registers. By using this fact, I can simplify the way this is all handled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189690 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Add handling for conversions to fast-isel.Bill Schmidt2013-08-301-0/+305
| | | | | | | | | | Yet another chunk of fast-isel code. This one handles various conversions involving floating-point. (It also includes some miscellaneous handling throughout the back end for LWA_32 and LWAX_32 that should have been part of the load-store patch.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189677 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach X86 backend to create BMI2 BZHI instructions from (and X, (add (shl 1, ↵Craig Topper2013-08-301-0/+45
| | | | | | Y), -1)). Fixes PR17038. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189653 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "ARM: Improve pattern for isel mul of vector by scalar."Michael Gottesman2013-08-301-18/+0
| | | | | | | | This reverts commit r189619. The commit was breaking the arm_neon_intrinsic test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189648 91177308-0d34-0410-b5e6-96231b3b80d8
* mi-sched: improve the generic register pressure comparison.Andrew Trick2013-08-303-17/+15
| | | | | | | Only compare pressure within the same set. When multiple sets are affected, we prioritize the most constrained set. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189641 91177308-0d34-0410-b5e6-96231b3b80d8
* mi-sched: Precompute a PressureDiff for each instruction, adjust for ↵Andrew Trick2013-08-303-4/+6
| | | | | | | | | | | | | liveness later. Created SUPressureDiffs array to hold the per node PDiff computed during DAG building. Added a getUpwardPressureDelta API that will soon replace the old one. Compute PressureDelta here from the precomputed PressureDiffs. Updating for liveness will come next. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189640 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Handle selection of compare instructions in fast-isel.Bill Schmidt2013-08-301-0/+289
| | | | | | | | Mostly trivial patch adding support for compares. The meat of the work was added with the branch support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189639 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Miscellaneous fast-isel test cases.Bill Schmidt2013-08-304-0/+131
| | | | | | | | Here are a few more tests that now pass after the recent fast-isel commits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189637 91177308-0d34-0410-b5e6-96231b3b80d8
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