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* BBVectorize: Enable vectorization of the fmuladd intrinsicHal Finkel2012-12-251-0/+28
* Loosen scheduling restrictions on the PPC dcbt intrinsicHal Finkel2012-12-251-0/+22
* Expand PPC64 atomic load and storeHal Finkel2012-12-251-0/+20
* [msan] Fix handling of vectors of pointers.Evgeniy Stepanov2012-12-251-0/+15
* [msan] Fix handling of select with vector condition.Evgeniy Stepanov2012-12-251-0/+17
* Harden test so it's not affected by changes to compare lowering.Benjamin Kramer2012-12-251-1/+1
* X86: Shave off one shuffle from the pcmpeqq sequence for SSE2 by making use o...Benjamin Kramer2012-12-251-4/+2
* X86: Custom lower <2 x i64> eq and ne when SSE41 is not available.Benjamin Kramer2012-12-251-0/+26
* Fix typo "Makre" -> "Make".Nick Lewycky2012-12-241-6/+4
* llvm/test/CodeGen/X86/fold-vex.ll: Add explicit triple.NAKAMURA Takumi2012-12-241-1/+1
* Some x86 instructions can load/store one of the operands to memory. On SSE, t...Nadav Rotem2012-12-241-0/+16
* LoopVectorizer: When checking for vectorizable types, also checkNadav Rotem2012-12-241-0/+29
* LoopVectorizer: Fix an endless loop in the code that looks for reductions.Nadav Rotem2012-12-241-0/+44
* CostModel: Change the default target-independent implementation for findingNadav Rotem2012-12-231-3/+3
* We are not ready to estimate the cost of integer expansions based on the numb...Nadav Rotem2012-12-231-2/+0
* Loop Vectorizer: Update the cost model of scatter/gather operations and makeNadav Rotem2012-12-231-1/+4
* X86: Turn mul of <4 x i32> into pmuludq when no SSE4.1 is available.Benjamin Kramer2012-12-221-0/+14
* X86: Emit vector sext as shuffle + sra if vpmovsx is not available.Benjamin Kramer2012-12-221-23/+96
* In some cases, due to scheduling constraints we copy the EFLAGS.Nadav Rotem2012-12-211-0/+37
* [mips] Fix encoding of BAL instruction. Also, fix assembler test case whichAkira Hatanaka2012-12-211-1/+1
* try to unbreak ppc buildbots.Benjamin Kramer2012-12-211-4/+4
* X86: Match pmin/pmax as a target specific dag combine. This occurs during vec...Benjamin Kramer2012-12-212-3/+2790
* R600: Expand vec4 INT <-> FP conversionsTom Stellard2012-12-211-0/+52
* [msan] Remove unreachable blocks before instrumenting a function.Evgeniy Stepanov2012-12-211-0/+23
* Improve the X86 cost model for loads and stores.Nadav Rotem2012-12-212-2/+67
* Add test case for r170674Reed Kotler2012-12-211-0/+29
* Fix a bug in the code that checks if we can vectorize loops while using dynamicNadav Rotem2012-12-212-48/+110
* Move these files over to the debug info directory.Eric Christopher2012-12-212-0/+0
* Revert "Adding support for llvm.arm.neon.vaddl[su].* and"Bob Wilson2012-12-202-128/+0
* LoopVectorize: Fix a bug in the scalarization of instructions.Nadav Rotem2012-12-201-0/+48
* On some ARM cpus, flags setting movs with shifter operand, i.e. lsl, lsr, asr,Evan Cheng2012-12-201-13/+69
* Change Lit error redirection to FileCheck to a more common syntax since itEli Bendersky2012-12-206-6/+6
* Add a largish auto-generated test for the aligned bundling feature, along withEli Bendersky2012-12-201-0/+2674
* Tests for the aligned bundling support added in r170718Eli Bendersky2012-12-2013-0/+289
* Simplify the testcase a bit.Rafael Espindola2012-12-201-15/+4
* Add a new attribute, 'noduplicate'. If a function contains a noduplicate call...James Molloy2012-12-205-1/+168
* Adding support for llvm.arm.neon.vaddl[su].* andRenato Golin2012-12-202-0/+128
* fix most of remaining issues with large frames.Reed Kotler2012-12-201-2/+2
* [mips] Use "or $r0, $r1, $zero" instead of "addu $r0, $zero, $r1" to copyAkira Hatanaka2012-12-206-18/+18
* Do not introduce vector operations in functions marked with noimplicitfloat.Bob Wilson2012-12-201-0/+17
* Split out abbreviations for the skeleton info from the rest ofEric Christopher2012-12-191-0/+3
* LLVM sdisel normalize bit extraction of the form:Evan Cheng2012-12-191-0/+25
* Remove edis - the enhanced disassembler. Fixes PR14654.Roman Divacky2012-12-191-10/+0
* Transform (x&C)>V into (x&C)!=0 where possiblePaul Redmond2012-12-191-0/+17
* PowerPC: Expand VSELECT nodes.Benjamin Kramer2012-12-191-0/+7
* Make TargetLowering::getTypeConversion more resilient against odd illegal MVTs.Benjamin Kramer2012-12-191-0/+22
* [msan] Heuristically instrument unknown intrinsics.Evgeniy Stepanov2012-12-191-2/+74
* Optimized load + SIGN_EXTEND patterns in the X86 backend.Elena Demikhovsky2012-12-193-3/+98
* After reducing the size of an operation in the DAG we zero-extend the reducedNadav Rotem2012-12-191-0/+21
* Teach SimplifySetCC that comparing AssertZext i1 against a constant 1 can be ...Craig Topper2012-12-191-0/+15