From 334c26473bba3ad8b88341bb0d25d0ac2008bb8d Mon Sep 17 00:00:00 2001 From: David Goodwin Date: Wed, 8 Jul 2009 16:09:28 +0000 Subject: Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75010 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/Thumb1InstrInfo.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'lib/Target/ARM/Thumb1InstrInfo.h') diff --git a/lib/Target/ARM/Thumb1InstrInfo.h b/lib/Target/ARM/Thumb1InstrInfo.h index 1bfa1d0..67b78fb 100644 --- a/lib/Target/ARM/Thumb1InstrInfo.h +++ b/lib/Target/ARM/Thumb1InstrInfo.h @@ -27,6 +27,16 @@ class Thumb1InstrInfo : public ARMBaseInstrInfo { public: explicit Thumb1InstrInfo(const ARMSubtarget &STI); + // Return the non-pre/post incrementing version of 'Opc'. Return 0 + // if there is not such an opcode. + unsigned getUnindexedOpcode(unsigned Opc) const; + + // Return the opcode that implements 'Op', or 0 if no opcode + unsigned getOpcode(ARMII::Op Op) const; + + // Return true if the block does not fall through. + bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const; + /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As /// such, whenever a client has an instance of instruction info, it should /// always be able to get register info as well (through this method). -- cgit v1.1