From 56837864265a27fdecc85c85f4c1cec73845cc94 Mon Sep 17 00:00:00 2001 From: Logan Chien Date: Fri, 16 Dec 2011 17:38:39 +0800 Subject: Fix LOCAL_MODULE for tblgen rules. Change-Id: I844d8c5c8dcc86cbc5ec32c2ee442bf70bff0290 --- llvm-tblgen-rules.mk | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'llvm-tblgen-rules.mk') diff --git a/llvm-tblgen-rules.mk b/llvm-tblgen-rules.mk index d2cf568..b91fde9 100644 --- a/llvm-tblgen-rules.mk +++ b/llvm-tblgen-rules.mk @@ -32,100 +32,126 @@ endif # The directory and the .td directory is not the same. # ifeq ($(tblgen_source_dir),$(LLVM_ROOT_PATH)/lib/Target/ARM/MCTargetDesc) +$(intermediates)/%GenRegisterInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(intermediates)/%GenRegisterInfo.inc: $(tblgen_source_dir)/../%.td $(TBLGEN) $(call transform-td-to-out, register-info) + +$(intermediates)/%GenInstrInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(intermediates)/%GenInstrInfo.inc: $(tblgen_source_dir)/../%.td $(TBLGEN) $(call transform-td-to-out,instr-info) + +$(intermediates)/%GenSubtargetInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(intermediates)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/../%.td $(TBLGEN) $(call transform-td-to-out,subtarget) endif ifeq ($(tblgen_source_dir),$(LLVM_ROOT_PATH)/lib/Target/X86/MCTargetDesc) +$(intermediates)/%GenRegisterInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(intermediates)/%GenRegisterInfo.inc: $(tblgen_source_dir)/../%.td $(TBLGEN) $(call transform-td-to-out, register-info) + +$(intermediates)/%GenInstrInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(intermediates)/%GenInstrInfo.inc: $(tblgen_source_dir)/../%.td $(TBLGEN) $(call transform-td-to-out,instr-info) + +$(intermediates)/%GenSubtargetInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(intermediates)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/../%.td $(TBLGEN) $(call transform-td-to-out,subtarget) endif ifneq ($(filter %GenRegisterInfo.inc,$(tblgen_gen_tables)),) +$(intermediates)/%GenRegisterInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(intermediates)/%GenRegisterInfo.inc: $(tblgen_source_dir)/%.td $(TBLGEN) $(call transform-td-to-out,register-info) endif ifneq ($(filter %GenInstrInfo.inc,$(tblgen_gen_tables)),) +$(intermediates)/%GenInstrInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(intermediates)/%GenInstrInfo.inc: $(tblgen_source_dir)/%.td $(TBLGEN) $(call transform-td-to-out,instr-info) endif ifneq ($(filter %GenAsmWriter.inc,$(tblgen_gen_tables)),) +$(intermediates)/%GenAsmWriter.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(intermediates)/%GenAsmWriter.inc: $(tblgen_source_dir)/%.td $(TBLGEN) $(call transform-td-to-out,asm-writer) endif ifneq ($(filter %GenAsmWriter1.inc,$(tblgen_gen_tables)),) +$(intermediates)/%GenAsmWriter1.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(intermediates)/%GenAsmWriter1.inc: $(tblgen_source_dir)/%.td $(TBLGEN) $(call transform-td-to-out,asm-writer -asmwriternum=1) endif ifneq ($(filter %GenAsmMatcher.inc,$(tblgen_gen_tables)),) +$(intermediates)/%GenAsmMatcher.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(intermediates)/%GenAsmMatcher.inc: $(tblgen_source_dir)/%.td $(TBLGEN) $(call transform-td-to-out,asm-matcher) endif ifneq ($(filter %GenCodeEmitter.inc,$(tblgen_gen_tables)),) +$(intermediates)/%GenCodeEmitter.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(intermediates)/%GenCodeEmitter.inc: $(tblgen_source_dir)/%.td $(TBLGEN) $(call transform-td-to-out,emitter) endif ifneq ($(filter %GenMCCodeEmitter.inc,$(tblgen_gen_tables)),) +$(intermediates)/%GenMCCodeEmitter.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(intermediates)/%GenMCCodeEmitter.inc: $(tblgen_source_dir)/%.td $(TBLGEN) $(call transform-td-to-out,emitter -mc-emitter) endif ifneq ($(filter %GenMCPseudoLowering.inc,$(tblgen_gen_tables)),) +$(intermediates)/%GenMCPseudoLowering.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(intermediates)/%GenMCPseudoLowering.inc: $(tblgen_source_dir)/%.td $(TBLGEN) $(call transform-td-to-out,pseudo-lowering) endif ifneq ($(filter %GenDAGISel.inc,$(tblgen_gen_tables)),) +$(intermediates)/%GenDAGISel.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(intermediates)/%GenDAGISel.inc: $(tblgen_source_dir)/%.td $(TBLGEN) $(call transform-td-to-out,dag-isel) endif ifneq ($(filter %GenDisassemblerTables.inc,$(tblgen_gen_tables)),) +$(intermediates)/%GenDisassemblerTables.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(intermediates)/%GenDisassemblerTables.inc: $(tblgen_source_dir)/%.td $(TBLGEN) $(call transform-td-to-out,disassembler) endif ifneq ($(filter %GenEDInfo.inc,$(tblgen_gen_tables)),) +$(intermediates)/%GenEDInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(intermediates)/%GenEDInfo.inc: $(tblgen_source_dir)/%.td $(TBLGEN) $(call transform-td-to-out,enhanced-disassembly-info) endif ifneq ($(filter %GenFastISel.inc,$(tblgen_gen_tables)),) +$(intermediates)/%GenFastISel.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(intermediates)/%GenFastISel.inc: $(tblgen_source_dir)/%.td $(TBLGEN) $(call transform-td-to-out,fast-isel) endif ifneq ($(filter %GenSubtargetInfo.inc,$(tblgen_gen_tables)),) +$(intermediates)/%GenSubtargetInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(intermediates)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/%.td $(TBLGEN) $(call transform-td-to-out,subtarget) endif ifneq ($(filter %GenCallingConv.inc,$(tblgen_gen_tables)),) +$(intermediates)/%GenCallingConv.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(intermediates)/%GenCallingConv.inc: $(tblgen_source_dir)/%.td $(TBLGEN) $(call transform-td-to-out,callingconv) endif ifneq ($(filter %GenIntrinsics.inc,$(tblgen_gen_tables)),) +$(intermediates)/%GenIntrinsics.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(intermediates)/%GenIntrinsics.inc: $(tblgen_source_dir)/%.td $(TBLGEN) $(call transform-td-to-out,tgt_intrinsics) endif ifneq ($(findstring ARMGenDecoderTables.inc,$(tblgen_gen_tables)),) +$(intermediates)/ARMGenDecoderTables.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(intermediates)/ARMGenDecoderTables.inc: $(tblgen_source_dir)/ARM.td $(TBLGEN) $(call transform-td-to-out,arm-decoder) endif -- cgit v1.1