From 287c84a0b45cc826b1200f4cf4be3547d2fcd69c Mon Sep 17 00:00:00 2001 From: Tim Northover Date: Fri, 23 Aug 2013 10:16:39 +0000 Subject: ARM: make sure ARM-mode pseudo-inst requires IsARM I'd forgotten that "Requires" blocks override rather than add to the constraints, so my pseudo-instruction was being selected in Thumb mode leading to nonsense instructions. rdar://problem/14817358 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189096 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/Thumb2/thumb2-select.ll | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) (limited to 'test/CodeGen/Thumb2') diff --git a/test/CodeGen/Thumb2/thumb2-select.ll b/test/CodeGen/Thumb2/thumb2-select.ll index c4d4480..5f5fa19 100644 --- a/test/CodeGen/Thumb2/thumb2-select.ll +++ b/test/CodeGen/Thumb2/thumb2-select.ll @@ -99,8 +99,17 @@ entry: define i32 @f10(i32 %a, i32 %b) { ; CHECK-LABEL: f10: -; CHECK: movwne r2, #1234 @ encoding: [0x40,0xf2,0xd2,0x42] +; CHECK: movwne {{r[0-9]+}}, #1234 @ encoding: [0x40,0xf2,0xd2,0x4{{[0-9a-f]+}}] %tst = icmp ne i32 %a, %b %val = select i1 %tst, i32 1234, i32 12345 ret i32 %val } + +; Make sure we pick the Thumb encoding for movw/movt +define i32 @f11(i32 %a, i32 %b) { +; CHECK-LABEL: f11: +; CHECK: movwne {{r[0-9]+}}, #50033 @ encoding: [0x4c,0xf2,0x71,0x3{{[0-9a-f]+}}] + %tst = icmp ne i32 %a, %b + %val = select i1 %tst, i32 123454321, i32 543212345 + ret i32 %val +} -- cgit v1.1