From 43a6c5e2fccadb299c35cb3147d112f706922acd Mon Sep 17 00:00:00 2001 From: Bill Wendling Date: Tue, 31 Aug 2010 22:41:22 +0000 Subject: We have a chance for an optimization. Consider this code: int x(int t) { if (t & 256) return -26; return 0; } We generate this: tst.w r0, #256 mvn r0, #25 it eq moveq r0, #0 while gcc generates this: ands r0, r0, #256 it ne mvnne r0, #25 bx lr Scandalous really! During ISel time, we can look for this particular pattern. One where we have a "MOVCC" that uses the flag off of a CMPZ that itself is comparing an AND instruction to 0. Something like this (greatly simplified): %r0 = ISD::AND ... ARMISD::CMPZ %r0, 0 @ sets [CPSR] %r0 = ARMISD::MOVCC 0, -26 @ reads [CPSR] All we have to do is convert the "ISD::AND" into an "ARM::ANDS" that sets [CPSR] when it's zero. The zero value will all ready be in the %r0 register and we only need to change it if the AND wasn't zero. Easy! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112664 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/Thumb2/thumb2-mvncc.ll | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 test/CodeGen/Thumb2/thumb2-mvncc.ll (limited to 'test/CodeGen/Thumb2') diff --git a/test/CodeGen/Thumb2/thumb2-mvncc.ll b/test/CodeGen/Thumb2/thumb2-mvncc.ll new file mode 100644 index 0000000..893728b --- /dev/null +++ b/test/CodeGen/Thumb2/thumb2-mvncc.ll @@ -0,0 +1,13 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s + +define i32 @f1(i32 %t) nounwind { +; CHECK: f1 +; CHECK-NOT: tst +; CHECK: ands +; CHECK: it ne +; CHECK: mvnne + %and = and i32 %t, 256 + %tobool = icmp eq i32 %and, 0 + %retval.0 = select i1 %tobool, i32 0, i32 -26 + ret i32 %retval.0 +} -- cgit v1.1