From 87773c318fcee853fb34a80a10c4347d523bdafb Mon Sep 17 00:00:00 2001 From: Tim Northover Date: Thu, 1 Aug 2013 09:20:35 +0000 Subject: AArch64: add initial NEON support Patch by Ana Pazos. - Completed implementation of instruction formats: AdvSIMD three same AdvSIMD modified immediate AdvSIMD scalar pairwise - Completed implementation of instruction classes (some of the instructions in these classes belong to yet unfinished instruction formats): Vector Arithmetic Vector Immediate Vector Pairwise Arithmetic - Initial implementation of instruction formats: AdvSIMD scalar two-reg misc AdvSIMD scalar three same - Intial implementation of instruction class: Scalar Arithmetic - Initial clang changes to support arm v8 intrinsics. Note: no clang changes for scalar intrinsics function name mangling yet. - Comprehensive test cases for added instructions To verify auto codegen, encoding, decoding, diagnosis, intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187567 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/MC/AArch64/neon-bitwise-instructions.s | 60 +++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 test/MC/AArch64/neon-bitwise-instructions.s (limited to 'test/MC/AArch64/neon-bitwise-instructions.s') diff --git a/test/MC/AArch64/neon-bitwise-instructions.s b/test/MC/AArch64/neon-bitwise-instructions.s new file mode 100644 index 0000000..79d0a9b --- /dev/null +++ b/test/MC/AArch64/neon-bitwise-instructions.s @@ -0,0 +1,60 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + +//------------------------------------------------------------------------------ +// Vector And +//------------------------------------------------------------------------------ + and v0.8b, v1.8b, v2.8b + and v0.16b, v1.16b, v2.16b + +// CHECK: and v0.8b, v1.8b, v2.8b // encoding: [0x20,0x1c,0x22,0x0e] +// CHECK: and v0.16b, v1.16b, v2.16b // encoding: [0x20,0x1c,0x22,0x4e] + + +//------------------------------------------------------------------------------ +// Vector Orr +//------------------------------------------------------------------------------ + orr v0.8b, v1.8b, v2.8b + orr v0.16b, v1.16b, v2.16b + +// CHECK: orr v0.8b, v1.8b, v2.8b // encoding: [0x20,0x1c,0xa2,0x0e] +// CHECK: orr v0.16b, v1.16b, v2.16b // encoding: [0x20,0x1c,0xa2,0x4e] + + +//------------------------------------------------------------------------------ +// Vector Eor +//------------------------------------------------------------------------------ + eor v0.8b, v1.8b, v2.8b + eor v0.16b, v1.16b, v2.16b + +// CHECK: eor v0.8b, v1.8b, v2.8b // encoding: [0x20,0x1c,0x22,0x2e] +// CHECK: eor v0.16b, v1.16b, v2.16b // encoding: [0x20,0x1c,0x22,0x6e] + + +//---------------------------------------------------------------------- +// Vector Bitwise +//---------------------------------------------------------------------- + + bit v0.8b, v1.8b, v2.8b + bit v0.16b, v1.16b, v2.16b + bif v0.8b, v1.8b, v2.8b + bif v0.16b, v1.16b, v2.16b + bsl v0.8b, v1.8b, v2.8b + bsl v0.16b, v1.16b, v2.16b + orn v0.8b, v1.8b, v2.8b + orn v0.16b, v1.16b, v2.16b + bic v0.8b, v1.8b, v2.8b + bic v0.16b, v1.16b, v2.16b + +// CHECK: bit v0.8b, v1.8b, v2.8b // encoding: [0x20,0x1c,0xa2,0x2e] +// CHECK: bit v0.16b, v1.16b, v2.16b // encoding: [0x20,0x1c,0xa2,0x6e] +// CHECK: bif v0.8b, v1.8b, v2.8b // encoding: [0x20,0x1c,0xe2,0x2e] +// CHECK: bif v0.16b, v1.16b, v2.16b // encoding: [0x20,0x1c,0xe2,0x6e] +// CHECK: bsl v0.8b, v1.8b, v2.8b // encoding: [0x20,0x1c,0x62,0x2e] +// CHECK: bsl v0.16b, v1.16b, v2.16b // encoding: [0x20,0x1c,0x62,0x6e] +// CHECK: orn v0.8b, v1.8b, v2.8b // encoding: [0x20,0x1c,0xe2,0x0e] +// CHECK: orn v0.16b, v1.16b, v2.16b // encoding: [0x20,0x1c,0xe2,0x4e] +// CHECK: bic v0.8b, v1.8b, v2.8b // encoding: [0x20,0x1c,0x62,0x0e] +// CHECK: bic v0.16b, v1.16b, v2.16b // encoding: [0x20,0x1c,0x62,0x4e] + -- cgit v1.1