From 342e3161d9dd4fa485b47788aa0266f9c91c3832 Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Tue, 30 Aug 2011 01:34:54 +0000 Subject: Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical register dependency (rather than glue them together). This is general goodness as it gives scheduler more freedom. However it is motivated by a nasty bug in isel. When a i64 sub is expanded to subc + sube. libcall #1 \ \ subc \ / \ \ / \ \ / libcall #2 sube If the libcalls are not serialized (i.e. both have chains which are dag entry), legalizer can serialize them in arbitrary orders. If it's unlucky, it can force libcall #2 before libcall #1 in the above case. subc | libcall #2 | libcall #1 | sube However since subc and sube are "glued" together, this ends up being a cycle when the scheduler combine subc and sube as a single scheduling unit. The right solution is to fix LegalizeType too chains the libcalls together. However, LegalizeType is not processing nodes in order so that's harder than it should be. For now, the move to physical register dependency will do. rdar://10019576 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138791 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/ARM/2011-08-29-SchedCycle.ll | 45 +++++++++++++++++++++++++++ test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll | 4 +-- 2 files changed, 47 insertions(+), 2 deletions(-) create mode 100644 test/CodeGen/ARM/2011-08-29-SchedCycle.ll (limited to 'test') diff --git a/test/CodeGen/ARM/2011-08-29-SchedCycle.ll b/test/CodeGen/ARM/2011-08-29-SchedCycle.ll new file mode 100644 index 0000000..be188ef --- /dev/null +++ b/test/CodeGen/ARM/2011-08-29-SchedCycle.ll @@ -0,0 +1,45 @@ +; RUN: llc %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -o - + +; When a i64 sub is expanded to subc + sube. +; libcall #1 +; \ +; \ subc +; \ / \ +; \ / \ +; \ / libcall #2 +; sube +; +; If the libcalls are not serialized (i.e. both have chains which are dag +; entry), legalizer can serialize them in arbitrary orders. If it's +; unlucky, it can force libcall #2 before libcall #1 in the above case. +; +; subc +; | +; libcall #2 +; | +; libcall #1 +; | +; sube +; +; However since subc and sube are "glued" together, this ends up being a +; cycle when the scheduler combine subc and sube as a single scheduling +; unit. +; +; The right solution is to fix LegalizeType too chains the libcalls together. +; However, LegalizeType is not processing nodes in order. The fix now is to +; fix subc / sube (and addc / adde) to use physical register dependency instead. +; rdar://10019576 + +define void @t() nounwind { +entry: + %tmp = load i64* undef, align 4 + %tmp5 = udiv i64 %tmp, 30 + %tmp13 = and i64 %tmp5, 64739244643450880 + %tmp16 = sub i64 0, %tmp13 + %tmp19 = and i64 %tmp16, 63 + %tmp20 = urem i64 %tmp19, 3 + %tmp22 = and i64 %tmp16, -272346829004752 + store i64 %tmp22, i64* undef, align 4 + store i64 %tmp20, i64* undef, align 4 + ret void +} diff --git a/test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll b/test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll index 8ca001c..ff45509 100644 --- a/test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll +++ b/test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll @@ -6,8 +6,8 @@ entry: ; -- The loop following the load should only use a single add-literation ; instruction. ; CHECK: ldr.64 -; CHECK: adds r{{[0-9]+}}, #1 -; CHECK-NOT: adds r{{[0-9]+}}, #1 +; CHECK: adds r{{[0-9]+}}, r{{[0-9]+}}, #1 +; CHECK-NOT: adds r{{[0-9]+}}, r{{[0-9]+}}, #1 ; CHECK: subsections_via_symbols -- cgit v1.1