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; RUN: llc < %s -march=arm64 -mcpu=cyclone | FileCheck %s
define i128 @shl(i128 %r, i128 %s) nounwind readnone {
; CHECK-LABEL: shl:
; CHECK: lslv [[XREG_0:x[0-9]+]], x1, x2
; CHECK-NEXT: orr [[XREG_1:x[0-9]+]], xzr, #0x40
; CHECK-NEXT: sub [[XREG_2:x[0-9]+]], [[XREG_1]], x2
; CHECK-NEXT: lsrv [[XREG_3:x[0-9]+]], x0, [[XREG_2]]
; CHECK-NEXT: orr [[XREG_6:x[0-9]+]], [[XREG_3]], [[XREG_0]]
; CHECK-NEXT: sub [[XREG_4:x[0-9]+]], x2, #64
; CHECK-NEXT: lslv [[XREG_5:x[0-9]+]], x0, [[XREG_4]]
; CHECK-NEXT: cmp [[XREG_4]], #0
; CHECK-NEXT: csel x1, [[XREG_5]], [[XREG_6]], ge
; CHECK-NEXT: lslv [[SMALLSHIFT_LO:x[0-9]+]], x0, x2
; CHECK-NEXT: csel x0, xzr, [[SMALLSHIFT_LO]], ge
; CHECK-NEXT: ret
%shl = shl i128 %r, %s
ret i128 %shl
}
define i128 @ashr(i128 %r, i128 %s) nounwind readnone {
; CHECK: ashr:
; CHECK: lsrv [[XREG_0:x[0-9]+]], x0, x2
; CHECK-NEXT: orr [[XREG_1:x[0-9]+]], xzr, #0x40
; CHECK-NEXT: sub [[XREG_2:x[0-9]+]], [[XREG_1]], x2
; CHECK-NEXT: lslv [[XREG_3:x[0-9]+]], x1, [[XREG_2]]
; CHECK-NEXT: orr [[XREG_4:x[0-9]+]], [[XREG_0]], [[XREG_3]]
; CHECK-NEXT: sub [[XREG_5:x[0-9]+]], x2, #64
; CHECK-NEXT: asrv [[XREG_6:x[0-9]+]], x1, [[XREG_5]]
; CHECK-NEXT: cmp [[XREG_5]], #0
; CHECK-NEXT: csel x0, [[XREG_6]], [[XREG_4]], ge
; CHECK-NEXT: asrv [[SMALLSHIFT_HI:x[0-9]+]], x1, x2
; CHECK-NEXT: asr [[BIGSHIFT_HI:x[0-9]+]], x1, #63
; CHECK-NEXT: csel x1, [[BIGSHIFT_HI]], [[SMALLSHIFT_HI]], ge
; CHECK-NEXT: ret
%shr = ashr i128 %r, %s
ret i128 %shr
}
define i128 @lshr(i128 %r, i128 %s) nounwind readnone {
; CHECK: lshr:
; CHECK: lsrv [[XREG_0:x[0-9]+]], x0, x2
; CHECK-NEXT: orr [[XREG_1:x[0-9]+]], xzr, #0x40
; CHECK-NEXT: sub [[XREG_2:x[0-9]+]], [[XREG_1]], x2
; CHECK-NEXT: lslv [[XREG_3:x[0-9]+]], x1, [[XREG_2]]
; CHECK-NEXT: orr [[XREG_4:x[0-9]+]], [[XREG_0]], [[XREG_3]]
; CHECK-NEXT: sub [[XREG_5:x[0-9]+]], x2, #64
; CHECK-NEXT: lsrv [[XREG_6:x[0-9]+]], x1, [[XREG_5]]
; CHECK-NEXT: cmp [[XREG_5]], #0
; CHECK-NEXT: csel x0, [[XREG_6]], [[XREG_4]], ge
; CHECK-NEXT: lsrv [[SMALLSHIFT_HI:x[0-9]+]], x1, x2
; CHECK-NEXT: csel x1, xzr, [[SMALLSHIFT_HI]], ge
; CHECK-NEXT: ret
%shr = lshr i128 %r, %s
ret i128 %shr
}
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