1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
|
; Test f32 conditional stores that are presented as selects.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
declare void @foo(float *)
; Test with the loaded value first.
define void @f1(float *%ptr, float %alt, i32 %limit) {
; CHECK-LABEL: f1:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; CHECK: ste %f0, 0(%r2)
; CHECK: [[LABEL]]:
; CHECK: br %r14
%cond = icmp ult i32 %limit, 420
%orig = load float , float *%ptr
%res = select i1 %cond, float %orig, float %alt
store float %res, float *%ptr
ret void
}
; ...and with the loaded value second
define void @f2(float *%ptr, float %alt, i32 %limit) {
; CHECK-LABEL: f2:
; CHECK-NOT: %r2
; CHECK: jhe [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; CHECK: ste %f0, 0(%r2)
; CHECK: [[LABEL]]:
; CHECK: br %r14
%cond = icmp ult i32 %limit, 420
%orig = load float , float *%ptr
%res = select i1 %cond, float %alt, float %orig
store float %res, float *%ptr
ret void
}
; Check the high end of the aligned STE range.
define void @f3(float *%base, float %alt, i32 %limit) {
; CHECK-LABEL: f3:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; CHECK: ste %f0, 4092(%r2)
; CHECK: [[LABEL]]:
; CHECK: br %r14
%ptr = getelementptr float, float *%base, i64 1023
%cond = icmp ult i32 %limit, 420
%orig = load float , float *%ptr
%res = select i1 %cond, float %orig, float %alt
store float %res, float *%ptr
ret void
}
; Check the next word up, which should use STEY instead of STE.
define void @f4(float *%base, float %alt, i32 %limit) {
; CHECK-LABEL: f4:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; CHECK: stey %f0, 4096(%r2)
; CHECK: [[LABEL]]:
; CHECK: br %r14
%ptr = getelementptr float, float *%base, i64 1024
%cond = icmp ult i32 %limit, 420
%orig = load float , float *%ptr
%res = select i1 %cond, float %orig, float %alt
store float %res, float *%ptr
ret void
}
; Check the high end of the aligned STEY range.
define void @f5(float *%base, float %alt, i32 %limit) {
; CHECK-LABEL: f5:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; CHECK: stey %f0, 524284(%r2)
; CHECK: [[LABEL]]:
; CHECK: br %r14
%ptr = getelementptr float, float *%base, i64 131071
%cond = icmp ult i32 %limit, 420
%orig = load float , float *%ptr
%res = select i1 %cond, float %orig, float %alt
store float %res, float *%ptr
ret void
}
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f6(float *%base, float %alt, i32 %limit) {
; CHECK-LABEL: f6:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; CHECK: agfi %r2, 524288
; CHECK: ste %f0, 0(%r2)
; CHECK: [[LABEL]]:
; CHECK: br %r14
%ptr = getelementptr float, float *%base, i64 131072
%cond = icmp ult i32 %limit, 420
%orig = load float , float *%ptr
%res = select i1 %cond, float %orig, float %alt
store float %res, float *%ptr
ret void
}
; Check the low end of the STEY range.
define void @f7(float *%base, float %alt, i32 %limit) {
; CHECK-LABEL: f7:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; CHECK: stey %f0, -524288(%r2)
; CHECK: [[LABEL]]:
; CHECK: br %r14
%ptr = getelementptr float, float *%base, i64 -131072
%cond = icmp ult i32 %limit, 420
%orig = load float , float *%ptr
%res = select i1 %cond, float %orig, float %alt
store float %res, float *%ptr
ret void
}
; Check the next word down, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f8(float *%base, float %alt, i32 %limit) {
; CHECK-LABEL: f8:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; CHECK: agfi %r2, -524292
; CHECK: ste %f0, 0(%r2)
; CHECK: [[LABEL]]:
; CHECK: br %r14
%ptr = getelementptr float, float *%base, i64 -131073
%cond = icmp ult i32 %limit, 420
%orig = load float , float *%ptr
%res = select i1 %cond, float %orig, float %alt
store float %res, float *%ptr
ret void
}
; Check that STEY allows an index.
define void @f9(i64 %base, i64 %index, float %alt, i32 %limit) {
; CHECK-LABEL: f9:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; CHECK: stey %f0, 4096(%r3,%r2)
; CHECK: [[LABEL]]:
; CHECK: br %r14
%add1 = add i64 %base, %index
%add2 = add i64 %add1, 4096
%ptr = inttoptr i64 %add2 to float *
%cond = icmp ult i32 %limit, 420
%orig = load float , float *%ptr
%res = select i1 %cond, float %orig, float %alt
store float %res, float *%ptr
ret void
}
; Check that volatile loads are not matched.
define void @f10(float *%ptr, float %alt, i32 %limit) {
; CHECK-LABEL: f10:
; CHECK: le {{%f[0-5]}}, 0(%r2)
; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
; CHECK: [[LABEL]]:
; CHECK: ste {{%f[0-5]}}, 0(%r2)
; CHECK: br %r14
%cond = icmp ult i32 %limit, 420
%orig = load volatile float , float *%ptr
%res = select i1 %cond, float %orig, float %alt
store float %res, float *%ptr
ret void
}
; ...likewise stores. In this case we should have a conditional load into %f0.
define void @f11(float *%ptr, float %alt, i32 %limit) {
; CHECK-LABEL: f11:
; CHECK: jhe [[LABEL:[^ ]*]]
; CHECK: le %f0, 0(%r2)
; CHECK: [[LABEL]]:
; CHECK: ste %f0, 0(%r2)
; CHECK: br %r14
%cond = icmp ult i32 %limit, 420
%orig = load float , float *%ptr
%res = select i1 %cond, float %orig, float %alt
store volatile float %res, float *%ptr
ret void
}
; Try a frame index base.
define void @f12(float %alt, i32 %limit) {
; CHECK-LABEL: f12:
; CHECK: brasl %r14, foo@PLT
; CHECK-NOT: %r15
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r15
; CHECK: ste {{%f[0-9]+}}, {{[0-9]+}}(%r15)
; CHECK: [[LABEL]]:
; CHECK: brasl %r14, foo@PLT
; CHECK: br %r14
%ptr = alloca float
call void @foo(float *%ptr)
%cond = icmp ult i32 %limit, 420
%orig = load float , float *%ptr
%res = select i1 %cond, float %orig, float %alt
store float %res, float *%ptr
call void @foo(float *%ptr)
ret void
}
|
