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| author | Jason Ekstrand <jason.ekstrand@intel.com> | 2016-11-21 20:22:53 -0800 |
|---|---|---|
| committer | Emil Velikov <emil.l.velikov@gmail.com> | 2016-11-24 16:34:42 +0000 |
| commit | f77b0972232af2d53241983f020449d5cdbdfa9a (patch) | |
| tree | 65ad06654bc7735b3b486aca8fa46286680c51e1 | |
| parent | 6c87a21497330a4640156c2e3cc7536754ac3931 (diff) | |
| download | external_mesa3d-f77b0972232af2d53241983f020449d5cdbdfa9a.zip external_mesa3d-f77b0972232af2d53241983f020449d5cdbdfa9a.tar.gz external_mesa3d-f77b0972232af2d53241983f020449d5cdbdfa9a.tar.bz2 | |
anv/cmd_buffer: Emit a CS stall before setting a CS pipeline
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit f680a01ad4ed360b44cd1b9d3c447a95cedbccd5)
| -rw-r--r-- | src/intel/vulkan/genX_cmd_buffer.c | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index b844460..f1b5387 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -1418,8 +1418,20 @@ genX(cmd_buffer_flush_compute_state)(struct anv_cmd_buffer *cmd_buffer) genX(flush_pipeline_select_gpgpu)(cmd_buffer); - if (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE) + if (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE) { + /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE: + * + * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless + * the only bits that are changed are scoreboard related: Scoreboard + * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For + * these scoreboard related states, a MEDIA_STATE_FLUSH is + * sufficient." + */ + cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_CS_STALL_BIT; + genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer); + anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch); + } if ((cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_COMPUTE_BIT) || (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)) { |