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| author | Arve Hjønnevåg <arve@android.com> | 2012-11-30 17:05:40 -0800 |
|---|---|---|
| committer | Wolfgang Wiedmeyer <wolfgit@wiedmeyer.de> | 2016-09-27 02:50:40 +0200 |
| commit | 07521fe4fa4fa493e76856c2305f608fc966b35b (patch) | |
| tree | dc0ec29a06a4b07d30905ddb9cafe1687379a413 | |
| parent | 89c8472033a23319b42bdf219726f253d21cfe19 (diff) | |
| download | kernel_i9300_mainline-07521fe4fa4fa493e76856c2305f608fc966b35b.zip kernel_i9300_mainline-07521fe4fa4fa493e76856c2305f608fc966b35b.tar.gz kernel_i9300_mainline-07521fe4fa4fa493e76856c2305f608fc966b35b.tar.bz2 | |
ARM: decompressor: Flush tlb before swiching domain 0 to client mode
If the bootloader used a page table that is incompatible with domain 0
in client mode, and boots with the mmu on, then swithing domain 0 to
client mode causes a fault if we don't flush the tlb after updating
the page table pointer.
v2: Add ISB before loading dacr.
Signed-off-by: Arve Hjønnevåg <arve@android.com>
| -rw-r--r-- | arch/arm/boot/compressed/head.S | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index af11c2f..a4d2c24 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -781,6 +781,8 @@ __armv7_mmu_cache_on: bic r6, r6, #1 << 31 @ 32-bit translation system bic r6, r6, #3 << 0 @ use only ttbr0 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer + mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs + mcr p15, 0, r0, c7, c5, 4 @ ISB mcrne p15, 0, r1, c3, c0, 0 @ load domain access control mcrne p15, 0, r6, c2, c0, 2 @ load ttb control #endif |