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| author | Suresh Siddha <suresh.b.siddha@intel.com> | 2008-07-10 11:16:50 -0700 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2008-07-12 08:45:00 +0200 |
| commit | 32e1d0a0651004f5fe47f85a2a5c725ad579a90c (patch) | |
| tree | 370e2673d24d52e1339b74097cbe14463cb12898 | |
| parent | 1b374e4d6f8b3eb2fcd034fcc24ea8ba1dfde7aa (diff) | |
| download | kernel_samsung_smdk4412-32e1d0a0651004f5fe47f85a2a5c725ad579a90c.zip kernel_samsung_smdk4412-32e1d0a0651004f5fe47f85a2a5c725ad579a90c.tar.gz kernel_samsung_smdk4412-32e1d0a0651004f5fe47f85a2a5c725ad579a90c.tar.bz2 | |
x64, x2apic/intr-remap: cpuid bits for x2apic feature
cpuid feature for x2apic.
Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com>
Cc: akpm@linux-foundation.org
Cc: arjan@linux.intel.com
Cc: andi@firstfloor.org
Cc: ebiederm@xmission.com
Cc: jbarnes@virtuousgeek.org
Cc: steiner@sgi.com
Signed-off-by: Ingo Molnar <mingo@elte.hu>
| -rw-r--r-- | arch/x86/kernel/cpu/feature_names.c | 2 | ||||
| -rw-r--r-- | include/asm-x86/cpufeature.h | 2 |
2 files changed, 3 insertions, 1 deletions
diff --git a/arch/x86/kernel/cpu/feature_names.c b/arch/x86/kernel/cpu/feature_names.c index e43ad4a..0bf4d37 100644 --- a/arch/x86/kernel/cpu/feature_names.c +++ b/arch/x86/kernel/cpu/feature_names.c @@ -45,7 +45,7 @@ const char * const x86_cap_flags[NCAPINTS*32] = { /* Intel-defined (#2) */ "pni", NULL, NULL, "monitor", "ds_cpl", "vmx", "smx", "est", "tm2", "ssse3", "cid", NULL, NULL, "cx16", "xtpr", NULL, - NULL, NULL, "dca", "sse4_1", "sse4_2", NULL, NULL, "popcnt", + NULL, NULL, "dca", "sse4_1", "sse4_2", "x2apic", NULL, "popcnt", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* VIA/Cyrix/Centaur-defined */ diff --git a/include/asm-x86/cpufeature.h b/include/asm-x86/cpufeature.h index 75ef959..5be9510 100644 --- a/include/asm-x86/cpufeature.h +++ b/include/asm-x86/cpufeature.h @@ -90,6 +90,7 @@ #define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */ #define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */ #define X86_FEATURE_DCA (4*32+18) /* Direct Cache Access */ +#define X86_FEATURE_X2APIC (4*32+21) /* x2APIC */ /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ #define X86_FEATURE_XSTORE (5*32+ 2) /* on-CPU RNG present (xstore insn) */ @@ -188,6 +189,7 @@ extern const char * const x86_power_flags[32]; #define cpu_has_gbpages boot_cpu_has(X86_FEATURE_GBPAGES) #define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON) #define cpu_has_pat boot_cpu_has(X86_FEATURE_PAT) +#define cpu_has_x2apic boot_cpu_has(X86_FEATURE_X2APIC) #if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64) # define cpu_has_invlpg 1 |