diff options
author | Eric Miao <eric.miao@marvell.com> | 2008-12-08 18:35:03 +0800 |
---|---|---|
committer | Eric Miao <eric.miao@marvell.com> | 2008-12-17 22:50:40 +0800 |
commit | c1f99c215c58111629984a49ba87b2b145dd1f5b (patch) | |
tree | ac3fd086d2d4f822b524e263fca5f18838ec20d4 /arch/arm/configs/clps7500_defconfig | |
parent | 07df1c4fea1474ae6db2c8554d2915cf5cf81369 (diff) | |
download | kernel_samsung_smdk4412-c1f99c215c58111629984a49ba87b2b145dd1f5b.zip kernel_samsung_smdk4412-c1f99c215c58111629984a49ba87b2b145dd1f5b.tar.gz kernel_samsung_smdk4412-c1f99c215c58111629984a49ba87b2b145dd1f5b.tar.bz2 |
[ARM] pxafb: allow better platform configurable smart panel timing
For smart panels (LCD panel with internal framebuffer), the following
LCCR3 register bits have different meanings than the parallel one:
LCCR3_PCP - controls the L_PCLK_WR polarity
LCCR3_HSP - controls the L_LCLK_A0 polarity
LCCR3_VSP - controls the L_FCLK_RD polarity
To keep minimum change to the original parallel timing, the .lcd_conn
flags and 'pxafb_mode_info.sync' are re-used to reflect this:
LCD_PCLK_EDGE_{RISE,FALL} - configures LCCR3_PCP
sync & FB_SYNC_{HOR,VERT}_HIGH_ACT - configures LCCR3_{HSP,VSP}
Signed-off-by: Eric Miao <eric.miao@marvell.com>
Diffstat (limited to 'arch/arm/configs/clps7500_defconfig')
0 files changed, 0 insertions, 0 deletions