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| author | Nicolas Ferre <nicolas.ferre@atmel.com> | 2010-06-21 14:59:27 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-07-09 12:31:50 +0100 |
| commit | 7dca3343fc5ae5af2fa9248057cd65077a5576e1 (patch) | |
| tree | 973030fa645ffe756cde695dd069768a42e52486 /arch/arm/mach-at91/include/mach/at91cap9.h | |
| parent | 5f9f0a412f16b2b849624f1b760477fb35ceff4a (diff) | |
| download | kernel_samsung_smdk4412-7dca3343fc5ae5af2fa9248057cd65077a5576e1.zip kernel_samsung_smdk4412-7dca3343fc5ae5af2fa9248057cd65077a5576e1.tar.gz kernel_samsung_smdk4412-7dca3343fc5ae5af2fa9248057cd65077a5576e1.tar.bz2 | |
ARM: 6185/1: AT91: PM: dual ram controller support
This rework allows to address tow memory controllers. AT91SAM9263 and
AT91SAM9G45 family have tow SDRAM or DDR/SDRAM controllers. Power management
should take care of this.
This patch modify the way RAM IP header files are implemented to allow
access to registers of both controllers ; it also adds some macros.
We also modify the power management files to use those modified header files.
Slow clock (assembly) and regular power management functions are synchronized
for setting of RAM self-refresh procedure:
(lpr & ~AT91_DDRSDRC_LPCB) | AT91_DDRSDRC_LPCB_SELF_REFRESH
Note that AT91RM9200 is not impacted by this modification.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Andrew Victor <linux@maxim.org.za>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-at91/include/mach/at91cap9.h')
| -rw-r--r-- | arch/arm/mach-at91/include/mach/at91cap9.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-at91/include/mach/at91cap9.h b/arch/arm/mach-at91/include/mach/at91cap9.h index d8c1ede..9c6af97 100644 --- a/arch/arm/mach-at91/include/mach/at91cap9.h +++ b/arch/arm/mach-at91/include/mach/at91cap9.h @@ -84,7 +84,7 @@ */ #define AT91_ECC (0xffffe200 - AT91_BASE_SYS) #define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS) -#define AT91_DDRSDRC (0xffffe600 - AT91_BASE_SYS) +#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) #define AT91_SMC (0xffffe800 - AT91_BASE_SYS) #define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) #define AT91_CCFG (0xffffeb10 - AT91_BASE_SYS) |