u1: import from CyanogenMod/android_kernel_samsung_smdk4210

Change-Id: I9629a4060538c9c4c6a43a86a56826cd7123d1b5

6 files changed, 728 insertions, 7 deletions

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index fb936b0..e53a6f0 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -871,6 +871,10 @@ config MACH_Q1_BD
 	bool "Q1 Board"
 
 endchoice
+config TARGET_LOCALE_NAATT_TEMP
+    bool "Support North America GSM ATT Board"
+	depends on MACH_U1
+    default n
 
 config MACH_PX
 	bool "PX board"
@@ -1712,6 +1716,12 @@ config SEC_MODEM_T0_TD_DUAL
 	select TDSCDMA_MODEM_SPRD8803
 	select LINK_DEVICE_SPI
 
+config SEC_MODEM_U1_SPR
+        bool "U1 with qsc6085"
+        select CDMA_MODEM_QSC6085
+        select LINK_DEVICE_DPRAM
+        select INTERNAL_MODEM_IF
+
 endchoice
 
 endif
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 7c710bb..804e3b2 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -287,6 +287,7 @@ obj-$(CONFIG_SEC_MODEM_M1)		+= board-c1-modems.o
 obj-$(CONFIG_SEC_MODEM_C1)		+= board-c1-modems.o
 obj-$(CONFIG_SEC_MODEM_C1_LGT)		+= board-c1lgt-modems.o
 obj-$(CONFIG_SEC_MODEM_U1)		+= board-u1-modems.o
+obj-$(CONFIG_SEC_MODEM_U1_SPR)		+= board-u1-spr-modems.o
 obj-$(CONFIG_SEC_MODEM_U1_LGT)		+= board-u1-lgt-modems.o
 obj-$(CONFIG_SEC_MODEM_P8LTE)		+= board-p8ltevzw-modems.o
 obj-$(CONFIG_SEC_DEBUG)			+= sec_debug.o sec_getlog.o sec_gaf.o
diff --git a/arch/arm/mach-exynos/board-u1-spr-modems.c b/arch/arm/mach-exynos/board-u1-spr-modems.c
new file mode 100644
index 0000000..b38533e
--- /dev/null
+++ b/arch/arm/mach-exynos/board-u1-spr-modems.c
@@ -0,0 +1,557 @@
+/* linux/arch/arm/mach-xxxx/board-u1-spr-modem.c
+ * Copyright (C) 2010 Samsung Electronics. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+#include <linux/regulator/consumer.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/interrupt.h>
+
+/* inlcude platform specific file */
+#include <linux/platform_data/modem_na_spr.h>
+#include <mach/gpio.h>
+#include <plat/gpio-cfg.h>
+
+static int __init init_modem(void);
+
+
+#define IDPRAM_SIZE	0x4000
+#define IDPRAM_PHY_START	0x13A00000
+#define IDPRAM_PHY_END (IDPRAM_PHY_START + IDPRAM_SIZE)
+
+/*S5PV210 Interanl Dpram Special Function Register*/
+#define IDPRAM_MIFCON_INT2APEN      (1<<2)
+#define IDPRAM_MIFCON_INT2MSMEN     (1<<3)
+#define IDPRAM_MIFCON_DMATXREQEN_0  (1<<16)
+#define IDPRAM_MIFCON_DMATXREQEN_1  (1<<17)
+#define IDPRAM_MIFCON_DMARXREQEN_0  (1<<18)
+#define IDPRAM_MIFCON_DMARXREQEN_1  (1<<19)
+#define IDPRAM_MIFCON_FIXBIT        (1<<20)
+
+#define IDPRAM_MIFPCON_ADM_MODE     (1<<6) /* mux / demux mode  */
+
+#define IDPRAM_DMA_ADR_MASK         0x3FFF
+#define IDPRAM_DMA_TX_ADR_0         /* shift 0 */
+#define IDPRAM_DMA_TX_ADR_1         /* shift 16  */
+#define IDPRAM_DMA_RX_ADR_0         /* shift 0  */
+#define IDPRAM_DMA_RX_ADR_1         /* shift 16  */
+
+#define IDPRAM_SFR_PHYSICAL_ADDR 0x13A08000
+#define IDPRAM_SFR_SIZE 0x1C
+
+/*#define IDPRAM_ADDRESS_DEMUX*/
+
+struct idpram_sfr_reg {
+	unsigned int2ap;
+	unsigned int2msm;
+	unsigned mifcon;
+	unsigned mifpcon;
+	unsigned msmintclr;
+	unsigned dma_tx_adr;
+	unsigned dma_rx_adr;
+};
+
+/*S5PV210 Internal Dpram GPIO table*/
+struct idpram_gpio_data {
+	unsigned num;
+	unsigned cfg;
+	unsigned pud;
+	unsigned val;
+};
+
+static volatile void __iomem *s5pv310_dpram_sfr_va;
+
+static struct idpram_gpio_data idpram_gpio_address[] = {
+#ifdef IDPRAM_ADDRESS_DEMUX
+	{
+		.num = EXYNOS4210_GPE1(0),	/* MSM_ADDR 0 -12 */
+		.cfg = S3C_GPIO_SFN(0x2),
+		.pud = S3C_GPIO_PULL_NONE,
+	}, {
+		.num = EXYNOS4210_GPE1(1),
+		.cfg = S3C_GPIO_SFN(0x2),
+		.pud = S3C_GPIO_PULL_NONE,
+	}, {
+		.num = EXYNOS4210_GPE1(2),
+		.cfg = S3C_GPIO_SFN(0x2),
+		.pud = S3C_GPIO_PULL_NONE,
+	}, {
+		.num = EXYNOS4210_GPE1(3),
+		.cfg = S3C_GPIO_SFN(0x2),
+		.pud = S3C_GPIO_PULL_NONE,
+	}, {
+		.num = EXYNOS4210_GPE1(4),
+		.cfg = S3C_GPIO_SFN(0x2),
+		.pud = S3C_GPIO_PULL_NONE,
+	}, {
+		.num = EXYNOS4210_GPE1(5),
+		.cfg = S3C_GPIO_SFN(0x2),
+		.pud = S3C_GPIO_PULL_NONE,
+	}, {
+		.num = EXYNOS4210_GPE1(6),
+		.cfg = S3C_GPIO_SFN(0x2),
+		.pud = S3C_GPIO_PULL_NONE,
+	}, {
+		.num = EXYNOS4210_GPE1(7),
+		.cfg = S3C_GPIO_SFN(0x2),
+		.pud = S3C_GPIO_PULL_NONE,
+	}, {
+		.num = EXYNOS4210_GPE2(0),
+		.cfg = S3C_GPIO_SFN(0x2),
+		.pud = S3C_GPIO_PULL_NONE,
+	}, {
+		.num = EXYNOS4210_GPE2(1),
+		.cfg = S3C_GPIO_SFN(0x2),
+		.pud = S3C_GPIO_PULL_NONE,
+	}, {
+		.num = EXYNOS4210_GPE2(2),
+		.cfg = S3C_GPIO_SFN(0x2),
+		.pud = S3C_GPIO_PULL_NONE,
+	}, {
+		.num = EXYNOS4210_GPE2(3),
+		.cfg = S3C_GPIO_SFN(0x2),
+		.pud = S3C_GPIO_PULL_NONE,
+	}, {
+		.num = EXYNOS4210_GPE2(4),
+		.cfg = S3C_GPIO_SFN(0x2),
+		.pud = S3C_GPIO_PULL_NONE,
+	}, {
+		.num = EXYNOS4210_GPE2(5),
+		.cfg = S3C_GPIO_SFN(0x2),
+		.pud = S3C_GPIO_PULL_NONE,
+	},
+#endif
+};
+
+static struct idpram_gpio_data idpram_gpio_data[] = {
+	{
+		.num = EXYNOS4210_GPE3(0), /* MSM_DATA 0 - 15 */
+		.cfg = S3C_GPIO_SFN(0x2),
+		.pud = S3C_GPIO_PULL_NONE,
+	}, {
+		.num = EXYNOS4210_GPE3(1),
+		.cfg = S3C_GPIO_SFN(0x2),
+		.pud = S3C_GPIO_PULL_NONE,
+	}, {
+		.num = EXYNOS4210_GPE3(2),
+		.cfg = S3C_GPIO_SFN(0x2),
+		.pud = S3C_GPIO_PULL_NONE,
+	}, {
+		.num = EXYNOS4210_GPE3(3),
+		.cfg = S3C_GPIO_SFN(0x2),
+		.pud = S3C_GPIO_PULL_NONE,
+	}, {
+		.num = EXYNOS4210_GPE3(4),
+		.cfg = S3C_GPIO_SFN(0x2),
+		.pud = S3C_GPIO_PULL_NONE,
+	}, {
+		.num = EXYNOS4210_GPE3(5),
+		.cfg = S3C_GPIO_SFN(0x2),
+		.pud = S3C_GPIO_PULL_NONE,
+	}, {
+		.num = EXYNOS4210_GPE3(6),
+		.cfg = S3C_GPIO_SFN(0x2),
+		.pud = S3C_GPIO_PULL_NONE,
+	}, {
+		.num = EXYNOS4210_GPE3(7),
+		.cfg = S3C_GPIO_SFN(0x2),
+		.pud = S3C_GPIO_PULL_NONE,
+	}, {
+		.num = EXYNOS4210_GPE4(0),
+		.cfg = S3C_GPIO_SFN(0x2),
+		.pud = S3C_GPIO_PULL_NONE,
+	}, {
+		.num = EXYNOS4210_GPE4(1),
+		.cfg = S3C_GPIO_SFN(0x2),
+		.pud = S3C_GPIO_PULL_NONE,
+	}, {
+		.num = EXYNOS4210_GPE4(2),
+		.cfg = S3C_GPIO_SFN(0x2),
+		.pud = S3C_GPIO_PULL_NONE,
+	}, {
+		.num = EXYNOS4210_GPE4(3),
+		.cfg = S3C_GPIO_SFN(0x2),
+		.pud = S3C_GPIO_PULL_NONE,
+	}, {
+		.num = EXYNOS4210_GPE4(4),
+		.cfg = S3C_GPIO_SFN(0x2),
+		.pud = S3C_GPIO_PULL_NONE,
+	}, {
+		.num = EXYNOS4210_GPE4(5),
+		.cfg = S3C_GPIO_SFN(0x2),
+		.pud = S3C_GPIO_PULL_NONE,
+	}, {
+		.num = EXYNOS4210_GPE4(6),
+		.cfg = S3C_GPIO_SFN(0x2),
+		.pud = S3C_GPIO_PULL_NONE,
+	}, {
+		.num = EXYNOS4210_GPE4(7),
+		.cfg = S3C_GPIO_SFN(0x2),
+		.pud = S3C_GPIO_PULL_NONE,
+	},
+};
+
+static struct idpram_gpio_data idpram_gpio_init_control[] = {
+	{
+		.num = EXYNOS4210_GPE0(1), /* MDM_CSn */
+		.cfg = S3C_GPIO_SFN(0x2),
+		.pud = S3C_GPIO_PULL_NONE,
+	}, {
+		.num = EXYNOS4210_GPE0(0), /* MDM_WEn */
+		.cfg = S3C_GPIO_SFN(0x2),
+		.pud = S3C_GPIO_PULL_NONE,
+	}, {
+		.num = EXYNOS4210_GPE0(2), /* MDM_Rn */
+		.cfg = S3C_GPIO_SFN(0x2),
+		.pud = S3C_GPIO_PULL_NONE,
+	}, {
+		.num = EXYNOS4210_GPE0(3), /* MDM_IRQn */
+		.cfg = S3C_GPIO_SFN(0x2),
+		.pud = S3C_GPIO_PULL_UP,
+	},
+#ifndef IDPRAM_ADDRESS_DEMUX
+	{
+		.num = EXYNOS4210_GPE0(4), /* MDM_ADVN */
+		.cfg = S3C_GPIO_SFN(0x2),
+		.pud = S3C_GPIO_PULL_NONE,
+	},
+#endif
+};
+
+static void idpram_gpio_cfg(struct idpram_gpio_data *gpio)
+{
+	printk(KERN_DEBUG "idpram set gpio num=%d, cfg=0x%x, pud=%d, val=%d\n",
+		gpio->num, gpio->cfg, gpio->pud, gpio->val);
+
+	s3c_gpio_cfgpin(gpio->num, gpio->cfg);
+	s3c_gpio_setpull(gpio->num, gpio->pud);
+	if (gpio->val)
+		gpio_set_value(gpio->num, gpio->val);
+}
+
+static void idpram_gpio_init(void)
+{
+	int i;
+
+#ifdef IDPRAM_ADDRESS_DEMUX
+	for (i = 0; i < ARRAY_SIZE(idpram_gpio_address); i++)
+		idpram_gpio_cfg(&idpram_gpio_address[i]);
+#endif
+
+	for (i = 0; i < ARRAY_SIZE(idpram_gpio_data); i++)
+		idpram_gpio_cfg(&idpram_gpio_data[i]);
+
+	for (i = 0; i < ARRAY_SIZE(idpram_gpio_init_control); i++)
+		idpram_gpio_cfg(&idpram_gpio_init_control[i]);
+}
+
+static void idpram_sfr_init(void)
+{
+	volatile struct idpram_sfr_reg __iomem *sfr = s5pv310_dpram_sfr_va;
+
+	sfr->mifcon = (IDPRAM_MIFCON_FIXBIT | IDPRAM_MIFCON_INT2APEN |
+		IDPRAM_MIFCON_INT2MSMEN);
+#ifndef IDPRAM_ADDRESS_DEMUX
+	sfr->mifpcon = (IDPRAM_MIFPCON_ADM_MODE);
+#endif
+}
+
+static void idpram_init(void)
+{
+	struct clk *clk;
+
+	/* enable internal dpram clock */
+	clk = clk_get(NULL, "modem");
+	if (!clk)
+		pr_err("MIF: idpram failed to get clock %s\n", __func__);
+
+	clk_enable(clk);
+
+	if (!s5pv310_dpram_sfr_va) {
+		s5pv310_dpram_sfr_va = (struct idpram_sfr_reg __iomem *)
+		ioremap_nocache(IDPRAM_SFR_PHYSICAL_ADDR, IDPRAM_SFR_SIZE);
+		if (!s5pv310_dpram_sfr_va) {
+			printk(KERN_ERR "MIF: idpram_sfr_base io-remap fail\n");
+			/*iounmap(idpram_base);*/
+		}
+	}
+
+	idpram_sfr_init();
+}
+
+static void idpram_clr_intr(void)
+{
+	volatile struct idpram_sfr_reg __iomem *sfr = s5pv310_dpram_sfr_va;
+	sfr->msmintclr = 0xFF;
+}
+
+/*
+	magic_code +
+	access_enable +
+	fmt_tx_head + fmt_tx_tail + fmt_tx_buff +
+	raw_tx_head + raw_tx_tail + raw_tx_buff +
+	fmt_rx_head + fmt_rx_tail + fmt_rx_buff +
+	raw_rx_head + raw_rx_tail + raw_rx_buff +
+	padding +
+	mbx_cp2ap +
+	mbx_ap2cp
+ =	2 +
+	2 +
+	2 + 2 + 2044 +
+	2 + 2 + 6128 +
+	2 + 2 + 2044 +
+	2 + 2 + 6128 +
+	16 +
+	2 +
+	2
+ =	16384
+*/
+
+#define QSC_DP_FMT_TX_BUFF_SZ	1020
+#define QSC_DP_RAW_TX_BUFF_SZ	7160
+#define QSC_DP_FMT_RX_BUFF_SZ	1020
+#define QSC_DP_RAW_RX_BUFF_SZ	7160
+
+/*
+** CDMA target platform data
+*/
+static struct modem_io_t cdma_io_devices[] = {
+	[0] = {
+		.name = "cdma_boot0",
+		.id = 0x1,
+		.format = IPC_BOOT,
+		.io_type = IODEV_MISC,
+		.link = LINKDEV_DPRAM,
+	},
+	[1] = {
+		.name = "cdma_ipc0",
+		.id = 0x1,
+		.format = IPC_FMT,
+		.io_type = IODEV_MISC,
+		.link = LINKDEV_DPRAM,
+	},
+	[2] = {
+		.name = "cdma_rfs0",
+		.id = 0x33,		/* 0x13 (ch.id) | 0x20 (mask) */
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.link = LINKDEV_DPRAM,
+	},
+	[3] = {
+		.name = "cdma_multipdp",
+		.id = 0x1,
+		.format = IPC_MULTI_RAW,
+		.io_type = IODEV_DUMMY,
+		.link = LINKDEV_DPRAM,
+	},
+	[4] = {
+		.name = "cdma_rmnet0",
+		.id = 0x2A,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.link = LINKDEV_DPRAM,
+	},
+	[5] = {
+		.name = "cdma_rmnet1",
+		.id = 0x2B,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.link = LINKDEV_DPRAM,
+	},
+	[6] = {
+		.name = "cdma_rmnet2",
+		.id = 0x2C,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.link = LINKDEV_DPRAM,
+	},
+	[7] = {
+		.name = "cdma_rmnet3",
+		.id = 0x2D,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.link = LINKDEV_DPRAM,
+	},
+	[8] = {
+		.name = "cdma_rmnet4",
+		.id = 0x27,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.link = LINKDEV_DPRAM,
+	},
+	[9] = {
+		.name = "cdma_rmnet5", /* DM Port IO device */
+		.id = 0x3A,
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.link = LINKDEV_DPRAM,
+	},
+	[10] = {
+		.name = "cdma_rmnet6", /* AT CMD IO device */
+		.id = 0x31,
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.link = LINKDEV_DPRAM,
+	},
+	[11] = {
+		.name = "cdma_ramdump0",
+		.id = 0x1,
+		.format = IPC_RAMDUMP,
+		.io_type = IODEV_MISC,
+		.link = LINKDEV_DPRAM,
+	},
+};
+
+/* To get modem state, register phone active irq using resource */
+static struct modem_data cdma_modem_data = {
+	.name = "qsc6085",
+
+	.gpio_cp_on        = GPIO_QSC_PHONE_ON,
+	.gpio_cp_reset     = GPIO_QSC_PHONE_RST,
+	.gpio_pda_active   = GPIO_PDA_ACTIVE,
+	.gpio_phone_active = GPIO_QSC_PHONE_ACTIVE,
+	.gpio_ap_wakeup = GPIO_C210_DPRAM_INT_N,
+	.gpio_cp_dump_int = GPIO_CP_DUMP_INT,
+
+	.modem_net  = CDMA_NETWORK,
+	.modem_type = QC_QSC6085,
+	.link_type = LINKDEV_DPRAM,
+
+	.num_iodevs = ARRAY_SIZE(cdma_io_devices),
+	.iodevs     = cdma_io_devices,
+
+	.clear_intr = idpram_clr_intr,
+	.sfr_init = idpram_sfr_init,
+};
+
+static struct resource cdma_modem_res[] = {
+	[0] = {
+		.name = "dpram",
+		.start = IDPRAM_PHY_START,
+		.end = IDPRAM_PHY_END,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.name = "dpram_irq",
+		.start = IRQ_MODEM_IF,
+		.end = IRQ_MODEM_IF,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+/* if use more than one modem device, then set id num */
+static struct platform_device cdma_modem = {
+	.name = "modem_if",
+	.id = -1,
+	.num_resources = ARRAY_SIZE(cdma_modem_res),
+	.resource = cdma_modem_res,
+	.dev = {
+		.platform_data = &cdma_modem_data,
+	},
+};
+
+static void config_cdma_modem_gpio(void)
+{
+	int err;
+	unsigned gpio_cp_on = cdma_modem_data.gpio_cp_on;
+	unsigned gpio_cp_rst = cdma_modem_data.gpio_cp_reset;
+	unsigned gpio_pda_active = cdma_modem_data.gpio_pda_active;
+	unsigned gpio_phone_active = cdma_modem_data.gpio_phone_active;
+	unsigned gpio_ap_wakeup = cdma_modem_data.gpio_ap_wakeup;
+	unsigned gpio_cp_dump_int = cdma_modem_data.gpio_cp_dump_int;
+
+	pr_info("MIF: <%s>\n", __func__);
+
+	if (gpio_cp_on) {
+		err = gpio_request(gpio_cp_on, "QSC_ON");
+		if (err) {
+			pr_err("fail to request gpio %s\n", "QSC_ON");
+		} else {
+			gpio_direction_output(gpio_cp_on, 0);
+			s3c_gpio_setpull(gpio_cp_on, S3C_GPIO_PULL_NONE);
+		}
+	}
+
+	if (gpio_cp_rst) {
+		err = gpio_request(gpio_cp_rst, "QSC_RST");
+		if (err) {
+			pr_err("fail to request gpio %s\n", "QSC_RST");
+		} else {
+			gpio_direction_output(gpio_cp_rst, 0);
+			s3c_gpio_setpull(gpio_cp_rst, S3C_GPIO_PULL_NONE);
+			s5p_gpio_set_drvstr(gpio_cp_rst, S5P_GPIO_DRVSTR_LV4);
+		}
+	}
+
+	if (gpio_pda_active) {
+		err = gpio_request(gpio_pda_active, "PDA_ACTIVE");
+		if (err) {
+			pr_err("fail to request gpio %s\n", "PDA_ACTIVE");
+		} else {
+			gpio_direction_output(gpio_pda_active, 0);
+			s3c_gpio_setpull(gpio_pda_active, S3C_GPIO_PULL_NONE);
+		}
+	}
+
+	if (gpio_phone_active) {
+		err = gpio_request(gpio_phone_active, "PHONE_ACTIVE");
+		if (err) {
+			pr_err("fail to request gpio %s\n", "PHONE_ACTIVE");
+		} else {
+			s3c_gpio_cfgpin(gpio_phone_active, S3C_GPIO_SFN(0xF));
+			s3c_gpio_setpull(gpio_phone_active, S3C_GPIO_PULL_NONE);
+		}
+	}
+
+	if (gpio_ap_wakeup) {
+		err = gpio_request(gpio_ap_wakeup, "HOST_WAKEUP");
+		if (err) {
+			pr_err("fail to request gpio %s\n", "HOST_WAKEUP");
+		} else {
+			s3c_gpio_cfgpin(gpio_ap_wakeup, S3C_GPIO_SFN(0xF));
+			s3c_gpio_setpull(gpio_ap_wakeup, S3C_GPIO_PULL_NONE);
+		}
+	}
+
+	if (gpio_cp_dump_int) {
+		err = gpio_request(gpio_cp_dump_int, "CP_DUMP_INT");
+		if (err) {
+			pr_err("fail to request gpio %s\n", "CP_DUMP_INT");
+		} else {
+			s3c_gpio_cfgpin(gpio_cp_dump_int, S3C_GPIO_SFN(0xF));
+			s3c_gpio_setpull(gpio_cp_dump_int, S3C_GPIO_PULL_DOWN);
+		}
+	}
+}
+
+static int __init init_modem(void)
+{
+	pr_info("MIF : <%s>\n", __func__);
+
+	/* interanl dpram gpio configure */
+	idpram_gpio_init();
+	idpram_init();
+
+	config_cdma_modem_gpio();
+
+	platform_device_register(&cdma_modem);
+	return 0;
+}
+late_initcall(init_modem);
+/*device_initcall(init_modem);*/
diff --git a/arch/arm/mach-exynos/include/mach/gpio-u1.h b/arch/arm/mach-exynos/include/mach/gpio-u1.h
index 6b8abb2..f077824 100644
--- a/arch/arm/mach-exynos/include/mach/gpio-u1.h
+++ b/arch/arm/mach-exynos/include/mach/gpio-u1.h
@@ -234,6 +234,39 @@
 #define GPIO_USB_I2C_SCL        EXYNOS4_GPY1(0)
 #endif /* CONFIG_USBHUB_USB3803 */
 
+/* GPIOs for IDPRAM driver of U1_NA_SPR(Gaudi) */
+#if defined(CONFIG_MACH_U1_NA_SPR)
+#define S5PV310_GPE0_0_MDM_WEn          EXYNOS4210_GPE0(0)
+#define S5PV310_GPE0_1_MDM_CSn          EXYNOS4210_GPE0(1)
+#define S5PV310_GPE0_2_MDM_Rn           EXYNOS4210_GPE0(2)
+#define S5PV310_GPE0_3_MDM_IRQn         EXYNOS4210_GPE0(3)
+#define S5PV310_GPE0_4_MDM_ADVN         EXYNOS4210_GPE0(4)
+
+#define S5PV310_GPE3_0_MDM_DATA_0       EXYNOS4210_GPE3(0)
+#define S5PV310_GPE3_1_MDM_DATA_1       EXYNOS4210_GPE3(1)
+#define S5PV310_GPE3_2_MDM_DATA_2       EXYNOS4210_GPE3(2)
+#define S5PV310_GPE3_3_MDM_DATA_3       EXYNOS4210_GPE3(3)
+#define S5PV310_GPE3_4_MDM_DATA_4       EXYNOS4210_GPE3(4)
+#define S5PV310_GPE3_5_MDM_DATA_5       EXYNOS4210_GPE3(5)
+#define S5PV310_GPE3_6_MDM_DATA_6       EXYNOS4210_GPE3(6)
+#define S5PV310_GPE3_7_MDM_DATA_7       EXYNOS4210_GPE3(7)
+
+#define S5PV310_GPE4_0_MDM_DATA_8       EXYNOS4210_GPE4(0)
+#define S5PV310_GPE4_1_MDM_DATA_9       EXYNOS4210_GPE4(1)
+#define S5PV310_GPE4_2_MDM_DATA_10      EXYNOS4210_GPE4(2)
+#define S5PV310_GPE4_3_MDM_DATA_11      EXYNOS4210_GPE4(3)
+#define S5PV310_GPE4_4_MDM_DATA_12      EXYNOS4210_GPE4(4)
+#define S5PV310_GPE4_5_MDM_DATA_13      EXYNOS4210_GPE4(5)
+#define S5PV310_GPE4_6_MDM_DATA_14      EXYNOS4210_GPE4(6)
+#define S5PV310_GPE4_7_MDM_DATA_15      EXYNOS4210_GPE4(7)
+
+#define GPIO_QSC_PHONE_ON               EXYNOS4_GPC1(1)
+#define GPIO_QSC_PHONE_RST              EXYNOS4_GPX1(4)
+#define GPIO_QSC_PHONE_ACTIVE           EXYNOS4_GPX1(6)
+#define IRQ_QSC_PHONE_ACTIVE		GPIO_QSC_PHONE_ACTIVE
+#define GPIO_C210_DPRAM_INT_N           EXYNOS4_GPX1(0)
+#endif
+/* End */
 
 #define GPIO_WLAN_EN		EXYNOS4_GPL1(2)
 #define GPIO_WLAN_EN_AF		1
diff --git a/arch/arm/mach-exynos/mach-u1.c b/arch/arm/mach-exynos/mach-u1.c
index 7e1ef2f..5aea5a3 100644
--- a/arch/arm/mach-exynos/mach-u1.c
+++ b/arch/arm/mach-exynos/mach-u1.c
@@ -280,6 +280,22 @@ static struct s3c2410_uartcfg smdkc210_uartcfgs[] __initdata = {
  */
 
 #ifdef CONFIG_VIDEO_M5MO
+
+struct class *camera_class;
+
+static int __init camera_class_init(void)
+{
+	camera_class = class_create(THIS_MODULE, "camera");
+	if (IS_ERR(camera_class)) {
+		pr_err("Failed to create class(camera)!\n");
+		return PTR_ERR(camera_class);
+	}
+
+	return 0;
+}
+
+subsys_initcall(camera_class_init);
+
 #define CAM_CHECK_ERR_RET(x, msg)					\
 	if (unlikely((x) < 0)) {					\
 		printk(KERN_ERR "\nfail to %s: err = %d\n", msg, x);	\
@@ -305,7 +321,7 @@ static int m5mo_power_on(void)
 	struct regulator *regulator;
 	int ret = 0;
 
-	printk(KERN_DEBUG "%s: in\n", __func__);
+	printk(KERN_DEBUG "%s: in. hw=0x%X\n", __func__, system_rev);
 
 	ret = gpio_request(GPIO_CAM_VGA_nSTBY, "GPL2");
 	if (ret) {
@@ -1154,6 +1170,9 @@ static struct s5k5bafx_platform_data s5k5bafx_plat = {
 	.pixelformat = V4L2_PIX_FMT_UYVY,
 	.freq = 24000000,
 	.is_mipi = 1,
+	.streamoff_delay = S5K5BAFX_STREAMOFF_DELAY,
+	.init_streamoff = true,
+	.dbg_level = CAMDBG_LEVEL_DEFAULT,
 };
 
 static struct i2c_board_info s5k5bafx_i2c_info = {
@@ -3331,7 +3350,63 @@ static struct max8997_motor_data max8997_motor = {
 #endif
 #endif
 
-#ifdef CONFIG_MACH_U1_KOR_LGT
+#if defined(CONFIG_TARGET_LOCALE_NA)
+#define USB_PATH_AP	0
+#define USB_PATH_CP	       1
+#define USB_PATH_ALL	2
+extern int u1_get_usb_hub_path(void);
+static int max8997_muic_set_safeout(int path)
+{
+	struct regulator *regulator;
+	int hub_usb_path = u1_get_usb_hub_path();
+
+	if (hub_usb_path == USB_PATH_CP) {
+		regulator = regulator_get(NULL, "safeout1");
+		if (IS_ERR(regulator))
+			return -ENODEV;
+		if (regulator_is_enabled(regulator))
+			regulator_force_disable(regulator);
+		regulator_put(regulator);
+
+		regulator = regulator_get(NULL, "safeout2");
+		if (IS_ERR(regulator))
+			return -ENODEV;
+		if (!regulator_is_enabled(regulator))
+			regulator_enable(regulator);
+		regulator_put(regulator);
+	} else if (hub_usb_path == USB_PATH_AP) {
+		regulator = regulator_get(NULL, "safeout1");
+		if (IS_ERR(regulator))
+			return -ENODEV;
+		if (!regulator_is_enabled(regulator))
+			regulator_enable(regulator);
+		regulator_put(regulator);
+
+		regulator = regulator_get(NULL, "safeout2");
+		if (IS_ERR(regulator))
+			return -ENODEV;
+		if (regulator_is_enabled(regulator))
+			regulator_force_disable(regulator);
+		regulator_put(regulator);
+	} else if (hub_usb_path == USB_PATH_ALL) {
+		regulator = regulator_get(NULL, "safeout1");
+		if (IS_ERR(regulator))
+			return -ENODEV;
+		if (!regulator_is_enabled(regulator))
+			regulator_enable(regulator);
+		regulator_put(regulator);
+
+		regulator = regulator_get(NULL, "safeout2");
+		if (IS_ERR(regulator))
+			return -ENODEV;
+		if (!regulator_is_enabled(regulator))
+			regulator_enable(regulator);
+		regulator_put(regulator);
+	}
+
+	return 0;
+}
+#elif defined(CONFIG_MACH_U1_KOR_LGT)
 static int max8997_muic_set_safeout(int path)
 {
 	static int safeout2_enabled;
@@ -5020,9 +5095,9 @@ struct gpio_keys_button u1_buttons[] = {
 		.isr_hook = sec_debug_check_crash_key,
 		.debounce_interval = 10,
 	},			/* power key */
-#if !defined(CONFIG_MACH_U1_NA_SPR) && !defined(CONFIG_MACH_U1_NA_USCC)
+#if !defined(CONFIG_MACH_U1_NA_SPR) && !defined(CONFIG_MACH_U1_NA_USCC) && !defined(CONFIG_TARGET_LOCALE_NAATT_TEMP)
 	{
-		.code = KEY_HOMEPAGE,
+		.code = KEY_HOME,
 		.gpio = GPIO_OK_KEY,
 		.active_low = 1,
 		.type = EV_KEY,
@@ -5375,6 +5450,7 @@ static const u8 *mxt224_config[] = {
 #define MXT224E_BLEN_BATT		32
 #define MXT224E_T48_BLEN_BATT		0
 #define MXT224E_BLEN_CHRG		0
+#define MXT224E_T48_BLEN_CHRG		0
 #define MXT224E_MOVFILTER_BATT		14
 #define MXT224E_MOVFILTER_CHRG		46
 #define MXT224E_ACTVSYNCSPERX_NORMAL		29
@@ -6639,6 +6715,7 @@ static struct i2c_board_info i2c_devs16[] __initdata = {
 
 
 #ifdef CONFIG_S3C_DEV_I2C17_EMUL
+#ifdef CONFIG_USBHUB_USB3803
 /* I2C17_EMUL */
 static struct i2c_gpio_platform_data i2c17_platdata = {
 	.sda_pin = GPIO_USB_I2C_SDA,
@@ -6651,7 +6728,7 @@ struct platform_device s3c_device_i2c17 = {
 	.dev.platform_data = &i2c17_platdata,
 };
 
-
+#endif
 #endif /* CONFIG_S3C_DEV_I2C17_EMUL */
 
 #ifdef CONFIG_USBHUB_USB3803
@@ -7099,6 +7176,7 @@ static struct platform_device *smdkc210_devices[] __initdata = {
 #ifdef CONFIG_BATTERY_SAMSUNG
 	&samsung_device_battery,
 #endif
+
 #ifdef CONFIG_FB_S5P
 	&s3c_device_fb,
 #endif
@@ -7156,10 +7234,12 @@ static struct platform_device *smdkc210_devices[] __initdata = {
 #if defined(CONFIG_SMB136_CHARGER_Q1) || defined(CONFIG_SMB328_CHARGER)
 	&s3c_device_i2c19,	/* SMB136, SMB328 */
 #endif
+#if defined(CONFIG_USBHUB_USB3803)
 #if defined(CONFIG_S3C_DEV_I2C17_EMUL)
 	&s3c_device_i2c17,	/* USB HUB */
 #endif
 #endif
+#endif
 
 	/* consumer driver should resume after resuming i2c drivers */
 	&u1_regulator_consumer,
@@ -7818,10 +7898,12 @@ static void __init smdkc210_machine_init(void)
 						ARRAY_SIZE(i2c_devs19_emul));
 #endif
 #ifdef CONFIG_S3C_DEV_I2C17_EMUL
+#ifdef CONFIG_USBHUB_USB3803
 	i2c_register_board_info(17, i2c_devs17_emul,
 						ARRAY_SIZE(i2c_devs17_emul));
 #endif
 #endif
+#endif
 
 
 	/* 400 kHz for initialization of MMC Card  */
diff --git a/arch/arm/mach-exynos/u1-gpio.c b/arch/arm/mach-exynos/u1-gpio.c
index dd1385d..77bb925 100644
--- a/arch/arm/mach-exynos/u1-gpio.c
+++ b/arch/arm/mach-exynos/u1-gpio.c
@@ -211,7 +211,7 @@ static struct gpio_init_data u1_init_gpios[] = {
 		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1},
 #endif /*CONFIG_TARGET_LOCALE_NA*/
 
-#if defined(CONFIG_TARGET_LOCALE_NA)
+#if defined(CONFIG_TARGET_LOCALE_NA) || defined(CONFIG_TARGET_LOCALE_NAATT_TEMP)
 	/* NC*/
 	{EXYNOS4_GPX3(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_ZERO,
 		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
@@ -476,7 +476,12 @@ static unsigned int u1_sleep_gpio_table[][3] = {
 	{EXYNOS4_GPB(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
 	{EXYNOS4_GPB(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
 #else
+#if defined(CONFIG_TARGET_LOCALE_NAATT_TEMP)
+	{EXYNOS4_GPB(0), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_NONE},
+#else
 	{EXYNOS4_GPB(0), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+#endif
+
 #if defined(CONFIG_LEDS_GPIO)
 	{EXYNOS4_GPB(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
 #else /*CONFIG_LEDS_GPIO*/
@@ -490,7 +495,9 @@ static unsigned int u1_sleep_gpio_table[][3] = {
 	{EXYNOS4_GPB(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
 	{EXYNOS4_GPB(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
 #endif/*CONFIG_MACH_U1_NA_USCC*/
+#if !defined(CONFIG_TARGET_LOCAL_NA)
 	{EXYNOS4_GPB(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
 	{EXYNOS4_GPB(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
 #endif
 	{EXYNOS4_GPB(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
@@ -564,8 +571,10 @@ static unsigned int u1_sleep_gpio_table[][3] = {
 	{EXYNOS4210_GPE0(4), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
 #else
 	{EXYNOS4210_GPE0(3), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+#if !defined(CONFIG_TARGET_LOCAL_NA)
 	{EXYNOS4210_GPE0(4), S3C_GPIO_SLP_OUT1,  S3C_GPIO_PULL_NONE},
 #endif
+#endif
 #endif /*end CONFIG_VIDEO_TSI*/
 	{EXYNOS4210_GPE1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
 	{EXYNOS4210_GPE1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
@@ -910,7 +919,7 @@ static unsigned int u1_sleep_gpio_table[][3] = {
 #endif /*CONFIG_TARGET_LOCALE_NA*/
 #if defined(CONFIG_MACH_U1_KOR_LGT)
 	{EXYNOS4_GPY2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
-#else
+#elif !defined(CONFIG_MACH_U1_NA_SPR)
 	{EXYNOS4_GPY2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
 #endif
 	{EXYNOS4_GPY2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
@@ -1045,6 +1054,9 @@ static unsigned int u1_sleep_gpio_table[][3] = {
 #endif /* CONFIG_TARGET_LOCALE_NA */
 
 #if defined(CONFIG_MACH_U1_NA_SPR) || defined(CONFIG_MACH_U1_NA_USCC)
+	{ EXYNOS4_GPY0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPY0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
 	/* SIDE_CLK_EN */
 	{ EXYNOS4_GPY2(5),  S3C_GPIO_SLP_OUT0,	S3C_GPIO_PULL_NONE},
 	/* SIDE_INT */
@@ -1081,6 +1093,14 @@ static unsigned int u1_sleep_gpio_table[][3] = {
 #endif
 };
 
+#if defined(CONFIG_TARGET_LOCALE_NAATT_TEMP)
+static unsigned int u1_exint_sleep_gpio_table[][3] = {
+	{ EXYNOS4_GPX2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPX3(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPX3(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+};
+#endif
+
 void u1_config_gpio_table(void)
 {
 	u32 i, gpio;
@@ -1109,8 +1129,26 @@ static void config_sleep_gpio_table(int array_size,
 	}
 }
 
+#if defined(CONFIG_TARGET_LOCALE_NAATT_TEMP)
+static void config_exint_sleep_gpio_table(int array_size,
+				unsigned int (*gpio_table)[3])
+{
+	u32 i, gpio;
+
+	for (i = 0; i < ARRAY_SIZE(u1_exint_sleep_gpio_table); i++) {
+		gpio = u1_exint_sleep_gpio_table[i][0];
+		s3c_gpio_cfgpin(gpio, u1_exint_sleep_gpio_table[i][1]);
+		s3c_gpio_setpull(gpio, u1_exint_sleep_gpio_table[i][2]);
+	}
+}
+#endif
+
 void u1_config_sleep_gpio_table(void)
 {
 	config_sleep_gpio_table(ARRAY_SIZE(u1_sleep_gpio_table),
 			u1_sleep_gpio_table);
+#if defined(CONFIG_TARGET_LOCALE_NAATT_TEMP)
+	config_exint_sleep_gpio_table(ARRAY_SIZE(u1_exint_sleep_gpio_table),
+			u1_exint_sleep_gpio_table);
+#endif
 }