samsung update 1

354 files changed, 157095 insertions, 0 deletions

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
new file mode 100644
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--- /dev/null
+++ b/arch/arm/mach-exynos/Kconfig
@@ -0,0 +1,1706 @@
+# arch/arm/mach-exynos/Kconfig
+#
+# Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+#		http://www.samsung.com/
+#
+# Licensed under GPLv2
+
+# Configuration options for the EXYNOS
+
+if ARCH_EXYNOS
+
+choice
+	prompt "EXYNOS system type"
+	default ARCH_EXYNOS4
+
+config ARCH_EXYNOS4
+	bool "Samsung Exynos4"
+	select ARM_ERRATA_743622
+	select ARM_ERRATA_751472
+	select ARM_ERRATA_754322
+	select ARM_ERRATA_764369
+	help
+	  Samsung EXYNOS4 series based systems
+
+config ARCH_EXYNOS5
+	bool "Samsung Exynos5"
+	select ARM_ERRATA_761171
+	select ARM_ERRATA_762974
+	select ARM_ERRATA_763722
+	select HAVE_EXYNOS5_HSI2C if I2C
+	help
+	  Samsung EXYNOS5 series based systems
+
+endchoice
+
+config CPU_EXYNOS4210
+	bool
+	select S3C_PL330_DMA
+	select PL310_ERRATA_727915
+	select ARM_ERRATA_753970
+	help
+	  Enable EXYNOS4210 CPU support
+
+config CPU_EXYNOS4212
+	bool
+	select S3C_PL330_DMA
+	help
+	  Enable EXYNOS4212 CPU support
+
+config CPU_EXYNOS4412
+	bool
+	select S3C_PL330_DMA
+	select ARM_ERRATA_761320
+	help
+	  Enable EXYNOS4412 CPU support
+
+config CPU_EXYNOS5210
+	bool
+	select S3C_PL330_DMA
+	help
+	  Enable EXYNOS5210 CPU support
+
+config S5PV310_HI_ARMCLK_THAN_1_2GHZ
+	bool "Enable the higher ARM clock than 1.2GHz"
+	default n
+	help
+	  S5PV310 has different max arm clock. (i.e. 1.0GHz, 1.2GHz and 1.4GHz etc.)
+	  If you are using the chip to work at the high clock than 1.2GHz,
+	  activate this option.
+
+choice
+	prompt "EXYNOS5210 core type"
+	depends on CPU_EXYNOS5210
+	default CPU_A15
+
+config CPU_EXYNOS5210_A15
+	bool "A15 core"
+	help
+	  A15 dual core CPU support
+
+config CPU_EXYNOS5210_A5_IOP
+	bool "A5 IOP core"
+	help
+	  A5 single core CPU support
+endchoice
+
+config CPU_EXYNOS5250
+	bool
+	select S3C_PL330_DMA
+	help
+	  Enable EXYNOS5250 CPU support
+
+config EXYNOS_CONTENT_PATH_PROTECTION
+	bool "Exynos Content Path Protection"
+	depends on (ARM_TRUSTZONE && (ARCH_EXYNOS4 || ARCH_EXYNOS5))
+	default n
+	help
+	  Enable content path protection of EXYNOS.
+
+config EXYNOS4_PM
+	bool "Exynos4 Power Management"
+	depends on (PM && ARCH_EXYNOS4)
+	default y
+	help
+	  Enable suspend and resume for Exynos4 series.
+
+config EXYNOS5_PM
+	bool "Exynos5 Power Management"
+	depends on (PM && ARCH_EXYNOS5)
+	default y
+	help
+	  Enable suspend and resume for Exynos5 series.
+
+config EXYNOS4_CPUIDLE
+	bool "Exynos4 CPUIDLE Feature"
+	depends on (CPU_IDLE && ARCH_EXYNOS4)
+	default y
+	help
+	  Enable CPUIDLE for Exynos4 series.
+
+config EXYNOS4_LOWPWR_IDLE
+	bool "Exynos4 Lowpower IDLE Feature"
+	depends on EXYNOS4_CPUIDLE
+	default y
+	help
+	  Enable Low power IDLE for Exynos4 series.
+
+config EXYNOS5_CPUIDLE
+	bool "Exynos5 CPUIDLE Feature"
+	depends on (CPU_IDLE && ARCH_EXYNOS5)
+	default y
+	help
+	  Enable CPUIDLE for Exynos5 series.
+
+config EXYNOS5_LOWPWR_IDLE
+	bool "Exynos5 Lowpower IDLE Feature"
+	depends on EXYNOS5_CPUIDLE
+	default y
+	help
+	  Enable Low power IDLE for Exynos5 series.
+
+config EXYNOS_MCT
+	bool
+	default y
+	help
+	  Use MCT (Multi Core Timer) as kernel timers
+
+config EXYNOS5_DEV_AHCI
+	bool
+	help
+	  Compile in platform device definitions for AHCI SATA3.0
+
+config EXYNOS4_DEV_AHCI
+	bool
+	help
+	  Compile in platform device definitions for AHCI
+
+config EXYNOS4_SETUP_FIMD0
+	bool
+	help
+	  Common setup code for FIMD0.
+
+config EXYNOS4_SETUP_FIMD
+	bool
+	help
+	  Common setup code for FIMD.
+
+config EXYNOS4_SETUP_DP
+	bool
+	help
+	  Common setup code for DP.
+
+config EXYNOS_DEV_SYSMMU
+	bool
+	help
+	  Common setup code for SYSTEM MMU in EXYNOS
+
+config EXYNOS_DEV_PD
+	bool
+	select SAMSUNG_PD
+	help
+	  Compile in platform device definitions for Power Domain
+
+config EXYNOS4_DEV_DWMCI
+	bool
+	help
+	  Compile in platform device definitions for DWMCI
+
+config EXYNOS4_DEV_FIMC_LITE
+	bool
+	help
+	  Compile in platform device definitions for FIMC_LITE
+
+config EXYNOS4_DEV_FIMC_IS
+	bool
+	depends on (VIDEO_EXYNOS_FIMC_IS || VIDEO_EXYNOS5_FIMC_IS)
+	default y
+	help
+	  Compile in platform device definition for FIMC-IS
+
+config EXYNOS4_SETUP_HDMI
+	bool
+	help
+	  Common setup code for hdmi
+
+config EXYNOS4_SETUP_I2C1
+	bool
+	help
+	  Common setup code for i2c bus 1.
+
+config EXYNOS4_SETUP_I2C2
+	bool
+	help
+	  Common setup code for i2c bus 2.
+
+config EXYNOS4_SETUP_I2C3
+	bool
+	help
+	  Common setup code for i2c bus 3.
+
+config EXYNOS4_SETUP_I2C4
+	bool
+	help
+	  Common setup code for i2c bus 4.
+
+config EXYNOS4_SETUP_I2C5
+	bool
+	help
+	  Common setup code for i2c bus 5.
+
+config EXYNOS4_SETUP_I2C6
+	bool
+	help
+	  Common setup code for i2c bus 6.
+
+config EXYNOS4_SETUP_I2C7
+	bool
+	help
+	  Common setup code for i2c bus 7.
+
+config EXYNOS5_SETUP_HSI2C0
+	bool
+	help
+	  Common setup code for hs-i2c bus 0.
+
+config EXYNOS5_SETUP_HSI2C1
+	bool
+	help
+	  Common setup code for hs-i2c bus 1.
+
+config EXYNOS5_SETUP_HSI2C2
+	bool
+	help
+	  Common setup code for hs-i2c bus 2.
+
+config EXYNOS5_DEV_HSI2C0
+	bool
+	help
+	  Compile in platform device definitions for HS-I2C channel 0
+
+config EXYNOS5_DEV_HSI2C1
+	bool
+	help
+	  Compile in platform device definitions for HS-I2C channel 1
+
+config EXYNOS5_DEV_HSI2C2
+	bool
+	help
+	  Compile in platform device definitions for HS-I2C channel 2
+
+config EXYNOS5_DEV_HSI2C3
+	bool
+	help
+	  Compile in platform device definitions for HS-I2C channel 3
+
+config EXYNOS5_SETUP_HSI2C3
+	bool
+	help
+	  Common setup code for hs-i2c bus 3.
+
+config EXYNOS4_SETUP_KEYPAD
+	bool
+	help
+	  Common setup code for keypad.
+
+config EXYNOS4_SETUP_MFC
+	bool
+	help
+	  Common setup code for MFC.
+
+config EXYNOS4_SETUP_SDHCI
+	bool
+	select EXYNOS4_SETUP_SDHCI_GPIO
+	help
+	  Internal helper functions for EXYNOS4 based SDHCI systems.
+
+config EXYNOS4_SETUP_SDHCI_GPIO
+	bool
+	help
+	  Common setup code for SDHCI gpio.
+
+config EXYNOS4_SETUP_MSHCI
+	bool
+	select EXYNOS4_SETUP_MSHCI_GPIO
+	help
+	  Internal helper functions for EXYNOS4 based MSHCI systems.
+
+config EXYNOS4_SETUP_MSHCI_GPIO
+	bool
+	help
+	  Common setup code for MSHCI gpio.
+
+config EXYNOS4_SETUP_FIMC
+	bool
+	depends on VIDEO_SAMSUNG_S5P_FIMC
+	default y
+	help
+	  Common setup code for the camera interfaces.
+
+config EXYNOS4_SETUP_FIMC0
+	bool
+	depends on VIDEO_FIMC
+	default y
+	help
+	  Common setup code for the camera interfaces.
+
+config EXYNOS4_SETUP_FIMC1
+	bool
+	depends on VIDEO_FIMC
+	default y
+	help
+	  Common setup code for the camera interfaces.
+
+config EXYNOS4_SETUP_FIMC2
+	bool
+	depends on VIDEO_FIMC
+	default y
+	help
+	  Common setup code for the camera interfaces.
+
+config EXYNOS4_SETUP_FIMC3
+	bool
+	depends on VIDEO_FIMC
+	default y
+	help
+	  Common setup code for the camera interfaces.
+
+config EXYNOS4_SETUP_FIMC_IS
+	bool
+	depends on (VIDEO_EXYNOS_FIMC_IS || VIDEO_EXYNOS5_FIMC_IS)
+	default y
+	help
+	  Common setup code for the FIMC-IS
+
+config EXYNOS4_SETUP_USB_PHY
+	bool
+	help
+	  Common setup code for USB PHY controller
+
+config EXYNOS4_SETUP_CSIS
+	bool
+	depends on VIDEO_FIMC_MIPI
+	default y
+	help
+	  Common setup code for MIPI-CSIS
+
+config EXYNOS4_SETUP_FB_S5P
+	bool
+	default n
+	help
+	  Setup code for EXYNOS4 FIMD
+
+config EXYNOS4_SETUP_TVOUT
+	bool
+	default y
+	help
+	  Common setup code for TVOUT
+
+config EXYNOS4_SETUP_THERMAL
+	bool "Use thermal management for exynos4"
+	depends on CPU_FREQ
+	help
+	  Common setup code for Exynos4 TMU
+
+config EXYNOS_SETUP_THERMAL
+	bool "Use thermal management"
+	depends on CPU_FREQ
+	help
+	  Common setup code for TMU
+
+config TMU_DEBUG
+	bool "Thermal management Debug"
+	depends on EXYNOS_SETUP_THERMAL
+	help
+	  TMU debugging message on
+
+config EXYNOS4_SETUP_MIPI_DSI
+	bool
+	depends on FB_S5P_MIPI_DSIM
+	default y
+	help
+	  Common setup code for MIPI_DSIM.
+
+config EXYNOS4_SETUP_MIPI_DSIM
+	bool
+	depends on FB_MIPI_DSIM
+	default y
+	help
+	  Common setup code for MIPI_DSIM to support mainline style fimd.
+
+config EXYNOS4_SETUP_JPEG
+	bool
+	depends on VIDEO_JPEG_V2X
+	default y
+	help
+	  Common setup code for JPEG
+
+config EXYNOS5_DEV_GSC
+	bool
+	depends on VIDEO_EXYNOS_GSCALER
+	default y
+	help
+	  Compile in platform device definitions for GSC
+
+config EXYNOS5_DEV_FIMC_IS
+	bool
+	depends on VIDEO_EXYNOS5_FIMC_IS
+	default y
+	help
+	  Compile in platform device definition for FIMC-IS
+
+config EXYNOS5_SETUP_GSC
+	bool
+	depends on VIDEO_EXYNOS_GSCALER
+	default y
+	help
+	  Common setup code for GSC
+
+config EXYNOS4_ENABLE_CLOCK_DOWN
+	bool "ARM core clock down feature enable"
+	depends on EXYNOS4_CPUIDLE
+	default n
+	help
+	  ARM core clock down in idle time.
+
+config EXYNOS5_ENABLE_CLOCK_DOWN
+	bool "ARM core clock down feature enable"
+	depends on EXYNOS5_CPUIDLE
+	default n
+	help
+	  ARM core clock down in idle time.
+
+config EXYNOS4_CPUFREQ
+	def_bool y
+	depends on CPU_FREQ && ARCH_EXYNOS4
+	help
+	  Exynos4 cpufreq support
+
+config EXYNOS5_CPUFREQ
+	def_bool y
+	depends on CPU_FREQ && ARCH_EXYNOS5
+	help
+	  Exynos5 cpufreq support
+
+choice
+	prompt "Max CPU frequency"
+	depends on EXYNOS4_CPUFREQ
+	default EXYNOS4X12_1400MHZ_SUPPORT if (CPU_EXYNOS4212 || CPU_EXYNOS4412)
+	default EXYNOS4210_1400MHZ_SUPPORT if CPU_EXYNOS4210
+
+config EXYNOS4210_1200MHZ_SUPPORT
+	bool "Max 1200MHz CPUFREQ LEVEL"
+	depends on EXYNOS4_CPUFREQ && CPU_EXYNOS4210
+	help
+	  Max 1.2Ghz support
+
+config EXYNOS4210_1400MHZ_SUPPORT
+	bool "Max 1400MHz CPUFREQ LEVEL"
+	depends on EXYNOS4_CPUFREQ && CPU_EXYNOS4210
+	help
+	  Max 1.4Ghz support
+
+config EXYNOS4X12_1500MHZ_SUPPORT
+	bool "Max 1500MHz CPUFREQ LEVEL"
+	depends on EXYNOS4_CPUFREQ && (CPU_EXYNOS4212 || CPU_EXYNOS4412)
+	help
+	  Max 1.5Ghz support
+
+config EXYNOS4X12_1400MHZ_SUPPORT
+	bool "Max 1400MHz CPUFREQ LEVEL"
+	depends on EXYNOS4_CPUFREQ && (CPU_EXYNOS4212 || CPU_EXYNOS4412)
+	help
+	  Max 1.4Ghz support
+
+config EXYNOS4X12_1200MHZ_SUPPORT
+	bool "Max 1200MHz CPUFREQ LEVEL"
+	depends on EXYNOS4_CPUFREQ && (CPU_EXYNOS4212 || CPU_EXYNOS4412)
+	help
+	  Max 1.2Ghz support
+
+config EXYNOS4X12_1000MHZ_SUPPORT
+	bool "Max 1000MHz CPUFREQ LEVEL"
+	depends on EXYNOS4_CPUFREQ && (CPU_EXYNOS4212 || CPU_EXYNOS4412)
+	help
+	  Max 1.0Ghz support
+
+endchoice
+
+config MIDAS_COMMON
+	bool
+	help
+	  Support common devices of MIDAS boards
+
+menu "Support dynamic CPU Hotplug"
+	depends on HOTPLUG_CPU && SMP
+
+config EXYNOS_PM_HOTPLUG
+	bool "EXYNOS Dynamic Hotplug"
+	help
+	  Dynamic CPU HOTLUG for EXYNOS series
+
+choice
+	prompt "Dynamic CPU HOTPLUG Policy"
+	depends on EXYNOS_PM_HOTPLUG
+	default DVFS_NR_RUNNING_POLICY if (CPU_EXYNOS4212 || CPU_EXYNOS4412 || CPU_EXYNOS5250)
+
+config STAND_ALONE_POLICY
+	bool "Stand alone policy CPU hotplug"
+	depends on EXYNOS_PM_HOTPLUG
+	help
+	  PM hotplug policy. This is for exynos4210
+	  Enable to use pm hotplug, then it uses stand-hotplug.c file.
+	  Avg-load is calculated with both cpu frequency aspect
+	  and run queue status.
+
+config LEGACY_HOTPLUG_POLICY
+	bool "Legacy policy CPU hotplug"
+	depends on EXYNOS_PM_HOTPLUG
+	help
+	  PM hotplug policy. This is for exynos4210
+	  Enable to use pm hotplug, then it uses pm-hotplug.c file.
+	  Avg-load is calculated with only cpu utilization of cpu
+	  frequency at that time.
+
+config WITH_DVFS_POLICY
+	depends on EXYNOS4_CPUFREQ
+	bool "Intergrated DVFS CPU hotplug"
+
+config DVFS_NR_RUNNING_POLICY
+	depends on (EXYNOS4_CPUFREQ || EXYNOS5_CPUFREQ)
+	bool "DVFS-nr_running CPU hotplug"
+
+config NR_RUNNING_POLICY
+	bool "nr_running CPU hotplug"
+
+endchoice
+endmenu
+
+menu "Busfreq Model"
+	depends on EXYNOS4_CPUFREQ || EXYNOS5_CPUFREQ
+
+config BUSFREQ
+	bool "Busfreq with PPC/PPMU"
+	depends on EXYNOS4_CPUFREQ
+
+config BUSFREQ_QOS
+	bool "QoS with Busfreq"
+	depends on BUSFREQ
+	default n
+
+config BUSFREQ_OPP
+	bool "Busfreq with OPP"
+	depends on EXYNOS4_CPUFREQ || EXYNOS5_CPUFREQ
+
+config DEVFREQ_BUS
+	bool "Busfreq support with Devfreq framework & Simple-Ondemand"
+	depends on EXYNOS4_CPUFREQ
+	select PM_DEVFREQ
+	select ARM_EXYNOS4_BUS_DEVFREQ
+
+choice
+	prompt "QoS LEVEL By Resolution"
+	depends on BUSFREQ_QOS || BUSFREQ_OPP
+	default BUSFREQ_QOS_LEVEL_NONE
+
+config BUSFREQ_QOS_NONE
+	bool "QoS Setting is not required"
+
+config BUSFREQ_QOS_1024X600
+	bool "QoS for 1024x600 (like P2)"
+
+config BUSFREQ_QOS_1280X720
+	bool "QoS for 1280x720 (like M0/T0)"
+
+config BUSFREQ_QOS_1280X800
+	bool "QoS for 1280x800 or 800x1280 (like Q1/P8)"
+
+endchoice
+
+endmenu
+
+config BUSFREQ_DEBUG
+	bool "BUSFREQ sysfs support"
+	default n
+
+config GPIO_MIDAS_01_BD
+	bool "GPIO configuration for Midas 01 BD"
+	depends on MACH_SLP_MIDAS
+
+config GPIO_MIDAS_02_BD
+	bool "GPIO configuration for Midas 02 BD"
+	depends on MACH_SLP_MIDAS
+
+config BUSFREQ_L2_160M
+	bool "Busfreq L2 level use 160MHz"
+	default n
+	help
+	Busfreq uses 160MHz for L2, not 133MHz. Optimize busfreq
+	dvfs level transition for LCD high resolution.
+	This enable 160MHz of L2 level. Q1 has high LCD resolution,
+	so uses busfreq dvfs L2 as 160MHz.
+
+config SEC_THERMISTOR
+	bool "Use external thermistor with ADC"
+	depends on SAMSUNG_DEV_ADC
+	default n
+	help
+	 Use thermistor driver for U1 & U1 Premium.
+	 U1 has two thermistors. this device driver use one of those
+	 to check system temperature.
+
+config EXYNOS_SYSREG_PM
+	bool "PM Support for System Registers"
+	depends on CPU_EXYNOS4210 || CPU_EXYNOS4412 || CPU_EXYNOS4212
+	default n
+	help
+	  Use System Register save/restore for suspend-to-RAM
+	  Some boards have this code hard coded in device drivers(FB);
+	  however, this is better supported at SoC support code.
+	  Currently, SLP kernel depends on this.
+
+config ANDROID_WIP
+	bool "work in progress hacks for android"
+	default n
+	help
+	  This enables 'work in progress' hacks for android issues.
+	  Please remove it later.
+
+# machine support
+
+menu "EXYNOS4 Machines"
+	depends on ARCH_EXYNOS4
+
+config MACH_SMDKC210
+	bool "SMDKC210"
+	select CPU_EXYNOS4210
+	select S3C_DEV_RTC
+	select S3C_DEV_WDT
+	select S3C_DEV_I2C1
+	select S3C_DEV_HSMMC2
+	select S3C_DEV_HSMMC3
+	select S3C_DEV_HWMON if S3C_ADC
+	select S5P_GPIO_INT
+	select S5P_DEV_FIMD0
+	select S5P_DEV_FIMD_S5P
+	select S5P_DEV_MFC
+	select S5P_DEV_FIMG2D
+	select S5P_DEV_ROTATOR
+	select S5P_DEV_USBGADGET
+	select S5P_DEV_JPEG
+	select S5P_DEV_THERMAL
+	select S5P_DEV_USB_EHCI
+	select S5P_SYSTEM_MMU
+	select EXYNOS_DEV_PD
+	select EXYNOS4_SETUP_FIMD0
+	select EXYNOS4_SETUP_I2C1
+	select EXYNOS4_SETUP_KEYPAD
+	select EXYNOS4_SETUP_SDHCI
+	select EXYNOS4_SETUP_FB_S5P
+	select EXYNOS4_SETUP_USB_PHY
+	select EXYNOS4_SETUP_MFC
+	select SAMSUNG_DEV_KEYPAD
+	select SAMSUNG_DEV_ADC
+	select SAMSUNG_DEV_TS
+	select SAMSUNG_DEV_TS1
+	select SAMSUNG_DEV_PWM
+	select SAMSUNG_DEV_BACKLIGHT
+	help
+	  Machine support for Samsung SMDKC210
+
+config MACH_SMDKV310
+	bool "SMDKV310"
+	select CPU_EXYNOS4210
+	select S3C_DEV_RTC
+	select S3C_DEV_WDT
+	select S3C_DEV_I2C1
+	select S3C_DEV_HSMMC2
+	select S3C_DEV_HSMMC3
+	select S3C_DEV_HWMON if S3C_ADC
+	select S5P_GPIO_INT
+	select S5P_DEV_FIMD0
+	select S5P_DEV_FIMD_S5P
+	select S5P_DEV_MFC
+	select S5P_DEV_FIMG2D
+	select S5P_DEV_ROTATOR
+	select S5P_DEV_USBGADGET
+	select S5P_DEV_JPEG
+	select S5P_DEV_THERMAL
+	select S5P_DEV_USB_EHCI
+	select S5P_SYSTEM_MMU
+	select EXYNOS_DEV_PD
+	select EXYNOS4_SETUP_FIMD0
+	select EXYNOS4_SETUP_I2C1
+	select EXYNOS4_SETUP_KEYPAD
+	select EXYNOS4_SETUP_SDHCI
+	select EXYNOS4_SETUP_FB_S5P
+	select EXYNOS4_SETUP_USB_PHY
+	select EXYNOS4_SETUP_MFC
+	select EXYNOS4_DEV_AHCI
+	select SAMSUNG_DEV_PWM
+	select SAMSUNG_DEV_BACKLIGHT
+	select SAMSUNG_DEV_KEYPAD
+	select SAMSUNG_DEV_ADC
+	select SAMSUNG_DEV_TS
+	select SAMSUNG_DEV_TS1
+	help
+	  Machine support for Samsung SMDKV310
+
+config MACH_ARMLEX4210
+	bool "ARMLEX4210"
+	select CPU_EXYNOS4210
+	select S3C_DEV_RTC
+	select S3C_DEV_WDT
+	select S3C_DEV_HSMMC
+	select S3C_DEV_HSMMC2
+	select S3C_DEV_HSMMC3
+	select S5P_SYSTEM_MMU
+	select EXYNOS4_DEV_AHCI
+	select EXYNOS4_SETUP_SDHCI
+	help
+	  Machine support for Samsung ARMLEX4210 based on EXYNOS4210
+
+config MACH_UNIVERSAL_C210
+	bool "Mobile UNIVERSAL_C210 Board"
+	select CPU_EXYNOS4210
+	select S3C_DEV_HSMMC
+	select S3C_DEV_HSMMC2
+	select S3C_DEV_HSMMC3
+	select S3C_DEV_I2C1
+	select S3C_DEV_I2C5
+	select S5P_DEV_ONENAND
+	select EXYNOS4_SETUP_I2C1
+	select EXYNOS4_SETUP_I2C5
+	select EXYNOS4_SETUP_SDHCI
+	help
+	  Machine support for Samsung Mobile Universal S5PC210 Reference
+	  Board.
+
+config MACH_NURI
+	bool "Mobile NURI Board"
+	select CPU_EXYNOS4210
+	select S3C_DEV_WDT
+	select S3C_DEV_HSMMC
+	select S3C_DEV_HSMMC2
+	select S3C_DEV_HSMMC3
+	select S3C_DEV_I2C1
+	select S3C_DEV_I2C3
+	select S3C_DEV_I2C4
+	select S3C_DEV_I2C5
+	select S5P_DEV_USB_EHCI
+	select EXYNOS4_SETUP_I2C1
+	select EXYNOS4_SETUP_I2C3
+	select EXYNOS4_SETUP_I2C4
+	select EXYNOS4_SETUP_I2C5
+	select EXYNOS4_SETUP_SDHCI
+	select EXYNOS4_SETUP_USB_PHY
+	select SAMSUNG_DEV_PWM
+	help
+	  Machine support for Samsung Mobile NURI Board.
+
+config MACH_U1
+	bool "U1 board"
+	select CPU_EXYNOS4210
+	select S5P_GPIO_INT
+	select S5P_DEV_FIMD0
+	select S5P_DEV_FIMD_S5P
+	select S5P_DEV_TVOUT
+	select S5P_DEV_MFC
+	select S5P_DEV_FIMG2D
+	select S5P_DEV_USB_EHCI
+	select S5P_SYSTEM_MMU
+	select S5P_DEV_USBGADGET
+	select S3C_DEV_RTC
+	select S3C_DEV_WDT
+	select S3C_DEV_I2C1
+	select S3C_DEV_I2C3
+	select S3C_DEV_I2C5
+	select S3C_DEV_I2C6
+	select S3C_DEV_I2C7
+	select S3C_DEV_I2C8_EMUL
+	select S3C_DEV_I2C9_EMUL
+	select EXYNOS4_DEV_MSHC
+	select EXYNOS4_MSHC_MPLL_40MHZ
+	select EXYNOS4_MSHC_DDR
+	select EXYNOS4_MSHC_8BIT
+	select S3C_DEV_HSMMC2
+	select S3C_DEV_HSMMC3
+	select SAMSUNG_DEV_ADC
+	select SAMSUNG_DEV_TS
+	select SAMSUNG_DEV_TS1
+	select EXYNOS_DEV_PD
+	select S5P_SYSTEM_MMU
+	select EXYNOS4_SETUP_FIMD0
+	select EXYNOS4_SETUP_I2C1
+	select EXYNOS4_SETUP_I2C3
+	select EXYNOS4_SETUP_I2C5
+	select EXYNOS4_SETUP_I2C6
+	select EXYNOS4_SETUP_I2C7
+	select EXYNOS4_SETUP_SDHCI
+	select EXYNOS4_SETUP_MSHCI
+	select EXYNOS4_SETUP_MFC
+	select EXYNOS4_SETUP_FB_S5P
+	select EXYNOS4_SETUP_USB_PHY
+	select EXYNOS4_SETUP_THERMAL
+	help
+	  Machine support for U1 Board
+
+choice
+	prompt "U1 board"
+	depends on MACH_U1
+	default MACH_U1_BD
+
+config MACH_U1_BD
+	bool "U1 Board"
+
+config MACH_U1CAMERA_BD
+	bool "U1CAMERA Board"
+
+config MACH_Q1_BD
+	bool "Q1 Board"
+
+endchoice
+
+config MACH_PX
+	bool "PX board"
+	select CPU_EXYNOS4210
+	select S5P_GPIO_INT
+	select S5P_DEV_FIMD0
+	select S5P_DEV_FIMD_S5P
+	select S5P_DEV_TVOUT
+	select S5P_DEV_MFC
+	select S5P_DEV_FIMG2D
+	select S5P_DEV_USB_EHCI
+	select S5P_SYSTEM_MMU
+	select S5P_DEV_USBGADGET
+	select S5P_DEV_THERMAL
+	select S3C_DEV_RTC
+	select S3C_DEV_WDT
+	select S3C_DEV_I2C1
+	select S3C_DEV_I2C3
+	select S3C_DEV_I2C4
+	select S3C_DEV_I2C5
+	select S3C_DEV_I2C6
+	select S3C_DEV_I2C7
+	select S3C_DEV_I2C9_EMUL
+	select EXYNOS4_DEV_MSHC
+	select EXYNOS4_MSHC_MPLL_40MHZ
+	select EXYNOS4_MSHC_DDR
+	select EXYNOS4_MSHC_8BIT
+	select S3C_DEV_HSMMC2
+	select S3C_DEV_HSMMC3
+	select SAMSUNG_DEV_ADC
+	select SAMSUNG_DEV_TS
+	select SAMSUNG_DEV_TS1
+	select EXYNOS_DEV_PD
+	select S5P_SYSTEM_MMU
+	select EXYNOS4_SETUP_FIMD0
+	select EXYNOS4_SETUP_I2C1
+	select EXYNOS4_SETUP_I2C3
+	select EXYNOS4_SETUP_I2C4
+	select EXYNOS4_SETUP_I2C5
+	select EXYNOS4_SETUP_I2C6
+	select EXYNOS4_SETUP_I2C7
+	select EXYNOS4_SETUP_SDHCI
+	select EXYNOS4_SETUP_MSHCI
+	select EXYNOS4_SETUP_MFC
+	select EXYNOS4_SETUP_FB_S5P
+	select EXYNOS4_SETUP_USB_PHY
+	help
+	  Machine support for PX Board
+choice
+	prompt "PX board"
+	depends on MACH_PX
+	default MACH_P4
+
+config MACH_P4
+	bool "P4 board"
+
+config MACH_P2
+	bool "P2 board"
+
+config MACH_P8
+	bool "P8 board"
+
+config MACH_P8LTE
+	bool "P8 LTE board"
+	select S3C64XX_DEV_SPI0
+
+endchoice
+
+choice
+	prompt "LCD panel select"
+	depends on MACH_U1
+	default PANEL_U1
+
+config PANEL_U1
+	bool "U1/Q1 default panel"
+
+endchoice
+
+config PANEL_S2PLUS
+	bool "s2plus panel"
+
+if MACH_U1 || MACH_C1 || MACH_C1VZW || MACH_M0 || MACH_P4 || MACH_P2 || MACH_P4NOTE || MACH_T0
+source "arch/arm/mach-exynos/Kconfig.local"
+endif
+
+config MACH_SMDK4X12
+	bool "SMDK4X12 board"
+	select CPU_EXYNOS4212
+	select CPU_EXYNOS4412
+	select S3C_DEV_WDT
+	select S3C_DEV_RTC
+	select S3C_DEV_HSMMC2
+	select S3C_DEV_I2C1
+	select S3C_DEV_I2C2
+	select S3C_DEV_I2C3
+	select S3C_DEV_I2C4
+	select S3C_DEV_I2C5
+	select S3C_DEV_I2C7
+	select S5P_DEV_I2C_HDMIPHY
+	select S5P_GPIO_INT
+	select S5P_DEV_MFC
+	select S5P_DEV_FIMG2D
+	select S5P_DEV_FIMD0
+	select S5P_DEV_FIMD_S5P
+	select S5P_DEV_USB_EHCI
+	select S5P_DEV_USBGADGET
+	select S5P_DEV_USB_SWITCH
+	select S5P_DEV_THERMAL
+	select S5P_SYSTEM_MMU
+	select EXYNOS_DEV_PD
+	select EXYNOS4_SETUP_SDHCI
+	select EXYNOS4_SETUP_FB_S5P
+	select EXYNOS4_SETUP_FIMD0
+	select EXYNOS4_SETUP_I2C1
+	select EXYNOS4_SETUP_I2C2
+	select EXYNOS4_SETUP_I2C3
+	select EXYNOS4_SETUP_I2C4
+	select EXYNOS4_SETUP_I2C5
+	select EXYNOS4_SETUP_I2C7
+	select EXYNOS4_SETUP_USB_PHY
+	select EXYNOS4_SETUP_KEYPAD
+	select EXYNOS4_SETUP_MFC
+	select EXYNOS4_DEV_FIMC_LITE
+	select SAMSUNG_DEV_ADC
+	select SAMSUNG_DEV_BACKLIGHT
+	select SAMSUNG_DEV_PWM
+	select SAMSUNG_DEV_KEYPAD
+	help
+	  Machine support for Samsung SMDK4X12
+
+config MACH_MIDAS
+	bool "MIDAS board"
+	select CPU_EXYNOS4212
+	select CPU_EXYNOS4412
+	select S3C_DEV_WDT
+	select S3C_DEV_RTC
+	select S3C_DEV_HSMMC2
+	select S3C_DEV_HSMMC3
+	select SAMSUNG_DEV_ADC
+	select S3C_DEV_I2C1
+	select S3C_DEV_I2C3
+	select S3C_DEV_I2C6
+	select S3C_DEV_I2C7
+	select S5P_GPIO_INT
+	select S5P_DEV_MFC
+	select S5P_DEV_TVOUT
+	select S5P_DEV_FIMG2D
+	select S5P_DEV_FIMD_S5P
+	select S5P_DEV_USB_EHCI
+	select S5P_DEV_USBGADGET
+	select EXYNOS4_DEV_MSHC
+	select EXYNOS4_SETUP_MSHCI
+	select EXYNOS4_MSHC_MPLL_40MHZ
+	select EXYNOS4_MSHC_DDR
+	select EXYNOS4_MSHC_8BIT
+	select EXYNOS4_SETUP_SDHCI
+	select EXYNOS4_DEV_FIMC_LITE
+	select EXYNOS4_SETUP_FB_S5P
+	select EXYNOS4_SETUP_I2C1
+	select EXYNOS4_SETUP_I2C3
+	select EXYNOS4_SETUP_I2C4
+	select EXYNOS4_SETUP_I2C5
+	select EXYNOS4_SETUP_I2C6
+	select EXYNOS4_SETUP_I2C7
+	select EXYNOS4_SETUP_USB_PHY
+	select EXYNOS4_SETUP_MFC
+	select SAMSUNG_DEV_BACKLIGHT
+	select SAMSUNG_DEV_PWM
+	select EXYNOS_DEV_PD
+	select EXYNOS4_SETUP_MFC
+	select MIDAS_COMMON
+	help
+	  Machine support for Samsung midas board
+
+choice
+	prompt "EXYNOS4212 board"
+	depends on MACH_MIDAS
+	default MACH_MIDAS_02_BD
+
+config MACH_MIDAS_01_BD
+	bool "Midas Rev 0.1 board"
+
+config MACH_MIDAS_02_BD
+	bool "Midas Rev 0.2 board"
+	select S3C_DEV_I2C4
+	select S3C_DEV_I2C5
+
+config MACH_M0
+	bool "M0 board"
+	select S3C_DEV_I2C4
+	select S3C_DEV_I2C5
+	select MIDAS_COMMON_BD
+
+config MACH_M3
+	bool "M3 board"
+	select S3C_DEV_I2C4
+	select S3C_DEV_I2C5
+	select MIDAS_COMMON_BD
+
+config MACH_C1
+	bool "C1 board"
+	select S3C_DEV_I2C4
+	select S3C_DEV_I2C5
+	select MIDAS_COMMON_BD
+
+config MACH_C1VZW
+	bool "C1 VZW board"
+	select S3C_DEV_I2C4
+	select S3C_DEV_I2C5
+	select MIDAS_COMMON_BD
+
+config MACH_C1CTC
+	bool "C1 CTC board"
+	select S3C_DEV_I2C4
+	select S3C_DEV_I2C5
+	select MIDAS_COMMON_BD
+
+config MACH_JENGA
+	bool "Jenga board"
+	select S3C_DEV_I2C4
+	select S3C_DEV_I2C5
+	select MIDAS_COMMON_BD
+
+config MACH_S2PLUS
+	bool "S2PLUS board"
+	select S3C_DEV_I2C4
+	select S3C_DEV_I2C5
+	select PANEL_S2PLUS
+	select MIDAS_COMMON_BD
+
+config MACH_S2PLUS
+	bool "S2 Plus board"
+	select S3C_DEV_I2C4
+	select MIDAS_COMMON_BD
+
+config MACH_P4NOTE
+	bool "P4 Note board"
+	select S3C_DEV_I2C4
+	select S3C_DEV_I2C5
+	select P4NOTE_00_BD
+
+config MACH_GC1
+	bool "Galuxy Camera board"
+	select S3C_DEV_I2C4
+	select S3C_DEV_I2C5
+	select GC1_00_BD
+
+config MACH_T0
+	bool "T0 board"
+	select S3C_DEV_I2C4
+	select S3C_DEV_I2C5
+	select T0_00_BD
+
+endchoice
+
+config MIDAS_COMMON_BD
+	bool "Midas default common Board"
+
+config P4NOTE_00_BD
+	bool "P4 Note PQ common Board"
+
+config GC1_00_BD
+	bool "Galaxy Camera common Board"
+
+config T0_00_BD
+	bool "T0 common Board"
+
+config WRITEBACK_ENABLED
+	bool "Samsung Writeback Enable"
+	help
+	  This option enables writeback operations. It can
+	  support fimd streams data to fimc destinations ram.
+	  writeback operations support final blended stream.
+	  when enable this options.
+
+endmenu
+
+menu "EXYNOS5 Machines"
+	depends on ARCH_EXYNOS5
+
+config MACH_SMDK5210
+	bool "SMDK5210 board"
+	select CPU_EXYNOS5210
+	select S3C_DEV_HSMMC2
+	select S3C_DEV_HSMMC3
+	select S3C_DEV_I2C1
+	select S3C_DEV_I2C2
+	select S5P_DEV_DP
+	select S5P_DEV_FIMD1
+	select S5P_DEV_MFC
+	select S5P_DEV_USB_EHCI
+	select EXYNOS_DEV_PD
+	select EXYNOS4_SETUP_DP
+	select EXYNOS4_SETUP_FIMD
+	select EXYNOS4_SETUP_I2C1
+	select EXYNOS4_SETUP_I2C2
+	select EXYNOS4_SETUP_MFC
+	select EXYNOS4_SETUP_SDHCI
+	select EXYNOS4_SETUP_USB_PHY
+	select SAMSUNG_DEV_BACKLIGHT
+	select SAMSUNG_DEV_PWM
+	select S5P_DEV_I2C_HDMIPHY
+	select EXYNOS_DEV_SS_UDC
+	help
+	  Machine support for Samsung SMDK5210
+
+config MACH_SMDK5250
+	bool "SMDK5250 board"
+	select CPU_EXYNOS5250
+	select S3C_DEV_HWMON if S3C_ADC
+	select S3C_DEV_RTC
+	select S3C_DEV_WDT
+	select S3C_DEV_HSMMC2
+	select S3C_DEV_HSMMC3
+	select S3C_DEV_I2C1
+	select S3C_DEV_I2C2
+	select S3C_DEV_I2C4
+	select S3C_DEV_I2C5
+	select S3C_DEV_I2C7
+	select S5P_GPIO_INT
+	select S5P_DEV_DP
+	select EXYNOS_DEV_SYSMMU
+	select S5P_DEV_FIMD1
+	select S5P_DEV_USB_EHCI
+	select S5P_DEV_MFC
+	select S5P_DEV_FIMG2D
+	select S5P_DEV_ROTATOR
+	select S5P_DEV_USBGADGET
+	select S5P_DEV_I2C_HDMIPHY
+	select S5P_DEV_THERMAL
+	select S5P_DEV_USB_SWITCH
+	select EXYNOS_DEV_PD
+	select EXYNOS4_DEV_FIMC_LITE
+	select EXYNOS4_SETUP_I2C1
+	select EXYNOS4_SETUP_I2C2
+	select EXYNOS4_SETUP_I2C4
+	select EXYNOS4_SETUP_I2C5
+	select EXYNOS4_SETUP_I2C7
+	select EXYNOS4_SETUP_SDHCI
+	select EXYNOS4_SETUP_DP
+	select EXYNOS4_SETUP_FIMD
+	select EXYNOS4_SETUP_USB_PHY
+	select EXYNOS4_SETUP_MFC
+	select EXYNOS5_DEV_AHCI
+	select EXYNOS5_DEV_DWMCI2
+	select EXYNOS_DEV_SS_UDC
+	select SAMSUNG_DEV_ADC
+	select SAMSUNG_DEV_BACKLIGHT
+	select SAMSUNG_DEV_PWM
+	help
+	  Machine support for Samsung SMDK5250
+
+config MACH_P10
+	bool "P10 board"
+	select CPU_EXYNOS5250
+	select S3C_DEV_HWMON if S3C_ADC
+	select S3C_DEV_RTC
+	select S3C_DEV_WDT
+	select S3C_DEV_HSMMC2
+	select S3C_DEV_HSMMC3
+	select S3C_DEV_I2C1
+	select S3C_DEV_I2C3
+	select S3C_DEV_I2C4
+	select S3C_DEV_I2C5
+	select S3C_DEV_I2C7
+	select S5P_GPIO_INT
+	select S5P_DEV_DP
+	select EXYNOS_DEV_SYSMMU
+	select S5P_DEV_FIMD1
+	select S5P_DEV_USB_EHCI
+	select S5P_DEV_TV
+	select S5P_DEV_USBGADGET
+	select S5P_DEV_MFC
+	select S5P_DEV_FIMG2D
+	select S5P_DEV_ROTATOR
+	select S5P_DEV_I2C_HDMIPHY
+	select EXYNOS_DEV_PD
+	select EXYNOS4_DEV_FIMC_LITE
+	select EXYNOS4_SETUP_I2C1
+	select EXYNOS4_SETUP_I2C3
+	select EXYNOS4_SETUP_I2C4
+	select EXYNOS4_SETUP_I2C5
+	select EXYNOS4_SETUP_I2C7
+	select EXYNOS4_SETUP_DP
+	select EXYNOS4_SETUP_SDHCI
+	select EXYNOS4_DEV_DWMCI
+	select EXYNOS4_SETUP_FIMD
+	select EXYNOS4_SETUP_USB_PHY
+	select SAMSUNG_DEV_BACKLIGHT
+	select SAMSUNG_DEV_PWM
+	select EXYNOS4_SETUP_MFC
+	select EXYNOS_DEV_SS_UDC
+	select SAMSUNG_DEV_ADC
+	select EXYNOS4_SETUP_THERMAL
+	help
+	  Machine support for Samsung P10 board
+
+choice
+	prompt "P10 board"
+	depends on MACH_P10
+	default MACH_P10_00_BD
+
+config MACH_P10_00_BD
+	bool "P10 Rev 0.0 board"
+
+config MACH_P10_LTE_00_BD
+	bool "P10 LTE Rev 0.0 board"
+
+config MACH_P10_WIFI_00_BD
+	bool "P10 WIFI Rev 0.0 board"
+
+config MACH_P10_LUNGO_01_BD
+	bool "P10 lungo Rev 0.1 board"
+
+config MACH_P10_LUNGO_WIFI_01_BD
+	bool "P10 lungo Wifi Rev 0.1 board"
+
+endchoice
+choice
+	prompt "P10 DP version"
+	depends on MACH_P10
+	default MACH_P10_DP_01
+
+config MACH_P10_DP_00
+	bool "P10 DP 0.0(evt0.0)"
+
+config MACH_P10_DP_01
+	bool "P10 DP 0.1(evt0.1)"
+
+endchoice
+choice
+	prompt "DP FrameRate of P10"
+	depends on MACH_P10
+	default DP_40HZ_P10
+
+config DP_40HZ_P10
+	bool "support 40HZ for DP of P10"
+
+config DP_60HZ_P10
+	bool "support 60HZ for DP of P10"
+
+endchoice
+endmenu
+
+config EXYNOS5_DEV_BTS
+	bool "Support BTS driver"
+	select S5P_BTS
+	help
+	  Compile in platform device definitions for BTS devices
+
+menu "MMC/SD slot setup"
+depends on PLAT_S5P
+
+comment "SELECT SYNOPSYS CONTROLLER INTERFACE DRIVER"
+config EXYNOS4_DEV_DWMCI
+	bool "DWMCI"
+	depends on PLAT_S5P && MMC_DW
+	default n
+	help
+	IF DWMCI is used, SDHC channel 0 is disabled.
+
+config EXYNOS5_DEV_DWMCI1
+	bool
+	help
+	  Compile in platform device definitions for DWMCI channel 1
+
+config EXYNOS5_DEV_DWMCI2
+	bool
+	help
+	  Compile in platform device definitions for DWMCI channel 2
+
+config EXYNOS5_DEV_DWMCI3
+	bool
+	help
+	  Compile in platform device definitions for DWMCI channel 3
+
+config EXYNOS4_DEV_MSHC
+	bool "MSHCI"
+	depends on PLAT_S5P
+	default n
+	help
+	IF MSHC is used, SDHC channel 0 is disabled.
+
+choice
+	prompt "Use Special PLL for MSHC"
+	depends on PLAT_S5P && EXYNOS4_DEV_MSHC
+	help
+		This feature change MMC4OUT's clock source between MPLL and EPLL
+	default EXYNOS4_MSHC_MPLL_40MHZ
+
+config EXYNOS4_MSHC_MPLL_40MHZ
+	bool "MPLL"
+
+config EXYNOS4_MSHC_VPLL_46MHZ
+	bool "VPLL"
+
+config EXYNOS4_MSHC_EPLL_45MHZ
+	bool "EPLL"
+endchoice
+
+comment "Use 8-bit bus width"
+
+config EXYNOS4_MSHC_8BIT
+	bool "MSHC with 8-bit bus"
+	depends on PLAT_S5P && EXYNOS4_DEV_MSHC
+	default n
+	help
+	  IF MSHC uses 8-bit bus, SDHC channel 1 is disabled.
+
+config EXYNOS4_SDHCI_CH0_8BIT
+	bool "SDHC Channel 0 with 8-bit bus"
+	depends on PLAT_S5P && !EXYNOS4_DEV_DWMCI && !EXYNOS4_DEV_MSHC
+	default n
+	help
+	  Support HSMMC Channel 0 8-bit bus.
+	  If selected, Channel 1 is disabled.
+
+config EXYNOS4_SDHCI_CH2_8BIT
+	bool "SDHC Channel 2 with 8-bit bus"
+	help
+	  Support HSMMC Channel 2 8-bit bus.
+	  If selected, Channel 3 is disabled.
+
+comment "Use DDR"
+	depends on PLAT_S5P && EXYNOS4_DEV_MSHC
+config EXYNOS4_MSHC_DDR
+	depends on PLAT_S5P && EXYNOS4_DEV_MSHC
+	bool "MSHC with DDR mode"
+	default n
+	help
+	  Enabling DDR(Dual Data Rate) mode.
+
+endmenu
+
+comment "Miscellaneous drivers"
+config WAKEUP_ASSIST
+	bool "Wakeup assist driver"
+	depends on PM
+	help
+	  If the wakeup time is too slow, toggling POWER butten shortly causes to
+	  ignore report of key event. It makes the android system not execute wake
+	  up codes.
+
+	  If selected, the wakeup assistant driver will report POWER key event
+	  directly
+endif
+
+config EXYNOS_C2C
+	bool "C2C device support"
+	depends on SAMSUNG_C2C
+	default y
+	help
+	  Add C2C device driver
+
+config S3C64XX_DEV_SPI0
+	bool
+	depends on S3C64XX_DEV_SPI
+	default n
+	help
+	  Samsung S3C64XX series type SPI
+
+config EXYNOS_DEV_C2C
+	bool
+	depends on EXYNOS_C2C
+	default y
+
+comment "Debugging Feature"
+menuconfig SEC_DEBUG
+	bool "Samsung TN Ramdump Feature"
+	default y
+	help
+	  Samsung TN Ramdump Feature. Use INFORM3 and magic number at 0xc0000000.
+
+if SEC_DEBUG
+config SEC_DEBUG_SCHED_LOG
+	bool "Samsung Scheduler Logging Feature"
+	default n
+	help
+	  Samsung Scheduler Logging Feature for Debug use.
+
+config SEC_DEBUG_SOFTIRQ_LOG
+	bool "Samsung Softirq Logging Feature"
+	default n
+	depends on SEC_DEBUG_SCHED_LOG
+	help
+	  Samsung Softirq Logging Feature for Debug use.
+	  This option enables us to log softirq enter/exit.
+	  It is not only hard-irq which results in scheduler lockup,
+	  To be more clear we need to see also softirq logs.
+
+config SEC_DEBUG_SCHED_LOG_NONCACHED
+	bool "Samsung Scheduler Logging on noncached buf"
+	depends on SEC_DEBUG_SCHED_LOG
+	default n
+	help
+	  This option enables sec_debug_sched_log_noncached support.
+	  It can support non-cached sched log in RAM dump and We don't
+	  need to concern cache flush status for analyzing sudden
+	  lockup issue.
+
+config SEC_DEBUG_SEMAPHORE_LOG
+	bool "Samsung Semaphore Logging Feature"
+	default n
+	help
+	  Samsung Semaphore Logging Feature for Debug use.
+
+config SEC_DEBUG_USER
+	bool "Panic on Userspace fault"
+	default y
+	help
+	  Panic on Userspace fault
+
+config SEC_DEBUG_PM_TEMP
+	bool "Temporary Logging for Sleep/Wakeup Issue"
+	default n
+	help
+	  Verbose Log on Sleep/Wakeup.
+
+config SEC_DEBUG_IRQ_EXIT_LOG
+	bool "Temporary Logging for IRQ delay"
+	default n
+	help
+	  Verbose Logging for IRQ delay.
+
+config SEC_DEBUG_AUXILIARY_LOG
+	bool "Samsung Auxiliary Logging on noncached buf"
+	default n
+	help
+	  This option enables sec_auxiliary_log support.
+	  we can log repeated information insuitable for kernel log like DVFS
+	  or power domain control information.
+	  It can support non-cached auxiliary log in RAM dump and We don't
+	  need to concern cache flush status for analyzing sudden
+	  system hang issue.
+
+config SEC_DEBUG_FUPLOAD_DUMP_MORE
+	bool "Dump more information at forced upload"
+	default n
+	help
+	  More information is printed out when a forced upload happens.
+	  It uses customized dump functions instead of panic call.
+
+config SEC_DEBUG_LIST_CORRUPTION
+	bool "Panic when list corruption detected"
+	default n
+	help
+	  Panic when list structure corruption detected.
+	  Sometimes list corruptions are reported.
+	  But it reports only with WARN level.
+	  This will immediately stop the system.
+
+config SEC_DEBUG_SYSRQ_B
+	bool "Panic when sysrq(b) detected"
+	default n
+	help
+	  Panic when sysrq('b') detected.
+	  In current debuggin feature sysrq('b') will anyway lead us to upload
+	  with unknown reset, we are not handling debug flags for this.
+	  With this feature we can find out what situation sysrq('b') is used.
+
+menuconfig SEC_WATCHDOG_RESET
+	bool "S5PV310 watchdog reset to exit from lockup"
+	depends on (CPU_EXYNOS4210 || CPU_EXYNOS4212 || CPU_EXYNOS4412)
+	default n
+	help
+	  Use watchdog reset to exit from lockup
+
+if SEC_WATCHDOG_RESET
+config SEC_WATCHDOG_PET_TIME
+	int "sec watchdog kicking time interval value"
+	default 5
+endif
+
+endif
+
+config SEC_LOG
+	default n
+	bool "Enable support for sec_log" if EMBEDDED
+	depends on PRINTK
+	help
+	  This option enables sec_log support. This provides combined
+	  log buffer for both bootloader and kernel. It also preserves
+	  previous content before reboot.
+
+config SEC_LOG_NONCACHED
+	default n
+	bool "Enable non cached kernel sec_log support" if EMBEDDED
+	depends on SEC_LOG
+	help
+	  This option enables sec_non_cached_klog support.  It can
+	  support non-cached kernel log in RAM dump and We don't need
+	  to concern cache flush status for analyzing sudden lockup
+	  issue.
+
+config SEC_LOG_LAST_KMSG
+	default n
+	bool "Enable /proc/last_kmsg support" if EMBEDDED
+	depends on SEC_LOG
+	help
+	  This option enables /proc/last_kmsg support.
+
+if SEC_MODEM
+comment "Samsung Modem Feature"
+
+config LTE_VIA_SWITCH
+	bool
+	default n
+
+choice
+	prompt "SEC MODEM CONFIG"
+	depends on SEC_MODEM
+	default SEC_MODEM_M0_C2C
+
+config SEC_MODEM_M0_C2C
+	bool "M0 with xmm6262 c2c"
+	select UMTS_MODEM_XMM6262
+	select LINK_DEVICE_HSIC
+	select LINK_DEVICE_C2C
+	select SAMSUNG_C2C
+	select C2C_DEUBG
+
+config SEC_MODEM_M0
+	bool "M0 with xmm6262"
+	select UMTS_MODEM_XMM6262
+	select LINK_DEVICE_HSIC
+
+config SEC_MODEM_M0_CTC
+	bool "M0 CTC with MDM6600"
+	select CDMA_MODEM_MDM6600
+	select LINK_DEVICE_DPRAM
+	select USBHUB_USB3503
+
+config SEC_MODEM_M1
+	bool "M1 with cmc221"
+	select LTE_MODEM_CMC221
+	select LINK_DEVICE_DPRAM
+	select LINK_DEVICE_USB
+	select USBHUB_USB3503
+
+config SEC_MODEM_C1
+	bool "C1 with cmc221"
+	select LTE_MODEM_CMC221
+	select LINK_DEVICE_DPRAM
+	select LINK_DEVICE_USB
+	select USBHUB_USB3503
+
+config SEC_MODEM_C1_VZW
+	bool "C1 with CMC221 and CBP7.2"
+	select CDMA_MODEM_CBP72
+	select LTE_MODEM_CMC221
+	select LTE_VIA_SWITCH
+	select LINK_DEVICE_DPRAM
+	select LINK_DEVICE_USB
+	select USBHUB_USB3503
+
+config SEC_MODEM_C1_LGT
+	bool "C1 with CMC221 and CBP7.2"
+	select CDMA_MODEM_CBP72
+	select LTE_MODEM_CMC221
+	select LTE_VIA_SWITCH
+	select LINK_DEVICE_DPRAM
+	select LINK_DEVICE_USB
+	select USBHUB_USB3503
+
+config SEC_MODEM_C1_CTC
+	bool "C1 with MDM6600"
+	select CDMA_MODEM_MDM6600
+	select LINK_DEVICE_DPRAM
+	select USBHUB_USB3503
+
+config SEC_MODEM_M2
+	bool "M2 with MDM9x15"
+
+config SEC_MODEM_U1
+	bool "U1 with xmm6260"
+	select UMTS_MODEM_XMM6260
+	select LINK_DEVICE_HSIC
+
+config SEC_MODEM_JENGA
+	bool "JENGA with xmm6262"
+	select UMTS_MODEM_XMM6262
+	select LINK_DEVICE_HSIC
+
+config SEC_MODEM_S2PLUS
+	bool "S2PLUS with xmm6262"
+	select UMTS_MODEM_XMM6262
+	select LINK_DEVICE_HSIC
+
+config SEC_MODEM_U1_LGT
+	bool "U1 with mdm6600"
+	select CDMA_MODEM_MDM6600
+	select LINK_DEVICE_DPRAM
+
+config SEC_MODEM_GAIA
+	bool "GAIA with cmc221"
+	select LTE_MODEM_CMC221
+	select LINK_DEVICE_DPRAM
+
+endchoice
+
+endif
+
+if BT
+config BT_CSR8811
+	bool "Enable CSR8811 driver"
+	default n
+
+config BT_BCM4330
+	bool "Enable BCM4330 driver"
+	default n
+
+config BT_BCM4334
+	bool "Enable BCM4334 driver"
+	default n
+	help
+	  Adds BCM4334 RFKILL driver for Broadcom BCM4334 chipset
+
+config BT_BCM43241
+	bool "Enable BCM43241 driver"
+	default n
+	help
+	  Adds BCM43241 RFKILL driver for Broadcom BCM4334 chipset
+
+config BT_MGMT
+	bool "Bluetooth Mgmt"
+	default n
+	help
+	  This is for bluetooth mgmt
+endif
+
+comment "Qualcomm Modem Feature"
+config QC_MODEM
+	bool "Qualcomm modem support"
+	default n
+
+config MSM_SUBSYSTEM_RESTART
+	bool "QC Modem restart handler"
+	default n
+
+config QC_MODEM_MDM9X15
+	bool "support QC mdm9x15 modem"
+	default n
+
+if QC_MODEM
+choice
+	prompt "QC MODEM CONFIG"
+	depends on QC_MODEM
+	default QC_MODEM_M3
+
+config QC_MODEM_M3
+	bool "M3 support QMI inteface over HSIC"
+	select MODEM_SUPPORT_QMI_INTERFACE
+	select MSM_SUBSYSTEM_RESTART
+	select USB_QCOM_DIAG_BRIDGE
+	select USB_QCOM_MDM_BRIDGE
+	select QC_MODEM_MDM9X15
+	select MSM_RMNET_USB
+
+endchoice
+endif
+
+config SAMSUNG_PRODUCT_SHIP
+	bool "set up for product shippling"
+	default n
diff --git a/arch/arm/mach-exynos/Kconfig.local b/arch/arm/mach-exynos/Kconfig.local
new file mode 100644
index 0000000..0e22814
--- /dev/null
+++ b/arch/arm/mach-exynos/Kconfig.local
@@ -0,0 +1,136 @@
+choice
+	prompt "Target Locale"
+	default TARGET_LOCALE_EUR
+
+config TARGET_LOCALE_EUR
+	bool "Europe Open"
+
+config TARGET_LOCALE_LTN
+	bool "Latin"
+
+config TARGET_LOCALE_KOR
+	bool "Kor"
+
+config TARGET_LOCALE_NAATT_TEMP
+	bool "NAGSM"
+
+config TARGET_LOCALE_P2EUR_TEMP
+	bool "P2EUR"
+
+config TARGET_LOCALE_P2TMO_TEMP
+	bool "P2TMO"
+
+config TARGET_LOCALE_EUR_U1_NFC
+	bool "Europe Open NFC"
+
+config TARGET_LOCALE_NTT
+	bool "JPN"
+
+config TARGET_LOCALE_CHN
+	bool "Chinese"
+
+config TARGET_LOCALE_USA
+	bool "USA"
+
+endchoice
+
+choice
+	prompt "C1 USA Target Carrier"
+	depends on MACH_C1 && (TARGET_LOCALE_EUR || TARGET_LOCALE_USA)
+	default MACH_C1_USA_ATT
+
+config MACH_C1_USA_ATT
+	bool "ATT"
+
+config MACH_C1_USA_VZW
+	bool "VZW"
+endchoice
+
+choice
+	prompt "U1 KOR Target Carrier"
+	depends on MACH_U1 && TARGET_LOCALE_KOR
+	default MACH_U1_KOR_SKT
+
+config MACH_U1_KOR_SKT
+	bool "SKT"
+
+config MACH_U1_KOR_KT
+	bool "KT"
+
+config MACH_U1_KOR_LGT
+	bool "LG U+"
+endchoice
+
+choice
+	prompt "C1 KOR Target Carrier"
+	depends on (MACH_C1 || MACH_C1VZW) && TARGET_LOCALE_KOR
+	default MACH_C1_KOR_SKT
+
+config MACH_C1_KOR_SKT
+	bool "SKT"
+
+config MACH_C1_KOR_KT
+	bool "KT"
+
+config MACH_C1_KOR_LGT
+	bool "LG U+"
+endchoice
+
+choice
+	prompt "M0 KOR Target Carrier"
+	depends on MACH_M0 && TARGET_LOCALE_KOR
+	default MACH_M0_KOR_SKT
+
+config MACH_M0_KOR_SKT
+	bool "SKT"
+
+config MACH_M0_KOR_KT
+	bool "KT"
+
+config MACH_M0_KOR_LGT
+	bool "LG U+"
+endchoice
+
+choice
+	prompt "P4 KOR Target Carrier"
+	depends on MACH_P4 && TARGET_LOCALE_KOR
+	default MACH_P4_KOR_ANY
+
+config MACH_P4_KOR_ANY
+	bool "P4 KOR OPEN Board"
+endchoice
+
+choice
+	prompt "M0 Chinese Target Carrier"
+	depends on MACH_M0 && TARGET_LOCALE_CHN
+
+config MACH_M0_CMCC
+	bool "M0 CHN CMCC board"
+
+config MACH_M0_CHNOPEN
+	bool "M0 CHN OPEN board"
+
+config MACH_M0_HKTW
+	bool "M0 CHN HKTW board"
+
+config MACH_M0_CTC
+	bool "M0 CHN CTC board"
+endchoice
+
+choice
+	prompt "Q1 Chinese Target Carrier"
+	depends on MACH_U1 && TARGET_LOCALE_CHN
+
+config MACH_Q1_CMCC_BD
+	bool "Q1 CHN CMCC board"
+endchoice
+
+
+menu "M0 CTC based models"
+	depends on MACH_M0_CTC && TARGET_LOCALE_CHN
+
+config MACH_M0_GRANDECTC
+	bool "M0 CHN GRANDE CTC board"
+endmenu
+
+
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
new file mode 100644
index 0000000..cf1d352
--- /dev/null
+++ b/arch/arm/mach-exynos/Makefile
@@ -0,0 +1,224 @@
+# arch/arm/mach-exynos/Makefile
+#
+# Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+#		http://www.samsung.com/
+#
+# Licensed under GPLv2
+
+ifneq ($(CONFIG_CMA),y)
+obj-y				:= reserve_mem-exynos4.o
+endif
+obj-m				:=
+obj-n				:=
+obj-				:=
+
+# Core support for EXYNOS system
+
+obj-y				+= init.o irq-combiner.o dma.o irq-eint.o ppmu.o
+obj-$(CONFIG_ARM_TRUSTZONE)	+= irq-sgi.o
+obj-$(CONFIG_ARCH_EXYNOS4)	+= exynos4-smc.o cpu-exynos4.o clock-exynos4.o pmu-exynos4.o ppc.o
+
+CFLAGS_exynos4-smc.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
+obj-$(CONFIG_ARCH_EXYNOS5)	+= cpu-exynos5.o clock-exynos5.o pmu-exynos5.o
+
+obj-y				+= clock-domain.o
+obj-$(CONFIG_CPU_EXYNOS4210)	+= clock-exynos4210.o
+obj-$(CONFIG_CPU_EXYNOS4212)	+= clock-exynos4212.o
+obj-$(CONFIG_EXYNOS4_PM)	+= pm-exynos4.o sleep-exynos4.o
+AFLAGS_sleep-exynos4.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
+
+obj-$(CONFIG_EXYNOS5_PM)	+= pm-exynos5.o sleep-exynos5.o
+obj-$(CONFIG_CPU_FREQ)		+= cpufreq.o
+obj-$(CONFIG_EXYNOS4_CPUFREQ)	+= asv.o asv-4210.o asv-4x12.o
+obj-$(CONFIG_EXYNOS4_CPUFREQ)	+= cpufreq-4210.o cpufreq-4x12.o
+obj-$(CONFIG_EXYNOS5_CPUFREQ)	+= asv.o asv-5250.o
+obj-$(CONFIG_EXYNOS5_CPUFREQ)	+= cpufreq-5250.o
+obj-$(CONFIG_EXYNOS4_CPUIDLE)	+= cpuidle-exynos4.o idle-exynos4.o
+AFLAGS_idle-exynos4.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
+
+obj-$(CONFIG_EXYNOS5_CPUIDLE)	+= cpuidle-exynos5.o idle-exynos5.o
+
+obj-$(CONFIG_BUSFREQ)		+= busfreq.o
+obj-$(CONFIG_BUSFREQ_OPP)	+= dev.o
+ifeq ($(CONFIG_BUSFREQ_OPP),y)
+obj-$(CONFIG_ARCH_EXYNOS4)	+= busfreq_opp_exynos4.o busfreq_opp_4x12.o
+obj-$(CONFIG_ARCH_EXYNOS5)	+= busfreq_opp_exynos5.o busfreq_opp_5250.o
+endif
+
+obj-$(CONFIG_SMP)		+= platsmp.o headsmp.o
+
+obj-$(CONFIG_EXYNOS_MCT)	+= mct.o
+
+obj-$(CONFIG_HOTPLUG_CPU)	+= hotplug.o
+
+obj-$(CONFIG_STAND_ALONE_POLICY)	+= stand-hotplug.o
+obj-$(CONFIG_LEGACY_HOTPLUG_POLICY)	+= pm-hotplug.o
+obj-$(CONFIG_WITH_DVFS_POLICY)		+= dvfs-hotplug.o
+obj-$(CONFIG_DVFS_NR_RUNNING_POLICY)	+= dynamic-dvfs-nr_running-hotplug.o
+obj-$(CONFIG_NR_RUNNING_POLICY)		+= dynamic-nr_running-hotplug.o
+
+# machine support
+
+obj-$(CONFIG_MACH_SMDKC210)		+= mach-smdkv310.o
+obj-$(CONFIG_MACH_SMDKV310)		+= mach-smdkv310.o
+obj-$(CONFIG_MACH_ARMLEX4210)		+= mach-armlex4210.o
+obj-$(CONFIG_MACH_UNIVERSAL_C210)	+= mach-universal_c210.o
+ifeq ($(CONFIG_MACH_U1CAMERA_BD),y)
+obj-$(CONFIG_MACH_U1)			+= mach-u1cam.o
+else
+obj-$(CONFIG_MACH_U1)			+= mach-u1.o
+endif
+obj-$(CONFIG_MACH_U1)			+= sec-common.o sec-switch_max8997.o
+obj-$(CONFIG_MACH_U1_BD)		+= u1-gpio.o board-gps-gsd4t.o
+obj-$(CONFIG_MACH_Q1_BD)		+= q1-gpio.o board-gps-bcm475x.o
+obj-$(CONFIG_MACH_U1CAMERA_BD)		+= u1camera-gpio.o board-gps-bcm475x.o
+obj-$(CONFIG_MACH_U1)			+= u1-wlan.o
+obj-$(CONFIG_MACH_PX)			+= mach-px.o sec-common.o board-gps-bcm475x.o px-switch.o
+obj-$(CONFIG_MACH_P2)			+= p2-gpio.o
+obj-$(CONFIG_MACH_P4)			+= p4-gpio.o
+obj-$(CONFIG_MACH_P8)			+= p8-gpio.o
+obj-$(CONFIG_MACH_P10)			+= board-p10-wlan.o board-gps-bcm475x.o
+obj-$(CONFIG_PANEL_U1)			+= u1-panel.o u1-panel_a2.o u1-panel_m2.o
+obj-$(CONFIG_PANEL_S2PLUS)		+= s2plus-panel.o
+obj-$(CONFIG_MACH_U1)			+= u1_regulator_consumer.o
+obj-$(CONFIG_MACH_PX)			+= u1_regulator_consumer.o
+obj-$(CONFIG_MACH_NURI)			+= mach-nuri.o
+obj-$(CONFIG_MACH_SMDK4X12)		+= mach-smdk4x12.o
+ifeq ($(CONFIG_MACH_P4NOTE),y)
+obj-$(CONFIG_MACH_MIDAS)		+= mach-p4notepq.o px-switch.o p4note-jack.o
+else
+obj-$(CONFIG_MACH_MIDAS)		+= mach-midas.o
+endif
+obj-$(CONFIG_MACH_SMDK5210)		+= mach-smdk5210.o
+obj-$(CONFIG_MACH_SMDK5250)		+= mach-smdk5250.o
+obj-$(CONFIG_MACH_SMDK5250)		+= board-smdk5250-mmc.o
+obj-$(CONFIG_MACH_SMDK5250)		+= board-smdk5250-display.o
+obj-$(CONFIG_MACH_SMDK5250)		+= board-smdk5250-power.o
+obj-$(CONFIG_MACH_SMDK5250)		+= board-smdk5250-audio.o
+obj-$(CONFIG_MACH_SMDK5250)		+= board-smdk5250-usb.o
+obj-$(CONFIG_MACH_SMDK5250)		+= board-smdk5250-input.o
+obj-$(CONFIG_MACH_SMDK5250)		+= board-smdk5250-spi.o
+
+obj-$(CONFIG_MACH_P4NOTE)		+= p4-input.o
+
+obj-$(CONFIG_MIDAS_COMMON)		+= sec-common.o board-gps-bcm475x.o \
+					   midas-tsp.o board-midas-wlan.o \
+					   midas-camera.o midas-thermistor.o \
+					   midas-mhl.o midas-lcd.o midas-sound.o
+
+obj-$(CONFIG_P4NOTE_00_BD)		+= p4note-gpio.o p4note-power.o
+obj-$(CONFIG_GC1_00_BD)			+= gc1-gpio.o gc1-power.o
+obj-$(CONFIG_T0_00_BD)			+= midas-gpio.o midas-power.o
+obj-$(CONFIG_MIDAS_COMMON_BD)	+= midas-gpio.o midas-power.o
+obj-$(CONFIG_EXTCON)			+= midas-extcon.o
+
+obj-$(CONFIG_NAPLES_COMMON)		+= naples-gpio.o sec-common.o midas-gps.o \
+					   naples-power.o naples-tsp.o board-midas-wlan.o \
+					   naples-camera.o midas-thermistor.o \
+					   midas-mhl.o
+
+obj-$(CONFIG_PN65N_NFC)			+= midas-nfc.o
+obj-$(CONFIG_MACH_MIDAS)		+= midas-sensor.o
+obj-$(CONFIG_LEDS_LP5521)		+= midas-leds.o
+
+obj-$(CONFIG_MACH_U1)			+= sec-reboot.o
+obj-$(CONFIG_MACH_PX)			+= sec-reboot.o
+obj-$(CONFIG_MACH_MIDAS)		+= sec-reboot.o
+
+obj-$(CONFIG_MACH_P10)			+= mach-p10.o p10-gpio.o sec-common.o p10-input.o \
+					   p10-switch.o p10-battery.o midas-sound.o p10-mhl.o
+
+# device support
+
+obj-$(CONFIG_ARCH_EXYNOS)		+= dev-audio.o
+obj-$(CONFIG_EXYNOS5_DEV_AHCI)		+= dev-ahci-exynos5.o
+obj-$(CONFIG_EXYNOS4_DEV_AHCI)		+= dev-ahci.o
+obj-$(CONFIG_EXYNOS_DEV_PD)		+= dev-pd.o
+ifeq ($(CONFIG_EXYNOS_DEV_PD),y)
+obj-$(CONFIG_ARCH_EXYNOS4)		+= dev-pd-exynos4.o
+obj-$(CONFIG_ARCH_EXYNOS5)		+= dev-pd-exynos5.o
+endif
+obj-$(CONFIG_S5P_SYSTEM_MMU)		+= dev-sysmmu-exynos4.o
+obj-$(CONFIG_EXYNOS_DEV_SYSMMU)		+= dev-sysmmu.o
+obj-$(CONFIG_EXYNOS4_DEV_DWMCI)		+= dev-dwmci.o
+obj-$(CONFIG_EXYNOS_DEV_C2C)		+= dev-c2c.o
+obj-$(CONFIG_EXYNOS4_DEV_FIMC_IS)	+= dev-fimc-is.o
+obj-$(CONFIG_EXYNOS4_DEV_FIMC_LITE)	+= dev-fimc-lite.o
+obj-$(CONFIG_EXYNOS5_DEV_GSC)		+= dev-gsc.o
+
+obj-$(CONFIG_EXYNOS4_SETUP_FIMC)	+= setup-fimc.o
+obj-$(CONFIG_EXYNOS4_SETUP_FIMC0)	+= setup-fimc0.o
+obj-$(CONFIG_EXYNOS4_SETUP_FIMC1)	+= setup-fimc1.o
+obj-$(CONFIG_EXYNOS4_SETUP_FIMC2)	+= setup-fimc2.o
+obj-$(CONFIG_EXYNOS4_SETUP_FIMC3)	+= setup-fimc3.o
+obj-$(CONFIG_EXYNOS4_SETUP_CSIS)	+= setup-csis.o
+obj-$(CONFIG_EXYNOS4_SETUP_FIMD0)	+= setup-fimd0.o
+obj-$(CONFIG_EXYNOS4_SETUP_FIMD)	+= setup-fimd.o
+obj-$(CONFIG_EXYNOS4_SETUP_DP)		+= setup-dp.o
+obj-$(CONFIG_EXYNOS4_SETUP_FIMC_IS)	+= setup-fimc-is.o
+obj-$(CONFIG_EXYNOS5_SETUP_GSC)		+= setup-gsc.o
+obj-$(CONFIG_EXYNOS4_SETUP_HDMI)	+= setup-hdmi.o
+obj-y					+= setup-i2c0.o
+obj-$(CONFIG_EXYNOS4_SETUP_I2C1)	+= setup-i2c1.o
+obj-$(CONFIG_EXYNOS4_SETUP_I2C2)	+= setup-i2c2.o
+obj-$(CONFIG_EXYNOS4_SETUP_I2C3)	+= setup-i2c3.o
+obj-$(CONFIG_EXYNOS4_SETUP_I2C4)	+= setup-i2c4.o
+obj-$(CONFIG_EXYNOS4_SETUP_I2C5)	+= setup-i2c5.o
+obj-$(CONFIG_EXYNOS4_SETUP_I2C6)	+= setup-i2c6.o
+obj-$(CONFIG_EXYNOS4_SETUP_I2C7)	+= setup-i2c7.o
+obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD)	+= setup-keypad.o
+obj-$(CONFIG_EXYNOS4_SETUP_MFC)		+= setup-mfc.o
+obj-$(CONFIG_EXYNOS4_SETUP_SDHCI)	+= setup-sdhci.o
+obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO)	+= setup-sdhci-gpio.o
+obj-$(CONFIG_EXYNOS4_SETUP_MSHCI)	+= setup-mshci.o
+obj-$(CONFIG_EXYNOS4_SETUP_MSHCI_GPIO)	+= setup-mshci-gpio.o
+
+obj-$(CONFIG_S3C64XX_DEV_SPI)		+= dev-spi.o
+
+obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY)	+= setup-usb-phy.o
+obj-$(CONFIG_EXYNOS4_SETUP_FB_S5P)	+= setup-fb-s5p.o
+obj-$(CONFIG_EXYNOS4_SETUP_TVOUT)	+= setup-tvout.o
+obj-$(CONFIG_EXYNOS4_SETUP_JPEG)	+= setup-jpeg.o
+obj-$(CONFIG_EXYNOS4_SETUP_THERMAL)	+= tmu.o
+obj-$(CONFIG_EXYNOS_SETUP_THERMAL)	+= tmu_exynos.o
+obj-$(CONFIG_EXYNOS4_SETUP_MIPI_DSI)	+= setup-dsim.o
+obj-$(CONFIG_EXYNOS4_SETUP_MIPI_DSIM)	+= setup-mipidsim.o
+obj-$(CONFIG_EXYNOS_CONTENT_PATH_PROTECTION) += secmem-allocdev.o
+obj-$(CONFIG_EXYNOS_C2C)		+= setup-c2c.o
+obj-$(CONFIG_SEC_MODEM_M0_C2C)		+= board-midas-modems.o
+ifeq ($(CONFIG_MACH_P4NOTE),y)
+obj-$(CONFIG_SEC_MODEM_M0)		+= board-p4notepq-modems.o
+else
+obj-$(CONFIG_SEC_MODEM_M0)		+= board-m0-modems.o
+endif
+obj-$(CONFIG_SEC_MODEM_M0_TD)           += board-m0-td-modems.o
+obj-$(CONFIG_SEC_MODEM_M0_CTC)		+= board-m0ctc-modems.o
+#obj-$(CONFIG_SEC_MODEM_M1)		+= board-m1-modems.o
+obj-$(CONFIG_SEC_MODEM_GAIA)		+= board-gaia-modems.o
+obj-$(CONFIG_SEC_MODEM_M1)		+= board-c1-modems.o
+obj-$(CONFIG_SEC_MODEM_C1)		+= board-c1-modems.o
+obj-$(CONFIG_SEC_MODEM_C1_VZW)		+= board-c1vzw-modems.o
+obj-$(CONFIG_SEC_MODEM_C1_LGT)		+= board-c1lgt-modems.o
+obj-$(CONFIG_SEC_MODEM_C1_CTC)		+= board-c1ctc-modems.o
+obj-$(CONFIG_SEC_MODEM_U1)		+= board-u1-modems.o
+obj-$(CONFIG_SEC_MODEM_JENGA)		+= board-jenga-modems.o
+obj-$(CONFIG_SEC_MODEM_S2PLUS)		+= board-s2plus-modems.o
+obj-$(CONFIG_SEC_MODEM_U1_LGT)		+= board-u1-lgt-modems.o
+obj-$(CONFIG_SEC_DEBUG)			+= sec_debug.o sec_getlog.o sec_gaf.o
+obj-$(CONFIG_SEC_WATCHDOG_RESET)	+= sec_watchdog.o
+obj-$(CONFIG_SEC_LOG)			+= sec_log.o
+obj-$(CONFIG_EXYNOS5_DEV_BTS)		+= bts.o
+
+obj-$(CONFIG_WAKEUP_ASSIST)		+= wakeup_assist.o
+obj-$(CONFIG_BT_CSR8811)		+= board-bluetooth-csr8811.o
+obj-$(CONFIG_ION_EXYNOS)		+= dev-ion.o
+obj-$(CONFIG_MFD_MAX77693)		+= sec-switch.o
+obj-$(CONFIG_BT_BCM4330)		+= board-bluetooth-bcm4330.o
+obj-$(CONFIG_BT_BCM4334)		+= board-bluetooth-bcm4334.o
+obj-$(CONFIG_BT_BCM43241)		+= board-bluetooth-bcm43241.o
+obj-$(CONFIG_GPS_BCM47511)		+= bcm47511.o
+obj-$(CONFIG_SEC_THERMISTOR)		+= sec_thermistor.o
+obj-$(CONFIG_EXYNOS_SYSREG_PM)		+= sysreg.o
+
+obj-$(CONFIG_QC_MODEM_MDM9X15)	+= mdm2.o mdm_common.o mdm_device.o
+obj-$(CONFIG_MSM_SUBSYSTEM_RESTART)	+= subsystem_notif.o subsystem_restart.o
diff --git a/arch/arm/mach-exynos/Makefile.boot b/arch/arm/mach-exynos/Makefile.boot
new file mode 100644
index 0000000..d65956f
--- /dev/null
+++ b/arch/arm/mach-exynos/Makefile.boot
@@ -0,0 +1,2 @@
+   zreladdr-y	:= 0x40008000
+params_phys-y	:= 0x40000100
diff --git a/arch/arm/mach-exynos/asv-4210.c b/arch/arm/mach-exynos/asv-4210.c
new file mode 100644
index 0000000..a3ef512
--- /dev/null
+++ b/arch/arm/mach-exynos/asv-4210.c
@@ -0,0 +1,457 @@
+/* linux/arch/arm/mach-exynos/asv-4210.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * EXYNOS4210 - ASV(Adaptive Supply Voltage) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/regulator/consumer.h>
+
+#include <plat/cpu.h>
+#include <plat/clock.h>
+
+#include <mach/regs-iem.h>
+#include <mach/regs-clock.h>
+#include <mach/cpufreq.h>
+#include <mach/asv.h>
+
+enum target_asv {
+	EXYNOS4210_1000,
+	EXYNOS4210_1200,
+	EXYNOS4210_1400,
+	EXYNOS4210_SINGLE_1200,
+};
+
+struct asv_judge_table exynos4210_1200_limit[] = {
+	/* HPM , IDS */
+	{8 , 4},
+	{11 , 8},
+	{14 , 12},
+	{18 , 17},
+	{21 , 27},
+	{23 , 45},
+	{25 , 55},
+};
+
+static struct asv_judge_table exynos4210_1400_limit[] = {
+	/* HPM , IDS */
+	{13 , 8},
+	{17 , 12},
+	{22 , 32},
+	{26 , 52},
+};
+
+static struct asv_judge_table exynos4210_single_1200_limit[] = {
+	/* HPM , IDS */
+	{8 , 4},
+	{14 , 12},
+	{21 , 27},
+	{25 , 55},
+};
+
+static int exynos4210_check_vdd_arm(void)
+{
+#if defined(CONFIG_REGULATOR)
+	struct regulator *arm_regulator;
+	int ret;
+
+	arm_regulator = regulator_get(NULL, "vdd_arm");
+	if (IS_ERR(arm_regulator)) {
+		pr_err("%s failed to get resource %s\n", __func__, "vdd_arm");
+		return -EINVAL;
+	}
+
+	/* Set vdd_arm to 1.2V to get hpm value */
+	ret = regulator_get_voltage(arm_regulator);
+	if (ret != 1200000) {
+		pr_info("%s: current vdd_arm(%duV), set vdd_arm (1.2V)\n",
+				__func__, ret);
+	        ret = regulator_set_voltage(arm_regulator, 1200000, 1200000);
+	        if (ret < 0) {
+	                pr_err("%s: fail to set vdd_arm(%d)\n", __func__, ret);
+			return -EINVAL;
+		}
+	} else {
+                pr_info("%s: current vdd_arm(%duV)\n", __func__, ret);
+	}
+
+	regulator_put(arm_regulator);
+#endif
+	return 0;
+}
+static int  exynos4210_hpm_clk_enable(void) 
+{
+        struct clk *clk_iec;
+        struct clk *clk_apc;
+        struct clk *clk_hpm;
+
+        /* IEC clock gate enable */
+        clk_iec = clk_get(NULL, "iec");
+        if (IS_ERR(clk_iec)) {
+                printk(KERN_ERR"ASV : IEM IEC clock get error\n");
+                return -EINVAL;
+        }
+        clk_enable(clk_iec);
+
+        /* APC clock gate enable */
+        clk_apc = clk_get(NULL, "apc");
+        if (IS_ERR(clk_apc)) {
+                printk(KERN_ERR"ASV : IEM APC clock get error\n");
+                return -EINVAL;
+        }
+        clk_enable(clk_apc);
+
+        /* hpm clock gate enalbe */
+        clk_hpm = clk_get(NULL, "hpm");
+        if (IS_ERR(clk_hpm)) {
+                printk(KERN_ERR"ASV : HPM clock get error\n");
+                return -EINVAL;
+        }
+        clk_enable(clk_hpm);
+	return 0;
+}
+
+
+static int exynos4210_hpm_clk_disble(void)
+{
+        struct clk *clk_iec;
+        struct clk *clk_apc;
+        struct clk *clk_hpm;
+
+        /* IEC clock gate enable */
+        clk_iec = clk_get(NULL, "iec");
+        if (IS_ERR(clk_iec)) {
+                printk(KERN_ERR"ASV : IEM IEC clock get error\n");
+                return -EINVAL;
+        }
+        clk_disable(clk_iec);
+
+        /* APC clock gate enable */
+        clk_apc = clk_get(NULL, "apc");
+        if (IS_ERR(clk_apc)) {
+                printk(KERN_ERR"ASV : IEM APC clock get error\n");
+                return -EINVAL;
+        }
+        clk_disable(clk_apc);
+
+        /* hpm clock gate enalbe */
+        clk_hpm = clk_get(NULL, "hpm");
+        if (IS_ERR(clk_hpm)) {
+                printk(KERN_ERR"ASV : HPM clock get error\n");
+                return -EINVAL;
+        }
+        clk_disable(clk_hpm);
+	return 0;
+}
+
+
+static int exynos4210_asv_pre_clock_init(void)
+{
+	struct clk *clk_hpm;
+	struct clk *clk_copy;
+	struct clk *clk_parent;
+	unsigned int tmp;
+
+	if(exynos4210_hpm_clk_enable())
+		return -EINVAL;
+
+	/* Change Divider - CPU1 */
+	tmp = __raw_readl(EXYNOS4_CLKDIV_CPU1);
+	tmp &= ~((0x7 << EXYNOS4_CLKDIV_CPU1_HPM_SHIFT) |
+		(0x7 << EXYNOS4_CLKDIV_CPU1_COPY_SHIFT));
+	tmp |= ((0x0 << EXYNOS4_CLKDIV_CPU1_HPM_SHIFT) |
+		(0x3 << EXYNOS4_CLKDIV_CPU1_COPY_SHIFT));
+	__raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
+
+	/* HPM SCLKMPLL */
+	tmp = __raw_readl(EXYNOS4_CLKSRC_CPU);
+	tmp &= ~(0x1 << EXYNOS4_CLKSRC_CPU_MUXHPM_SHIFT);
+	tmp |= 0x1 << EXYNOS4_CLKSRC_CPU_MUXHPM_SHIFT;
+	__raw_writel(tmp, EXYNOS4_CLKSRC_CPU);
+
+	/* PWI clock setting */
+	clk_copy = clk_get(NULL, "sclk_pwi");
+	if (IS_ERR(clk_copy)) {
+		pr_info("EXYNOS4210: ASV : SCLK_PWI clock get error\n");
+		return -EINVAL;
+	} else {
+		clk_parent = clk_get(NULL, "xusbxti");
+
+		if (IS_ERR(clk_parent)) {
+			pr_info("EXYNOS4210: ASV: MOUT_APLL clock get error\n");
+			clk_put(clk_copy);
+			return -EINVAL;
+		}
+		if (clk_set_parent(clk_copy, clk_parent))
+			pr_info("EXYNOS4210: ASV: Unable to set parent %s of clock %s.\n",
+					clk_parent->name, clk_copy->name);
+
+		clk_put(clk_parent);
+	}
+	clk_set_rate(clk_copy, 4800000);
+
+	clk_put(clk_copy);
+
+	/* HPM clock setting */
+	clk_copy = clk_get(NULL, "dout_copy");
+	if (IS_ERR(clk_copy)) {
+		pr_info("EXYNOS4210: ASV: DOUT_COPY clock get error\n");
+		return -EINVAL;
+	} else {
+		clk_parent = clk_get(NULL, "mout_mpll");
+		if (IS_ERR(clk_parent)) {
+			pr_info("EXYNOS4210: ASV: MOUT_MPLL clock get error\n");
+			clk_put(clk_copy);
+			return -EINVAL;
+		}
+		if (clk_set_parent(clk_copy, clk_parent))
+			pr_info("EXYNOS4210: ASV: Unable to set parent %s of clock %s.\n",
+					clk_parent->name, clk_copy->name);
+
+		clk_put(clk_parent);
+	}
+
+	clk_set_rate(clk_copy, (400 * 1000 * 1000));
+
+	clk_put(clk_copy);
+
+	clk_hpm = clk_get(NULL, "sclk_hpm");
+	if (IS_ERR(clk_hpm)) {
+		pr_info("EXYNOS4210: ASV: Fail to get sclk_hpm\n");
+		return -EINVAL;
+	}
+
+	clk_set_rate(clk_hpm, (200 * 1000 * 1000));
+
+	clk_put(clk_hpm);
+
+	return 0;
+}
+
+static int exynos4210_asv_pre_clock_setup(void)
+{
+	/* APLL_CON0 level register */
+	__raw_writel(0x80FA0601, EXYNOS4_APLL_CON0L8);
+	__raw_writel(0x80C80601, EXYNOS4_APLL_CON0L7);
+	__raw_writel(0x80C80602, EXYNOS4_APLL_CON0L6);
+	__raw_writel(0x80C80604, EXYNOS4_APLL_CON0L5);
+	__raw_writel(0x80C80601, EXYNOS4_APLL_CON0L4);
+	__raw_writel(0x80C80601, EXYNOS4_APLL_CON0L3);
+	__raw_writel(0x80C80601, EXYNOS4_APLL_CON0L2);
+	__raw_writel(0x80C80601, EXYNOS4_APLL_CON0L1);
+
+	/* IEM Divider register */
+	__raw_writel(0x00500000, EXYNOS4_CLKDIV_IEM_L8);
+	__raw_writel(0x00500000, EXYNOS4_CLKDIV_IEM_L7);
+	__raw_writel(0x00500000, EXYNOS4_CLKDIV_IEM_L6);
+	__raw_writel(0x00500000, EXYNOS4_CLKDIV_IEM_L5);
+	__raw_writel(0x00500000, EXYNOS4_CLKDIV_IEM_L4);
+	__raw_writel(0x00500000, EXYNOS4_CLKDIV_IEM_L3);
+	__raw_writel(0x00500000, EXYNOS4_CLKDIV_IEM_L2);
+	__raw_writel(0x00500000, EXYNOS4_CLKDIV_IEM_L1);
+
+	return 0;
+}
+
+static int exynos4210_find_group(struct samsung_asv *asv_info,
+			      enum target_asv exynos4_target)
+{
+	unsigned int ret = 0;
+	unsigned int i;
+
+	if (exynos4_target == EXYNOS4210_1200) {
+		ret = ARRAY_SIZE(exynos4210_1200_limit);
+
+		for (i = 0; i < ARRAY_SIZE(exynos4210_1200_limit); i++) {
+			if (asv_info->hpm_result <= exynos4210_1200_limit[i].hpm_limit ||
+			   asv_info->ids_result <= exynos4210_1200_limit[i].ids_limit) {
+				ret = i;
+				break;
+			}
+		}
+	} else if (exynos4_target == EXYNOS4210_1400) {
+		ret = ARRAY_SIZE(exynos4210_1400_limit);
+
+		for (i = 0; i < ARRAY_SIZE(exynos4210_1400_limit); i++) {
+			if (asv_info->hpm_result <= exynos4210_1400_limit[i].hpm_limit ||
+			   asv_info->ids_result <= exynos4210_1400_limit[i].ids_limit) {
+				ret = i;
+				break;
+			}
+		}
+	} else if (exynos4_target == EXYNOS4210_SINGLE_1200) {
+		ret = ARRAY_SIZE(exynos4210_single_1200_limit);
+
+		for (i = 0; i < ARRAY_SIZE(exynos4210_single_1200_limit); i++) {
+			if (asv_info->hpm_result <= exynos4210_single_1200_limit[i].hpm_limit ||
+			   asv_info->ids_result <= exynos4210_single_1200_limit[i].ids_limit) {
+				ret = i;
+				break;
+			}
+		}
+	}
+
+	return ret;
+}
+
+static int exynos4210_get_hpm(struct samsung_asv *asv_info)
+{
+	unsigned int i;
+	unsigned int tmp;
+	unsigned int hpm_delay = 0;
+	void __iomem *iem_base;
+
+	iem_base = ioremap(EXYNOS4_PA_IEM, (128 * 1024));
+
+	if (!iem_base) {
+		pr_info("EXYNOS: ioremap fail\n");
+		return -EPERM;
+	}
+
+	/* Clock setting to get asv value */
+	if (!asv_info->pre_clock_init) {
+		pr_info("EXYNOS: No Pre-setup function\n");
+		goto err;
+	} else {
+		if (asv_info->pre_clock_init()) {
+			pr_info("EXYNOS: pre_clock_init function fail");
+			goto err;
+		} else {
+			/* HPM enable  */
+			tmp = __raw_readl(iem_base + EXYNOS4_APC_CONTROL);
+			tmp |= APC_HPM_EN;
+			__raw_writel(tmp, (iem_base + EXYNOS4_APC_CONTROL));
+
+			asv_info->pre_clock_setup();
+
+			/* IEM enable */
+			tmp = __raw_readl(iem_base + EXYNOS4_IECDPCCR);
+			tmp |= IEC_EN;
+			__raw_writel(tmp, (iem_base + EXYNOS4_IECDPCCR));
+		}
+	}
+
+	/* Get HPM Delay value */
+	for (i = 0; i < LOOP_CNT; i++) {
+		tmp = __raw_readb(iem_base + EXYNOS4_APC_DBG_DLYCODE);
+		hpm_delay += tmp;
+	}
+
+	hpm_delay /= LOOP_CNT;
+	hpm_delay --;
+	/* Store result of hpm value */
+	asv_info->hpm_result = hpm_delay;
+
+	pr_info("EXYNOS4: HPM value = %d\n", hpm_delay);
+
+	/* HPM SCLKAPLL */
+	tmp = __raw_readl(EXYNOS4_CLKSRC_CPU);
+	tmp &= ~(0x1 << EXYNOS4_CLKSRC_CPU_MUXHPM_SHIFT);
+	tmp |= 0x0 << EXYNOS4_CLKSRC_CPU_MUXHPM_SHIFT;
+	__raw_writel(tmp, EXYNOS4_CLKSRC_CPU);
+
+	if(exynos4210_hpm_clk_disble())
+		return -EPERM;
+	return 0;
+
+err:
+	iounmap(iem_base);
+	return -EPERM;
+}
+
+static int exynos4210_get_ids(struct samsung_asv *asv_info)
+{
+	unsigned int pkg_id_val;
+
+	if (!asv_info->ids_offset || !asv_info->ids_mask) {
+		pr_info("EXYNOS4: No ids_offset or No ids_mask\n");
+		return -EPERM;
+	}
+
+	pkg_id_val = __raw_readl(S5P_VA_CHIPID + 0x4);
+	asv_info->pkg_id = pkg_id_val;
+	asv_info->ids_result = ((pkg_id_val >> asv_info->ids_offset) &
+							asv_info->ids_mask);
+
+	pr_info("EXYNOS4: IDS value = %d\n", asv_info->ids_result);
+	return 0;
+}
+
+#define PACK_ID				8
+#define PACK_MASK			0x3
+
+static int exynos4210_asv_store_result(struct samsung_asv *asv_info)
+{
+	unsigned int result_grp;
+	char *support_freq;
+
+	/* Single chip is only support 1.2GHz */
+	if (!((samsung_cpu_id >> PACK_ID) & PACK_MASK)) {
+		result_grp = exynos4210_find_group(asv_info, EXYNOS4210_SINGLE_1200);
+		result_grp |= SUPPORT_1200MHZ;
+		support_freq = "1.2GHz";
+
+		goto set_reg;
+	}
+
+	/* Check support freq */
+	switch (asv_info->pkg_id & 0x7) {
+	/* Support 1.2GHz */
+	case 1:
+	case 7:
+		result_grp = exynos4210_find_group(asv_info, EXYNOS4210_1200);
+		result_grp |= SUPPORT_1200MHZ;
+		support_freq = "1.2GHz";
+		break;
+	/* Support 1.4GHz */
+	case 5:
+		result_grp = exynos4210_find_group(asv_info, EXYNOS4210_1400);
+		result_grp |= SUPPORT_1400MHZ;
+		support_freq = "1.4GHz";
+		break;
+	/* Defalut support 1.0GHz */
+	default:
+		result_grp = exynos4210_find_group(asv_info, EXYNOS4210_1000);
+		result_grp |= SUPPORT_1000MHZ;
+		support_freq = "1.0GHz";
+		break;
+	}
+
+set_reg:
+	exynos_result_of_asv = result_grp;
+
+	pr_info(KERN_INFO "Support %s\n", support_freq);
+	pr_info(KERN_INFO "ASV Group for This Exynos4210 is 0x%x\n", exynos_result_of_asv);
+
+	return 0;
+}
+
+int exynos4210_asv_init(struct samsung_asv *asv_info)
+{
+	pr_info("EXYNOS4210: Adaptive Support Voltage init\n");
+
+	exynos_result_of_asv = 0;
+
+	asv_info->ids_offset = 24;
+	asv_info->ids_mask = 0xFF;
+
+	asv_info->get_ids = exynos4210_get_ids;
+	asv_info->get_hpm = exynos4210_get_hpm;
+	asv_info->check_vdd_arm = exynos4210_check_vdd_arm;
+	asv_info->pre_clock_init = exynos4210_asv_pre_clock_init;
+	asv_info->pre_clock_setup = exynos4210_asv_pre_clock_setup;
+	asv_info->store_result = exynos4210_asv_store_result;
+
+	return 0;
+}
diff --git a/arch/arm/mach-exynos/asv-4x12.c b/arch/arm/mach-exynos/asv-4x12.c
new file mode 100644
index 0000000..5eeaf20
--- /dev/null
+++ b/arch/arm/mach-exynos/asv-4x12.c
@@ -0,0 +1,190 @@
+/* linux/arch/arm/mach-exynos/asv-4x12.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * EXYNOS4X12 - ASV(Adaptive Supply Voltage) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <mach/asv.h>
+#include <mach/map.h>
+#include <plat/cpu.h>
+
+/* ASV function for Fused Chip */
+#define IDS_ARM_OFFSET		24
+#define IDS_ARM_MASK		0xFF
+#define HPM_OFFSET		12
+#define HPM_MASK		0x1F
+
+#define FUSED_SG_OFFSET		3
+#define ORIG_SG_OFFSET		17
+#define ORIG_SG_MASK		0xF
+#define MOD_SG_OFFSET		21
+#define MOD_SG_MASK		0x7
+
+#define DEFAULT_ASV_GROUP	1
+
+#define CHIP_ID_REG		(S5P_VA_CHIPID + 0x4)
+
+struct asv_judge_table exynos4x12_limit[] = {
+	/* HPM, IDS */
+	{  0,   0},		/* Reserved Group */
+	{  0,   0},		/* Reserved Group */
+	{ 14,   9},
+	{ 16,  14},
+	{ 18,  17},
+	{ 20,  20},
+	{ 21,  24},
+	{ 22,  30},
+	{ 23,  34},
+	{ 24,  39},
+	{100, 100},
+	{999, 999},		/* Reserved Group */
+};
+
+struct asv_judge_table exynos4212_limit[] = {
+	/* HPM, IDS */
+	{  0,   0},		/* Reserved Group */
+	{ 17,  12},
+	{ 18,  13},
+	{ 20,  14},
+	{ 22,  18},
+	{ 24,  22},
+	{ 25,  29},
+	{ 26,  31},
+	{ 27,  35},
+	{ 28,  39},
+	{100, 100},
+	{999, 999},		/* Reserved Group */
+};
+
+static int exynos4x12_get_hpm(struct samsung_asv *asv_info)
+{
+	asv_info->hpm_result = (asv_info->pkg_id >> HPM_OFFSET) & HPM_MASK;
+
+	return 0;
+}
+
+static int exynos4x12_get_ids(struct samsung_asv *asv_info)
+{
+	asv_info->ids_result = (asv_info->pkg_id >> IDS_ARM_OFFSET) & IDS_ARM_MASK;
+
+	return 0;
+}
+
+static void exynos4x12_pre_set_abb(void)
+{
+	switch (exynos_result_of_asv) {
+	case 0:
+	case 1:
+	case 2:
+	case 3:
+		exynos4x12_set_abb(ABB_MODE_100V);
+		break;
+
+	default:
+		exynos4x12_set_abb(ABB_MODE_130V);
+		break;
+	}
+}
+
+static int exynos4x12_asv_store_result(struct samsung_asv *asv_info)
+{
+	unsigned int i;
+
+	if (soc_is_exynos4412()) {
+		for (i = 0; i < ARRAY_SIZE(exynos4x12_limit); i++) {
+			if ((asv_info->ids_result <= exynos4x12_limit[i].ids_limit) ||
+			    (asv_info->hpm_result <= exynos4x12_limit[i].hpm_limit)) {
+				exynos_result_of_asv = i;
+				break;
+			}
+		}
+	} else {
+		for (i = 0; i < ARRAY_SIZE(exynos4212_limit); i++) {
+			if ((asv_info->ids_result <= exynos4212_limit[i].ids_limit) ||
+			    (asv_info->hpm_result <= exynos4212_limit[i].hpm_limit)) {
+				exynos_result_of_asv = i;
+				break;
+			}
+		}
+
+	}
+
+	/*
+	 * If ASV result value is lower than default value
+	 * Fix with default value.
+	 */
+	if (exynos_result_of_asv < DEFAULT_ASV_GROUP)
+		exynos_result_of_asv = DEFAULT_ASV_GROUP;
+
+	pr_info("EXYNOS4X12(NO SG): IDS : %d HPM : %d RESULT : %d\n",
+		asv_info->ids_result, asv_info->hpm_result, exynos_result_of_asv);
+
+	exynos4x12_pre_set_abb();
+
+	return 0;
+}
+
+int exynos4x12_asv_init(struct samsung_asv *asv_info)
+{
+	unsigned int tmp;
+	unsigned int exynos_orig_sp;
+	unsigned int exynos_mod_sp;
+	int exynos_cal_asv;
+
+	exynos_result_of_asv = 0;
+
+	pr_info("EXYNOS4X12: Adaptive Support Voltage init\n");
+
+	tmp = __raw_readl(CHIP_ID_REG);
+
+	/* Store PKG_ID */
+	asv_info->pkg_id = tmp;
+
+	/* If Speed group is fused, get speed group from */
+	if ((tmp >> FUSED_SG_OFFSET) & 0x1) {
+		exynos_orig_sp = (tmp >> ORIG_SG_OFFSET) & ORIG_SG_MASK;
+		exynos_mod_sp = (tmp >> MOD_SG_OFFSET) & MOD_SG_MASK;
+
+		exynos_cal_asv = exynos_orig_sp - exynos_mod_sp;
+
+		/*
+		 * If There is no origin speed group,
+		 * store 1 asv group into exynos_result_of_asv.
+		 */
+		if (!exynos_orig_sp) {
+			pr_info("EXYNOS4X12: No Origin speed Group\n");
+			exynos_result_of_asv = DEFAULT_ASV_GROUP;
+		} else {
+			if (exynos_cal_asv < DEFAULT_ASV_GROUP)
+				exynos_result_of_asv = DEFAULT_ASV_GROUP;
+			else
+				exynos_result_of_asv = exynos_cal_asv;
+		}
+
+		pr_info("EXYNOS4X12(SG):  ORIG : %d MOD : %d RESULT : %d\n",
+			exynos_orig_sp, exynos_mod_sp, exynos_result_of_asv);
+
+		exynos4x12_pre_set_abb();
+
+		return -EEXIST;
+	}
+
+	asv_info->get_ids = exynos4x12_get_ids;
+	asv_info->get_hpm = exynos4x12_get_hpm;
+	asv_info->store_result = exynos4x12_asv_store_result;
+
+	return 0;
+}
diff --git a/arch/arm/mach-exynos/asv-5250.c b/arch/arm/mach-exynos/asv-5250.c
new file mode 100644
index 0000000..867154f
--- /dev/null
+++ b/arch/arm/mach-exynos/asv-5250.c
@@ -0,0 +1,200 @@
+/* linux/arch/arm/mach-exynos/asv-4x12.c
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * EXYNOS5250 - ASV(Adaptive Supply Voltage) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/string.h>
+
+#include <mach/asv.h>
+#include <mach/map.h>
+
+#include <plat/cpu.h>
+
+/* ASV function for Fused Chip */
+#define IDS_ARM_OFFSET		24
+#define IDS_ARM_MASK		0xFF
+#define HPM_OFFSET		12
+#define HPM_MASK		0x1F
+
+#define FUSED_SG_OFFSET		3
+#define ORIG_SG_OFFSET		17
+#define ORIG_SG_MASK		0xF
+#define MOD_SG_OFFSET		21
+#define MOD_SG_MASK		0x7
+
+#define DEFAULT_ASV_GROUP	1
+
+#define CHIP_ID_REG		(S5P_VA_CHIPID + 0x4)
+#define LOT_ID_REG		(S5P_VA_CHIPID + 0x14)
+
+struct asv_judge_table exynos5250_limit[] = {
+	/* HPM, IDS */
+	{  0,   0},		/* Reserved Group */
+	{  9,   7},
+	{ 10,   9},
+	{ 12,  11},
+	{ 14,  14},
+	{ 15,  17},
+	{ 16,  20},
+	{ 17,  23},
+	{ 18,  27},
+	{ 19,  30},
+	{100, 100},
+	{999, 999},		/* Reserved Group */
+};
+
+static int exynos5250_get_hpm(struct samsung_asv *asv_info)
+{
+	asv_info->hpm_result = (asv_info->pkg_id >> HPM_OFFSET) & HPM_MASK;
+
+	return 0;
+}
+
+static int exynos5250_get_ids(struct samsung_asv *asv_info)
+{
+	asv_info->ids_result = (asv_info->pkg_id >> IDS_ARM_OFFSET) & IDS_ARM_MASK;
+
+	return 0;
+}
+
+/*
+ * If lot id is "NZVPU", it is need to modify for ARM_IDS value
+ */
+static int exynos5250_check_lot_id(void)
+{
+	unsigned int lid_reg = 0;
+	unsigned int rev_lid = 0;
+	unsigned int i;
+	unsigned int tmp;
+	char lot_id[5];
+
+	lid_reg = __raw_readl(LOT_ID_REG);
+
+	for (i = 0; i < 32; i++) {
+		tmp = (lid_reg >> i) & 0x1;
+		rev_lid += tmp << (31 - i);
+	}
+
+	lot_id[0] = 'N';
+	lid_reg = (rev_lid >> 11) & 0x1FFFFF;
+
+	for (i = 4; i >= 1; i--) {
+		tmp = lid_reg % 36;
+		lid_reg /= 36;
+		lot_id[i] = (tmp < 10) ? (tmp + '0') : ((tmp - 10) + 'A');
+	}
+
+	return strncmp(lot_id, "NZVPU", ARRAY_SIZE(lot_id));
+}
+
+static void exynos5250_pre_set_abb(void)
+{
+	switch (exynos_result_of_asv) {
+	case 0:
+	case 1:
+	case 2:
+		exynos4x12_set_abb(ABB_MODE_080V);
+		break;
+	case 3:
+	case 4:
+		exynos4x12_set_abb(ABB_MODE_BYPASS);
+		break;
+	default:
+		exynos4x12_set_abb(ABB_MODE_130V);
+		break;
+	}
+}
+
+static int exynos5250_asv_store_result(struct samsung_asv *asv_info)
+{
+	unsigned int i;
+
+	if (!exynos5250_check_lot_id())
+		asv_info->ids_result -= 15;
+
+	if (soc_is_exynos5250()) {
+		for (i = 0; i < ARRAY_SIZE(exynos5250_limit); i++) {
+			if ((asv_info->ids_result <= exynos5250_limit[i].ids_limit) ||
+			    (asv_info->hpm_result <= exynos5250_limit[i].hpm_limit)) {
+				exynos_result_of_asv = i;
+				break;
+			}
+		}
+	}
+
+	/*
+	 * If ASV result value is lower than default value
+	 * Fix with default value.
+	 */
+	if (exynos_result_of_asv < DEFAULT_ASV_GROUP)
+		exynos_result_of_asv = DEFAULT_ASV_GROUP;
+
+	pr_info("EXYNOS5250(NO SG): IDS : %d HPM : %d RESULT : %d\n",
+		asv_info->ids_result, asv_info->hpm_result, exynos_result_of_asv);
+
+	exynos5250_pre_set_abb();
+
+	return 0;
+}
+
+int exynos5250_asv_init(struct samsung_asv *asv_info)
+{
+	unsigned int tmp;
+	unsigned int exynos_orig_sp;
+	unsigned int exynos_mod_sp;
+	int exynos_cal_asv;
+
+	exynos_result_of_asv = 0;
+
+	pr_info("EXYNOS5250: Adaptive Support Voltage init\n");
+
+	tmp = __raw_readl(CHIP_ID_REG);
+
+	/* Store PKG_ID */
+	asv_info->pkg_id = tmp;
+
+	/* If Speed group is fused, get speed group from */
+	if ((tmp >> FUSED_SG_OFFSET) & 0x1) {
+		exynos_orig_sp = (tmp >> ORIG_SG_OFFSET) & ORIG_SG_MASK;
+		exynos_mod_sp = (tmp >> MOD_SG_OFFSET) & MOD_SG_MASK;
+
+		exynos_cal_asv = exynos_orig_sp - exynos_mod_sp;
+		/*
+		 * If There is no origin speed group,
+		 * store 1 asv group into exynos_result_of_asv.
+		 */
+		if (!exynos_orig_sp) {
+			pr_info("EXYNOS5250: No Origin speed Group\n");
+			exynos_result_of_asv = DEFAULT_ASV_GROUP;
+		} else {
+			if (exynos_cal_asv < DEFAULT_ASV_GROUP)
+				exynos_result_of_asv = DEFAULT_ASV_GROUP;
+			else
+				exynos_result_of_asv = exynos_cal_asv;
+		}
+
+		pr_info("EXYNOS5250(SG):  ORIG : %d MOD : %d RESULT : %d\n",
+			exynos_orig_sp, exynos_mod_sp, exynos_result_of_asv);
+
+		return -EEXIST;
+	}
+
+	asv_info->get_ids = exynos5250_get_ids;
+	asv_info->get_hpm = exynos5250_get_hpm;
+	asv_info->store_result = exynos5250_asv_store_result;
+
+	return 0;
+}
diff --git a/arch/arm/mach-exynos/asv.c b/arch/arm/mach-exynos/asv.c
new file mode 100644
index 0000000..4a58ad0
--- /dev/null
+++ b/arch/arm/mach-exynos/asv.c
@@ -0,0 +1,105 @@
+/* linux/arch/arm/mach-exynos/asv.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * EXYNOS4 - ASV(Adaptive Supply Voltage) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+
+#include <plat/cpu.h>
+
+#include <mach/map.h>
+#include <mach/regs-iem.h>
+#include <mach/asv.h>
+
+static struct samsung_asv *exynos_asv;
+unsigned int exynos_result_of_asv;
+
+static int __init exynos4_asv_init(void)
+{
+	int ret = -EINVAL;
+
+	exynos_asv = kzalloc(sizeof(struct samsung_asv), GFP_KERNEL);
+	if (!exynos_asv)
+		goto out1;
+
+	if (soc_is_exynos4210())
+		ret = exynos4210_asv_init(exynos_asv);
+	else if (soc_is_exynos4412() || soc_is_exynos4212()) {
+		ret = exynos4x12_asv_init(exynos_asv);
+
+		/*
+		 * If return value is not zero,
+		 * There is already value for asv group.
+		 * So, It is not necessary to execute for getting asv group.
+		 */
+		if (ret) {
+			kfree(exynos_asv);
+			return 0;
+		}
+	} else if (soc_is_exynos5250())  {
+		ret = exynos5250_asv_init(exynos_asv);
+                if (ret)
+                        return 0;
+	} else {
+		pr_info("EXYNOS: There is no type for ASV\n");
+		goto out2;
+	}
+
+	if (exynos_asv->check_vdd_arm) {
+		if (exynos_asv->check_vdd_arm()) {
+			pr_info("EXYNOS: It is wrong vdd_arm\n");
+			goto out2;
+		}
+	}
+
+	/* Get HPM Delay value */
+	if (exynos_asv->get_hpm) {
+		if (exynos_asv->get_hpm(exynos_asv)) {
+			pr_info("EXYNOS: Fail to get HPM Value\n");
+			goto out2;
+		}
+	} else {
+		pr_info("EXYNOS: Fail to get HPM Value\n");
+		goto out2;
+	}
+
+	/* Get IDS ARM Value */
+	if (exynos_asv->get_ids) {
+		if (exynos_asv->get_ids(exynos_asv)) {
+			pr_info("EXYNOS: Fail to get IDS Value\n");
+			goto out2;
+		}
+	} else {
+		pr_info("EXYNOS: Fail to get IDS Value\n");
+		goto out2;
+	}
+
+	if (exynos_asv->store_result) {
+		if (exynos_asv->store_result(exynos_asv)) {
+			pr_info("EXYNOS: Can not success to store result\n");
+			goto out2;
+		}
+	} else {
+		pr_info("EXYNOS: No store_result function\n");
+		goto out2;
+	}
+
+	return 0;
+out2:
+	kfree(exynos_asv);
+out1:
+	return -EINVAL;
+}
+device_initcall_sync(exynos4_asv_init);
diff --git a/arch/arm/mach-exynos/bcm47511.c b/arch/arm/mach-exynos/bcm47511.c
new file mode 100644
index 0000000..1ae2c8b
--- /dev/null
+++ b/arch/arm/mach-exynos/bcm47511.c
@@ -0,0 +1,253 @@
+/*
+ *  bcm47511.c: Machine specific driver for GPS module
+ *
+ *  Copyright (c) 2011 Samsung Electronics
+ *  Minho Ban <mhban@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mutex.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+#include <linux/rfkill.h>
+#include <linux/regulator/machine.h>
+
+#include <mach/gpio.h>
+#include <mach/bcm47511.h>
+
+#include <plat/gpio-cfg.h>
+
+struct bcm47511_data {
+	struct bcm47511_platform_data	*pdata;
+	struct rfkill			*rfk;
+	bool				in_use;
+	bool				regulator_state;
+	struct regulator		*regulator;
+};
+
+static void bcm47511_enable(void *data)
+{
+	struct bcm47511_data *bd = data;
+	struct bcm47511_platform_data *pdata = bd->pdata;
+
+	if (bd->regulator && !bd->regulator_state) {
+		regulator_enable(bd->regulator);
+		bd->regulator_state = true;
+	}
+
+	gpio_set_value(pdata->regpu, 1);
+
+	if (gpio_is_valid(pdata->nrst))
+		gpio_set_value(pdata->nrst, 1);
+
+	if (gpio_is_valid(pdata->gps_cntl))
+		gpio_set_value(pdata->gps_cntl, 1);
+
+	bd->in_use = true;
+}
+
+static void bcm47511_disable(void *data)
+{
+	struct bcm47511_data *bd = data;
+	struct bcm47511_platform_data *pdata = bd->pdata;
+
+	gpio_set_value(pdata->regpu, 0);
+
+	if (gpio_is_valid(pdata->gps_cntl))
+		gpio_set_value(pdata->gps_cntl, 0);
+
+	if (bd->regulator && bd->regulator_state) {
+		regulator_disable(bd->regulator);
+		bd->regulator_state = false;
+	}
+
+	bd->in_use = false;
+}
+
+static int bcm47511_set_block(void *data, bool blocked)
+{
+	if (!blocked) {
+		printk(KERN_INFO "%s : Enable GPS chip\n", __func__);
+		bcm47511_enable(data);
+	} else {
+		printk(KERN_INFO "%s : Disable GPS chip\n", __func__);
+		bcm47511_disable(data);
+	}
+	return 0;
+}
+
+static const struct rfkill_ops bcm47511_rfkill_ops = {
+	.set_block = bcm47511_set_block,
+};
+
+static int __devinit bcm47511_probe(struct platform_device *dev)
+{
+	struct bcm47511_platform_data *pdata;
+	struct bcm47511_data *bd;
+	int gpio;
+	int ret = 0;
+
+	pdata = dev->dev.platform_data;
+	if (!pdata) {
+		dev_err(&dev->dev, "No plat data.\n");
+		return -EINVAL;
+	}
+
+	if (!pdata->reg32khz) {
+		dev_err(&dev->dev, "No 32KHz clock id.\n");
+		return -EINVAL;
+	}
+
+	bd = kzalloc(sizeof(struct bcm47511_data), GFP_KERNEL);
+	if (!bd)
+		return -ENOMEM;
+
+	bd->pdata = pdata;
+
+	if (gpio_is_valid(pdata->regpu)) {
+		gpio = pdata->regpu;
+
+		/* GPS_EN is low */
+		gpio_request(gpio, "GPS_EN");
+		gpio_direction_output(gpio, 0);
+	}
+
+	if (gpio_is_valid(pdata->nrst)) {
+		gpio = pdata->nrst;
+		/* GPS_nRST is high */
+		gpio_request(gpio, "GPS_nRST");
+		gpio_direction_output(gpio, 1);
+	}
+
+	/* GPS_UART_RXD */
+	if (gpio_is_valid(pdata->uart_rxd))
+		s3c_gpio_setpull(pdata->uart_rxd, S3C_GPIO_PULL_UP);
+
+	if (gpio_is_valid(pdata->gps_cntl)) {
+		gpio = pdata->gps_cntl;
+		gpio_request(gpio, "GPS_CNTL");
+		gpio_direction_output(gpio, 0);
+	}
+
+	/* Register BCM47511 to RFKILL class */
+	bd->rfk = rfkill_alloc("bcm47511", &dev->dev, RFKILL_TYPE_GPS,
+			&bcm47511_rfkill_ops, bd);
+	if (!bd->rfk) {
+		ret = -ENOMEM;
+		goto err_rfk_alloc;
+	}
+
+	bd->regulator = regulator_get(&dev->dev, pdata->reg32khz);
+	if (IS_ERR_OR_NULL(bd->regulator)) {
+		dev_err(&dev->dev, "regulator_get error (%ld)\n",
+				PTR_ERR(bd->regulator));
+		goto err_regulator;
+	}
+
+	bd->regulator_state = false;
+
+	/*
+	 * described by the comment in rfkill.h
+	 * true : turn off
+	 * false : turn on
+	 */
+	rfkill_init_sw_state(bd->rfk, true);
+	bd->in_use = false;
+
+	ret = rfkill_register(bd->rfk);
+	if (ret)
+		goto err_rfkill;
+
+	platform_set_drvdata(dev, bd);
+
+	dev_info(&dev->dev, "ready\n");
+
+	return 0;
+
+err_rfkill:
+	rfkill_destroy(bd->rfk);
+err_regulator:
+err_rfk_alloc:
+	kfree(bd);
+	return ret;
+}
+
+static int __devexit bcm47511_remove(struct platform_device *dev)
+{
+	struct bcm47511_data *bd = platform_get_drvdata(dev);
+	struct bcm47511_platform_data *pdata = bd->pdata;
+
+	rfkill_unregister(bd->rfk);
+	rfkill_destroy(bd->rfk);
+	gpio_free(pdata->regpu);
+	gpio_free(pdata->nrst);
+	kfree(bd);
+	platform_set_drvdata(dev, NULL);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int bcm47511_suspend(struct platform_device *dev, pm_message_t stata)
+{
+	struct bcm47511_data *bd = platform_get_drvdata(dev);
+	struct bcm47511_platform_data *pdata = bd->pdata;
+
+	if (bd->in_use) {
+		s5p_gpio_set_pd_cfg(pdata->regpu, S5P_GPIO_PD_OUTPUT1);
+		s5p_gpio_set_pd_cfg(pdata->nrst, S5P_GPIO_PD_OUTPUT1);
+		if (gpio_is_valid(pdata->gps_cntl))
+			s5p_gpio_set_pd_cfg(pdata->gps_cntl, S5P_GPIO_PD_OUTPUT1);
+	} else {
+		s5p_gpio_set_pd_cfg(pdata->regpu, S5P_GPIO_PD_OUTPUT0);
+		s5p_gpio_set_pd_cfg(pdata->nrst, S5P_GPIO_PD_OUTPUT0);
+		if (gpio_is_valid(pdata->gps_cntl))
+			s5p_gpio_set_pd_cfg(pdata->gps_cntl, S5P_GPIO_PD_OUTPUT0);
+	}
+
+	return 0;
+}
+
+static int bcm47511_resume(struct platform_device *dev)
+{
+	return 0;
+}
+#else
+#define bcm47511_suspend	NULL
+#define bcm47511_resume		NULL
+#endif
+
+static struct platform_driver bcm47511_driver = {
+	.probe		= bcm47511_probe,
+	.remove		= __devexit_p(bcm47511_remove),
+	.suspend	= bcm47511_suspend,
+	.resume		= bcm47511_resume,
+	.driver	= {
+		.name	= "bcm47511",
+	},
+};
+
+static int __init bcm47511_init(void)
+{
+	return platform_driver_register(&bcm47511_driver);
+}
+
+static void __exit bcm47511_exit(void)
+{
+	platform_driver_unregister(&bcm47511_driver);
+}
+
+module_init(bcm47511_init);
+module_exit(bcm47511_exit);
+
+MODULE_AUTHOR("Minho Ban <mhban@samsung.com>");
+MODULE_DESCRIPTION("BCM47511 GPS module driver");
+MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-exynos/board-bluetooth-bcm43241.c b/arch/arm/mach-exynos/board-bluetooth-bcm43241.c
new file mode 100644
index 0000000..d508638
--- /dev/null
+++ b/arch/arm/mach-exynos/board-bluetooth-bcm43241.c
@@ -0,0 +1,383 @@
+/*
+ * Bluetooth Broadcom GPIO and Low Power Mode control
+ *
+ *  Copyright (C) 2011 Samsung Electronics Co., Ltd.
+ *  Copyright (C) 2011 Google, Inc.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/hrtimer.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/rfkill.h>
+#include <linux/wakelock.h>
+
+#include <net/bluetooth/bluetooth.h>
+#include <net/bluetooth/hci_core.h>
+
+#include <asm/mach-types.h>
+
+#include <mach/gpio.h>
+#include <plat/gpio-cfg.h>
+
+#define BT_UART_CFG
+#define BT_LPM_ENABLE
+
+static struct rfkill *bt_rfkill;
+
+struct bcm_bt_lpm {
+	int wake;
+	int host_wake;
+
+	struct hrtimer enter_lpm_timer;
+	ktime_t enter_lpm_delay;
+
+	struct hci_dev *hdev;
+
+	struct wake_lock wake_lock;
+	char wake_lock_name[100];
+} bt_lpm;
+
+#ifdef BT_UART_CFG
+int bt_is_running;
+EXPORT_SYMBOL(bt_is_running);
+
+extern int s3c_gpio_slp_cfgpin(unsigned int pin, unsigned int config);
+extern int s3c_gpio_slp_setpull_updown(unsigned int pin, unsigned int config);
+
+static unsigned int bt_uart_on_table[][4] = {
+	{EXYNOS5_GPA0(0), 2, 2, S3C_GPIO_PULL_NONE},
+	{EXYNOS5_GPA0(1), 2, 2, S3C_GPIO_PULL_NONE},
+	{EXYNOS5_GPA0(2), 2, 2, S3C_GPIO_PULL_NONE},
+	{EXYNOS5_GPA0(3), 2, 2, S3C_GPIO_PULL_NONE},
+};
+
+void bt_config_gpio_table(int array_size, unsigned int (*gpio_table)[4])
+{
+	u32 i, gpio;
+
+	for (i = 0; i < array_size; i++) {
+		gpio = gpio_table[i][0];
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(gpio_table[i][1]));
+		s3c_gpio_setpull(gpio, gpio_table[i][3]);
+		if (gpio_table[i][2] != 2)
+			gpio_set_value(gpio, gpio_table[i][2]);
+	}
+}
+
+void bt_uart_rts_ctrl(int flag)
+{
+	if (!gpio_get_value(GPIO_BTREG_ON))
+		return;
+	if (flag) {
+		/* BT RTS Set to HIGH */
+		s3c_gpio_cfgpin(EXYNOS5_GPA0(3), S3C_GPIO_OUTPUT);
+		s3c_gpio_setpull(EXYNOS5_GPA0(3), S3C_GPIO_PULL_NONE);
+		gpio_set_value(EXYNOS5_GPA0(3), 1);
+		s3c_gpio_slp_cfgpin(EXYNOS5_GPA0(3), S3C_GPIO_SLP_OUT0);
+		s3c_gpio_slp_setpull_updown(EXYNOS5_GPA0(3), S3C_GPIO_PULL_NONE);
+	} else {
+		/* BT RTS Set to LOW */
+		s3c_gpio_cfgpin(EXYNOS5_GPA0(3), S3C_GPIO_OUTPUT);
+		gpio_set_value(EXYNOS5_GPA0(3), 0);
+		s3c_gpio_cfgpin(EXYNOS5_GPA0(3), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(EXYNOS5_GPA0(3), S3C_GPIO_PULL_NONE);
+	}
+}
+EXPORT_SYMBOL(bt_uart_rts_ctrl);
+#endif
+
+static int bcm43241_bt_rfkill_set_power(void *data, bool blocked)
+{
+	/* rfkill_ops callback. Turn transmitter on when blocked is false */
+	if (!blocked) {
+		pr_info("[BT] Bluetooth Power On.\n");
+#ifdef BT_UART_CFG
+		bt_config_gpio_table(ARRAY_SIZE(bt_uart_on_table),
+					bt_uart_on_table);
+#endif
+		gpio_set_value(GPIO_BTREG_ON, 1);
+		msleep(50);
+	} else {
+		pr_info("[BT] Bluetooth Power Off.\n");
+		bt_is_running = 0;
+		gpio_set_value(GPIO_BTREG_ON, 0);
+	}
+	return 0;
+}
+
+static const struct rfkill_ops bcm43241_bt_rfkill_ops = {
+	.set_block = bcm43241_bt_rfkill_set_power,
+};
+
+#ifdef BT_LPM_ENABLE
+static void set_wake_locked(int wake)
+{
+	bt_lpm.wake = wake;
+
+	if (!wake)
+		wake_unlock(&bt_lpm.wake_lock);
+
+	gpio_set_value(GPIO_BT_WAKE, wake);
+}
+
+static enum hrtimer_restart enter_lpm(struct hrtimer *timer)
+{
+	unsigned long flags;
+
+	if (bt_lpm.hdev != NULL) {
+		spin_lock_irqsave(&bt_lpm.hdev->lock, flags);
+		set_wake_locked(0);
+		spin_unlock_irqrestore(&bt_lpm.hdev->lock, flags);
+	}
+
+	bt_is_running = 0;
+
+	return HRTIMER_NORESTART;
+}
+
+static void bcm_bt_lpm_exit_lpm_locked(struct hci_dev *hdev)
+{
+	bt_lpm.hdev = hdev;
+
+	hrtimer_try_to_cancel(&bt_lpm.enter_lpm_timer);
+	bt_is_running = 1;
+	set_wake_locked(1);
+
+	pr_debug("[BT] bcm_bt_lpm_exit_lpm_locked\n");
+	hrtimer_start(&bt_lpm.enter_lpm_timer, bt_lpm.enter_lpm_delay,
+		HRTIMER_MODE_REL);
+}
+
+static void update_host_wake_locked(int host_wake)
+{
+	if (host_wake == bt_lpm.host_wake)
+		return;
+
+	bt_lpm.host_wake = host_wake;
+
+	bt_is_running = 1;
+
+	if (host_wake) {
+		wake_lock(&bt_lpm.wake_lock);
+	} else  {
+		/* Take a timed wakelock, so that upper layers can take it.
+		 * The chipset deasserts the hostwake lock, when there is no
+		 * more data to send.
+		 */
+		wake_lock_timeout(&bt_lpm.wake_lock, HZ/2);
+	}
+}
+
+static irqreturn_t host_wake_isr(int irq, void *dev)
+{
+	int host_wake;
+	unsigned long flags;
+
+	host_wake = gpio_get_value(GPIO_BT_HOST_WAKE);
+	irq_set_irq_type(irq, host_wake ? IRQF_TRIGGER_LOW : IRQF_TRIGGER_HIGH);
+
+	if (!bt_lpm.hdev) {
+		bt_lpm.host_wake = host_wake;
+		return IRQ_HANDLED;
+	}
+
+	spin_lock_irqsave(&bt_lpm.hdev->lock, flags);
+	update_host_wake_locked(host_wake);
+	spin_unlock_irqrestore(&bt_lpm.hdev->lock, flags);
+
+	return IRQ_HANDLED;
+}
+
+static int bcm_bt_lpm_init(struct platform_device *pdev)
+{
+	int irq;
+	int ret;
+
+	hrtimer_init(&bt_lpm.enter_lpm_timer, CLOCK_MONOTONIC,
+			HRTIMER_MODE_REL);
+	bt_lpm.enter_lpm_delay = ktime_set(1, 0);  /* 1 sec */
+	bt_lpm.enter_lpm_timer.function = enter_lpm;
+
+	bt_lpm.host_wake = 0;
+	bt_is_running = 0;
+
+	snprintf(bt_lpm.wake_lock_name, sizeof(bt_lpm.wake_lock_name),
+			"BTLowPower");
+	wake_lock_init(&bt_lpm.wake_lock, WAKE_LOCK_SUSPEND,
+			 bt_lpm.wake_lock_name);
+
+	irq = IRQ_BT_HOST_WAKE;
+	ret = request_irq(irq, host_wake_isr, IRQF_TRIGGER_HIGH,
+		"bt host_wake", NULL);
+	if (ret) {
+		pr_err("[BT] Request_host wake irq failed.\n");
+		return ret;
+	}
+
+	ret = irq_set_irq_wake(irq, 1);
+	if (ret) {
+		pr_err("[BT] Set_irq_wake failed.\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int bcm_hci_wake_peer(struct notifier_block *this, unsigned long event, void *ptr)
+{
+	struct hci_dev *hdev = (struct hci_dev *) ptr;
+
+	if (event == HCI_DEV_REG) {
+		if (hdev != NULL) {
+			hdev->wake_peer = bcm_bt_lpm_exit_lpm_locked;
+			pr_info("[BT] wake_peer is registered.\n");
+		}
+	} else if (event == HCI_DEV_UNREG) {
+		pr_info("[BT] %s: handle HCI_DEV_UNREG noti\n", __func__);
+		if (hdev != NULL && bt_lpm.hdev == hdev) {
+			bt_lpm.hdev = NULL;
+			pr_info("[BT] bt_lpm.hdev set to NULL\n");
+		}
+	}
+
+	return NOTIFY_DONE;
+}
+
+static struct notifier_block bcm_bt_nblock = {
+	.notifier_call = bcm_hci_wake_peer
+};
+#endif
+
+static int bcm43241_bluetooth_probe(struct platform_device *pdev)
+{
+	int rc = 0;
+	int ret;
+
+	rc = gpio_request(GPIO_BTREG_ON, "bcm43241_bten_gpio");
+	if (unlikely(rc)) {
+		pr_err("[BT] GPIO_BTREG_ON request failed.\n");
+		return rc;
+	}
+	rc = gpio_request(GPIO_BT_WAKE, "bcm43241_btwake_gpio");
+	if (unlikely(rc)) {
+		pr_err("[BT] GPIO_BT_WAKE request failed.\n");
+		gpio_free(GPIO_BTREG_ON);
+		return rc;
+	}
+	rc = gpio_request(GPIO_BT_HOST_WAKE, "bcm43241_bthostwake_gpio");
+	if (unlikely(rc)) {
+		pr_err("[BT] GPIO_BT_HOST_WAKE request failed.\n");
+		gpio_free(GPIO_BT_WAKE);
+		gpio_free(GPIO_BTREG_ON);
+		return rc;
+	}
+	gpio_direction_input(GPIO_BT_HOST_WAKE);
+	gpio_direction_output(GPIO_BT_WAKE, 0);
+	gpio_direction_output(GPIO_BTREG_ON, 0);
+
+	bt_rfkill = rfkill_alloc("bcm43241 Bluetooth", &pdev->dev,
+				RFKILL_TYPE_BLUETOOTH, &bcm43241_bt_rfkill_ops,
+				NULL);
+
+	if (unlikely(!bt_rfkill)) {
+		pr_err("[BT] bt_rfkill alloc failed.\n");
+		gpio_free(GPIO_BT_HOST_WAKE);
+		gpio_free(GPIO_BT_WAKE);
+		gpio_free(GPIO_BTREG_ON);
+		return -ENOMEM;
+	}
+
+	rfkill_init_sw_state(bt_rfkill, 0);
+
+	rc = rfkill_register(bt_rfkill);
+
+	if (unlikely(rc)) {
+		pr_err("[BT] bt_rfkill register failed.\n");
+		rfkill_destroy(bt_rfkill);
+		gpio_free(GPIO_BT_HOST_WAKE);
+		gpio_free(GPIO_BT_WAKE);
+		gpio_free(GPIO_BTREG_ON);
+		return -1;
+	}
+
+	rfkill_set_sw_state(bt_rfkill, true);
+
+#ifdef BT_LPM_ENABLE
+	ret = bcm_bt_lpm_init(pdev);
+	if (ret) {
+		rfkill_unregister(bt_rfkill);
+		rfkill_destroy(bt_rfkill);
+
+		gpio_free(GPIO_BT_HOST_WAKE);
+		gpio_free(GPIO_BT_WAKE);
+		gpio_free(GPIO_BTREG_ON);
+	}
+
+	hci_register_notifier(&bcm_bt_nblock);
+#endif
+	return rc;
+}
+
+static int bcm43241_bluetooth_remove(struct platform_device *pdev)
+{
+	rfkill_unregister(bt_rfkill);
+	rfkill_destroy(bt_rfkill);
+
+	gpio_free(GPIO_BTREG_ON);
+	gpio_free(GPIO_BT_WAKE);
+	gpio_free(GPIO_BT_HOST_WAKE);
+
+	wake_lock_destroy(&bt_lpm.wake_lock);
+
+#ifdef BT_LPM_ENABLE
+	hci_unregister_notifier(&bcm_bt_nblock);
+#endif
+	return 0;
+}
+
+static struct platform_driver bcm43241_bluetooth_platform_driver = {
+	.probe = bcm43241_bluetooth_probe,
+	.remove = bcm43241_bluetooth_remove,
+	.driver = {
+		   .name = "bcm43241_bluetooth",
+		   .owner = THIS_MODULE,
+		   },
+};
+
+static int __init bcm43241_bluetooth_init(void)
+{
+	return platform_driver_register(&bcm43241_bluetooth_platform_driver);
+}
+
+static void __exit bcm43241_bluetooth_exit(void)
+{
+	platform_driver_unregister(&bcm43241_bluetooth_platform_driver);
+}
+
+
+module_init(bcm43241_bluetooth_init);
+module_exit(bcm43241_bluetooth_exit);
+
+MODULE_ALIAS("platform:bcm43241");
+MODULE_DESCRIPTION("bcm43241_bluetooth");
+MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-exynos/board-bluetooth-bcm4330.c b/arch/arm/mach-exynos/board-bluetooth-bcm4330.c
new file mode 100644
index 0000000..624d81a
--- /dev/null
+++ b/arch/arm/mach-exynos/board-bluetooth-bcm4330.c
@@ -0,0 +1,360 @@
+/*
+ * Bluetooth Broadcom GPIO and Low Power Mode control
+ *
+ *  Copyright (C) 2011 Samsung Electronics Co., Ltd.
+ *  Copyright (C) 2011 Google, Inc.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/hrtimer.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/rfkill.h>
+#include <linux/serial_core.h>
+#include <linux/wakelock.h>
+
+#include <asm/mach-types.h>
+
+#include <mach/gpio.h>
+#include <plat/gpio-cfg.h>
+
+#define BT_UART_CFG
+#define BT_LPM_ENABLE
+
+static struct rfkill *bt_rfkill;
+
+struct bcm_bt_lpm {
+	int host_wake;
+
+	struct hrtimer enter_lpm_timer;
+	ktime_t enter_lpm_delay;
+
+	struct uart_port *uport;
+
+	struct wake_lock wake_lock;
+	char wake_lock_name[100];
+} bt_lpm;
+
+#ifdef BT_UART_CFG
+int bt_is_running;
+EXPORT_SYMBOL(bt_is_running);
+
+extern int s3c_gpio_slp_cfgpin(unsigned int pin, unsigned int config);
+extern int s3c_gpio_slp_setpull_updown(unsigned int pin, unsigned int config);
+
+static unsigned int bt_uart_on_table[][4] = {
+	{EXYNOS4_GPA0(0), 2, 2, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(1), 2, 2, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(2), 2, 2, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(3), 2, 2, S3C_GPIO_PULL_NONE},
+};
+
+void bt_config_gpio_table(int array_size, unsigned int (*gpio_table)[4])
+{
+	u32 i, gpio;
+
+	for (i = 0; i < array_size; i++) {
+		gpio = gpio_table[i][0];
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(gpio_table[i][1]));
+		s3c_gpio_setpull(gpio, gpio_table[i][3]);
+		if (gpio_table[i][2] != 2)
+			gpio_set_value(gpio, gpio_table[i][2]);
+	}
+}
+
+void bt_uart_rts_ctrl(int flag)
+{
+	if (!gpio_get_value(GPIO_BT_EN))
+		return;
+	if (flag) {
+		/* BT RTS Set to HIGH */
+		s3c_gpio_cfgpin(EXYNOS4_GPA0(3), S3C_GPIO_OUTPUT);
+		s3c_gpio_setpull(EXYNOS4_GPA0(3), S3C_GPIO_PULL_NONE);
+		gpio_set_value(EXYNOS4_GPA0(3), 1);
+		s3c_gpio_slp_cfgpin(EXYNOS4_GPA0(3), S3C_GPIO_SLP_OUT0);
+		s3c_gpio_slp_setpull_updown(EXYNOS4_GPA0(3), S3C_GPIO_PULL_NONE);
+	} else {
+		/* BT RTS Set to LOW */
+		s3c_gpio_cfgpin(EXYNOS4_GPA0(3), S3C_GPIO_OUTPUT);
+		gpio_set_value(EXYNOS4_GPA0(3), 0);
+		s3c_gpio_cfgpin(EXYNOS4_GPA0(3), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(EXYNOS4_GPA0(3), S3C_GPIO_PULL_NONE);
+	}
+}
+EXPORT_SYMBOL(bt_uart_rts_ctrl);
+#endif
+
+static int bcm4330_bt_rfkill_set_power(void *data, bool blocked)
+{
+	/* rfkill_ops callback. Turn transmitter on when blocked is false */
+	if (!blocked) {
+		pr_info("[BT] Bluetooth Power On.\n");
+#ifdef BT_UART_CFG
+		bt_config_gpio_table(ARRAY_SIZE(bt_uart_on_table),
+					bt_uart_on_table);
+#endif
+		gpio_set_value(GPIO_BT_EN, 1);
+		msleep(20);
+		gpio_set_value(GPIO_BT_nRST, 1);
+		msleep(50);
+	} else {
+		pr_info("[BT] Bluetooth Power Off.\n");
+		bt_is_running = 0;
+		gpio_set_value(GPIO_BT_nRST, 0);
+		gpio_set_value(GPIO_BT_EN, 0);
+	}
+	return 0;
+}
+
+static const struct rfkill_ops bcm4330_bt_rfkill_ops = {
+	.set_block = bcm4330_bt_rfkill_set_power,
+};
+
+#ifdef BT_LPM_ENABLE
+static void set_wake_locked(int wake)
+{
+
+	if (!wake)
+		wake_unlock(&bt_lpm.wake_lock);
+
+	gpio_set_value(GPIO_BT_WAKE, wake);
+}
+
+static enum hrtimer_restart enter_lpm(struct hrtimer *timer)
+{
+	unsigned long flags;
+	spin_lock_irqsave(&bt_lpm.uport->lock, flags);
+	bt_is_running = 0;
+	set_wake_locked(0);
+	spin_unlock_irqrestore(&bt_lpm.uport->lock, flags);
+
+	return HRTIMER_NORESTART;
+}
+
+void bcm_bt_lpm_exit_lpm_locked(struct uart_port *uport)
+{
+	bt_lpm.uport = uport;
+
+	hrtimer_try_to_cancel(&bt_lpm.enter_lpm_timer);
+	bt_is_running = 1;
+	set_wake_locked(1);
+
+	hrtimer_start(&bt_lpm.enter_lpm_timer, bt_lpm.enter_lpm_delay,
+		HRTIMER_MODE_REL);
+}
+EXPORT_SYMBOL(bcm_bt_lpm_exit_lpm_locked);
+
+static void update_host_wake_locked(int host_wake)
+{
+	if (host_wake == bt_lpm.host_wake)
+		return;
+
+	bt_lpm.host_wake = host_wake;
+
+	bt_is_running = 1;
+	if (host_wake) {
+		wake_lock(&bt_lpm.wake_lock);
+	} else  {
+		/* Take a timed wakelock, so that upper layers can take it.
+		 * The chipset deasserts the hostwake lock, when there is no
+		 * more data to send.
+		 */
+		wake_lock_timeout(&bt_lpm.wake_lock, HZ/2);
+	}
+}
+
+static irqreturn_t host_wake_isr(int irq, void *dev)
+{
+	int host_wake;
+	unsigned long flags;
+
+	host_wake = gpio_get_value(GPIO_BT_HOST_WAKE);
+	irq_set_irq_type(irq, host_wake ? IRQF_TRIGGER_LOW : IRQF_TRIGGER_HIGH);
+
+	if (!bt_lpm.uport) {
+		bt_lpm.host_wake = host_wake;
+		return IRQ_HANDLED;
+	}
+
+	spin_lock_irqsave(&bt_lpm.uport->lock, flags);
+	update_host_wake_locked(host_wake);
+	spin_unlock_irqrestore(&bt_lpm.uport->lock, flags);
+
+	return IRQ_HANDLED;
+}
+
+static int bcm_bt_lpm_init(struct platform_device *pdev)
+{
+	int irq;
+	int ret;
+
+	hrtimer_init(&bt_lpm.enter_lpm_timer, CLOCK_MONOTONIC,
+			HRTIMER_MODE_REL);
+	bt_lpm.enter_lpm_delay = ktime_set(1, 0);  /* 1 sec */
+	bt_lpm.enter_lpm_timer.function = enter_lpm;
+
+	bt_lpm.host_wake = 0;
+	bt_is_running = 0;
+
+	snprintf(bt_lpm.wake_lock_name, sizeof(bt_lpm.wake_lock_name),
+			"BTLowPower");
+	wake_lock_init(&bt_lpm.wake_lock, WAKE_LOCK_SUSPEND,
+			 bt_lpm.wake_lock_name);
+
+	irq = IRQ_BT_HOST_WAKE;
+	ret = request_irq(irq, host_wake_isr, IRQF_TRIGGER_HIGH,
+		"bt host_wake", NULL);
+	if (ret) {
+		pr_err("[BT] Request_host wake irq failed.\n");
+		return ret;
+	}
+
+	ret = irq_set_irq_wake(irq, 1);
+	if (ret) {
+		pr_err("[BT] Set_irq_wake failed.\n");
+		return ret;
+	}
+
+	return 0;
+}
+#endif
+
+static int bcm4330_bluetooth_probe(struct platform_device *pdev)
+{
+	int rc = 0;
+	int ret;
+
+	rc = gpio_request(GPIO_BT_EN, "bcm4330_bten_gpio");
+	if (unlikely(rc)) {
+		pr_err("[BT] GPIO_BT_EN request failed.\n");
+		return rc;
+	}
+	rc = gpio_request(GPIO_BT_nRST, "bcm4330_btnrst_gpio");
+	if (unlikely(rc)) {
+		pr_err("[BT] GPIO_BT_nRST request failed.\n");
+		gpio_free(GPIO_BT_EN);
+		return rc;
+	}
+	rc = gpio_request(GPIO_BT_WAKE, "bcm4330_btwake_gpio");
+	if (unlikely(rc)) {
+		pr_err("[BT] GPIO_BT_WAKE request failed.\n");
+		gpio_free(GPIO_BT_nRST);
+		gpio_free(GPIO_BT_EN);
+		return rc;
+	}
+	rc = gpio_request(GPIO_BT_HOST_WAKE, "bcm4330_bthostwake_gpio");
+	if (unlikely(rc)) {
+		pr_err("[BT] GPIO_BT_HOST_WAKE request failed.\n");
+		gpio_free(GPIO_BT_WAKE);
+		gpio_free(GPIO_BT_nRST);
+		gpio_free(GPIO_BT_EN);
+		return rc;
+	}
+	gpio_direction_input(GPIO_BT_HOST_WAKE);
+	gpio_direction_output(GPIO_BT_WAKE, 0);
+	gpio_direction_output(GPIO_BT_nRST, 0);
+	gpio_direction_output(GPIO_BT_EN, 0);
+
+	bt_rfkill = rfkill_alloc("bcm4330 Bluetooth", &pdev->dev,
+				RFKILL_TYPE_BLUETOOTH, &bcm4330_bt_rfkill_ops,
+				NULL);
+
+	if (unlikely(!bt_rfkill)) {
+		pr_err("[BT] bt_rfkill alloc failed.\n");
+		gpio_free(GPIO_BT_HOST_WAKE);
+		gpio_free(GPIO_BT_WAKE);
+		gpio_free(GPIO_BT_nRST);
+		gpio_free(GPIO_BT_EN);
+		return -ENOMEM;
+	}
+
+	rfkill_init_sw_state(bt_rfkill, 0);
+
+	rc = rfkill_register(bt_rfkill);
+
+	if (unlikely(rc)) {
+		pr_err("[BT] bt_rfkill register failed.\n");
+		rfkill_destroy(bt_rfkill);
+		gpio_free(GPIO_BT_HOST_WAKE);
+		gpio_free(GPIO_BT_WAKE);
+		gpio_free(GPIO_BT_nRST);
+		gpio_free(GPIO_BT_EN);
+		return -1;
+	}
+
+	rfkill_set_sw_state(bt_rfkill, true);
+
+#ifdef BT_LPM_ENABLE
+	ret = bcm_bt_lpm_init(pdev);
+	if (ret) {
+		rfkill_unregister(bt_rfkill);
+		rfkill_destroy(bt_rfkill);
+
+		gpio_free(GPIO_BT_HOST_WAKE);
+		gpio_free(GPIO_BT_WAKE);
+		gpio_free(GPIO_BT_nRST);
+		gpio_free(GPIO_BT_EN);
+	}
+#endif
+	return rc;
+}
+
+static int bcm4330_bluetooth_remove(struct platform_device *pdev)
+{
+	rfkill_unregister(bt_rfkill);
+	rfkill_destroy(bt_rfkill);
+
+	gpio_free(GPIO_BT_EN);
+	gpio_free(GPIO_BT_nRST);
+	gpio_free(GPIO_BT_WAKE);
+	gpio_free(GPIO_BT_HOST_WAKE);
+
+	wake_lock_destroy(&bt_lpm.wake_lock);
+	return 0;
+}
+
+static struct platform_driver bcm4330_bluetooth_platform_driver = {
+	.probe = bcm4330_bluetooth_probe,
+	.remove = bcm4330_bluetooth_remove,
+	.driver = {
+		   .name = "bcm4330_bluetooth",
+		   .owner = THIS_MODULE,
+		   },
+};
+
+static int __init bcm4330_bluetooth_init(void)
+{
+	return platform_driver_register(&bcm4330_bluetooth_platform_driver);
+}
+
+static void __exit bcm4330_bluetooth_exit(void)
+{
+	platform_driver_unregister(&bcm4330_bluetooth_platform_driver);
+}
+
+
+module_init(bcm4330_bluetooth_init);
+module_exit(bcm4330_bluetooth_exit);
+
+MODULE_ALIAS("platform:bcm4330");
+MODULE_DESCRIPTION("bcm4330_bluetooth");
+MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-exynos/board-bluetooth-bcm4334.c b/arch/arm/mach-exynos/board-bluetooth-bcm4334.c
new file mode 100644
index 0000000..7d7c00e
--- /dev/null
+++ b/arch/arm/mach-exynos/board-bluetooth-bcm4334.c
@@ -0,0 +1,380 @@
+/*
+ * Bluetooth Broadcom GPIO and Low Power Mode control
+ *
+ *  Copyright (C) 2011 Samsung Electronics Co., Ltd.
+ *  Copyright (C) 2011 Google, Inc.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/hrtimer.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/rfkill.h>
+#include <linux/wakelock.h>
+
+#include <net/bluetooth/bluetooth.h>
+#include <net/bluetooth/hci_core.h>
+
+#include <asm/mach-types.h>
+
+#include <mach/gpio.h>
+#include <plat/gpio-cfg.h>
+
+#define BT_UART_CFG
+#define BT_LPM_ENABLE
+
+static struct rfkill *bt_rfkill;
+
+struct bcm_bt_lpm {
+	int host_wake;
+
+	struct hrtimer enter_lpm_timer;
+	ktime_t enter_lpm_delay;
+
+	struct hci_dev *hdev;
+
+	struct wake_lock host_wake_lock;
+	struct wake_lock bt_wake_lock;
+	char wake_lock_name[100];
+} bt_lpm;
+
+#ifdef BT_UART_CFG
+int bt_is_running;
+EXPORT_SYMBOL(bt_is_running);
+
+extern int s3c_gpio_slp_cfgpin(unsigned int pin, unsigned int config);
+extern int s3c_gpio_slp_setpull_updown(unsigned int pin, unsigned int config);
+
+static unsigned int bt_uart_on_table[][4] = {
+	{EXYNOS4_GPA0(0), 2, 2, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(1), 2, 2, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(2), 2, 2, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(3), 2, 2, S3C_GPIO_PULL_NONE},
+};
+
+void bt_config_gpio_table(int array_size, unsigned int (*gpio_table)[4])
+{
+	u32 i, gpio;
+
+	for (i = 0; i < array_size; i++) {
+		gpio = gpio_table[i][0];
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(gpio_table[i][1]));
+		s3c_gpio_setpull(gpio, gpio_table[i][3]);
+		if (gpio_table[i][2] != 2)
+			gpio_set_value(gpio, gpio_table[i][2]);
+	}
+}
+
+void bt_uart_rts_ctrl(int flag)
+{
+	if (!gpio_get_value(GPIO_BT_EN))
+		return;
+	if (flag) {
+		/* BT RTS Set to HIGH */
+		s3c_gpio_cfgpin(EXYNOS4_GPA0(3), S3C_GPIO_OUTPUT);
+		s3c_gpio_setpull(EXYNOS4_GPA0(3), S3C_GPIO_PULL_NONE);
+		gpio_set_value(EXYNOS4_GPA0(3), 1);
+		s3c_gpio_slp_cfgpin(EXYNOS4_GPA0(3), S3C_GPIO_SLP_OUT0);
+		s3c_gpio_slp_setpull_updown(EXYNOS4_GPA0(3), S3C_GPIO_PULL_NONE);
+	} else {
+		/* BT RTS Set to LOW */
+		s3c_gpio_cfgpin(EXYNOS4_GPA0(3), S3C_GPIO_OUTPUT);
+		gpio_set_value(EXYNOS4_GPA0(3), 0);
+		s3c_gpio_cfgpin(EXYNOS4_GPA0(3), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(EXYNOS4_GPA0(3), S3C_GPIO_PULL_NONE);
+	}
+}
+EXPORT_SYMBOL(bt_uart_rts_ctrl);
+#endif
+
+static int bcm4334_bt_rfkill_set_power(void *data, bool blocked)
+{
+	/* rfkill_ops callback. Turn transmitter on when blocked is false */
+	if (!blocked) {
+		pr_info("[BT] Bluetooth Power On.\n");
+#ifdef BT_UART_CFG
+		bt_config_gpio_table(ARRAY_SIZE(bt_uart_on_table),
+					bt_uart_on_table);
+#endif
+		gpio_set_value(GPIO_BT_EN, 1);
+		msleep(50);
+	} else {
+		pr_info("[BT] Bluetooth Power Off.\n");
+		bt_is_running = 0;
+		gpio_set_value(GPIO_BT_EN, 0);
+	}
+	return 0;
+}
+
+static const struct rfkill_ops bcm4334_bt_rfkill_ops = {
+	.set_block = bcm4334_bt_rfkill_set_power,
+};
+
+#ifdef BT_LPM_ENABLE
+static void set_wake_locked(int wake)
+{
+	if (wake)
+		wake_lock(&bt_lpm.bt_wake_lock);
+
+	gpio_set_value(GPIO_BT_WAKE, wake);
+}
+
+static enum hrtimer_restart enter_lpm(struct hrtimer *timer)
+{
+	if (bt_lpm.hdev != NULL)
+		set_wake_locked(0);
+
+	bt_is_running = 0;
+	wake_lock_timeout(&bt_lpm.bt_wake_lock, HZ/2);
+
+	return HRTIMER_NORESTART;
+}
+
+static void bcm_bt_lpm_exit_lpm_locked(struct hci_dev *hdev)
+{
+	bt_lpm.hdev = hdev;
+
+	hrtimer_try_to_cancel(&bt_lpm.enter_lpm_timer);
+	bt_is_running = 1;
+	set_wake_locked(1);
+
+	pr_debug("[BT] bcm_bt_lpm_exit_lpm_locked\n");
+	hrtimer_start(&bt_lpm.enter_lpm_timer, bt_lpm.enter_lpm_delay,
+		HRTIMER_MODE_REL);
+}
+
+static void update_host_wake_locked(int host_wake)
+{
+	if (host_wake == bt_lpm.host_wake)
+		return;
+
+	bt_lpm.host_wake = host_wake;
+
+	bt_is_running = 1;
+
+	if (host_wake) {
+		wake_lock(&bt_lpm.host_wake_lock);
+	} else  {
+		/* Take a timed wakelock, so that upper layers can take it.
+		 * The chipset deasserts the hostwake lock, when there is no
+		 * more data to send.
+		 */
+		wake_lock_timeout(&bt_lpm.host_wake_lock, HZ/2);
+	}
+}
+
+static irqreturn_t host_wake_isr(int irq, void *dev)
+{
+	int host_wake;
+
+	host_wake = gpio_get_value(GPIO_BT_HOST_WAKE);
+	irq_set_irq_type(irq, host_wake ? IRQF_TRIGGER_LOW : IRQF_TRIGGER_HIGH);
+
+	if (!bt_lpm.hdev) {
+		bt_lpm.host_wake = host_wake;
+		return IRQ_HANDLED;
+	}
+
+	update_host_wake_locked(host_wake);
+
+	return IRQ_HANDLED;
+}
+
+static int bcm_bt_lpm_init(struct platform_device *pdev)
+{
+	int irq;
+	int ret;
+
+	hrtimer_init(&bt_lpm.enter_lpm_timer, CLOCK_MONOTONIC,
+			HRTIMER_MODE_REL);
+	bt_lpm.enter_lpm_delay = ktime_set(4, 0);  /* 1 sec */ /*1->3*//*3->4*/
+	bt_lpm.enter_lpm_timer.function = enter_lpm;
+
+	bt_lpm.host_wake = 0;
+	bt_is_running = 0;
+
+	snprintf(bt_lpm.wake_lock_name, sizeof(bt_lpm.wake_lock_name),
+			"BT_host_wake");
+	wake_lock_init(&bt_lpm.host_wake_lock, WAKE_LOCK_SUSPEND,
+			 bt_lpm.wake_lock_name);
+
+	snprintf(bt_lpm.wake_lock_name, sizeof(bt_lpm.wake_lock_name),
+			"BT_bt_wake");
+	wake_lock_init(&bt_lpm.bt_wake_lock, WAKE_LOCK_SUSPEND,
+			 bt_lpm.wake_lock_name);
+
+	irq = IRQ_BT_HOST_WAKE;
+	ret = request_irq(irq, host_wake_isr, IRQF_TRIGGER_HIGH,
+		"bt host_wake", NULL);
+	if (ret) {
+		pr_err("[BT] Request_host wake irq failed.\n");
+		return ret;
+	}
+
+	ret = irq_set_irq_wake(irq, 1);
+	if (ret) {
+		pr_err("[BT] Set_irq_wake failed.\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int bcm_hci_wake_peer(struct notifier_block *this, unsigned long event, void *ptr)
+{
+	struct hci_dev *hdev = (struct hci_dev *) ptr;
+
+	if (event == HCI_DEV_REG) {
+		if (hdev != NULL) {
+			hdev->wake_peer = bcm_bt_lpm_exit_lpm_locked;
+			pr_info("[BT] wake_peer is registered.\n");
+		}
+	} else if (event == HCI_DEV_UNREG) {
+		pr_info("[BT] %s: handle HCI_DEV_UNREG noti\n", __func__);
+		if (hdev != NULL && bt_lpm.hdev == hdev) {
+			bt_lpm.hdev = NULL;
+			pr_info("[BT] bt_lpm.hdev set to NULL\n");
+		}
+	}
+
+	return NOTIFY_DONE;
+}
+
+static struct notifier_block bcm_bt_nblock = {
+	.notifier_call = bcm_hci_wake_peer
+};
+#endif
+
+static int bcm4334_bluetooth_probe(struct platform_device *pdev)
+{
+	int rc = 0;
+	int ret;
+
+	rc = gpio_request(GPIO_BT_EN, "bcm4334_bten_gpio");
+	if (unlikely(rc)) {
+		pr_err("[BT] GPIO_BT_EN request failed.\n");
+		return rc;
+	}
+	rc = gpio_request(GPIO_BT_WAKE, "bcm4334_btwake_gpio");
+	if (unlikely(rc)) {
+		pr_err("[BT] GPIO_BT_WAKE request failed.\n");
+		gpio_free(GPIO_BT_EN);
+		return rc;
+	}
+	rc = gpio_request(GPIO_BT_HOST_WAKE, "bcm4334_bthostwake_gpio");
+	if (unlikely(rc)) {
+		pr_err("[BT] GPIO_BT_HOST_WAKE request failed.\n");
+		gpio_free(GPIO_BT_WAKE);
+		gpio_free(GPIO_BT_EN);
+		return rc;
+	}
+	gpio_direction_input(GPIO_BT_HOST_WAKE);
+	gpio_direction_output(GPIO_BT_WAKE, 0);
+	gpio_direction_output(GPIO_BT_EN, 0);
+
+	bt_rfkill = rfkill_alloc("bcm4334 Bluetooth", &pdev->dev,
+				RFKILL_TYPE_BLUETOOTH, &bcm4334_bt_rfkill_ops,
+				NULL);
+
+	if (unlikely(!bt_rfkill)) {
+		pr_err("[BT] bt_rfkill alloc failed.\n");
+		gpio_free(GPIO_BT_HOST_WAKE);
+		gpio_free(GPIO_BT_WAKE);
+		gpio_free(GPIO_BT_EN);
+		return -ENOMEM;
+	}
+
+	rfkill_init_sw_state(bt_rfkill, 0);
+
+	rc = rfkill_register(bt_rfkill);
+
+	if (unlikely(rc)) {
+		pr_err("[BT] bt_rfkill register failed.\n");
+		rfkill_destroy(bt_rfkill);
+		gpio_free(GPIO_BT_HOST_WAKE);
+		gpio_free(GPIO_BT_WAKE);
+		gpio_free(GPIO_BT_EN);
+		return -1;
+	}
+
+	rfkill_set_sw_state(bt_rfkill, true);
+
+#ifdef BT_LPM_ENABLE
+	ret = bcm_bt_lpm_init(pdev);
+	if (ret) {
+		rfkill_unregister(bt_rfkill);
+		rfkill_destroy(bt_rfkill);
+
+		gpio_free(GPIO_BT_HOST_WAKE);
+		gpio_free(GPIO_BT_WAKE);
+		gpio_free(GPIO_BT_EN);
+	}
+
+	hci_register_notifier(&bcm_bt_nblock);
+#endif
+	return rc;
+}
+
+static int bcm4334_bluetooth_remove(struct platform_device *pdev)
+{
+	rfkill_unregister(bt_rfkill);
+	rfkill_destroy(bt_rfkill);
+
+	gpio_free(GPIO_BT_EN);
+	gpio_free(GPIO_BT_WAKE);
+	gpio_free(GPIO_BT_HOST_WAKE);
+
+	wake_lock_destroy(&bt_lpm.host_wake_lock);
+	wake_lock_destroy(&bt_lpm.bt_wake_lock);
+
+#ifdef BT_LPM_ENABLE
+	hci_unregister_notifier(&bcm_bt_nblock);
+#endif
+	return 0;
+}
+
+static struct platform_driver bcm4334_bluetooth_platform_driver = {
+	.probe = bcm4334_bluetooth_probe,
+	.remove = bcm4334_bluetooth_remove,
+	.driver = {
+		   .name = "bcm4334_bluetooth",
+		   .owner = THIS_MODULE,
+		   },
+};
+
+static int __init bcm4334_bluetooth_init(void)
+{
+	return platform_driver_register(&bcm4334_bluetooth_platform_driver);
+}
+
+static void __exit bcm4334_bluetooth_exit(void)
+{
+	platform_driver_unregister(&bcm4334_bluetooth_platform_driver);
+}
+
+
+module_init(bcm4334_bluetooth_init);
+module_exit(bcm4334_bluetooth_exit);
+
+MODULE_ALIAS("platform:bcm4334");
+MODULE_DESCRIPTION("bcm4334_bluetooth");
+MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-exynos/board-bluetooth-csr8811.c b/arch/arm/mach-exynos/board-bluetooth-csr8811.c
new file mode 100644
index 0000000..c3f46bb
--- /dev/null
+++ b/arch/arm/mach-exynos/board-bluetooth-csr8811.c
@@ -0,0 +1,334 @@
+/*
+ * Bluetooth CSR GPIO
+ *
+ *  Copyright (C) 2011 Samsung Electronics Co., Ltd.
+ *  Copyright (C) 2011 Google, Inc.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/hrtimer.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/rfkill.h>
+#include <linux/serial_core.h>
+#include <linux/wakelock.h>
+
+#include <asm/mach-types.h>
+
+#include <mach/gpio.h>
+#include <plat/gpio-cfg.h>
+
+#define BT_UART_CFG
+#define BT_LPM_ENABLE
+
+#define IRQ_BT_HOST_WAKE	IRQ_EINT(22)
+
+static struct rfkill *bt_rfkill;
+
+struct csr_bt_lpm {
+	int wake;
+	int host_wake;
+
+	struct hrtimer enter_lpm_timer;
+	ktime_t enter_lpm_delay;
+
+	struct uart_port *uport;
+
+	struct wake_lock wake_lock;
+	char wake_lock_name[100];
+} bt_lpm;
+
+#ifdef BT_UART_CFG
+int bt_is_running;
+EXPORT_SYMBOL(bt_is_running);
+
+extern int s3c_gpio_slp_cfgpin(unsigned int pin, unsigned int config);
+extern int s3c_gpio_slp_setpull_updown(unsigned int pin, unsigned int config);
+
+static unsigned int bt_uart_on_table[][4] = {
+	{EXYNOS4_GPA0(0), 2, 2, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(1), 2, 2, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(2), 2, 2, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(3), 2, 2, S3C_GPIO_PULL_NONE},
+};
+
+void bt_config_gpio_table(int array_size, unsigned int (*gpio_table)[4])
+{
+	u32 i, gpio;
+
+	for (i = 0; i < array_size; i++) {
+		gpio = gpio_table[i][0];
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(gpio_table[i][1]));
+		s3c_gpio_setpull(gpio, gpio_table[i][3]);
+		if (gpio_table[i][2] != 2)
+			gpio_set_value(gpio, gpio_table[i][2]);
+	}
+}
+
+void bt_uart_rts_ctrl(int flag)
+{
+	if (flag) {
+		/* BT RTS Set to HIGH */
+		s3c_gpio_cfgpin(EXYNOS4_GPA0(3), S3C_GPIO_OUTPUT);
+		s3c_gpio_setpull(EXYNOS4_GPA0(3), S3C_GPIO_PULL_NONE);
+		gpio_set_value(EXYNOS4_GPA0(3), 1);
+		s3c_gpio_slp_cfgpin(EXYNOS4_GPA0(3), S3C_GPIO_SLP_OUT0);
+		s3c_gpio_slp_setpull_updown(EXYNOS4_GPA0(3), S3C_GPIO_PULL_NONE);
+	} else {
+		/* BT RTS Set to LOW */
+		s3c_gpio_cfgpin(EXYNOS4_GPA0(3), S3C_GPIO_OUTPUT);
+		gpio_set_value(EXYNOS4_GPA0(3), 0);
+		s3c_gpio_cfgpin(EXYNOS4_GPA0(3), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(EXYNOS4_GPA0(3), S3C_GPIO_PULL_NONE);
+	}
+}
+EXPORT_SYMBOL(bt_uart_rts_ctrl);
+#endif
+
+static int csr8811_bt_rfkill_set_power(void *data, bool blocked)
+{
+	/* rfkill_ops callback. Turn transmitter on when blocked is false */
+	if (!blocked) {
+		pr_info("[BT] Bluetooth Power On.\n");
+#ifdef BT_UART_CFG
+		bt_config_gpio_table(ARRAY_SIZE(bt_uart_on_table),
+					bt_uart_on_table);
+#endif
+		msleep(20);
+		gpio_set_value(GPIO_BT_nRST, 1);
+		msleep(50);
+	} else {
+		pr_info("[BT] Bluetooth Power Off.\n");
+		bt_is_running = 0;
+		gpio_set_value(GPIO_BT_nRST, 0);
+	}
+	return 0;
+}
+
+static const struct rfkill_ops csr8811_bt_rfkill_ops = {
+	.set_block = csr8811_bt_rfkill_set_power,
+};
+
+#ifdef BT_LPM_ENABLE
+static void set_wake_locked(int wake)
+{
+	bt_lpm.wake = wake;
+
+	if (!wake)
+		wake_unlock(&bt_lpm.wake_lock);
+}
+
+static enum hrtimer_restart enter_lpm(struct hrtimer *timer)
+{
+	unsigned long flags;
+	spin_lock_irqsave(&bt_lpm.uport->lock, flags);
+	bt_is_running = 0;
+	set_wake_locked(0);
+	spin_unlock_irqrestore(&bt_lpm.uport->lock, flags);
+
+	return HRTIMER_NORESTART;
+}
+
+void csr_bt_lpm_exit_lpm_locked(struct uart_port *uport)
+{
+	bt_lpm.uport = uport;
+
+	hrtimer_try_to_cancel(&bt_lpm.enter_lpm_timer);
+	bt_is_running = 1;
+	set_wake_locked(1);
+
+	hrtimer_start(&bt_lpm.enter_lpm_timer, bt_lpm.enter_lpm_delay,
+		HRTIMER_MODE_REL);
+}
+EXPORT_SYMBOL(csr_bt_lpm_exit_lpm_locked);
+
+static void update_host_wake_locked(int host_wake)
+{
+	if (host_wake == bt_lpm.host_wake)
+		return;
+
+	bt_lpm.host_wake = host_wake;
+
+	bt_is_running = 1;
+	if (host_wake) {
+		wake_lock(&bt_lpm.wake_lock);
+	} else  {
+		/* Take a timed wakelock, so that upper layers can take it.
+		 * The chipset deasserts the hostwake lock, when there is no
+		 * more data to send.
+		 */
+		wake_lock_timeout(&bt_lpm.wake_lock, 5*HZ);
+	}
+}
+
+static irqreturn_t host_wake_isr(int irq, void *dev)
+{
+	int host_wake;
+	unsigned long flags;
+
+	host_wake = gpio_get_value(GPIO_BT_HOST_WAKE);
+	irq_set_irq_type(irq, host_wake ? IRQF_TRIGGER_LOW : IRQF_TRIGGER_HIGH);
+
+	if (!bt_lpm.uport) {
+		bt_lpm.host_wake = host_wake;
+		return IRQ_HANDLED;
+	}
+
+	spin_lock_irqsave(&bt_lpm.uport->lock, flags);
+	update_host_wake_locked(host_wake);
+	spin_unlock_irqrestore(&bt_lpm.uport->lock, flags);
+
+	return IRQ_HANDLED;
+}
+
+static int csr_bt_lpm_init(struct platform_device *pdev)
+{
+	int irq;
+	int ret;
+
+	hrtimer_init(&bt_lpm.enter_lpm_timer, CLOCK_MONOTONIC,
+			HRTIMER_MODE_REL);
+	bt_lpm.enter_lpm_delay = ktime_set(1, 0);  /* 1 sec */
+	bt_lpm.enter_lpm_timer.function = enter_lpm;
+
+	bt_lpm.host_wake = 0;
+	bt_is_running = 0;
+
+	irq = IRQ_BT_HOST_WAKE;
+	ret = request_irq(irq, host_wake_isr, IRQF_TRIGGER_HIGH,
+		"bt host_wake", NULL);
+	if (ret) {
+		pr_err("[BT] Request_host wake irq failed.\n");
+		return ret;
+	}
+
+	ret = irq_set_irq_wake(irq, 1);
+	if (ret) {
+		pr_err("[BT] Set_irq_wake failed.\n");
+		return ret;
+	}
+
+	snprintf(bt_lpm.wake_lock_name, sizeof(bt_lpm.wake_lock_name),
+			"BTLowPower");
+	wake_lock_init(&bt_lpm.wake_lock, WAKE_LOCK_SUSPEND,
+			 bt_lpm.wake_lock_name);
+	return 0;
+}
+#endif
+
+static int csr8811_bluetooth_probe(struct platform_device *pdev)
+{
+	int rc = 0;
+	int ret;
+
+	printk("%s\n", __func__);
+
+	rc = gpio_request(GPIO_BT_nRST, "csr8811_btnrst_gpio");
+	if (unlikely(rc)) {
+		pr_err("[BT] GPIO_BT_nRST request failed.\n");
+		return rc;
+	}
+	rc = gpio_request(GPIO_BT_HOST_WAKE, "csr8811_bthostwake_gpio");
+	if (unlikely(rc)) {
+		pr_err("[BT] GPIO_BT_HOST_WAKE request failed.\n");
+		gpio_free(GPIO_BT_nRST);
+		return rc;
+	}
+	gpio_direction_input(GPIO_BT_HOST_WAKE);
+	gpio_direction_output(GPIO_BT_nRST, 0);
+
+	bt_rfkill = rfkill_alloc("csr8811 Bluetooth", &pdev->dev,
+				RFKILL_TYPE_BLUETOOTH, &csr8811_bt_rfkill_ops,
+				NULL);
+
+	if (unlikely(!bt_rfkill)) {
+		pr_err("[BT] bt_rfkill alloc failed.\n");
+		gpio_free(GPIO_BT_HOST_WAKE);
+		gpio_free(GPIO_BT_nRST);
+		return -ENOMEM;
+	}
+
+	rfkill_init_sw_state(bt_rfkill, 0);
+
+	rc = rfkill_register(bt_rfkill);
+
+	if (unlikely(rc)) {
+		pr_err("[BT] bt_rfkill register failed.\n");
+		rfkill_destroy(bt_rfkill);
+		gpio_free(GPIO_BT_HOST_WAKE);
+		gpio_free(GPIO_BT_nRST);
+		return -1;
+	}
+
+	rfkill_set_sw_state(bt_rfkill, true);
+
+#ifdef BT_LPM_ENABLE
+	ret = csr_bt_lpm_init(pdev);
+	if (ret) {
+		rfkill_unregister(bt_rfkill);
+		rfkill_destroy(bt_rfkill);
+
+		gpio_free(GPIO_BT_HOST_WAKE);
+		gpio_free(GPIO_BT_nRST);
+	}
+#endif
+	return rc;
+}
+
+static int csr8811_bluetooth_remove(struct platform_device *pdev)
+{
+	rfkill_unregister(bt_rfkill);
+	rfkill_destroy(bt_rfkill);
+
+	gpio_free(GPIO_BT_nRST);
+	gpio_free(GPIO_BT_HOST_WAKE);
+
+	wake_lock_destroy(&bt_lpm.wake_lock);
+	return 0;
+}
+
+static struct platform_driver csr8811_bluetooth_platform_driver = {
+	.probe = csr8811_bluetooth_probe,
+	.remove = csr8811_bluetooth_remove,
+	.driver = {
+		   .name = "csr8811_bluetooth",
+		   .owner = THIS_MODULE,
+		   },
+};
+
+static int __init csr8811_bluetooth_init(void)
+{
+	return platform_driver_register(&csr8811_bluetooth_platform_driver);
+}
+
+static void __exit csr8811_bluetooth_exit(void)
+{
+	platform_driver_unregister(&csr8811_bluetooth_platform_driver);
+}
+
+
+module_init(csr8811_bluetooth_init);
+module_exit(csr8811_bluetooth_exit);
+
+MODULE_ALIAS("platform:csr8811");
+MODULE_DESCRIPTION("csr8811_bluetooth");
+MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-exynos/board-c1-modems.c b/arch/arm/mach-exynos/board-c1-modems.c
new file mode 100644
index 0000000..9c33fda
--- /dev/null
+++ b/arch/arm/mach-exynos/board-c1-modems.c
@@ -0,0 +1,1302 @@
+/* linux/arch/arm/mach-xxxx/board-c1-modems.c
+ * Copyright (C) 2010 Samsung Electronics. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/regulator/consumer.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+
+/* inlcude platform specific file */
+#include <linux/platform_data/modem.h>
+#include <mach/sec_modem.h>
+#include <mach/gpio.h>
+#include <mach/gpio-exynos4.h>
+#include <plat/gpio-cfg.h>
+#include <mach/regs-mem.h>
+#include <plat/regs-srom.h>
+
+#ifdef CONFIG_USBHUB_USB3503
+#include <linux/i2c.h>
+#include <linux/i2c-gpio.h>
+#include <linux/platform_data/usb3503.h>
+#include <mach/cpufreq.h>
+#include <plat/usb-phy.h>
+#endif
+#include <plat/devs.h>
+#include <plat/ehci.h>
+
+#define SROM_CS0_BASE		0x04000000
+#define SROM_WIDTH		0x01000000
+#define SROM_NUM_ADDR_BITS	14
+
+/* For "bus width and wait control (BW)" register */
+enum sromc_attr {
+	SROMC_DATA_16   = 0x1,	/* 16-bit data bus	*/
+	SROMC_BYTE_ADDR = 0x2,	/* Byte base address	*/
+	SROMC_WAIT_EN   = 0x4,	/* Wait enabled		*/
+	SROMC_BYTE_EN   = 0x8,	/* Byte access enabled	*/
+	SROMC_MASK      = 0xF
+};
+
+/* DPRAM configuration */
+struct sromc_cfg {
+	enum sromc_attr attr;
+	unsigned size;
+	unsigned csn;		/* CSn #			*/
+	unsigned addr;		/* Start address (physical)	*/
+	unsigned end;		/* End address (physical)	*/
+};
+
+/* DPRAM access timing configuration */
+struct sromc_access_cfg {
+	u32 tacs;		/* Address set-up before CSn		*/
+	u32 tcos;		/* Chip selection set-up before OEn	*/
+	u32 tacc;		/* Access cycle				*/
+	u32 tcoh;		/* Chip selection hold on OEn		*/
+	u32 tcah;		/* Address holding time after CSn	*/
+	u32 tacp;		/* Page mode access cycle at Page mode	*/
+	u32 pmc;		/* Page Mode config			*/
+};
+
+/* For CMC221 IDPRAM (Internal DPRAM) */
+#define CMC_IDPRAM_SIZE		0x4000	/* 16 KB */
+
+/* FOR CMC221 SFR for IDPRAM */
+#define CMC_INT2CP_REG		0x10	/* Interrupt to CP            */
+#define CMC_INT2AP_REG		0x50
+#define CMC_CLR_INT_REG		0x28	/* Clear Interrupt to AP      */
+#define CMC_RESET_REG		0x3C
+#define CMC_PUT_REG		0x40	/* AP->CP reg for hostbooting */
+#define CMC_GET_REG		0x50	/* CP->AP reg for hostbooting */
+
+#define INT_MASK_REQ_ACK_F	0x0020
+#define INT_MASK_REQ_ACK_R	0x0010
+#define INT_MASK_RES_ACK_F	0x0008
+#define INT_MASK_RES_ACK_R	0x0004
+#define INT_MASK_SEND_F		0x0002
+#define INT_MASK_SEND_R		0x0001
+
+/* Function prototypes */
+static void config_dpram_port_gpio(void);
+static void init_sromc(void);
+static void setup_sromc(unsigned csn, struct sromc_cfg *cfg,
+		struct sromc_access_cfg *acc_cfg);
+static void setup_dpram_speed(unsigned csn, struct sromc_access_cfg *acc_cfg);
+static int __init init_modem(void);
+
+#ifdef CONFIG_USBHUB_USB3503
+static int host_port_enable(int port, int enable);
+#else
+static int host_port_enable(int port, int enable)
+{
+	return s5p_ehci_port_control(&s5p_device_ehci, port, enable);
+}
+#endif
+
+static struct sromc_cfg cmc_idpram_cfg = {
+	.attr = SROMC_DATA_16,
+	.size = CMC_IDPRAM_SIZE,
+};
+
+static struct sromc_access_cfg cmc_idpram_access_cfg[] = {
+	[DPRAM_SPEED_LOW] = {
+		/* for 33 MHz clock, 64 cycles */
+		.tacs = 0x08 << 28,
+		.tcos = 0x08 << 24,
+		.tacc = 0x1F << 16,
+		.tcoh = 0x08 << 12,
+		.tcah = 0x08 << 8,
+		.tacp = 0x00 << 4,
+		.pmc  = 0x00 << 0,
+	},
+	[DPRAM_SPEED_MID] = {
+		/* for 66 MHz clock, 32 cycles */
+		.tacs = 0x01 << 28,
+		.tcos = 0x01 << 24,
+		.tacc = 0x1B << 16,
+		.tcoh = 0x01 << 12,
+		.tcah = 0x01 << 8,
+		.tacp = 0x00 << 4,
+		.pmc  = 0x00 << 0,
+	},
+	[DPRAM_SPEED_HIGH] = {
+		/* for 133 MHz clock, 16 cycles */
+		.tacs = 0x01 << 28,
+		.tcos = 0x01 << 24,
+		.tacc = 0x0B << 16,
+		.tcoh = 0x01 << 12,
+		.tcah = 0x01 << 8,
+		.tacp = 0x00 << 4,
+		.pmc  = 0x00 << 0,
+	},
+};
+
+/*
+	magic_code +
+	access_enable +
+	fmt_tx_head + fmt_tx_tail + fmt_tx_buff +
+	raw_tx_head + raw_tx_tail + raw_tx_buff +
+	fmt_rx_head + fmt_rx_tail + fmt_rx_buff +
+	raw_rx_head + raw_rx_tail + raw_rx_buff +
+	mbx_cp2ap +
+	mbx_ap2cp
+ =	2 +
+	2 +
+	2 + 2 + 1336 +
+	2 + 2 + 4564 +
+	2 + 2 + 1336 +
+	2 + 2 + 9124 +
+	2 +
+	2
+ =	16384
+*/
+
+#define DP_FMT_TX_BUFF_SZ	1336
+#define DP_RAW_TX_BUFF_SZ	4564
+#define DP_FMT_RX_BUFF_SZ	1336
+#define DP_RAW_RX_BUFF_SZ	9124
+
+#define MAX_CMC_IDPRAM_IPC_DEV	(IPC_RAW + 1)	/* FMT, RAW */
+
+struct dpram_ipc_cfg {
+	u16 magic;
+	u16 access;
+
+	u16 fmt_tx_head;
+	u16 fmt_tx_tail;
+	u8  fmt_tx_buff[DP_FMT_TX_BUFF_SZ];
+
+	u16 raw_tx_head;
+	u16 raw_tx_tail;
+	u8  raw_tx_buff[DP_RAW_TX_BUFF_SZ];
+
+	u16 fmt_rx_head;
+	u16 fmt_rx_tail;
+	u8  fmt_rx_buff[DP_FMT_RX_BUFF_SZ];
+
+	u16 raw_rx_head;
+	u16 raw_rx_tail;
+	u8  raw_rx_buff[DP_RAW_RX_BUFF_SZ];
+
+	u16 mbx_cp2ap;
+	u16 mbx_ap2cp;
+};
+
+struct cmc221_idpram_sfr {
+	u16 __iomem *int2cp;
+	u16 __iomem *int2ap;
+	u16 __iomem *clr_int2ap;
+	u16 __iomem *reset;
+	u16 __iomem *msg2cp;
+	u16 __iomem *msg2ap;
+};
+
+static struct dpram_ipc_map cmc_ipc_map;
+static u8 *cmc_sfr_base;
+static struct cmc221_idpram_sfr cmc_sfr;
+
+/* Function prototypes */
+static void cmc_idpram_reset(void);
+static void cmc_idpram_setup_speed(enum dpram_speed);
+static int  cmc_idpram_wakeup(void);
+static void cmc_idpram_sleep(void);
+static void cmc_idpram_clr_intr(void);
+static u16  cmc_idpram_recv_intr(void);
+static void cmc_idpram_send_intr(u16 irq_mask);
+static u16  cmc_idpram_recv_msg(void);
+static void cmc_idpram_send_msg(u16 msg);
+
+static u16  cmc_idpram_get_magic(void);
+static void cmc_idpram_set_magic(u16 value);
+static u16  cmc_idpram_get_access(void);
+static void cmc_idpram_set_access(u16 value);
+
+static u32  cmc_idpram_get_tx_head(int dev_id);
+static u32  cmc_idpram_get_tx_tail(int dev_id);
+static void cmc_idpram_set_tx_head(int dev_id, u32 head);
+static void cmc_idpram_set_tx_tail(int dev_id, u32 tail);
+static u8 __iomem *cmc_idpram_get_tx_buff(int dev_id);
+static u32  cmc_idpram_get_tx_buff_size(int dev_id);
+
+static u32  cmc_idpram_get_rx_head(int dev_id);
+static u32  cmc_idpram_get_rx_tail(int dev_id);
+static void cmc_idpram_set_rx_head(int dev_id, u32 head);
+static void cmc_idpram_set_rx_tail(int dev_id, u32 tail);
+static u8 __iomem *cmc_idpram_get_rx_buff(int dev_id);
+static u32  cmc_idpram_get_rx_buff_size(int dev_id);
+
+static u16  cmc_idpram_get_mask_req_ack(int dev_id);
+static u16  cmc_idpram_get_mask_res_ack(int dev_id);
+static u16  cmc_idpram_get_mask_send(int dev_id);
+
+static struct modemlink_dpram_control cmc_idpram_ctrl = {
+	.reset = cmc_idpram_reset,
+
+	.setup_speed = cmc_idpram_setup_speed,
+
+	.wakeup = cmc_idpram_wakeup,
+	.sleep  = cmc_idpram_sleep,
+
+	.clear_intr = cmc_idpram_clr_intr,
+	.recv_intr  = cmc_idpram_recv_intr,
+	.send_intr  = cmc_idpram_send_intr,
+	.recv_msg   = cmc_idpram_recv_msg,
+	.send_msg   = cmc_idpram_send_msg,
+
+	.get_magic  = cmc_idpram_get_magic,
+	.set_magic  = cmc_idpram_set_magic,
+	.get_access = cmc_idpram_get_access,
+	.set_access = cmc_idpram_set_access,
+
+	.get_tx_head = cmc_idpram_get_tx_head,
+	.get_tx_tail = cmc_idpram_get_tx_tail,
+	.set_tx_head = cmc_idpram_set_tx_head,
+	.set_tx_tail = cmc_idpram_set_tx_tail,
+	.get_tx_buff = cmc_idpram_get_tx_buff,
+	.get_tx_buff_size = cmc_idpram_get_tx_buff_size,
+
+	.get_rx_head = cmc_idpram_get_rx_head,
+	.get_rx_tail = cmc_idpram_get_rx_tail,
+	.set_rx_head = cmc_idpram_set_rx_head,
+	.set_rx_tail = cmc_idpram_set_rx_tail,
+	.get_rx_buff = cmc_idpram_get_rx_buff,
+	.get_rx_buff_size = cmc_idpram_get_rx_buff_size,
+
+	.get_mask_req_ack = cmc_idpram_get_mask_req_ack,
+	.get_mask_res_ack = cmc_idpram_get_mask_res_ack,
+	.get_mask_send    = cmc_idpram_get_mask_send,
+
+	.dp_base = NULL,
+	.dp_size = 0,
+	.dp_type = CP_IDPRAM,
+	.aligned = 1,
+
+	.dpram_irq = CMC_IDPRAM_INT_IRQ_00,
+	.dpram_irq_flags = (IRQF_NO_SUSPEND | IRQF_TRIGGER_RISING),
+	.dpram_irq_name = "CMC221_IDPRAM_IRQ",
+	.dpram_wlock_name = "CMC221_IDPRAM_WLOCK",
+
+	.max_ipc_dev = MAX_CMC_IDPRAM_IPC_DEV,
+};
+
+/*
+** UMTS target platform data
+*/
+static struct modem_io_t umts_io_devices[] = {
+	[0] = {
+		.name = "umts_boot0",
+		.id = 0,
+		.format = IPC_BOOT,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[1] = {
+		.name = "umts_ipc0",
+		.id = 235,
+		.format = IPC_FMT,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[2] = {
+		.name = "umts_rfs0",
+		.id = 245,
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[3] = {
+		.name = "umts_multipdp",
+		.id = 0,
+		.format = IPC_MULTI_RAW,
+		.io_type = IODEV_DUMMY,
+		.links = LINKTYPE(LINKDEV_DPRAM) | LINKTYPE(LINKDEV_USB),
+		.tx_link = LINKDEV_DPRAM,
+	},
+	[4] = {
+		.name = "rmnet0",
+		.id = 10,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_DPRAM) | LINKTYPE(LINKDEV_USB),
+		.tx_link = LINKDEV_DPRAM,
+	},
+	[5] = {
+		.name = "rmnet1",
+		.id = 11,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_DPRAM) | LINKTYPE(LINKDEV_USB),
+		.tx_link = LINKDEV_DPRAM,
+	},
+	[6] = {
+		.name = "rmnet2",
+		.id = 12,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_DPRAM) | LINKTYPE(LINKDEV_USB),
+		.tx_link = LINKDEV_DPRAM,
+	},
+	[7] = {
+		.name = "rmnet3",
+		.id = 13,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_DPRAM) | LINKTYPE(LINKDEV_USB),
+		.tx_link = LINKDEV_DPRAM,
+	},
+	[8] = {
+		.name = "umts_csd",	/* CS Video Telephony */
+		.id = 1,
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[9] = {
+		.name = "umts_router",	/* AT Iface & Dial-up */
+		.id = 25,
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[10] = {
+		.name = "umts_dm0",	/* DM Port */
+		.id = 28,
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[11] = {
+		.name = "umts_loopback_ap2cp",
+		.id = 30,
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[12] = {
+		.name = "umts_loopback_cp2ap",
+		.id = 31,
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[13] = {
+		.name = "umts_ramdump0",
+		.id = 0,
+		.format = IPC_RAMDUMP,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[14] = {
+		.name = "lte_ipc0",
+		.id = 235,
+		.format = IPC_FMT,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_USB),
+	},
+};
+
+static int exynos_cpu_frequency_lock(void);
+static int exynos_cpu_frequency_unlock(void);
+
+static struct modemlink_pm_data umts_link_pm_data = {
+	.name = "umts_link_pm",
+
+	.gpio_link_enable    = 0,
+	.gpio_link_active    = GPIO_ACTIVE_STATE,
+	.gpio_link_hostwake  = GPIO_IPC_HOST_WAKEUP,
+	.gpio_link_slavewake = GPIO_IPC_SLAVE_WAKEUP,
+
+	.port_enable = host_port_enable,
+/*
+	.link_reconnect = umts_link_reconnect,
+*/
+	.freqlock = ATOMIC_INIT(0),
+	.cpufreq_lock = exynos_cpu_frequency_lock,
+	.cpufreq_unlock = exynos_cpu_frequency_unlock,
+
+	.autosuspend_delay_ms = 2000,
+
+	.has_usbhub = true,
+};
+
+static struct modem_data umts_modem_data = {
+	.name = "cmc221",
+
+	.gpio_cp_on = CP_CMC221_PMIC_PWRON,
+	.gpio_cp_reset = CP_CMC221_CPU_RST,
+	.gpio_phone_active = GPIO_LTE_ACTIVE,
+
+	.gpio_dpram_int = GPIO_CMC_IDPRAM_INT_00,
+	.gpio_dpram_status = GPIO_CMC_IDPRAM_STATUS,
+	.gpio_dpram_wakeup = GPIO_CMC_IDPRAM_WAKEUP,
+
+	.gpio_slave_wakeup = GPIO_IPC_SLAVE_WAKEUP,
+	.gpio_host_active = GPIO_ACTIVE_STATE,
+	.gpio_host_wakeup = GPIO_IPC_HOST_WAKEUP,
+	.gpio_dynamic_switching = GPIO_AP2CMC_INT2,
+
+	.modem_net = UMTS_NETWORK,
+	.modem_type = SEC_CMC221,
+	.link_types = LINKTYPE(LINKDEV_DPRAM) | LINKTYPE(LINKDEV_USB),
+	.link_name = "cmc221_idpram",
+	.dpram_ctl = &cmc_idpram_ctrl,
+
+	.num_iodevs = ARRAY_SIZE(umts_io_devices),
+	.iodevs = umts_io_devices,
+
+	.link_pm_data = &umts_link_pm_data,
+
+	.ipc_version = SIPC_VER_50,
+	.use_mif_log = true,
+};
+
+static struct resource umts_modem_res[] = {
+	[0] = {
+		.name  = "cp_active_irq",
+		.start = LTE_ACTIVE_IRQ,
+		.end   = LTE_ACTIVE_IRQ,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device umts_modem = {
+	.name = "mif_sipc5",
+	.id = 1,
+	.num_resources = ARRAY_SIZE(umts_modem_res),
+	.resource = umts_modem_res,
+	.dev = {
+		.platform_data = &umts_modem_data,
+	},
+};
+
+#define HUB_STATE_OFF 0
+void set_hsic_lpa_states(int states)
+{
+	int val = gpio_get_value(umts_modem_data.gpio_cp_reset);
+
+	mif_trace("\n");
+
+	if (val && states == STATE_HSIC_LPA_ENTER) {
+		mif_info("usb3503: hub off - lpa\n");
+		host_port_enable(2, 0);
+		*(umts_link_pm_data.p_hub_status) = HUB_STATE_OFF;
+	}
+}
+
+int get_cp_active_state(void)
+{
+	return gpio_get_value(umts_modem_data.gpio_phone_active);
+}
+
+static void cmc_idpram_reset(void)
+{
+	iowrite16(1, cmc_sfr.reset);
+}
+
+static void cmc_idpram_setup_speed(enum dpram_speed speed)
+{
+	setup_dpram_speed(cmc_idpram_cfg.csn, &cmc_idpram_access_cfg[speed]);
+}
+
+static int cmc_idpram_wakeup(void)
+{
+	int cnt = 0;
+
+	gpio_set_value(umts_modem_data.gpio_dpram_wakeup, 1);
+
+	while (!gpio_get_value(umts_modem_data.gpio_dpram_status)) {
+		if (cnt++ > 10) {
+			mif_err("ERR: gpio_dpram_status == 0\n");
+			return -EAGAIN;
+		}
+
+		if (in_interrupt())
+			mdelay(1);
+		else
+			msleep_interruptible(1);
+	}
+
+	return 0;
+}
+
+static void cmc_idpram_sleep(void)
+{
+	gpio_set_value(umts_modem_data.gpio_dpram_wakeup, 0);
+}
+
+static void cmc_idpram_clr_intr(void)
+{
+	iowrite16(0xFFFF, cmc_sfr.clr_int2ap);
+	iowrite16(0, cmc_sfr.int2ap);
+}
+
+static u16 cmc_idpram_recv_intr(void)
+{
+	return ioread16(cmc_sfr.int2ap);
+}
+
+static void cmc_idpram_send_intr(u16 irq_mask)
+{
+	iowrite16(irq_mask, cmc_sfr.int2cp);
+}
+
+static u16 cmc_idpram_recv_msg(void)
+{
+	return ioread16(cmc_sfr.msg2ap);
+}
+
+static void cmc_idpram_send_msg(u16 msg)
+{
+	iowrite16(msg, cmc_sfr.msg2cp);
+}
+
+static u16 cmc_idpram_get_magic(void)
+{
+	return ioread16(cmc_ipc_map.magic);
+}
+
+static void cmc_idpram_set_magic(u16 value)
+{
+	iowrite16(value, cmc_ipc_map.magic);
+}
+
+static u16 cmc_idpram_get_access(void)
+{
+	return ioread16(cmc_ipc_map.access);
+}
+
+static void cmc_idpram_set_access(u16 value)
+{
+	iowrite16(value, cmc_ipc_map.access);
+}
+
+static u32 cmc_idpram_get_tx_head(int dev_id)
+{
+	return ioread16(cmc_ipc_map.dev[dev_id].txq.head);
+}
+
+static u32 cmc_idpram_get_tx_tail(int dev_id)
+{
+	return ioread16(cmc_ipc_map.dev[dev_id].txq.tail);
+}
+
+static void cmc_idpram_set_tx_head(int dev_id, u32 head)
+{
+	int cnt = 100;
+	u32 val = 0;
+
+	iowrite16((u16)head, cmc_ipc_map.dev[dev_id].txq.head);
+
+	do {
+		/* Check head value written */
+		val = ioread16(cmc_ipc_map.dev[dev_id].txq.head);
+		if (val == head)
+			break;
+
+		mif_err("ERR: txq.head(%d) != head(%d)\n", val, head);
+
+		/* Write head value again */
+		iowrite16((u16)head, cmc_ipc_map.dev[dev_id].txq.head);
+	} while (cnt--);
+}
+
+static void cmc_idpram_set_tx_tail(int dev_id, u32 tail)
+{
+	int cnt = 100;
+	u32 val = 0;
+
+	iowrite16((u16)tail, cmc_ipc_map.dev[dev_id].txq.tail);
+
+	do {
+		/* Check tail value written */
+		val = ioread16(cmc_ipc_map.dev[dev_id].txq.tail);
+		if (val == tail)
+			break;
+
+		mif_err("ERR: txq.tail(%d) != tail(%d)\n", val, tail);
+
+		/* Write tail value again */
+		iowrite16((u16)tail, cmc_ipc_map.dev[dev_id].txq.tail);
+	} while (cnt--);
+}
+
+static u8 __iomem *cmc_idpram_get_tx_buff(int dev_id)
+{
+	return cmc_ipc_map.dev[dev_id].txq.buff;
+}
+
+static u32 cmc_idpram_get_tx_buff_size(int dev_id)
+{
+	return cmc_ipc_map.dev[dev_id].txq.size;
+}
+
+static u32 cmc_idpram_get_rx_head(int dev_id)
+{
+	return ioread16(cmc_ipc_map.dev[dev_id].rxq.head);
+}
+
+static u32 cmc_idpram_get_rx_tail(int dev_id)
+{
+	return ioread16(cmc_ipc_map.dev[dev_id].rxq.tail);
+}
+
+static void cmc_idpram_set_rx_head(int dev_id, u32 head)
+{
+	int cnt = 100;
+	u32 val = 0;
+
+	iowrite16((u16)head, cmc_ipc_map.dev[dev_id].rxq.head);
+
+	do {
+		/* Check head value written */
+		val = ioread16(cmc_ipc_map.dev[dev_id].rxq.head);
+		if (val == head)
+			break;
+
+		mif_err("ERR: rxq.head(%d) != head(%d)\n", val, head);
+
+		/* Write head value again */
+		iowrite16((u16)head, cmc_ipc_map.dev[dev_id].rxq.head);
+	} while (cnt--);
+}
+
+static void cmc_idpram_set_rx_tail(int dev_id, u32 tail)
+{
+	int cnt = 100;
+	u32 val = 0;
+
+	iowrite16((u16)tail, cmc_ipc_map.dev[dev_id].rxq.tail);
+
+	do {
+		/* Check tail value written */
+		val = ioread16(cmc_ipc_map.dev[dev_id].rxq.tail);
+		if (val == tail)
+			break;
+
+		mif_err("ERR: rxq.tail(%d) != tail(%d)\n", val, tail);
+
+		/* Write tail value again */
+		iowrite16((u16)tail, cmc_ipc_map.dev[dev_id].rxq.tail);
+	} while (cnt--);
+}
+
+static u8 __iomem *cmc_idpram_get_rx_buff(int dev_id)
+{
+	return cmc_ipc_map.dev[dev_id].rxq.buff;
+}
+
+static u32 cmc_idpram_get_rx_buff_size(int dev_id)
+{
+	return cmc_ipc_map.dev[dev_id].rxq.size;
+}
+
+static u16 cmc_idpram_get_mask_req_ack(int dev_id)
+{
+	return cmc_ipc_map.dev[dev_id].mask_req_ack;
+}
+
+static u16 cmc_idpram_get_mask_res_ack(int dev_id)
+{
+	return cmc_ipc_map.dev[dev_id].mask_res_ack;
+}
+
+static u16 cmc_idpram_get_mask_send(int dev_id)
+{
+	return cmc_ipc_map.dev[dev_id].mask_send;
+}
+
+/* Set dynamic environment for a modem */
+static void setup_umts_modem_env(void)
+{
+	/* Config DPRAM control structure */
+	cmc_idpram_cfg.csn  = 0;
+	cmc_idpram_cfg.addr = SROM_CS0_BASE + (SROM_WIDTH * cmc_idpram_cfg.csn);
+	cmc_idpram_cfg.end  = cmc_idpram_cfg.addr + cmc_idpram_cfg.size - 1;
+
+	umts_modem_data.gpio_dpram_int = GPIO_CMC_IDPRAM_INT_00;
+}
+
+static void config_umts_modem_gpio(void)
+{
+	int err;
+	unsigned gpio_cp_on = umts_modem_data.gpio_cp_on;
+	unsigned gpio_cp_rst = umts_modem_data.gpio_cp_reset;
+	unsigned gpio_pda_active = umts_modem_data.gpio_pda_active;
+	unsigned gpio_phone_active = umts_modem_data.gpio_phone_active;
+	unsigned gpio_active_state = umts_modem_data.gpio_host_active;
+	unsigned gpio_host_wakeup = umts_modem_data.gpio_host_wakeup;
+	unsigned gpio_slave_wakeup = umts_modem_data.gpio_slave_wakeup;
+	unsigned gpio_dpram_int = umts_modem_data.gpio_dpram_int;
+	unsigned gpio_dpram_status = umts_modem_data.gpio_dpram_status;
+	unsigned gpio_dpram_wakeup = umts_modem_data.gpio_dpram_wakeup;
+	unsigned gpio_dynamic_switching =
+			umts_modem_data.gpio_dynamic_switching;
+
+	if (gpio_cp_on) {
+		err = gpio_request(gpio_cp_on, "CMC_ON");
+		if (err) {
+			mif_err("ERR: fail to request gpio %s\n", "CMC_ON");
+		} else {
+			gpio_direction_output(gpio_cp_on, 0);
+			s3c_gpio_setpull(gpio_cp_on, S3C_GPIO_PULL_NONE);
+		}
+	}
+
+	if (gpio_cp_rst) {
+		err = gpio_request(gpio_cp_rst, "CMC_RST");
+		if (err) {
+			mif_err("ERR: fail to request gpio %s\n", "CMC_RST");
+		} else {
+			gpio_direction_output(gpio_cp_rst, 0);
+			s3c_gpio_setpull(gpio_cp_rst, S3C_GPIO_PULL_NONE);
+		}
+	}
+
+	if (gpio_pda_active) {
+		err = gpio_request(gpio_pda_active, "PDA_ACTIVE");
+		if (err) {
+			mif_err("ERR: fail to request gpio %s\n", "PDA_ACTIVE");
+		} else {
+			gpio_direction_output(gpio_pda_active, 0);
+			s3c_gpio_setpull(gpio_pda_active, S3C_GPIO_PULL_NONE);
+		}
+	}
+
+	if (gpio_phone_active) {
+		err = gpio_request(gpio_phone_active, "CMC_ACTIVE");
+		if (err) {
+			mif_err("ERR: fail to request gpio %s\n", "CMC_ACTIVE");
+		} else {
+			/* Configure as a wake-up source */
+			gpio_direction_input(gpio_phone_active);
+			s3c_gpio_setpull(gpio_phone_active, S3C_GPIO_PULL_DOWN);
+			s3c_gpio_cfgpin(gpio_phone_active, S3C_GPIO_SFN(0xF));
+		}
+	}
+
+	if (gpio_active_state) {
+		err = gpio_request(gpio_active_state, "CMC_ACTIVE_STATE");
+		if (err) {
+			mif_err("ERR: fail to request gpio %s\n",
+				"CMC_ACTIVE_STATE");
+		} else {
+			gpio_direction_output(gpio_active_state, 0);
+			s3c_gpio_setpull(gpio_active_state, S3C_GPIO_PULL_NONE);
+		}
+	}
+
+	if (gpio_slave_wakeup) {
+		err = gpio_request(gpio_slave_wakeup, "CMC_SLAVE_WAKEUP");
+		if (err) {
+			mif_err("ERR: fail to request gpio %s\n",
+				"CMC_SLAVE_WAKEUP");
+		} else {
+			gpio_direction_output(gpio_slave_wakeup, 0);
+			s3c_gpio_setpull(gpio_slave_wakeup, S3C_GPIO_PULL_NONE);
+		}
+	}
+
+	if (gpio_host_wakeup) {
+		err = gpio_request(gpio_host_wakeup, "CMC_HOST_WAKEUP");
+		if (err) {
+			mif_err("ERR: fail to request gpio %s\n",
+				"CMC_HOST_WAKEUP");
+		} else {
+			/* Configure as a wake-up source */
+			gpio_direction_input(gpio_host_wakeup);
+			s3c_gpio_setpull(gpio_host_wakeup, S3C_GPIO_PULL_DOWN);
+			s3c_gpio_cfgpin(gpio_host_wakeup, S3C_GPIO_SFN(0xF));
+		}
+	}
+
+	if (gpio_dpram_int) {
+		err = gpio_request(gpio_dpram_int, "CMC_DPRAM_INT");
+		if (err) {
+			mif_err("ERR: fail to request gpio %s\n",
+				"CMC_DPRAM_INT");
+		} else {
+			/* Configure as a wake-up source */
+			gpio_direction_input(gpio_dpram_int);
+			s3c_gpio_setpull(gpio_dpram_int, S3C_GPIO_PULL_NONE);
+			s3c_gpio_cfgpin(gpio_dpram_int, S3C_GPIO_SFN(0xF));
+		}
+	}
+
+	if (gpio_dpram_status) {
+		err = gpio_request(gpio_dpram_status, "CMC_DPRAM_STATUS");
+		if (err) {
+			mif_err("ERR: fail to request gpio %s\n",
+				"CMC_DPRAM_STATUS");
+		} else {
+			gpio_direction_input(gpio_dpram_status);
+			s3c_gpio_setpull(gpio_dpram_status, S3C_GPIO_PULL_NONE);
+		}
+	}
+
+	if (gpio_dpram_wakeup) {
+		err = gpio_request(gpio_dpram_wakeup, "CMC_DPRAM_WAKEUP");
+		if (err) {
+			mif_err("ERR: fail to request gpio %s\n",
+				"CMC_DPRAM_WAKEUP");
+		} else {
+			gpio_direction_output(gpio_dpram_wakeup, 1);
+			s3c_gpio_setpull(gpio_dpram_wakeup, S3C_GPIO_PULL_NONE);
+		}
+	}
+
+	if (gpio_dynamic_switching) {
+		err = gpio_request(gpio_dynamic_switching, "DYNAMIC_SWITCHING");
+		if (err) {
+			mif_err("ERR: fail to request gpio %s\n",
+					"DYNAMIC_SWITCHING\n");
+		} else {
+			gpio_direction_input(gpio_dynamic_switching);
+			s3c_gpio_setpull(gpio_dynamic_switching,
+					S3C_GPIO_PULL_NONE);
+		}
+	}
+}
+
+static u8 *cmc_idpram_remap_mem_region(struct sromc_cfg *cfg)
+{
+	int dp_addr = cfg->addr;
+	int dp_size = cfg->size;
+	u8 __iomem *dp_base;
+	struct dpram_ipc_cfg *ipc_map;
+	struct dpram_ipc_device *dev;
+
+	/* Remap DPRAM memory region */
+	dp_base = (u8 __iomem *)ioremap_nocache(dp_addr, dp_size);
+	if (!dp_base) {
+		mif_err("ERR: ioremap_nocache for dp_base fail\n");
+		return NULL;
+	}
+	mif_err("DPRAM VA=0x%08X\n", (int)dp_base);
+
+	/* Remap DPRAM SFR region */
+	dp_addr += dp_size;
+	cmc_sfr_base = (u8 __iomem *)ioremap_nocache(dp_addr, dp_size);
+	if (cmc_sfr_base == NULL) {
+		iounmap(dp_base);
+		mif_err("ERR: ioremap_nocache for cmc_sfr_base fail\n");
+		return NULL;
+	}
+
+	cmc_sfr.int2cp = (u16 __iomem *)(cmc_sfr_base + CMC_INT2CP_REG);
+	cmc_sfr.int2ap = (u16 __iomem *)(cmc_sfr_base + CMC_INT2AP_REG);
+	cmc_sfr.clr_int2ap = (u16 __iomem *)(cmc_sfr_base + CMC_CLR_INT_REG);
+	cmc_sfr.reset = (u16 __iomem *)(cmc_sfr_base + CMC_RESET_REG);
+	cmc_sfr.msg2cp = (u16 __iomem *)(cmc_sfr_base + CMC_PUT_REG);
+	cmc_sfr.msg2ap = (u16 __iomem *)(cmc_sfr_base + CMC_GET_REG);
+
+	cmc_idpram_ctrl.dp_base = (u8 __iomem *)dp_base;
+	cmc_idpram_ctrl.dp_size = dp_size;
+
+	/* Map for IPC */
+	ipc_map = (struct dpram_ipc_cfg *)dp_base;
+
+	/* Magic code and access enable fields */
+	cmc_ipc_map.magic  = (u16 __iomem *)&ipc_map->magic;
+	cmc_ipc_map.access = (u16 __iomem *)&ipc_map->access;
+
+	/* FMT */
+	dev = &cmc_ipc_map.dev[IPC_FMT];
+
+	strcpy(dev->name, "FMT");
+	dev->id = IPC_FMT;
+
+	dev->txq.head = (u16 __iomem *)&ipc_map->fmt_tx_head;
+	dev->txq.tail = (u16 __iomem *)&ipc_map->fmt_tx_tail;
+	dev->txq.buff = (u8 __iomem *)&ipc_map->fmt_tx_buff[0];
+	dev->txq.size = DP_FMT_TX_BUFF_SZ;
+
+	dev->rxq.head = (u16 __iomem *)&ipc_map->fmt_rx_head;
+	dev->rxq.tail = (u16 __iomem *)&ipc_map->fmt_rx_tail;
+	dev->rxq.buff = (u8 __iomem *)&ipc_map->fmt_rx_buff[0];
+	dev->rxq.size = DP_FMT_RX_BUFF_SZ;
+
+	dev->mask_req_ack = INT_MASK_REQ_ACK_F;
+	dev->mask_res_ack = INT_MASK_RES_ACK_F;
+	dev->mask_send    = INT_MASK_SEND_F;
+
+	/* RAW */
+	dev = &cmc_ipc_map.dev[IPC_RAW];
+
+	strcpy(dev->name, "RAW");
+	dev->id = IPC_RAW;
+
+	dev->txq.head = (u16 __iomem *)&ipc_map->raw_tx_head;
+	dev->txq.tail = (u16 __iomem *)&ipc_map->raw_tx_tail;
+	dev->txq.buff = (u8 __iomem *)&ipc_map->raw_tx_buff[0];
+	dev->txq.size = DP_RAW_TX_BUFF_SZ;
+
+	dev->rxq.head = (u16 __iomem *)&ipc_map->raw_rx_head;
+	dev->rxq.tail = (u16 __iomem *)&ipc_map->raw_rx_tail;
+	dev->rxq.buff = (u8 __iomem *)&ipc_map->raw_rx_buff[0];
+	dev->rxq.size = DP_RAW_RX_BUFF_SZ;
+
+	dev->mask_req_ack = INT_MASK_REQ_ACK_R;
+	dev->mask_res_ack = INT_MASK_RES_ACK_R;
+	dev->mask_send    = INT_MASK_SEND_R;
+
+	return dp_base;
+}
+
+/**
+ *	DPRAM GPIO settings
+ *
+ *	SROM_NUM_ADDR_BITS value indicate the address line number or
+ *	the mux/demux dpram type. if you want to set mux mode, define the
+ *	SROM_NUM_ADDR_BITS to zero.
+ *
+ *	for CMC22x
+ *	CMC22x has 16KB + a SFR register address.
+ *	It used 14 bits (13bits for 16KB word address and 1 bit for SFR
+ *	register)
+ */
+static void config_dpram_port_gpio(void)
+{
+	int addr_bits = SROM_NUM_ADDR_BITS;
+
+	mif_info("address line = %d bits\n", addr_bits);
+
+	/*
+	** Config DPRAM address/data GPIO pins
+	*/
+
+	/* Set GPIO for address bus (13 ~ 14 bits) */
+	switch (addr_bits) {
+	case 0:
+		break;
+
+	case 13 ... 14:
+		s3c_gpio_cfgrange_nopull(GPIO_SROM_ADDR_BUS_LOW,
+			EXYNOS4_GPIO_Y3_NR, S3C_GPIO_SFN(2));
+		s3c_gpio_cfgrange_nopull(GPIO_SROM_ADDR_BUS_HIGH,
+			(addr_bits - EXYNOS4_GPIO_Y3_NR), S3C_GPIO_SFN(2));
+		break;
+
+	default:
+		mif_err("ERR: invalid addr_bits!!!\n");
+		return;
+	}
+
+	/* Set GPIO for data bus (16 bits) */
+	s3c_gpio_cfgrange_nopull(GPIO_SROM_DATA_BUS_LOW, 8, S3C_GPIO_SFN(2));
+	s3c_gpio_cfgrange_nopull(GPIO_SROM_DATA_BUS_HIGH, 8, S3C_GPIO_SFN(2));
+
+	/* Setup SROMC CSn pins */
+	s3c_gpio_cfgpin(GPIO_DPRAM_CSN0, S3C_GPIO_SFN(2));
+
+	/* Config OEn, WEn */
+	s3c_gpio_cfgpin(GPIO_DPRAM_REN, S3C_GPIO_SFN(2));
+	s3c_gpio_cfgpin(GPIO_DPRAM_WEN, S3C_GPIO_SFN(2));
+}
+
+static void init_sromc(void)
+{
+	struct clk *clk = NULL;
+
+	/* SROMC clk enable */
+	clk = clk_get(NULL, "sromc");
+	if (!clk) {
+		mif_err("ERR: SROMC clock gate fail\n");
+		return;
+	}
+	clk_enable(clk);
+}
+
+static void setup_sromc
+(
+	unsigned csn,
+	struct sromc_cfg *cfg,
+	struct sromc_access_cfg *acc_cfg
+)
+{
+	unsigned bw = 0;	/* Bus width and wait control	*/
+	unsigned bc = 0;	/* Vank control			*/
+	void __iomem *bank_sfr = S5P_SROM_BC0 + (4 * csn);
+
+	mif_err("SROMC settings for CS%d...\n", csn);
+
+	bw = __raw_readl(S5P_SROM_BW);
+	bc = __raw_readl(bank_sfr);
+	mif_err("Old SROMC settings = BW(0x%08X) BC%d(0x%08X)\n", bw, csn, bc);
+
+	/* Set the BW control field for the CSn */
+	bw &= ~(SROMC_MASK << (csn << 2));
+	bw |= (cfg->attr << (csn << 2));
+	writel(bw, S5P_SROM_BW);
+
+	/* Set SROMC memory access timing for the CSn */
+	bc = acc_cfg->tacs | acc_cfg->tcos | acc_cfg->tacc |
+	     acc_cfg->tcoh | acc_cfg->tcah | acc_cfg->tacp | acc_cfg->pmc;
+
+	writel(bc, bank_sfr);
+
+	/* Verify SROMC settings */
+	bw = __raw_readl(S5P_SROM_BW);
+	bc = __raw_readl(bank_sfr);
+	mif_err("New SROMC settings = BW(0x%08X) BC%d(0x%08X)\n", bw, csn, bc);
+}
+
+static void setup_dpram_speed(unsigned csn, struct sromc_access_cfg *acc_cfg)
+{
+	void __iomem *bank_sfr = S5P_SROM_BC0 + (4 * csn);
+	unsigned bc = 0;
+
+	bc = __raw_readl(bank_sfr);
+	mif_info("Old CS%d setting = 0x%08X\n", csn, bc);
+
+	/* SROMC memory access timing setting */
+	bc = acc_cfg->tacs | acc_cfg->tcos | acc_cfg->tacc |
+	     acc_cfg->tcoh | acc_cfg->tcah | acc_cfg->tacp | acc_cfg->pmc;
+	writel(bc, bank_sfr);
+
+	bc = __raw_readl(bank_sfr);
+	mif_info("New CS%d setting = 0x%08X\n", csn, bc);
+}
+
+static int __init init_modem(void)
+{
+	struct sromc_cfg *cfg = NULL;
+	struct sromc_access_cfg *acc_cfg = NULL;
+
+	mif_err("System Revision = %d\n", system_rev);
+
+	setup_umts_modem_env();
+
+	config_dpram_port_gpio();
+
+	config_umts_modem_gpio();
+
+	init_sromc();
+
+	cfg = &cmc_idpram_cfg;
+	acc_cfg = &cmc_idpram_access_cfg[DPRAM_SPEED_LOW];
+
+	setup_sromc(cfg->csn, cfg, acc_cfg);
+
+	if (!cmc_idpram_remap_mem_region(&cmc_idpram_cfg))
+		return -1;
+
+	platform_device_register(&umts_modem);
+
+	return 0;
+}
+late_initcall(init_modem);
+/*device_initcall(init_modem);*/
+
+#ifdef CONFIG_USBHUB_USB3503
+static int (*usbhub_set_mode)(struct usb3503_hubctl *, int);
+static struct usb3503_hubctl *usbhub_ctl;
+
+#ifdef CONFIG_EXYNOS4_CPUFREQ
+static int exynos_cpu_frequency_lock(void)
+{
+	unsigned int level, freq = 700;
+
+	if (atomic_read(&umts_link_pm_data.freqlock) == 0) {
+		if (exynos_cpufreq_get_level(freq * 1000, &level)) {
+			mif_err("ERR: exynos_cpufreq_get_level fail\n");
+			return -EINVAL;
+		}
+
+		if (exynos_cpufreq_lock(DVFS_LOCK_ID_USB_IF, level)) {
+			mif_err("ERR: exynos_cpufreq_lock fail\n");
+			return -EINVAL;
+		}
+
+		atomic_set(&umts_link_pm_data.freqlock, 1);
+		mif_debug("<%d> %d MHz\n", level, freq);
+	}
+	return 0;
+}
+
+static int exynos_cpu_frequency_unlock(void)
+{
+	if (atomic_read(&umts_link_pm_data.freqlock) == 1) {
+		exynos_cpufreq_lock_free(DVFS_LOCK_ID_USB_IF);
+		atomic_set(&umts_link_pm_data.freqlock, 0);
+		mif_debug("\n");
+	}
+	return 0;
+}
+#else
+static int exynos_cpu_frequency_lock(void)
+{
+	return 0;
+}
+
+static int exynos_cpu_frequency_unlock(void)
+{
+	return 0;
+}
+#endif
+
+void set_host_states(struct platform_device *pdev, int type)
+{
+}
+
+static int usb3503_hub_handler(void (*set_mode)(void), void *ctl)
+{
+	if (!set_mode || !ctl)
+		return -EINVAL;
+
+	usbhub_set_mode = (int (*)(struct usb3503_hubctl *, int))set_mode;
+	usbhub_ctl = (struct usb3503_hubctl *)ctl;
+
+	mif_info("set_mode(%pF)\n", set_mode);
+
+	return 0;
+}
+
+static int usb3503_hw_config(void)
+{
+	int err;
+
+	err = gpio_request(GPIO_USB_HUB_RST, "HUB_RST");
+	if (err) {
+		mif_err("ERR: fail to request gpio %s\n", "HUB_RST");
+	} else {
+		gpio_direction_output(GPIO_USB_HUB_RST, 0);
+		s3c_gpio_setpull(GPIO_USB_HUB_RST, S3C_GPIO_PULL_NONE);
+	}
+	s5p_gpio_set_drvstr(GPIO_USB_HUB_RST, S5P_GPIO_DRVSTR_LV1);
+	/* need to check drvstr 1 or 2 */
+
+	/* for USB3503 26Mhz Reference clock setting */
+	err = gpio_request(GPIO_USB_HUB_INT, "HUB_INT");
+	if (err) {
+		mif_err("ERR: fail to request gpio %s\n", "HUB_INT");
+	} else {
+		gpio_direction_output(GPIO_USB_HUB_INT, 1);
+		s3c_gpio_setpull(GPIO_USB_HUB_INT, S3C_GPIO_PULL_NONE);
+	}
+
+	return 0;
+}
+
+static int usb3503_reset_n(int val)
+{
+	gpio_set_value(GPIO_USB_HUB_RST, 0);
+
+	/* hub off from cpuidle(LPA), skip the msleep schedule*/
+	if (val) {
+		msleep(20);
+		mif_info("val = %d\n", gpio_get_value(GPIO_USB_HUB_RST));
+
+		gpio_set_value(GPIO_USB_HUB_RST, !!val);
+
+		mif_info("val = %d\n", gpio_get_value(GPIO_USB_HUB_RST));
+		udelay(5); /* need it ?*/
+	}
+	return 0;
+}
+
+static struct usb3503_platform_data usb3503_pdata = {
+	.initial_mode = USB3503_MODE_STANDBY,
+	.reset_n = usb3503_reset_n,
+	.register_hub_handler = usb3503_hub_handler,
+	.port_enable = host_port_enable,
+};
+
+static struct i2c_board_info i2c_devs20_emul[] __initdata = {
+	{
+		I2C_BOARD_INFO(USB3503_I2C_NAME, 0x08),
+		.platform_data = &usb3503_pdata,
+	},
+};
+
+/* I2C20_EMUL */
+static struct i2c_gpio_platform_data i2c20_platdata = {
+	.sda_pin = GPIO_USB_HUB_SDA,
+	.scl_pin = GPIO_USB_HUB_SCL,
+	/*FIXME: need to timming tunning...  */
+	.udelay	= 20,
+};
+
+static struct platform_device s3c_device_i2c20 = {
+	.name = "i2c-gpio",
+	.id = 20,
+	.dev.platform_data = &i2c20_platdata,
+};
+
+static int __init init_usbhub(void)
+{
+	usb3503_hw_config();
+	i2c_register_board_info(20, i2c_devs20_emul,
+				ARRAY_SIZE(i2c_devs20_emul));
+
+	platform_device_register(&s3c_device_i2c20);
+	return 0;
+}
+
+device_initcall(init_usbhub);
+
+static int host_port_enable(int port, int enable)
+{
+	int err;
+
+	mif_info("port(%d) control(%d)\n", port, enable);
+
+	if (enable) {
+		err = usbhub_set_mode(usbhub_ctl, USB3503_MODE_HUB);
+		if (err < 0) {
+			mif_err("ERR: hub on fail\n");
+			goto exit;
+		}
+		err = s5p_ehci_port_control(&s5p_device_ehci, port, 1);
+		if (err < 0) {
+			mif_err("ERR: port(%d) enable fail\n", port);
+			goto exit;
+		}
+	} else {
+		err = s5p_ehci_port_control(&s5p_device_ehci, port, 0);
+		if (err < 0) {
+			mif_err("ERR: port(%d) enable fail\n", port);
+			goto exit;
+		}
+		err = usbhub_set_mode(usbhub_ctl, USB3503_MODE_STANDBY);
+		if (err < 0) {
+			mif_err("ERR: hub off fail\n");
+			goto exit;
+		}
+	}
+
+	err = gpio_direction_output(umts_modem_data.gpio_host_active, enable);
+	mif_info("active state err(%d), en(%d), level(%d)\n",
+		err, enable, gpio_get_value(umts_modem_data.gpio_host_active));
+
+exit:
+	return err;
+}
+#else
+void set_host_states(struct platform_device *pdev, int type)
+{
+	if (active_ctl.gpio_initialized) {
+		mif_err("<%s> Active States =%d, %s\n", pdev->name, type);
+		gpio_direction_output(umts_link_pm_data.gpio_link_active, type);
+	} else {
+		active_ctl.gpio_request_host_active = 1;
+	}
+}
+#endif
+
diff --git a/arch/arm/mach-exynos/board-c1ctc-modems.c b/arch/arm/mach-exynos/board-c1ctc-modems.c
new file mode 100644
index 0000000..85e35f5
--- /dev/null
+++ b/arch/arm/mach-exynos/board-c1ctc-modems.c
@@ -0,0 +1,1712 @@
+/* linux/arch/arm/mach-xxxx/board-c1ctc-modems.c
+ * Copyright (C) 2010 Samsung Electronics. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/regulator/consumer.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/vmalloc.h>
+#include <linux/if_arp.h>
+
+/* inlcude platform specific file */
+#include <linux/platform_data/modem.h>
+#include <mach/sec_modem.h>
+#include <mach/gpio.h>
+#include <mach/gpio-exynos4.h>
+#include <plat/gpio-cfg.h>
+#include <mach/regs-mem.h>
+#include <plat/regs-srom.h>
+
+#ifdef CONFIG_USBHUB_USB3503
+#include <linux/i2c.h>
+#include <linux/i2c-gpio.h>
+#include <linux/platform_data/usb3503.h>
+#endif
+#include <plat/devs.h>
+#include <plat/ehci.h>
+
+
+#define SROM_CS0_BASE		0x04000000
+#define SROM_WIDTH		0x01000000
+#define SROM_NUM_ADDR_BITS	14
+
+/*
+ * For SROMC Configuration:
+ * SROMC_ADDR_BYTE enable for byte access
+ */
+#define SROMC_DATA_16		0x1
+#define SROMC_ADDR_BYTE		0x2
+#define SROMC_WAIT_EN		0x4
+#define SROMC_BYTE_EN		0x8
+#define SROMC_MASK		0xF
+
+/* Memory attributes */
+enum sromc_attr {
+	MEM_DATA_BUS_16BIT = 0x00000001,
+	MEM_BYTE_ADDRESSABLE = 0x00000002,
+	MEM_WAIT_EN = 0x00000004,
+	MEM_BYTE_EN = 0x00000008,
+
+};
+
+/* DPRAM configuration */
+struct sromc_cfg {
+	enum sromc_attr attr;
+	unsigned size;
+	unsigned csn;		/* CSn #			*/
+	unsigned addr;		/* Start address (physical)	*/
+	unsigned end;		/* End address (physical)	*/
+};
+
+/* DPRAM access timing configuration */
+struct sromc_access_cfg {
+	u32 tacs;		/* Address set-up before CSn		*/
+	u32 tcos;		/* Chip selection set-up before OEn	*/
+	u32 tacc;		/* Access cycle				*/
+	u32 tcoh;		/* Chip selection hold on OEn		*/
+	u32 tcah;		/* Address holding time after CSn	*/
+	u32 tacp;		/* Page mode access cycle at Page mode	*/
+	u32 pmc;		/* Page Mode config			*/
+};
+
+/* For MDM6600 EDPRAM (External DPRAM) */
+#define MSM_EDPRAM_SIZE		0x4000	/* 16 KB */
+
+
+#define INT_MASK_REQ_ACK_F	0x0020
+#define INT_MASK_REQ_ACK_R	0x0010
+#define INT_MASK_RES_ACK_F	0x0008
+#define INT_MASK_RES_ACK_R	0x0004
+#define INT_MASK_SEND_F		0x0002
+#define INT_MASK_SEND_R		0x0001
+
+#define INT_MASK_REQ_ACK_RFS	0x0400 /* Request RES_ACK_RFS		*/
+#define INT_MASK_RES_ACK_RFS	0x0200 /* Response of REQ_ACK_RFS	*/
+#define INT_MASK_SEND_RFS	0x0100 /* Indicate sending RFS data	*/
+
+
+/* Function prototypes */
+static void config_dpram_port_gpio(void);
+static void init_sromc(void);
+static void setup_sromc(unsigned csn, struct sromc_cfg *cfg,
+		struct sromc_access_cfg *acc_cfg);
+static void setup_dpram_speed(unsigned csn, struct sromc_access_cfg *acc_cfg);
+static int __init init_modem(void);
+
+#ifdef CONFIG_USBHUB_USB3503
+static int host_port_enable(int port, int enable);
+#else
+static int host_port_enable(int port, int enable)
+{
+	return s5p_ehci_port_control(&s5p_device_ehci, port, enable);
+}
+#endif
+
+static struct sromc_cfg msm_edpram_cfg = {
+	.attr = (MEM_DATA_BUS_16BIT | MEM_WAIT_EN | MEM_BYTE_EN),
+	.size = MSM_EDPRAM_SIZE,
+};
+
+static struct sromc_access_cfg msm_edpram_access_cfg[] = {
+	[DPRAM_SPEED_LOW] = {
+		.tacs = 0x2 << 28,
+		.tcos = 0x2 << 24,
+		.tacc = 0x3 << 16,
+		.tcoh = 0x2 << 12,
+		.tcah = 0x2 << 8,
+		.tacp = 0x2 << 4,
+		.pmc  = 0x0 << 0,
+	},
+};
+
+/*
+	magic_code +
+	access_enable +
+	fmt_tx_head + fmt_tx_tail + fmt_tx_buff +
+	raw_tx_head + raw_tx_tail + raw_tx_buff +
+	fmt_rx_head + fmt_rx_tail + fmt_rx_buff +
+	raw_rx_head + raw_rx_tail + raw_rx_buff +
+	padding +
+	mbx_cp2ap +
+	mbx_ap2cp
+ =	2 +
+	2 +
+	2 + 2 + 2044 +
+	2 + 2 + 6128 +
+	2 + 2 + 2044 +
+	2 + 2 + 6128 +
+	16 +
+	2 +
+	2
+ =	16384
+*/
+
+#define MSM_DP_FMT_TX_BUFF_SZ	2044
+#define MSM_DP_RAW_TX_BUFF_SZ	6128
+#define MSM_DP_FMT_RX_BUFF_SZ	2044
+#define MSM_DP_RAW_RX_BUFF_SZ	6128
+
+#define MAX_MSM_EDPRAM_IPC_DEV	2	/* FMT, RAW */
+
+struct msm_edpram_ipc_cfg {
+	u16 magic;
+	u16 access;
+
+	u16 fmt_tx_head;
+	u16 fmt_tx_tail;
+	u8  fmt_tx_buff[MSM_DP_FMT_TX_BUFF_SZ];
+
+	u16 raw_tx_head;
+	u16 raw_tx_tail;
+	u8  raw_tx_buff[MSM_DP_RAW_TX_BUFF_SZ];
+
+	u16 fmt_rx_head;
+	u16 fmt_rx_tail;
+	u8  fmt_rx_buff[MSM_DP_FMT_RX_BUFF_SZ];
+
+	u16 raw_rx_head;
+	u16 raw_rx_tail;
+	u8  raw_rx_buff[MSM_DP_RAW_RX_BUFF_SZ];
+
+	u8  padding[16];
+	u16 mbx_ap2cp;
+	u16 mbx_cp2ap;
+};
+
+struct msm_edpram_circ {
+	u16 __iomem *head;
+	u16 __iomem *tail;
+	u8  __iomem *buff;
+	u32          size;
+};
+
+struct msm_edpram_ipc_device {
+	char name[16];
+	int  id;
+
+	struct msm_edpram_circ txq;
+	struct msm_edpram_circ rxq;
+
+	u16 mask_req_ack;
+	u16 mask_res_ack;
+	u16 mask_send;
+};
+
+struct msm_edpram_ipc_map {
+	u16 __iomem *magic;
+	u16 __iomem *access;
+
+	struct msm_edpram_ipc_device dev[MAX_MSM_EDPRAM_IPC_DEV];
+
+	u16 __iomem *mbx_ap2cp;
+	u16 __iomem *mbx_cp2ap;
+};
+
+
+struct msm_edpram_boot_map {
+	u8  __iomem *buff;
+	u16  __iomem *frame_size;
+	u16  __iomem *tag;
+	u16  __iomem *count;
+};
+
+static struct msm_edpram_ipc_map msm_ipc_map;
+
+struct _param_nv {
+	unsigned char *addr;
+	unsigned int size;
+	unsigned int count;
+	unsigned int tag;
+};
+
+
+#if (MSM_EDPRAM_SIZE == 0x4000)
+/*
+------------------
+Buffer : 15KByte
+------------------
+Reserved: 1014Byte
+------------------
+SIZE: 2Byte
+------------------
+TAG: 2Byte
+------------------
+COUNT: 2Byte
+------------------
+AP -> CP Intr : 2Byte
+------------------
+CP -> AP Intr : 2Byte
+------------------
+*/
+#define DP_BOOT_CLEAR_OFFSET	4
+#define DP_BOOT_RSRVD_OFFSET	0x3C00
+#define DP_BOOT_SIZE_OFFSET	    0x3FF6
+#define DP_BOOT_TAG_OFFSET	    0x3FF8
+#define DP_BOOT_COUNT_OFFSET	0x3FFA
+
+
+#define DP_BOOT_FRAME_SIZE_LIMIT     0x3C00 /* 15KB = 15360byte = 0x3C00 */
+#else
+/*
+------------------
+Buffer : 31KByte
+------------------
+Reserved: 1014Byte
+------------------
+SIZE: 2Byte
+------------------
+TAG: 2Byte
+------------------
+COUNT: 2Byte
+------------------
+AP -> CP Intr : 2Byte
+------------------
+CP -> AP Intr : 2Byte
+------------------
+*/
+#define DP_BOOT_CLEAR_OFFSET	4
+#define DP_BOOT_RSRVD_OFFSET	0x7C00
+#define DP_BOOT_SIZE_OFFSET	    0x7FF6
+#define DP_BOOT_TAG_OFFSET	    0x7FF8
+#define DP_BOOT_COUNT_OFFSET	0x7FFA
+
+
+#define DP_BOOT_FRAME_SIZE_LIMIT     0x7C00 /* 31KB = 31744byte = 0x7C00 */
+#endif
+
+struct _param_check {
+	unsigned int total_size;
+	unsigned int rest_size;
+	unsigned int send_size;
+	unsigned int copy_start;
+	unsigned int copy_complete;
+	unsigned int boot_complete;
+};
+
+static struct _param_nv *data_param;
+static struct _param_check check_param;
+
+static unsigned int boot_start_complete;
+static struct msm_edpram_boot_map msm_edpram_bt_map;
+static struct msm_edpram_ipc_map msm_ipc_map;
+
+static void msm_edpram_reset(void);
+static void msm_edpram_clr_intr(void);
+static u16  msm_edpram_recv_intr(void);
+static void msm_edpram_send_intr(u16 irq_mask);
+static u16  msm_edpram_recv_msg(void);
+static void msm_edpram_send_msg(u16 msg);
+
+static u16  msm_edpram_get_magic(void);
+static void msm_edpram_set_magic(u16 value);
+static u16  msm_edpram_get_access(void);
+static void msm_edpram_set_access(u16 value);
+
+static u32  msm_edpram_get_tx_head(int dev_id);
+static u32  msm_edpram_get_tx_tail(int dev_id);
+static void msm_edpram_set_tx_head(int dev_id, u32 head);
+static void msm_edpram_set_tx_tail(int dev_id, u32 tail);
+static u8 __iomem *msm_edpram_get_tx_buff(int dev_id);
+static u32  msm_edpram_get_tx_buff_size(int dev_id);
+
+static u32  msm_edpram_get_rx_head(int dev_id);
+static u32  msm_edpram_get_rx_tail(int dev_id);
+static void msm_edpram_set_rx_head(int dev_id, u32 head);
+static void msm_edpram_set_rx_tail(int dev_id, u32 tail);
+static u8 __iomem *msm_edpram_get_rx_buff(int dev_id);
+static u32  msm_edpram_get_rx_buff_size(int dev_id);
+
+static u16  msm_edpram_get_mask_req_ack(int dev_id);
+static u16  msm_edpram_get_mask_res_ack(int dev_id);
+static u16  msm_edpram_get_mask_send(int dev_id);
+
+static void msm_log_disp(struct modemlink_dpram_control *dpctl);
+static int msm_uload_step1(struct modemlink_dpram_control *dpctl);
+static int msm_uload_step2(void *arg, struct modemlink_dpram_control *dpctl);
+static int msm_dload_prep(struct modemlink_dpram_control *dpctl);
+static int msm_dload(void *arg, struct modemlink_dpram_control *dpctl);
+static int msm_nv_load(void *arg, struct modemlink_dpram_control *dpctl);
+static int msm_boot_start(struct modemlink_dpram_control *dpctl);
+static int msm_boot_start_post_proc(void);
+static void msm_boot_start_handler(struct modemlink_dpram_control *dpctl);
+static void msm_dload_handler(struct modemlink_dpram_control *dpctl, u16 cmd);
+static void msm_bt_map_init(struct modemlink_dpram_control *dpctl);
+static void msm_load_init(struct modemlink_dpram_control *dpctl);
+
+static struct modemlink_dpram_control msm_edpram_ctrl = {
+	.reset      = msm_edpram_reset,
+
+	.clear_intr = msm_edpram_clr_intr,
+	.recv_intr  = msm_edpram_recv_intr,
+	.send_intr  = msm_edpram_send_intr,
+	.recv_msg   = msm_edpram_recv_msg,
+	.send_msg   = msm_edpram_send_msg,
+
+	.get_magic  = msm_edpram_get_magic,
+	.set_magic  = msm_edpram_set_magic,
+	.get_access = msm_edpram_get_access,
+	.set_access = msm_edpram_set_access,
+
+	.get_tx_head = msm_edpram_get_tx_head,
+	.get_tx_tail = msm_edpram_get_tx_tail,
+	.set_tx_head = msm_edpram_set_tx_head,
+	.set_tx_tail = msm_edpram_set_tx_tail,
+	.get_tx_buff = msm_edpram_get_tx_buff,
+	.get_tx_buff_size = msm_edpram_get_tx_buff_size,
+
+	.get_rx_head = msm_edpram_get_rx_head,
+	.get_rx_tail = msm_edpram_get_rx_tail,
+	.set_rx_head = msm_edpram_set_rx_head,
+	.set_rx_tail = msm_edpram_set_rx_tail,
+	.get_rx_buff = msm_edpram_get_rx_buff,
+	.get_rx_buff_size = msm_edpram_get_rx_buff_size,
+
+	.get_mask_req_ack = msm_edpram_get_mask_req_ack,
+	.get_mask_res_ack = msm_edpram_get_mask_res_ack,
+	.get_mask_send    = msm_edpram_get_mask_send,
+
+	.log_disp			= msm_log_disp,
+	.cpupload_step1		= msm_uload_step1,
+	.cpupload_step2		= msm_uload_step2,
+	.cpimage_load		= msm_dload,
+	.nvdata_load		= msm_nv_load,
+	.phone_boot_start	= msm_boot_start,
+	.dload_cmd_hdlr		= msm_dload_handler,
+	.bt_map_init		= msm_bt_map_init,
+	.load_init			= msm_load_init,
+	.cpimage_load_prepare			= msm_dload_prep,
+	.phone_boot_start_post_process	= msm_boot_start_post_proc,
+	.phone_boot_start_handler		= msm_boot_start_handler,
+
+	.dp_base = NULL,
+	.dp_size = 0,
+	.dp_type = EXT_DPRAM,
+
+	.dpram_irq        = MSM_DPRAM_INT_IRQ,
+	.dpram_irq_flags  = IRQF_TRIGGER_FALLING,
+	.dpram_irq_name   = "MDM6600_EDPRAM_IRQ",
+	.dpram_wlock_name = "MDM6600_EDPRAM_WLOCK",
+
+	.max_ipc_dev = IPC_RFS,
+};
+
+/*
+** CDMA target platform data
+*/
+static struct modem_io_t cdma_io_devices[] = {
+	[0] = {
+		.name = "cdma_boot0",
+		.id = 0x1,
+		.format = IPC_BOOT,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[1] = {
+		.name = "cdma_ipc0",
+		.id = 0x1,
+		.format = IPC_FMT,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[2] = {
+		.name = "cdma_multipdp",
+		.id = 0x1,
+		.format = IPC_MULTI_RAW,
+		.io_type = IODEV_DUMMY,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[3] = {
+		.name = "cdma_CSD",
+		.id = (1|0x20),
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[4] = {
+		.name = "cdma_FOTA",
+		.id = (2|0x20),
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[5] = {
+		.name = "cdma_GPS",
+		.id = (5|0x20),
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[6] = {
+		.name = "cdma_XTRA",
+		.id = (6|0x20),
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[7] = {
+		.name = "cdma_CDMA",
+		.id = (7|0x20),
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[8] = {
+		.name = "cdma_EFS",
+		.id = (8|0x20),
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[9] = {
+		.name = "cdma_TRFB",
+		.id = (9|0x20),
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[10] = {
+		.name = "rmnet0",
+		.id = 0x2A,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[11] = {
+		.name = "rmnet1",
+		.id = 0x2B,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[12] = {
+		.name = "rmnet2",
+		.id = 0x2C,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[13] = {
+		.name = "rmnet3",
+		.id = 0x2D,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[14] = {
+		.name = "cdma_SMD",
+		.id = (25|0x20),
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[15] = {
+		.name = "cdma_VTVD",
+		.id = (26|0x20),
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[16] = {
+		.name = "cdma_VTAD",
+		.id = (27|0x20),
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[17] = {
+		.name = "cdma_VTCTRL",
+		.id = (28|0x20),
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[18] = {
+		.name = "cdma_VTENT",
+		.id = (29|0x20),
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[19] = {
+		.name = "cdma_ramdump0",
+		.id = 0x1,
+		.format = IPC_RAMDUMP,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+};
+
+static struct modem_data cdma_modem_data = {
+	.name = "mdm6600",
+
+	.gpio_cp_on        = GPIO_CP_MSM_PWRON,
+	.gpio_cp_off       = 0,
+	.gpio_reset_req_n  = GPIO_CP_MSM_PMU_RST,
+	.gpio_cp_reset     = GPIO_CP_MSM_RST,
+	.gpio_pda_active   = GPIO_PDA_ACTIVE,
+	.gpio_phone_active = GPIO_MSM_PHONE_ACTIVE,
+	.gpio_flm_uart_sel = GPIO_BOOT_SW_SEL,
+
+	.gpio_cp_dump_int   = 0,
+	.gpio_cp_warm_reset = 0,
+
+	.use_handover = false,
+
+	.modem_net  = CDMA_NETWORK,
+	.modem_type = QC_MDM6600,
+	.link_types = LINKTYPE(LINKDEV_DPRAM),
+	.link_name  = "mdm6600_edpram",
+	.dpram_ctl  = &msm_edpram_ctrl,
+
+	.num_iodevs = ARRAY_SIZE(cdma_io_devices),
+	.iodevs     = cdma_io_devices,
+};
+
+static struct resource cdma_modem_res[] = {
+	[0] = {
+		.name  = "cp_active_irq",
+		.start = MSM_PHONE_ACTIVE_IRQ,
+		.end   = MSM_PHONE_ACTIVE_IRQ,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device cdma_modem = {
+	.name = "modem_if",
+	.id = 2,
+	.num_resources = ARRAY_SIZE(cdma_modem_res),
+	.resource = cdma_modem_res,
+	.dev = {
+		.platform_data = &cdma_modem_data,
+	},
+};
+
+static void msm_edpram_reset(void)
+{
+	return;
+}
+
+static void msm_edpram_clr_intr(void)
+{
+	ioread16(msm_ipc_map.mbx_cp2ap);
+}
+
+static u16 msm_edpram_recv_intr(void)
+{
+	return ioread16(msm_ipc_map.mbx_cp2ap);
+}
+
+static void msm_edpram_send_intr(u16 irq_mask)
+{
+	iowrite16(irq_mask, msm_ipc_map.mbx_ap2cp);
+}
+
+static u16 msm_edpram_recv_msg(void)
+{
+	return ioread16(msm_ipc_map.mbx_cp2ap);
+}
+
+static void msm_edpram_send_msg(u16 msg)
+{
+	iowrite16(msg, msm_ipc_map.mbx_ap2cp);
+}
+
+static u16 msm_edpram_get_magic(void)
+{
+	return ioread16(msm_ipc_map.magic);
+}
+
+static void msm_edpram_set_magic(u16 value)
+{
+	iowrite16(value, msm_ipc_map.magic);
+}
+
+static u16 msm_edpram_get_access(void)
+{
+	return ioread16(msm_ipc_map.access);
+}
+
+static void msm_edpram_set_access(u16 value)
+{
+	iowrite16(value, msm_ipc_map.access);
+}
+
+static u32 msm_edpram_get_tx_head(int dev_id)
+{
+	return ioread16(msm_ipc_map.dev[dev_id].txq.head);
+}
+
+static u32 msm_edpram_get_tx_tail(int dev_id)
+{
+	return ioread16(msm_ipc_map.dev[dev_id].txq.tail);
+}
+
+static void msm_edpram_set_tx_head(int dev_id, u32 head)
+{
+	iowrite16((u16)head, msm_ipc_map.dev[dev_id].txq.head);
+}
+
+static void msm_edpram_set_tx_tail(int dev_id, u32 tail)
+{
+	iowrite16((u16)tail, msm_ipc_map.dev[dev_id].txq.tail);
+}
+
+static u8 __iomem *msm_edpram_get_tx_buff(int dev_id)
+{
+	return msm_ipc_map.dev[dev_id].txq.buff;
+}
+
+static u32 msm_edpram_get_tx_buff_size(int dev_id)
+{
+	return msm_ipc_map.dev[dev_id].txq.size;
+}
+
+static u32 msm_edpram_get_rx_head(int dev_id)
+{
+	return ioread16(msm_ipc_map.dev[dev_id].rxq.head);
+}
+
+static u32 msm_edpram_get_rx_tail(int dev_id)
+{
+	return ioread16(msm_ipc_map.dev[dev_id].rxq.tail);
+}
+
+static void msm_edpram_set_rx_head(int dev_id, u32 head)
+{
+	return iowrite16((u16)head, msm_ipc_map.dev[dev_id].rxq.head);
+}
+
+static void msm_edpram_set_rx_tail(int dev_id, u32 tail)
+{
+	return iowrite16((u16)tail, msm_ipc_map.dev[dev_id].rxq.tail);
+}
+
+static u8 __iomem *msm_edpram_get_rx_buff(int dev_id)
+{
+	return msm_ipc_map.dev[dev_id].rxq.buff;
+}
+
+static u32 msm_edpram_get_rx_buff_size(int dev_id)
+{
+	return msm_ipc_map.dev[dev_id].rxq.size;
+}
+
+static u16 msm_edpram_get_mask_req_ack(int dev_id)
+{
+	return msm_ipc_map.dev[dev_id].mask_req_ack;
+}
+
+static u16 msm_edpram_get_mask_res_ack(int dev_id)
+{
+	return msm_ipc_map.dev[dev_id].mask_res_ack;
+}
+
+static u16 msm_edpram_get_mask_send(int dev_id)
+{
+	return msm_ipc_map.dev[dev_id].mask_send;
+}
+
+static void msm_log_disp(struct modemlink_dpram_control *dpctl)
+{
+	static unsigned char buf[151];
+	u8 __iomem *tmp_buff = NULL;
+
+	tmp_buff = dpctl->get_rx_buff(IPC_FMT);
+	memcpy(buf, tmp_buff, (sizeof(buf)-1));
+
+	pr_info("[LNK] | PHONE ERR MSG\t| CDMA Crash\n");
+	pr_info("[LNK] | PHONE ERR MSG\t| %s\n", buf);
+}
+
+static int msm_data_upload(struct _param_nv *param,
+	struct modemlink_dpram_control *dpctl)
+{
+	int retval = 0;
+	u16 in_interrupt = 0;
+	int count = 0;
+
+	while (1) {
+		if (!gpio_get_value(GPIO_MSM_DPRAM_INT)) {
+			in_interrupt = dpctl->recv_msg();
+			if (in_interrupt == 0xDBAB) {
+				break;
+			} else {
+				pr_err("[LNK][intr]:0x%08x\n", in_interrupt);
+				pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+				return -1;
+			}
+		}
+		msleep_interruptible(1);
+		count++;
+		if (count > 200) {
+			pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+			return -1;
+		}
+	}
+
+	param->size = ioread16(msm_edpram_bt_map.frame_size);
+	memcpy(param->addr, msm_edpram_bt_map.buff, param->size);
+	param->tag = ioread16(msm_edpram_bt_map.tag);
+	param->count = ioread16(msm_edpram_bt_map.count);
+
+	dpctl->clear_intr();
+	dpctl->send_msg(0xDB12);
+
+	return retval;
+
+}
+
+static int msm_data_load(struct _param_nv *param,
+	struct modemlink_dpram_control *dpctl)
+{
+	int retval = 0;
+
+	if (param->size <= DP_BOOT_FRAME_SIZE_LIMIT) {
+		memcpy(msm_edpram_bt_map.buff, param->addr, param->size);
+		iowrite16(param->size, msm_edpram_bt_map.frame_size);
+		iowrite16(param->tag, msm_edpram_bt_map.tag);
+		iowrite16(param->count, msm_edpram_bt_map.count);
+
+		dpctl->clear_intr();
+		dpctl->send_msg(0xDB12);
+
+	} else {
+		pr_err("[LNK/E]<%s> size:0x%x\n", __func__, param->size);
+	}
+
+	return retval;
+}
+
+static int msm_uload_step1(struct modemlink_dpram_control *dpctl)
+{
+	int retval = 0;
+	int count = 0;
+	u16 in_interrupt = 0, out_interrupt = 0;
+
+	pr_info("[LNK] +---------------------------------------------+\n");
+	pr_info("[LNK] |            UPLOAD PHONE SDRAM               |\n");
+	pr_info("[LNK] +---------------------------------------------+\n");
+
+	while (1) {
+		if (!gpio_get_value(GPIO_MSM_DPRAM_INT)) {
+			in_interrupt = dpctl->recv_msg();
+			pr_info("[LNK] [in_interrupt] 0x%04x\n", in_interrupt);
+			if (in_interrupt == 0x1234) {
+				break;
+			} else {
+				pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+				return -1;
+			}
+		}
+		msleep_interruptible(1);
+		count++;
+		if (count > 200) {
+			pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+			in_interrupt = dpctl->recv_msg();
+			if (in_interrupt == 0x1234) {
+				pr_info("[LNK] [in_interrupt]: 0x%04x\n",
+							in_interrupt);
+				break;
+			}
+			return -1;
+		}
+	}
+	out_interrupt = 0xDEAD;
+	dpctl->send_msg(out_interrupt);
+
+	return retval;
+}
+
+static int msm_uload_step2(void *arg,
+					struct modemlink_dpram_control *dpctl)
+{
+	int retval = 0;
+	struct _param_nv param;
+
+	retval = copy_from_user((void *)&param, (void *)arg, sizeof(param));
+	if (retval < 0) {
+		pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+		return -1;
+	}
+
+	retval = msm_data_upload(&param, dpctl);
+	if (retval < 0) {
+		pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+		return -1;
+	}
+
+	if (!(param.count % 500))
+		pr_info("[LNK] [param->count]:%d\n", param.count);
+
+	if (param.tag == 4) {
+		dpctl->clear_intr();
+		enable_irq(msm_edpram_ctrl.dpram_irq);
+		pr_info("[LNK] [param->tag]:%d\n", param.tag);
+	}
+
+	retval = copy_to_user((unsigned long *)arg, &param, sizeof(param));
+	if (retval < 0) {
+		pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+		return -1;
+	}
+
+	return retval;
+}
+
+static int msm_dload_prep(struct modemlink_dpram_control *dpctl)
+{
+	int retval = 0;
+	int count = 0;
+
+	while (1) {
+		if (check_param.copy_start) {
+			check_param.copy_start = 0;
+			break;
+		}
+		msleep_interruptible(10);
+		count++;
+		if (count > 200) {
+			pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+			return -1;
+		}
+	}
+
+	return retval;
+}
+
+static int msm_dload(void *arg, struct modemlink_dpram_control *dpctl)
+{
+	int retval = 0;
+	int count = 0;
+	unsigned char *img = NULL;
+	struct _param_nv param;
+
+	retval = copy_from_user((void *)&param, (void *)arg, sizeof(param));
+	if (retval < 0) {
+		pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+		return -1;
+	}
+
+	img = vmalloc(param.size);
+	if (img == NULL) {
+		pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+		return -1;
+	}
+	memset(img, 0, param.size);
+	memcpy(img, param.addr, param.size);
+
+	data_param = kzalloc(sizeof(struct _param_nv), GFP_KERNEL);
+	if (data_param == NULL)	{
+		pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+		vfree(img);
+		return -1;
+	}
+
+	check_param.total_size = param.size;
+	check_param.rest_size = param.size;
+	check_param.send_size = 0;
+	check_param.copy_complete = 0;
+
+	data_param->addr = img;
+	data_param->size = DP_BOOT_FRAME_SIZE_LIMIT;
+	data_param->count = param.count;
+
+	data_param->tag = 0x0001;
+
+	if (check_param.rest_size < DP_BOOT_FRAME_SIZE_LIMIT)
+		data_param->size = check_param.rest_size;
+
+	retval = msm_data_load(data_param, dpctl);
+
+	while (1) {
+		if (check_param.copy_complete) {
+			check_param.copy_complete = 0;
+
+			vfree(img);
+			kfree(data_param);
+
+			break;
+		}
+		msleep_interruptible(10);
+		count++;
+		if (count > 1000) {
+			pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+			vfree(img);
+			kfree(data_param);
+			return -1;
+		}
+	}
+
+	return retval;
+
+}
+
+static int msm_nv_load(void *arg, struct modemlink_dpram_control *dpctl)
+{
+	int retval = 0;
+	int count = 0;
+	unsigned char *img = NULL;
+	struct _param_nv param;
+
+	retval = copy_from_user((void *)&param, (void *)arg, sizeof(param));
+	if (retval < 0) {
+		pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+		return -1;
+	}
+
+	img = vmalloc(param.size);
+	if (img == NULL) {
+		pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+		return -1;
+	}
+	memset(img, 0, param.size);
+	memcpy(img, param.addr, param.size);
+
+	data_param = kzalloc(sizeof(struct _param_nv), GFP_KERNEL);
+	if (data_param == NULL) {
+		pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+		vfree(img);
+		return -1;
+	}
+
+	check_param.total_size = param.size;
+	check_param.rest_size = param.size;
+	check_param.send_size = 0;
+	check_param.copy_complete = 0;
+
+	data_param->addr = img;
+	data_param->size = DP_BOOT_FRAME_SIZE_LIMIT;
+	data_param->count = 1;
+	data_param->tag = 0x0002;
+
+	if (check_param.rest_size < DP_BOOT_FRAME_SIZE_LIMIT)
+		data_param->size = check_param.rest_size;
+
+	retval = msm_data_load(data_param, dpctl);
+
+	while (1) {
+		if (check_param.copy_complete) {
+			check_param.copy_complete = 0;
+
+			vfree(img);
+			kfree(data_param);
+
+			break;
+		}
+		msleep_interruptible(10);
+		count++;
+		if (count > 200) {
+			pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+			vfree(img);
+			kfree(data_param);
+			return -1;
+		}
+	}
+
+	return retval;
+
+}
+
+static int msm_boot_start(struct modemlink_dpram_control *dpctl)
+{
+
+	u16 out_interrupt = 0;
+	int count = 0;
+
+	/* Send interrupt -> '0x4567' */
+	out_interrupt = 0x4567;
+	dpctl->send_msg(out_interrupt);
+
+	while (1) {
+		if (check_param.boot_complete) {
+			check_param.boot_complete = 0;
+			break;
+		}
+		msleep_interruptible(10);
+		count++;
+		if (count > 200) {
+			pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+			return -1;
+		}
+	}
+
+	return 0;
+}
+
+static struct modemlink_dpram_control *tasklet_dpctl;
+
+static void interruptable_load_tasklet_handler(unsigned long data);
+
+static DECLARE_TASKLET(interruptable_load_tasklet,
+	interruptable_load_tasklet_handler, (unsigned long) &tasklet_dpctl);
+
+static void interruptable_load_tasklet_handler(unsigned long data)
+{
+	struct modemlink_dpram_control *dpctl =
+		(struct modemlink_dpram_control *)
+		(*((struct modemlink_dpram_control **) data));
+
+	if (data_param == NULL) {
+		pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+		return;
+	}
+
+	check_param.send_size += data_param->size;
+	check_param.rest_size -= data_param->size;
+	data_param->addr += data_param->size;
+
+	if (check_param.send_size < check_param.total_size) {
+
+		if (check_param.rest_size < DP_BOOT_FRAME_SIZE_LIMIT)
+			data_param->size = check_param.rest_size;
+
+
+		data_param->count += 1;
+
+		msm_data_load(data_param, dpctl);
+	} else {
+		data_param->tag = 0;
+		check_param.copy_complete = 1;
+	}
+
+}
+
+static int msm_boot_start_post_proc(void)
+{
+	int count = 0;
+
+	while (1) {
+		if (boot_start_complete) {
+			boot_start_complete = 0;
+			break;
+		}
+		msleep_interruptible(10);
+		count++;
+		if (count > 200) {
+			pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+			return -1;
+		}
+	}
+
+	return 0;
+}
+
+static void msm_boot_start_handler(struct modemlink_dpram_control *dpctl)
+{
+	boot_start_complete = 1;
+
+	/* Send INIT_END code to CP */
+	pr_info("[LNK] <%s> Send 0x11C2 (INIT_END)\n", __func__);
+
+	/*
+	 * INT_MASK_VALID|INT_MASK_CMD|INT_MASK_CP_AIRPLANE_BOOT|
+	 * INT_MASK_CP_AP_ANDROID|INT_MASK_CMD_INIT_END
+	 */
+	dpctl->send_intr((0x0080|0x0040|0x1000|0x0100|0x0002));
+}
+
+static void msm_dload_handler(struct modemlink_dpram_control *dpctl, u16 cmd)
+{
+	switch (cmd) {
+	case 0x1234:
+		check_param.copy_start = 1;
+		break;
+
+	case 0xDBAB:
+		tasklet_schedule(&interruptable_load_tasklet);
+		break;
+
+	case 0xABCD:
+		check_param.boot_complete = 1;
+		break;
+
+	default:
+		pr_err("[LNK/Err] <%s> Unknown command.. %x\n", __func__, cmd);
+	}
+}
+
+static void msm_bt_map_init(struct modemlink_dpram_control *dpctl)
+{
+	msm_edpram_bt_map.buff = (u8 *)(dpctl->dp_base);
+	msm_edpram_bt_map.frame_size  =
+		(u16 *)(dpctl->dp_base + DP_BOOT_SIZE_OFFSET);
+	msm_edpram_bt_map.tag =
+		(u16 *)(dpctl->dp_base + DP_BOOT_TAG_OFFSET);
+	msm_edpram_bt_map.count =
+		(u16 *)(dpctl->dp_base + DP_BOOT_COUNT_OFFSET);
+}
+
+
+static void msm_load_init(struct modemlink_dpram_control *dpctl)
+{
+	tasklet_dpctl = dpctl;
+	if (tasklet_dpctl == NULL)
+		pr_err("[LNK/Err] failed tasklet_dpctl remap\n");
+
+	check_param.total_size = 0;
+	check_param.rest_size = 0;
+	check_param.send_size = 0;
+	check_param.copy_start = 0;
+	check_param.copy_complete = 0;
+	check_param.boot_complete = 0;
+
+	dpctl->clear_intr();
+}
+
+static void config_cdma_modem_gpio(void)
+{
+	int err;
+	unsigned gpio_cp_on = cdma_modem_data.gpio_cp_on;
+	unsigned gpio_cp_off = cdma_modem_data.gpio_cp_off;
+	unsigned gpio_rst_req_n = cdma_modem_data.gpio_reset_req_n;
+	unsigned gpio_cp_rst = cdma_modem_data.gpio_cp_reset;
+	unsigned gpio_pda_active = cdma_modem_data.gpio_pda_active;
+	unsigned gpio_phone_active = cdma_modem_data.gpio_phone_active;
+	unsigned gpio_flm_uart_sel = cdma_modem_data.gpio_flm_uart_sel;
+
+	pr_info("[MODEMS] <%s>\n", __func__);
+
+	if (gpio_pda_active) {
+		err = gpio_request(gpio_pda_active, "PDA_ACTIVE");
+		if (err) {
+			pr_err("fail to request gpio %s\n", "PDA_ACTIVE");
+		} else {
+			gpio_direction_output(gpio_pda_active, 1);
+			s3c_gpio_setpull(gpio_pda_active, S3C_GPIO_PULL_NONE);
+			gpio_set_value(gpio_pda_active, 0);
+		}
+	}
+
+	if (gpio_phone_active) {
+		err = gpio_request(gpio_phone_active, "MSM_ACTIVE");
+		if (err) {
+			pr_err("fail to request gpio %s\n", "MSM_ACTIVE");
+		} else {
+			s3c_gpio_cfgpin(gpio_phone_active, S3C_GPIO_SFN(0xF));
+			s3c_gpio_setpull(gpio_phone_active, S3C_GPIO_PULL_NONE);
+			irq_set_irq_type(gpio_phone_active, IRQ_TYPE_EDGE_BOTH);
+		}
+	}
+
+	if (gpio_flm_uart_sel) {
+		err = gpio_request(gpio_flm_uart_sel, "BOOT_SW_SEL");
+		if (err) {
+			pr_err("fail to request gpio %s\n", "BOOT_SW_SEL");
+		} else {
+			gpio_direction_output(gpio_flm_uart_sel, 1);
+			s3c_gpio_setpull(gpio_flm_uart_sel, S3C_GPIO_PULL_NONE);
+			gpio_set_value(gpio_flm_uart_sel, 1);
+		}
+	}
+
+	if (gpio_cp_on) {
+		err = gpio_request(gpio_cp_on, "MSM_ON");
+		if (err) {
+			pr_err("fail to request gpio %s\n", "MSM_ON");
+		} else {
+			gpio_direction_output(gpio_cp_on, 1);
+			s3c_gpio_setpull(gpio_cp_on, S3C_GPIO_PULL_NONE);
+			gpio_set_value(gpio_cp_on, 0);
+		}
+	}
+
+	if (gpio_cp_off) {
+		err = gpio_request(gpio_cp_off, "MSM_OFF");
+		if (err) {
+			pr_err("fail to request gpio %s\n", "MSM_OFF");
+		} else {
+			gpio_direction_output(gpio_cp_off, 1);
+			s3c_gpio_setpull(gpio_cp_off, S3C_GPIO_PULL_NONE);
+			gpio_set_value(gpio_cp_off, 1);
+		}
+	}
+
+	if (gpio_rst_req_n) {
+		err = gpio_request(gpio_rst_req_n, "MSM_RST_REQ");
+		if (err) {
+			pr_err("fail to request gpio %s\n", "MSM_RST_REQ");
+		} else {
+			gpio_direction_output(gpio_rst_req_n, 1);
+			s3c_gpio_setpull(gpio_rst_req_n, S3C_GPIO_PULL_NONE);
+		}
+		gpio_set_value(gpio_rst_req_n, 0);
+	}
+
+	if (gpio_cp_rst) {
+		err = gpio_request(gpio_cp_rst, "MSM_RST");
+		if (err) {
+			pr_err("fail to request gpio %s\n", "MSM_RST");
+		} else {
+			gpio_direction_output(gpio_cp_rst, 1);
+			s3c_gpio_setpull(gpio_cp_rst, S3C_GPIO_PULL_NONE);
+		}
+		gpio_set_value(gpio_cp_rst, 0);
+	}
+}
+
+static u8 *msm_edpram_remap_mem_region(struct sromc_cfg *cfg)
+{
+	int			      dp_addr = 0;
+	int			      dp_size = 0;
+	u8 __iomem                   *dp_base = NULL;
+	struct msm_edpram_ipc_cfg    *ipc_map = NULL;
+	struct msm_edpram_ipc_device *dev = NULL;
+
+	dp_addr = cfg->addr;
+	dp_size = cfg->size;
+	dp_base = (u8 *)ioremap_nocache(dp_addr, dp_size);
+	if (!dp_base) {
+		pr_err("[MDM] <%s> dpram base ioremap fail\n", __func__);
+		return NULL;
+	}
+	pr_info("[MDM] <%s> DPRAM VA=0x%08X\n", __func__, (int)dp_base);
+
+	msm_edpram_ctrl.dp_base = (u8 __iomem *)dp_base;
+	msm_edpram_ctrl.dp_size = dp_size;
+
+	/* Map for IPC */
+	ipc_map = (struct msm_edpram_ipc_cfg *)dp_base;
+
+	/* Magic code and access enable fields */
+	msm_ipc_map.magic  = (u16 __iomem *)&ipc_map->magic;
+	msm_ipc_map.access = (u16 __iomem *)&ipc_map->access;
+
+	/* FMT */
+	dev = &msm_ipc_map.dev[IPC_FMT];
+
+	strcpy(dev->name, "FMT");
+	dev->id = IPC_FMT;
+
+	dev->txq.head = (u16 __iomem *)&ipc_map->fmt_tx_head;
+	dev->txq.tail = (u16 __iomem *)&ipc_map->fmt_tx_tail;
+	dev->txq.buff = (u8 __iomem *)&ipc_map->fmt_tx_buff[0];
+	dev->txq.size = MSM_DP_FMT_TX_BUFF_SZ;
+
+	dev->rxq.head = (u16 __iomem *)&ipc_map->fmt_rx_head;
+	dev->rxq.tail = (u16 __iomem *)&ipc_map->fmt_rx_tail;
+	dev->rxq.buff = (u8 __iomem *)&ipc_map->fmt_rx_buff[0];
+	dev->rxq.size = MSM_DP_FMT_RX_BUFF_SZ;
+
+	dev->mask_req_ack = INT_MASK_REQ_ACK_F;
+	dev->mask_res_ack = INT_MASK_RES_ACK_F;
+	dev->mask_send    = INT_MASK_SEND_F;
+
+	/* RAW */
+	dev = &msm_ipc_map.dev[IPC_RAW];
+
+	strcpy(dev->name, "RAW");
+	dev->id = IPC_RAW;
+
+	dev->txq.head = (u16 __iomem *)&ipc_map->raw_tx_head;
+	dev->txq.tail = (u16 __iomem *)&ipc_map->raw_tx_tail;
+	dev->txq.buff = (u8 __iomem *)&ipc_map->raw_tx_buff[0];
+	dev->txq.size = MSM_DP_RAW_TX_BUFF_SZ;
+
+	dev->rxq.head = (u16 __iomem *)&ipc_map->raw_rx_head;
+	dev->rxq.tail = (u16 __iomem *)&ipc_map->raw_rx_tail;
+	dev->rxq.buff = (u8 __iomem *)&ipc_map->raw_rx_buff[0];
+	dev->rxq.size = MSM_DP_RAW_RX_BUFF_SZ;
+
+	dev->mask_req_ack = INT_MASK_REQ_ACK_R;
+	dev->mask_res_ack = INT_MASK_RES_ACK_R;
+	dev->mask_send    = INT_MASK_SEND_R;
+
+#if 0
+	/* RFS */
+	dev = &msm_ipc_map.dev[IPC_RFS];
+
+	strcpy(dev->name, "RFS");
+	dev->id = IPC_RFS;
+
+	dev->txq.head = (u16 __iomem *)&ipc_map->rfs_tx_head;
+	dev->txq.tail = (u16 __iomem *)&ipc_map->rfs_tx_tail;
+	dev->txq.buff = (u8 __iomem *)&ipc_map->rfs_tx_buff[0];
+	dev->txq.size = MSM_DP_RFS_TX_BUFF_SZ;
+
+	dev->rxq.head = (u16 __iomem *)&ipc_map->rfs_rx_head;
+	dev->rxq.tail = (u16 __iomem *)&ipc_map->rfs_rx_tail;
+	dev->rxq.buff = (u8 __iomem *)&ipc_map->rfs_rx_buff[0];
+	dev->rxq.size = MSM_DP_RFS_RX_BUFF_SZ;
+
+	dev->mask_req_ack = INT_MASK_REQ_ACK_RFS;
+	dev->mask_res_ack = INT_MASK_RES_ACK_RFS;
+	dev->mask_send    = INT_MASK_SEND_RFS;
+#endif
+
+	/* Mailboxes */
+	msm_ipc_map.mbx_ap2cp = (u16 __iomem *)&ipc_map->mbx_ap2cp;
+	msm_ipc_map.mbx_cp2ap = (u16 __iomem *)&ipc_map->mbx_cp2ap;
+
+	return dp_base;
+}
+
+/**
+ *	DPRAM GPIO settings
+ *
+ *	SROM_NUM_ADDR_BITS value indicate the address line number or
+ *	the mux/demux dpram type. if you want to set mux mode, define the
+ *	SROM_NUM_ADDR_BITS to zero.
+ *
+ *	for CMC22x
+ *	CMC22x has 16KB + a SFR register address.
+ *	It used 14 bits (13bits for 16KB word address and 1 bit for SFR
+ *	register)
+ */
+static void config_dpram_port_gpio(void)
+{
+	int addr_bits = SROM_NUM_ADDR_BITS;
+
+	pr_info("[MDM] <%s> address line = %d bits\n", __func__, addr_bits);
+
+	/*
+	** Config DPRAM address/data GPIO pins
+	*/
+
+	/* Set GPIO for dpram address */
+	switch (addr_bits) {
+	case 0:
+		break;
+
+	case 13 ... 14:
+		s3c_gpio_cfgrange_nopull(EXYNOS4_GPY3(0), EXYNOS4_GPIO_Y3_NR,
+			S3C_GPIO_SFN(2));
+		s3c_gpio_cfgrange_nopull(EXYNOS4_GPY4(0),
+			addr_bits - EXYNOS4_GPIO_Y3_NR, S3C_GPIO_SFN(2));
+		pr_info("[MDM] <%s> last data gpio EXYNOS4_GPY4(0) ~ %d\n",
+			__func__, addr_bits - EXYNOS4_GPIO_Y3_NR);
+		break;
+
+	default:
+		pr_err("[MDM/E] <%s> Invalid addr_bits!!!\n", __func__);
+		return;
+	}
+
+	/* Set GPIO for dpram data - 16bit */
+	s3c_gpio_cfgrange_nopull(EXYNOS4_GPY5(0), 8, S3C_GPIO_SFN(2));
+	s3c_gpio_cfgrange_nopull(EXYNOS4_GPY6(0), 8, S3C_GPIO_SFN(2));
+
+	/* Setup SROMC CSn pins */
+	s3c_gpio_cfgpin(GPIO_DPRAM_CSN0, S3C_GPIO_SFN(2));
+
+	/* Config OEn, WEn */
+	s3c_gpio_cfgrange_nopull(GPIO_DPRAM_REN, 2, S3C_GPIO_SFN(2));
+
+	/* Config LBn, UBn */
+	s3c_gpio_cfgrange_nopull(GPIO_DPRAM_LBN, 2, S3C_GPIO_SFN(2));
+
+	/* Config BUSY */
+	s3c_gpio_cfgpin(GPIO_DPRAM_BUSY, S3C_GPIO_SFN(2));
+}
+
+static void init_sromc(void)
+{
+	struct clk *clk = NULL;
+
+	/* SROMC clk enable */
+	clk = clk_get(NULL, "sromc");
+	if (!clk) {
+		pr_err("[MDM/E] <%s> SROMC clock gate fail\n", __func__);
+		return;
+	}
+	clk_enable(clk);
+}
+
+static void setup_sromc
+(
+	unsigned csn,
+	struct sromc_cfg *cfg,
+	struct sromc_access_cfg *acc_cfg
+)
+{
+	unsigned bw = 0;
+	unsigned bc = 0;
+	void __iomem *bank_sfr = S5P_SROM_BC0 + (4 * csn);
+
+	pr_err("[MDM] <%s> SROMC settings for CS%d...\n", __func__, csn);
+
+	bw = __raw_readl(S5P_SROM_BW);
+	bc = __raw_readl(bank_sfr);
+	pr_err("[MDM] <%s> Old SROMC settings = BW(0x%08X), BC%d(0x%08X)\n",
+		__func__, bw, csn, bc);
+
+	/* Set the BW control field for the CSn */
+	bw &= ~(SROMC_MASK << (csn * 4));
+
+	if (cfg->attr | MEM_DATA_BUS_16BIT)
+		bw |= (SROMC_DATA_16 << (csn * 4));
+
+	if (cfg->attr | MEM_WAIT_EN)
+		bw |= (SROMC_WAIT_EN << (csn * 4));
+
+	if (cfg->attr | MEM_BYTE_EN)
+		bw |= (SROMC_BYTE_EN << (csn * 4));
+
+	writel(bw, S5P_SROM_BW);
+
+	/* Set SROMC memory access timing for the CSn */
+	bc = acc_cfg->tacs | acc_cfg->tcos | acc_cfg->tacc |
+	     acc_cfg->tcoh | acc_cfg->tcah | acc_cfg->tacp | acc_cfg->pmc;
+
+	writel(bc, bank_sfr);
+
+	/* Verify SROMC settings */
+	bw = __raw_readl(S5P_SROM_BW);
+	bc = __raw_readl(bank_sfr);
+	pr_err("[MDM] <%s> New SROMC settings = BW(0x%08X), BC%d(0x%08X)\n",
+		__func__, bw, csn, bc);
+}
+
+static void setup_dpram_speed(unsigned csn, struct sromc_access_cfg *acc_cfg)
+{
+	void __iomem *bank_sfr = S5P_SROM_BC0 + (4 * csn);
+	unsigned bc = 0;
+
+	bc = __raw_readl(bank_sfr);
+	pr_info("[MDM] <%s> Old CS%d setting = 0x%08X\n", __func__, csn, bc);
+
+	/* SROMC memory access timing setting */
+	bc = acc_cfg->tacs | acc_cfg->tcos | acc_cfg->tacc |
+	     acc_cfg->tcoh | acc_cfg->tcah | acc_cfg->tacp | acc_cfg->pmc;
+	writel(bc, bank_sfr);
+
+	bc = __raw_readl(bank_sfr);
+	pr_err("[MDM] <%s> New CS%d setting = 0x%08X\n", __func__, csn, bc);
+}
+
+static int __init init_modem(void)
+{
+	struct sromc_cfg *cfg = NULL;
+	struct sromc_access_cfg *acc_cfg = NULL;
+
+	msm_edpram_cfg.csn	= 0;
+	msm_edpram_cfg.addr = SROM_CS0_BASE + (SROM_WIDTH * msm_edpram_cfg.csn);
+	msm_edpram_cfg.end	= msm_edpram_cfg.addr + msm_edpram_cfg.size - 1;
+
+	config_dpram_port_gpio();
+	config_cdma_modem_gpio();
+
+	init_sromc();
+	cfg = &msm_edpram_cfg;
+	acc_cfg = &msm_edpram_access_cfg[DPRAM_SPEED_LOW];
+	setup_sromc(cfg->csn, cfg, acc_cfg);
+
+	if (!msm_edpram_remap_mem_region(&msm_edpram_cfg))
+		return -1;
+	platform_device_register(&cdma_modem);
+
+	return 0;
+}
+late_initcall(init_modem);
+/*device_initcall(init_modem);*/
+
+#ifdef CONFIG_USBHUB_USB3503
+static int (*usbhub_set_mode)(struct usb3503_hubctl *, int);
+static struct usb3503_hubctl *usbhub_ctl;
+
+void set_host_states(struct platform_device *pdev, int type)
+{
+}
+
+static int usb3503_hub_handler(void (*set_mode)(void), void *ctl)
+{
+	if (!set_mode || !ctl)
+		return -EINVAL;
+
+	usbhub_set_mode = (int (*)(struct usb3503_hubctl *, int))set_mode;
+	usbhub_ctl = (struct usb3503_hubctl *)ctl;
+
+	pr_info("[MDM] <%s> set_mode(%pF)\n", __func__, set_mode);
+
+	return 0;
+}
+
+static int usb3503_hw_config(void)
+{
+	int err;
+
+	err = gpio_request(GPIO_USB_HUB_CONNECT, "HUB_CONNECT");
+	if (err) {
+		pr_err("fail to request gpio %s\n", "HUB_CONNECT");
+	} else {
+		gpio_direction_output(GPIO_USB_HUB_CONNECT, 0);
+		s3c_gpio_setpull(GPIO_USB_HUB_CONNECT, S3C_GPIO_PULL_NONE);
+	}
+	s5p_gpio_set_drvstr(GPIO_USB_HUB_CONNECT, S5P_GPIO_DRVSTR_LV1);
+
+	err = gpio_request(GPIO_USB_BOOT_EN, "USB_BOOT_EN");
+	if (err) {
+		pr_err("fail to request gpio %s\n", "USB_BOOT_EN");
+	} else {
+		gpio_direction_output(GPIO_USB_BOOT_EN, 1);
+		s3c_gpio_setpull(GPIO_USB_BOOT_EN, S3C_GPIO_PULL_NONE);
+	}
+	msleep(100);
+
+	err = gpio_request(GPIO_USB_HUB_RST, "HUB_RST");
+	if (err) {
+		pr_err("fail to request gpio %s\n", "HUB_RST");
+	} else {
+		gpio_direction_output(GPIO_USB_HUB_RST, 0);
+		s3c_gpio_setpull(GPIO_USB_HUB_RST, S3C_GPIO_PULL_NONE);
+	}
+	s5p_gpio_set_drvstr(GPIO_USB_HUB_RST, S5P_GPIO_DRVSTR_LV1);
+	/* need to check drvstr 1 or 2 */
+
+	/* for USB3503 26Mhz Reference clock setting */
+	err = gpio_request(GPIO_USB_HUB_INT, "HUB_INT");
+	if (err) {
+		pr_err("fail to request gpio %s\n", "HUB_INT");
+	} else {
+		gpio_direction_output(GPIO_USB_HUB_INT, 1);
+		s3c_gpio_setpull(GPIO_USB_HUB_INT, S3C_GPIO_PULL_NONE);
+	}
+
+	return 0;
+}
+
+static int usb3503_reset_n(int val)
+{
+	gpio_set_value(GPIO_USB_HUB_RST, 0);
+	msleep(20);
+	pr_info("[MDM] <%s> val = %d\n", __func__,
+		gpio_get_value(GPIO_USB_HUB_RST));
+	gpio_set_value(GPIO_USB_HUB_RST, !!val);
+
+	pr_info("[MDM] <%s> val = %d\n", __func__,
+		gpio_get_value(GPIO_USB_HUB_RST));
+
+	udelay(5); /* need it ?*/
+	return 0;
+}
+
+static struct usb3503_platform_data usb3503_pdata = {
+	.initial_mode = USB3503_MODE_STANDBY,
+	.reset_n = usb3503_reset_n,
+	.register_hub_handler = usb3503_hub_handler,
+	.port_enable = host_port_enable,
+};
+
+static struct i2c_board_info i2c_devs20_emul[] __initdata = {
+	{
+		I2C_BOARD_INFO(USB3503_I2C_NAME, 0x08),
+		.platform_data = &usb3503_pdata,
+	},
+};
+
+/* I2C20_EMUL */
+static struct i2c_gpio_platform_data i2c20_platdata = {
+	.sda_pin = GPIO_USB_HUB_SDA,
+	.scl_pin = GPIO_USB_HUB_SCL,
+	/*FIXME: need to timming tunning...  */
+	.udelay	= 20,
+};
+
+static struct platform_device s3c_device_i2c20 = {
+	.name = "i2c-gpio",
+	.id = 20,
+	.dev.platform_data = &i2c20_platdata,
+};
+
+static int __init init_usbhub(void)
+{
+	usb3503_hw_config();
+	i2c_register_board_info(20, i2c_devs20_emul,
+				ARRAY_SIZE(i2c_devs20_emul));
+
+	platform_device_register(&s3c_device_i2c20);
+	return 0;
+}
+
+device_initcall(init_usbhub);
+
+static int host_port_enable(int port, int enable)
+{
+	int err, retry = 30;
+
+	pr_info("[MDM] <%s> port(%d) control(%d)\n", __func__, port, enable);
+
+	if (enable) {
+		err = usbhub_set_mode(usbhub_ctl, USB3503_MODE_HUB);
+		if (err < 0) {
+			pr_err("[MDM] <%s> hub on fail\n", __func__);
+			goto exit;
+		}
+		err = s5p_ehci_port_control(&s5p_device_ehci, port, 1);
+		if (err < 0) {
+			pr_err("[MDM] <%s> port(%d) enable fail\n", __func__,
+				port);
+			goto exit;
+		}
+#ifdef CONFIG_LTE_MODEM_CMC221
+		msleep(20);
+		err = gpio_direction_output(umts_modem_data.gpio_slave_wakeup,
+			1);
+		pr_err("[MDM] <%s> slave wakeup err(%d), en(%d), level(%d)\n",
+			__func__, err, 1,
+			gpio_get_value(umts_modem_data.gpio_slave_wakeup));
+
+		while (!gpio_get_value(umts_modem_data.gpio_slave_wakeup)
+			&& retry--)
+			msleep(20);
+		pr_err("[MDM] <%s> Host wakeup (%d) retry(%d)\n", __func__,
+			gpio_get_value(umts_modem_data.gpio_host_wakeup),
+			retry);
+		err = gpio_direction_output(umts_modem_data.gpio_slave_wakeup,
+			0);
+		pr_err("[MDM] <%s> slave wakeup err(%d), en(%d), level(%d)\n",
+			__func__, err, 0,
+			gpio_get_value(umts_modem_data.gpio_slave_wakeup));
+#endif
+	} else {
+		err = s5p_ehci_port_control(&s5p_device_ehci, port, 0);
+		if (err < 0) {
+			pr_err("[MDM] <%s> port(%d) enable fail\n", __func__,
+				port);
+			goto exit;
+		}
+		err = usbhub_set_mode(usbhub_ctl, USB3503_MODE_STANDBY);
+		if (err < 0) {
+			pr_err("[MDM] <%s> hub off fail\n", __func__);
+			goto exit;
+		}
+	}
+
+#ifdef CONFIG_LTE_MODEM_CMC221
+	err = gpio_direction_output(umts_modem_data.gpio_host_active, enable);
+	pr_info("[MDM] <%s> active state err(%d), en(%d), level(%d)\n",
+		__func__, err, enable,
+		gpio_get_value(umts_modem_data.gpio_host_active));
+#endif
+
+exit:
+	return err;
+}
+#else
+void set_host_states(struct platform_device *pdev, int type)
+{
+	if (active_ctl.gpio_initialized) {
+		pr_err(" [MODEM_IF] Active States =%d, %s\n", type, pdev->name);
+		gpio_direction_output(modem_link_pm_data.gpio_link_active,
+			type);
+	} else
+		active_ctl.gpio_request_host_active = 1;
+}
+#endif
+
diff --git a/arch/arm/mach-exynos/board-c1lgt-modems.c b/arch/arm/mach-exynos/board-c1lgt-modems.c
new file mode 100644
index 0000000..aa218db
--- /dev/null
+++ b/arch/arm/mach-exynos/board-c1lgt-modems.c
@@ -0,0 +1,1937 @@
+/* linux/arch/arm/mach-xxxx/board-c1lgt-modems.c
+ * Copyright (C) 2010 Samsung Electronics. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/regulator/consumer.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+
+/* inlcude platform specific file */
+#include <linux/platform_data/modem.h>
+#include <mach/sec_modem.h>
+#include <mach/gpio.h>
+#include <mach/gpio-exynos4.h>
+#include <plat/gpio-cfg.h>
+#include <mach/regs-mem.h>
+#include <plat/regs-srom.h>
+
+#ifdef CONFIG_USBHUB_USB3503
+#include <linux/i2c.h>
+#include <linux/i2c-gpio.h>
+#include <linux/platform_data/usb3503.h>
+#include <mach/cpufreq.h>
+#include <plat/usb-phy.h>
+#endif
+#include <plat/devs.h>
+#include <plat/ehci.h>
+
+#define SROM_CS0_BASE		0x04000000
+#define SROM_WIDTH		0x01000000
+#define SROM_NUM_ADDR_BITS	14
+
+/* For "bus width and wait control (BW)" register */
+enum sromc_attr {
+	SROMC_DATA_16   = 0x1,	/* 16-bit data bus	*/
+	SROMC_BYTE_ADDR = 0x2,	/* Byte base address	*/
+	SROMC_WAIT_EN   = 0x4,	/* Wait enabled		*/
+	SROMC_BYTE_EN   = 0x8,	/* Byte access enabled	*/
+	SROMC_MASK      = 0xF
+};
+
+/* DPRAM configuration */
+struct sromc_cfg {
+	enum sromc_attr attr;
+	unsigned size;
+	unsigned csn;		/* CSn #			*/
+	unsigned addr;		/* Start address (physical)	*/
+	unsigned end;		/* End address (physical)	*/
+};
+
+/* DPRAM access timing configuration */
+struct sromc_access_cfg {
+	u32 tacs;		/* Address set-up before CSn		*/
+	u32 tcos;		/* Chip selection set-up before OEn	*/
+	u32 tacc;		/* Access cycle				*/
+	u32 tcoh;		/* Chip selection hold on OEn		*/
+	u32 tcah;		/* Address holding time after CSn	*/
+	u32 tacp;		/* Page mode access cycle at Page mode	*/
+	u32 pmc;		/* Page Mode config			*/
+};
+
+/* For CMC221 IDPRAM (Internal DPRAM) */
+#define CMC_IDPRAM_SIZE		0x4000	/* 16 KB */
+
+/* FOR CMC221 SFR for IDPRAM */
+#define CMC_INT2CP_REG		0x10	/* Interrupt to CP            */
+#define CMC_INT2AP_REG		0x50
+#define CMC_CLR_INT_REG		0x28	/* Clear Interrupt to AP      */
+#define CMC_RESET_REG		0x3C
+#define CMC_PUT_REG		0x40	/* AP->CP reg for hostbooting */
+#define CMC_GET_REG		0x50	/* CP->AP reg for hostbooting */
+
+/* For CBP7.2 EDPRAM (External DPRAM) */
+#define CBP_EDPRAM_SIZE		0x4000	/* 16 KB */
+
+#define INT_MASK_REQ_ACK_F	0x0020
+#define INT_MASK_REQ_ACK_R	0x0010
+#define INT_MASK_RES_ACK_F	0x0008
+#define INT_MASK_RES_ACK_R	0x0004
+#define INT_MASK_SEND_F		0x0002
+#define INT_MASK_SEND_R		0x0001
+
+#define INT_MASK_REQ_ACK_RFS	0x0400 /* Request RES_ACK_RFS		*/
+#define INT_MASK_RES_ACK_RFS	0x0200 /* Response of REQ_ACK_RFS	*/
+#define INT_MASK_SEND_RFS	0x0100 /* Indicate sending RFS data	*/
+
+
+/* Function prototypes */
+static void config_dpram_port_gpio(void);
+static void init_sromc(void);
+static void setup_sromc(unsigned csn, struct sromc_cfg *cfg,
+		struct sromc_access_cfg *acc_cfg);
+static void setup_dpram_speed(unsigned csn, struct sromc_access_cfg *acc_cfg);
+static int __init init_modem(void);
+
+#ifdef CONFIG_USBHUB_USB3503
+static int host_port_enable(int port, int enable);
+#else
+static int host_port_enable(int port, int enable)
+{
+	return s5p_ehci_port_control(&s5p_device_ehci, port, enable);
+}
+#endif
+
+#ifdef CONFIG_LTE_MODEM_CMC221
+static struct sromc_cfg cmc_idpram_cfg = {
+	.attr = SROMC_DATA_16,
+	.size = CMC_IDPRAM_SIZE,
+};
+
+static struct sromc_access_cfg cmc_idpram_access_cfg[] = {
+	[DPRAM_SPEED_LOW] = {
+		/* for 33 MHz clock, 64 cycles */
+		.tacs = 0x08 << 28,
+		.tcos = 0x08 << 24,
+		.tacc = 0x1F << 16,
+		.tcoh = 0x08 << 12,
+		.tcah = 0x08 << 8,
+		.tacp = 0x00 << 4,
+		.pmc  = 0x00 << 0,
+	},
+	[DPRAM_SPEED_MID] = {
+		/* for 66 MHz clock, 32 cycles */
+		.tacs = 0x01 << 28,
+		.tcos = 0x01 << 24,
+		.tacc = 0x1B << 16,
+		.tcoh = 0x01 << 12,
+		.tcah = 0x01 << 8,
+		.tacp = 0x00 << 4,
+		.pmc  = 0x00 << 0,
+	},
+	[DPRAM_SPEED_HIGH] = {
+		/* for 133 MHz clock, 16 cycles */
+		.tacs = 0x01 << 28,
+		.tcos = 0x01 << 24,
+		.tacc = 0x0B << 16,
+		.tcoh = 0x01 << 12,
+		.tcah = 0x01 << 8,
+		.tacp = 0x00 << 4,
+		.pmc  = 0x00 << 0,
+	},
+};
+
+/*
+	magic_code +
+	access_enable +
+	fmt_tx_head + fmt_tx_tail + fmt_tx_buff +
+	raw_tx_head + raw_tx_tail + raw_tx_buff +
+	fmt_rx_head + fmt_rx_tail + fmt_rx_buff +
+	raw_rx_head + raw_rx_tail + raw_rx_buff +
+	mbx_cp2ap +
+	mbx_ap2cp
+ =	2 +
+	2 +
+	2 + 2 + 1336 +
+	2 + 2 + 4564 +
+	2 + 2 + 1336 +
+	2 + 2 + 9124 +
+	2 +
+	2
+ =	16384
+*/
+
+#define DP_FMT_TX_BUFF_SZ	1336
+#define DP_RAW_TX_BUFF_SZ	4564
+#define DP_FMT_RX_BUFF_SZ	1336
+#define DP_RAW_RX_BUFF_SZ	9124
+
+#define MAX_CMC_IDPRAM_IPC_DEV	(IPC_RAW + 1)	/* FMT, RAW */
+
+struct dpram_ipc_cfg {
+	u16 magic;
+	u16 access;
+
+	u16 fmt_tx_head;
+	u16 fmt_tx_tail;
+	u8  fmt_tx_buff[DP_FMT_TX_BUFF_SZ];
+
+	u16 raw_tx_head;
+	u16 raw_tx_tail;
+	u8  raw_tx_buff[DP_RAW_TX_BUFF_SZ];
+
+	u16 fmt_rx_head;
+	u16 fmt_rx_tail;
+	u8  fmt_rx_buff[DP_FMT_RX_BUFF_SZ];
+
+	u16 raw_rx_head;
+	u16 raw_rx_tail;
+	u8  raw_rx_buff[DP_RAW_RX_BUFF_SZ];
+
+	u16 mbx_cp2ap;
+	u16 mbx_ap2cp;
+};
+
+struct cmc221_idpram_sfr {
+	u16 __iomem *int2cp;
+	u16 __iomem *int2ap;
+	u16 __iomem *clr_int2ap;
+	u16 __iomem *reset;
+	u16 __iomem *msg2cp;
+	u16 __iomem *msg2ap;
+};
+
+static struct dpram_ipc_map cmc_ipc_map;
+static u8 *cmc_sfr_base;
+static struct cmc221_idpram_sfr cmc_sfr;
+
+/* Function prototypes */
+static void cmc_idpram_reset(void);
+static void cmc_idpram_setup_speed(enum dpram_speed);
+static int  cmc_idpram_wakeup(void);
+static void cmc_idpram_sleep(void);
+static void cmc_idpram_clr_intr(void);
+static u16  cmc_idpram_recv_intr(void);
+static void cmc_idpram_send_intr(u16 irq_mask);
+static u16  cmc_idpram_recv_msg(void);
+static void cmc_idpram_send_msg(u16 msg);
+
+static u16  cmc_idpram_get_magic(void);
+static void cmc_idpram_set_magic(u16 value);
+static u16  cmc_idpram_get_access(void);
+static void cmc_idpram_set_access(u16 value);
+
+static u32  cmc_idpram_get_tx_head(int dev_id);
+static u32  cmc_idpram_get_tx_tail(int dev_id);
+static void cmc_idpram_set_tx_head(int dev_id, u32 head);
+static void cmc_idpram_set_tx_tail(int dev_id, u32 tail);
+static u8 __iomem *cmc_idpram_get_tx_buff(int dev_id);
+static u32  cmc_idpram_get_tx_buff_size(int dev_id);
+
+static u32  cmc_idpram_get_rx_head(int dev_id);
+static u32  cmc_idpram_get_rx_tail(int dev_id);
+static void cmc_idpram_set_rx_head(int dev_id, u32 head);
+static void cmc_idpram_set_rx_tail(int dev_id, u32 tail);
+static u8 __iomem *cmc_idpram_get_rx_buff(int dev_id);
+static u32  cmc_idpram_get_rx_buff_size(int dev_id);
+
+static u16  cmc_idpram_get_mask_req_ack(int dev_id);
+static u16  cmc_idpram_get_mask_res_ack(int dev_id);
+static u16  cmc_idpram_get_mask_send(int dev_id);
+
+static struct modemlink_dpram_control cmc_idpram_ctrl = {
+	.reset = cmc_idpram_reset,
+
+	.setup_speed = cmc_idpram_setup_speed,
+
+	.wakeup = cmc_idpram_wakeup,
+	.sleep  = cmc_idpram_sleep,
+
+	.clear_intr = cmc_idpram_clr_intr,
+	.recv_intr  = cmc_idpram_recv_intr,
+	.send_intr  = cmc_idpram_send_intr,
+	.recv_msg   = cmc_idpram_recv_msg,
+	.send_msg   = cmc_idpram_send_msg,
+
+	.get_magic  = cmc_idpram_get_magic,
+	.set_magic  = cmc_idpram_set_magic,
+	.get_access = cmc_idpram_get_access,
+	.set_access = cmc_idpram_set_access,
+
+	.get_tx_head = cmc_idpram_get_tx_head,
+	.get_tx_tail = cmc_idpram_get_tx_tail,
+	.set_tx_head = cmc_idpram_set_tx_head,
+	.set_tx_tail = cmc_idpram_set_tx_tail,
+	.get_tx_buff = cmc_idpram_get_tx_buff,
+	.get_tx_buff_size = cmc_idpram_get_tx_buff_size,
+
+	.get_rx_head = cmc_idpram_get_rx_head,
+	.get_rx_tail = cmc_idpram_get_rx_tail,
+	.set_rx_head = cmc_idpram_set_rx_head,
+	.set_rx_tail = cmc_idpram_set_rx_tail,
+	.get_rx_buff = cmc_idpram_get_rx_buff,
+	.get_rx_buff_size = cmc_idpram_get_rx_buff_size,
+
+	.get_mask_req_ack = cmc_idpram_get_mask_req_ack,
+	.get_mask_res_ack = cmc_idpram_get_mask_res_ack,
+	.get_mask_send    = cmc_idpram_get_mask_send,
+
+	.dp_base = NULL,
+	.dp_size = 0,
+	.dp_type = CP_IDPRAM,
+	.aligned = 1,
+
+	.dpram_irq = CMC_IDPRAM_INT_IRQ_00,
+	.dpram_irq_flags = (IRQF_NO_SUSPEND | IRQF_TRIGGER_RISING),
+	.dpram_irq_name = "CMC221_IDPRAM_IRQ",
+	.dpram_wlock_name = "CMC221_IDPRAM_WLOCK",
+
+	.max_ipc_dev = MAX_CMC_IDPRAM_IPC_DEV,
+};
+
+/*
+** UMTS target platform data
+*/
+static struct modem_io_t umts_io_devices[] = {
+	[0] = {
+		.name = "umts_boot0",
+		.id = 0,
+		.format = IPC_BOOT,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[1] = {
+		.name = "umts_ipc0",
+		.id = 235,
+		.format = IPC_FMT,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[2] = {
+		.name = "umts_rfs0",
+		.id = 245,
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[3] = {
+		.name = "lte_multipdp",
+		.id = 0,
+		.format = IPC_MULTI_RAW,
+		.io_type = IODEV_DUMMY,
+		.links = LINKTYPE(LINKDEV_DPRAM) | LINKTYPE(LINKDEV_USB),
+		.tx_link = LINKDEV_DPRAM,
+	},
+	[4] = {
+		.name = "lte_rmnet0",
+		.id = 10,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_DPRAM) | LINKTYPE(LINKDEV_USB),
+		.tx_link = LINKDEV_DPRAM,
+	},
+	[5] = {
+		.name = "lte_rmnet1",
+		.id = 11,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_DPRAM) | LINKTYPE(LINKDEV_USB),
+		.tx_link = LINKDEV_DPRAM,
+	},
+	[6] = {
+		.name = "lte_rmnet2",
+		.id = 12,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_DPRAM) | LINKTYPE(LINKDEV_USB),
+		.tx_link = LINKDEV_DPRAM,
+	},
+	[7] = {
+		.name = "lte_rmnet3",
+		.id = 13,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_DPRAM) | LINKTYPE(LINKDEV_USB),
+		.tx_link = LINKDEV_DPRAM,
+	},
+	[8] = {
+		.name = "umts_csd",	/* CS Video Telephony */
+		.id = 1,
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[9] = {
+		.name = "umts_router",	/* AT Iface & Dial-up */
+		.id = 25,
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[10] = {
+		.name = "umts_dm0",	/* DM Port */
+		.id = 28,
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[11] = {
+		.name = "umts_loopback_ap2cp",
+		.id = 30,
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[12] = {
+		.name = "umts_loopback_cp2ap",
+		.id = 31,
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[13] = {
+		.name = "umts_ramdump0",
+		.id = 0,
+		.format = IPC_RAMDUMP,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[14] = {
+		.name = "lte_ipc0",
+		.id = 235,
+		.format = IPC_FMT,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_USB),
+	},
+};
+
+static int exynos_cpu_frequency_lock(void);
+static int exynos_cpu_frequency_unlock(void);
+
+static struct modemlink_pm_data umts_link_pm_data = {
+	.name = "umts_link_pm",
+
+	.gpio_link_enable    = 0,
+	.gpio_link_active    = GPIO_ACTIVE_STATE,
+	.gpio_link_hostwake  = GPIO_IPC_HOST_WAKEUP,
+	.gpio_link_slavewake = GPIO_IPC_SLAVE_WAKEUP,
+
+	.port_enable = host_port_enable,
+/*
+	.link_reconnect = umts_link_reconnect,
+*/
+	.freqlock = ATOMIC_INIT(0),
+	.cpufreq_lock = exynos_cpu_frequency_lock,
+	.cpufreq_unlock = exynos_cpu_frequency_unlock,
+
+	.autosuspend_delay_ms = 2000,
+
+	.has_usbhub = true,
+};
+
+static struct modem_data umts_modem_data = {
+	.name = "cmc221",
+
+	.gpio_cp_on = CP_CMC221_PMIC_PWRON,
+	.gpio_cp_reset = CP_CMC221_CPU_RST,
+	.gpio_phone_active = GPIO_LTE_ACTIVE,
+
+	.gpio_dpram_int = GPIO_CMC_IDPRAM_INT_00,
+	.gpio_dpram_status = GPIO_CMC_IDPRAM_STATUS,
+	.gpio_dpram_wakeup = GPIO_CMC_IDPRAM_WAKEUP,
+
+	.gpio_slave_wakeup = GPIO_IPC_SLAVE_WAKEUP,
+	.gpio_host_active = GPIO_ACTIVE_STATE,
+	.gpio_host_wakeup = GPIO_IPC_HOST_WAKEUP,
+
+	.modem_net = UMTS_NETWORK,
+	.modem_type = SEC_CMC221,
+	.link_types = LINKTYPE(LINKDEV_DPRAM) | LINKTYPE(LINKDEV_USB),
+	.link_name = "cmc221_idpram",
+	.dpram_ctl = &cmc_idpram_ctrl,
+
+	.num_iodevs = ARRAY_SIZE(umts_io_devices),
+	.iodevs = umts_io_devices,
+
+	.link_pm_data = &umts_link_pm_data,
+
+	.use_handover = true,
+
+	.ipc_version = SIPC_VER_50,
+	.use_mif_log = true,
+};
+
+static struct resource umts_modem_res[] = {
+	[0] = {
+		.name  = "cp_active_irq",
+		.start = LTE_ACTIVE_IRQ,
+		.end   = LTE_ACTIVE_IRQ,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device umts_modem = {
+	.name = "mif_sipc5",
+	.id = 1,
+	.num_resources = ARRAY_SIZE(umts_modem_res),
+	.resource = umts_modem_res,
+	.dev = {
+		.platform_data = &umts_modem_data,
+	},
+};
+
+#define HUB_STATE_OFF 0
+void set_hsic_lpa_states(int states)
+{
+	int val = gpio_get_value(umts_modem_data.gpio_cp_reset);
+
+	mif_trace("\n");
+
+	if (val && states == STATE_HSIC_LPA_ENTER) {
+		mif_info("usb3503: hub off - lpa\n");
+		host_port_enable(2, 0);
+		*(umts_link_pm_data.p_hub_status) = HUB_STATE_OFF;
+	}
+}
+
+int get_cp_active_state(void)
+{
+	return gpio_get_value(umts_modem_data.gpio_phone_active);
+}
+
+static void cmc_idpram_reset(void)
+{
+	iowrite16(1, cmc_sfr.reset);
+}
+
+static void cmc_idpram_setup_speed(enum dpram_speed speed)
+{
+	setup_dpram_speed(cmc_idpram_cfg.csn, &cmc_idpram_access_cfg[speed]);
+}
+
+static int cmc_idpram_wakeup(void)
+{
+	int cnt = 0;
+
+	gpio_set_value(umts_modem_data.gpio_dpram_wakeup, 1);
+
+	while (!gpio_get_value(umts_modem_data.gpio_dpram_status)) {
+		if (cnt++ > 10) {
+			mif_err("ERR: gpio_dpram_status == 0\n");
+			return -EAGAIN;
+		}
+
+		if (in_interrupt())
+			mdelay(1);
+		else
+			msleep_interruptible(1);
+	}
+
+	return 0;
+}
+
+static void cmc_idpram_sleep(void)
+{
+	gpio_set_value(umts_modem_data.gpio_dpram_wakeup, 0);
+}
+
+static void cmc_idpram_clr_intr(void)
+{
+	iowrite16(0xFFFF, cmc_sfr.clr_int2ap);
+	iowrite16(0, cmc_sfr.int2ap);
+}
+
+static u16 cmc_idpram_recv_intr(void)
+{
+	return ioread16(cmc_sfr.int2ap);
+}
+
+static void cmc_idpram_send_intr(u16 irq_mask)
+{
+	iowrite16(irq_mask, cmc_sfr.int2cp);
+}
+
+static u16 cmc_idpram_recv_msg(void)
+{
+	return ioread16(cmc_sfr.msg2ap);
+}
+
+static void cmc_idpram_send_msg(u16 msg)
+{
+	iowrite16(msg, cmc_sfr.msg2cp);
+}
+
+static u16 cmc_idpram_get_magic(void)
+{
+	return ioread16(cmc_ipc_map.magic);
+}
+
+static void cmc_idpram_set_magic(u16 value)
+{
+	iowrite16(value, cmc_ipc_map.magic);
+}
+
+static u16 cmc_idpram_get_access(void)
+{
+	return ioread16(cmc_ipc_map.access);
+}
+
+static void cmc_idpram_set_access(u16 value)
+{
+	iowrite16(value, cmc_ipc_map.access);
+}
+
+static u32 cmc_idpram_get_tx_head(int dev_id)
+{
+	return ioread16(cmc_ipc_map.dev[dev_id].txq.head);
+}
+
+static u32 cmc_idpram_get_tx_tail(int dev_id)
+{
+	return ioread16(cmc_ipc_map.dev[dev_id].txq.tail);
+}
+
+static void cmc_idpram_set_tx_head(int dev_id, u32 head)
+{
+	int cnt = 100;
+	u32 val = 0;
+
+	iowrite16((u16)head, cmc_ipc_map.dev[dev_id].txq.head);
+
+	do {
+		/* Check head value written */
+		val = ioread16(cmc_ipc_map.dev[dev_id].txq.head);
+		if (val == head)
+			break;
+
+		mif_err("ERR: txq.head(%d) != head(%d)\n", val, head);
+
+		/* Write head value again */
+		iowrite16((u16)head, cmc_ipc_map.dev[dev_id].txq.head);
+	} while (cnt--);
+}
+
+static void cmc_idpram_set_tx_tail(int dev_id, u32 tail)
+{
+	int cnt = 100;
+	u32 val = 0;
+
+	iowrite16((u16)tail, cmc_ipc_map.dev[dev_id].txq.tail);
+
+	do {
+		/* Check tail value written */
+		val = ioread16(cmc_ipc_map.dev[dev_id].txq.tail);
+		if (val == tail)
+			break;
+
+		mif_err("ERR: txq.tail(%d) != tail(%d)\n", val, tail);
+
+		/* Write tail value again */
+		iowrite16((u16)tail, cmc_ipc_map.dev[dev_id].txq.tail);
+	} while (cnt--);
+}
+
+static u8 __iomem *cmc_idpram_get_tx_buff(int dev_id)
+{
+	return cmc_ipc_map.dev[dev_id].txq.buff;
+}
+
+static u32 cmc_idpram_get_tx_buff_size(int dev_id)
+{
+	return cmc_ipc_map.dev[dev_id].txq.size;
+}
+
+static u32 cmc_idpram_get_rx_head(int dev_id)
+{
+	return ioread16(cmc_ipc_map.dev[dev_id].rxq.head);
+}
+
+static u32 cmc_idpram_get_rx_tail(int dev_id)
+{
+	return ioread16(cmc_ipc_map.dev[dev_id].rxq.tail);
+}
+
+static void cmc_idpram_set_rx_head(int dev_id, u32 head)
+{
+	int cnt = 100;
+	u32 val = 0;
+
+	iowrite16((u16)head, cmc_ipc_map.dev[dev_id].rxq.head);
+
+	do {
+		/* Check head value written */
+		val = ioread16(cmc_ipc_map.dev[dev_id].rxq.head);
+		if (val == head)
+			break;
+
+		mif_err("ERR: rxq.head(%d) != head(%d)\n", val, head);
+
+		/* Write head value again */
+		iowrite16((u16)head, cmc_ipc_map.dev[dev_id].rxq.head);
+	} while (cnt--);
+}
+
+static void cmc_idpram_set_rx_tail(int dev_id, u32 tail)
+{
+	int cnt = 100;
+	u32 val = 0;
+
+	iowrite16((u16)tail, cmc_ipc_map.dev[dev_id].rxq.tail);
+
+	do {
+		/* Check tail value written */
+		val = ioread16(cmc_ipc_map.dev[dev_id].rxq.tail);
+		if (val == tail)
+			break;
+
+		mif_err("ERR: rxq.tail(%d) != tail(%d)\n", val, tail);
+
+		/* Write tail value again */
+		iowrite16((u16)tail, cmc_ipc_map.dev[dev_id].rxq.tail);
+	} while (cnt--);
+}
+
+static u8 __iomem *cmc_idpram_get_rx_buff(int dev_id)
+{
+	return cmc_ipc_map.dev[dev_id].rxq.buff;
+}
+
+static u32 cmc_idpram_get_rx_buff_size(int dev_id)
+{
+	return cmc_ipc_map.dev[dev_id].rxq.size;
+}
+
+static u16 cmc_idpram_get_mask_req_ack(int dev_id)
+{
+	return cmc_ipc_map.dev[dev_id].mask_req_ack;
+}
+
+static u16 cmc_idpram_get_mask_res_ack(int dev_id)
+{
+	return cmc_ipc_map.dev[dev_id].mask_res_ack;
+}
+
+static u16 cmc_idpram_get_mask_send(int dev_id)
+{
+	return cmc_ipc_map.dev[dev_id].mask_send;
+}
+
+/* Set dynamic environment for a modem */
+static void setup_umts_modem_env(void)
+{
+	/*
+	** Config DPRAM control structure
+	*/
+	if (system_rev == 1 || system_rev >= 4)
+		cmc_idpram_cfg.csn = 0;
+	else
+		cmc_idpram_cfg.csn = 1;
+
+	cmc_idpram_cfg.addr = SROM_CS0_BASE + (SROM_WIDTH * cmc_idpram_cfg.csn);
+	cmc_idpram_cfg.end  = cmc_idpram_cfg.addr + cmc_idpram_cfg.size - 1;
+
+	if (system_rev == 1 || system_rev >= 4) {
+		umts_modem_data.gpio_dpram_int = GPIO_CMC_IDPRAM_INT_01;
+		cmc_idpram_ctrl.dpram_irq = CMC_IDPRAM_INT_IRQ_01;
+	}
+}
+
+static void config_umts_modem_gpio(void)
+{
+	int err;
+	unsigned gpio_cp_on = umts_modem_data.gpio_cp_on;
+	unsigned gpio_cp_rst = umts_modem_data.gpio_cp_reset;
+	unsigned gpio_pda_active = umts_modem_data.gpio_pda_active;
+	unsigned gpio_phone_active = umts_modem_data.gpio_phone_active;
+	unsigned gpio_active_state = umts_modem_data.gpio_host_active;
+	unsigned gpio_host_wakeup = umts_modem_data.gpio_host_wakeup;
+	unsigned gpio_slave_wakeup = umts_modem_data.gpio_slave_wakeup;
+	unsigned gpio_dpram_int = umts_modem_data.gpio_dpram_int;
+	unsigned gpio_dpram_status = umts_modem_data.gpio_dpram_status;
+	unsigned gpio_dpram_wakeup = umts_modem_data.gpio_dpram_wakeup;
+
+	if (gpio_cp_on) {
+		err = gpio_request(gpio_cp_on, "CMC_ON");
+		if (err) {
+			mif_err("ERR: fail to request gpio %s\n", "CMC_ON");
+		} else {
+			gpio_direction_output(gpio_cp_on, 0);
+			s3c_gpio_setpull(gpio_cp_on, S3C_GPIO_PULL_NONE);
+		}
+	}
+
+	if (gpio_cp_rst) {
+		err = gpio_request(gpio_cp_rst, "CMC_RST");
+		if (err) {
+			mif_err("ERR: fail to request gpio %s\n", "CMC_RST");
+		} else {
+			gpio_direction_output(gpio_cp_rst, 0);
+			s3c_gpio_setpull(gpio_cp_rst, S3C_GPIO_PULL_NONE);
+		}
+	}
+
+	if (gpio_pda_active) {
+		err = gpio_request(gpio_pda_active, "PDA_ACTIVE");
+		if (err) {
+			mif_err("ERR: fail to request gpio %s\n", "PDA_ACTIVE");
+		} else {
+			gpio_direction_output(gpio_pda_active, 0);
+			s3c_gpio_setpull(gpio_pda_active, S3C_GPIO_PULL_NONE);
+		}
+	}
+
+	if (gpio_phone_active) {
+		err = gpio_request(gpio_phone_active, "CMC_ACTIVE");
+		if (err) {
+			mif_err("ERR: fail to request gpio %s\n", "CMC_ACTIVE");
+		} else {
+			/* Configure as a wake-up source */
+			gpio_direction_input(gpio_phone_active);
+			s3c_gpio_setpull(gpio_phone_active, S3C_GPIO_PULL_DOWN);
+			s3c_gpio_cfgpin(gpio_phone_active, S3C_GPIO_SFN(0xF));
+		}
+	}
+
+	if (gpio_active_state) {
+		err = gpio_request(gpio_active_state, "CMC_ACTIVE_STATE");
+		if (err) {
+			mif_err("ERR: fail to request gpio %s\n",
+				"CMC_ACTIVE_STATE");
+		} else {
+			gpio_direction_output(gpio_active_state, 0);
+			s3c_gpio_setpull(gpio_active_state, S3C_GPIO_PULL_NONE);
+		}
+	}
+
+	if (gpio_slave_wakeup) {
+		err = gpio_request(gpio_slave_wakeup, "CMC_SLAVE_WAKEUP");
+		if (err) {
+			mif_err("ERR: fail to request gpio %s\n",
+				"CMC_SLAVE_WAKEUP");
+		} else {
+			gpio_direction_output(gpio_slave_wakeup, 0);
+			s3c_gpio_setpull(gpio_slave_wakeup, S3C_GPIO_PULL_NONE);
+		}
+	}
+
+	if (gpio_host_wakeup) {
+		err = gpio_request(gpio_host_wakeup, "CMC_HOST_WAKEUP");
+		if (err) {
+			mif_err("ERR: fail to request gpio %s\n",
+				"CMC_HOST_WAKEUP");
+		} else {
+			/* Configure as a wake-up source */
+			gpio_direction_input(gpio_host_wakeup);
+			s3c_gpio_setpull(gpio_host_wakeup, S3C_GPIO_PULL_DOWN);
+			s3c_gpio_cfgpin(gpio_host_wakeup, S3C_GPIO_SFN(0xF));
+		}
+	}
+
+	if (gpio_dpram_int) {
+		err = gpio_request(gpio_dpram_int, "CMC_DPRAM_INT");
+		if (err) {
+			mif_err("ERR: fail to request gpio %s\n",
+				"CMC_DPRAM_INT");
+		} else {
+			/* Configure as a wake-up source */
+			gpio_direction_input(gpio_dpram_int);
+			s3c_gpio_setpull(gpio_dpram_int, S3C_GPIO_PULL_NONE);
+			s3c_gpio_cfgpin(gpio_dpram_int, S3C_GPIO_SFN(0xF));
+		}
+	}
+
+	if (gpio_dpram_status) {
+		err = gpio_request(gpio_dpram_status, "CMC_DPRAM_STATUS");
+		if (err) {
+			mif_err("ERR: fail to request gpio %s\n",
+				"CMC_DPRAM_STATUS");
+		} else {
+			gpio_direction_input(gpio_dpram_status);
+			s3c_gpio_setpull(gpio_dpram_status, S3C_GPIO_PULL_NONE);
+		}
+	}
+
+	if (gpio_dpram_wakeup) {
+		err = gpio_request(gpio_dpram_wakeup, "CMC_DPRAM_WAKEUP");
+		if (err) {
+			mif_err("ERR: fail to request gpio %s\n",
+				"CMC_DPRAM_WAKEUP");
+		} else {
+			gpio_direction_output(gpio_dpram_wakeup, 1);
+			s3c_gpio_setpull(gpio_dpram_wakeup, S3C_GPIO_PULL_NONE);
+		}
+	}
+}
+
+static u8 *cmc_idpram_remap_mem_region(struct sromc_cfg *cfg)
+{
+	int dp_addr = cfg->addr;
+	int dp_size = cfg->size;
+	u8 __iomem *dp_base;
+	struct dpram_ipc_cfg *ipc_map;
+	struct dpram_ipc_device *dev;
+
+	/* Remap DPRAM memory region */
+	dp_base = (u8 __iomem *)ioremap_nocache(dp_addr, dp_size);
+	if (!dp_base) {
+		mif_err("ERR: ioremap_nocache for dp_base fail\n");
+		return NULL;
+	}
+	mif_err("DPRAM VA=0x%08X\n", (int)dp_base);
+
+	/* Remap DPRAM SFR region */
+	dp_addr += dp_size;
+	cmc_sfr_base = (u8 __iomem *)ioremap_nocache(dp_addr, dp_size);
+	if (cmc_sfr_base == NULL) {
+		iounmap(dp_base);
+		mif_err("ERR: ioremap_nocache for cmc_sfr_base fail\n");
+		return NULL;
+	}
+
+	cmc_sfr.int2cp = (u16 __iomem *)(cmc_sfr_base + CMC_INT2CP_REG);
+	cmc_sfr.int2ap = (u16 __iomem *)(cmc_sfr_base + CMC_INT2AP_REG);
+	cmc_sfr.clr_int2ap = (u16 __iomem *)(cmc_sfr_base + CMC_CLR_INT_REG);
+	cmc_sfr.reset = (u16 __iomem *)(cmc_sfr_base + CMC_RESET_REG);
+	cmc_sfr.msg2cp = (u16 __iomem *)(cmc_sfr_base + CMC_PUT_REG);
+	cmc_sfr.msg2ap = (u16 __iomem *)(cmc_sfr_base + CMC_GET_REG);
+
+	cmc_idpram_ctrl.dp_base = (u8 __iomem *)dp_base;
+	cmc_idpram_ctrl.dp_size = dp_size;
+
+	/* Map for IPC */
+	ipc_map = (struct dpram_ipc_cfg *)dp_base;
+
+	/* Magic code and access enable fields */
+	cmc_ipc_map.magic  = (u16 __iomem *)&ipc_map->magic;
+	cmc_ipc_map.access = (u16 __iomem *)&ipc_map->access;
+
+	/* FMT */
+	dev = &cmc_ipc_map.dev[IPC_FMT];
+
+	strcpy(dev->name, "FMT");
+	dev->id = IPC_FMT;
+
+	dev->txq.head = (u16 __iomem *)&ipc_map->fmt_tx_head;
+	dev->txq.tail = (u16 __iomem *)&ipc_map->fmt_tx_tail;
+	dev->txq.buff = (u8 __iomem *)&ipc_map->fmt_tx_buff[0];
+	dev->txq.size = DP_FMT_TX_BUFF_SZ;
+
+	dev->rxq.head = (u16 __iomem *)&ipc_map->fmt_rx_head;
+	dev->rxq.tail = (u16 __iomem *)&ipc_map->fmt_rx_tail;
+	dev->rxq.buff = (u8 __iomem *)&ipc_map->fmt_rx_buff[0];
+	dev->rxq.size = DP_FMT_RX_BUFF_SZ;
+
+	dev->mask_req_ack = INT_MASK_REQ_ACK_F;
+	dev->mask_res_ack = INT_MASK_RES_ACK_F;
+	dev->mask_send    = INT_MASK_SEND_F;
+
+	/* RAW */
+	dev = &cmc_ipc_map.dev[IPC_RAW];
+
+	strcpy(dev->name, "RAW");
+	dev->id = IPC_RAW;
+
+	dev->txq.head = (u16 __iomem *)&ipc_map->raw_tx_head;
+	dev->txq.tail = (u16 __iomem *)&ipc_map->raw_tx_tail;
+	dev->txq.buff = (u8 __iomem *)&ipc_map->raw_tx_buff[0];
+	dev->txq.size = DP_RAW_TX_BUFF_SZ;
+
+	dev->rxq.head = (u16 __iomem *)&ipc_map->raw_rx_head;
+	dev->rxq.tail = (u16 __iomem *)&ipc_map->raw_rx_tail;
+	dev->rxq.buff = (u8 __iomem *)&ipc_map->raw_rx_buff[0];
+	dev->rxq.size = DP_RAW_RX_BUFF_SZ;
+
+	dev->mask_req_ack = INT_MASK_REQ_ACK_R;
+	dev->mask_res_ack = INT_MASK_RES_ACK_R;
+	dev->mask_send    = INT_MASK_SEND_R;
+
+	return dp_base;
+}
+#endif
+
+#ifdef CONFIG_CDMA_MODEM_CBP72
+static struct sromc_cfg cbp_edpram_cfg = {
+	.attr = SROMC_DATA_16 | SROMC_BYTE_EN,
+	.size = CBP_EDPRAM_SIZE,
+};
+
+static struct sromc_access_cfg cbp_edpram_access_cfg[] = {
+	[DPRAM_SPEED_LOW] = {
+		.tacs = 0x00 << 28,
+		.tcos = 0x00 << 24,
+		.tacc = 0x0F << 16,
+		.tcoh = 0x00 << 12,
+		.tcah = 0x00 << 8,
+		.tacp = 0x00 << 4,
+		.pmc  = 0x00 << 0,
+	},
+};
+
+/*
+	magic_code +
+	access_enable +
+	fmt_tx_head + fmt_tx_tail + fmt_tx_buff +
+	raw_tx_head + raw_tx_tail + raw_tx_buff +
+	fmt_rx_head + fmt_rx_tail + fmt_rx_buff +
+	raw_rx_head + raw_rx_tail + raw_rx_buff +
+	mbx_cp2ap +
+	mbx_ap2cp
+ =	2 +
+	2 +
+	2 + 2 + 1336 +
+	2 + 2 + 4564 +
+	2 + 2 + 1336 +
+	2 + 2 + 9124 +
+	2 +
+	2
+ =	16384
+*/
+
+#define CBP_DP_FMT_TX_BUFF_SZ	1336
+#define CBP_DP_RAW_TX_BUFF_SZ	4564
+#define CBP_DP_FMT_RX_BUFF_SZ	1336
+#define CBP_DP_RAW_RX_BUFF_SZ	9124
+
+#define MAX_CBP_EDPRAM_IPC_DEV	(IPC_RAW + 1)	/* FMT, RAW */
+
+struct cbp_edpram_ipc_cfg {
+	u16 magic;
+	u16 access;
+
+	u16 fmt_tx_head;
+	u16 fmt_tx_tail;
+	u8  fmt_tx_buff[CBP_DP_FMT_TX_BUFF_SZ];
+
+	u16 raw_tx_head;
+	u16 raw_tx_tail;
+	u8  raw_tx_buff[CBP_DP_RAW_TX_BUFF_SZ];
+
+	u16 fmt_rx_head;
+	u16 fmt_rx_tail;
+	u8  fmt_rx_buff[CBP_DP_FMT_RX_BUFF_SZ];
+
+	u16 raw_rx_head;
+	u16 raw_rx_tail;
+	u8  raw_rx_buff[CBP_DP_RAW_RX_BUFF_SZ];
+
+	u16 mbx_cp2ap;
+	u16 mbx_ap2cp;
+};
+
+static struct dpram_ipc_map cbp_ipc_map;
+
+static void cbp_edpram_reset(void);
+static void cbp_edpram_clr_intr(void);
+static u16  cbp_edpram_recv_intr(void);
+static void cbp_edpram_send_intr(u16 irq_mask);
+static u16  cbp_edpram_recv_msg(void);
+static void cbp_edpram_send_msg(u16 msg);
+
+static u16  cbp_edpram_get_magic(void);
+static void cbp_edpram_set_magic(u16 value);
+static u16  cbp_edpram_get_access(void);
+static void cbp_edpram_set_access(u16 value);
+
+static u32  cbp_edpram_get_tx_head(int dev_id);
+static u32  cbp_edpram_get_tx_tail(int dev_id);
+static void cbp_edpram_set_tx_head(int dev_id, u32 head);
+static void cbp_edpram_set_tx_tail(int dev_id, u32 tail);
+static u8 __iomem *cbp_edpram_get_tx_buff(int dev_id);
+static u32  cbp_edpram_get_tx_buff_size(int dev_id);
+
+static u32  cbp_edpram_get_rx_head(int dev_id);
+static u32  cbp_edpram_get_rx_tail(int dev_id);
+static void cbp_edpram_set_rx_head(int dev_id, u32 head);
+static void cbp_edpram_set_rx_tail(int dev_id, u32 tail);
+static u8 __iomem *cbp_edpram_get_rx_buff(int dev_id);
+static u32  cbp_edpram_get_rx_buff_size(int dev_id);
+
+static u16  cbp_edpram_get_mask_req_ack(int dev_id);
+static u16  cbp_edpram_get_mask_res_ack(int dev_id);
+static u16  cbp_edpram_get_mask_send(int dev_id);
+
+static struct modemlink_dpram_control cbp_edpram_ctrl = {
+	.reset      = cbp_edpram_reset,
+
+	.clear_intr = cbp_edpram_clr_intr,
+	.recv_intr  = cbp_edpram_recv_intr,
+	.send_intr  = cbp_edpram_send_intr,
+	.recv_msg   = cbp_edpram_recv_msg,
+	.send_msg   = cbp_edpram_send_msg,
+
+	.get_magic  = cbp_edpram_get_magic,
+	.set_magic  = cbp_edpram_set_magic,
+	.get_access = cbp_edpram_get_access,
+	.set_access = cbp_edpram_set_access,
+
+	.get_tx_head = cbp_edpram_get_tx_head,
+	.get_tx_tail = cbp_edpram_get_tx_tail,
+	.set_tx_head = cbp_edpram_set_tx_head,
+	.set_tx_tail = cbp_edpram_set_tx_tail,
+	.get_tx_buff = cbp_edpram_get_tx_buff,
+	.get_tx_buff_size = cbp_edpram_get_tx_buff_size,
+
+	.get_rx_head = cbp_edpram_get_rx_head,
+	.get_rx_tail = cbp_edpram_get_rx_tail,
+	.set_rx_head = cbp_edpram_set_rx_head,
+	.set_rx_tail = cbp_edpram_set_rx_tail,
+	.get_rx_buff = cbp_edpram_get_rx_buff,
+	.get_rx_buff_size = cbp_edpram_get_rx_buff_size,
+
+	.get_mask_req_ack = cbp_edpram_get_mask_req_ack,
+	.get_mask_res_ack = cbp_edpram_get_mask_res_ack,
+	.get_mask_send    = cbp_edpram_get_mask_send,
+
+	.dp_base = NULL,
+	.dp_size = 0,
+	.dp_type = EXT_DPRAM,
+	.aligned = 1,
+
+	.dpram_irq        = CBP_DPRAM_INT_IRQ_00,
+	.dpram_irq_flags  = (IRQF_NO_SUSPEND | IRQF_TRIGGER_FALLING),
+	.dpram_irq_name   = "CBP72_EDPRAM_IRQ",
+	.dpram_wlock_name = "CBP72_EDPRAM_WLOCK",
+
+	.max_ipc_dev = MAX_CBP_EDPRAM_IPC_DEV,
+};
+
+/*
+** CDMA target platform data
+*/
+static struct modem_io_t cdma_io_devices[] = {
+	[0] = {
+		.name = "cdma_boot0",
+		.id = 0,
+		.format = IPC_BOOT,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[1] = {
+		.name = "cdma_ipc0",
+		.id = 235,
+		.format = IPC_FMT,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[2] = {
+		.name = "cdma_rfs0",
+		.id = 245,
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[3] = {
+		.name = "cdma_multipdp",
+		.id = 0,
+		.format = IPC_MULTI_RAW,
+		.io_type = IODEV_DUMMY,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[4] = {
+		.name = "cdma_rmnet0",
+		.id = 10,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[5] = {
+		.name = "cdma_rmnet1",
+		.id = 11,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[6] = {
+		.name = "cdma_rmnet2",
+		.id = 12,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[7] = {
+		.name = "cdma_rmnet3",
+		.id = 13,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[8] = {
+		.name = "cdma_rmnet4",
+		.id = 7,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[9] = {
+		.name = "cdma_rmnet5", /* DM Port IO device */
+		.id = 26,
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[10] = {
+		.name = "cdma_rmnet6", /* AT CMD IO device */
+		.id = 17,
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[11] = {
+		.name = "cdma_ramdump0",
+		.id = 0,
+		.format = IPC_RAMDUMP,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[12] = {
+		.name = "cdma_cplog",
+		.id = 29,
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+};
+
+static struct modem_data cdma_modem_data = {
+	.name = "cbp7.2",
+
+	.gpio_cp_on        = GPIO_CBP_PMIC_PWRON,
+	.gpio_cp_off       = GPIO_CBP_PS_HOLD_OFF,
+	.gpio_cp_reset     = GPIO_CBP_CP_RST,
+	.gpio_pda_active   = GPIO_PDA_ACTIVE,
+	.gpio_phone_active = GPIO_CBP_PHONE_ACTIVE,
+
+	.gpio_dpram_int = GPIO_CBP_DPRAM_INT_00,
+
+	.modem_net  = CDMA_NETWORK,
+	.modem_type = VIA_CBP72,
+	.link_types = LINKTYPE(LINKDEV_DPRAM),
+	.link_name  = "cbp72_edpram",
+	.dpram_ctl  = &cbp_edpram_ctrl,
+
+	.num_iodevs = ARRAY_SIZE(cdma_io_devices),
+	.iodevs     = cdma_io_devices,
+
+	.use_handover = true,
+
+	.ipc_version = SIPC_VER_50,
+};
+
+static struct resource cdma_modem_res[] = {
+	[0] = {
+		.name  = "cp_active_irq",
+		.start = CBP_PHONE_ACTIVE_IRQ,
+		.end   = CBP_PHONE_ACTIVE_IRQ,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device cdma_modem = {
+	.name = "mif_sipc5",
+	.id = 2,
+	.num_resources = ARRAY_SIZE(cdma_modem_res),
+	.resource = cdma_modem_res,
+	.dev = {
+		.platform_data = &cdma_modem_data,
+	},
+};
+
+static void cbp_edpram_reset(void)
+{
+	return;
+}
+
+static void cbp_edpram_clr_intr(void)
+{
+	ioread16(cbp_ipc_map.mbx_cp2ap);
+}
+
+static u16 cbp_edpram_recv_intr(void)
+{
+	return ioread16(cbp_ipc_map.mbx_cp2ap);
+}
+
+static void cbp_edpram_send_intr(u16 irq_mask)
+{
+	iowrite16(irq_mask, cbp_ipc_map.mbx_ap2cp);
+}
+
+static u16 cbp_edpram_recv_msg(void)
+{
+	return ioread16(cbp_ipc_map.mbx_cp2ap);
+}
+
+static void cbp_edpram_send_msg(u16 msg)
+{
+	iowrite16(msg, cbp_ipc_map.mbx_ap2cp);
+}
+
+static u16 cbp_edpram_get_magic(void)
+{
+	return ioread16(cbp_ipc_map.magic);
+}
+
+static void cbp_edpram_set_magic(u16 value)
+{
+	iowrite16(value, cbp_ipc_map.magic);
+}
+
+static u16 cbp_edpram_get_access(void)
+{
+	return ioread16(cbp_ipc_map.access);
+}
+
+static void cbp_edpram_set_access(u16 value)
+{
+	iowrite16(value, cbp_ipc_map.access);
+}
+
+static u32 cbp_edpram_get_tx_head(int dev_id)
+{
+	return ioread16(cbp_ipc_map.dev[dev_id].txq.head);
+}
+
+static u32 cbp_edpram_get_tx_tail(int dev_id)
+{
+	return ioread16(cbp_ipc_map.dev[dev_id].txq.tail);
+}
+
+static void cbp_edpram_set_tx_head(int dev_id, u32 head)
+{
+	iowrite16((u16)head, cbp_ipc_map.dev[dev_id].txq.head);
+}
+
+static void cbp_edpram_set_tx_tail(int dev_id, u32 tail)
+{
+	iowrite16((u16)tail, cbp_ipc_map.dev[dev_id].txq.tail);
+}
+
+static u8 __iomem *cbp_edpram_get_tx_buff(int dev_id)
+{
+	return cbp_ipc_map.dev[dev_id].txq.buff;
+}
+
+static u32 cbp_edpram_get_tx_buff_size(int dev_id)
+{
+	return cbp_ipc_map.dev[dev_id].txq.size;
+}
+
+static u32 cbp_edpram_get_rx_head(int dev_id)
+{
+	return ioread16(cbp_ipc_map.dev[dev_id].rxq.head);
+}
+
+static u32 cbp_edpram_get_rx_tail(int dev_id)
+{
+	return ioread16(cbp_ipc_map.dev[dev_id].rxq.tail);
+}
+
+static void cbp_edpram_set_rx_head(int dev_id, u32 head)
+{
+	return iowrite16((u16)head, cbp_ipc_map.dev[dev_id].rxq.head);
+}
+
+static void cbp_edpram_set_rx_tail(int dev_id, u32 tail)
+{
+	return iowrite16((u16)tail, cbp_ipc_map.dev[dev_id].rxq.tail);
+}
+
+static u8 __iomem *cbp_edpram_get_rx_buff(int dev_id)
+{
+	return cbp_ipc_map.dev[dev_id].rxq.buff;
+}
+
+static u32 cbp_edpram_get_rx_buff_size(int dev_id)
+{
+	return cbp_ipc_map.dev[dev_id].rxq.size;
+}
+
+static u16 cbp_edpram_get_mask_req_ack(int dev_id)
+{
+	return cbp_ipc_map.dev[dev_id].mask_req_ack;
+}
+
+static u16 cbp_edpram_get_mask_res_ack(int dev_id)
+{
+	return cbp_ipc_map.dev[dev_id].mask_res_ack;
+}
+
+static u16 cbp_edpram_get_mask_send(int dev_id)
+{
+	return cbp_ipc_map.dev[dev_id].mask_send;
+}
+
+/* Set dynamic environment for a modem */
+static void setup_cdma_modem_env(void)
+{
+	/*
+	** Config DPRAM control structure
+	*/
+	if (system_rev == 1 || system_rev >= 4)
+		cbp_edpram_cfg.csn = 1;
+	else
+		cbp_edpram_cfg.csn = 0;
+
+	cbp_edpram_cfg.addr = SROM_CS0_BASE + (SROM_WIDTH * cbp_edpram_cfg.csn);
+	cbp_edpram_cfg.end  = cbp_edpram_cfg.addr + cbp_edpram_cfg.size - 1;
+
+	if (system_rev == 1 || system_rev >= 4) {
+		cdma_modem_data.gpio_dpram_int = GPIO_CBP_DPRAM_INT_01;
+		cbp_edpram_ctrl.dpram_irq = CBP_DPRAM_INT_IRQ_01;
+	}
+}
+
+static void config_cdma_modem_gpio(void)
+{
+	int err;
+	unsigned gpio_boot_sel = GPIO_CBP_BOOT_SEL;
+	unsigned gpio_cp_on = cdma_modem_data.gpio_cp_on;
+	unsigned gpio_cp_off = cdma_modem_data.gpio_cp_off;
+	unsigned gpio_cp_rst = cdma_modem_data.gpio_cp_reset;
+	unsigned gpio_pda_active = cdma_modem_data.gpio_pda_active;
+	unsigned gpio_phone_active = cdma_modem_data.gpio_phone_active;
+	unsigned gpio_dpram_int = cdma_modem_data.gpio_dpram_int;
+
+	pr_info("[MDM] <%s>\n", __func__);
+
+	if (gpio_boot_sel) {
+		err = gpio_request(gpio_boot_sel, "CBP_BOOT_SEL");
+		if (err) {
+			pr_err("fail to request gpio %s\n", "CBP_BOOT_SEL");
+		} else {
+			gpio_direction_output(gpio_boot_sel, 0);
+			s3c_gpio_setpull(gpio_boot_sel, S3C_GPIO_PULL_NONE);
+		}
+	}
+
+	if (gpio_cp_on) {
+		err = gpio_request(gpio_cp_on, "CBP_ON");
+		if (err) {
+			pr_err("fail to request gpio %s\n", "CBP_ON");
+		} else {
+			gpio_direction_output(gpio_cp_on, 0);
+			s3c_gpio_setpull(gpio_cp_on, S3C_GPIO_PULL_NONE);
+		}
+	}
+
+	if (gpio_cp_off) {
+		err = gpio_request(gpio_cp_off, "CBP_OFF");
+		if (err) {
+			pr_err("fail to request gpio %s\n", "CBP_OFF");
+		} else {
+			gpio_direction_output(gpio_cp_off, 1);
+			s3c_gpio_setpull(gpio_cp_off, S3C_GPIO_PULL_NONE);
+		}
+	}
+
+	if (gpio_cp_rst) {
+		err = gpio_request(gpio_cp_rst, "CBP_RST");
+		if (err) {
+			pr_err("fail to request gpio %s\n", "CBP_RST");
+		} else {
+			gpio_direction_output(gpio_cp_rst, 0);
+			s3c_gpio_setpull(gpio_cp_rst, S3C_GPIO_PULL_NONE);
+		}
+	}
+
+	if (gpio_pda_active) {
+		err = gpio_request(gpio_pda_active, "PDA_ACTIVE");
+		if (err) {
+			pr_err("fail to request gpio %s\n", "PDA_ACTIVE");
+		} else {
+			gpio_direction_output(gpio_pda_active, 0);
+			s3c_gpio_setpull(gpio_pda_active, S3C_GPIO_PULL_NONE);
+		}
+	}
+
+	if (gpio_phone_active) {
+		err = gpio_request(gpio_phone_active, "CBP_ACTIVE");
+		if (err) {
+			pr_err("fail to request gpio %s\n", "CBP_ACTIVE");
+		} else {
+			/* Configure as a wake-up source */
+			gpio_direction_input(gpio_phone_active);
+			s3c_gpio_setpull(gpio_phone_active, S3C_GPIO_PULL_NONE);
+			s3c_gpio_cfgpin(gpio_phone_active, S3C_GPIO_SFN(0xF));
+		}
+	}
+
+	if (gpio_dpram_int) {
+		err = gpio_request(gpio_dpram_int, "CBP_DPRAM_INT");
+		if (err) {
+			pr_err("fail to request gpio %s\n", "CBP_DPRAM_INT");
+		} else {
+			/* Configure as a wake-up source */
+			gpio_direction_input(gpio_dpram_int);
+			s3c_gpio_setpull(gpio_dpram_int, S3C_GPIO_PULL_NONE);
+			s3c_gpio_cfgpin(gpio_dpram_int, S3C_GPIO_SFN(0xF));
+		}
+	}
+
+	/* set low unused gpios between AP and CP */
+	err = gpio_request(GPIO_FLM_RXD, "FLM_RXD");
+	if (err)
+		pr_err(LOG_TAG "fail to request gpio %s : %d\n", "FLM_RXD",
+		err);
+	else {
+		gpio_direction_input(GPIO_FLM_RXD);
+		s3c_gpio_setpull(GPIO_FLM_RXD, S3C_GPIO_PULL_UP);
+		s3c_gpio_cfgpin(GPIO_FLM_RXD, S3C_GPIO_SFN(2));
+	}
+
+	err = gpio_request(GPIO_FLM_TXD, "FLM_TXD");
+	if (err)
+		pr_err(LOG_TAG "fail to request gpio %s : %d\n", "FLM_TXD",
+		err);
+	else {
+		gpio_direction_input(GPIO_FLM_TXD);
+		s3c_gpio_setpull(GPIO_FLM_TXD, S3C_GPIO_PULL_NONE);
+		s3c_gpio_cfgpin(GPIO_FLM_TXD, S3C_GPIO_SFN(2));
+	}
+}
+
+static u8 *cbp_edpram_remap_mem_region(struct sromc_cfg *cfg)
+{
+	int			      dp_addr = 0;
+	int			      dp_size = 0;
+	u8 __iomem                   *dp_base = NULL;
+	struct cbp_edpram_ipc_cfg    *ipc_map = NULL;
+	struct dpram_ipc_device *dev = NULL;
+
+	dp_addr = cfg->addr;
+	dp_size = cfg->size;
+	dp_base = (u8 *)ioremap_nocache(dp_addr, dp_size);
+	if (!dp_base) {
+		pr_err("[MDM] <%s> dpram base ioremap fail\n", __func__);
+		return NULL;
+	}
+	pr_info("[MDM] <%s> DPRAM VA=0x%08X\n", __func__, (int)dp_base);
+
+	cbp_edpram_ctrl.dp_base = (u8 __iomem *)dp_base;
+	cbp_edpram_ctrl.dp_size = dp_size;
+
+	/* Map for IPC */
+	ipc_map = (struct cbp_edpram_ipc_cfg *)dp_base;
+
+	/* Magic code and access enable fields */
+	cbp_ipc_map.magic  = (u16 __iomem *)&ipc_map->magic;
+	cbp_ipc_map.access = (u16 __iomem *)&ipc_map->access;
+
+	/* FMT */
+	dev = &cbp_ipc_map.dev[IPC_FMT];
+
+	strcpy(dev->name, "FMT");
+	dev->id = IPC_FMT;
+
+	dev->txq.head = (u16 __iomem *)&ipc_map->fmt_tx_head;
+	dev->txq.tail = (u16 __iomem *)&ipc_map->fmt_tx_tail;
+	dev->txq.buff = (u8 __iomem *)&ipc_map->fmt_tx_buff[0];
+	dev->txq.size = CBP_DP_FMT_TX_BUFF_SZ;
+
+	dev->rxq.head = (u16 __iomem *)&ipc_map->fmt_rx_head;
+	dev->rxq.tail = (u16 __iomem *)&ipc_map->fmt_rx_tail;
+	dev->rxq.buff = (u8 __iomem *)&ipc_map->fmt_rx_buff[0];
+	dev->rxq.size = CBP_DP_FMT_RX_BUFF_SZ;
+
+	dev->mask_req_ack = INT_MASK_REQ_ACK_F;
+	dev->mask_res_ack = INT_MASK_RES_ACK_F;
+	dev->mask_send    = INT_MASK_SEND_F;
+
+	/* RAW */
+	dev = &cbp_ipc_map.dev[IPC_RAW];
+
+	strcpy(dev->name, "RAW");
+	dev->id = IPC_RAW;
+
+	dev->txq.head = (u16 __iomem *)&ipc_map->raw_tx_head;
+	dev->txq.tail = (u16 __iomem *)&ipc_map->raw_tx_tail;
+	dev->txq.buff = (u8 __iomem *)&ipc_map->raw_tx_buff[0];
+	dev->txq.size = CBP_DP_RAW_TX_BUFF_SZ;
+
+	dev->rxq.head = (u16 __iomem *)&ipc_map->raw_rx_head;
+	dev->rxq.tail = (u16 __iomem *)&ipc_map->raw_rx_tail;
+	dev->rxq.buff = (u8 __iomem *)&ipc_map->raw_rx_buff[0];
+	dev->rxq.size = CBP_DP_RAW_RX_BUFF_SZ;
+
+	dev->mask_req_ack = INT_MASK_REQ_ACK_R;
+	dev->mask_res_ack = INT_MASK_RES_ACK_R;
+	dev->mask_send    = INT_MASK_SEND_R;
+
+	/* Mailboxes */
+	cbp_ipc_map.mbx_ap2cp = (u16 __iomem *)&ipc_map->mbx_ap2cp;
+	cbp_ipc_map.mbx_cp2ap = (u16 __iomem *)&ipc_map->mbx_cp2ap;
+
+	return dp_base;
+}
+#endif
+
+/**
+ *	DPRAM GPIO settings
+ *
+ *	SROM_NUM_ADDR_BITS value indicate the address line number or
+ *	the mux/demux dpram type. if you want to set mux mode, define the
+ *	SROM_NUM_ADDR_BITS to zero.
+ *
+ *	for CMC22x
+ *	CMC22x has 16KB + a SFR register address.
+ *	It used 14 bits (13bits for 16KB word address and 1 bit for SFR
+ *	register)
+ */
+static void config_dpram_port_gpio(void)
+{
+	int addr_bits = SROM_NUM_ADDR_BITS;
+
+	mif_info("address line = %d bits\n", addr_bits);
+
+	/*
+	** Config DPRAM address/data GPIO pins
+	*/
+
+	/* Set GPIO for address bus (13 ~ 14 bits) */
+	switch (addr_bits) {
+	case 0:
+		break;
+
+	case 13 ... 14:
+		s3c_gpio_cfgrange_nopull(GPIO_SROM_ADDR_BUS_LOW,
+			EXYNOS4_GPIO_Y3_NR, S3C_GPIO_SFN(2));
+		s3c_gpio_cfgrange_nopull(GPIO_SROM_ADDR_BUS_HIGH,
+			(addr_bits - EXYNOS4_GPIO_Y3_NR), S3C_GPIO_SFN(2));
+		break;
+
+	default:
+		mif_err("ERR: invalid addr_bits!!!\n");
+		return;
+	}
+
+	/* Set GPIO for data bus (16 bits) */
+	s3c_gpio_cfgrange_nopull(GPIO_SROM_DATA_BUS_LOW, 8, S3C_GPIO_SFN(2));
+	s3c_gpio_cfgrange_nopull(GPIO_SROM_DATA_BUS_HIGH, 8, S3C_GPIO_SFN(2));
+
+	/* Setup SROMC CSn pins */
+	s3c_gpio_cfgpin(GPIO_DPRAM_CSN0, S3C_GPIO_SFN(2));
+	s3c_gpio_cfgpin((GPIO_DPRAM_CSN0 + 1), S3C_GPIO_SFN(2));
+
+	/* Config OEn, WEn */
+	s3c_gpio_cfgpin(GPIO_DPRAM_REN, S3C_GPIO_SFN(2));
+	s3c_gpio_cfgpin(GPIO_DPRAM_WEN, S3C_GPIO_SFN(2));
+
+	/* Config LBn, UBn */
+	s3c_gpio_cfgpin(GPIO_DPRAM_LBN, S3C_GPIO_SFN(2));
+	s3c_gpio_cfgpin(GPIO_DPRAM_UBN, S3C_GPIO_SFN(2));
+}
+
+static void init_sromc(void)
+{
+	struct clk *clk = NULL;
+
+	/* SROMC clk enable */
+	clk = clk_get(NULL, "sromc");
+	if (!clk) {
+		mif_err("ERR: SROMC clock gate fail\n");
+		return;
+	}
+	clk_enable(clk);
+}
+
+static void setup_sromc
+(
+	unsigned csn,
+	struct sromc_cfg *cfg,
+	struct sromc_access_cfg *acc_cfg
+)
+{
+	unsigned bw = 0;	/* Bus width and wait control	*/
+	unsigned bc = 0;	/* Vank control			*/
+	void __iomem *bank_sfr = S5P_SROM_BC0 + (4 * csn);
+
+	mif_err("SROMC settings for CS%d...\n", csn);
+
+	bw = __raw_readl(S5P_SROM_BW);
+	bc = __raw_readl(bank_sfr);
+	mif_err("Old SROMC settings = BW(0x%08X) BC%d(0x%08X)\n", bw, csn, bc);
+
+	/* Set the BW control field for the CSn */
+	bw &= ~(SROMC_MASK << (csn << 2));
+	bw |= (cfg->attr << (csn << 2));
+	writel(bw, S5P_SROM_BW);
+
+	/* Set SROMC memory access timing for the CSn */
+	bc = acc_cfg->tacs | acc_cfg->tcos | acc_cfg->tacc |
+	     acc_cfg->tcoh | acc_cfg->tcah | acc_cfg->tacp | acc_cfg->pmc;
+
+	writel(bc, bank_sfr);
+
+	/* Verify SROMC settings */
+	bw = __raw_readl(S5P_SROM_BW);
+	bc = __raw_readl(bank_sfr);
+	mif_err("New SROMC settings = BW(0x%08X) BC%d(0x%08X)\n", bw, csn, bc);
+}
+
+static void setup_dpram_speed(unsigned csn, struct sromc_access_cfg *acc_cfg)
+{
+	void __iomem *bank_sfr = S5P_SROM_BC0 + (4 * csn);
+	unsigned bc = 0;
+
+	bc = __raw_readl(bank_sfr);
+	mif_info("Old CS%d setting = 0x%08X\n", csn, bc);
+
+	/* SROMC memory access timing setting */
+	bc = acc_cfg->tacs | acc_cfg->tcos | acc_cfg->tacc |
+	     acc_cfg->tcoh | acc_cfg->tcah | acc_cfg->tacp | acc_cfg->pmc;
+	writel(bc, bank_sfr);
+
+	bc = __raw_readl(bank_sfr);
+	mif_info("New CS%d setting = 0x%08X\n", csn, bc);
+}
+
+static int __init init_modem(void)
+{
+	struct sromc_cfg *cfg = NULL;
+	struct sromc_access_cfg *acc_cfg = NULL;
+
+	mif_err("System Revision = %d\n", system_rev);
+
+	setup_umts_modem_env();
+	setup_cdma_modem_env();
+
+	config_dpram_port_gpio();
+
+	config_umts_modem_gpio();
+	config_cdma_modem_gpio();
+
+	init_sromc();
+
+	cfg = &cmc_idpram_cfg;
+	acc_cfg = &cmc_idpram_access_cfg[DPRAM_SPEED_LOW];
+	setup_sromc(cfg->csn, cfg, acc_cfg);
+
+	cfg = &cbp_edpram_cfg;
+	acc_cfg = &cbp_edpram_access_cfg[DPRAM_SPEED_LOW];
+	setup_sromc(cfg->csn, cfg, acc_cfg);
+
+	if (!cmc_idpram_remap_mem_region(&cmc_idpram_cfg))
+		return -1;
+	platform_device_register(&umts_modem);
+
+	if (!cbp_edpram_remap_mem_region(&cbp_edpram_cfg))
+		return -1;
+	platform_device_register(&cdma_modem);
+
+	return 0;
+}
+late_initcall(init_modem);
+/*device_initcall(init_modem);*/
+
+#ifdef CONFIG_USBHUB_USB3503
+static int (*usbhub_set_mode)(struct usb3503_hubctl *, int);
+static struct usb3503_hubctl *usbhub_ctl;
+
+#ifdef CONFIG_EXYNOS4_CPUFREQ
+static int exynos_cpu_frequency_lock(void)
+{
+	unsigned int level, freq = 700;
+
+	if (atomic_read(&umts_link_pm_data.freqlock) == 0) {
+		if (exynos_cpufreq_get_level(freq * 1000, &level)) {
+			mif_err("ERR: exynos_cpufreq_get_level fail\n");
+			return -EINVAL;
+		}
+
+		if (exynos_cpufreq_lock(DVFS_LOCK_ID_USB_IF, level)) {
+			mif_err("ERR: exynos_cpufreq_lock fail\n");
+			return -EINVAL;
+		}
+
+		atomic_set(&umts_link_pm_data.freqlock, 1);
+		mif_debug("<%d> %d MHz\n", level, freq);
+	}
+	return 0;
+}
+
+static int exynos_cpu_frequency_unlock(void)
+{
+	if (atomic_read(&umts_link_pm_data.freqlock) == 1) {
+		exynos_cpufreq_lock_free(DVFS_LOCK_ID_USB_IF);
+		atomic_set(&umts_link_pm_data.freqlock, 0);
+		mif_debug("\n");
+	}
+	return 0;
+}
+#else
+static int exynos_cpu_frequency_lock(void)
+{
+	return 0;
+}
+
+static int exynos_cpu_frequency_unlock(void)
+{
+	return 0;
+}
+#endif
+
+void set_host_states(struct platform_device *pdev, int type)
+{
+}
+
+static int usb3503_hub_handler(void (*set_mode)(void), void *ctl)
+{
+	if (!set_mode || !ctl)
+		return -EINVAL;
+
+	usbhub_set_mode = (int (*)(struct usb3503_hubctl *, int))set_mode;
+	usbhub_ctl = (struct usb3503_hubctl *)ctl;
+
+	mif_info("set_mode(%pF)\n", set_mode);
+
+	return 0;
+}
+
+static int usb3503_hw_config(void)
+{
+	int err;
+
+	err = gpio_request(GPIO_USB_HUB_RST, "HUB_RST");
+	if (err) {
+		mif_err("ERR: fail to request gpio %s\n", "HUB_RST");
+	} else {
+		gpio_direction_output(GPIO_USB_HUB_RST, 0);
+		s3c_gpio_setpull(GPIO_USB_HUB_RST, S3C_GPIO_PULL_NONE);
+	}
+	s5p_gpio_set_drvstr(GPIO_USB_HUB_RST, S5P_GPIO_DRVSTR_LV1);
+	/* need to check drvstr 1 or 2 */
+
+	/* for USB3503 26Mhz Reference clock setting */
+	err = gpio_request(GPIO_USB_HUB_INT, "HUB_INT");
+	if (err) {
+		mif_err("ERR: fail to request gpio %s\n", "HUB_INT");
+	} else {
+		gpio_direction_output(GPIO_USB_HUB_INT, 1);
+		s3c_gpio_setpull(GPIO_USB_HUB_INT, S3C_GPIO_PULL_NONE);
+	}
+
+	return 0;
+}
+
+static int usb3503_reset_n(int val)
+{
+	gpio_set_value(GPIO_USB_HUB_RST, 0);
+
+	/* hub off from cpuidle(LPA), skip the msleep schedule*/
+	if (val) {
+		msleep(20);
+		mif_info("val = %d\n", gpio_get_value(GPIO_USB_HUB_RST));
+
+		gpio_set_value(GPIO_USB_HUB_RST, !!val);
+
+		mif_info("val = %d\n", gpio_get_value(GPIO_USB_HUB_RST));
+		udelay(5); /* need it ?*/
+	}
+	return 0;
+}
+
+static struct usb3503_platform_data usb3503_pdata = {
+	.initial_mode = USB3503_MODE_STANDBY,
+	.reset_n = usb3503_reset_n,
+	.register_hub_handler = usb3503_hub_handler,
+	.port_enable = host_port_enable,
+};
+
+static struct i2c_board_info i2c_devs20_emul[] __initdata = {
+	{
+		I2C_BOARD_INFO(USB3503_I2C_NAME, 0x08),
+		.platform_data = &usb3503_pdata,
+	},
+};
+
+/* I2C20_EMUL */
+static struct i2c_gpio_platform_data i2c20_platdata = {
+	.sda_pin = GPIO_USB_HUB_SDA,
+	.scl_pin = GPIO_USB_HUB_SCL,
+	/*FIXME: need to timming tunning...  */
+	.udelay	= 20,
+};
+
+static struct platform_device s3c_device_i2c20 = {
+	.name = "i2c-gpio",
+	.id = 20,
+	.dev.platform_data = &i2c20_platdata,
+};
+
+static int __init init_usbhub(void)
+{
+	usb3503_hw_config();
+	i2c_register_board_info(20, i2c_devs20_emul,
+				ARRAY_SIZE(i2c_devs20_emul));
+
+	platform_device_register(&s3c_device_i2c20);
+	return 0;
+}
+
+device_initcall(init_usbhub);
+
+static int host_port_enable(int port, int enable)
+{
+	int err;
+
+	mif_info("port(%d) control(%d)\n", port, enable);
+
+	if (enable) {
+		err = usbhub_set_mode(usbhub_ctl, USB3503_MODE_HUB);
+		if (err < 0) {
+			mif_err("ERR: hub on fail\n");
+			goto exit;
+		}
+		err = s5p_ehci_port_control(&s5p_device_ehci, port, 1);
+		if (err < 0) {
+			mif_err("ERR: port(%d) enable fail\n", port);
+			goto exit;
+		}
+	} else {
+		err = s5p_ehci_port_control(&s5p_device_ehci, port, 0);
+		if (err < 0) {
+			mif_err("ERR: port(%d) enable fail\n", port);
+			goto exit;
+		}
+		err = usbhub_set_mode(usbhub_ctl, USB3503_MODE_STANDBY);
+		if (err < 0) {
+			mif_err("ERR: hub off fail\n");
+			goto exit;
+		}
+	}
+
+	err = gpio_direction_output(umts_modem_data.gpio_host_active, enable);
+	mif_info("active state err(%d), en(%d), level(%d)\n",
+		err, enable, gpio_get_value(umts_modem_data.gpio_host_active));
+
+exit:
+	return err;
+}
+#else
+void set_host_states(struct platform_device *pdev, int type)
+{
+	if (active_ctl.gpio_initialized) {
+		mif_err("<%s> Active States =%d, %s\n", pdev->name, type);
+		gpio_direction_output(umts_link_pm_data.gpio_link_active, type);
+	} else {
+		active_ctl.gpio_request_host_active = 1;
+	}
+}
+#endif
+
diff --git a/arch/arm/mach-exynos/board-c1vzw-modems.c b/arch/arm/mach-exynos/board-c1vzw-modems.c
new file mode 100644
index 0000000..6eb0509
--- /dev/null
+++ b/arch/arm/mach-exynos/board-c1vzw-modems.c
@@ -0,0 +1,1930 @@
+/* linux/arch/arm/mach-xxxx/board-c1vzw-modems.c
+ * Copyright (C) 2010 Samsung Electronics. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/regulator/consumer.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+
+/* inlcude platform specific file */
+#include <linux/platform_data/modem.h>
+#include <mach/sec_modem.h>
+#include <mach/gpio.h>
+#include <mach/gpio-exynos4.h>
+#include <plat/gpio-cfg.h>
+#include <mach/regs-mem.h>
+#include <plat/regs-srom.h>
+
+#ifdef CONFIG_USBHUB_USB3503
+#include <linux/i2c.h>
+#include <linux/i2c-gpio.h>
+#include <linux/platform_data/usb3503.h>
+#include <mach/cpufreq.h>
+#include <plat/usb-phy.h>
+#endif
+#include <plat/devs.h>
+#include <plat/ehci.h>
+
+#define SROM_CS0_BASE		0x04000000
+#define SROM_WIDTH		0x01000000
+#define SROM_NUM_ADDR_BITS	14
+
+/* For "bus width and wait control (BW)" register */
+enum sromc_attr {
+	SROMC_DATA_16   = 0x1,	/* 16-bit data bus	*/
+	SROMC_BYTE_ADDR = 0x2,	/* Byte base address	*/
+	SROMC_WAIT_EN   = 0x4,	/* Wait enabled		*/
+	SROMC_BYTE_EN   = 0x8,	/* Byte access enabled	*/
+	SROMC_MASK      = 0xF
+};
+
+/* DPRAM configuration */
+struct sromc_cfg {
+	enum sromc_attr attr;
+	unsigned size;
+	unsigned csn;		/* CSn #			*/
+	unsigned addr;		/* Start address (physical)	*/
+	unsigned end;		/* End address (physical)	*/
+};
+
+/* DPRAM access timing configuration */
+struct sromc_access_cfg {
+	u32 tacs;		/* Address set-up before CSn		*/
+	u32 tcos;		/* Chip selection set-up before OEn	*/
+	u32 tacc;		/* Access cycle				*/
+	u32 tcoh;		/* Chip selection hold on OEn		*/
+	u32 tcah;		/* Address holding time after CSn	*/
+	u32 tacp;		/* Page mode access cycle at Page mode	*/
+	u32 pmc;		/* Page Mode config			*/
+};
+
+/* For CMC221 IDPRAM (Internal DPRAM) */
+#define CMC_IDPRAM_SIZE		0x4000	/* 16 KB */
+
+/* FOR CMC221 SFR for IDPRAM */
+#define CMC_INT2CP_REG		0x10	/* Interrupt to CP            */
+#define CMC_INT2AP_REG		0x50
+#define CMC_CLR_INT_REG		0x28	/* Clear Interrupt to AP      */
+#define CMC_RESET_REG		0x3C
+#define CMC_PUT_REG		0x40	/* AP->CP reg for hostbooting */
+#define CMC_GET_REG		0x50	/* CP->AP reg for hostbooting */
+
+/* For CBP7.2 EDPRAM (External DPRAM) */
+#define CBP_EDPRAM_SIZE		0x4000	/* 16 KB */
+
+#define INT_MASK_REQ_ACK_F	0x0020
+#define INT_MASK_REQ_ACK_R	0x0010
+#define INT_MASK_RES_ACK_F	0x0008
+#define INT_MASK_RES_ACK_R	0x0004
+#define INT_MASK_SEND_F		0x0002
+#define INT_MASK_SEND_R		0x0001
+
+#define INT_MASK_REQ_ACK_RFS	0x0400 /* Request RES_ACK_RFS		*/
+#define INT_MASK_RES_ACK_RFS	0x0200 /* Response of REQ_ACK_RFS	*/
+#define INT_MASK_SEND_RFS	0x0100 /* Indicate sending RFS data	*/
+
+
+/* Function prototypes */
+static void config_dpram_port_gpio(void);
+static void init_sromc(void);
+static void setup_sromc(unsigned csn, struct sromc_cfg *cfg,
+		struct sromc_access_cfg *acc_cfg);
+static void setup_dpram_speed(unsigned csn, struct sromc_access_cfg *acc_cfg);
+static int __init init_modem(void);
+
+#ifdef CONFIG_USBHUB_USB3503
+static int host_port_enable(int port, int enable);
+#else
+static int host_port_enable(int port, int enable)
+{
+	return s5p_ehci_port_control(&s5p_device_ehci, port, enable);
+}
+#endif
+
+#ifdef CONFIG_LTE_MODEM_CMC221
+static struct sromc_cfg cmc_idpram_cfg = {
+	.attr = SROMC_DATA_16,
+	.size = CMC_IDPRAM_SIZE,
+};
+
+static struct sromc_access_cfg cmc_idpram_access_cfg[] = {
+	[DPRAM_SPEED_LOW] = {
+		/* for 33 MHz clock, 64 cycles */
+		.tacs = 0x08 << 28,
+		.tcos = 0x08 << 24,
+		.tacc = 0x1F << 16,
+		.tcoh = 0x08 << 12,
+		.tcah = 0x08 << 8,
+		.tacp = 0x00 << 4,
+		.pmc  = 0x00 << 0,
+	},
+	[DPRAM_SPEED_MID] = {
+		/* for 66 MHz clock, 32 cycles */
+		.tacs = 0x01 << 28,
+		.tcos = 0x01 << 24,
+		.tacc = 0x1B << 16,
+		.tcoh = 0x01 << 12,
+		.tcah = 0x01 << 8,
+		.tacp = 0x00 << 4,
+		.pmc  = 0x00 << 0,
+	},
+	[DPRAM_SPEED_HIGH] = {
+		/* for 133 MHz clock, 16 cycles */
+		.tacs = 0x01 << 28,
+		.tcos = 0x01 << 24,
+		.tacc = 0x0B << 16,
+		.tcoh = 0x01 << 12,
+		.tcah = 0x01 << 8,
+		.tacp = 0x00 << 4,
+		.pmc  = 0x00 << 0,
+	},
+};
+
+/*
+	magic_code +
+	access_enable +
+	fmt_tx_head + fmt_tx_tail + fmt_tx_buff +
+	raw_tx_head + raw_tx_tail + raw_tx_buff +
+	fmt_rx_head + fmt_rx_tail + fmt_rx_buff +
+	raw_rx_head + raw_rx_tail + raw_rx_buff +
+	mbx_cp2ap +
+	mbx_ap2cp
+ =	2 +
+	2 +
+	2 + 2 + 1336 +
+	2 + 2 + 4564 +
+	2 + 2 + 1336 +
+	2 + 2 + 9124 +
+	2 +
+	2
+ =	16384
+*/
+
+#define DP_FMT_TX_BUFF_SZ	1336
+#define DP_RAW_TX_BUFF_SZ	4564
+#define DP_FMT_RX_BUFF_SZ	1336
+#define DP_RAW_RX_BUFF_SZ	9124
+
+#define MAX_CMC_IDPRAM_IPC_DEV	(IPC_RAW + 1)	/* FMT, RAW */
+
+struct dpram_ipc_cfg {
+	u16 magic;
+	u16 access;
+
+	u16 fmt_tx_head;
+	u16 fmt_tx_tail;
+	u8  fmt_tx_buff[DP_FMT_TX_BUFF_SZ];
+
+	u16 raw_tx_head;
+	u16 raw_tx_tail;
+	u8  raw_tx_buff[DP_RAW_TX_BUFF_SZ];
+
+	u16 fmt_rx_head;
+	u16 fmt_rx_tail;
+	u8  fmt_rx_buff[DP_FMT_RX_BUFF_SZ];
+
+	u16 raw_rx_head;
+	u16 raw_rx_tail;
+	u8  raw_rx_buff[DP_RAW_RX_BUFF_SZ];
+
+	u16 mbx_cp2ap;
+	u16 mbx_ap2cp;
+};
+
+struct cmc221_idpram_sfr {
+	u16 __iomem *int2cp;
+	u16 __iomem *int2ap;
+	u16 __iomem *clr_int2ap;
+	u16 __iomem *reset;
+	u16 __iomem *msg2cp;
+	u16 __iomem *msg2ap;
+};
+
+static struct dpram_ipc_map cmc_ipc_map;
+static u8 *cmc_sfr_base;
+static struct cmc221_idpram_sfr cmc_sfr;
+
+/* Function prototypes */
+static void cmc_idpram_reset(void);
+static void cmc_idpram_setup_speed(enum dpram_speed);
+static int  cmc_idpram_wakeup(void);
+static void cmc_idpram_sleep(void);
+static void cmc_idpram_clr_intr(void);
+static u16  cmc_idpram_recv_intr(void);
+static void cmc_idpram_send_intr(u16 irq_mask);
+static u16  cmc_idpram_recv_msg(void);
+static void cmc_idpram_send_msg(u16 msg);
+
+static u16  cmc_idpram_get_magic(void);
+static void cmc_idpram_set_magic(u16 value);
+static u16  cmc_idpram_get_access(void);
+static void cmc_idpram_set_access(u16 value);
+
+static u32  cmc_idpram_get_tx_head(int dev_id);
+static u32  cmc_idpram_get_tx_tail(int dev_id);
+static void cmc_idpram_set_tx_head(int dev_id, u32 head);
+static void cmc_idpram_set_tx_tail(int dev_id, u32 tail);
+static u8 __iomem *cmc_idpram_get_tx_buff(int dev_id);
+static u32  cmc_idpram_get_tx_buff_size(int dev_id);
+
+static u32  cmc_idpram_get_rx_head(int dev_id);
+static u32  cmc_idpram_get_rx_tail(int dev_id);
+static void cmc_idpram_set_rx_head(int dev_id, u32 head);
+static void cmc_idpram_set_rx_tail(int dev_id, u32 tail);
+static u8 __iomem *cmc_idpram_get_rx_buff(int dev_id);
+static u32  cmc_idpram_get_rx_buff_size(int dev_id);
+
+static u16  cmc_idpram_get_mask_req_ack(int dev_id);
+static u16  cmc_idpram_get_mask_res_ack(int dev_id);
+static u16  cmc_idpram_get_mask_send(int dev_id);
+
+static struct modemlink_dpram_control cmc_idpram_ctrl = {
+	.reset = cmc_idpram_reset,
+
+	.setup_speed = cmc_idpram_setup_speed,
+
+	.wakeup = cmc_idpram_wakeup,
+	.sleep  = cmc_idpram_sleep,
+
+	.clear_intr = cmc_idpram_clr_intr,
+	.recv_intr  = cmc_idpram_recv_intr,
+	.send_intr  = cmc_idpram_send_intr,
+	.recv_msg   = cmc_idpram_recv_msg,
+	.send_msg   = cmc_idpram_send_msg,
+
+	.get_magic  = cmc_idpram_get_magic,
+	.set_magic  = cmc_idpram_set_magic,
+	.get_access = cmc_idpram_get_access,
+	.set_access = cmc_idpram_set_access,
+
+	.get_tx_head = cmc_idpram_get_tx_head,
+	.get_tx_tail = cmc_idpram_get_tx_tail,
+	.set_tx_head = cmc_idpram_set_tx_head,
+	.set_tx_tail = cmc_idpram_set_tx_tail,
+	.get_tx_buff = cmc_idpram_get_tx_buff,
+	.get_tx_buff_size = cmc_idpram_get_tx_buff_size,
+
+	.get_rx_head = cmc_idpram_get_rx_head,
+	.get_rx_tail = cmc_idpram_get_rx_tail,
+	.set_rx_head = cmc_idpram_set_rx_head,
+	.set_rx_tail = cmc_idpram_set_rx_tail,
+	.get_rx_buff = cmc_idpram_get_rx_buff,
+	.get_rx_buff_size = cmc_idpram_get_rx_buff_size,
+
+	.get_mask_req_ack = cmc_idpram_get_mask_req_ack,
+	.get_mask_res_ack = cmc_idpram_get_mask_res_ack,
+	.get_mask_send    = cmc_idpram_get_mask_send,
+
+	.dp_base = NULL,
+	.dp_size = 0,
+	.dp_type = CP_IDPRAM,
+	.aligned = 1,
+
+	.dpram_irq = CMC_IDPRAM_INT_IRQ_00,
+	.dpram_irq_flags = (IRQF_NO_SUSPEND | IRQF_TRIGGER_RISING),
+	.dpram_irq_name = "CMC221_IDPRAM_IRQ",
+	.dpram_wlock_name = "CMC221_IDPRAM_WLOCK",
+
+	.max_ipc_dev = MAX_CMC_IDPRAM_IPC_DEV,
+};
+
+/*
+** UMTS target platform data
+*/
+static struct modem_io_t umts_io_devices[] = {
+	[0] = {
+		.name = "umts_boot0",
+		.id = 0,
+		.format = IPC_BOOT,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[1] = {
+		.name = "umts_ipc0",
+		.id = 235,
+		.format = IPC_FMT,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[2] = {
+		.name = "umts_rfs0",
+		.id = 245,
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[3] = {
+		.name = "lte_multipdp",
+		.id = 0,
+		.format = IPC_MULTI_RAW,
+		.io_type = IODEV_DUMMY,
+		.links = LINKTYPE(LINKDEV_DPRAM) | LINKTYPE(LINKDEV_USB),
+		.tx_link = LINKDEV_DPRAM,
+	},
+	[4] = {
+		.name = "lte_rmnet0",
+		.id = 10,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_DPRAM) | LINKTYPE(LINKDEV_USB),
+		.tx_link = LINKDEV_DPRAM,
+	},
+	[5] = {
+		.name = "lte_rmnet1",
+		.id = 11,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_DPRAM) | LINKTYPE(LINKDEV_USB),
+		.tx_link = LINKDEV_DPRAM,
+	},
+	[6] = {
+		.name = "lte_rmnet2",
+		.id = 12,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_DPRAM) | LINKTYPE(LINKDEV_USB),
+		.tx_link = LINKDEV_DPRAM,
+	},
+	[7] = {
+		.name = "lte_rmnet3",
+		.id = 13,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_DPRAM) | LINKTYPE(LINKDEV_USB),
+		.tx_link = LINKDEV_DPRAM,
+	},
+	[8] = {
+		.name = "umts_csd",	/* CS Video Telephony */
+		.id = 1,
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[9] = {
+		.name = "umts_router",	/* AT Iface & Dial-up */
+		.id = 25,
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[10] = {
+		.name = "umts_dm0",	/* DM Port */
+		.id = 28,
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[11] = {
+		.name = "umts_loopback_ap2cp",
+		.id = 30,
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[12] = {
+		.name = "umts_loopback_cp2ap",
+		.id = 31,
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[13] = {
+		.name = "umts_ramdump0",
+		.id = 0,
+		.format = IPC_RAMDUMP,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[14] = {
+		.name = "lte_ipc0",
+		.id = 235,
+		.format = IPC_FMT,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_USB),
+	},
+};
+
+static int exynos_cpu_frequency_lock(void);
+static int exynos_cpu_frequency_unlock(void);
+
+static struct modemlink_pm_data umts_link_pm_data = {
+	.name = "umts_link_pm",
+
+	.gpio_link_enable    = 0,
+	.gpio_link_active    = GPIO_ACTIVE_STATE,
+	.gpio_link_hostwake  = GPIO_IPC_HOST_WAKEUP,
+	.gpio_link_slavewake = GPIO_IPC_SLAVE_WAKEUP,
+
+	.port_enable = host_port_enable,
+/*
+	.link_reconnect = umts_link_reconnect,
+*/
+	.freqlock = ATOMIC_INIT(0),
+	.cpufreq_lock = exynos_cpu_frequency_lock,
+	.cpufreq_unlock = exynos_cpu_frequency_unlock,
+
+	.autosuspend_delay_ms = 2000,
+
+	.has_usbhub = true,
+};
+
+static struct modem_data umts_modem_data = {
+	.name = "cmc221",
+
+	.gpio_cp_on = CP_CMC221_PMIC_PWRON,
+	.gpio_cp_reset = CP_CMC221_CPU_RST,
+	.gpio_phone_active = GPIO_LTE_ACTIVE,
+
+	.gpio_dpram_int = GPIO_CMC_IDPRAM_INT_00,
+	.gpio_dpram_status = GPIO_CMC_IDPRAM_STATUS,
+	.gpio_dpram_wakeup = GPIO_CMC_IDPRAM_WAKEUP,
+
+	.gpio_slave_wakeup = GPIO_IPC_SLAVE_WAKEUP,
+	.gpio_host_active = GPIO_ACTIVE_STATE,
+	.gpio_host_wakeup = GPIO_IPC_HOST_WAKEUP,
+
+	.modem_net = UMTS_NETWORK,
+	.modem_type = SEC_CMC221,
+	.link_types = LINKTYPE(LINKDEV_DPRAM) | LINKTYPE(LINKDEV_USB),
+	.link_name = "cmc221_idpram",
+	.dpram_ctl = &cmc_idpram_ctrl,
+
+	.num_iodevs = ARRAY_SIZE(umts_io_devices),
+	.iodevs = umts_io_devices,
+
+	.link_pm_data = &umts_link_pm_data,
+
+	.use_handover = true,
+
+	.ipc_version = SIPC_VER_50,
+	.use_mif_log = true,
+};
+
+static struct resource umts_modem_res[] = {
+	[0] = {
+		.name  = "cp_active_irq",
+		.start = LTE_ACTIVE_IRQ,
+		.end   = LTE_ACTIVE_IRQ,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device umts_modem = {
+	.name = "mif_sipc5",
+	.id = 1,
+	.num_resources = ARRAY_SIZE(umts_modem_res),
+	.resource = umts_modem_res,
+	.dev = {
+		.platform_data = &umts_modem_data,
+	},
+};
+
+#define HUB_STATE_OFF 0
+void set_hsic_lpa_states(int states)
+{
+	int val = gpio_get_value(umts_modem_data.gpio_cp_reset);
+
+	mif_trace("\n");
+
+	if (val && states == STATE_HSIC_LPA_ENTER) {
+		mif_info("usb3503: hub off - lpa\n");
+		host_port_enable(2, 0);
+		*(umts_link_pm_data.p_hub_status) = HUB_STATE_OFF;
+	}
+}
+
+int get_cp_active_state(void)
+{
+	return gpio_get_value(umts_modem_data.gpio_phone_active);
+}
+
+static void cmc_idpram_reset(void)
+{
+	iowrite16(1, cmc_sfr.reset);
+}
+
+static void cmc_idpram_setup_speed(enum dpram_speed speed)
+{
+	setup_dpram_speed(cmc_idpram_cfg.csn, &cmc_idpram_access_cfg[speed]);
+}
+
+static int cmc_idpram_wakeup(void)
+{
+	int cnt = 0;
+
+	gpio_set_value(umts_modem_data.gpio_dpram_wakeup, 1);
+
+	while (!gpio_get_value(umts_modem_data.gpio_dpram_status)) {
+		if (cnt++ > 10) {
+			mif_err("ERR: gpio_dpram_status == 0\n");
+			return -EAGAIN;
+		}
+
+		if (in_interrupt())
+			mdelay(1);
+		else
+			msleep_interruptible(1);
+	}
+
+	return 0;
+}
+
+static void cmc_idpram_sleep(void)
+{
+	gpio_set_value(umts_modem_data.gpio_dpram_wakeup, 0);
+}
+
+static void cmc_idpram_clr_intr(void)
+{
+	iowrite16(0xFFFF, cmc_sfr.clr_int2ap);
+	iowrite16(0, cmc_sfr.int2ap);
+}
+
+static u16 cmc_idpram_recv_intr(void)
+{
+	return ioread16(cmc_sfr.int2ap);
+}
+
+static void cmc_idpram_send_intr(u16 irq_mask)
+{
+	iowrite16(irq_mask, cmc_sfr.int2cp);
+}
+
+static u16 cmc_idpram_recv_msg(void)
+{
+	return ioread16(cmc_sfr.msg2ap);
+}
+
+static void cmc_idpram_send_msg(u16 msg)
+{
+	iowrite16(msg, cmc_sfr.msg2cp);
+}
+
+static u16 cmc_idpram_get_magic(void)
+{
+	return ioread16(cmc_ipc_map.magic);
+}
+
+static void cmc_idpram_set_magic(u16 value)
+{
+	iowrite16(value, cmc_ipc_map.magic);
+}
+
+static u16 cmc_idpram_get_access(void)
+{
+	return ioread16(cmc_ipc_map.access);
+}
+
+static void cmc_idpram_set_access(u16 value)
+{
+	iowrite16(value, cmc_ipc_map.access);
+}
+
+static u32 cmc_idpram_get_tx_head(int dev_id)
+{
+	return ioread16(cmc_ipc_map.dev[dev_id].txq.head);
+}
+
+static u32 cmc_idpram_get_tx_tail(int dev_id)
+{
+	return ioread16(cmc_ipc_map.dev[dev_id].txq.tail);
+}
+
+static void cmc_idpram_set_tx_head(int dev_id, u32 head)
+{
+	int cnt = 100;
+	u32 val = 0;
+
+	iowrite16((u16)head, cmc_ipc_map.dev[dev_id].txq.head);
+
+	do {
+		/* Check head value written */
+		val = ioread16(cmc_ipc_map.dev[dev_id].txq.head);
+		if (val == head)
+			break;
+
+		mif_err("ERR: txq.head(%d) != head(%d)\n", val, head);
+
+		/* Write head value again */
+		iowrite16((u16)head, cmc_ipc_map.dev[dev_id].txq.head);
+	} while (cnt--);
+}
+
+static void cmc_idpram_set_tx_tail(int dev_id, u32 tail)
+{
+	int cnt = 100;
+	u32 val = 0;
+
+	iowrite16((u16)tail, cmc_ipc_map.dev[dev_id].txq.tail);
+
+	do {
+		/* Check tail value written */
+		val = ioread16(cmc_ipc_map.dev[dev_id].txq.tail);
+		if (val == tail)
+			break;
+
+		mif_err("ERR: txq.tail(%d) != tail(%d)\n", val, tail);
+
+		/* Write tail value again */
+		iowrite16((u16)tail, cmc_ipc_map.dev[dev_id].txq.tail);
+	} while (cnt--);
+}
+
+static u8 __iomem *cmc_idpram_get_tx_buff(int dev_id)
+{
+	return cmc_ipc_map.dev[dev_id].txq.buff;
+}
+
+static u32 cmc_idpram_get_tx_buff_size(int dev_id)
+{
+	return cmc_ipc_map.dev[dev_id].txq.size;
+}
+
+static u32 cmc_idpram_get_rx_head(int dev_id)
+{
+	return ioread16(cmc_ipc_map.dev[dev_id].rxq.head);
+}
+
+static u32 cmc_idpram_get_rx_tail(int dev_id)
+{
+	return ioread16(cmc_ipc_map.dev[dev_id].rxq.tail);
+}
+
+static void cmc_idpram_set_rx_head(int dev_id, u32 head)
+{
+	int cnt = 100;
+	u32 val = 0;
+
+	iowrite16((u16)head, cmc_ipc_map.dev[dev_id].rxq.head);
+
+	do {
+		/* Check head value written */
+		val = ioread16(cmc_ipc_map.dev[dev_id].rxq.head);
+		if (val == head)
+			break;
+
+		mif_err("ERR: rxq.head(%d) != head(%d)\n", val, head);
+
+		/* Write head value again */
+		iowrite16((u16)head, cmc_ipc_map.dev[dev_id].rxq.head);
+	} while (cnt--);
+}
+
+static void cmc_idpram_set_rx_tail(int dev_id, u32 tail)
+{
+	int cnt = 100;
+	u32 val = 0;
+
+	iowrite16((u16)tail, cmc_ipc_map.dev[dev_id].rxq.tail);
+
+	do {
+		/* Check tail value written */
+		val = ioread16(cmc_ipc_map.dev[dev_id].rxq.tail);
+		if (val == tail)
+			break;
+
+		mif_err("ERR: rxq.tail(%d) != tail(%d)\n", val, tail);
+
+		/* Write tail value again */
+		iowrite16((u16)tail, cmc_ipc_map.dev[dev_id].rxq.tail);
+	} while (cnt--);
+}
+
+static u8 __iomem *cmc_idpram_get_rx_buff(int dev_id)
+{
+	return cmc_ipc_map.dev[dev_id].rxq.buff;
+}
+
+static u32 cmc_idpram_get_rx_buff_size(int dev_id)
+{
+	return cmc_ipc_map.dev[dev_id].rxq.size;
+}
+
+static u16 cmc_idpram_get_mask_req_ack(int dev_id)
+{
+	return cmc_ipc_map.dev[dev_id].mask_req_ack;
+}
+
+static u16 cmc_idpram_get_mask_res_ack(int dev_id)
+{
+	return cmc_ipc_map.dev[dev_id].mask_res_ack;
+}
+
+static u16 cmc_idpram_get_mask_send(int dev_id)
+{
+	return cmc_ipc_map.dev[dev_id].mask_send;
+}
+
+/* Set dynamic environment for a modem */
+static void setup_umts_modem_env(void)
+{
+	/*
+	** Config DPRAM control structure
+	*/
+	if (system_rev == 1 || system_rev >= 4)
+		cmc_idpram_cfg.csn = 0;
+	else
+		cmc_idpram_cfg.csn = 1;
+
+	cmc_idpram_cfg.addr = SROM_CS0_BASE + (SROM_WIDTH * cmc_idpram_cfg.csn);
+	cmc_idpram_cfg.end  = cmc_idpram_cfg.addr + cmc_idpram_cfg.size - 1;
+
+	if (system_rev == 1 || system_rev >= 4) {
+		umts_modem_data.gpio_dpram_int = GPIO_CMC_IDPRAM_INT_01;
+		cmc_idpram_ctrl.dpram_irq = CMC_IDPRAM_INT_IRQ_01;
+	}
+}
+
+static void config_umts_modem_gpio(void)
+{
+	int err;
+	unsigned gpio_cp_on = umts_modem_data.gpio_cp_on;
+	unsigned gpio_cp_rst = umts_modem_data.gpio_cp_reset;
+	unsigned gpio_pda_active = umts_modem_data.gpio_pda_active;
+	unsigned gpio_phone_active = umts_modem_data.gpio_phone_active;
+	unsigned gpio_active_state = umts_modem_data.gpio_host_active;
+	unsigned gpio_host_wakeup = umts_modem_data.gpio_host_wakeup;
+	unsigned gpio_slave_wakeup = umts_modem_data.gpio_slave_wakeup;
+	unsigned gpio_dpram_int = umts_modem_data.gpio_dpram_int;
+	unsigned gpio_dpram_status = umts_modem_data.gpio_dpram_status;
+	unsigned gpio_dpram_wakeup = umts_modem_data.gpio_dpram_wakeup;
+
+	if (gpio_cp_on) {
+		err = gpio_request(gpio_cp_on, "CMC_ON");
+		if (err) {
+			mif_err("ERR: fail to request gpio %s\n", "CMC_ON");
+		} else {
+			gpio_direction_output(gpio_cp_on, 0);
+			s3c_gpio_setpull(gpio_cp_on, S3C_GPIO_PULL_NONE);
+		}
+	}
+
+	if (gpio_cp_rst) {
+		err = gpio_request(gpio_cp_rst, "CMC_RST");
+		if (err) {
+			mif_err("ERR: fail to request gpio %s\n", "CMC_RST");
+		} else {
+			gpio_direction_output(gpio_cp_rst, 0);
+			s3c_gpio_setpull(gpio_cp_rst, S3C_GPIO_PULL_NONE);
+		}
+	}
+
+	if (gpio_pda_active) {
+		err = gpio_request(gpio_pda_active, "PDA_ACTIVE");
+		if (err) {
+			mif_err("ERR: fail to request gpio %s\n", "PDA_ACTIVE");
+		} else {
+			gpio_direction_output(gpio_pda_active, 0);
+			s3c_gpio_setpull(gpio_pda_active, S3C_GPIO_PULL_NONE);
+		}
+	}
+
+	if (gpio_phone_active) {
+		err = gpio_request(gpio_phone_active, "CMC_ACTIVE");
+		if (err) {
+			mif_err("ERR: fail to request gpio %s\n", "CMC_ACTIVE");
+		} else {
+			/* Configure as a wake-up source */
+			gpio_direction_input(gpio_phone_active);
+			s3c_gpio_setpull(gpio_phone_active, S3C_GPIO_PULL_DOWN);
+			s3c_gpio_cfgpin(gpio_phone_active, S3C_GPIO_SFN(0xF));
+		}
+	}
+
+	if (gpio_active_state) {
+		err = gpio_request(gpio_active_state, "CMC_ACTIVE_STATE");
+		if (err) {
+			mif_err("ERR: fail to request gpio %s\n",
+				"CMC_ACTIVE_STATE");
+		} else {
+			gpio_direction_output(gpio_active_state, 0);
+			s3c_gpio_setpull(gpio_active_state, S3C_GPIO_PULL_NONE);
+		}
+	}
+
+	if (gpio_slave_wakeup) {
+		err = gpio_request(gpio_slave_wakeup, "CMC_SLAVE_WAKEUP");
+		if (err) {
+			mif_err("ERR: fail to request gpio %s\n",
+				"CMC_SLAVE_WAKEUP");
+		} else {
+			gpio_direction_output(gpio_slave_wakeup, 0);
+			s3c_gpio_setpull(gpio_slave_wakeup, S3C_GPIO_PULL_NONE);
+		}
+	}
+
+	if (gpio_host_wakeup) {
+		err = gpio_request(gpio_host_wakeup, "CMC_HOST_WAKEUP");
+		if (err) {
+			mif_err("ERR: fail to request gpio %s\n",
+				"CMC_HOST_WAKEUP");
+		} else {
+			/* Configure as a wake-up source */
+			gpio_direction_input(gpio_host_wakeup);
+			s3c_gpio_setpull(gpio_host_wakeup, S3C_GPIO_PULL_DOWN);
+			s3c_gpio_cfgpin(gpio_host_wakeup, S3C_GPIO_SFN(0xF));
+		}
+	}
+
+	if (gpio_dpram_int) {
+		err = gpio_request(gpio_dpram_int, "CMC_DPRAM_INT");
+		if (err) {
+			mif_err("ERR: fail to request gpio %s\n",
+				"CMC_DPRAM_INT");
+		} else {
+			/* Configure as a wake-up source */
+			gpio_direction_input(gpio_dpram_int);
+			s3c_gpio_setpull(gpio_dpram_int, S3C_GPIO_PULL_NONE);
+			s3c_gpio_cfgpin(gpio_dpram_int, S3C_GPIO_SFN(0xF));
+		}
+	}
+
+	if (gpio_dpram_status) {
+		err = gpio_request(gpio_dpram_status, "CMC_DPRAM_STATUS");
+		if (err) {
+			mif_err("ERR: fail to request gpio %s\n",
+				"CMC_DPRAM_STATUS");
+		} else {
+			gpio_direction_input(gpio_dpram_status);
+			s3c_gpio_setpull(gpio_dpram_status, S3C_GPIO_PULL_NONE);
+		}
+	}
+
+	if (gpio_dpram_wakeup) {
+		err = gpio_request(gpio_dpram_wakeup, "CMC_DPRAM_WAKEUP");
+		if (err) {
+			mif_err("ERR: fail to request gpio %s\n",
+				"CMC_DPRAM_WAKEUP");
+		} else {
+			gpio_direction_output(gpio_dpram_wakeup, 1);
+			s3c_gpio_setpull(gpio_dpram_wakeup, S3C_GPIO_PULL_NONE);
+		}
+	}
+}
+
+static u8 *cmc_idpram_remap_mem_region(struct sromc_cfg *cfg)
+{
+	int dp_addr = cfg->addr;
+	int dp_size = cfg->size;
+	u8 __iomem *dp_base;
+	struct dpram_ipc_cfg *ipc_map;
+	struct dpram_ipc_device *dev;
+
+	/* Remap DPRAM memory region */
+	dp_base = (u8 __iomem *)ioremap_nocache(dp_addr, dp_size);
+	if (!dp_base) {
+		mif_err("ERR: ioremap_nocache for dp_base fail\n");
+		return NULL;
+	}
+	mif_err("DPRAM VA=0x%08X\n", (int)dp_base);
+
+	/* Remap DPRAM SFR region */
+	dp_addr += dp_size;
+	cmc_sfr_base = (u8 __iomem *)ioremap_nocache(dp_addr, dp_size);
+	if (cmc_sfr_base == NULL) {
+		iounmap(dp_base);
+		mif_err("ERR: ioremap_nocache for cmc_sfr_base fail\n");
+		return NULL;
+	}
+
+	cmc_sfr.int2cp = (u16 __iomem *)(cmc_sfr_base + CMC_INT2CP_REG);
+	cmc_sfr.int2ap = (u16 __iomem *)(cmc_sfr_base + CMC_INT2AP_REG);
+	cmc_sfr.clr_int2ap = (u16 __iomem *)(cmc_sfr_base + CMC_CLR_INT_REG);
+	cmc_sfr.reset = (u16 __iomem *)(cmc_sfr_base + CMC_RESET_REG);
+	cmc_sfr.msg2cp = (u16 __iomem *)(cmc_sfr_base + CMC_PUT_REG);
+	cmc_sfr.msg2ap = (u16 __iomem *)(cmc_sfr_base + CMC_GET_REG);
+
+	cmc_idpram_ctrl.dp_base = (u8 __iomem *)dp_base;
+	cmc_idpram_ctrl.dp_size = dp_size;
+
+	/* Map for IPC */
+	ipc_map = (struct dpram_ipc_cfg *)dp_base;
+
+	/* Magic code and access enable fields */
+	cmc_ipc_map.magic  = (u16 __iomem *)&ipc_map->magic;
+	cmc_ipc_map.access = (u16 __iomem *)&ipc_map->access;
+
+	/* FMT */
+	dev = &cmc_ipc_map.dev[IPC_FMT];
+
+	strcpy(dev->name, "FMT");
+	dev->id = IPC_FMT;
+
+	dev->txq.head = (u16 __iomem *)&ipc_map->fmt_tx_head;
+	dev->txq.tail = (u16 __iomem *)&ipc_map->fmt_tx_tail;
+	dev->txq.buff = (u8 __iomem *)&ipc_map->fmt_tx_buff[0];
+	dev->txq.size = DP_FMT_TX_BUFF_SZ;
+
+	dev->rxq.head = (u16 __iomem *)&ipc_map->fmt_rx_head;
+	dev->rxq.tail = (u16 __iomem *)&ipc_map->fmt_rx_tail;
+	dev->rxq.buff = (u8 __iomem *)&ipc_map->fmt_rx_buff[0];
+	dev->rxq.size = DP_FMT_RX_BUFF_SZ;
+
+	dev->mask_req_ack = INT_MASK_REQ_ACK_F;
+	dev->mask_res_ack = INT_MASK_RES_ACK_F;
+	dev->mask_send    = INT_MASK_SEND_F;
+
+	/* RAW */
+	dev = &cmc_ipc_map.dev[IPC_RAW];
+
+	strcpy(dev->name, "RAW");
+	dev->id = IPC_RAW;
+
+	dev->txq.head = (u16 __iomem *)&ipc_map->raw_tx_head;
+	dev->txq.tail = (u16 __iomem *)&ipc_map->raw_tx_tail;
+	dev->txq.buff = (u8 __iomem *)&ipc_map->raw_tx_buff[0];
+	dev->txq.size = DP_RAW_TX_BUFF_SZ;
+
+	dev->rxq.head = (u16 __iomem *)&ipc_map->raw_rx_head;
+	dev->rxq.tail = (u16 __iomem *)&ipc_map->raw_rx_tail;
+	dev->rxq.buff = (u8 __iomem *)&ipc_map->raw_rx_buff[0];
+	dev->rxq.size = DP_RAW_RX_BUFF_SZ;
+
+	dev->mask_req_ack = INT_MASK_REQ_ACK_R;
+	dev->mask_res_ack = INT_MASK_RES_ACK_R;
+	dev->mask_send    = INT_MASK_SEND_R;
+
+	return dp_base;
+}
+#endif
+
+#ifdef CONFIG_CDMA_MODEM_CBP72
+static struct sromc_cfg cbp_edpram_cfg = {
+	.attr = SROMC_DATA_16 | SROMC_BYTE_EN,
+	.size = CBP_EDPRAM_SIZE,
+};
+
+static struct sromc_access_cfg cbp_edpram_access_cfg[] = {
+	[DPRAM_SPEED_LOW] = {
+		.tacs = 0x00 << 28,
+		.tcos = 0x00 << 24,
+		.tacc = 0x0F << 16,
+		.tcoh = 0x00 << 12,
+		.tcah = 0x00 << 8,
+		.tacp = 0x00 << 4,
+		.pmc  = 0x00 << 0,
+	},
+};
+
+/*
+	magic_code +
+	access_enable +
+	fmt_tx_head + fmt_tx_tail + fmt_tx_buff +
+	raw_tx_head + raw_tx_tail + raw_tx_buff +
+	fmt_rx_head + fmt_rx_tail + fmt_rx_buff +
+	raw_rx_head + raw_rx_tail + raw_rx_buff +
+	mbx_cp2ap +
+	mbx_ap2cp
+ =	2 +
+	2 +
+	2 + 2 + 1336 +
+	2 + 2 + 4564 +
+	2 + 2 + 1336 +
+	2 + 2 + 9124 +
+	2 +
+	2
+ =	16384
+*/
+
+#define CBP_DP_FMT_TX_BUFF_SZ	1336
+#define CBP_DP_RAW_TX_BUFF_SZ	4564
+#define CBP_DP_FMT_RX_BUFF_SZ	1336
+#define CBP_DP_RAW_RX_BUFF_SZ	9124
+
+#define MAX_CBP_EDPRAM_IPC_DEV	(IPC_RAW + 1)	/* FMT, RAW */
+
+struct cbp_edpram_ipc_cfg {
+	u16 magic;
+	u16 access;
+
+	u16 fmt_tx_head;
+	u16 fmt_tx_tail;
+	u8  fmt_tx_buff[CBP_DP_FMT_TX_BUFF_SZ];
+
+	u16 raw_tx_head;
+	u16 raw_tx_tail;
+	u8  raw_tx_buff[CBP_DP_RAW_TX_BUFF_SZ];
+
+	u16 fmt_rx_head;
+	u16 fmt_rx_tail;
+	u8  fmt_rx_buff[CBP_DP_FMT_RX_BUFF_SZ];
+
+	u16 raw_rx_head;
+	u16 raw_rx_tail;
+	u8  raw_rx_buff[CBP_DP_RAW_RX_BUFF_SZ];
+
+	u16 mbx_cp2ap;
+	u16 mbx_ap2cp;
+};
+
+static struct dpram_ipc_map cbp_ipc_map;
+
+static void cbp_edpram_reset(void);
+static void cbp_edpram_clr_intr(void);
+static u16  cbp_edpram_recv_intr(void);
+static void cbp_edpram_send_intr(u16 irq_mask);
+static u16  cbp_edpram_recv_msg(void);
+static void cbp_edpram_send_msg(u16 msg);
+
+static u16  cbp_edpram_get_magic(void);
+static void cbp_edpram_set_magic(u16 value);
+static u16  cbp_edpram_get_access(void);
+static void cbp_edpram_set_access(u16 value);
+
+static u32  cbp_edpram_get_tx_head(int dev_id);
+static u32  cbp_edpram_get_tx_tail(int dev_id);
+static void cbp_edpram_set_tx_head(int dev_id, u32 head);
+static void cbp_edpram_set_tx_tail(int dev_id, u32 tail);
+static u8 __iomem *cbp_edpram_get_tx_buff(int dev_id);
+static u32  cbp_edpram_get_tx_buff_size(int dev_id);
+
+static u32  cbp_edpram_get_rx_head(int dev_id);
+static u32  cbp_edpram_get_rx_tail(int dev_id);
+static void cbp_edpram_set_rx_head(int dev_id, u32 head);
+static void cbp_edpram_set_rx_tail(int dev_id, u32 tail);
+static u8 __iomem *cbp_edpram_get_rx_buff(int dev_id);
+static u32  cbp_edpram_get_rx_buff_size(int dev_id);
+
+static u16  cbp_edpram_get_mask_req_ack(int dev_id);
+static u16  cbp_edpram_get_mask_res_ack(int dev_id);
+static u16  cbp_edpram_get_mask_send(int dev_id);
+
+static struct modemlink_dpram_control cbp_edpram_ctrl = {
+	.reset      = cbp_edpram_reset,
+
+	.clear_intr = cbp_edpram_clr_intr,
+	.recv_intr  = cbp_edpram_recv_intr,
+	.send_intr  = cbp_edpram_send_intr,
+	.recv_msg   = cbp_edpram_recv_msg,
+	.send_msg   = cbp_edpram_send_msg,
+
+	.get_magic  = cbp_edpram_get_magic,
+	.set_magic  = cbp_edpram_set_magic,
+	.get_access = cbp_edpram_get_access,
+	.set_access = cbp_edpram_set_access,
+
+	.get_tx_head = cbp_edpram_get_tx_head,
+	.get_tx_tail = cbp_edpram_get_tx_tail,
+	.set_tx_head = cbp_edpram_set_tx_head,
+	.set_tx_tail = cbp_edpram_set_tx_tail,
+	.get_tx_buff = cbp_edpram_get_tx_buff,
+	.get_tx_buff_size = cbp_edpram_get_tx_buff_size,
+
+	.get_rx_head = cbp_edpram_get_rx_head,
+	.get_rx_tail = cbp_edpram_get_rx_tail,
+	.set_rx_head = cbp_edpram_set_rx_head,
+	.set_rx_tail = cbp_edpram_set_rx_tail,
+	.get_rx_buff = cbp_edpram_get_rx_buff,
+	.get_rx_buff_size = cbp_edpram_get_rx_buff_size,
+
+	.get_mask_req_ack = cbp_edpram_get_mask_req_ack,
+	.get_mask_res_ack = cbp_edpram_get_mask_res_ack,
+	.get_mask_send    = cbp_edpram_get_mask_send,
+
+	.dp_base = NULL,
+	.dp_size = 0,
+	.dp_type = EXT_DPRAM,
+	.aligned = 1,
+
+	.dpram_irq        = CBP_DPRAM_INT_IRQ_00,
+	.dpram_irq_flags  = (IRQF_NO_SUSPEND | IRQF_TRIGGER_FALLING),
+	.dpram_irq_name   = "CBP72_EDPRAM_IRQ",
+	.dpram_wlock_name = "CBP72_EDPRAM_WLOCK",
+
+	.max_ipc_dev = MAX_CBP_EDPRAM_IPC_DEV,
+};
+
+/*
+** CDMA target platform data
+*/
+static struct modem_io_t cdma_io_devices[] = {
+	[0] = {
+		.name = "cdma_boot0",
+		.id = 0,
+		.format = IPC_BOOT,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[1] = {
+		.name = "cdma_ipc0",
+		.id = 235,
+		.format = IPC_FMT,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[2] = {
+		.name = "cdma_rfs0",
+		.id = 245,
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[3] = {
+		.name = "cdma_multipdp",
+		.id = 0,
+		.format = IPC_MULTI_RAW,
+		.io_type = IODEV_DUMMY,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[4] = {
+		.name = "cdma_rmnet0",
+		.id = 10,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[5] = {
+		.name = "cdma_rmnet1",
+		.id = 11,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[6] = {
+		.name = "cdma_rmnet2",
+		.id = 12,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[7] = {
+		.name = "cdma_rmnet3",
+		.id = 13,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[8] = {
+		.name = "cdma_rmnet4",
+		.id = 7,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[9] = {
+		.name = "cdma_rmnet5", /* DM Port IO device */
+		.id = 26,
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[10] = {
+		.name = "cdma_rmnet6", /* AT CMD IO device */
+		.id = 17,
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[11] = {
+		.name = "cdma_ramdump0",
+		.id = 0,
+		.format = IPC_RAMDUMP,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+};
+
+static struct modem_data cdma_modem_data = {
+	.name = "cbp7.2",
+
+	.gpio_cp_on        = GPIO_CBP_PMIC_PWRON,
+	.gpio_cp_off       = GPIO_CBP_PS_HOLD_OFF,
+	.gpio_cp_reset     = GPIO_CBP_CP_RST,
+	.gpio_pda_active   = GPIO_PDA_ACTIVE,
+	.gpio_phone_active = GPIO_CBP_PHONE_ACTIVE,
+
+	.gpio_dpram_int = GPIO_CBP_DPRAM_INT_00,
+
+	.modem_net  = CDMA_NETWORK,
+	.modem_type = VIA_CBP72,
+	.link_types = LINKTYPE(LINKDEV_DPRAM),
+	.link_name  = "cbp72_edpram",
+	.dpram_ctl  = &cbp_edpram_ctrl,
+
+	.num_iodevs = ARRAY_SIZE(cdma_io_devices),
+	.iodevs     = cdma_io_devices,
+
+	.use_handover = true,
+
+	.ipc_version = SIPC_VER_50,
+};
+
+static struct resource cdma_modem_res[] = {
+	[0] = {
+		.name  = "cp_active_irq",
+		.start = CBP_PHONE_ACTIVE_IRQ,
+		.end   = CBP_PHONE_ACTIVE_IRQ,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device cdma_modem = {
+	.name = "mif_sipc5",
+	.id = 2,
+	.num_resources = ARRAY_SIZE(cdma_modem_res),
+	.resource = cdma_modem_res,
+	.dev = {
+		.platform_data = &cdma_modem_data,
+	},
+};
+
+static void cbp_edpram_reset(void)
+{
+	return;
+}
+
+static void cbp_edpram_clr_intr(void)
+{
+	ioread16(cbp_ipc_map.mbx_cp2ap);
+}
+
+static u16 cbp_edpram_recv_intr(void)
+{
+	return ioread16(cbp_ipc_map.mbx_cp2ap);
+}
+
+static void cbp_edpram_send_intr(u16 irq_mask)
+{
+	iowrite16(irq_mask, cbp_ipc_map.mbx_ap2cp);
+}
+
+static u16 cbp_edpram_recv_msg(void)
+{
+	return ioread16(cbp_ipc_map.mbx_cp2ap);
+}
+
+static void cbp_edpram_send_msg(u16 msg)
+{
+	iowrite16(msg, cbp_ipc_map.mbx_ap2cp);
+}
+
+static u16 cbp_edpram_get_magic(void)
+{
+	return ioread16(cbp_ipc_map.magic);
+}
+
+static void cbp_edpram_set_magic(u16 value)
+{
+	iowrite16(value, cbp_ipc_map.magic);
+}
+
+static u16 cbp_edpram_get_access(void)
+{
+	return ioread16(cbp_ipc_map.access);
+}
+
+static void cbp_edpram_set_access(u16 value)
+{
+	iowrite16(value, cbp_ipc_map.access);
+}
+
+static u32 cbp_edpram_get_tx_head(int dev_id)
+{
+	return ioread16(cbp_ipc_map.dev[dev_id].txq.head);
+}
+
+static u32 cbp_edpram_get_tx_tail(int dev_id)
+{
+	return ioread16(cbp_ipc_map.dev[dev_id].txq.tail);
+}
+
+static void cbp_edpram_set_tx_head(int dev_id, u32 head)
+{
+	iowrite16((u16)head, cbp_ipc_map.dev[dev_id].txq.head);
+}
+
+static void cbp_edpram_set_tx_tail(int dev_id, u32 tail)
+{
+	iowrite16((u16)tail, cbp_ipc_map.dev[dev_id].txq.tail);
+}
+
+static u8 __iomem *cbp_edpram_get_tx_buff(int dev_id)
+{
+	return cbp_ipc_map.dev[dev_id].txq.buff;
+}
+
+static u32 cbp_edpram_get_tx_buff_size(int dev_id)
+{
+	return cbp_ipc_map.dev[dev_id].txq.size;
+}
+
+static u32 cbp_edpram_get_rx_head(int dev_id)
+{
+	return ioread16(cbp_ipc_map.dev[dev_id].rxq.head);
+}
+
+static u32 cbp_edpram_get_rx_tail(int dev_id)
+{
+	return ioread16(cbp_ipc_map.dev[dev_id].rxq.tail);
+}
+
+static void cbp_edpram_set_rx_head(int dev_id, u32 head)
+{
+	return iowrite16((u16)head, cbp_ipc_map.dev[dev_id].rxq.head);
+}
+
+static void cbp_edpram_set_rx_tail(int dev_id, u32 tail)
+{
+	return iowrite16((u16)tail, cbp_ipc_map.dev[dev_id].rxq.tail);
+}
+
+static u8 __iomem *cbp_edpram_get_rx_buff(int dev_id)
+{
+	return cbp_ipc_map.dev[dev_id].rxq.buff;
+}
+
+static u32 cbp_edpram_get_rx_buff_size(int dev_id)
+{
+	return cbp_ipc_map.dev[dev_id].rxq.size;
+}
+
+static u16 cbp_edpram_get_mask_req_ack(int dev_id)
+{
+	return cbp_ipc_map.dev[dev_id].mask_req_ack;
+}
+
+static u16 cbp_edpram_get_mask_res_ack(int dev_id)
+{
+	return cbp_ipc_map.dev[dev_id].mask_res_ack;
+}
+
+static u16 cbp_edpram_get_mask_send(int dev_id)
+{
+	return cbp_ipc_map.dev[dev_id].mask_send;
+}
+
+/* Set dynamic environment for a modem */
+static void setup_cdma_modem_env(void)
+{
+	/*
+	** Config DPRAM control structure
+	*/
+	if (system_rev == 1 || system_rev >= 4)
+		cbp_edpram_cfg.csn = 1;
+	else
+		cbp_edpram_cfg.csn = 0;
+
+	cbp_edpram_cfg.addr = SROM_CS0_BASE + (SROM_WIDTH * cbp_edpram_cfg.csn);
+	cbp_edpram_cfg.end  = cbp_edpram_cfg.addr + cbp_edpram_cfg.size - 1;
+
+	if (system_rev == 1 || system_rev >= 4) {
+		cdma_modem_data.gpio_dpram_int = GPIO_CBP_DPRAM_INT_01;
+		cbp_edpram_ctrl.dpram_irq = CBP_DPRAM_INT_IRQ_01;
+	}
+}
+
+static void config_cdma_modem_gpio(void)
+{
+	int err;
+	unsigned gpio_boot_sel = GPIO_CBP_BOOT_SEL;
+	unsigned gpio_cp_on = cdma_modem_data.gpio_cp_on;
+	unsigned gpio_cp_off = cdma_modem_data.gpio_cp_off;
+	unsigned gpio_cp_rst = cdma_modem_data.gpio_cp_reset;
+	unsigned gpio_pda_active = cdma_modem_data.gpio_pda_active;
+	unsigned gpio_phone_active = cdma_modem_data.gpio_phone_active;
+	unsigned gpio_dpram_int = cdma_modem_data.gpio_dpram_int;
+
+	pr_info("[MDM] <%s>\n", __func__);
+
+	if (gpio_boot_sel) {
+		err = gpio_request(gpio_boot_sel, "CBP_BOOT_SEL");
+		if (err) {
+			pr_err("fail to request gpio %s\n", "CBP_BOOT_SEL");
+		} else {
+			gpio_direction_output(gpio_boot_sel, 0);
+			s3c_gpio_setpull(gpio_boot_sel, S3C_GPIO_PULL_NONE);
+		}
+	}
+
+	if (gpio_cp_on) {
+		err = gpio_request(gpio_cp_on, "CBP_ON");
+		if (err) {
+			pr_err("fail to request gpio %s\n", "CBP_ON");
+		} else {
+			gpio_direction_output(gpio_cp_on, 0);
+			s3c_gpio_setpull(gpio_cp_on, S3C_GPIO_PULL_NONE);
+		}
+	}
+
+	if (gpio_cp_off) {
+		err = gpio_request(gpio_cp_off, "CBP_OFF");
+		if (err) {
+			pr_err("fail to request gpio %s\n", "CBP_OFF");
+		} else {
+			gpio_direction_output(gpio_cp_off, 1);
+			s3c_gpio_setpull(gpio_cp_off, S3C_GPIO_PULL_NONE);
+		}
+	}
+
+	if (gpio_cp_rst) {
+		err = gpio_request(gpio_cp_rst, "CBP_RST");
+		if (err) {
+			pr_err("fail to request gpio %s\n", "CBP_RST");
+		} else {
+			gpio_direction_output(gpio_cp_rst, 0);
+			s3c_gpio_setpull(gpio_cp_rst, S3C_GPIO_PULL_NONE);
+		}
+	}
+
+	if (gpio_pda_active) {
+		err = gpio_request(gpio_pda_active, "PDA_ACTIVE");
+		if (err) {
+			pr_err("fail to request gpio %s\n", "PDA_ACTIVE");
+		} else {
+			gpio_direction_output(gpio_pda_active, 0);
+			s3c_gpio_setpull(gpio_pda_active, S3C_GPIO_PULL_NONE);
+		}
+	}
+
+	if (gpio_phone_active) {
+		err = gpio_request(gpio_phone_active, "CBP_ACTIVE");
+		if (err) {
+			pr_err("fail to request gpio %s\n", "CBP_ACTIVE");
+		} else {
+			/* Configure as a wake-up source */
+			gpio_direction_input(gpio_phone_active);
+			s3c_gpio_setpull(gpio_phone_active, S3C_GPIO_PULL_NONE);
+			s3c_gpio_cfgpin(gpio_phone_active, S3C_GPIO_SFN(0xF));
+		}
+	}
+
+	if (gpio_dpram_int) {
+		err = gpio_request(gpio_dpram_int, "CBP_DPRAM_INT");
+		if (err) {
+			pr_err("fail to request gpio %s\n", "CBP_DPRAM_INT");
+		} else {
+			/* Configure as a wake-up source */
+			gpio_direction_input(gpio_dpram_int);
+			s3c_gpio_setpull(gpio_dpram_int, S3C_GPIO_PULL_NONE);
+			s3c_gpio_cfgpin(gpio_dpram_int, S3C_GPIO_SFN(0xF));
+		}
+	}
+
+	/* set low unused gpios between AP and CP */
+	err = gpio_request(GPIO_FLM_RXD, "FLM_RXD");
+	if (err)
+		pr_err(LOG_TAG "fail to request gpio %s : %d\n", "FLM_RXD",
+		err);
+	else {
+		gpio_direction_input(GPIO_FLM_RXD);
+		s3c_gpio_setpull(GPIO_FLM_RXD, S3C_GPIO_PULL_UP);
+		s3c_gpio_cfgpin(GPIO_FLM_RXD, S3C_GPIO_SFN(2));
+	}
+
+	err = gpio_request(GPIO_FLM_TXD, "FLM_TXD");
+	if (err)
+		pr_err(LOG_TAG "fail to request gpio %s : %d\n", "FLM_TXD",
+		err);
+	else {
+		gpio_direction_input(GPIO_FLM_TXD);
+		s3c_gpio_setpull(GPIO_FLM_TXD, S3C_GPIO_PULL_NONE);
+		s3c_gpio_cfgpin(GPIO_FLM_TXD, S3C_GPIO_SFN(2));
+	}
+}
+
+static u8 *cbp_edpram_remap_mem_region(struct sromc_cfg *cfg)
+{
+	int			      dp_addr = 0;
+	int			      dp_size = 0;
+	u8 __iomem                   *dp_base = NULL;
+	struct cbp_edpram_ipc_cfg    *ipc_map = NULL;
+	struct dpram_ipc_device *dev = NULL;
+
+	dp_addr = cfg->addr;
+	dp_size = cfg->size;
+	dp_base = (u8 *)ioremap_nocache(dp_addr, dp_size);
+	if (!dp_base) {
+		pr_err("[MDM] <%s> dpram base ioremap fail\n", __func__);
+		return NULL;
+	}
+	pr_info("[MDM] <%s> DPRAM VA=0x%08X\n", __func__, (int)dp_base);
+
+	cbp_edpram_ctrl.dp_base = (u8 __iomem *)dp_base;
+	cbp_edpram_ctrl.dp_size = dp_size;
+
+	/* Map for IPC */
+	ipc_map = (struct cbp_edpram_ipc_cfg *)dp_base;
+
+	/* Magic code and access enable fields */
+	cbp_ipc_map.magic  = (u16 __iomem *)&ipc_map->magic;
+	cbp_ipc_map.access = (u16 __iomem *)&ipc_map->access;
+
+	/* FMT */
+	dev = &cbp_ipc_map.dev[IPC_FMT];
+
+	strcpy(dev->name, "FMT");
+	dev->id = IPC_FMT;
+
+	dev->txq.head = (u16 __iomem *)&ipc_map->fmt_tx_head;
+	dev->txq.tail = (u16 __iomem *)&ipc_map->fmt_tx_tail;
+	dev->txq.buff = (u8 __iomem *)&ipc_map->fmt_tx_buff[0];
+	dev->txq.size = CBP_DP_FMT_TX_BUFF_SZ;
+
+	dev->rxq.head = (u16 __iomem *)&ipc_map->fmt_rx_head;
+	dev->rxq.tail = (u16 __iomem *)&ipc_map->fmt_rx_tail;
+	dev->rxq.buff = (u8 __iomem *)&ipc_map->fmt_rx_buff[0];
+	dev->rxq.size = CBP_DP_FMT_RX_BUFF_SZ;
+
+	dev->mask_req_ack = INT_MASK_REQ_ACK_F;
+	dev->mask_res_ack = INT_MASK_RES_ACK_F;
+	dev->mask_send    = INT_MASK_SEND_F;
+
+	/* RAW */
+	dev = &cbp_ipc_map.dev[IPC_RAW];
+
+	strcpy(dev->name, "RAW");
+	dev->id = IPC_RAW;
+
+	dev->txq.head = (u16 __iomem *)&ipc_map->raw_tx_head;
+	dev->txq.tail = (u16 __iomem *)&ipc_map->raw_tx_tail;
+	dev->txq.buff = (u8 __iomem *)&ipc_map->raw_tx_buff[0];
+	dev->txq.size = CBP_DP_RAW_TX_BUFF_SZ;
+
+	dev->rxq.head = (u16 __iomem *)&ipc_map->raw_rx_head;
+	dev->rxq.tail = (u16 __iomem *)&ipc_map->raw_rx_tail;
+	dev->rxq.buff = (u8 __iomem *)&ipc_map->raw_rx_buff[0];
+	dev->rxq.size = CBP_DP_RAW_RX_BUFF_SZ;
+
+	dev->mask_req_ack = INT_MASK_REQ_ACK_R;
+	dev->mask_res_ack = INT_MASK_RES_ACK_R;
+	dev->mask_send    = INT_MASK_SEND_R;
+
+	/* Mailboxes */
+	cbp_ipc_map.mbx_ap2cp = (u16 __iomem *)&ipc_map->mbx_ap2cp;
+	cbp_ipc_map.mbx_cp2ap = (u16 __iomem *)&ipc_map->mbx_cp2ap;
+
+	return dp_base;
+}
+#endif
+
+/**
+ *	DPRAM GPIO settings
+ *
+ *	SROM_NUM_ADDR_BITS value indicate the address line number or
+ *	the mux/demux dpram type. if you want to set mux mode, define the
+ *	SROM_NUM_ADDR_BITS to zero.
+ *
+ *	for CMC22x
+ *	CMC22x has 16KB + a SFR register address.
+ *	It used 14 bits (13bits for 16KB word address and 1 bit for SFR
+ *	register)
+ */
+static void config_dpram_port_gpio(void)
+{
+	int addr_bits = SROM_NUM_ADDR_BITS;
+
+	mif_info("address line = %d bits\n", addr_bits);
+
+	/*
+	** Config DPRAM address/data GPIO pins
+	*/
+
+	/* Set GPIO for address bus (13 ~ 14 bits) */
+	switch (addr_bits) {
+	case 0:
+		break;
+
+	case 13 ... 14:
+		s3c_gpio_cfgrange_nopull(GPIO_SROM_ADDR_BUS_LOW,
+			EXYNOS4_GPIO_Y3_NR, S3C_GPIO_SFN(2));
+		s3c_gpio_cfgrange_nopull(GPIO_SROM_ADDR_BUS_HIGH,
+			(addr_bits - EXYNOS4_GPIO_Y3_NR), S3C_GPIO_SFN(2));
+		break;
+
+	default:
+		mif_err("ERR: invalid addr_bits!!!\n");
+		return;
+	}
+
+	/* Set GPIO for data bus (16 bits) */
+	s3c_gpio_cfgrange_nopull(GPIO_SROM_DATA_BUS_LOW, 8, S3C_GPIO_SFN(2));
+	s3c_gpio_cfgrange_nopull(GPIO_SROM_DATA_BUS_HIGH, 8, S3C_GPIO_SFN(2));
+
+	/* Setup SROMC CSn pins */
+	s3c_gpio_cfgpin(GPIO_DPRAM_CSN0, S3C_GPIO_SFN(2));
+	s3c_gpio_cfgpin((GPIO_DPRAM_CSN0 + 1), S3C_GPIO_SFN(2));
+
+	/* Config OEn, WEn */
+	s3c_gpio_cfgpin(GPIO_DPRAM_REN, S3C_GPIO_SFN(2));
+	s3c_gpio_cfgpin(GPIO_DPRAM_WEN, S3C_GPIO_SFN(2));
+
+	/* Config LBn, UBn */
+	s3c_gpio_cfgpin(GPIO_DPRAM_LBN, S3C_GPIO_SFN(2));
+	s3c_gpio_cfgpin(GPIO_DPRAM_UBN, S3C_GPIO_SFN(2));
+}
+
+static void init_sromc(void)
+{
+	struct clk *clk = NULL;
+
+	/* SROMC clk enable */
+	clk = clk_get(NULL, "sromc");
+	if (!clk) {
+		mif_err("ERR: SROMC clock gate fail\n");
+		return;
+	}
+	clk_enable(clk);
+}
+
+static void setup_sromc
+(
+	unsigned csn,
+	struct sromc_cfg *cfg,
+	struct sromc_access_cfg *acc_cfg
+)
+{
+	unsigned bw = 0;	/* Bus width and wait control	*/
+	unsigned bc = 0;	/* Vank control			*/
+	void __iomem *bank_sfr = S5P_SROM_BC0 + (4 * csn);
+
+	mif_err("SROMC settings for CS%d...\n", csn);
+
+	bw = __raw_readl(S5P_SROM_BW);
+	bc = __raw_readl(bank_sfr);
+	mif_err("Old SROMC settings = BW(0x%08X) BC%d(0x%08X)\n", bw, csn, bc);
+
+	/* Set the BW control field for the CSn */
+	bw &= ~(SROMC_MASK << (csn << 2));
+	bw |= (cfg->attr << (csn << 2));
+	writel(bw, S5P_SROM_BW);
+
+	/* Set SROMC memory access timing for the CSn */
+	bc = acc_cfg->tacs | acc_cfg->tcos | acc_cfg->tacc |
+	     acc_cfg->tcoh | acc_cfg->tcah | acc_cfg->tacp | acc_cfg->pmc;
+
+	writel(bc, bank_sfr);
+
+	/* Verify SROMC settings */
+	bw = __raw_readl(S5P_SROM_BW);
+	bc = __raw_readl(bank_sfr);
+	mif_err("New SROMC settings = BW(0x%08X) BC%d(0x%08X)\n", bw, csn, bc);
+}
+
+static void setup_dpram_speed(unsigned csn, struct sromc_access_cfg *acc_cfg)
+{
+	void __iomem *bank_sfr = S5P_SROM_BC0 + (4 * csn);
+	unsigned bc = 0;
+
+	bc = __raw_readl(bank_sfr);
+	mif_info("Old CS%d setting = 0x%08X\n", csn, bc);
+
+	/* SROMC memory access timing setting */
+	bc = acc_cfg->tacs | acc_cfg->tcos | acc_cfg->tacc |
+	     acc_cfg->tcoh | acc_cfg->tcah | acc_cfg->tacp | acc_cfg->pmc;
+	writel(bc, bank_sfr);
+
+	bc = __raw_readl(bank_sfr);
+	mif_info("New CS%d setting = 0x%08X\n", csn, bc);
+}
+
+static int __init init_modem(void)
+{
+	struct sromc_cfg *cfg = NULL;
+	struct sromc_access_cfg *acc_cfg = NULL;
+
+	mif_err("System Revision = %d\n", system_rev);
+
+	setup_umts_modem_env();
+	setup_cdma_modem_env();
+
+	config_dpram_port_gpio();
+
+	config_umts_modem_gpio();
+	config_cdma_modem_gpio();
+
+	init_sromc();
+
+	cfg = &cmc_idpram_cfg;
+	acc_cfg = &cmc_idpram_access_cfg[DPRAM_SPEED_LOW];
+	setup_sromc(cfg->csn, cfg, acc_cfg);
+
+	cfg = &cbp_edpram_cfg;
+	acc_cfg = &cbp_edpram_access_cfg[DPRAM_SPEED_LOW];
+	setup_sromc(cfg->csn, cfg, acc_cfg);
+
+	if (!cmc_idpram_remap_mem_region(&cmc_idpram_cfg))
+		return -1;
+	platform_device_register(&umts_modem);
+
+	if (!cbp_edpram_remap_mem_region(&cbp_edpram_cfg))
+		return -1;
+	platform_device_register(&cdma_modem);
+
+	return 0;
+}
+late_initcall(init_modem);
+/*device_initcall(init_modem);*/
+
+#ifdef CONFIG_USBHUB_USB3503
+static int (*usbhub_set_mode)(struct usb3503_hubctl *, int);
+static struct usb3503_hubctl *usbhub_ctl;
+
+#ifdef CONFIG_EXYNOS4_CPUFREQ
+static int exynos_cpu_frequency_lock(void)
+{
+	unsigned int level, freq = 700;
+
+	if (atomic_read(&umts_link_pm_data.freqlock) == 0) {
+		if (exynos_cpufreq_get_level(freq * 1000, &level)) {
+			mif_err("ERR: exynos_cpufreq_get_level fail\n");
+			return -EINVAL;
+		}
+
+		if (exynos_cpufreq_lock(DVFS_LOCK_ID_USB_IF, level)) {
+			mif_err("ERR: exynos_cpufreq_lock fail\n");
+			return -EINVAL;
+		}
+
+		atomic_set(&umts_link_pm_data.freqlock, 1);
+		mif_debug("<%d> %d MHz\n", level, freq);
+	}
+	return 0;
+}
+
+static int exynos_cpu_frequency_unlock(void)
+{
+	if (atomic_read(&umts_link_pm_data.freqlock) == 1) {
+		exynos_cpufreq_lock_free(DVFS_LOCK_ID_USB_IF);
+		atomic_set(&umts_link_pm_data.freqlock, 0);
+		mif_debug("\n");
+	}
+	return 0;
+}
+#else
+static int exynos_cpu_frequency_lock(void)
+{
+	return 0;
+}
+
+static int exynos_cpu_frequency_unlock(void)
+{
+	return 0;
+}
+#endif
+
+void set_host_states(struct platform_device *pdev, int type)
+{
+}
+
+static int usb3503_hub_handler(void (*set_mode)(void), void *ctl)
+{
+	if (!set_mode || !ctl)
+		return -EINVAL;
+
+	usbhub_set_mode = (int (*)(struct usb3503_hubctl *, int))set_mode;
+	usbhub_ctl = (struct usb3503_hubctl *)ctl;
+
+	mif_info("set_mode(%pF)\n", set_mode);
+
+	return 0;
+}
+
+static int usb3503_hw_config(void)
+{
+	int err;
+
+	err = gpio_request(GPIO_USB_HUB_RST, "HUB_RST");
+	if (err) {
+		mif_err("ERR: fail to request gpio %s\n", "HUB_RST");
+	} else {
+		gpio_direction_output(GPIO_USB_HUB_RST, 0);
+		s3c_gpio_setpull(GPIO_USB_HUB_RST, S3C_GPIO_PULL_NONE);
+	}
+	s5p_gpio_set_drvstr(GPIO_USB_HUB_RST, S5P_GPIO_DRVSTR_LV1);
+	/* need to check drvstr 1 or 2 */
+
+	/* for USB3503 26Mhz Reference clock setting */
+	err = gpio_request(GPIO_USB_HUB_INT, "HUB_INT");
+	if (err) {
+		mif_err("ERR: fail to request gpio %s\n", "HUB_INT");
+	} else {
+		gpio_direction_output(GPIO_USB_HUB_INT, 1);
+		s3c_gpio_setpull(GPIO_USB_HUB_INT, S3C_GPIO_PULL_NONE);
+	}
+
+	return 0;
+}
+
+static int usb3503_reset_n(int val)
+{
+	gpio_set_value(GPIO_USB_HUB_RST, 0);
+
+	/* hub off from cpuidle(LPA), skip the msleep schedule*/
+	if (val) {
+		msleep(20);
+		mif_info("val = %d\n", gpio_get_value(GPIO_USB_HUB_RST));
+
+		gpio_set_value(GPIO_USB_HUB_RST, !!val);
+
+		mif_info("val = %d\n", gpio_get_value(GPIO_USB_HUB_RST));
+		udelay(5); /* need it ?*/
+	}
+	return 0;
+}
+
+static struct usb3503_platform_data usb3503_pdata = {
+	.initial_mode = USB3503_MODE_STANDBY,
+	.reset_n = usb3503_reset_n,
+	.register_hub_handler = usb3503_hub_handler,
+	.port_enable = host_port_enable,
+};
+
+static struct i2c_board_info i2c_devs20_emul[] __initdata = {
+	{
+		I2C_BOARD_INFO(USB3503_I2C_NAME, 0x08),
+		.platform_data = &usb3503_pdata,
+	},
+};
+
+/* I2C20_EMUL */
+static struct i2c_gpio_platform_data i2c20_platdata = {
+	.sda_pin = GPIO_USB_HUB_SDA,
+	.scl_pin = GPIO_USB_HUB_SCL,
+	/*FIXME: need to timming tunning...  */
+	.udelay	= 20,
+};
+
+static struct platform_device s3c_device_i2c20 = {
+	.name = "i2c-gpio",
+	.id = 20,
+	.dev.platform_data = &i2c20_platdata,
+};
+
+static int __init init_usbhub(void)
+{
+	usb3503_hw_config();
+	i2c_register_board_info(20, i2c_devs20_emul,
+				ARRAY_SIZE(i2c_devs20_emul));
+
+	platform_device_register(&s3c_device_i2c20);
+	return 0;
+}
+
+device_initcall(init_usbhub);
+
+static int host_port_enable(int port, int enable)
+{
+	int err;
+
+	mif_info("port(%d) control(%d)\n", port, enable);
+
+	if (enable) {
+		err = usbhub_set_mode(usbhub_ctl, USB3503_MODE_HUB);
+		if (err < 0) {
+			mif_err("ERR: hub on fail\n");
+			goto exit;
+		}
+		err = s5p_ehci_port_control(&s5p_device_ehci, port, 1);
+		if (err < 0) {
+			mif_err("ERR: port(%d) enable fail\n", port);
+			goto exit;
+		}
+	} else {
+		err = s5p_ehci_port_control(&s5p_device_ehci, port, 0);
+		if (err < 0) {
+			mif_err("ERR: port(%d) enable fail\n", port);
+			goto exit;
+		}
+		err = usbhub_set_mode(usbhub_ctl, USB3503_MODE_STANDBY);
+		if (err < 0) {
+			mif_err("ERR: hub off fail\n");
+			goto exit;
+		}
+	}
+
+	err = gpio_direction_output(umts_modem_data.gpio_host_active, enable);
+	mif_info("active state err(%d), en(%d), level(%d)\n",
+		err, enable, gpio_get_value(umts_modem_data.gpio_host_active));
+
+exit:
+	return err;
+}
+#else
+void set_host_states(struct platform_device *pdev, int type)
+{
+	if (active_ctl.gpio_initialized) {
+		mif_err("<%s> Active States =%d, %s\n", pdev->name, type);
+		gpio_direction_output(umts_link_pm_data.gpio_link_active, type);
+	} else {
+		active_ctl.gpio_request_host_active = 1;
+	}
+}
+#endif
+
diff --git a/arch/arm/mach-exynos/board-gaia-modems.c b/arch/arm/mach-exynos/board-gaia-modems.c
new file mode 100644
index 0000000..e453d6e
--- /dev/null
+++ b/arch/arm/mach-exynos/board-gaia-modems.c
@@ -0,0 +1,1369 @@
+/* linux/arch/arm/mach-xxxx/board-c1via-modems.c
+ * Copyright (C) 2010 Samsung Electronics. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/regulator/consumer.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+
+/* inlcude platform specific file */
+#include <linux/platform_data/modem.h>
+#include <mach/sec_modem.h>
+#include <mach/gpio.h>
+#include <mach/gpio-exynos5.h>
+#include <plat/gpio-cfg.h>
+#include <mach/regs-mem.h>
+#include <plat/regs-srom.h>
+
+#ifdef CONFIG_USBHUB_USB3503
+#include <linux/i2c.h>
+#include <linux/i2c-gpio.h>
+#include <linux/platform_data/usb3503.h>
+#include <mach/cpufreq.h>
+#include <plat/usb-phy.h>
+#endif
+#include <plat/devs.h>
+#include <plat/ehci.h>
+
+#define SROM_CS0_BASE		0x04000000
+#define SROM_WIDTH		0x01000000
+#define SROM_NUM_ADDR_BITS	14
+
+/* For "bus width and wait control (BW)" register */
+enum sromc_attr {
+	SROMC_DATA_16   = 0x1,	/* 16-bit data bus	*/
+	SROMC_BYTE_ADDR = 0x2,	/* Byte base address	*/
+	SROMC_WAIT_EN   = 0x4,	/* Wait enabled		*/
+	SROMC_BYTE_EN   = 0x8,	/* Byte access enabled	*/
+	SROMC_MASK      = 0xF
+};
+
+/* DPRAM configuration */
+struct sromc_cfg {
+	enum sromc_attr attr;
+	unsigned size;
+	unsigned csn;		/* CSn #			*/
+	unsigned addr;		/* Start address (physical)	*/
+	unsigned end;		/* End address (physical)	*/
+};
+
+/* DPRAM access timing configuration */
+struct sromc_access_cfg {
+	u32 tacs;		/* Address set-up before CSn		*/
+	u32 tcos;		/* Chip selection set-up before OEn	*/
+	u32 tacc;		/* Access cycle				*/
+	u32 tcoh;		/* Chip selection hold on OEn		*/
+	u32 tcah;		/* Address holding time after CSn	*/
+	u32 tacp;		/* Page mode access cycle at Page mode	*/
+	u32 pmc;		/* Page Mode config			*/
+};
+
+/* For CMC221 IDPRAM (Internal DPRAM) */
+#define CMC_IDPRAM_SIZE		0x4000	/* 16 KB */
+
+/* FOR CMC221 SFR for IDPRAM */
+#define CMC_INT2CP_REG		0x10	/* Interrupt to CP            */
+#define CMC_INT2AP_REG		0x50
+#define CMC_CLR_INT_REG		0x28	/* Clear Interrupt to AP      */
+#define CMC_RESET_REG		0x3C
+#define CMC_PUT_REG		0x40	/* AP->CP reg for hostbooting */
+#define CMC_GET_REG		0x50	/* CP->AP reg for hostbooting */
+
+#define INT_MASK_REQ_ACK_F	0x0020
+#define INT_MASK_REQ_ACK_R	0x0010
+#define INT_MASK_RES_ACK_F	0x0008
+#define INT_MASK_RES_ACK_R	0x0004
+#define INT_MASK_SEND_F		0x0002
+#define INT_MASK_SEND_R		0x0001
+
+#define INT_MASK_REQ_ACK_RFS	0x0400 /* Request RES_ACK_RFS		*/
+#define INT_MASK_RES_ACK_RFS	0x0200 /* Response of REQ_ACK_RFS	*/
+#define INT_MASK_SEND_RFS	0x0100 /* Indicate sending RFS data	*/
+
+
+/* Function prototypes */
+static void config_dpram_port_gpio(void);
+static void init_sromc(void);
+static void setup_sromc(unsigned csn, struct sromc_cfg *cfg,
+		struct sromc_access_cfg *acc_cfg);
+static void setup_dpram_speed(unsigned csn, struct sromc_access_cfg *acc_cfg);
+static int __init init_modem(void);
+
+
+#ifdef CONFIG_USBHUB_USB3503
+static int host_port_enable(int port, int enable);
+#else
+/*
+static int host_port_enable(int port, int enable)
+{
+	return s5p_ehci_port_control(&s5p_device_ehci, port, enable);
+}
+*/
+#endif
+
+static struct sromc_cfg cmc_idpram_cfg = {
+	.attr = SROMC_DATA_16,
+	.size = CMC_IDPRAM_SIZE,
+};
+
+static struct sromc_access_cfg cmc_idpram_access_cfg[] = {
+	[DPRAM_SPEED_LOW] = {
+		.tacs = 0x0F << 28,
+		.tcos = 0x0F << 24,
+		.tacc = 0x1F << 16,
+		.tcoh = 0x0F << 12,
+		.tcah = 0x0F << 8,
+		.tacp = 0x00 << 4,
+		.pmc  = 0x00 << 0,
+	},
+/*	[DPRAM_SPEED_LOW] = {
+		.tacs = 0x01 << 28,
+		.tcos = 0x01 << 24,
+		.tacc = 0x1B << 16,
+		.tcoh = 0x01 << 12,
+		.tcah = 0x01 << 8,
+		.tacp = 0x00 << 4,
+		.pmc  = 0x00 << 0,
+	},*/
+	[DPRAM_SPEED_HIGH] = {
+		.tacs = 0x01 << 28,
+		.tcos = 0x01 << 24,
+		.tacc = 0x0B << 16,
+		.tcoh = 0x01 << 12,
+		.tcah = 0x01 << 8,
+		.tacp = 0x00 << 4,
+		.pmc  = 0x00 << 0,
+	},
+};
+
+/*
+	magic_code +
+	access_enable +
+	fmt_tx_head + fmt_tx_tail + fmt_tx_buff +
+	raw_tx_head + raw_tx_tail + raw_tx_buff +
+	rfs_tx_head + rfs_tx_tail + rfs_tx_buff +
+	fmt_rx_head + fmt_rx_tail + fmt_rx_buff +
+	raw_rx_head + raw_rx_tail + raw_rx_buff +
+	rfs_rx_head + rfs_rx_tail + rfs_rx_buff +
+ =	2 +
+	2 +
+	4 + 4 + 2040 +
+	4 + 4 + 4088 +
+	4 + 4 + 1016 +
+	4 + 4 + 2040 +
+	4 + 4 + 5112 +
+	4 + 4 + 2036 +
+ =	16384
+*/
+#define DP_FMT_TX_BUFF_SZ	2040
+#define DP_RAW_TX_BUFF_SZ	4088
+#define DP_RFS_TX_BUFF_SZ	1016
+#define DP_FMT_RX_BUFF_SZ	2040
+#define DP_RAW_RX_BUFF_SZ	5112
+#define DP_RFS_RX_BUFF_SZ	2036
+
+#define MAX_CMC_IDPRAM_IPC_DEV	(IPC_RFS + 1)	/* FMT, RAW, RFS */
+
+struct dpram_ipc_cfg {
+	u16 magic;
+	u16 access;
+
+	u32 fmt_tx_head;
+	u32 fmt_tx_tail;
+	u8  fmt_tx_buff[DP_FMT_TX_BUFF_SZ];
+
+	u32 raw_tx_head;
+	u32 raw_tx_tail;
+	u8  raw_tx_buff[DP_RAW_TX_BUFF_SZ];
+
+	u32 rfs_tx_head;
+	u32 rfs_tx_tail;
+	u8  rfs_tx_buff[DP_RFS_TX_BUFF_SZ];
+
+	u32 fmt_rx_head;
+	u32 fmt_rx_tail;
+	u8  fmt_rx_buff[DP_FMT_RX_BUFF_SZ];
+
+	u32 raw_rx_head;
+	u32 raw_rx_tail;
+	u8  raw_rx_buff[DP_RAW_RX_BUFF_SZ];
+
+	u32 rfs_rx_head;
+	u32 rfs_rx_tail;
+	u8  rfs_rx_buff[DP_RFS_RX_BUFF_SZ];
+};
+
+struct cmc_dpram_circ {
+	u32 __iomem *head;
+	u32 __iomem *tail;
+	u8  __iomem *buff;
+	u32          size;
+};
+
+struct cmc_dpram_ipc_device {
+	char name[16];
+	int  id;
+
+	struct cmc_dpram_circ txq;
+	struct cmc_dpram_circ rxq;
+
+	u16 mask_req_ack;
+	u16 mask_res_ack;
+	u16 mask_send;
+};
+
+struct cmc_dpram_ipc_map {
+	u16 __iomem *magic;
+	u16 __iomem *access;
+
+	struct cmc_dpram_ipc_device dev[MAX_CMC_IDPRAM_IPC_DEV];
+};
+
+struct cmc221_idpram_sfr {
+	u16 __iomem *int2cp;
+	u16 __iomem *int2ap;
+	u16 __iomem *clr_int2ap;
+	u16 __iomem *reset;
+	u16 __iomem *msg2cp;
+	u16 __iomem *msg2ap;
+};
+
+static struct cmc_dpram_ipc_map cmc_ipc_map;
+static u8 *cmc_sfr_base;
+static struct cmc221_idpram_sfr cmc_sfr;
+
+/* Function prototypes */
+static void cmc_idpram_reset(void);
+static void cmc_idpram_setup_speed(enum dpram_speed);
+static int  cmc_idpram_wakeup(void);
+static void cmc_idpram_sleep(void);
+static void cmc_idpram_clr_intr(void);
+static u16  cmc_idpram_recv_intr(void);
+static void cmc_idpram_send_intr(u16 irq_mask);
+static u16  cmc_idpram_recv_msg(void);
+static void cmc_idpram_send_msg(u16 msg);
+
+static u16  cmc_idpram_get_magic(void);
+static void cmc_idpram_set_magic(u16 value);
+static u16  cmc_idpram_get_access(void);
+static void cmc_idpram_set_access(u16 value);
+
+static u32  cmc_idpram_get_tx_head(int dev_id);
+static u32  cmc_idpram_get_tx_tail(int dev_id);
+static void cmc_idpram_set_tx_head(int dev_id, u32 head);
+static void cmc_idpram_set_tx_tail(int dev_id, u32 tail);
+static u8 __iomem *cmc_idpram_get_tx_buff(int dev_id);
+static u32  cmc_idpram_get_tx_buff_size(int dev_id);
+
+static u32  cmc_idpram_get_rx_head(int dev_id);
+static u32  cmc_idpram_get_rx_tail(int dev_id);
+static void cmc_idpram_set_rx_head(int dev_id, u32 head);
+static void cmc_idpram_set_rx_tail(int dev_id, u32 tail);
+static u8 __iomem *cmc_idpram_get_rx_buff(int dev_id);
+static u32  cmc_idpram_get_rx_buff_size(int dev_id);
+
+static u16  cmc_idpram_get_mask_req_ack(int dev_id);
+static u16  cmc_idpram_get_mask_res_ack(int dev_id);
+static u16  cmc_idpram_get_mask_send(int dev_id);
+
+static struct modemlink_dpram_control cmc_idpram_ctrl = {
+	.reset = cmc_idpram_reset,
+
+	.setup_speed = cmc_idpram_setup_speed,
+
+	.wakeup = cmc_idpram_wakeup,
+	.sleep  = cmc_idpram_sleep,
+
+	.clear_intr = cmc_idpram_clr_intr,
+	.recv_intr  = cmc_idpram_recv_intr,
+	.send_intr  = cmc_idpram_send_intr,
+	.recv_msg   = cmc_idpram_recv_msg,
+	.send_msg   = cmc_idpram_send_msg,
+
+	.get_magic  = cmc_idpram_get_magic,
+	.set_magic  = cmc_idpram_set_magic,
+	.get_access = cmc_idpram_get_access,
+	.set_access = cmc_idpram_set_access,
+
+	.get_tx_head = cmc_idpram_get_tx_head,
+	.get_tx_tail = cmc_idpram_get_tx_tail,
+	.set_tx_head = cmc_idpram_set_tx_head,
+	.set_tx_tail = cmc_idpram_set_tx_tail,
+	.get_tx_buff = cmc_idpram_get_tx_buff,
+	.get_tx_buff_size = cmc_idpram_get_tx_buff_size,
+
+	.get_rx_head = cmc_idpram_get_rx_head,
+	.get_rx_tail = cmc_idpram_get_rx_tail,
+	.set_rx_head = cmc_idpram_set_rx_head,
+	.set_rx_tail = cmc_idpram_set_rx_tail,
+	.get_rx_buff = cmc_idpram_get_rx_buff,
+	.get_rx_buff_size = cmc_idpram_get_rx_buff_size,
+
+	.get_mask_req_ack = cmc_idpram_get_mask_req_ack,
+	.get_mask_res_ack = cmc_idpram_get_mask_res_ack,
+	.get_mask_send    = cmc_idpram_get_mask_send,
+
+	.dp_base = NULL,
+	.dp_size = 0,
+	.dp_type = CP_IDPRAM,
+	.aligned = 1,
+
+	.dpram_irq        = CMC_IDPRAM_INT_IRQ_00,
+	.dpram_irq_flags  = (IRQF_NO_SUSPEND | IRQF_TRIGGER_RISING),
+	.dpram_irq_name   = "CMC221_IDPRAM_IRQ",
+	.dpram_wlock_name = "CMC221_IDPRAM_WLOCK",
+
+	.max_ipc_dev = MAX_CMC_IDPRAM_IPC_DEV,
+};
+
+/*
+** UMTS target platform data
+*/
+static struct modem_io_t umts_io_devices[] = {
+	[0] = {
+		.name = "umts_boot0",
+		.id = 0x0,
+		.format = IPC_BOOT,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[1] = {
+		.name = "umts_ipc0",
+		.id = 0x0,
+		.format = IPC_FMT,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[2] = {
+		.name = "umts_rfs0",
+		.id = 0x0,
+		.format = IPC_RFS,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[3] = {
+		.name = "umts_multipdp",
+		.id = 0x1,
+		.format = IPC_MULTI_RAW,
+		.io_type = IODEV_DUMMY,
+		/* .links = LINKTYPE(LINKDEV_DPRAM) | LINKTYPE(LINKDEV_USB), */
+		.links = LINKTYPE(LINKDEV_DPRAM),
+		.tx_link = LINKDEV_DPRAM,
+	},
+	[4] = {
+		.name = "rmnet0",
+		.id = 0x2A,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[5] = {
+		.name = "rmnet1",
+		.id = 0x2B,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[6] = {
+		.name = "rmnet2",
+		.id = 0x2C,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[7] = {
+		.name = "rmnet3",
+		.id = 0x2D,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[8] = {
+		.name = "umts_rmnet4",
+		.id = 0x27,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[9] = {
+		.name = "umts_rmnet5",
+		.id = 0x3A,
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[10] = {
+		.name = "umts_router",	/* AT Iface & Dial-up */
+		.id = 0x3E,		/* Channel 30 (0x3E & 0x1F) */
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[11] = {
+		.name = "umts_csd",
+		.id = 0x21,
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[12] = {
+		.name = "umts_ramdump0",
+		.id = 0x0,
+		.format = IPC_RAMDUMP,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[13] = {
+		.name = "umts_loopback0",
+		.id = 0x0,
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[14] = {
+		.name = "umts_dm0",	/* DM Port */
+		.id = 0x3F,		/* Channel 31 (0x3F & 0x1F) */
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+/*
+	[15] = {
+		.name = "lte_ipc0",
+		.id = 0x1,
+		.format = IPC_FMT,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_USB),
+	},
+*/
+};
+
+/*
+static int exynos_cpu_frequency_lock(void);
+static int exynos_cpu_frequency_unlock(void);
+*/
+
+static struct modemlink_pm_data umts_link_pm_data = {
+	.name = "umts_link_pm",
+
+	.gpio_link_enable    = 0,
+	/*
+	.gpio_link_active    = GPIO_ACTIVE_STATE,
+	.gpio_link_hostwake  = GPIO_IPC_HOST_WAKEUP,
+	.gpio_link_slavewake = GPIO_IPC_SLAVE_WAKEUP,
+
+	.port_enable = host_port_enable,
+
+	.link_reconnect = umts_link_reconnect,
+	*/
+	.freqlock = ATOMIC_INIT(0),
+	/*
+	.cpufreq_lock = exynos_cpu_frequency_lock,
+	.cpufreq_unlock = exynos_cpu_frequency_unlock,
+	*/
+};
+
+static struct modem_data umts_modem_data = {
+	.name = "cmc221",
+
+	.gpio_cp_on        = CP_CMC221_PMIC_PWRON,
+	.gpio_cp_reset     = CP_CMC221_CPU_RST,
+	.gpio_phone_active = GPIO_LTE_ACTIVE,
+
+	.gpio_dpram_int    = GPIO_CMC_IDPRAM_INT_00,
+	.gpio_dpram_status = GPIO_CMC_IDPRAM_STATUS,
+	.gpio_dpram_wakeup = GPIO_CMC_IDPRAM_WAKEUP,
+	/*
+	.gpio_slave_wakeup = GPIO_IPC_SLAVE_WAKEUP,
+	.gpio_host_active  = GPIO_ACTIVE_STATE,
+	.gpio_host_wakeup  = GPIO_IPC_HOST_WAKEUP,
+	*/
+	.modem_net  = UMTS_NETWORK,
+	.modem_type = SEC_CMC221,
+	/* .link_types = LINKTYPE(LINKDEV_DPRAM) | LINKTYPE(LINKDEV_USB), */
+	.link_types = LINKTYPE(LINKDEV_DPRAM),
+	.link_name  = "cmc221_idpram",
+	.dpram_ctl  = &cmc_idpram_ctrl,
+
+	.num_iodevs = ARRAY_SIZE(umts_io_devices),
+	.iodevs     = umts_io_devices,
+
+	.link_pm_data = &umts_link_pm_data,
+
+	.ipc_version = SIPC_VER_41,
+};
+
+static struct resource umts_modem_res[] = {
+	[0] = {
+		.name  = "cp_active_irq",
+		.start = LTE_ACTIVE_IRQ,
+		.end   = LTE_ACTIVE_IRQ,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device umts_modem = {
+	.name = "modem_if",
+	.id = 1,
+	.num_resources = ARRAY_SIZE(umts_modem_res),
+	.resource = umts_modem_res,
+	.dev = {
+		.platform_data = &umts_modem_data,
+	},
+};
+
+#define HUB_STATE_OFF 0
+#if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB)
+void set_hsic_lpa_states(int states)
+{
+	int val = gpio_get_value(umts_modem_data.gpio_cp_reset);
+
+	mif_trace("\n");
+
+	if (val && states == STATE_HSIC_LPA_ENTER) {
+		pr_info("mif: usb3503: %s: hub off - lpa\n", __func__);
+		host_port_enable(2, 0);
+		*(umts_link_pm_data.p_hub_status) = HUB_STATE_OFF;
+	}
+}
+#endif
+
+int get_cp_active_state(void)
+{
+	return gpio_get_value(umts_modem_data.gpio_phone_active);
+}
+
+static void cmc_idpram_reset(void)
+{
+	iowrite16(1, cmc_sfr.reset);
+}
+
+static void cmc_idpram_setup_speed(enum dpram_speed speed)
+{
+	setup_dpram_speed(cmc_idpram_cfg.csn, &cmc_idpram_access_cfg[speed]);
+}
+
+static int cmc_idpram_wakeup(void)
+{
+	int cnt = 0;
+	u16 magic = 0;
+	u16 access = 0;
+
+	gpio_set_value(umts_modem_data.gpio_dpram_wakeup, 1);
+
+	cnt = 0;
+	while (!gpio_get_value(umts_modem_data.gpio_dpram_status)) {
+		if (cnt++ > 10) {
+			pr_err("[MDM/E] <%s> gpio_dpram_status == 0\n",
+				__func__);
+			break;	/* return -EAGAIN; */
+		}
+
+		if (in_interrupt())
+			mdelay(1);
+		else
+			msleep_interruptible(1);
+	}
+
+	return 0;
+}
+
+static void cmc_idpram_sleep(void)
+{
+	gpio_set_value(umts_modem_data.gpio_dpram_wakeup, 0);
+}
+
+static void cmc_idpram_clr_intr(void)
+{
+	iowrite16(0xFFFF, cmc_sfr.clr_int2ap);
+	iowrite16(0, cmc_sfr.int2ap);
+}
+
+static u16 cmc_idpram_recv_intr(void)
+{
+	return ioread16(cmc_sfr.int2ap);
+}
+
+static void cmc_idpram_send_intr(u16 irq_mask)
+{
+	iowrite16(irq_mask, cmc_sfr.int2cp);
+}
+
+static u16 cmc_idpram_recv_msg(void)
+{
+	return ioread16(cmc_sfr.msg2ap);
+}
+
+static void cmc_idpram_send_msg(u16 msg)
+{
+	iowrite16(msg, cmc_sfr.msg2cp);
+}
+
+static u16 cmc_idpram_get_magic(void)
+{
+	return ioread16(cmc_ipc_map.magic);
+}
+
+static void cmc_idpram_set_magic(u16 value)
+{
+	iowrite16(value, cmc_ipc_map.magic);
+}
+
+static u16 cmc_idpram_get_access(void)
+{
+	return ioread16(cmc_ipc_map.access);
+}
+
+static void cmc_idpram_set_access(u16 value)
+{
+	iowrite16(value, cmc_ipc_map.access);
+}
+
+static u32 cmc_idpram_get_tx_head(int dev_id)
+{
+	return ioread32(cmc_ipc_map.dev[dev_id].txq.head);
+}
+
+static u32 cmc_idpram_get_tx_tail(int dev_id)
+{
+	return ioread32(cmc_ipc_map.dev[dev_id].txq.tail);
+}
+
+static void cmc_idpram_set_tx_head(int dev_id, u32 head)
+{
+	int cnt = 100;
+	u32 val = 0;
+
+	iowrite32(head, cmc_ipc_map.dev[dev_id].txq.head);
+
+	do {
+		/* Check head value written */
+		val = ioread32(cmc_ipc_map.dev[dev_id].txq.head);
+		if (val == head)
+			break;
+
+		pr_err("[MDM/E] <%s> txq.head(%d) != head(%d)\n",
+			__func__, val, head);
+
+		/* Write head value again */
+		iowrite32(head, cmc_ipc_map.dev[dev_id].txq.head);
+	} while (cnt--);
+}
+
+static void cmc_idpram_set_tx_tail(int dev_id, u32 tail)
+{
+	int cnt = 100;
+	u32 val = 0;
+
+	iowrite32(tail, cmc_ipc_map.dev[dev_id].txq.tail);
+
+	do {
+		/* Check tail value written */
+		val = ioread32(cmc_ipc_map.dev[dev_id].txq.tail);
+		if (val == tail)
+			break;
+
+		pr_err("[MDM/E] <%s> txq.tail(%d) != tail(%d)\n",
+			__func__, val, tail);
+
+		/* Write tail value again */
+		iowrite32(tail, cmc_ipc_map.dev[dev_id].txq.tail);
+	} while (cnt--);
+}
+
+static u8 __iomem *cmc_idpram_get_tx_buff(int dev_id)
+{
+	return cmc_ipc_map.dev[dev_id].txq.buff;
+}
+
+static u32 cmc_idpram_get_tx_buff_size(int dev_id)
+{
+	return cmc_ipc_map.dev[dev_id].txq.size;
+}
+
+static u32 cmc_idpram_get_rx_head(int dev_id)
+{
+	return ioread32(cmc_ipc_map.dev[dev_id].rxq.head);
+}
+
+static u32 cmc_idpram_get_rx_tail(int dev_id)
+{
+	return ioread32(cmc_ipc_map.dev[dev_id].rxq.tail);
+}
+
+static void cmc_idpram_set_rx_head(int dev_id, u32 head)
+{
+	int cnt = 100;
+	u32 val = 0;
+
+	iowrite32(head, cmc_ipc_map.dev[dev_id].rxq.head);
+
+	do {
+		/* Check head value written */
+		val = ioread32(cmc_ipc_map.dev[dev_id].rxq.head);
+		if (val == head)
+			break;
+
+		pr_err("[MDM/E] <%s> rxq.head(%d) != head(%d)\n",
+			__func__, val, head);
+
+		/* Write head value again */
+		iowrite32(head, cmc_ipc_map.dev[dev_id].rxq.head);
+	} while (cnt--);
+}
+
+static void cmc_idpram_set_rx_tail(int dev_id, u32 tail)
+{
+	int cnt = 100;
+	u32 val = 0;
+
+	iowrite32(tail, cmc_ipc_map.dev[dev_id].rxq.tail);
+
+	do {
+		/* Check tail value written */
+		val = ioread32(cmc_ipc_map.dev[dev_id].rxq.tail);
+		if (val == tail)
+			break;
+
+		pr_err("[MDM/E] <%s> rxq.tail(%d) != tail(%d)\n",
+			__func__, val, tail);
+
+		/* Write tail value again */
+		iowrite32(tail, cmc_ipc_map.dev[dev_id].rxq.tail);
+	} while (cnt--);
+}
+
+static u8 __iomem *cmc_idpram_get_rx_buff(int dev_id)
+{
+	return cmc_ipc_map.dev[dev_id].rxq.buff;
+}
+
+static u32 cmc_idpram_get_rx_buff_size(int dev_id)
+{
+	return cmc_ipc_map.dev[dev_id].rxq.size;
+}
+
+static u16 cmc_idpram_get_mask_req_ack(int dev_id)
+{
+	return cmc_ipc_map.dev[dev_id].mask_req_ack;
+}
+
+static u16 cmc_idpram_get_mask_res_ack(int dev_id)
+{
+	return cmc_ipc_map.dev[dev_id].mask_res_ack;
+}
+
+static u16 cmc_idpram_get_mask_send(int dev_id)
+{
+	return cmc_ipc_map.dev[dev_id].mask_send;
+}
+
+/* Set dynamic environment for a modem */
+static void setup_umts_modem_env(void)
+{
+	/* Config DPRAM control structure */
+	cmc_idpram_cfg.csn  = 0;
+	cmc_idpram_cfg.addr = SROM_CS0_BASE + (SROM_WIDTH * cmc_idpram_cfg.csn);
+	cmc_idpram_cfg.end  = cmc_idpram_cfg.addr + cmc_idpram_cfg.size - 1;
+
+	umts_modem_data.gpio_dpram_int = GPIO_CMC_IDPRAM_INT_00;
+}
+
+static void config_umts_modem_gpio(void)
+{
+	int err = 0;
+	unsigned gpio_cp_on        = umts_modem_data.gpio_cp_on;
+	unsigned gpio_cp_rst       = umts_modem_data.gpio_cp_reset;
+	unsigned gpio_pda_active   = umts_modem_data.gpio_pda_active;
+	unsigned gpio_phone_active = umts_modem_data.gpio_phone_active;
+	unsigned gpio_active_state = umts_modem_data.gpio_host_active;
+	unsigned gpio_host_wakeup  = umts_modem_data.gpio_host_wakeup;
+	unsigned gpio_slave_wakeup = umts_modem_data.gpio_slave_wakeup;
+	unsigned gpio_dpram_int    = umts_modem_data.gpio_dpram_int;
+	unsigned gpio_dpram_status = umts_modem_data.gpio_dpram_status;
+	unsigned gpio_dpram_wakeup = umts_modem_data.gpio_dpram_wakeup;
+
+	pr_info("[MDM] <%s>\n", __func__);
+
+	if (gpio_cp_on) {
+		err = gpio_request(gpio_cp_on, "CMC_ON");
+		if (err) {
+			pr_err("fail to request gpio %s\n", "CMC_ON");
+		} else {
+			gpio_direction_output(gpio_cp_on, 0);
+			s3c_gpio_setpull(gpio_cp_on, S3C_GPIO_PULL_NONE);
+		}
+	}
+
+	if (gpio_cp_rst) {
+		err = gpio_request(gpio_cp_rst, "CMC_RST");
+		if (err) {
+			pr_err("fail to request gpio %s\n", "CMC_RST");
+		} else {
+			gpio_direction_output(gpio_cp_rst, 0);
+			s3c_gpio_setpull(gpio_cp_rst, S3C_GPIO_PULL_NONE);
+		}
+	}
+
+	if (gpio_pda_active) {
+		err = gpio_request(gpio_pda_active, "PDA_ACTIVE");
+		if (err) {
+			pr_err("fail to request gpio %s\n", "PDA_ACTIVE");
+		} else {
+			gpio_direction_output(gpio_pda_active, 0);
+			s3c_gpio_setpull(gpio_pda_active, S3C_GPIO_PULL_NONE);
+		}
+	}
+
+	if (gpio_phone_active) {
+		err = gpio_request(gpio_phone_active, "CMC_ACTIVE");
+		if (err) {
+			pr_err("fail to request gpio %s\n", "CMC_ACTIVE");
+		} else {
+			s3c_gpio_cfgpin(gpio_phone_active, S3C_GPIO_SFN(0xF));
+			s3c_gpio_setpull(gpio_phone_active, S3C_GPIO_PULL_NONE);
+		}
+	}
+
+	if (gpio_active_state) {
+		err = gpio_request(gpio_active_state, "CMC_ACTIVE_STATE");
+		if (err) {
+			pr_err("fail to request gpio %s\n", "CMC_ACTIVE_STATE");
+		} else {
+			gpio_direction_output(gpio_active_state, 0);
+			s3c_gpio_setpull(gpio_active_state, S3C_GPIO_PULL_NONE);
+		}
+	}
+
+	if (gpio_slave_wakeup) {
+		err = gpio_request(gpio_slave_wakeup, "CMC_SLAVE_WAKEUP");
+		if (err) {
+			pr_err("fail to request gpio %s\n", "CMC_SLAVE_WAKEUP");
+		} else {
+			gpio_direction_output(gpio_slave_wakeup, 0);
+			s3c_gpio_setpull(gpio_slave_wakeup, S3C_GPIO_PULL_NONE);
+		}
+	}
+
+	if (gpio_host_wakeup) {
+		err = gpio_request(gpio_host_wakeup, "CMC_HOST_WAKEUP");
+		if (err) {
+			pr_err("fail to request gpio %s\n", "CMC_HOST_WAKEUP");
+		} else {
+			s3c_gpio_cfgpin(gpio_host_wakeup, S3C_GPIO_SFN(0xF));
+			s3c_gpio_setpull(gpio_host_wakeup, S3C_GPIO_PULL_DOWN);
+		}
+	}
+
+	if (gpio_dpram_int) {
+		err = gpio_request(gpio_dpram_int, "CMC_DPRAM_INT");
+		if (err) {
+			pr_err("fail to request gpio %s\n", "CMC_DPRAM_INT");
+		} else {
+			/* Configure as a wake-up source */
+			s3c_gpio_cfgpin(gpio_dpram_int, S3C_GPIO_SFN(0xF));
+			s3c_gpio_setpull(gpio_dpram_int, S3C_GPIO_PULL_NONE);
+		}
+	}
+
+	if (gpio_dpram_status) {
+		err = gpio_request(gpio_dpram_status, "CMC_DPRAM_STATUS");
+		if (err) {
+			pr_err("fail to request gpio %s\n", "CMC_DPRAM_STATUS");
+		} else {
+			/* Configure as a wake-up source */
+			s3c_gpio_cfgpin(gpio_dpram_status, S3C_GPIO_SFN(0xF));
+			s3c_gpio_setpull(gpio_dpram_status, S3C_GPIO_PULL_NONE);
+		}
+	}
+
+	if (gpio_dpram_wakeup) {
+		err = gpio_request(gpio_dpram_wakeup, "CMC_DPRAM_WAKEUP");
+		if (err) {
+			pr_err("fail to request gpio %s\n", "CMC_DPRAM_WAKEUP");
+		} else {
+			gpio_direction_output(gpio_dpram_wakeup, 1);
+			s3c_gpio_setpull(gpio_dpram_wakeup, S3C_GPIO_PULL_NONE);
+		}
+	}
+}
+
+static u8 *cmc_idpram_remap_mem_region(struct sromc_cfg *cfg)
+{
+	int			 dp_addr = 0;
+	int			 dp_size = 0;
+	u8 __iomem              *dp_base = NULL;
+	struct dpram_ipc_cfg    *ipc_map = NULL;
+	struct cmc_dpram_ipc_device *dev = NULL;
+
+	dp_addr = cfg->addr;
+	dp_size = cfg->size;
+
+	dp_base = (u8 *)ioremap_nocache(dp_addr, dp_size);
+	if (!dp_base) {
+		pr_err("[MDM] <%s> dpram base ioremap fail\n", __func__);
+		return NULL;
+	}
+	pr_info("[MDM] <%s> DPRAM VA=0x%08X\n", __func__, (int)dp_base);
+
+	cmc_sfr_base = (u8 *)ioremap_nocache((dp_addr + dp_size), dp_size);
+	if (cmc_sfr_base == NULL) {
+		pr_err("[MDM] <%s> Failed in ioremap_nocache()\n", __func__);
+		return NULL;
+	}
+
+	cmc_sfr.int2cp     = (u16 __iomem *)(cmc_sfr_base + CMC_INT2CP_REG);
+	cmc_sfr.int2ap     = (u16 __iomem *)(cmc_sfr_base + CMC_INT2AP_REG);
+	cmc_sfr.clr_int2ap = (u16 __iomem *)(cmc_sfr_base + CMC_CLR_INT_REG);
+	cmc_sfr.reset      = (u16 __iomem *)(cmc_sfr_base + CMC_RESET_REG);
+	cmc_sfr.msg2cp     = (u16 __iomem *)(cmc_sfr_base + CMC_PUT_REG);
+	cmc_sfr.msg2ap     = (u16 __iomem *)(cmc_sfr_base + CMC_GET_REG);
+
+
+	cmc_idpram_ctrl.dp_base = (u8 __iomem *)dp_base;
+	cmc_idpram_ctrl.dp_size = dp_size;
+
+	/* Map for IPC */
+	ipc_map = (struct dpram_ipc_cfg *)dp_base;
+
+	/* Magic code and access enable fields */
+	cmc_ipc_map.magic  = (u16 __iomem *)&ipc_map->magic;
+	cmc_ipc_map.access = (u16 __iomem *)&ipc_map->access;
+
+	/* FMT */
+	dev = &cmc_ipc_map.dev[IPC_FMT];
+
+	strcpy(dev->name, "FMT");
+	dev->id = IPC_FMT;
+
+	dev->txq.head = (u32 __iomem *)&ipc_map->fmt_tx_head;
+	dev->txq.tail = (u32 __iomem *)&ipc_map->fmt_tx_tail;
+	dev->txq.buff = (u8 __iomem *)&ipc_map->fmt_tx_buff[0];
+	dev->txq.size = DP_FMT_TX_BUFF_SZ;
+
+	dev->rxq.head = (u32 __iomem *)&ipc_map->fmt_rx_head;
+	dev->rxq.tail = (u32 __iomem *)&ipc_map->fmt_rx_tail;
+	dev->rxq.buff = (u8 __iomem *)&ipc_map->fmt_rx_buff[0];
+	dev->rxq.size = DP_FMT_RX_BUFF_SZ;
+
+	dev->mask_req_ack = INT_MASK_REQ_ACK_F;
+	dev->mask_res_ack = INT_MASK_RES_ACK_F;
+	dev->mask_send    = INT_MASK_SEND_F;
+
+	/* RAW */
+	dev = &cmc_ipc_map.dev[IPC_RAW];
+
+	strcpy(dev->name, "RAW");
+	dev->id = IPC_RAW;
+
+	dev->txq.head = (u32 __iomem *)&ipc_map->raw_tx_head;
+	dev->txq.tail = (u32 __iomem *)&ipc_map->raw_tx_tail;
+	dev->txq.buff = (u8 __iomem *)&ipc_map->raw_tx_buff[0];
+	dev->txq.size = DP_RAW_TX_BUFF_SZ;
+
+	dev->rxq.head = (u32 __iomem *)&ipc_map->raw_rx_head;
+	dev->rxq.tail = (u32 __iomem *)&ipc_map->raw_rx_tail;
+	dev->rxq.buff = (u8 __iomem *)&ipc_map->raw_rx_buff[0];
+	dev->rxq.size = DP_RAW_RX_BUFF_SZ;
+
+	dev->mask_req_ack = INT_MASK_REQ_ACK_R;
+	dev->mask_res_ack = INT_MASK_RES_ACK_R;
+	dev->mask_send    = INT_MASK_SEND_R;
+
+	/* RFS */
+	dev = &cmc_ipc_map.dev[IPC_RFS];
+
+	strcpy(dev->name, "RFS");
+	dev->id = IPC_RFS;
+
+	dev->txq.head = (u32 __iomem *)&ipc_map->rfs_tx_head;
+	dev->txq.tail = (u32 __iomem *)&ipc_map->rfs_tx_tail;
+	dev->txq.buff = (u8 __iomem *)&ipc_map->rfs_tx_buff[0];
+	dev->txq.size = DP_RFS_TX_BUFF_SZ;
+
+	dev->rxq.head = (u32 __iomem *)&ipc_map->rfs_rx_head;
+	dev->rxq.tail = (u32 __iomem *)&ipc_map->rfs_rx_tail;
+	dev->rxq.buff = (u8 __iomem *)&ipc_map->rfs_rx_buff[0];
+	dev->rxq.size = DP_RFS_RX_BUFF_SZ;
+
+	dev->mask_req_ack = INT_MASK_REQ_ACK_RFS;
+	dev->mask_res_ack = INT_MASK_RES_ACK_RFS;
+	dev->mask_send    = INT_MASK_SEND_RFS;
+
+	return dp_base;
+}
+
+/**
+ *	DPRAM GPIO settings
+ *
+ *	SROM_NUM_ADDR_BITS value indicate the address line number or
+ *	the mux/demux dpram type. if you want to set mux mode, define the
+ *	SROM_NUM_ADDR_BITS to zero.
+ *
+ *	for CMC22x
+ *	CMC22x has 16KB + a SFR register address.
+ *	It used 14 bits (13bits for 16KB word address and 1 bit for SFR
+ *	register)
+ */
+static void config_dpram_port_gpio(void)
+{
+	int addr_bits = SROM_NUM_ADDR_BITS;
+
+	pr_info("[MDM] <%s> address line = %d bits\n", __func__, addr_bits);
+
+	/*
+	** Config DPRAM address/data GPIO pins
+	*/
+
+	/* Set GPIO for address bus (13 ~ 14 bits) */
+	switch (addr_bits) {
+	case 0:
+		break;
+
+	case 13 ... 14:
+		s3c_gpio_cfgrange_nopull(GPIO_SROM_ADDR_BUS_LOW,
+			EXYNOS4_GPIO_Y3_NR, S3C_GPIO_SFN(2));
+		s3c_gpio_cfgrange_nopull(GPIO_SROM_ADDR_BUS_HIGH,
+			(addr_bits - EXYNOS4_GPIO_Y3_NR), S3C_GPIO_SFN(2));
+		break;
+
+	default:
+		pr_err("[MDM/E] <%s> Invalid addr_bits!!!\n", __func__);
+		return;
+	}
+
+	/* Set GPIO for data bus (16 bits) */
+	s3c_gpio_cfgrange_nopull(GPIO_SROM_DATA_BUS_LOW, 8, S3C_GPIO_SFN(2));
+	s3c_gpio_cfgrange_nopull(GPIO_SROM_DATA_BUS_HIGH, 8, S3C_GPIO_SFN(2));
+
+	/* Setup SROMC CSn pins */
+	s3c_gpio_cfgpin(GPIO_DPRAM_CSN0, S3C_GPIO_SFN(2));
+
+	/* Config OEn, WEn */
+	s3c_gpio_cfgpin(GPIO_DPRAM_REN, S3C_GPIO_SFN(2));
+	s3c_gpio_cfgpin(GPIO_DPRAM_WEN, S3C_GPIO_SFN(2));
+}
+
+static void init_sromc(void)
+{
+	struct clk *clk = NULL;
+
+	/* SROMC clk enable */
+	clk = clk_get(NULL, "sromc");
+	if (!clk) {
+		pr_err("[MDM/E] <%s> SROMC clock gate fail\n", __func__);
+		return;
+	}
+	clk_enable(clk);
+}
+
+static void setup_sromc
+(
+	unsigned csn,
+	struct sromc_cfg *cfg,
+	struct sromc_access_cfg *acc_cfg
+)
+{
+	unsigned bw = 0;	/* Bus width and wait control	*/
+	unsigned bc = 0;	/* Vank control			*/
+	void __iomem *bank_sfr = S5P_SROM_BC0 + (4 * csn);
+
+	pr_err("[MDM] <%s> SROMC settings for CS%d...\n", __func__, csn);
+
+	bw = __raw_readl(S5P_SROM_BW);
+	bc = __raw_readl(bank_sfr);
+	pr_err("[MDM] <%s> Old SROMC settings = BW(0x%08X), BC%d(0x%08X)\n",
+		__func__, bw, csn, bc);
+
+	/* Set the BW control field for the CSn */
+	bw &= ~(SROMC_MASK << (csn << 2));
+	bw |= (cfg->attr << (csn << 2));
+	writel(bw, S5P_SROM_BW);
+
+	/* Set SROMC memory access timing for the CSn */
+	bc = acc_cfg->tacs | acc_cfg->tcos | acc_cfg->tacc |
+	     acc_cfg->tcoh | acc_cfg->tcah | acc_cfg->tacp | acc_cfg->pmc;
+
+	writel(bc, bank_sfr);
+
+	/* Verify SROMC settings */
+	bw = __raw_readl(S5P_SROM_BW);
+	bc = __raw_readl(bank_sfr);
+	pr_err("[MDM] <%s> New SROMC settings = BW(0x%08X), BC%d(0x%08X)\n",
+		__func__, bw, csn, bc);
+}
+
+static void setup_dpram_speed(unsigned csn, struct sromc_access_cfg *acc_cfg)
+{
+	void __iomem *bank_sfr = S5P_SROM_BC0 + (4 * csn);
+	unsigned bc = 0;
+
+	bc = __raw_readl(bank_sfr);
+	pr_info("[MDM] <%s> Old CS%d setting = 0x%08X\n", __func__, csn, bc);
+
+	/* SROMC memory access timing setting */
+	bc = acc_cfg->tacs | acc_cfg->tcos | acc_cfg->tacc |
+	     acc_cfg->tcoh | acc_cfg->tcah | acc_cfg->tacp | acc_cfg->pmc;
+	writel(bc, bank_sfr);
+
+	bc = __raw_readl(bank_sfr);
+	pr_info("[MDM] <%s> New CS%d setting = 0x%08X\n", __func__, csn, bc);
+}
+
+static int __init init_modem(void)
+{
+	struct sromc_cfg *cfg = NULL;
+	struct sromc_access_cfg *acc_cfg = NULL;
+
+	pr_err("[MODEM_IF] <%s> System Revision = %d\n", __func__, system_rev);
+
+	setup_umts_modem_env();
+
+	config_dpram_port_gpio();
+
+	config_umts_modem_gpio();
+
+	init_sromc();
+
+	cfg = &cmc_idpram_cfg;
+	acc_cfg = &cmc_idpram_access_cfg[DPRAM_SPEED_LOW];
+
+	setup_sromc(cfg->csn, cfg, acc_cfg);
+
+	if (!cmc_idpram_remap_mem_region(&cmc_idpram_cfg))
+		return -1;
+
+	platform_device_register(&umts_modem);
+
+	pr_err("[MODEM_IF] %s: DONE!!\n", __func__);
+	return 0;
+}
+late_initcall(init_modem);
+/*device_initcall(init_modem);*/
+
+
+
+
+
+
+#ifdef CONFIG_USBHUB_USB3503
+static int (*usbhub_set_mode)(struct usb3503_hubctl *, int);
+static struct usb3503_hubctl *usbhub_ctl;
+
+#ifdef CONFIG_EXYNOS4_CPUFREQ
+static int exynos_cpu_frequency_lock(void)
+{
+	unsigned int level, freq = 700;
+
+	if (atomic_read(&umts_link_pm_data.freqlock) == 0) {
+		if (exynos_cpufreq_get_level(freq * 1000, &level)) {
+			pr_err("[MIF] exynos_cpufreq_get_level is fail\n");
+			return -EINVAL;
+		}
+
+		if (exynos_cpufreq_lock(DVFS_LOCK_ID_USB_IF, level)) {
+			pr_err("[MIF] exynos_cpufreq_lock is fail\n");
+			return -EINVAL;
+		}
+
+		atomic_set(&umts_link_pm_data.freqlock, 1);
+		pr_debug("[MIF] %s: <%d>%dMHz\n", __func__, level, freq);
+	}
+	return 0;
+}
+
+static int exynos_cpu_frequency_unlock(void)
+{
+	if (atomic_read(&umts_link_pm_data.freqlock) == 1) {
+		exynos_cpufreq_lock_free(DVFS_LOCK_ID_USB_IF);
+		atomic_set(&umts_link_pm_data.freqlock, 0);
+		pr_debug("[MIF] %s\n", __func__);
+	}
+	return 0;
+}
+#else /* for CONFIG_EXYNOS4_CPUFREQ */
+static int exynos_cpu_frequency_lock(void)
+{
+	return 0;
+}
+
+static int exynos_cpu_frequency_unlock(void)
+{
+	return 0;
+}
+#endif /* for CONFIG_EXYNOS4_CPUFREQ */
+
+void set_host_states(struct platform_device *pdev, int type)
+{
+}
+
+static int usb3503_hub_handler(void (*set_mode)(void), void *ctl)
+{
+	if (!set_mode || !ctl)
+		return -EINVAL;
+
+	usbhub_set_mode = (int (*)(struct usb3503_hubctl *, int))set_mode;
+	usbhub_ctl = (struct usb3503_hubctl *)ctl;
+
+	pr_info("[MDM] <%s> set_mode(%pF)\n", __func__, set_mode);
+
+	return 0;
+}
+
+static int usb3503_hw_config(void)
+{
+	int err;
+
+	err = gpio_request(GPIO_USB_HUB_RST, "HUB_RST");
+	if (err) {
+		pr_err("fail to request gpio %s\n", "HUB_RST");
+	} else {
+		gpio_direction_output(GPIO_USB_HUB_RST, 0);
+		s3c_gpio_setpull(GPIO_USB_HUB_RST, S3C_GPIO_PULL_NONE);
+	}
+	s5p_gpio_set_drvstr(GPIO_USB_HUB_RST, S5P_GPIO_DRVSTR_LV1);
+	/* need to check drvstr 1 or 2 */
+
+	/* for USB3503 26Mhz Reference clock setting */
+	err = gpio_request(GPIO_USB_HUB_INT, "HUB_INT");
+	if (err) {
+		pr_err("fail to request gpio %s\n", "HUB_INT");
+	} else {
+		gpio_direction_output(GPIO_USB_HUB_INT, 1);
+		s3c_gpio_setpull(GPIO_USB_HUB_INT, S3C_GPIO_PULL_NONE);
+	}
+
+	return 0;
+}
+
+static int usb3503_reset_n(int val)
+{
+	gpio_set_value(GPIO_USB_HUB_RST, 0);
+
+	/* hub off from cpuidle(LPA), skip the msleep schedule*/
+	if (val) {
+		msleep(20);
+		pr_info("[MDM] <%s> val = %d\n", __func__,
+			gpio_get_value(GPIO_USB_HUB_RST));
+		gpio_set_value(GPIO_USB_HUB_RST, !!val);
+
+		pr_info("[MDM] <%s> val = %d\n", __func__,
+			gpio_get_value(GPIO_USB_HUB_RST));
+
+		udelay(5); /* need it ?*/
+	}
+	return 0;
+}
+
+static struct usb3503_platform_data usb3503_pdata = {
+	.initial_mode = USB3503_MODE_STANDBY,
+	.reset_n = usb3503_reset_n,
+	.register_hub_handler = usb3503_hub_handler,
+	.port_enable = host_port_enable,
+};
+
+static struct i2c_board_info i2c_devs20_emul[] __initdata = {
+	{
+		I2C_BOARD_INFO(USB3503_I2C_NAME, 0x08),
+		.platform_data = &usb3503_pdata,
+	},
+};
+
+/* I2C20_EMUL */
+static struct i2c_gpio_platform_data i2c20_platdata = {
+	.sda_pin = GPIO_USB_HUB_SDA,
+	.scl_pin = GPIO_USB_HUB_SCL,
+	/*FIXME: need to timming tunning...  */
+	.udelay	= 20,
+};
+
+static struct platform_device s3c_device_i2c20 = {
+	.name = "i2c-gpio",
+	.id = 20,
+	.dev.platform_data = &i2c20_platdata,
+};
+
+static int __init init_usbhub(void)
+{
+	usb3503_hw_config();
+	i2c_register_board_info(20, i2c_devs20_emul,
+				ARRAY_SIZE(i2c_devs20_emul));
+
+	platform_device_register(&s3c_device_i2c20);
+	return 0;
+}
+
+device_initcall(init_usbhub);
+
+static int host_port_enable(int port, int enable)
+{
+	int err;
+
+	pr_info("[MDM] <%s> port(%d) control(%d)\n", __func__, port, enable);
+
+	if (enable) {
+		err = usbhub_set_mode(usbhub_ctl, USB3503_MODE_HUB);
+		if (err < 0) {
+			pr_err("[MDM] <%s> hub on fail\n", __func__);
+			goto exit;
+		}
+		err = s5p_ehci_port_control(&s5p_device_ehci, port, 1);
+		if (err < 0) {
+			pr_err("[MDM] <%s> port(%d) enable fail\n", __func__,
+				port);
+			goto exit;
+		}
+	} else {
+		err = s5p_ehci_port_control(&s5p_device_ehci, port, 0);
+		if (err < 0) {
+			pr_err("[MDM] <%s> port(%d) enable fail\n", __func__,
+				port);
+			goto exit;
+		}
+		err = usbhub_set_mode(usbhub_ctl, USB3503_MODE_STANDBY);
+		if (err < 0) {
+			pr_err("[MDM] <%s> hub off fail\n", __func__);
+			goto exit;
+		}
+	}
+
+	err = gpio_direction_output(umts_modem_data.gpio_host_active, enable);
+	pr_info("[MDM] <%s> active state err(%d), en(%d), level(%d)\n",
+		__func__, err, enable,
+		gpio_get_value(umts_modem_data.gpio_host_active));
+
+exit:
+	return err;
+}
+#else /* for CONFIG_USBHUB_USB3503 */
+void set_host_states(struct platform_device *pdev, int type)
+{
+	/*
+	if (active_ctl.gpio_initialized) {
+		pr_err(" [MODEM_IF] Active States =%d, %s\n", type, pdev->name);
+		gpio_direction_output(umts_link_pm_data.gpio_link_active,
+			type);
+	} else
+		active_ctl.gpio_request_host_active = 1;
+		*/
+	return;
+}
+#endif /* for CONFIG_USBHUB_USB3503 */
+
diff --git a/arch/arm/mach-exynos/board-gps-bcm475x.c b/arch/arm/mach-exynos/board-gps-bcm475x.c
new file mode 100644
index 0000000..7b9a1c7
--- /dev/null
+++ b/arch/arm/mach-exynos/board-gps-bcm475x.c
@@ -0,0 +1,69 @@
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <mach/gpio.h>
+#include <plat/gpio-cfg.h>
+#include <mach/board-gps.h>
+
+#if !defined(CONFIG_MACH_M0_GRANDECTC)
+
+static struct device *gps_dev;
+
+static int __init gps_bcm475x_init(void)
+{
+	int n_rst_pin = 0;
+	int n_rst_nc_pin = 0;
+	BUG_ON(!sec_class);
+	gps_dev = device_create(sec_class, NULL, 0, NULL, "gps");
+	BUG_ON(!gps_dev);
+
+	s3c_gpio_cfgpin(GPIO_GPS_RXD, S3C_GPIO_SFN(GPIO_GPS_RXD_AF));
+	s3c_gpio_setpull(GPIO_GPS_RXD, S3C_GPIO_PULL_UP);
+	s3c_gpio_cfgpin(GPIO_GPS_TXD, S3C_GPIO_SFN(GPIO_GPS_TXD_AF));
+	s3c_gpio_setpull(GPIO_GPS_TXD, S3C_GPIO_PULL_NONE);
+	s3c_gpio_cfgpin(GPIO_GPS_CTS, S3C_GPIO_SFN(GPIO_GPS_CTS_AF));
+	s3c_gpio_setpull(GPIO_GPS_CTS, S3C_GPIO_PULL_NONE);
+	s3c_gpio_cfgpin(GPIO_GPS_RTS, S3C_GPIO_SFN(GPIO_GPS_RTS_AF));
+	s3c_gpio_setpull(GPIO_GPS_RTS, S3C_GPIO_PULL_NONE);
+
+#ifdef CONFIG_MACH_P2
+	n_rst_pin = GPIO_GPS_nRST_28V;
+	n_rst_nc_pin = GPIO_GPS_nRST;
+#else
+	n_rst_pin = GPIO_GPS_nRST;
+	n_rst_nc_pin = 0;
+#endif
+
+	if (gpio_request(n_rst_pin, "GPS_nRST"))
+		WARN(1, "fail to request gpio (GPS_nRST)\n");
+
+	s3c_gpio_setpull(n_rst_pin, S3C_GPIO_PULL_UP);
+	s3c_gpio_cfgpin(n_rst_pin, S3C_GPIO_OUTPUT);
+	gpio_direction_output(n_rst_pin, 1);
+
+	if (gpio_request(GPIO_GPS_PWR_EN, "GPS_PWR_EN"))
+		WARN(1, "fail to request gpio (GPS_PWR_EN)\n");
+
+#ifdef CONFIG_MACH_P2
+	gpio_set_value(n_rst_nc_pin, 0);
+	s3c_gpio_cfgpin(n_rst_nc_pin, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(n_rst_nc_pin, S3C_GPIO_PULL_NONE);
+#endif
+
+	s3c_gpio_setpull(GPIO_GPS_PWR_EN, S3C_GPIO_PULL_NONE);
+	s3c_gpio_cfgpin(GPIO_GPS_PWR_EN, S3C_GPIO_OUTPUT);
+	gpio_direction_output(GPIO_GPS_PWR_EN, 0);
+
+	gpio_export(n_rst_pin, 1);
+	gpio_export(GPIO_GPS_PWR_EN, 1);
+
+	gpio_export_link(gps_dev, "GPS_nRST", n_rst_pin);
+	gpio_export_link(gps_dev, "GPS_PWR_EN", GPIO_GPS_PWR_EN);
+
+	return 0;
+}
+
+device_initcall(gps_bcm475x_init);
+
+#endif
diff --git a/arch/arm/mach-exynos/board-gps-gsd4t.c b/arch/arm/mach-exynos/board-gps-gsd4t.c
new file mode 100644
index 0000000..cabb9a7
--- /dev/null
+++ b/arch/arm/mach-exynos/board-gps-gsd4t.c
@@ -0,0 +1,90 @@
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <mach/gpio.h>
+#include <plat/gpio-cfg.h>
+#include <mach/board-gps.h>
+
+static struct device *gps_dev;
+
+static int __init gps_gsd4t_init(void)
+{
+	BUG_ON(!sec_class);
+	gps_dev = device_create(sec_class, NULL, 0, NULL, "gps");
+	BUG_ON(!gps_dev);
+
+	s3c_gpio_cfgpin(GPIO_GPS_RXD, S3C_GPIO_SFN(GPIO_GPS_RXD_AF));
+	s3c_gpio_setpull(GPIO_GPS_RXD, S3C_GPIO_PULL_UP);
+	s3c_gpio_cfgpin(GPIO_GPS_TXD, S3C_GPIO_SFN(GPIO_GPS_TXD_AF));
+	s3c_gpio_setpull(GPIO_GPS_TXD, S3C_GPIO_PULL_NONE);
+
+	if (gpio_request(GPIO_GPS_nRST, "GPS_nRST"))
+		WARN(1, "fail to request gpio (GPS_nRST)\n");
+
+	s3c_gpio_setpull(GPIO_GPS_nRST, S3C_GPIO_PULL_UP);
+	s3c_gpio_cfgpin(GPIO_GPS_nRST, S3C_GPIO_OUTPUT);
+	gpio_direction_output(GPIO_GPS_nRST, 1);
+
+#ifdef CONFIG_TARGET_LOCALE_NTT
+	if (system_rev >= 11) {
+		if (gpio_request(GPIO_GPS_PWR_EN, "GPS_PWR_EN"))
+			WARN(1, "fail to request gpio (GPS_PWR_EN)\n");
+		s3c_gpio_setpull(GPIO_GPS_PWR_EN, S3C_GPIO_PULL_NONE);
+		s3c_gpio_cfgpin(GPIO_GPS_PWR_EN, S3C_GPIO_OUTPUT);
+		gpio_direction_output(GPIO_GPS_PWR_EN, 0);
+
+		gpio_export(GPIO_GPS_nRST, 1);
+		gpio_export(GPIO_GPS_PWR_EN, 1);
+	} else {
+		if (gpio_request(GPIO_GPS_PWR_EN_SPI, "GPS_PWR_EN"))
+			WARN(1, "fail to request gpio (GPS_PWR_EN)\n");
+		s3c_gpio_setpull(GPIO_GPS_PWR_EN_SPI, S3C_GPIO_PULL_NONE);
+		s3c_gpio_cfgpin(GPIO_GPS_PWR_EN_SPI, S3C_GPIO_OUTPUT);
+		gpio_direction_output(GPIO_GPS_PWR_EN_SPI, 0);
+
+		gpio_export(GPIO_GPS_nRST, 1);
+		gpio_export(GPIO_GPS_PWR_EN_SPI, 1);
+	}
+#else
+	if (gpio_request(GPIO_GPS_PWR_EN, "GPS_PWR_EN"))
+		WARN(1, "fail to request gpio (GPS_PWR_EN)\n");
+
+	s3c_gpio_setpull(GPIO_GPS_PWR_EN, S3C_GPIO_PULL_NONE);
+	s3c_gpio_cfgpin(GPIO_GPS_PWR_EN, S3C_GPIO_OUTPUT);
+	gpio_direction_output(GPIO_GPS_PWR_EN, 0);
+
+	gpio_export(GPIO_GPS_nRST, 1);
+	gpio_export(GPIO_GPS_PWR_EN, 1);
+#endif
+
+#ifdef CONFIG_TARGET_LOCALE_KOR
+	if (system_rev >= 7) {
+		if (gpio_request(GPIO_GPS_RTS, "GPS_RTS"))
+			WARN(1, "fail to request gpio (GPS_RTS)\n");
+		s3c_gpio_setpull(GPIO_GPS_RTS, S3C_GPIO_PULL_UP);
+		s3c_gpio_cfgpin(GPIO_GPS_RTS, S3C_GPIO_OUTPUT);
+		gpio_direction_output(GPIO_GPS_RTS, 1);
+
+		if (gpio_request(GPIO_GPS_CTS, "GPS_CTS"))
+			WARN(1, "fail to request gpio (GPS_RTS)\n");
+		s3c_gpio_setpull(GPIO_GPS_CTS, S3C_GPIO_PULL_UP);
+		s3c_gpio_cfgpin(GPIO_GPS_CTS, S3C_GPIO_OUTPUT);
+		gpio_direction_output(GPIO_GPS_CTS, 1);
+	}
+#endif
+
+	gpio_export_link(gps_dev, "GPS_nRST", GPIO_GPS_nRST);
+#ifdef CONFIG_TARGET_LOCALE_NTT
+	if (system_rev >= 11)
+		gpio_export_link(gps_dev, "GPS_PWR_EN", GPIO_GPS_PWR_EN);
+	else
+		gpio_export_link(gps_dev, "GPS_PWR_EN", GPIO_GPS_PWR_EN_SPI);
+#else
+	gpio_export_link(gps_dev, "GPS_PWR_EN", GPIO_GPS_PWR_EN);
+#endif
+
+	return 0;
+}
+
+device_initcall(gps_gsd4t_init);
diff --git a/arch/arm/mach-exynos/board-jenga-modems.c b/arch/arm/mach-exynos/board-jenga-modems.c
new file mode 100644
index 0000000..8071df1
--- /dev/null
+++ b/arch/arm/mach-exynos/board-jenga-modems.c
@@ -0,0 +1,429 @@
+/* linux/arch/arm/mach-xxxx/board-m0-modems.c
+ * Copyright (C) 2010 Samsung Electronics. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* Modem configuraiton for M0 (P-Q + XMM6262)*/
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+#include <mach/gpio-exynos4.h>
+#include <plat/gpio-cfg.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+
+#include <linux/platform_data/modem.h>
+
+/* umts target platform data */
+static struct modem_io_t umts_io_devices[] = {
+	[0] = {
+		.name = "umts_ipc0",
+		.id = 0x1,
+		.format = IPC_FMT,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[1] = {
+		.name = "umts_rfs0",
+		.id = 0x41,
+		.format = IPC_RFS,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[2] = {
+		.name = "umts_boot0",
+		.id = 0x0,
+		.format = IPC_BOOT,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[3] = {
+		.name = "multipdp",
+		.id = 0x1,
+		.format = IPC_MULTI_RAW,
+		.io_type = IODEV_DUMMY,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[4] = {
+		.name = "rmnet0",
+		.id = 0x2A,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[5] = {
+		.name = "rmnet1",
+		.id = 0x2B,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[6] = {
+		.name = "rmnet2",
+		.id = 0x2C,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[7] = {
+		.name = "umts_router",
+		.id = 0x39,
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[8] = {
+		.name = "umts_csd",
+		.id = 0x21,
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[9] = {
+		.name = "umts_ramdump0",
+		.id = 0x0,
+		.format = IPC_RAMDUMP,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[10] = {
+		.name = "umts_loopback0",
+		.id = 0x3f,
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+};
+
+/* To get modem state, register phone active irq using resource */
+static struct resource umts_modem_res[] = {
+};
+
+static int umts_link_ldo_enble(bool enable)
+{
+	/* Exynos HSIC V1.2 LDO was controlled by kernel */
+	return 0;
+}
+
+static int umts_link_reconnect(void);
+static struct modemlink_pm_data modem_link_pm_data = {
+	.name = "link_pm",
+	.link_ldo_enable = umts_link_ldo_enble,
+	.gpio_link_enable = 0,
+	.gpio_link_active = GPIO_ACTIVE_STATE,
+	.gpio_link_hostwake = GPIO_IPC_HOST_WAKEUP,
+	.gpio_link_slavewake = GPIO_IPC_SLAVE_WAKEUP,
+	.link_reconnect = umts_link_reconnect,
+};
+
+static struct modemlink_pm_link_activectl active_ctl;
+
+static void xmm_gpio_revers_bias_clear(void);
+static void xmm_gpio_revers_bias_restore(void);
+static struct modem_data umts_modem_data = {
+	.name = "xmm6262",
+
+	.gpio_cp_on = GPIO_PHONE_ON,
+	.gpio_reset_req_n = GPIO_CP_REQ_RESET,
+	.gpio_cp_reset = GPIO_CP_RST,
+	.gpio_pda_active = GPIO_PDA_ACTIVE,
+	.gpio_phone_active = GPIO_PHONE_ACTIVE,
+	.gpio_cp_dump_int = GPIO_CP_DUMP_INT,
+	.gpio_flm_uart_sel = 0,
+	.gpio_cp_warm_reset = 0,
+
+	.modem_type = IMC_XMM6262,
+	.link_types = LINKTYPE(LINKDEV_HSIC),
+	.modem_net = UMTS_NETWORK,
+	.use_handover = false,
+
+	.num_iodevs = ARRAY_SIZE(umts_io_devices),
+	.iodevs = umts_io_devices,
+
+	.link_pm_data = &modem_link_pm_data,
+	.gpio_revers_bias_clear = xmm_gpio_revers_bias_clear,
+	.gpio_revers_bias_restore = xmm_gpio_revers_bias_restore,
+};
+
+/* HSIC specific function */
+void set_slave_wake(void)
+{
+	int spin = 20;
+	if (gpio_get_value(modem_link_pm_data.gpio_link_hostwake)) {
+		pr_err(LOG_TAG "Send Slave Wake\n");
+		gpio_direction_output(
+			modem_link_pm_data.gpio_link_slavewake, 1);
+		mdelay(5);
+		gpio_direction_output(
+			modem_link_pm_data.gpio_link_slavewake, 0);
+		while (spin--) {
+			if (!gpio_get_value(
+				modem_link_pm_data.gpio_link_hostwake))
+				break;
+			mdelay(5);
+		}
+	}
+}
+
+void set_host_states(struct platform_device *pdev, int type)
+{
+	if (active_ctl.gpio_initialized) {
+		if (type)
+			set_slave_wake();
+		pr_err(LOG_TAG "Active States =%d, %s\n", type, pdev->name);
+		gpio_direction_output(modem_link_pm_data.gpio_link_active,
+			type);
+	} else
+		active_ctl.gpio_request_host_active = 1;
+}
+
+static int umts_link_reconnect(void)
+{
+	if (gpio_get_value(umts_modem_data.gpio_phone_active) &&
+		gpio_get_value(umts_modem_data.gpio_cp_reset)) {
+		pr_info("[MODEM_IF] trying reconnect link\n");
+		gpio_set_value(modem_link_pm_data.gpio_link_active, 0);
+		mdelay(10);
+		set_slave_wake();
+		gpio_set_value(modem_link_pm_data.gpio_link_active, 1);
+	} else
+		return -ENODEV;
+
+	return 0;
+}
+
+/* if use more than one modem device, then set id num */
+static struct platform_device umts_modem = {
+	.name = "modem_if",
+	.id = -1,
+	.num_resources = ARRAY_SIZE(umts_modem_res),
+	.resource = umts_modem_res,
+	.dev = {
+		.platform_data = &umts_modem_data,
+	},
+};
+
+static void umts_modem_cfg_gpio(void)
+{
+	int err = 0;
+
+	unsigned gpio_reset_req_n = umts_modem_data.gpio_reset_req_n;
+	unsigned gpio_cp_on = umts_modem_data.gpio_cp_on;
+	unsigned gpio_cp_rst = umts_modem_data.gpio_cp_reset;
+	unsigned gpio_pda_active = umts_modem_data.gpio_pda_active;
+	unsigned gpio_phone_active = umts_modem_data.gpio_phone_active;
+	unsigned gpio_cp_dump_int = umts_modem_data.gpio_cp_dump_int;
+	unsigned gpio_flm_uart_sel = umts_modem_data.gpio_flm_uart_sel;
+	unsigned irq_phone_active = umts_modem_res[0].start;
+
+	if (gpio_reset_req_n) {
+		err = gpio_request(gpio_reset_req_n, "RESET_REQ_N");
+		if (err) {
+			pr_err(LOG_TAG "fail to request gpio %s : %d\n",
+			"RESET_REQ_N", err);
+		}
+		gpio_direction_output(gpio_reset_req_n, 0);
+	}
+
+	if (gpio_cp_on) {
+		err = gpio_request(gpio_cp_on, "CP_ON");
+		if (err) {
+			pr_err(LOG_TAG "fail to request gpio %s : %d\n",
+			       "CP_ON", err);
+		}
+		gpio_direction_output(gpio_cp_on, 0);
+	}
+
+	if (gpio_cp_rst) {
+		err = gpio_request(gpio_cp_rst, "CP_RST");
+		if (err) {
+			pr_err(LOG_TAG "fail to request gpio %s : %d\n",
+			       "CP_RST", err);
+		}
+		gpio_direction_output(gpio_cp_rst, 0);
+	}
+
+	if (gpio_pda_active) {
+		err = gpio_request(gpio_pda_active, "PDA_ACTIVE");
+		if (err) {
+			pr_err(LOG_TAG "fail to request gpio %s : %d\n",
+			       "PDA_ACTIVE", err);
+		}
+		gpio_direction_output(gpio_pda_active, 0);
+	}
+
+	if (gpio_phone_active) {
+		err = gpio_request(gpio_phone_active, "PHONE_ACTIVE");
+		if (err) {
+			pr_err(LOG_TAG "fail to request gpio %s : %d\n",
+			       "PHONE_ACTIVE", err);
+		}
+		gpio_direction_input(gpio_phone_active);
+		pr_err(LOG_TAG "check phone active = %d\n", irq_phone_active);
+	}
+
+	if (gpio_cp_dump_int) {
+		err = gpio_request(gpio_cp_dump_int, "CP_DUMP_INT");
+		if (err) {
+			pr_err(LOG_TAG "fail to request gpio %s : %d\n",
+			       "CP_DUMP_INT", err);
+		}
+		gpio_direction_input(gpio_cp_dump_int);
+	}
+
+	if (gpio_flm_uart_sel) {
+		err = gpio_request(gpio_flm_uart_sel, "GPS_UART_SEL");
+		if (err) {
+			pr_err(LOG_TAG "fail to request gpio %s : %d\n",
+			       "GPS_UART_SEL", err);
+		}
+		gpio_direction_output(gpio_reset_req_n, 0);
+	}
+
+	if (gpio_phone_active)
+		irq_set_irq_type(gpio_to_irq(gpio_phone_active),
+							IRQ_TYPE_LEVEL_HIGH);
+	/* set low unused gpios between AP and CP */
+	err = gpio_request(GPIO_FLM_RXD, "FLM_RXD");
+	if (err)
+		pr_err(LOG_TAG "fail to request gpio %s : %d\n", "FLM_RXD",
+		err);
+	else {
+		gpio_direction_output(GPIO_FLM_RXD, 0);
+		s3c_gpio_setpull(GPIO_FLM_RXD, S3C_GPIO_PULL_NONE);
+	}
+	err = gpio_request(GPIO_FLM_TXD, "FLM_TXD");
+	if (err)
+		pr_err(LOG_TAG "fail to request gpio %s : %d\n", "FLM_TXD",
+		err);
+	else {
+		gpio_direction_output(GPIO_FLM_TXD, 0);
+		s3c_gpio_setpull(GPIO_FLM_TXD, S3C_GPIO_PULL_NONE);
+	}
+	err = gpio_request(GPIO_SUSPEND_REQUEST, "SUS_REQ");
+	if (err)
+		pr_err(LOG_TAG "fail to request gpio %s : %d\n", "SUS_REQ",
+		err);
+	else {
+		gpio_direction_output(GPIO_SUSPEND_REQUEST, 0);
+		s3c_gpio_setpull(GPIO_SUSPEND_REQUEST, S3C_GPIO_PULL_NONE);
+	}
+	err = gpio_request(GPIO_GPS_CNTL, "GPS_CNTL");
+	if (err)
+		pr_err(LOG_TAG "fail to request gpio %s : %d\n", "GPS_CNTL",
+		err);
+	else {
+		gpio_direction_output(GPIO_GPS_CNTL, 0);
+		s3c_gpio_setpull(GPIO_GPS_CNTL, S3C_GPIO_PULL_NONE);
+	}
+
+	pr_info(LOG_TAG "umts_modem_cfg_gpio done\n");
+}
+
+static void xmm_gpio_revers_bias_clear(void)
+{
+	gpio_direction_output(umts_modem_data.gpio_pda_active, 0);
+	gpio_direction_output(umts_modem_data.gpio_phone_active, 0);
+	gpio_direction_output(umts_modem_data.gpio_cp_dump_int, 0);
+	gpio_direction_output(modem_link_pm_data.gpio_link_active, 0);
+	gpio_direction_output(modem_link_pm_data.gpio_link_hostwake, 0);
+	gpio_direction_output(modem_link_pm_data.gpio_link_slavewake, 0);
+
+	msleep(20);
+}
+
+static void xmm_gpio_revers_bias_restore(void)
+{
+	s3c_gpio_cfgpin(umts_modem_data.gpio_phone_active, S3C_GPIO_SFN(0xF));
+	s3c_gpio_cfgpin(modem_link_pm_data.gpio_link_hostwake,
+		S3C_GPIO_SFN(0xF));
+	gpio_direction_input(umts_modem_data.gpio_cp_dump_int);
+}
+
+static void modem_link_pm_config_gpio(void)
+{
+	int err = 0;
+
+	unsigned gpio_link_enable = modem_link_pm_data.gpio_link_enable;
+	unsigned gpio_link_active = modem_link_pm_data.gpio_link_active;
+	unsigned gpio_link_hostwake = modem_link_pm_data.gpio_link_hostwake;
+	unsigned gpio_link_slavewake = modem_link_pm_data.gpio_link_slavewake;
+	/* unsigned irq_link_hostwake = umts_modem_res[1].start; */
+
+	if (gpio_link_enable) {
+		err = gpio_request(gpio_link_enable, "LINK_EN");
+		if (err) {
+			pr_err(LOG_TAG "fail to request gpio %s : %d\n",
+			       "LINK_EN", err);
+		}
+		gpio_direction_output(gpio_link_enable, 0);
+	}
+
+	if (gpio_link_active) {
+		err = gpio_request(gpio_link_active, "LINK_ACTIVE");
+		if (err) {
+			pr_err(LOG_TAG "fail to request gpio %s : %d\n",
+			       "LINK_ACTIVE", err);
+		}
+		gpio_direction_output(gpio_link_active, 0);
+	}
+
+	if (gpio_link_hostwake) {
+		err = gpio_request(gpio_link_hostwake, "HOSTWAKE");
+		if (err) {
+			pr_err(LOG_TAG "fail to request gpio %s : %d\n",
+			       "HOSTWAKE", err);
+		}
+		gpio_direction_input(gpio_link_hostwake);
+	}
+
+	if (gpio_link_slavewake) {
+		err = gpio_request(gpio_link_slavewake, "SLAVEWAKE");
+		if (err) {
+			pr_err(LOG_TAG "fail to request gpio %s : %d\n",
+			       "SLAVEWAKE", err);
+		}
+		gpio_direction_output(gpio_link_slavewake, 0);
+	}
+
+	if (gpio_link_hostwake)
+		irq_set_irq_type(gpio_to_irq(gpio_link_hostwake),
+							IRQ_TYPE_EDGE_BOTH);
+
+	active_ctl.gpio_initialized = 1;
+	if (active_ctl.gpio_request_host_active) {
+		pr_err(LOG_TAG "Active States = 1, %s\n", __func__);
+		gpio_direction_output(modem_link_pm_data.gpio_link_active, 1);
+	}
+
+
+	pr_info(LOG_TAG "modem_link_pm_config_gpio done\n");
+}
+
+static int __init init_modem(void)
+{
+	int ret;
+	pr_info(LOG_TAG "init_modem\n");
+
+	/* umts gpios configuration */
+	umts_modem_cfg_gpio();
+	modem_link_pm_config_gpio();
+	ret = platform_device_register(&umts_modem);
+	if (ret < 0)
+		return ret;
+
+	return ret;
+}
+late_initcall(init_modem);
diff --git a/arch/arm/mach-exynos/board-m0-modems.c b/arch/arm/mach-exynos/board-m0-modems.c
new file mode 100644
index 0000000..9362e24
--- /dev/null
+++ b/arch/arm/mach-exynos/board-m0-modems.c
@@ -0,0 +1,498 @@
+/* linux/arch/arm/mach-xxxx/board-m0-modems.c
+ * Copyright (C) 2010 Samsung Electronics. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* Modem configuraiton for M0 (P-Q + XMM6262)*/
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+#include <mach/gpio-exynos4.h>
+#include <plat/gpio-cfg.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+
+#include <linux/platform_data/modem.h>
+#include <mach/sec_modem.h>
+
+extern int s3c_gpio_slp_cfgpin(unsigned int pin, unsigned int config);
+/* umts target platform data */
+static struct modem_io_t umts_io_devices[] = {
+	[0] = {
+		.name = "umts_ipc0",
+		.id = 0x1,
+		.format = IPC_FMT,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[1] = {
+		.name = "umts_rfs0",
+		.id = 0x41,
+		.format = IPC_RFS,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[2] = {
+		.name = "umts_boot0",
+		.id = 0x0,
+		.format = IPC_BOOT,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[3] = {
+		.name = "multipdp",
+		.id = 0x1,
+		.format = IPC_MULTI_RAW,
+		.io_type = IODEV_DUMMY,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[4] = {
+#ifdef CONFIG_SLP
+		.name = "pdp0",
+#else
+		.name = "rmnet0",
+#endif
+		.id = 0x2A,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[5] = {
+#ifdef CONFIG_SLP
+		.name = "pdp1",
+#else
+		.name = "rmnet1",
+#endif
+		.id = 0x2B,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[6] = {
+#ifdef CONFIG_SLP
+		.name = "pdp2",
+#else
+		.name = "rmnet2",
+#endif
+		.id = 0x2C,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[7] = {
+		.name = "umts_router",
+		.id = 0x39,
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[8] = {
+		.name = "umts_csd",
+		.id = 0x21,
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[9] = {
+		.name = "umts_ramdump0",
+		.id = 0x0,
+		.format = IPC_RAMDUMP,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[10] = {
+		.name = "umts_loopback0",
+		.id = 0x3f,
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+};
+
+/* To get modem state, register phone active irq using resource */
+static struct resource umts_modem_res[] = {
+};
+
+static int umts_link_ldo_enble(bool enable)
+{
+	/* Exynos HSIC V1.2 LDO was controlled by kernel */
+	return 0;
+}
+
+static int umts_link_reconnect(void);
+static struct modemlink_pm_data modem_link_pm_data = {
+	.name = "link_pm",
+	.link_ldo_enable = umts_link_ldo_enble,
+	.gpio_link_enable = 0,
+	.gpio_link_active = GPIO_ACTIVE_STATE,
+	.gpio_link_hostwake = GPIO_IPC_HOST_WAKEUP,
+	.gpio_link_slavewake = GPIO_IPC_SLAVE_WAKEUP,
+	.link_reconnect = umts_link_reconnect,
+};
+
+static struct modemlink_pm_link_activectl active_ctl;
+
+static void xmm_gpio_revers_bias_clear(void);
+static void xmm_gpio_revers_bias_restore(void);
+
+#ifndef GPIO_AP_DUMP_INT
+#define GPIO_AP_DUMP_INT 0
+#endif
+static struct modem_data umts_modem_data = {
+	.name = "xmm6262",
+
+	.gpio_cp_on = GPIO_PHONE_ON,
+	.gpio_reset_req_n = GPIO_CP_REQ_RESET,
+	.gpio_cp_reset = GPIO_CP_RST,
+	.gpio_pda_active = GPIO_PDA_ACTIVE,
+	.gpio_phone_active = GPIO_PHONE_ACTIVE,
+	.gpio_cp_dump_int = GPIO_CP_DUMP_INT,
+	.gpio_ap_dump_int = GPIO_AP_DUMP_INT,
+	.gpio_flm_uart_sel = 0,
+	.gpio_cp_warm_reset = 0,
+
+	.modem_type = IMC_XMM6262,
+	.link_types = LINKTYPE(LINKDEV_HSIC),
+	.modem_net = UMTS_NETWORK,
+	.use_handover = false,
+
+	.num_iodevs = ARRAY_SIZE(umts_io_devices),
+	.iodevs = umts_io_devices,
+
+	.link_pm_data = &modem_link_pm_data,
+	.gpio_revers_bias_clear = xmm_gpio_revers_bias_clear,
+	.gpio_revers_bias_restore = xmm_gpio_revers_bias_restore,
+};
+
+/* HSIC specific function */
+void set_slave_wake(void)
+{
+	if (gpio_get_value(modem_link_pm_data.gpio_link_hostwake)) {
+		pr_info("[MODEM_IF]Slave Wake\n");
+		if (gpio_get_value(modem_link_pm_data.gpio_link_slavewake)) {
+			pr_info("[MODEM_IF]Slave Wake set _-\n");
+			gpio_direction_output(
+			modem_link_pm_data.gpio_link_slavewake, 0);
+			mdelay(10);
+		}
+		gpio_direction_output(
+			modem_link_pm_data.gpio_link_slavewake, 1);
+	}
+}
+
+void set_host_states(struct platform_device *pdev, int type)
+{
+	int val = gpio_get_value(umts_modem_data.gpio_cp_reset);
+
+	if (!val) {
+		pr_info("CP not ready, Active State low\n");
+		return;
+	}
+
+	if (active_ctl.gpio_initialized) {
+		pr_err(LOG_TAG "Active States =%d, %s\n", type, pdev->name);
+		gpio_direction_output(modem_link_pm_data.gpio_link_active,
+			type);
+	}
+}
+
+void set_hsic_lpa_states(int states)
+{
+	int val = gpio_get_value(umts_modem_data.gpio_cp_reset);
+
+	mif_trace("\n");
+
+	if (val) {
+		switch (states) {
+		case STATE_HSIC_LPA_ENTER:
+			gpio_set_value(modem_link_pm_data.gpio_link_active, 0);
+			gpio_set_value(umts_modem_data.gpio_pda_active, 0);
+			pr_info(LOG_TAG "set hsic lpa enter: "
+				"active state (%d)" ", pda active (%d)\n",
+				gpio_get_value(
+					modem_link_pm_data.gpio_link_active),
+				gpio_get_value(umts_modem_data.gpio_pda_active)
+				);
+			break;
+		case STATE_HSIC_LPA_WAKE:
+			gpio_set_value(umts_modem_data.gpio_pda_active, 1);
+			pr_info(LOG_TAG "set hsic lpa wake: "
+				"pda active (%d)\n",
+				gpio_get_value(umts_modem_data.gpio_pda_active)
+				);
+			break;
+		case STATE_HSIC_LPA_PHY_INIT:
+			gpio_set_value(umts_modem_data.gpio_pda_active, 1);
+			set_slave_wake();
+			pr_info(LOG_TAG "set hsic lpa phy init: "
+				"slave wake-up (%d)\n",
+				gpio_get_value(
+					modem_link_pm_data.gpio_link_slavewake)
+				);
+			break;
+		}
+	}
+}
+
+int get_cp_active_state(void)
+{
+	return gpio_get_value(umts_modem_data.gpio_phone_active);
+}
+
+static int umts_link_reconnect(void)
+{
+	if (gpio_get_value(umts_modem_data.gpio_phone_active) &&
+		gpio_get_value(umts_modem_data.gpio_cp_reset)) {
+		pr_info("[MODEM_IF] trying reconnect link\n");
+		gpio_set_value(modem_link_pm_data.gpio_link_active, 0);
+		mdelay(10);
+		set_slave_wake();
+		gpio_set_value(modem_link_pm_data.gpio_link_active, 1);
+	} else
+		return -ENODEV;
+
+	return 0;
+}
+
+/* if use more than one modem device, then set id num */
+static struct platform_device umts_modem = {
+	.name = "modem_if",
+	.id = -1,
+	.num_resources = ARRAY_SIZE(umts_modem_res),
+	.resource = umts_modem_res,
+	.dev = {
+		.platform_data = &umts_modem_data,
+	},
+};
+
+static void umts_modem_cfg_gpio(void)
+{
+	int err = 0;
+
+	unsigned gpio_reset_req_n = umts_modem_data.gpio_reset_req_n;
+	unsigned gpio_cp_on = umts_modem_data.gpio_cp_on;
+	unsigned gpio_cp_rst = umts_modem_data.gpio_cp_reset;
+	unsigned gpio_pda_active = umts_modem_data.gpio_pda_active;
+	unsigned gpio_phone_active = umts_modem_data.gpio_phone_active;
+	unsigned gpio_cp_dump_int = umts_modem_data.gpio_cp_dump_int;
+	unsigned gpio_ap_dump_int = umts_modem_data.gpio_ap_dump_int;
+	unsigned gpio_flm_uart_sel = umts_modem_data.gpio_flm_uart_sel;
+	unsigned irq_phone_active = umts_modem_res[0].start;
+
+	if (gpio_reset_req_n) {
+		err = gpio_request(gpio_reset_req_n, "RESET_REQ_N");
+		if (err) {
+			pr_err(LOG_TAG "fail to request gpio %s : %d\n",
+			"RESET_REQ_N", err);
+		}
+		s3c_gpio_slp_cfgpin(gpio_reset_req_n, S3C_GPIO_SLP_OUT1);
+		gpio_direction_output(gpio_reset_req_n, 0);
+	}
+
+	if (gpio_cp_on) {
+		err = gpio_request(gpio_cp_on, "CP_ON");
+		if (err) {
+			pr_err(LOG_TAG "fail to request gpio %s : %d\n",
+			       "CP_ON", err);
+		}
+		gpio_direction_output(gpio_cp_on, 0);
+	}
+
+	if (gpio_cp_rst) {
+		err = gpio_request(gpio_cp_rst, "CP_RST");
+		if (err) {
+			pr_err(LOG_TAG "fail to request gpio %s : %d\n",
+			       "CP_RST", err);
+		}
+		s3c_gpio_slp_cfgpin(gpio_cp_rst, S3C_GPIO_SLP_OUT1);
+		gpio_direction_output(gpio_cp_rst, 0);
+	}
+
+	if (gpio_pda_active) {
+		err = gpio_request(gpio_pda_active, "PDA_ACTIVE");
+		if (err) {
+			pr_err(LOG_TAG "fail to request gpio %s : %d\n",
+			       "PDA_ACTIVE", err);
+		}
+		gpio_direction_output(gpio_pda_active, 0);
+	}
+
+	if (gpio_phone_active) {
+		err = gpio_request(gpio_phone_active, "PHONE_ACTIVE");
+		if (err) {
+			pr_err(LOG_TAG "fail to request gpio %s : %d\n",
+			       "PHONE_ACTIVE", err);
+		}
+		gpio_direction_input(gpio_phone_active);
+		pr_err(LOG_TAG "check phone active = %d\n", irq_phone_active);
+	}
+
+	if (gpio_cp_dump_int) {
+		err = gpio_request(gpio_cp_dump_int, "CP_DUMP_INT");
+		if (err) {
+			pr_err(LOG_TAG "fail to request gpio %s : %d\n",
+			       "CP_DUMP_INT", err);
+		}
+		gpio_direction_input(gpio_cp_dump_int);
+	}
+
+	if (gpio_ap_dump_int /*&& system_rev >= 11*/) {    /* MO rev1.0*/
+		err = gpio_request(gpio_ap_dump_int, "AP_DUMP_INT");
+		if (err) {
+			pr_err(LOG_TAG "fail to request gpio %s : %d\n",
+			       "AP_DUMP_INT", err);
+		}
+		gpio_direction_output(gpio_ap_dump_int, 0);
+	}
+
+	if (gpio_flm_uart_sel) {
+		err = gpio_request(gpio_flm_uart_sel, "GPS_UART_SEL");
+		if (err) {
+			pr_err(LOG_TAG "fail to request gpio %s : %d\n",
+			       "GPS_UART_SEL", err);
+		}
+		gpio_direction_output(gpio_reset_req_n, 0);
+	}
+
+	if (gpio_phone_active)
+		irq_set_irq_type(gpio_to_irq(gpio_phone_active),
+							IRQ_TYPE_LEVEL_HIGH);
+	/* set low unused gpios between AP and CP */
+	err = gpio_request(GPIO_FLM_RXD, "FLM_RXD");
+	if (err)
+		pr_err(LOG_TAG "fail to request gpio %s : %d\n", "FLM_RXD",
+		err);
+	else {
+		gpio_direction_output(GPIO_FLM_RXD, 0);
+		s3c_gpio_setpull(GPIO_FLM_RXD, S3C_GPIO_PULL_NONE);
+	}
+	err = gpio_request(GPIO_FLM_TXD, "FLM_TXD");
+	if (err)
+		pr_err(LOG_TAG "fail to request gpio %s : %d\n", "FLM_TXD",
+		err);
+	else {
+		gpio_direction_output(GPIO_FLM_TXD, 0);
+		s3c_gpio_setpull(GPIO_FLM_TXD, S3C_GPIO_PULL_NONE);
+	}
+	err = gpio_request(GPIO_SUSPEND_REQUEST, "SUS_REQ");
+	if (err)
+		pr_err(LOG_TAG "fail to request gpio %s : %d\n", "SUS_REQ",
+		err);
+	else {
+		gpio_direction_output(GPIO_SUSPEND_REQUEST, 0);
+		s3c_gpio_setpull(GPIO_SUSPEND_REQUEST, S3C_GPIO_PULL_NONE);
+	}
+	err = gpio_request(GPIO_GPS_CNTL, "GPS_CNTL");
+	if (err)
+		pr_err(LOG_TAG "fail to request gpio %s : %d\n", "GPS_CNTL",
+		err);
+	else {
+		gpio_direction_output(GPIO_GPS_CNTL, 0);
+		s3c_gpio_setpull(GPIO_GPS_CNTL, S3C_GPIO_PULL_NONE);
+	}
+
+	pr_info(LOG_TAG "umts_modem_cfg_gpio done\n");
+}
+
+static void xmm_gpio_revers_bias_clear(void)
+{
+	gpio_direction_output(umts_modem_data.gpio_pda_active, 0);
+	gpio_direction_output(umts_modem_data.gpio_phone_active, 0);
+	gpio_direction_output(umts_modem_data.gpio_cp_dump_int, 0);
+	gpio_direction_output(modem_link_pm_data.gpio_link_active, 0);
+	gpio_direction_output(modem_link_pm_data.gpio_link_hostwake, 0);
+	gpio_direction_output(modem_link_pm_data.gpio_link_slavewake, 0);
+
+	msleep(20);
+}
+
+static void xmm_gpio_revers_bias_restore(void)
+{
+	s3c_gpio_cfgpin(umts_modem_data.gpio_phone_active, S3C_GPIO_SFN(0xF));
+	s3c_gpio_cfgpin(modem_link_pm_data.gpio_link_hostwake,
+		S3C_GPIO_SFN(0xF));
+	gpio_direction_input(umts_modem_data.gpio_cp_dump_int);
+}
+
+static void modem_link_pm_config_gpio(void)
+{
+	int err = 0;
+
+	unsigned gpio_link_enable = modem_link_pm_data.gpio_link_enable;
+	unsigned gpio_link_active = modem_link_pm_data.gpio_link_active;
+	unsigned gpio_link_hostwake = modem_link_pm_data.gpio_link_hostwake;
+	unsigned gpio_link_slavewake = modem_link_pm_data.gpio_link_slavewake;
+	/* unsigned irq_link_hostwake = umts_modem_res[1].start; */
+
+	if (gpio_link_enable) {
+		err = gpio_request(gpio_link_enable, "LINK_EN");
+		if (err) {
+			pr_err(LOG_TAG "fail to request gpio %s : %d\n",
+			       "LINK_EN", err);
+		}
+		gpio_direction_output(gpio_link_enable, 0);
+	}
+
+	if (gpio_link_active) {
+		err = gpio_request(gpio_link_active, "LINK_ACTIVE");
+		if (err) {
+			pr_err(LOG_TAG "fail to request gpio %s : %d\n",
+			       "LINK_ACTIVE", err);
+		}
+		gpio_direction_output(gpio_link_active, 0);
+	}
+
+	if (gpio_link_hostwake) {
+		err = gpio_request(gpio_link_hostwake, "HOSTWAKE");
+		if (err) {
+			pr_err(LOG_TAG "fail to request gpio %s : %d\n",
+			       "HOSTWAKE", err);
+		}
+		gpio_direction_input(gpio_link_hostwake);
+	}
+
+	if (gpio_link_slavewake) {
+		err = gpio_request(gpio_link_slavewake, "SLAVEWAKE");
+		if (err) {
+			pr_err(LOG_TAG "fail to request gpio %s : %d\n",
+			       "SLAVEWAKE", err);
+		}
+		gpio_direction_output(gpio_link_slavewake, 0);
+	}
+
+	if (gpio_link_hostwake)
+		irq_set_irq_type(gpio_to_irq(gpio_link_hostwake),
+							IRQ_TYPE_EDGE_BOTH);
+
+	active_ctl.gpio_initialized = 1;
+
+	pr_info(LOG_TAG "modem_link_pm_config_gpio done\n");
+}
+
+static int __init init_modem(void)
+{
+	int ret;
+	pr_info(LOG_TAG "init_modem, system_rev = %d\n", system_rev);
+
+	/* umts gpios configuration */
+	umts_modem_cfg_gpio();
+	modem_link_pm_config_gpio();
+	ret = platform_device_register(&umts_modem);
+	if (ret < 0)
+		return ret;
+
+	return ret;
+}
+late_initcall(init_modem);
diff --git a/arch/arm/mach-exynos/board-m0-td-modems.c b/arch/arm/mach-exynos/board-m0-td-modems.c
new file mode 100644
index 0000000..f98a66b
--- /dev/null
+++ b/arch/arm/mach-exynos/board-m0-td-modems.c
@@ -0,0 +1,292 @@
+#include <linux/gpio.h>
+#include <plat/gpio-cfg.h>
+#include <plat/devs.h>
+#include <mach/regs-gpio.h>
+#include <mach/gpio.h>
+#include <mach/irqs.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+#include <linux/workqueue.h>
+#include <linux/regulator/consumer.h>
+#ifdef CONFIG_HAS_WAKELOCK
+#include <linux/wakelock.h>
+#endif
+#include <linux/phone_svn/modemctl.h>
+
+#define DEBUG
+
+static struct modemctl_platform_data mdmctl_data;
+void modemctl_cfg_gpio(void)
+{
+	int err = 0;
+
+	unsigned gpio_phone_on = mdmctl_data.gpio_phone_on;
+	unsigned gpio_phone_active = mdmctl_data.gpio_phone_active;
+	unsigned gpio_cp_rst = mdmctl_data.gpio_cp_reset;
+	unsigned gpio_pda_active = mdmctl_data.gpio_pda_active;
+	unsigned gpio_cp_req_reset = mdmctl_data.gpio_cp_req_reset;
+	unsigned gpio_ipc_slave_wakeup = mdmctl_data.gpio_ipc_slave_wakeup;
+	unsigned gpio_ipc_host_wakeup = mdmctl_data.gpio_ipc_host_wakeup;
+	unsigned gpio_suspend_request = mdmctl_data.gpio_suspend_request;
+	unsigned gpio_active_state = mdmctl_data.gpio_active_state;
+	unsigned gpio_cp_dump_int = mdmctl_data.gpio_cp_dump_int;
+
+	/*TODO: check uart init func AP FLM BOOT RX -- */
+	s3c_gpio_setpull(EXYNOS4_GPA1(4), S3C_GPIO_PULL_UP);
+
+	err = gpio_request(gpio_phone_on, "PHONE_ON");
+	if (err) {
+		printk(KERN_ERR "fail to request gpio %s\n", "PHONE_ON");
+	} else {
+		gpio_direction_output(gpio_phone_on, 0);
+		s3c_gpio_setpull(gpio_phone_on, S3C_GPIO_PULL_NONE);
+	}
+	err = gpio_request(gpio_pda_active, "PDA_ACTIVE");
+	if (err) {
+		printk(KERN_ERR "fail to request gpio %s\n", "PDA_ACTIVE");
+	} else {
+		gpio_direction_output(gpio_pda_active, 0);
+		s3c_gpio_setpull(gpio_pda_active, S3C_GPIO_PULL_NONE);
+	}
+#if !defined(CONFIG_CHN_CMCC_SPI_SPRD)
+	err = gpio_request(gpio_cp_rst, "CP_RST");
+	if (err) {
+		printk(KERN_ERR "fail to request gpio %s\n", "CP_RST");
+	} else {
+		gpio_direction_output(gpio_cp_rst, 0);
+		s3c_gpio_setpull(gpio_cp_rst, S3C_GPIO_PULL_NONE);
+	}
+	err = gpio_request(gpio_cp_req_reset, "CP_REQ_RESET");
+	if (err) {
+		printk(KERN_ERR "fail to request gpio %s\n", "CP_REQ_RESET");
+	} else {
+		gpio_direction_output(gpio_cp_req_reset, 0);
+		s3c_gpio_setpull(gpio_cp_req_reset, S3C_GPIO_PULL_NONE);
+	}
+
+	err = gpio_request(gpio_ipc_slave_wakeup, "IPC_SLAVE_WAKEUP");
+	if (err) {
+		printk(KERN_ERR "fail to request gpio %s\n",
+			"IPC_SLAVE_WAKEUP");
+	} else {
+		gpio_direction_output(gpio_ipc_slave_wakeup, 0);
+		s3c_gpio_setpull(gpio_ipc_slave_wakeup, S3C_GPIO_PULL_NONE);
+	}
+
+	err = gpio_request(gpio_ipc_host_wakeup, "IPC_HOST_WAKEUP");
+	if (err) {
+		printk(KERN_ERR "fail to request gpio %s\n", "IPC_HOST_WAKEUP");
+	} else {
+		gpio_direction_output(gpio_ipc_host_wakeup, 0);
+		s3c_gpio_cfgpin(gpio_ipc_host_wakeup, S3C_GPIO_SFN(0xF));
+		s3c_gpio_setpull(gpio_ipc_host_wakeup, S3C_GPIO_PULL_NONE);
+	}
+
+	err = gpio_request(gpio_suspend_request, "SUSPEND_REQUEST");
+	if (err) {
+		printk(KERN_ERR "fail to request gpio %s\n", "SUSPEND_REQUEST");
+	} else {
+		gpio_direction_input(gpio_suspend_request);
+		s3c_gpio_setpull(gpio_suspend_request, S3C_GPIO_PULL_NONE);
+	}
+
+	err = gpio_request(gpio_active_state, "ACTIVE_STATE");
+	if (err) {
+		printk(KERN_ERR "fail to request gpio %s\n", "ACTIVE_STATE");
+	} else {
+		gpio_direction_output(gpio_active_state, 0);
+		s3c_gpio_setpull(gpio_active_state, S3C_GPIO_PULL_NONE);
+	}
+#endif
+	err = gpio_request(gpio_phone_active, "PHONE_ACTIVE");
+	if (err) {
+		printk(KERN_ERR "fail to request gpio %s\n", "PHONE_ACTIVE");
+	} else {
+		gpio_direction_input(gpio_phone_active);
+		s3c_gpio_cfgpin(gpio_phone_active, S3C_GPIO_SFN(0xF));
+		s3c_gpio_setpull(gpio_phone_active, S3C_GPIO_PULL_DOWN);
+	}
+
+	err = gpio_request(gpio_cp_dump_int, "CP_DUMP_INT");
+	if (err) {
+		printk(KERN_ERR "fail to request gpio %s\n", "CP_DUMP_INT");
+	} else {
+		gpio_direction_input(gpio_cp_dump_int);
+		s3c_gpio_cfgpin(gpio_cp_dump_int, S3C_GPIO_SFN(0xF));
+		s3c_gpio_setpull(gpio_cp_dump_int, S3C_GPIO_PULL_DOWN);
+	}
+}
+
+static void xmm6260_vcc_init(struct modemctl *mc)
+{
+	int err;
+
+	if (!mc->vcc) {
+		mc->vcc = regulator_get(NULL, "vhsic");
+		if (IS_ERR(mc->vcc)) {
+			err = PTR_ERR(mc->vcc);
+			dev_dbg(mc->dev, "No VHSIC_1.2V regualtor: %d\n", err);
+			mc->vcc = NULL;
+		}
+	}
+
+	if (mc->vcc)
+		regulator_enable(mc->vcc);
+}
+
+static void xmm6260_vcc_off(struct modemctl *mc)
+{
+	if (mc->vcc)
+		regulator_disable(mc->vcc);
+}
+
+static void xmm6260_on(struct modemctl *mc)
+{
+	dev_dbg(mc->dev, "%s\n", __func__);
+	if (!mc->gpio_cp_reset || !mc->gpio_phone_on || !mc->gpio_cp_req_reset)
+		return;
+#if defined(CONFIG_CHN_CMCC_SPI_SPRD)
+	gpio_set_value(mc->gpio_cp_req_reset, 0);
+	gpio_set_value(mc->gpio_pda_active, 0);
+	gpio_set_value(mc->gpio_phone_on, 0);
+	msleep(100);
+	gpio_set_value(mc->gpio_phone_on, 1);
+	gpio_set_value(mc->gpio_pda_active, 1);
+#else
+	xmm6260_vcc_init(mc);
+
+	gpio_set_value(mc->gpio_phone_on, 0);
+	gpio_set_value(mc->gpio_cp_reset, 0);
+	udelay(160);
+
+	gpio_set_value(mc->gpio_pda_active, 0);
+	gpio_set_value(mc->gpio_active_state, 0);
+	msleep(100);
+
+	gpio_set_value(mc->gpio_cp_reset, 1);
+	udelay(160);
+	gpio_set_value(mc->gpio_cp_req_reset, 1);
+	udelay(160);
+
+	gpio_set_value(mc->gpio_phone_on, 1);
+
+	msleep(20);
+	gpio_set_value(mc->gpio_active_state, 1);
+	gpio_set_value(mc->gpio_pda_active, 1);
+#endif
+}
+
+static void xmm6260_off(struct modemctl *mc)
+{
+	dev_dbg(mc->dev, "%s\n", __func__);
+	if (!mc->gpio_cp_reset || !mc->gpio_phone_on)
+		return;
+
+	gpio_set_value(mc->gpio_phone_on, 0);
+	gpio_set_value(mc->gpio_cp_reset, 0);
+
+	xmm6260_vcc_off(mc);
+}
+
+static void xmm6260_reset(struct modemctl *mc)
+{
+	dev_dbg(mc->dev, "%s\n", __func__);
+	if (!mc->gpio_cp_reset || !mc->gpio_cp_req_reset)
+		return;
+
+#if defined(CONFIG_CHN_CMCC_SPI_SPRD)
+	gpio_set_value(mc->gpio_cp_req_reset, 0);
+	msleep(100);
+	gpio_set_value(mc->gpio_cp_req_reset, 1);
+#else
+/*	gpio_set_value(mc->gpio_pda_active, 0);
+	gpio_set_value(mc->gpio_active_state, 0);*/
+	gpio_set_value(mc->gpio_cp_reset, 0);
+	gpio_set_value(mc->gpio_cp_req_reset, 0);
+
+	msleep(100);
+
+	gpio_set_value(mc->gpio_cp_reset, 1);
+	udelay(160);
+	gpio_set_value(mc->gpio_cp_req_reset, 1);
+#endif
+}
+
+/* move the PDA_ACTIVE Pin control to sleep_gpio_table */
+static void xmm6260_suspend(struct modemctl *mc)
+{
+	xmm6260_vcc_off(mc);
+}
+
+static void xmm6260_resume(struct modemctl *mc)
+{
+	xmm6260_vcc_init(mc);
+}
+
+#if defined(CONFIG_CHN_CMCC_SPI_SPRD)
+static struct modemctl_platform_data mdmctl_data = {
+	.name = "xmm6260",
+
+	.gpio_phone_on = GPIO_PHONE_ON,
+	.gpio_phone_active = GPIO_PHONE_ACTIVE,
+	.gpio_pda_active = GPIO_PDA_ACTIVE,
+	.gpio_cp_reset = GPIO_CP_RST,
+	.gpio_cp_req_reset = GPIO_AP_CP_INT2,
+	.gpio_ipc_slave_wakeup = GPIO_IPC_SLAVE_WAKEUP,
+	.gpio_ipc_host_wakeup = GPIO_IPC_HOST_WAKEUP,
+	.gpio_suspend_request = GPIO_SUSPEND_REQUEST,
+	.gpio_active_state = GPIO_ACTIVE_STATE,
+	.gpio_cp_dump_int = GPIO_CP_DUMP_INT,
+
+	.ops = {
+		.modem_on = xmm6260_on,
+		.modem_off = xmm6260_off,
+		.modem_reset = xmm6260_reset,
+		.modem_suspend = xmm6260_suspend,
+		.modem_resume = xmm6260_resume,
+		.modem_cfg_gpio = modemctl_cfg_gpio,
+	}
+};
+#else
+static struct modemctl_platform_data mdmctl_data = {
+	.name = "xmm6260",
+	.gpio_phone_on = GPIO_PHONE_ON,
+	.gpio_phone_active = GPIO_PHONE_ACTIVE,
+	.gpio_pda_active = GPIO_PDA_ACTIVE,
+	.gpio_cp_reset = GPIO_CP_RST,
+	.gpio_cp_req_reset = GPIO_CP_REQ_RESET,
+	.gpio_ipc_slave_wakeup = GPIO_IPC_SLAVE_WAKEUP,
+	.gpio_ipc_host_wakeup = GPIO_IPC_HOST_WAKEUP,
+	.gpio_suspend_request = GPIO_SUSPEND_REQUEST,
+	.gpio_active_state = GPIO_ACTIVE_STATE,
+	.gpio_cp_dump_int = GPIO_CP_DUMP_INT,
+	.ops = {
+		.modem_on = xmm6260_on,
+		.modem_off = xmm6260_off,
+		.modem_reset = xmm6260_reset,
+		.modem_suspend = xmm6260_suspend,
+		.modem_resume = xmm6260_resume,
+		.modem_cfg_gpio = modemctl_cfg_gpio,
+	}
+};
+#endif
+
+/* TODO: check the IRQs..... */
+static struct resource mdmctl_res[] = {
+	[0] = {
+		.start = IRQ_PHONE_ACTIVE,
+		.end = IRQ_PHONE_ACTIVE,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+struct platform_device modemctl = {
+	.name = "modemctl",
+	.id = -1,
+	.num_resources = ARRAY_SIZE(mdmctl_res),
+	.resource = mdmctl_res,
+
+	.dev = {
+		.platform_data = &mdmctl_data,
+	},
+};
diff --git a/arch/arm/mach-exynos/board-m0ctc-modems.c b/arch/arm/mach-exynos/board-m0ctc-modems.c
new file mode 100644
index 0000000..3f69c69
--- /dev/null
+++ b/arch/arm/mach-exynos/board-m0ctc-modems.c
@@ -0,0 +1,1877 @@
+/* linux/arch/arm/mach-xxxx/board-c1ctc-modems.c
+ * Copyright (C) 2010 Samsung Electronics. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/regulator/consumer.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/vmalloc.h>
+#include <linux/if_arp.h>
+
+/* inlcude platform specific file */
+#include <linux/platform_data/modem.h>
+#include <mach/sec_modem.h>
+#include <mach/gpio.h>
+#include <mach/gpio-exynos4.h>
+#include <plat/gpio-cfg.h>
+#include <mach/regs-mem.h>
+#include <plat/regs-srom.h>
+
+#ifdef CONFIG_USBHUB_USB3503
+#include <linux/i2c.h>
+#include <linux/i2c-gpio.h>
+#include <linux/platform_data/usb3503.h>
+#endif
+#include <plat/devs.h>
+#include <plat/ehci.h>
+
+#define SROM_CS0_BASE		0x04000000
+#define SROM_WIDTH		0x01000000
+#define SROM_NUM_ADDR_BITS	14
+
+/*
+ * For SROMC Configuration:
+ * SROMC_ADDR_BYTE enable for byte access
+ */
+#define SROMC_DATA_16		0x1
+#define SROMC_ADDR_BYTE		0x2
+#define SROMC_WAIT_EN		0x4
+#define SROMC_BYTE_EN		0x8
+#define SROMC_MASK		0xF
+
+/* Memory attributes */
+enum sromc_attr {
+	MEM_DATA_BUS_16BIT = 0x00000001,
+	MEM_BYTE_ADDRESSABLE = 0x00000002,
+	MEM_WAIT_EN = 0x00000004,
+	MEM_BYTE_EN = 0x00000008,
+
+};
+
+/* DPRAM configuration */
+struct sromc_cfg {
+	enum sromc_attr attr;
+	unsigned size;
+	unsigned csn;		/* CSn #                        */
+	unsigned addr;		/* Start address (physical)     */
+	unsigned end;		/* End address (physical)       */
+};
+
+/* DPRAM access timing configuration */
+struct sromc_access_cfg {
+	u32 tacs;		/* Address set-up before CSn            */
+	u32 tcos;		/* Chip selection set-up before OEn     */
+	u32 tacc;		/* Access cycle                         */
+	u32 tcoh;		/* Chip selection hold on OEn           */
+	u32 tcah;		/* Address holding time after CSn       */
+	u32 tacp;		/* Page mode access cycle at Page mode  */
+	u32 pmc;		/* Page Mode config                     */
+};
+
+/* For MDM6600 EDPRAM (External DPRAM) */
+#define MSM_EDPRAM_SIZE		0x4000	/* 16 KB */
+
+#define INT_MASK_REQ_ACK_F	0x0020
+#define INT_MASK_REQ_ACK_R	0x0010
+#define INT_MASK_RES_ACK_F	0x0008
+#define INT_MASK_RES_ACK_R	0x0004
+#define INT_MASK_SEND_F		0x0002
+#define INT_MASK_SEND_R		0x0001
+
+#define INT_MASK_REQ_ACK_RFS	0x0400	/* Request RES_ACK_RFS           */
+#define INT_MASK_RES_ACK_RFS	0x0200	/* Response of REQ_ACK_RFS       */
+#define INT_MASK_SEND_RFS	0x0100	/* Indicate sending RFS data     */
+
+/* Function prototypes */
+static void config_dpram_port_gpio(void);
+static void init_sromc(void);
+static void setup_sromc(unsigned csn, struct sromc_cfg *cfg,
+			struct sromc_access_cfg *acc_cfg);
+static void setup_dpram_speed(unsigned csn, struct sromc_access_cfg *acc_cfg);
+static int __init init_modem(void);
+
+#ifdef CONFIG_USBHUB_USB3503
+static int host_port_enable(int port, int enable);
+#else
+static int host_port_enable(int port, int enable)
+{
+	return s5p_ehci_port_control(&s5p_device_ehci, port, enable);
+}
+#endif
+
+static struct sromc_cfg msm_edpram_cfg = {
+	.attr = (MEM_DATA_BUS_16BIT | MEM_WAIT_EN | MEM_BYTE_EN),
+	.size = MSM_EDPRAM_SIZE,
+};
+
+static struct sromc_access_cfg msm_edpram_access_cfg[] = {
+	[DPRAM_SPEED_LOW] = {
+			     .tacs = 0x2 << 28,
+			     .tcos = 0x2 << 24,
+			     .tacc = 0x3 << 16,
+			     .tcoh = 0x2 << 12,
+			     .tcah = 0x2 << 8,
+			     .tacp = 0x2 << 4,
+			     .pmc = 0x0 << 0,
+			     },
+};
+
+/*
+	magic_code +
+	access_enable +
+	fmt_tx_head + fmt_tx_tail + fmt_tx_buff +
+	raw_tx_head + raw_tx_tail + raw_tx_buff +
+	fmt_rx_head + fmt_rx_tail + fmt_rx_buff +
+	raw_rx_head + raw_rx_tail + raw_rx_buff +
+	padding +
+	mbx_cp2ap +
+	mbx_ap2cp
+ =	2 +
+	2 +
+	2 + 2 + 2044 +
+	2 + 2 + 6128 +
+	2 + 2 + 2044 +
+	2 + 2 + 6128 +
+	16 +
+	2 +
+	2
+ =	16384
+*/
+
+#define MSM_DP_FMT_TX_BUFF_SZ	2044
+#define MSM_DP_RAW_TX_BUFF_SZ	6128
+#define MSM_DP_FMT_RX_BUFF_SZ	2044
+#define MSM_DP_RAW_RX_BUFF_SZ	6128
+
+#define MAX_MSM_EDPRAM_IPC_DEV	2	/* FMT, RAW */
+
+struct msm_edpram_ipc_cfg {
+	u16 magic;
+	u16 access;
+
+	u16 fmt_tx_head;
+	u16 fmt_tx_tail;
+	u8 fmt_tx_buff[MSM_DP_FMT_TX_BUFF_SZ];
+
+	u16 raw_tx_head;
+	u16 raw_tx_tail;
+	u8 raw_tx_buff[MSM_DP_RAW_TX_BUFF_SZ];
+
+	u16 fmt_rx_head;
+	u16 fmt_rx_tail;
+	u8 fmt_rx_buff[MSM_DP_FMT_RX_BUFF_SZ];
+
+	u16 raw_rx_head;
+	u16 raw_rx_tail;
+	u8 raw_rx_buff[MSM_DP_RAW_RX_BUFF_SZ];
+
+	u8 padding[16];
+	u16 mbx_ap2cp;
+	u16 mbx_cp2ap;
+};
+
+struct msm_edpram_boot_map {
+	u8 __iomem *buff;
+	u16 __iomem *frame_size;
+	u16 __iomem *tag;
+	u16 __iomem *count;
+};
+
+static struct dpram_ipc_map msm_ipc_map;
+
+struct _param_nv {
+	unsigned char *addr;
+	unsigned int size;
+	unsigned int count;
+	unsigned int tag;
+};
+
+#if (MSM_EDPRAM_SIZE == 0x4000)
+/*
+------------------
+Buffer : 15KByte
+------------------
+Reserved: 1014Byte
+------------------
+SIZE: 2Byte
+------------------
+TAG: 2Byte
+------------------
+COUNT: 2Byte
+------------------
+AP -> CP Intr : 2Byte
+------------------
+CP -> AP Intr : 2Byte
+------------------
+*/
+#define DP_BOOT_CLEAR_OFFSET	4
+#define DP_BOOT_RSRVD_OFFSET	0x3C00
+#define DP_BOOT_SIZE_OFFSET	    0x3FF6
+#define DP_BOOT_TAG_OFFSET	    0x3FF8
+#define DP_BOOT_COUNT_OFFSET	0x3FFA
+
+#define DP_BOOT_FRAME_SIZE_LIMIT     0x3C00	/* 15KB = 15360byte = 0x3C00 */
+#else
+/*
+------------------
+Buffer : 31KByte
+------------------
+Reserved: 1014Byte
+------------------
+SIZE: 2Byte
+------------------
+TAG: 2Byte
+------------------
+COUNT: 2Byte
+------------------
+AP -> CP Intr : 2Byte
+------------------
+CP -> AP Intr : 2Byte
+------------------
+*/
+#define DP_BOOT_CLEAR_OFFSET	4
+#define DP_BOOT_RSRVD_OFFSET	0x7C00
+#define DP_BOOT_SIZE_OFFSET	    0x7FF6
+#define DP_BOOT_TAG_OFFSET	    0x7FF8
+#define DP_BOOT_COUNT_OFFSET	0x7FFA
+
+#define DP_BOOT_FRAME_SIZE_LIMIT     0x7C00	/* 31KB = 31744byte = 0x7C00 */
+#endif
+
+struct _param_check {
+	unsigned int total_size;
+	unsigned int rest_size;
+	unsigned int send_size;
+	unsigned int copy_start;
+	unsigned int copy_complete;
+	unsigned int boot_complete;
+};
+
+static struct _param_nv *data_param;
+static struct _param_check check_param;
+
+static unsigned int boot_start_complete;
+static struct msm_edpram_boot_map msm_edpram_bt_map;
+static struct dpram_ipc_map msm_ipc_map;
+
+static unsigned char *img;
+static unsigned char *nv_img;
+
+static void msm_edpram_reset(void);
+static void msm_edpram_clr_intr(void);
+static u16 msm_edpram_recv_intr(void);
+static void msm_edpram_send_intr(u16 irq_mask);
+static u16 msm_edpram_recv_msg(void);
+static void msm_edpram_send_msg(u16 msg);
+
+static u16 msm_edpram_get_magic(void);
+static void msm_edpram_set_magic(u16 value);
+static u16 msm_edpram_get_access(void);
+static void msm_edpram_set_access(u16 value);
+
+static u32 msm_edpram_get_tx_head(int dev_id);
+static u32 msm_edpram_get_tx_tail(int dev_id);
+static void msm_edpram_set_tx_head(int dev_id, u32 head);
+static void msm_edpram_set_tx_tail(int dev_id, u32 tail);
+static u8 __iomem *msm_edpram_get_tx_buff(int dev_id);
+static u32 msm_edpram_get_tx_buff_size(int dev_id);
+
+static u32 msm_edpram_get_rx_head(int dev_id);
+static u32 msm_edpram_get_rx_tail(int dev_id);
+static void msm_edpram_set_rx_head(int dev_id, u32 head);
+static void msm_edpram_set_rx_tail(int dev_id, u32 tail);
+static u8 __iomem *msm_edpram_get_rx_buff(int dev_id);
+static u32 msm_edpram_get_rx_buff_size(int dev_id);
+
+static u16 msm_edpram_get_mask_req_ack(int dev_id);
+static u16 msm_edpram_get_mask_res_ack(int dev_id);
+static u16 msm_edpram_get_mask_send(int dev_id);
+
+static void msm_log_disp(struct modemlink_dpram_control *dpctl);
+static int msm_uload_step1(struct modemlink_dpram_control *dpctl);
+static int msm_uload_step2(void *arg, struct modemlink_dpram_control *dpctl);
+static int msm_dload_prep(struct modemlink_dpram_control *dpctl);
+static int msm_dload(void *arg, struct modemlink_dpram_control *dpctl);
+static int msm_nv_load(void *arg, struct modemlink_dpram_control *dpctl);
+static int msm_boot_start(struct modemlink_dpram_control *dpctl);
+static int msm_boot_start_post_proc(void);
+static void msm_boot_start_handler(struct modemlink_dpram_control *dpctl);
+static void msm_dload_handler(struct modemlink_dpram_control *dpctl, u16 cmd);
+static void msm_bt_map_init(struct modemlink_dpram_control *dpctl);
+static void msm_load_init(struct modemlink_dpram_control *dpctl);
+static void msm_terminate_link(struct modemlink_dpram_control *dpctl);
+
+static struct modemlink_dpram_control msm_edpram_ctrl = {
+	.reset = msm_edpram_reset,
+
+	.clear_intr = msm_edpram_clr_intr,
+	.recv_intr = msm_edpram_recv_intr,
+	.send_intr = msm_edpram_send_intr,
+	.recv_msg = msm_edpram_recv_msg,
+	.send_msg = msm_edpram_send_msg,
+
+	.get_magic = msm_edpram_get_magic,
+	.set_magic = msm_edpram_set_magic,
+	.get_access = msm_edpram_get_access,
+	.set_access = msm_edpram_set_access,
+
+	.get_tx_head = msm_edpram_get_tx_head,
+	.get_tx_tail = msm_edpram_get_tx_tail,
+	.set_tx_head = msm_edpram_set_tx_head,
+	.set_tx_tail = msm_edpram_set_tx_tail,
+	.get_tx_buff = msm_edpram_get_tx_buff,
+	.get_tx_buff_size = msm_edpram_get_tx_buff_size,
+
+	.get_rx_head = msm_edpram_get_rx_head,
+	.get_rx_tail = msm_edpram_get_rx_tail,
+	.set_rx_head = msm_edpram_set_rx_head,
+	.set_rx_tail = msm_edpram_set_rx_tail,
+	.get_rx_buff = msm_edpram_get_rx_buff,
+	.get_rx_buff_size = msm_edpram_get_rx_buff_size,
+
+	.get_mask_req_ack = msm_edpram_get_mask_req_ack,
+	.get_mask_res_ack = msm_edpram_get_mask_res_ack,
+	.get_mask_send = msm_edpram_get_mask_send,
+
+	.log_disp = msm_log_disp,
+	.cpupload_step1 = msm_uload_step1,
+	.cpupload_step2 = msm_uload_step2,
+	.cpimage_load = msm_dload,
+	.nvdata_load = msm_nv_load,
+	.phone_boot_start = msm_boot_start,
+	.dload_cmd_hdlr = msm_dload_handler,
+	.bt_map_init = msm_bt_map_init,
+	.load_init = msm_load_init,
+	.cpimage_load_prepare = msm_dload_prep,
+	.phone_boot_start_post_process = msm_boot_start_post_proc,
+	.phone_boot_start_handler = msm_boot_start_handler,
+	.terminate_link = msm_terminate_link,
+
+	.dp_base = NULL,
+	.dp_size = 0,
+	.dp_type = EXT_DPRAM,
+
+	.dpram_irq = MSM_DPRAM_INT_IRQ,
+	.dpram_irq_flags = IRQF_TRIGGER_FALLING,
+	.dpram_irq_name = "MDM6600_EDPRAM_IRQ",
+	.dpram_wlock_name = "MDM6600_EDPRAM_WLOCK",
+
+	.max_ipc_dev = IPC_RFS,
+};
+
+/*
+** CDMA target platform data
+*/
+static struct modem_io_t cdma_io_devices[] = {
+	[0] = {
+	       .name = "cdma_boot0",
+	       .id = 0x1,
+	       .format = IPC_BOOT,
+	       .io_type = IODEV_MISC,
+	       .links = LINKTYPE(LINKDEV_DPRAM),
+	       },
+	[1] = {
+	       .name = "cdma_ramdump0",
+	       .id = 0x1,
+	       .format = IPC_RAMDUMP,
+	       .io_type = IODEV_MISC,
+	       .links = LINKTYPE(LINKDEV_DPRAM),
+	       },
+	[2] = {
+	       .name = "umts_ipc0",
+	       .id = 0x01,
+	       .format = IPC_FMT,
+	       .io_type = IODEV_MISC,
+	       .links = LINKTYPE(LINKDEV_DPRAM),
+	       },
+	[3] = {
+	       .name = "cdma_ipc0",
+	       .id = 0x00,
+	       .format = IPC_FMT,
+	       .io_type = IODEV_MISC,
+	       .links = LINKTYPE(LINKDEV_DPRAM),
+	       },
+	[4] = {
+	       .name = "multi_pdp",
+	       .id = 0x1,
+	       .format = IPC_MULTI_RAW,
+	       .io_type = IODEV_DUMMY,
+	       .links = LINKTYPE(LINKDEV_DPRAM),
+	       },
+	[5] = {
+	       .name = "cdma_CSD",
+	       .id = (1 | 0x20),
+	       .format = IPC_RAW,
+	       .io_type = IODEV_MISC,
+	       .links = LINKTYPE(LINKDEV_DPRAM),
+	       },
+	[6] = {
+	       .name = "cdma_FOTA",
+	       .id = (2 | 0x20),
+	       .format = IPC_RAW,
+	       .io_type = IODEV_MISC,
+	       .links = LINKTYPE(LINKDEV_DPRAM),
+	       },
+	[7] = {
+	       .name = "cdma_GPS",
+	       .id = (5 | 0x20),
+	       .format = IPC_RAW,
+	       .io_type = IODEV_MISC,
+	       .links = LINKTYPE(LINKDEV_DPRAM),
+	       },
+	[8] = {
+	       .name = "cdma_XTRA",
+	       .id = (6 | 0x20),
+	       .format = IPC_RAW,
+	       .io_type = IODEV_MISC,
+	       .links = LINKTYPE(LINKDEV_DPRAM),
+	       },
+	[9] = {
+	       .name = "cdma_CDMA",
+	       .id = (7 | 0x20),
+	       .format = IPC_RAW,
+	       .io_type = IODEV_MISC,
+	       .links = LINKTYPE(LINKDEV_DPRAM),
+	       },
+	[10] = {
+		.name = "cdma_EFS",
+		.id = (8 | 0x20),
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+		},
+	[11] = {
+		.name = "cdma_TRFB",
+		.id = (9 | 0x20),
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+		},
+	[12] = {
+		.name = "rmnet0",
+		.id = 0x2A,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+		},
+	[13] = {
+		.name = "rmnet1",
+		.id = 0x2B,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+		},
+	[14] = {
+		.name = "rmnet2",
+		.id = 0x2C,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+		},
+	[15] = {
+		.name = "rmnet3",
+		.id = 0x2D,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+		},
+	[16] = {
+		.name = "cdma_SMD",
+		.id = (25 | 0x20),
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+		},
+	[17] = {
+		.name = "cdma_VTVD",
+		.id = (26 | 0x20),
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+		},
+	[18] = {
+		.name = "cdma_VTAD",
+		.id = (27 | 0x20),
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+		},
+	[19] = {
+		.name = "cdma_VTCTRL",
+		.id = (28 | 0x20),
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+		},
+	[20] = {
+		.name = "cdma_VTENT",
+		.id = (29 | 0x20),
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+		},
+};
+
+static struct modem_data cdma_modem_data = {
+	.name = "mdm6600",
+
+	.gpio_cp_on = GPIO_CP_MSM_PWRON,
+	.gpio_cp_off = 0,
+	.gpio_reset_req_n = GPIO_CP_MSM_PMU_RST,
+	.gpio_cp_reset = GPIO_CP_MSM_RST,
+	.gpio_pda_active = GPIO_PDA_ACTIVE,
+	.gpio_phone_active = GPIO_MSM_PHONE_ACTIVE,
+	.gpio_flm_uart_sel = GPIO_BOOT_SW_SEL,
+#if 1
+	.gpio_flm_uart_sel_rev06 = GPIO_BOOT_SW_SEL_REV06,
+#endif
+
+	.gpio_dpram_int = GPIO_MSM_DPRAM_INT,
+	.gpio_host_wakeup = GPIO_IPC_HOST_WAKEUP,
+
+	.gpio_cp_dump_int = 0,
+	.gpio_cp_warm_reset = 0,
+
+	.use_handover = false,
+
+	.modem_net = CDMA_NETWORK,
+	.modem_type = QC_MDM6600,
+	.link_types = LINKTYPE(LINKDEV_DPRAM),
+	.link_name = "mdm6600_edpram",
+	.dpram_ctl = &msm_edpram_ctrl,
+
+	.ipc_version = SIPC_VER_42,
+
+	.num_iodevs = ARRAY_SIZE(cdma_io_devices),
+	.iodevs = cdma_io_devices,
+};
+
+static struct resource cdma_modem_res[] = {
+	[0] = {
+	       .name = "cp_active_irq",
+	       .start = MSM_PHONE_ACTIVE_IRQ,
+	       .end = MSM_PHONE_ACTIVE_IRQ,
+	       .flags = IORESOURCE_IRQ,
+	       },
+};
+
+static struct platform_device cdma_modem = {
+	.name = "modem_if",
+	.id = 2,
+	.num_resources = ARRAY_SIZE(cdma_modem_res),
+	.resource = cdma_modem_res,
+	.dev = {
+		.platform_data = &cdma_modem_data,
+		},
+};
+
+static void msm_edpram_reset(void)
+{
+	return;
+}
+
+static void msm_edpram_clr_intr(void)
+{
+	ioread16(msm_ipc_map.mbx_cp2ap);
+}
+
+static u16 msm_edpram_recv_intr(void)
+{
+	return ioread16(msm_ipc_map.mbx_cp2ap);
+}
+
+static void msm_edpram_send_intr(u16 irq_mask)
+{
+	iowrite16(irq_mask, msm_ipc_map.mbx_ap2cp);
+}
+
+static u16 msm_edpram_recv_msg(void)
+{
+	return ioread16(msm_ipc_map.mbx_cp2ap);
+}
+
+static void msm_edpram_send_msg(u16 msg)
+{
+	iowrite16(msg, msm_ipc_map.mbx_ap2cp);
+}
+
+static u16 msm_edpram_get_magic(void)
+{
+	return ioread16(msm_ipc_map.magic);
+}
+
+static void msm_edpram_set_magic(u16 value)
+{
+	iowrite16(value, msm_ipc_map.magic);
+}
+
+static u16 msm_edpram_get_access(void)
+{
+	return ioread16(msm_ipc_map.access);
+}
+
+static void msm_edpram_set_access(u16 value)
+{
+	iowrite16(value, msm_ipc_map.access);
+}
+
+static u32 msm_edpram_get_tx_head(int dev_id)
+{
+	return ioread16(msm_ipc_map.dev[dev_id].txq.head);
+}
+
+static u32 msm_edpram_get_tx_tail(int dev_id)
+{
+	return ioread16(msm_ipc_map.dev[dev_id].txq.tail);
+}
+
+static void msm_edpram_set_tx_head(int dev_id, u32 head)
+{
+	iowrite16((u16) head, msm_ipc_map.dev[dev_id].txq.head);
+}
+
+static void msm_edpram_set_tx_tail(int dev_id, u32 tail)
+{
+	iowrite16((u16) tail, msm_ipc_map.dev[dev_id].txq.tail);
+}
+
+static u8 __iomem *msm_edpram_get_tx_buff(int dev_id)
+{
+	return msm_ipc_map.dev[dev_id].txq.buff;
+}
+
+static u32 msm_edpram_get_tx_buff_size(int dev_id)
+{
+	return msm_ipc_map.dev[dev_id].txq.size;
+}
+
+static u32 msm_edpram_get_rx_head(int dev_id)
+{
+	return ioread16(msm_ipc_map.dev[dev_id].rxq.head);
+}
+
+static u32 msm_edpram_get_rx_tail(int dev_id)
+{
+	return ioread16(msm_ipc_map.dev[dev_id].rxq.tail);
+}
+
+static void msm_edpram_set_rx_head(int dev_id, u32 head)
+{
+	return iowrite16((u16) head, msm_ipc_map.dev[dev_id].rxq.head);
+}
+
+static void msm_edpram_set_rx_tail(int dev_id, u32 tail)
+{
+	return iowrite16((u16) tail, msm_ipc_map.dev[dev_id].rxq.tail);
+}
+
+static u8 __iomem *msm_edpram_get_rx_buff(int dev_id)
+{
+	return msm_ipc_map.dev[dev_id].rxq.buff;
+}
+
+static u32 msm_edpram_get_rx_buff_size(int dev_id)
+{
+	return msm_ipc_map.dev[dev_id].rxq.size;
+}
+
+static u16 msm_edpram_get_mask_req_ack(int dev_id)
+{
+	return msm_ipc_map.dev[dev_id].mask_req_ack;
+}
+
+static u16 msm_edpram_get_mask_res_ack(int dev_id)
+{
+	return msm_ipc_map.dev[dev_id].mask_res_ack;
+}
+
+static u16 msm_edpram_get_mask_send(int dev_id)
+{
+	return msm_ipc_map.dev[dev_id].mask_send;
+}
+
+static void msm_log_disp(struct modemlink_dpram_control *dpctl)
+{
+	static unsigned char buf[151];
+	u8 __iomem *tmp_buff = NULL;
+
+	tmp_buff = dpctl->get_rx_buff(IPC_FMT);
+	memcpy(buf, tmp_buff, (sizeof(buf) - 1));
+
+	pr_info("[LNK] | PHONE ERR MSG\t| CDMA Crash\n");
+	pr_info("[LNK] | PHONE ERR MSG\t| %s\n", buf);
+}
+
+static int msm_data_upload(struct _param_nv *param,
+			   struct modemlink_dpram_control *dpctl)
+{
+	int retval = 0;
+	u16 in_interrupt = 0;
+	int count = 0;
+
+	while (1) {
+		if (!gpio_get_value(GPIO_MSM_DPRAM_INT)) {
+			in_interrupt = dpctl->recv_msg();
+			if (in_interrupt == 0xDBAB) {
+				break;
+			} else {
+				pr_err("[LNK][intr]:0x%08x\n", in_interrupt);
+				pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+				return -1;
+			}
+		}
+		msleep_interruptible(1);
+		count++;
+		if (count > 200) {
+			pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+			return -1;
+		}
+	}
+
+	param->size = ioread16(msm_edpram_bt_map.frame_size);
+	memcpy(param->addr, msm_edpram_bt_map.buff, param->size);
+	param->tag = ioread16(msm_edpram_bt_map.tag);
+	param->count = ioread16(msm_edpram_bt_map.count);
+
+	dpctl->clear_intr();
+	dpctl->send_msg(0xDB12);
+
+	return retval;
+
+}
+
+static int msm_data_load(struct _param_nv *param,
+			 struct modemlink_dpram_control *dpctl)
+{
+	int retval = 0;
+
+	if (param->size <= DP_BOOT_FRAME_SIZE_LIMIT) {
+		memcpy(msm_edpram_bt_map.buff, param->addr, param->size);
+		iowrite16(param->size, msm_edpram_bt_map.frame_size);
+		iowrite16(param->tag, msm_edpram_bt_map.tag);
+		iowrite16(param->count, msm_edpram_bt_map.count);
+
+		dpctl->clear_intr();
+		dpctl->send_msg(0xDB12);
+
+	} else {
+		pr_err("[LNK/E]<%s> size:0x%x\n", __func__, param->size);
+	}
+
+	return retval;
+}
+
+static int msm_uload_step1(struct modemlink_dpram_control *dpctl)
+{
+	int retval = 0;
+	int count = 0;
+	u16 in_interrupt = 0, out_interrupt = 0;
+
+	pr_info("[LNK] +---------------------------------------------+\n");
+	pr_info("[LNK] |            UPLOAD PHONE SDRAM               |\n");
+	pr_info("[LNK] +---------------------------------------------+\n");
+
+	while (1) {
+		if (!gpio_get_value(GPIO_MSM_DPRAM_INT)) {
+			in_interrupt = dpctl->recv_msg();
+			pr_info("[LNK] [in_interrupt] 0x%04x\n", in_interrupt);
+			if (in_interrupt == 0x1234) {
+				break;
+			} else {
+				pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+				return -1;
+			}
+		}
+		msleep_interruptible(1);
+		count++;
+		if (count > 200) {
+			pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+			in_interrupt = dpctl->recv_msg();
+			if (in_interrupt == 0x1234) {
+				pr_info("[LNK] [in_interrupt]: 0x%04x\n",
+					in_interrupt);
+				break;
+			}
+			return -1;
+		}
+	}
+	out_interrupt = 0xDEAD;
+	dpctl->send_msg(out_interrupt);
+
+	return retval;
+}
+
+static int msm_uload_step2(void *arg, struct modemlink_dpram_control *dpctl)
+{
+	int retval = 0;
+	struct _param_nv param;
+
+	retval = copy_from_user((void *)&param, (void *)arg, sizeof(param));
+	if (retval < 0) {
+		pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+		return -1;
+	}
+
+	retval = msm_data_upload(&param, dpctl);
+	if (retval < 0) {
+		pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+		return -1;
+	}
+
+	if (!(param.count % 500))
+		pr_info("[LNK] [param->count]:%d\n", param.count);
+
+	if (param.tag == 4) {
+		dpctl->clear_intr();
+		enable_irq(msm_edpram_ctrl.dpram_irq);
+		pr_info("[LNK] [param->tag]:%d\n", param.tag);
+	}
+
+	retval = copy_to_user((unsigned long *)arg, &param, sizeof(param));
+	if (retval < 0) {
+		pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+		return -1;
+	}
+
+	return retval;
+}
+
+static int msm_dload_prep(struct modemlink_dpram_control *dpctl)
+{
+	int retval = 0;
+	int count = 0;
+
+	while (1) {
+		if (check_param.copy_start) {
+			check_param.copy_start = 0;
+			break;
+		}
+		msleep_interruptible(10);
+		count++;
+		if (count > 200) {
+			pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+			return -1;
+		}
+	}
+
+	return retval;
+}
+
+static int msm_dload(void *arg, struct modemlink_dpram_control *dpctl)
+{
+	int retval = 0;
+	int count = 0;
+	struct _param_nv param;
+
+	retval = copy_from_user((void *)&param, (void *)arg, sizeof(param));
+	if (retval < 0) {
+		pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+		return -1;
+	}
+
+	img = vmalloc(param.size);
+	if (img == NULL) {
+		pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+		return -1;
+	}
+	memset(img, 0, param.size);
+	memcpy(img, param.addr, param.size);
+
+	data_param = kzalloc(sizeof(struct _param_nv), GFP_KERNEL);
+	if (data_param == NULL) {
+		pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+		vfree(img);
+		img = NULL;
+		return -1;
+	}
+
+	check_param.total_size = param.size;
+	check_param.rest_size = param.size;
+	check_param.send_size = 0;
+	check_param.copy_complete = 0;
+
+	data_param->addr = img;
+	data_param->size = DP_BOOT_FRAME_SIZE_LIMIT;
+	data_param->count = param.count;
+
+	data_param->tag = 0x0001;
+
+	if (check_param.rest_size < DP_BOOT_FRAME_SIZE_LIMIT)
+		data_param->size = check_param.rest_size;
+
+	retval = msm_data_load(data_param, dpctl);
+
+	while (1) {
+		if (check_param.copy_complete) {
+			check_param.copy_complete = 0;
+
+			vfree(img);
+			img = NULL;
+			kfree(data_param);
+			data_param = NULL;
+
+			break;
+		}
+		msleep_interruptible(10);
+		count++;
+		if (count > 1000) {
+			pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+			vfree(img);
+			img = NULL;
+			kfree(data_param);
+			data_param = NULL;
+			return -1;
+		}
+	}
+
+	return retval;
+
+}
+
+static int msm_nv_load(void *arg, struct modemlink_dpram_control *dpctl)
+{
+	int retval = 0;
+	int count = 0;
+	struct _param_nv param;
+
+	retval = copy_from_user((void *)&param, (void *)arg, sizeof(param));
+	if (retval < 0) {
+		pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+		return -1;
+	}
+
+	nv_img = vmalloc(param.size);
+	if (nv_img == NULL) {
+		pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+		return -1;
+	}
+	memset(nv_img, 0, param.size);
+	memcpy(nv_img, param.addr, param.size);
+
+	data_param = kzalloc(sizeof(struct _param_nv), GFP_KERNEL);
+	if (data_param == NULL) {
+		pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+		vfree(nv_img);
+		nv_img = NULL;
+		return -1;
+	}
+
+	check_param.total_size = param.size;
+	check_param.rest_size = param.size;
+	check_param.send_size = 0;
+	check_param.copy_complete = 0;
+
+	data_param->addr = nv_img;
+	data_param->size = DP_BOOT_FRAME_SIZE_LIMIT;
+	data_param->count = 1;
+	data_param->tag = 0x0002;
+
+	if (check_param.rest_size < DP_BOOT_FRAME_SIZE_LIMIT)
+		data_param->size = check_param.rest_size;
+
+	retval = msm_data_load(data_param, dpctl);
+
+	while (1) {
+		if (check_param.copy_complete) {
+			check_param.copy_complete = 0;
+
+			vfree(nv_img);
+			nv_img = NULL;
+			kfree(data_param);
+			data_param = NULL;
+			break;
+		}
+		msleep_interruptible(10);
+		count++;
+		if (count > 200) {
+			pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+			vfree(nv_img);
+			nv_img = NULL;
+			kfree(data_param);
+			data_param = NULL;
+			return -1;
+		}
+	}
+
+	return retval;
+
+}
+
+static int msm_boot_start(struct modemlink_dpram_control *dpctl)
+{
+
+	u16 out_interrupt = 0;
+	int count = 0;
+
+	/* Send interrupt -> '0x4567' */
+	out_interrupt = 0x4567;
+	dpctl->send_msg(out_interrupt);
+
+	while (1) {
+		if (check_param.boot_complete) {
+			check_param.boot_complete = 0;
+			break;
+		}
+		msleep_interruptible(10);
+		count++;
+		if (count > 200) {
+			pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+			return -1;
+		}
+	}
+
+	return 0;
+}
+
+
+static void msm_terminate_link(struct modemlink_dpram_control *dpctl)
+{
+	pr_info("[LNK] +--------------msm_terminate_link------------+\n");
+	if (img != NULL) {
+		pr_info("[LNK] +--------------img free----------------+\n");
+		vfree(img);
+		img = NULL;
+	}
+	if (nv_img != NULL) {
+		pr_info("[LNK] +--------------nv_img free----------------+\n");
+		vfree(nv_img);
+		nv_img = NULL;
+	}
+	if (data_param != NULL) {
+		pr_info("[LNK] +--------------data_param free----------------+\n");
+		kfree(data_param);
+		data_param = NULL;
+	}
+
+}
+
+static struct modemlink_dpram_control *tasklet_dpctl;
+
+static void interruptable_load_tasklet_handler(unsigned long data);
+
+static DECLARE_TASKLET(interruptable_load_tasklet,
+		       interruptable_load_tasklet_handler,
+		       (unsigned long)&tasklet_dpctl);
+
+static void interruptable_load_tasklet_handler(unsigned long data)
+{
+	struct modemlink_dpram_control *dpctl =
+	    (struct modemlink_dpram_control *)
+	    (*((struct modemlink_dpram_control **)data));
+
+	if (data_param == NULL) {
+		pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+		return;
+	}
+
+	check_param.send_size += data_param->size;
+	check_param.rest_size -= data_param->size;
+	data_param->addr += data_param->size;
+
+	if (check_param.send_size < check_param.total_size) {
+
+		if (check_param.rest_size < DP_BOOT_FRAME_SIZE_LIMIT)
+			data_param->size = check_param.rest_size;
+
+		data_param->count += 1;
+
+		msm_data_load(data_param, dpctl);
+	} else {
+		data_param->tag = 0;
+		check_param.copy_complete = 1;
+	}
+
+}
+
+static int msm_boot_start_post_proc(void)
+{
+	int count = 0;
+
+	while (1) {
+		if (boot_start_complete) {
+			boot_start_complete = 0;
+			break;
+		}
+		msleep_interruptible(10);
+		count++;
+		if (count > 200) {
+			pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+			return -1;
+		}
+	}
+
+	return 0;
+}
+
+static void msm_boot_start_handler(struct modemlink_dpram_control *dpctl)
+{
+	boot_start_complete = 1;
+
+	/* Send INIT_END code to CP */
+	pr_info("[LNK] <%s> Send 0x11C2 (INIT_END)\n", __func__);
+
+	/*
+	 * INT_MASK_VALID|INT_MASK_CMD|INT_MASK_CP_AIRPLANE_BOOT|
+	 * INT_MASK_CP_AP_ANDROID|INT_MASK_CMD_INIT_END
+	 */
+	dpctl->send_intr((0x0080 | 0x0040 | 0x1000 | 0x0100 | 0x0002));
+}
+
+static void msm_dload_handler(struct modemlink_dpram_control *dpctl, u16 cmd)
+{
+	switch (cmd) {
+	case 0x1234:
+		check_param.copy_start = 1;
+		break;
+
+	case 0xDBAB:
+		tasklet_schedule(&interruptable_load_tasklet);
+		break;
+
+	case 0xABCD:
+		check_param.boot_complete = 1;
+		break;
+
+	default:
+		pr_err("[LNK/Err] <%s> Unknown command.. %x\n", __func__, cmd);
+	}
+}
+
+static void msm_bt_map_init(struct modemlink_dpram_control *dpctl)
+{
+	msm_edpram_bt_map.buff = (u8 *) (dpctl->dp_base);
+	msm_edpram_bt_map.frame_size =
+	    (u16 *) (dpctl->dp_base + DP_BOOT_SIZE_OFFSET);
+	msm_edpram_bt_map.tag = (u16 *) (dpctl->dp_base + DP_BOOT_TAG_OFFSET);
+	msm_edpram_bt_map.count =
+	    (u16 *) (dpctl->dp_base + DP_BOOT_COUNT_OFFSET);
+}
+
+static void msm_load_init(struct modemlink_dpram_control *dpctl)
+{
+	tasklet_dpctl = dpctl;
+	if (tasklet_dpctl == NULL)
+		pr_err("[LNK/Err] failed tasklet_dpctl remap\n");
+
+	check_param.total_size = 0;
+	check_param.rest_size = 0;
+	check_param.send_size = 0;
+	check_param.copy_start = 0;
+	check_param.copy_complete = 0;
+	check_param.boot_complete = 0;
+
+	dpctl->clear_intr();
+}
+
+static irqreturn_t host_wakeup_isr(int irq, void *dev)
+{
+	pr_err("[MODEMS] <%s>\n", __func__);
+
+	return IRQ_HANDLED;
+}
+
+static void config_cdma_modem_gpio(void)
+{
+	int err;
+	unsigned gpio_cp_on = cdma_modem_data.gpio_cp_on;
+	unsigned gpio_cp_off = cdma_modem_data.gpio_cp_off;
+	unsigned gpio_rst_req_n = cdma_modem_data.gpio_reset_req_n;
+	unsigned gpio_cp_rst = cdma_modem_data.gpio_cp_reset;
+	unsigned gpio_pda_active = cdma_modem_data.gpio_pda_active;
+	unsigned gpio_phone_active = cdma_modem_data.gpio_phone_active;
+	unsigned gpio_flm_uart_sel = cdma_modem_data.gpio_flm_uart_sel;
+#if 1
+	unsigned gpio_flm_uart_sel_rev06 =
+	    cdma_modem_data.gpio_flm_uart_sel_rev06;
+#endif
+	unsigned gpio_dpram_int = cdma_modem_data.gpio_dpram_int;
+	unsigned gpio_host_wakeup = cdma_modem_data.gpio_host_wakeup;
+
+	pr_info("[MODEMS] <%s>\n", __func__);
+
+	if (gpio_pda_active) {
+		err = gpio_request(gpio_pda_active, "PDA_ACTIVE");
+		if (err) {
+			pr_err("fail to request gpio %s\n", "PDA_ACTIVE");
+		} else {
+			gpio_direction_output(gpio_pda_active, 1);
+			s3c_gpio_setpull(gpio_pda_active, S3C_GPIO_PULL_NONE);
+			gpio_set_value(gpio_pda_active, 0);
+		}
+	}
+
+	if (gpio_phone_active) {
+		err = gpio_request(gpio_phone_active, "MSM_ACTIVE");
+		if (err) {
+			pr_err("fail to request gpio %s\n", "MSM_ACTIVE");
+		} else {
+			s3c_gpio_cfgpin(gpio_phone_active, S3C_GPIO_SFN(0xF));
+			s3c_gpio_setpull(gpio_phone_active, S3C_GPIO_PULL_NONE);
+			irq_set_irq_type(gpio_phone_active, IRQ_TYPE_EDGE_BOTH);
+		}
+	}
+
+	if (system_rev < 11) {
+		if (gpio_flm_uart_sel) {
+			err = gpio_request(gpio_flm_uart_sel, "BOOT_SW_SEL");
+			if (err) {
+				pr_err("fail request gpio %s\n", "BOOT_SW_SEL");
+			} else {
+				gpio_direction_output(gpio_flm_uart_sel, 1);
+				s3c_gpio_setpull(gpio_flm_uart_sel,
+						S3C_GPIO_PULL_NONE);
+				gpio_set_value(gpio_flm_uart_sel, 1);
+			}
+		}
+	} else if (system_rev == 11) {
+		if (gpio_flm_uart_sel) {
+			err = gpio_request(gpio_flm_uart_sel, "BOOT_SW_SEL");
+			if (err) {
+				pr_err("fail request gpio %s\n", "BOOT_SW_SEL");
+			} else {
+				gpio_direction_output(gpio_flm_uart_sel, 1);
+				s3c_gpio_setpull(gpio_flm_uart_sel,
+						S3C_GPIO_PULL_NONE);
+				gpio_set_value(gpio_flm_uart_sel, 1);
+			}
+		}
+		if (gpio_flm_uart_sel_rev06) {
+			err = gpio_request(gpio_flm_uart_sel_rev06,
+					   "BOOT_SW_SEL_REV06");
+			if (err) {
+				pr_err("fail request gpio %s\n",
+				       "BOOT_SW_SEL_REV06");
+			} else {
+				gpio_direction_output(gpio_flm_uart_sel_rev06,
+						      1);
+				s3c_gpio_setpull(gpio_flm_uart_sel_rev06,
+						S3C_GPIO_PULL_NONE);
+				gpio_set_value(gpio_flm_uart_sel_rev06, 1);
+			}
+		}
+	} else {
+		err =
+		    gpio_request(gpio_flm_uart_sel_rev06, "BOOT_SW_SEL_REV06");
+		if (err) {
+			pr_err("fail request gpio %s\n", "BOOT_SW_SEL_REV06");
+		} else {
+			gpio_direction_output(gpio_flm_uart_sel_rev06, 1);
+			s3c_gpio_setpull(gpio_flm_uart_sel_rev06,
+					S3C_GPIO_PULL_NONE);
+			gpio_set_value(gpio_flm_uart_sel_rev06, 1);
+		}
+	}
+
+	if (gpio_cp_on) {
+		err = gpio_request(gpio_cp_on, "MSM_ON");
+		if (err) {
+			pr_err("fail to request gpio %s\n", "MSM_ON");
+		} else {
+			gpio_direction_output(gpio_cp_on, 1);
+			s3c_gpio_setpull(gpio_cp_on, S3C_GPIO_PULL_NONE);
+			gpio_set_value(gpio_cp_on, 0);
+		}
+	}
+
+	if (gpio_cp_off) {
+		err = gpio_request(gpio_cp_off, "MSM_OFF");
+		if (err) {
+			pr_err("fail to request gpio %s\n", "MSM_OFF");
+		} else {
+			gpio_direction_output(gpio_cp_off, 1);
+			s3c_gpio_setpull(gpio_cp_off, S3C_GPIO_PULL_NONE);
+			gpio_set_value(gpio_cp_off, 1);
+		}
+	}
+
+	if (gpio_rst_req_n) {
+		err = gpio_request(gpio_rst_req_n, "MSM_RST_REQ");
+		if (err) {
+			pr_err("fail to request gpio %s\n", "MSM_RST_REQ");
+		} else {
+			gpio_direction_output(gpio_rst_req_n, 1);
+			s3c_gpio_setpull(gpio_rst_req_n, S3C_GPIO_PULL_NONE);
+		}
+		gpio_set_value(gpio_rst_req_n, 0);
+	}
+
+	if (gpio_cp_rst) {
+		err = gpio_request(gpio_cp_rst, "MSM_RST");
+		if (err) {
+			pr_err("fail to request gpio %s\n", "MSM_RST");
+		} else {
+			gpio_direction_output(gpio_cp_rst, 1);
+			s3c_gpio_setpull(gpio_cp_rst, S3C_GPIO_PULL_NONE);
+		}
+		gpio_set_value(gpio_cp_rst, 0);
+	}
+
+	if (gpio_dpram_int) {
+		err = gpio_request(gpio_dpram_int, "MSM_DPRAM_INT");
+		if (err) {
+			pr_err("fail to request gpio %s\n", "MSM_DPRAM_INT");
+		} else {
+			/* Configure as a wake-up source */
+			s3c_gpio_cfgpin(gpio_dpram_int, S3C_GPIO_SFN(0xF));
+			s3c_gpio_setpull(gpio_dpram_int, S3C_GPIO_PULL_NONE);
+		}
+	}
+
+	if (gpio_host_wakeup) {
+		err = gpio_request(gpio_host_wakeup, "MSM_HOST_WAKEUP");
+		if (err) {
+			pr_err("fail to request gpio %s\n", "MSM_HOST_WAKEUP");
+		} else {
+			/* Configure as a wake-up source */
+			s3c_gpio_cfgpin(gpio_host_wakeup, S3C_GPIO_SFN(0xF));
+			s3c_gpio_setpull(gpio_host_wakeup, S3C_GPIO_PULL_NONE);
+			irq_set_irq_type(gpio_to_irq(gpio_host_wakeup),
+					IRQ_TYPE_LEVEL_HIGH);
+		}
+	}
+}
+
+static u8 *msm_edpram_remap_mem_region(struct sromc_cfg *cfg)
+{
+	int dp_addr = 0;
+	int dp_size = 0;
+	u8 __iomem *dp_base = NULL;
+	struct msm_edpram_ipc_cfg *ipc_map = NULL;
+	struct dpram_ipc_device *dev = NULL;
+
+	dp_addr = cfg->addr;
+	dp_size = cfg->size;
+	dp_base = (u8 *) ioremap_nocache(dp_addr, dp_size);
+	if (!dp_base) {
+		pr_err("[MDM] <%s> dpram base ioremap fail\n", __func__);
+		return NULL;
+	}
+	pr_info("[MDM] <%s> DPRAM VA=0x%08X\n", __func__, (int)dp_base);
+
+	msm_edpram_ctrl.dp_base = (u8 __iomem *) dp_base;
+	msm_edpram_ctrl.dp_size = dp_size;
+
+	/* Map for IPC */
+	ipc_map = (struct msm_edpram_ipc_cfg *)dp_base;
+
+	/* Magic code and access enable fields */
+	msm_ipc_map.magic = (u16 __iomem *) &ipc_map->magic;
+	msm_ipc_map.access = (u16 __iomem *) &ipc_map->access;
+
+	/* FMT */
+	dev = &msm_ipc_map.dev[IPC_FMT];
+
+	strcpy(dev->name, "FMT");
+	dev->id = IPC_FMT;
+
+	dev->txq.head = (u16 __iomem *) &ipc_map->fmt_tx_head;
+	dev->txq.tail = (u16 __iomem *) &ipc_map->fmt_tx_tail;
+	dev->txq.buff = (u8 __iomem *) &ipc_map->fmt_tx_buff[0];
+	dev->txq.size = MSM_DP_FMT_TX_BUFF_SZ;
+
+	dev->rxq.head = (u16 __iomem *) &ipc_map->fmt_rx_head;
+	dev->rxq.tail = (u16 __iomem *) &ipc_map->fmt_rx_tail;
+	dev->rxq.buff = (u8 __iomem *) &ipc_map->fmt_rx_buff[0];
+	dev->rxq.size = MSM_DP_FMT_RX_BUFF_SZ;
+
+	dev->mask_req_ack = INT_MASK_REQ_ACK_F;
+	dev->mask_res_ack = INT_MASK_RES_ACK_F;
+	dev->mask_send = INT_MASK_SEND_F;
+
+	/* RAW */
+	dev = &msm_ipc_map.dev[IPC_RAW];
+
+	strcpy(dev->name, "RAW");
+	dev->id = IPC_RAW;
+
+	dev->txq.head = (u16 __iomem *) &ipc_map->raw_tx_head;
+	dev->txq.tail = (u16 __iomem *) &ipc_map->raw_tx_tail;
+	dev->txq.buff = (u8 __iomem *) &ipc_map->raw_tx_buff[0];
+	dev->txq.size = MSM_DP_RAW_TX_BUFF_SZ;
+
+	dev->rxq.head = (u16 __iomem *) &ipc_map->raw_rx_head;
+	dev->rxq.tail = (u16 __iomem *) &ipc_map->raw_rx_tail;
+	dev->rxq.buff = (u8 __iomem *) &ipc_map->raw_rx_buff[0];
+	dev->rxq.size = MSM_DP_RAW_RX_BUFF_SZ;
+
+	dev->mask_req_ack = INT_MASK_REQ_ACK_R;
+	dev->mask_res_ack = INT_MASK_RES_ACK_R;
+	dev->mask_send = INT_MASK_SEND_R;
+
+#if 0
+	/* RFS */
+	dev = &msm_ipc_map.dev[IPC_RFS];
+
+	strcpy(dev->name, "RFS");
+	dev->id = IPC_RFS;
+
+	dev->txq.head = (u16 __iomem *) &ipc_map->rfs_tx_head;
+	dev->txq.tail = (u16 __iomem *) &ipc_map->rfs_tx_tail;
+	dev->txq.buff = (u8 __iomem *) &ipc_map->rfs_tx_buff[0];
+	dev->txq.size = MSM_DP_RFS_TX_BUFF_SZ;
+
+	dev->rxq.head = (u16 __iomem *) &ipc_map->rfs_rx_head;
+	dev->rxq.tail = (u16 __iomem *) &ipc_map->rfs_rx_tail;
+	dev->rxq.buff = (u8 __iomem *) &ipc_map->rfs_rx_buff[0];
+	dev->rxq.size = MSM_DP_RFS_RX_BUFF_SZ;
+
+	dev->mask_req_ack = INT_MASK_REQ_ACK_RFS;
+	dev->mask_res_ack = INT_MASK_RES_ACK_RFS;
+	dev->mask_send = INT_MASK_SEND_RFS;
+#endif
+
+	/* Mailboxes */
+	msm_ipc_map.mbx_ap2cp = (u16 __iomem *) &ipc_map->mbx_ap2cp;
+	msm_ipc_map.mbx_cp2ap = (u16 __iomem *) &ipc_map->mbx_cp2ap;
+
+	return dp_base;
+}
+
+/**
+ *	DPRAM GPIO settings
+ *
+ *	SROM_NUM_ADDR_BITS value indicate the address line number or
+ *	the mux/demux dpram type. if you want to set mux mode, define the
+ *	SROM_NUM_ADDR_BITS to zero.
+ *
+ *	for CMC22x
+ *	CMC22x has 16KB + a SFR register address.
+ *	It used 14 bits (13bits for 16KB word address and 1 bit for SFR
+ *	register)
+ */
+static void config_dpram_port_gpio(void)
+{
+	int addr_bits = SROM_NUM_ADDR_BITS;
+
+	pr_info("[MDM] <%s> address line = %d bits\n", __func__, addr_bits);
+
+	/*
+	 ** Config DPRAM address/data GPIO pins
+	 */
+
+	/* Set GPIO for dpram address */
+	switch (addr_bits) {
+	case 0:
+		break;
+
+	case 13 ... 14:
+		s3c_gpio_cfgrange_nopull(EXYNOS4_GPY3(0), EXYNOS4_GPIO_Y3_NR,
+					 S3C_GPIO_SFN(2));
+		s3c_gpio_cfgrange_nopull(EXYNOS4_GPY4(0),
+					 addr_bits - EXYNOS4_GPIO_Y3_NR,
+					 S3C_GPIO_SFN(2));
+		pr_info("[MDM] <%s> last data gpio EXYNOS4_GPY4(0) ~ %d\n",
+			__func__, addr_bits - EXYNOS4_GPIO_Y3_NR);
+		break;
+
+	default:
+		pr_err("[MDM/E] <%s> Invalid addr_bits!!!\n", __func__);
+		return;
+	}
+
+	/* Set GPIO for dpram data - 16bit */
+	s3c_gpio_cfgrange_nopull(EXYNOS4_GPY5(0), 8, S3C_GPIO_SFN(2));
+	s3c_gpio_cfgrange_nopull(EXYNOS4_GPY6(0), 8, S3C_GPIO_SFN(2));
+
+	/* Setup SROMC CSn pins */
+	s3c_gpio_cfgpin(GPIO_DPRAM_CSN0, S3C_GPIO_SFN(2));
+
+	/* Config OEn, WEn */
+	s3c_gpio_cfgrange_nopull(GPIO_DPRAM_REN, 2, S3C_GPIO_SFN(2));
+
+	/* Config LBn, UBn */
+	s3c_gpio_cfgrange_nopull(GPIO_DPRAM_LBN, 2, S3C_GPIO_SFN(2));
+
+	/* Config BUSY */
+	s3c_gpio_cfgpin(GPIO_DPRAM_BUSY, S3C_GPIO_SFN(2));
+}
+
+static void init_sromc(void)
+{
+	struct clk *clk = NULL;
+
+	/* SROMC clk enable */
+	clk = clk_get(NULL, "sromc");
+	if (!clk) {
+		pr_err("[MDM/E] <%s> SROMC clock gate fail\n", __func__);
+		return;
+	}
+	clk_enable(clk);
+}
+
+static void setup_sromc
+(unsigned csn, struct sromc_cfg *cfg, struct sromc_access_cfg *acc_cfg) {
+	unsigned bw = 0;
+	unsigned bc = 0;
+	void __iomem *bank_sfr = S5P_SROM_BC0 + (4 * csn);
+
+	pr_err("[MDM] <%s> SROMC settings for CS%d...\n", __func__, csn);
+
+	bw = __raw_readl(S5P_SROM_BW);
+	bc = __raw_readl(bank_sfr);
+	pr_err("[MDM] <%s> Old SROMC settings = BW(0x%08X), BC%d(0x%08X)\n",
+	       __func__, bw, csn, bc);
+
+	/* Set the BW control field for the CSn */
+	bw &= ~(SROMC_MASK << (csn * 4));
+
+	if (cfg->attr | MEM_DATA_BUS_16BIT)
+		bw |= (SROMC_DATA_16 << (csn * 4));
+
+	if (cfg->attr | MEM_WAIT_EN)
+		bw |= (SROMC_WAIT_EN << (csn * 4));
+
+	if (cfg->attr | MEM_BYTE_EN)
+		bw |= (SROMC_BYTE_EN << (csn * 4));
+
+	writel(bw, S5P_SROM_BW);
+
+	/* Set SROMC memory access timing for the CSn */
+	bc = acc_cfg->tacs | acc_cfg->tcos | acc_cfg->tacc |
+	    acc_cfg->tcoh | acc_cfg->tcah | acc_cfg->tacp | acc_cfg->pmc;
+
+	writel(bc, bank_sfr);
+
+	/* Verify SROMC settings */
+	bw = __raw_readl(S5P_SROM_BW);
+	bc = __raw_readl(bank_sfr);
+	pr_err("[MDM] <%s> New SROMC settings = BW(0x%08X), BC%d(0x%08X)\n",
+	       __func__, bw, csn, bc);
+}
+
+static void setup_dpram_speed(unsigned csn, struct sromc_access_cfg *acc_cfg)
+{
+	void __iomem *bank_sfr = S5P_SROM_BC0 + (4 * csn);
+	unsigned bc = 0;
+
+	bc = __raw_readl(bank_sfr);
+	pr_info("[MDM] <%s> Old CS%d setting = 0x%08X\n", __func__, csn, bc);
+
+	/* SROMC memory access timing setting */
+	bc = acc_cfg->tacs | acc_cfg->tcos | acc_cfg->tacc |
+	    acc_cfg->tcoh | acc_cfg->tcah | acc_cfg->tacp | acc_cfg->pmc;
+	writel(bc, bank_sfr);
+
+	bc = __raw_readl(bank_sfr);
+	pr_err("[MDM] <%s> New CS%d setting = 0x%08X\n", __func__, csn, bc);
+}
+
+static int __init init_modem(void)
+{
+	struct sromc_cfg *cfg = NULL;
+	struct sromc_access_cfg *acc_cfg = NULL;
+
+	msm_edpram_cfg.csn = 0;
+	msm_edpram_cfg.addr = SROM_CS0_BASE + (SROM_WIDTH * msm_edpram_cfg.csn);
+	msm_edpram_cfg.end = msm_edpram_cfg.addr + msm_edpram_cfg.size - 1;
+
+	config_dpram_port_gpio();
+	config_cdma_modem_gpio();
+
+	init_sromc();
+	cfg = &msm_edpram_cfg;
+	acc_cfg = &msm_edpram_access_cfg[DPRAM_SPEED_LOW];
+	setup_sromc(cfg->csn, cfg, acc_cfg);
+
+	if (!msm_edpram_remap_mem_region(&msm_edpram_cfg))
+		return -1;
+	platform_device_register(&cdma_modem);
+
+	return 0;
+}
+
+late_initcall(init_modem);
+/*device_initcall(init_modem);*/
+
+#ifdef CONFIG_USBHUB_USB3503
+static int (*usbhub_set_mode) (struct usb3503_hubctl *, int);
+static struct usb3503_hubctl *usbhub_ctl;
+
+void set_host_states(struct platform_device *pdev, int type)
+{
+}
+
+static int usb3503_hub_handler(void (*set_mode) (void), void *ctl)
+{
+	if (!set_mode || !ctl)
+		return -EINVAL;
+
+	usbhub_set_mode = (int (*)(struct usb3503_hubctl *, int))set_mode;
+	usbhub_ctl = (struct usb3503_hubctl *)ctl;
+
+	pr_info("[MDM] <%s> set_mode(%pF)\n", __func__, set_mode);
+
+	return 0;
+}
+
+static int usb3503_hw_config(void)
+{
+	int err;
+
+	err = gpio_request(GPIO_USB_HUB_CONNECT, "HUB_CONNECT");
+	if (err) {
+		pr_err("fail to request gpio %s\n", "HUB_CONNECT");
+	} else {
+		gpio_direction_output(GPIO_USB_HUB_CONNECT, 0);
+		s3c_gpio_setpull(GPIO_USB_HUB_CONNECT, S3C_GPIO_PULL_NONE);
+	}
+	s5p_gpio_set_drvstr(GPIO_USB_HUB_CONNECT, S5P_GPIO_DRVSTR_LV1);
+
+	if (system_rev < 11) {
+		err = gpio_request(GPIO_USB_BOOT_EN, "USB_BOOT_EN");
+		if (err) {
+			pr_err("fail to request gpio %s\n", "USB_BOOT_EN");
+		} else {
+			gpio_direction_output(GPIO_USB_BOOT_EN, 1);
+			s3c_gpio_setpull(GPIO_USB_BOOT_EN, S3C_GPIO_PULL_NONE);
+		}
+	} else if (system_rev == 11) {
+		err = gpio_request(GPIO_USB_BOOT_EN, "USB_BOOT_EN");
+		if (err) {
+			pr_err("fail to request gpio %s\n", "USB_BOOT_EN");
+		} else {
+			gpio_direction_output(GPIO_USB_BOOT_EN, 1);
+			s3c_gpio_setpull(GPIO_USB_BOOT_EN, S3C_GPIO_PULL_NONE);
+		}
+		err = gpio_request(GPIO_USB_BOOT_EN_REV06, "USB_BOOT_EN_REV06");
+		if (err) {
+			pr_err("fail to request gpio %s\n",
+			       "USB_BOOT_EN_REV06");
+		} else {
+			gpio_direction_output(GPIO_USB_BOOT_EN_REV06, 1);
+			s3c_gpio_setpull(GPIO_USB_BOOT_EN_REV06,
+					 S3C_GPIO_PULL_NONE);
+		}
+	} else {
+		err = gpio_request(GPIO_USB_BOOT_EN_REV06, "USB_BOOT_EN_REV06");
+		if (err) {
+			pr_err("fail to request gpio %s\n",
+			       "USB_BOOT_EN_REV06");
+		} else {
+			gpio_direction_output(GPIO_USB_BOOT_EN_REV06, 1);
+			s3c_gpio_setpull(GPIO_USB_BOOT_EN_REV06,
+					 S3C_GPIO_PULL_NONE);
+		}
+	}
+
+	msleep(100);
+
+	err = gpio_request(GPIO_USB_HUB_RST, "HUB_RST");
+	if (err) {
+		pr_err("fail to request gpio %s\n", "HUB_RST");
+	} else {
+		gpio_direction_output(GPIO_USB_HUB_RST, 0);
+		s3c_gpio_setpull(GPIO_USB_HUB_RST, S3C_GPIO_PULL_NONE);
+	}
+	s5p_gpio_set_drvstr(GPIO_USB_HUB_RST, S5P_GPIO_DRVSTR_LV1);
+	/* need to check drvstr 1 or 2 */
+
+	/* for USB3503 26Mhz Reference clock setting */
+	err = gpio_request(GPIO_USB_HUB_INT, "HUB_INT");
+	if (err) {
+		pr_err("fail to request gpio %s\n", "HUB_INT");
+	} else {
+		gpio_direction_output(GPIO_USB_HUB_INT, 1);
+		s3c_gpio_setpull(GPIO_USB_HUB_INT, S3C_GPIO_PULL_NONE);
+	}
+
+	return 0;
+}
+
+static int usb3503_reset_n(int val)
+{
+	gpio_set_value(GPIO_USB_HUB_RST, 0);
+	msleep(20);
+	pr_info("[MDM] <%s> val = %d\n", __func__,
+		gpio_get_value(GPIO_USB_HUB_RST));
+	gpio_set_value(GPIO_USB_HUB_RST, !!val);
+
+	pr_info("[MDM] <%s> val = %d\n", __func__,
+		gpio_get_value(GPIO_USB_HUB_RST));
+
+	udelay(5);		/* need it ? */
+	return 0;
+}
+
+static struct usb3503_platform_data usb3503_pdata = {
+	.initial_mode = USB3503_MODE_STANDBY,
+	.reset_n = usb3503_reset_n,
+	.register_hub_handler = usb3503_hub_handler,
+	.port_enable = host_port_enable,
+};
+
+static struct i2c_board_info i2c_devs20_emul[] __initdata = {
+	{
+	 I2C_BOARD_INFO(USB3503_I2C_NAME, 0x08),
+	 .platform_data = &usb3503_pdata,
+	 },
+};
+
+/* I2C20_EMUL */
+static struct i2c_gpio_platform_data i2c20_platdata = {
+	.sda_pin = GPIO_USB_HUB_SDA,
+	.scl_pin = GPIO_USB_HUB_SCL,
+	/*FIXME: need to timming tunning...  */
+	.udelay = 20,
+};
+
+static struct platform_device s3c_device_i2c20 = {
+	.name = "i2c-gpio",
+	.id = 20,
+	.dev.platform_data = &i2c20_platdata,
+};
+
+static int __init init_usbhub(void)
+{
+	usb3503_hw_config();
+	i2c_register_board_info(20, i2c_devs20_emul,
+				ARRAY_SIZE(i2c_devs20_emul));
+
+	platform_device_register(&s3c_device_i2c20);
+	return 0;
+}
+
+device_initcall(init_usbhub);
+
+static int host_port_enable(int port, int enable)
+{
+	int err, retry = 30;
+
+	pr_info("[MDM] <%s> port(%d) control(%d)\n", __func__, port, enable);
+
+	if (enable) {
+		err = usbhub_set_mode(usbhub_ctl, USB3503_MODE_HUB);
+		if (err < 0) {
+			pr_err("[MDM] <%s> hub on fail\n", __func__);
+			goto exit;
+		}
+		err = s5p_ehci_port_control(&s5p_device_ehci, port, 1);
+		if (err < 0) {
+			pr_err("[MDM] <%s> port(%d) enable fail\n", __func__,
+			       port);
+			goto exit;
+		}
+	} else {
+		err = s5p_ehci_port_control(&s5p_device_ehci, port, 0);
+		if (err < 0) {
+			pr_err("[MDM] <%s> port(%d) enable fail\n", __func__,
+			       port);
+			goto exit;
+		}
+		err = usbhub_set_mode(usbhub_ctl, USB3503_MODE_STANDBY);
+		if (err < 0) {
+			pr_err("[MDM] <%s> hub off fail\n", __func__);
+			goto exit;
+		}
+
+		gpio_direction_output(GPIO_USB_BOOT_EN, 0);
+		s3c_gpio_setpull(GPIO_USB_BOOT_EN, S3C_GPIO_PULL_NONE);
+		gpio_set_value(GPIO_USB_BOOT_EN, 0);
+
+		gpio_direction_output(GPIO_USB_BOOT_EN, 1);
+		gpio_set_value(GPIO_USB_BOOT_EN, 1);
+
+		gpio_direction_output(GPIO_BOOT_SW_SEL, 0);
+		s3c_gpio_setpull(GPIO_BOOT_SW_SEL, S3C_GPIO_PULL_NONE);
+		gpio_set_value(GPIO_BOOT_SW_SEL, 0);
+
+		gpio_direction_output(GPIO_BOOT_SW_SEL, 1);
+		gpio_set_value(GPIO_BOOT_SW_SEL, 1);
+
+		if (system_rev < 11) {
+			gpio_direction_output(GPIO_USB_BOOT_EN, 0);
+			s3c_gpio_setpull(GPIO_USB_BOOT_EN, S3C_GPIO_PULL_NONE);
+			gpio_set_value(GPIO_USB_BOOT_EN, 0);
+
+			gpio_direction_output(GPIO_USB_BOOT_EN, 1);
+			gpio_set_value(GPIO_USB_BOOT_EN, 1);
+
+			gpio_direction_output(GPIO_BOOT_SW_SEL, 0);
+			s3c_gpio_setpull(GPIO_BOOT_SW_SEL, S3C_GPIO_PULL_NONE);
+			gpio_set_value(GPIO_BOOT_SW_SEL, 0);
+
+			gpio_direction_output(GPIO_BOOT_SW_SEL, 1);
+			gpio_set_value(GPIO_BOOT_SW_SEL, 1);
+		} else if (system_rev == 11) {
+			gpio_direction_output(GPIO_USB_BOOT_EN, 0);
+			s3c_gpio_setpull(GPIO_USB_BOOT_EN, S3C_GPIO_PULL_NONE);
+			gpio_set_value(GPIO_USB_BOOT_EN, 0);
+
+			gpio_direction_output(GPIO_USB_BOOT_EN, 1);
+			gpio_set_value(GPIO_USB_BOOT_EN, 1);
+
+			gpio_direction_output(GPIO_BOOT_SW_SEL, 0);
+			s3c_gpio_setpull(GPIO_BOOT_SW_SEL, S3C_GPIO_PULL_NONE);
+			gpio_set_value(GPIO_BOOT_SW_SEL, 0);
+
+			gpio_direction_output(GPIO_BOOT_SW_SEL, 1);
+			gpio_set_value(GPIO_BOOT_SW_SEL, 1);
+
+			gpio_direction_output(GPIO_USB_BOOT_EN_REV06, 0);
+			s3c_gpio_setpull(GPIO_USB_BOOT_EN_REV06,
+					 S3C_GPIO_PULL_NONE);
+			gpio_set_value(GPIO_USB_BOOT_EN_REV06, 0);
+
+			gpio_direction_output(GPIO_USB_BOOT_EN_REV06, 1);
+			gpio_set_value(GPIO_USB_BOOT_EN_REV06, 1);
+
+			gpio_direction_output(GPIO_BOOT_SW_SEL_REV06, 0);
+			s3c_gpio_setpull(GPIO_BOOT_SW_SEL_REV06,
+					 S3C_GPIO_PULL_NONE);
+			gpio_set_value(GPIO_BOOT_SW_SEL_REV06, 0);
+
+			gpio_direction_output(GPIO_BOOT_SW_SEL_REV06, 1);
+			gpio_set_value(GPIO_BOOT_SW_SEL_REV06, 1);
+
+		} else {
+			gpio_direction_output(GPIO_USB_BOOT_EN_REV06, 0);
+			s3c_gpio_setpull(GPIO_USB_BOOT_EN_REV06,
+					 S3C_GPIO_PULL_NONE);
+			gpio_set_value(GPIO_USB_BOOT_EN_REV06, 0);
+
+			gpio_direction_output(GPIO_USB_BOOT_EN_REV06, 1);
+			gpio_set_value(GPIO_USB_BOOT_EN_REV06, 1);
+
+			gpio_direction_output(GPIO_BOOT_SW_SEL_REV06, 0);
+			s3c_gpio_setpull(GPIO_BOOT_SW_SEL_REV06,
+					 S3C_GPIO_PULL_NONE);
+			gpio_set_value(GPIO_BOOT_SW_SEL_REV06, 0);
+
+			gpio_direction_output(GPIO_BOOT_SW_SEL_REV06, 1);
+			gpio_set_value(GPIO_BOOT_SW_SEL_REV06, 1);
+
+		}
+
+	}
+
+ exit:
+	return err;
+}
+#else
+void set_host_states(struct platform_device *pdev, int type)
+{
+	if (active_ctl.gpio_initialized) {
+		pr_err(" [MODEM_IF] Active States =%d, %s\n", type, pdev->name);
+		gpio_direction_output(modem_link_pm_data.gpio_link_active,
+				      type);
+	} else
+		active_ctl.gpio_request_host_active = 1;
+}
+#endif
diff --git a/arch/arm/mach-exynos/board-midas-modems.c b/arch/arm/mach-exynos/board-midas-modems.c
new file mode 100644
index 0000000..635fbbd
--- /dev/null
+++ b/arch/arm/mach-exynos/board-midas-modems.c
@@ -0,0 +1,250 @@
+/* linux/arch/arm/mach-xxxx/board-midas-modems.c
+ * Copyright (C) 2010 Samsung Electronics. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+#include <linux/platform_data/modem.h>
+
+/* umts target platform data */
+static struct modem_io_t umts_io_devices[] = {
+	[0] = {
+		.name = "umts_boot0",
+		.id = 0x0,
+		.format = IPC_BOOT,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_C2C),
+	},
+	[1] = {
+		.name = "umts_ipc0",
+		.id = 0x1,
+		.format = IPC_FMT,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[2] = {
+		.name = "umts_rfs0",
+		.id = 0x41,
+		.format = IPC_RFS,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[3] = {
+		.name = "multipdp",
+		.id = 0x1,
+		.format = IPC_MULTI_RAW,
+		.io_type = IODEV_DUMMY,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[4] = {
+		.name = "rmnet0",
+		.id = 0x2A,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[5] = {
+		.name = "rmnet1",
+		.id = 0x2B,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[6] = {
+		.name = "rmnet2",
+		.id = 0x2C,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[7] = {
+		.name = "umts_router",
+		.id = 0x39,
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[8] = {
+		.name = "umts_csd",
+		.id = 0x21,
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+};
+
+/* To get modem state, register phone active irq using resource */
+static struct resource umts_modem_res[] = {
+	[0] = {
+		.name = "umts_phone_active",
+		.start = PHONE_ACTIVE_IRQ,
+		.end = PHONE_ACTIVE_IRQ,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+static int umts_link_ldo_enble(bool enable)
+{
+	/* Exynos HSIC V1.2 LDO was controlled by kernel */
+	return 0;
+}
+
+static struct modemlink_pm_data modem_link_pm_data = {
+	.name = "link_pm",
+	.link_ldo_enable = umts_link_ldo_enble,
+	.gpio_link_enable = 0,
+	.gpio_link_active = GPIO_ACTIVE_STATE,
+	.gpio_link_hostwake = GPIO_IPC_HOST_WAKEUP,
+	.gpio_link_slavewake = GPIO_IPC_SLAVE_WAKEUP,
+};
+static struct modemlink_pm_link_activectl active_ctl;
+
+static struct modem_data umts_modem_data = {
+	.name = "xmm6262",
+
+	.gpio_cp_on = CP_ON,
+	.gpio_reset_req_n = CP_RESET_REQ_N,
+	.gpio_cp_reset = CP_PMU_RST_N,
+	.gpio_pda_active = PDA_ACTIVE,
+	.gpio_phone_active = PHONE_ACTIVE,
+	.gpio_cp_dump_int = CP_DUMP_INT,
+	.gpio_flm_uart_sel = 0,
+	.gpio_cp_warm_reset = 0,
+
+	.modem_type = IMC_XMM6262,
+	.link_types = LINKTYPE(LINKDEV_HSIC) | LINKTYPE(LINKDEV_C2C),
+	.modem_net = UMTS_NETWORK,
+	.use_handover = false,
+
+	.num_iodevs = ARRAY_SIZE(umts_io_devices),
+	.iodevs = umts_io_devices,
+
+	.link_pm_data = &modem_link_pm_data,
+};
+
+/* HSIC specific function */
+void set_host_states(struct platform_device *pdev, int type)
+{
+	if (active_ctl.gpio_initialized) {
+		pr_err(" [MODEM_IF] Active States =%d, %s\n", type, pdev->name);
+		gpio_direction_output(modem_link_pm_data.gpio_link_active,
+			type);
+	} else
+		active_ctl.gpio_request_host_active = 1;
+}
+
+static struct platform_device umts_modem = {
+	.name = "modem_if",
+	.id = -1,
+	.num_resources = ARRAY_SIZE(umts_modem_res),
+	.resource = umts_modem_res,
+	.dev = {
+		.platform_data = &umts_modem_data,
+	},
+};
+
+struct io_list {
+	unsigned num;
+	char *name;
+	unsigned val;
+};
+
+static void umts_modem_cfg_gpio(void)
+{
+	unsigned gpio_reset_req_n = umts_modem_data.gpio_reset_req_n;
+	unsigned gpio_cp_on = umts_modem_data.gpio_cp_on;
+	unsigned gpio_cp_rst = umts_modem_data.gpio_cp_reset;
+	unsigned gpio_pda_active = umts_modem_data.gpio_pda_active;
+	unsigned gpio_phone_active = umts_modem_data.gpio_phone_active;
+
+	if (gpio_reset_req_n) {
+		gpio_request(gpio_reset_req_n, "CP_RST_REQ");
+		gpio_direction_output(gpio_reset_req_n, 0);
+	}
+
+	if (gpio_cp_on) {
+		gpio_request(gpio_cp_on, "CP_ON");
+		gpio_direction_output(gpio_cp_on, 0);
+	}
+
+	if (gpio_cp_rst) {
+		gpio_request(gpio_cp_rst, "CP_RST");
+		gpio_direction_output(gpio_cp_rst, 0);
+	}
+
+	if (gpio_pda_active) {
+		gpio_request(gpio_pda_active, "PDA_ACTIVE");
+		gpio_direction_output(gpio_pda_active, 0);
+	}
+
+	if (gpio_phone_active) {
+		gpio_request(gpio_phone_active, "PHONE_ACTIVE");
+		gpio_direction_input(gpio_phone_active);
+	}
+}
+
+static void modem_link_pm_config_gpio(void)
+{
+	int i, err;
+	unsigned gpio_num;
+	struct io_list gpio_list[] = {
+		{modem_link_pm_data.gpio_link_enable, "hsic_en", 1},
+		{modem_link_pm_data.gpio_link_active, "host_active", 0},
+		{modem_link_pm_data.gpio_link_hostwake, "host_wakeup", 0},
+		{modem_link_pm_data.gpio_link_slavewake, "slave_wakeup", 0},
+	};
+	unsigned gpio_link_hostwake = modem_link_pm_data.gpio_link_hostwake;
+
+	for (i = 0; i < ARRAY_SIZE(gpio_list); i++) {
+		gpio_num = gpio_list[i].num;
+		if (gpio_num) {
+			err = gpio_request(gpio_num, gpio_list[i].name);
+			if (err) {
+				pr_err("request gpio fail %s: %d\n",
+				gpio_list[i].name, err);
+				continue;
+			}
+			gpio_direction_output(gpio_num, gpio_list[i].val);
+			pr_debug("%s gpio cfg done\n", gpio_list[i].name);
+		}
+	}
+
+	if (gpio_link_hostwake)
+		irq_set_irq_type(gpio_to_irq(gpio_link_hostwake),
+			IRQ_TYPE_EDGE_BOTH);
+
+	active_ctl.gpio_initialized = 1;
+	if (active_ctl.gpio_request_host_active) {
+		pr_err(" [MODEM_IF] Active States = 1, %s\n", __func__);
+		gpio_direction_output(modem_link_pm_data.gpio_link_active, 1);
+	}
+
+	printk(KERN_INFO "modem_link_pm_config_gpio done\n");
+}
+
+static int __init init_modem(void)
+{
+	pr_debug("[BOARD] <%s> Invoked!!!\n", __func__);
+
+	umts_modem_cfg_gpio();
+	modem_link_pm_config_gpio();
+	platform_device_register(&umts_modem);
+
+	return 0;
+}
+late_initcall(init_modem);
diff --git a/arch/arm/mach-exynos/board-midas-wlan.c b/arch/arm/mach-exynos/board-midas-wlan.c
new file mode 100755
index 0000000..5d9a584
--- /dev/null
+++ b/arch/arm/mach-exynos/board-midas-wlan.c
@@ -0,0 +1,326 @@
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/skbuff.h>
+#include <linux/wlan_plat.h>
+
+#include <plat/devs.h>
+#include <plat/sdhci.h>
+#include <plat/gpio-cfg.h>
+#include <mach/regs-gpio.h>
+#include <mach/gpio.h>
+
+#ifdef CONFIG_BROADCOM_WIFI_RESERVED_MEM
+
+#define WLAN_STATIC_SCAN_BUF0		5
+#define WLAN_STATIC_SCAN_BUF1		6
+#define PREALLOC_WLAN_SEC_NUM		4
+#define PREALLOC_WLAN_BUF_NUM		160
+#define PREALLOC_WLAN_SECTION_HEADER	24
+
+#define WLAN_SECTION_SIZE_0	(PREALLOC_WLAN_BUF_NUM * 128)
+#define WLAN_SECTION_SIZE_1	(PREALLOC_WLAN_BUF_NUM * 128)
+#define WLAN_SECTION_SIZE_2	(PREALLOC_WLAN_BUF_NUM * 512)
+#define WLAN_SECTION_SIZE_3	(PREALLOC_WLAN_BUF_NUM * 1024)
+
+#define DHD_SKB_HDRSIZE			336
+#define DHD_SKB_1PAGE_BUFSIZE	((PAGE_SIZE*1)-DHD_SKB_HDRSIZE)
+#define DHD_SKB_2PAGE_BUFSIZE	((PAGE_SIZE*2)-DHD_SKB_HDRSIZE)
+#define DHD_SKB_4PAGE_BUFSIZE	((PAGE_SIZE*4)-DHD_SKB_HDRSIZE)
+
+#define WLAN_SKB_BUF_NUM	17
+
+static struct sk_buff *wlan_static_skb[WLAN_SKB_BUF_NUM];
+
+struct wlan_mem_prealloc {
+	void *mem_ptr;
+	unsigned long size;
+};
+
+static struct wlan_mem_prealloc wlan_mem_array[PREALLOC_WLAN_SEC_NUM] = {
+	{NULL, (WLAN_SECTION_SIZE_0 + PREALLOC_WLAN_SECTION_HEADER)},
+	{NULL, (WLAN_SECTION_SIZE_1 + PREALLOC_WLAN_SECTION_HEADER)},
+	{NULL, (WLAN_SECTION_SIZE_2 + PREALLOC_WLAN_SECTION_HEADER)},
+	{NULL, (WLAN_SECTION_SIZE_3 + PREALLOC_WLAN_SECTION_HEADER)}
+};
+
+void *wlan_static_scan_buf0;
+void *wlan_static_scan_buf1;
+static void *brcm_wlan_mem_prealloc(int section, unsigned long size)
+{
+	if (section == PREALLOC_WLAN_SEC_NUM)
+		return wlan_static_skb;
+	if (section == WLAN_STATIC_SCAN_BUF0)
+		return wlan_static_scan_buf0;
+	if (section == WLAN_STATIC_SCAN_BUF1)
+		return wlan_static_scan_buf1;
+	if ((section < 0) || (section > PREALLOC_WLAN_SEC_NUM))
+		return NULL;
+
+	if (wlan_mem_array[section].size < size)
+		return NULL;
+
+	return wlan_mem_array[section].mem_ptr;
+}
+
+static int brcm_init_wlan_mem(void)
+{
+	int i;
+	int j;
+
+	for (i = 0; i < 8; i++) {
+		wlan_static_skb[i] = dev_alloc_skb(DHD_SKB_1PAGE_BUFSIZE);
+		if (!wlan_static_skb[i])
+			goto err_skb_alloc;
+	}
+
+	for (; i < 16; i++) {
+		wlan_static_skb[i] = dev_alloc_skb(DHD_SKB_2PAGE_BUFSIZE);
+		if (!wlan_static_skb[i])
+			goto err_skb_alloc;
+	}
+
+	wlan_static_skb[i] = dev_alloc_skb(DHD_SKB_4PAGE_BUFSIZE);
+	if (!wlan_static_skb[i])
+		goto err_skb_alloc;
+
+	for (i = 0 ; i < PREALLOC_WLAN_SEC_NUM ; i++) {
+		wlan_mem_array[i].mem_ptr =
+				kmalloc(wlan_mem_array[i].size, GFP_KERNEL);
+
+		if (!wlan_mem_array[i].mem_ptr)
+			goto err_mem_alloc;
+	}
+	wlan_static_scan_buf0 = kmalloc (65536, GFP_KERNEL);
+	if(!wlan_static_scan_buf0)
+		goto err_mem_alloc;
+	wlan_static_scan_buf1 = kmalloc (65536, GFP_KERNEL);
+	if(!wlan_static_scan_buf1)
+		goto err_mem_alloc;
+
+	printk("%s: WIFI MEM Allocated\n", __FUNCTION__);
+	return 0;
+
+ err_mem_alloc:
+	pr_err("Failed to mem_alloc for WLAN\n");
+	for (j = 0 ; j < i ; j++)
+		kfree(wlan_mem_array[j].mem_ptr);
+
+	i = WLAN_SKB_BUF_NUM;
+
+ err_skb_alloc:
+	pr_err("Failed to skb_alloc for WLAN\n");
+	for (j = 0 ; j < i ; j++)
+		dev_kfree_skb(wlan_static_skb[j]);
+
+	return -ENOMEM;
+}
+#endif /* CONFIG_BROADCOM_WIFI_RESERVED_MEM */
+
+static unsigned int wlan_on_gpio_table[][4] = {
+        {GPIO_WLAN_EN , GPIO_WLAN_EN_AF, GPIO_LEVEL_HIGH, S3C_GPIO_PULL_NONE},
+        {GPIO_WLAN_HOST_WAKE, GPIO_WLAN_HOST_WAKE_AF, GPIO_LEVEL_NONE, S3C_GPIO_PULL_DOWN},
+};
+
+static unsigned int wlan_off_gpio_table[][4] = {
+        {GPIO_WLAN_EN , GPIO_WLAN_EN_AF, GPIO_LEVEL_LOW, S3C_GPIO_PULL_NONE},
+        {GPIO_WLAN_HOST_WAKE, 0 , GPIO_LEVEL_NONE, S3C_GPIO_PULL_DOWN},
+};
+
+static unsigned int wlan_sdio_on_table[][4] = {
+        {GPIO_WLAN_SDIO_CLK, GPIO_WLAN_SDIO_CLK_AF, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE},
+        {GPIO_WLAN_SDIO_CMD, GPIO_WLAN_SDIO_CMD_AF, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE},
+        {GPIO_WLAN_SDIO_D0, GPIO_WLAN_SDIO_D0_AF, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE},
+        {GPIO_WLAN_SDIO_D1, GPIO_WLAN_SDIO_D1_AF, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE},
+        {GPIO_WLAN_SDIO_D2, GPIO_WLAN_SDIO_D2_AF, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE},
+        {GPIO_WLAN_SDIO_D3, GPIO_WLAN_SDIO_D3_AF, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE},
+};
+
+static unsigned int wlan_sdio_off_table[][4] = {
+        {GPIO_WLAN_SDIO_CLK, 1, GPIO_LEVEL_LOW, S3C_GPIO_PULL_NONE},
+        {GPIO_WLAN_SDIO_CMD, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE},
+        {GPIO_WLAN_SDIO_D0, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE},
+        {GPIO_WLAN_SDIO_D1, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE},
+        {GPIO_WLAN_SDIO_D2, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE},
+        {GPIO_WLAN_SDIO_D3, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE},
+};
+
+static void s3c_config_gpio_alive_table(int array_size, unsigned int (*gpio_table)[4])
+{
+	u32 i, gpio;
+	printk("gpio_table = [%d] \r\n" , array_size);
+	for (i = 0; i < array_size; i++) {
+		gpio = gpio_table[i][0];
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(gpio_table[i][1]));
+		s3c_gpio_setpull(gpio, gpio_table[i][3]);
+		if (gpio_table[i][2] != GPIO_LEVEL_NONE)
+		    gpio_set_value(gpio, gpio_table[i][2]);
+	}
+}
+
+static int brcm_wlan_power(int onoff)
+{
+	printk("------------------------------------------------");
+	printk("------------------------------------------------\n");
+	printk("%s Enter: power %s\n", __FUNCTION__, onoff ? "on" : "off");
+	pr_info("111%s Enter: power %s\n", __FUNCTION__, onoff ? "on" : "off");
+	if (onoff) {
+		s3c_config_gpio_alive_table(ARRAY_SIZE(wlan_on_gpio_table), wlan_on_gpio_table);
+		udelay(200);
+		gpio_set_value(GPIO_WLAN_EN, GPIO_LEVEL_HIGH);
+		printk(KERN_DEBUG "WLAN: GPIO_WLAN_EN = %d \n", gpio_get_value(GPIO_WLAN_EN));
+	} else {
+		gpio_set_value(GPIO_WLAN_EN, GPIO_LEVEL_LOW);
+		s3c_config_gpio_alive_table(ARRAY_SIZE(wlan_off_gpio_table), wlan_off_gpio_table);
+		printk(KERN_DEBUG "WLAN: GPIO_WLAN_EN = %d \n", gpio_get_value(GPIO_WLAN_EN));
+	}
+
+	return 0;
+}
+
+static int brcm_wlan_reset(int onoff)
+{
+	gpio_set_value(GPIO_WLAN_EN,
+			onoff ? GPIO_LEVEL_HIGH : GPIO_LEVEL_LOW);
+	return 0;
+}
+
+static int brcm_wlan_set_carddetect(int onoff)
+{
+	if (onoff)
+		s3c_config_gpio_alive_table(ARRAY_SIZE(wlan_sdio_on_table), wlan_sdio_on_table);
+	else
+		s3c_config_gpio_alive_table(ARRAY_SIZE(wlan_sdio_off_table), wlan_sdio_off_table);
+
+	udelay(200);
+
+	mmc_force_presence_change(&s3c_device_hsmmc3);
+	/* msleep(500);  wait for carddetect */
+	return 0;
+}
+
+/* Customized Locale table : OPTIONAL feature */
+#define WLC_CNTRY_BUF_SZ        4
+typedef struct cntry_locales_custom {
+	char iso_abbrev[WLC_CNTRY_BUF_SZ];
+	char custom_locale[WLC_CNTRY_BUF_SZ];
+	int  custom_locale_rev;
+} cntry_locales_custom_t;
+
+static cntry_locales_custom_t brcm_wlan_translate_custom_table[] = {
+	/* Table should be filled out based on custom platform regulatory requirement */
+	{"",   "XZ", 11},  /* Universal if Country code is unknown or empty */
+	{"AE", "AE", 1},
+	{"AR", "AR", 1},
+	{"AT", "AT", 1},
+	{"AU", "AU", 2},
+	{"BE", "BE", 1},
+	{"BG", "BG", 1},
+	{"BN", "BN", 1},
+	{"CA", "CA", 2},
+	{"CH", "CH", 1},
+	{"CY", "CY", 1},
+	{"CZ", "CZ", 1},
+	{"DE", "DE", 3},
+	{"DK", "DK", 1},
+	{"EE", "EE", 1},
+	{"ES", "ES", 1},
+	{"FI", "FI", 1},
+	{"FR", "FR", 1},
+	{"GB", "GB", 1},
+	{"GR", "GR", 1},
+	{"HR", "HR", 1},
+	{"HU", "HU", 1},
+	{"IE", "IE", 1},
+	{"IS", "IS", 1},
+	{"IT", "IT", 1},
+	{"JP", "JP", 3},
+	{"KR", "KR", 24},
+	{"KW", "KW", 1},
+	{"LI", "LI", 1},
+	{"LT", "LT", 1},
+	{"LU", "LU", 1},
+	{"LV", "LV", 1},
+	{"MA", "MA", 1},
+	{"MT", "MT", 1},
+	{"MX", "MX", 1},
+	{"NL", "NL", 1},
+	{"NO", "NO", 1},
+	{"PL", "PL", 1},
+	{"PT", "PT", 1},
+	{"PY", "PY", 1},
+	{"RO", "RO", 1},
+	{"RU", "RU", 5},
+	{"SE", "SE", 1},
+	{"SG", "SG", 4},
+	{"SI", "SI", 1},
+	{"SK", "SK", 1},
+	{"TR", "TR", 7},
+	{"TW", "TW", 2},
+	{"US", "US", 46}
+};
+
+static void *brcm_wlan_get_country_code(char *ccode)
+{
+	int size = ARRAY_SIZE(brcm_wlan_translate_custom_table);
+	int i;
+
+	if (!ccode)
+		return NULL;
+
+	for (i = 0; i < size; i++)
+		if (strcmp(ccode, brcm_wlan_translate_custom_table[i].iso_abbrev) == 0)
+			return &brcm_wlan_translate_custom_table[i];
+	return &brcm_wlan_translate_custom_table[0];
+}
+
+static struct resource brcm_wlan_resources[] = {
+	[0] = {
+		.name	= "bcmdhd_wlan_irq",
+		.start	= IRQ_EINT(21),
+		.end	= IRQ_EINT(21),
+//chanyun 12.21		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
+		.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL | IORESOURCE_IRQ_SHAREABLE,
+	},
+};
+
+static struct wifi_platform_data brcm_wlan_control = {
+	.set_power	= brcm_wlan_power,
+	.set_reset	= brcm_wlan_reset,
+	.set_carddetect	= brcm_wlan_set_carddetect,
+#ifdef CONFIG_BROADCOM_WIFI_RESERVED_MEM
+	.mem_prealloc	= brcm_wlan_mem_prealloc,
+#endif
+	.get_country_code = brcm_wlan_get_country_code,
+};
+
+static struct platform_device brcm_device_wlan = {
+	.name		= "bcmdhd_wlan",
+	.id		= 1,
+	.num_resources	= ARRAY_SIZE(brcm_wlan_resources),
+	.resource	= brcm_wlan_resources,
+	.dev		= {
+		.platform_data = &brcm_wlan_control,
+	},
+};
+
+int __init brcm_wlan_init(void)
+{
+	int ret;
+	printk("%s: start\n", __FUNCTION__);
+
+#ifdef CONFIG_BROADCOM_WIFI_RESERVED_MEM
+	brcm_init_wlan_mem();
+#endif
+
+	ret =  platform_device_register(&brcm_device_wlan);
+	printk("-----------------------------------------------------\n");
+	printk("-----------------------------------------------------\n");
+	printk("-----------------------------------------------------\n");
+	printk("regist ret:%d\n", ret);
+	return ret;
+
+//	return platform_device_register(&brcm_device_wlan);
+}
diff --git a/arch/arm/mach-exynos/board-mobile.h b/arch/arm/mach-exynos/board-mobile.h
new file mode 100644
index 0000000..54384d0
--- /dev/null
+++ b/arch/arm/mach-exynos/board-mobile.h
@@ -0,0 +1,39 @@
+#ifndef __SAMSUNG_MOBILE_BOARD_COMMON_H
+#define __SAMSUNG_MOBILE_BOARD_COMMON_H
+
+/*
+ * Please add the common mobile external declarations
+ */
+extern void midas_camera_init(void);
+
+/* charger-manager */
+extern struct charger_global_desc midas_charger_g_desc;
+extern struct platform_device midas_charger_manager;
+
+/* MAX77693 */
+extern struct max77693_muic_data max77693_muic;
+extern struct max77693_regulator_data max77693_regulators;
+
+/* i2c-gpio(sw) pin configuration */
+#define GPIO_I2C_PIN_SETUP(_bus)	{	\
+	s3c_gpio_cfgpin(gpio_i2c_##_bus.sda_pin, S3C_GPIO_INPUT);	\
+	s3c_gpio_setpull(gpio_i2c_##_bus.sda_pin, S3C_GPIO_PULL_NONE);	\
+	s3c_gpio_cfgpin(gpio_i2c_##_bus.scl_pin, S3C_GPIO_INPUT);	\
+	s3c_gpio_setpull(gpio_i2c_##_bus.scl_pin, S3C_GPIO_PULL_NONE);	\
+}
+
+#ifdef CONFIG_SLP
+extern int __init midas_nfc_init(int i2c_bus);
+
+/* NTC thermistor */
+extern struct platform_device midas_ncp15wb473_thermistor;
+extern int __init adc_ntc_init(int port);
+#endif
+
+/* wifi */
+extern int brcm_wlan_init(void);
+
+/* gps */
+extern void set_gps_uart_op(int onoff);
+
+#endif
diff --git a/arch/arm/mach-exynos/board-p10-wlan.c b/arch/arm/mach-exynos/board-p10-wlan.c
new file mode 100644
index 0000000..de4b352
--- /dev/null
+++ b/arch/arm/mach-exynos/board-p10-wlan.c
@@ -0,0 +1,333 @@
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/skbuff.h>
+#include <linux/wlan_plat.h>
+
+#include <plat/devs.h>
+#include <plat/sdhci.h>
+#include <plat/gpio-cfg.h>
+#include <mach/regs-gpio.h>
+#include <mach/gpio.h>
+
+#ifdef CONFIG_BROADCOM_WIFI_RESERVED_MEM
+
+#define WLAN_STATIC_SCAN_BUF0		5
+#define WLAN_STATIC_SCAN_BUF1		6
+#define WLAN_SCAN_BUF_SIZE		(64 * 1024)
+#define PREALLOC_WLAN_SEC_NUM		4
+#define PREALLOC_WLAN_BUF_NUM		160
+#define PREALLOC_WLAN_SECTION_HEADER	24
+
+#define WLAN_SECTION_SIZE_0	(PREALLOC_WLAN_BUF_NUM * 128)
+#define WLAN_SECTION_SIZE_1	(PREALLOC_WLAN_BUF_NUM * 128)
+#define WLAN_SECTION_SIZE_2	(PREALLOC_WLAN_BUF_NUM * 512)
+#define WLAN_SECTION_SIZE_3	(PREALLOC_WLAN_BUF_NUM * 1024)
+
+#define DHD_SKB_HDRSIZE			336
+#define DHD_SKB_1PAGE_BUFSIZE	((PAGE_SIZE*1)-DHD_SKB_HDRSIZE)
+#define DHD_SKB_2PAGE_BUFSIZE	((PAGE_SIZE*2)-DHD_SKB_HDRSIZE)
+#define DHD_SKB_4PAGE_BUFSIZE	((PAGE_SIZE*4)-DHD_SKB_HDRSIZE)
+
+#define WLAN_SKB_BUF_NUM	17
+
+static struct sk_buff *wlan_static_skb[WLAN_SKB_BUF_NUM];
+
+struct wlan_mem_prealloc {
+	void *mem_ptr;
+	unsigned long size;
+};
+
+static struct wlan_mem_prealloc wlan_mem_array[PREALLOC_WLAN_SEC_NUM] = {
+	{NULL, (WLAN_SECTION_SIZE_0 + PREALLOC_WLAN_SECTION_HEADER)},
+	{NULL, (WLAN_SECTION_SIZE_1 + PREALLOC_WLAN_SECTION_HEADER)},
+	{NULL, (WLAN_SECTION_SIZE_2 + PREALLOC_WLAN_SECTION_HEADER)},
+	{NULL, (WLAN_SECTION_SIZE_3 + PREALLOC_WLAN_SECTION_HEADER)}
+};
+
+void *wlan_static_scan_buf0;
+void *wlan_static_scan_buf1;
+
+static void *brcm_wlan_mem_prealloc(int section, unsigned long size)
+{
+	if (section == PREALLOC_WLAN_SEC_NUM)
+		return wlan_static_skb;
+
+	if (section == WLAN_STATIC_SCAN_BUF0)
+		return wlan_static_scan_buf0;
+
+	if (section == WLAN_STATIC_SCAN_BUF1)
+		return wlan_static_scan_buf1;
+
+	if ((section < 0) || (section > PREALLOC_WLAN_SEC_NUM))
+		return NULL;
+
+	if (wlan_mem_array[section].size < size)
+		return NULL;
+
+	return wlan_mem_array[section].mem_ptr;
+}
+
+static int brcm_init_wlan_mem(void)
+{
+	int i;
+	int j;
+
+	for (i = 0; i < 8; i++) {
+		wlan_static_skb[i] = dev_alloc_skb(DHD_SKB_1PAGE_BUFSIZE);
+		if (!wlan_static_skb[i])
+			goto err_skb_alloc;
+	}
+
+	for (; i < 16; i++) {
+		wlan_static_skb[i] = dev_alloc_skb(DHD_SKB_2PAGE_BUFSIZE);
+		if (!wlan_static_skb[i])
+			goto err_skb_alloc;
+	}
+
+	wlan_static_skb[i] = dev_alloc_skb(DHD_SKB_4PAGE_BUFSIZE);
+	if (!wlan_static_skb[i])
+		goto err_skb_alloc;
+
+	for (i = 0 ; i < PREALLOC_WLAN_SEC_NUM ; i++) {
+		wlan_mem_array[i].mem_ptr =
+				kmalloc(wlan_mem_array[i].size, GFP_KERNEL);
+
+		if (!wlan_mem_array[i].mem_ptr)
+			goto err_mem_alloc;
+	}
+
+	wlan_static_scan_buf0 = kmalloc (WLAN_SCAN_BUF_SIZE, GFP_KERNEL);
+	if (!wlan_static_scan_buf0)
+		goto err_mem_alloc;
+
+	wlan_static_scan_buf1 = kmalloc (WLAN_SCAN_BUF_SIZE, GFP_KERNEL);
+	if (!wlan_static_scan_buf1)
+		goto err_mem_alloc;
+
+	printk(KERN_INFO"%s: WIFI MEM Allocated\n", __func__);
+	return 0;
+
+ err_mem_alloc:
+	pr_err("Failed to mem_alloc for WLAN\n");
+	for (j = 0 ; j < i ; j++)
+		kfree(wlan_mem_array[j].mem_ptr);
+
+	i = WLAN_SKB_BUF_NUM;
+
+ err_skb_alloc:
+	pr_err("Failed to skb_alloc for WLAN\n");
+	for (j = 0 ; j < i ; j++)
+		dev_kfree_skb(wlan_static_skb[j]);
+
+	return -ENOMEM;
+}
+#endif /* CONFIG_BROADCOM_WIFI_RESERVED_MEM */
+
+static unsigned int wlan_on_gpio_table[][4] = {
+	{GPIO_WLAN_EN , GPIO_WLAN_EN_AF, GPIO_LEVEL_HIGH, S3C_GPIO_PULL_NONE},
+	{GPIO_WLAN_HOST_WAKE, GPIO_WLAN_HOST_WAKE_AF,
+	 GPIO_LEVEL_NONE, S3C_GPIO_PULL_DOWN},
+};
+
+static unsigned int wlan_off_gpio_table[][4] = {
+	{GPIO_WLAN_EN , GPIO_WLAN_EN_AF, GPIO_LEVEL_LOW, S3C_GPIO_PULL_NONE},
+	{GPIO_WLAN_HOST_WAKE, 0 , GPIO_LEVEL_NONE, S3C_GPIO_PULL_DOWN},
+};
+
+static unsigned int wlan_sdio_on_table[][4] = {
+	{GPIO_WLAN_SDIO_CLK, GPIO_WLAN_SDIO_CLK_AF,
+	 GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE},
+	{GPIO_WLAN_SDIO_CMD, GPIO_WLAN_SDIO_CMD_AF,
+	 GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE},
+	{GPIO_WLAN_SDIO_D0, GPIO_WLAN_SDIO_D0_AF,
+	 GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE},
+	{GPIO_WLAN_SDIO_D1, GPIO_WLAN_SDIO_D1_AF,
+	 GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE},
+	{GPIO_WLAN_SDIO_D2, GPIO_WLAN_SDIO_D2_AF,
+	 GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE},
+	{GPIO_WLAN_SDIO_D3, GPIO_WLAN_SDIO_D3_AF,
+	 GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE},
+};
+
+static unsigned int wlan_sdio_off_table[][4] = {
+	{GPIO_WLAN_SDIO_CLK, 1, GPIO_LEVEL_LOW, S3C_GPIO_PULL_NONE},
+	{GPIO_WLAN_SDIO_CMD, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE},
+	{GPIO_WLAN_SDIO_D0, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE},
+	{GPIO_WLAN_SDIO_D1, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE},
+	{GPIO_WLAN_SDIO_D2, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE},
+	{GPIO_WLAN_SDIO_D3, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE},
+};
+
+static void s3c_config_gpio_alive_table
+(int array_size, unsigned int
+(*gpio_table)[4])
+{
+	u32 i, gpio;
+	printk(KERN_INFO"gpio_table = [%d] \r\n" , array_size);
+	for (i = 0; i < array_size; i++) {
+		gpio = gpio_table[i][0];
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(gpio_table[i][1]));
+		s3c_gpio_setpull(gpio, gpio_table[i][3]);
+		if (gpio_table[i][2] != GPIO_LEVEL_NONE)
+			gpio_set_value(gpio, gpio_table[i][2]);
+	}
+}
+
+static int brcm_wlan_power(int onoff)
+{
+	printk(KERN_INFO"------------------------------------------------");
+	printk(KERN_INFO"------------------------------------------------\n");
+	printk(KERN_INFO"%s Enter: power %s\n", __func__, onoff ? "on" : "off");
+	if (onoff) {
+		s3c_config_gpio_alive_table
+		(ARRAY_SIZE(wlan_on_gpio_table), wlan_on_gpio_table);
+		udelay(200);
+		gpio_set_value(GPIO_WLAN_EN, GPIO_LEVEL_HIGH);
+		printk(KERN_DEBUG"WLAN: GPIO_WLAN_EN = %d\n",
+		gpio_get_value(GPIO_WLAN_EN));
+	} else {
+		gpio_set_value(GPIO_WLAN_EN, GPIO_LEVEL_LOW);
+		s3c_config_gpio_alive_table
+		(ARRAY_SIZE(wlan_off_gpio_table), wlan_off_gpio_table);
+		printk(KERN_DEBUG"WLAN: GPIO_WLAN_EN = %d\n",
+		gpio_get_value(GPIO_WLAN_EN));
+	}
+
+	return 0;
+}
+
+static int brcm_wlan_reset(int onoff)
+{
+	gpio_set_value(GPIO_WLAN_EN,
+			onoff ? GPIO_LEVEL_HIGH : GPIO_LEVEL_LOW);
+	return 0;
+}
+
+static int brcm_wlan_set_carddetect(int onoff)
+{
+	if (onoff) {
+		s3c_config_gpio_alive_table(
+ARRAY_SIZE(wlan_sdio_on_table), wlan_sdio_on_table);
+	} else {
+		s3c_config_gpio_alive_table(
+ARRAY_SIZE(wlan_sdio_off_table), wlan_sdio_off_table); }
+
+	udelay(200);
+
+	mmc_force_presence_change(&s3c_device_hsmmc3);
+	msleep(500); /* wait for carddetect */
+	return 0;
+}
+
+/* Customized Locale table : OPTIONAL feature */
+#define WLC_CNTRY_BUF_SZ        4
+struct cntry_locales_custom {
+	char iso_abbrev[WLC_CNTRY_BUF_SZ];
+	char custom_locale[WLC_CNTRY_BUF_SZ];
+	int  custom_locale_rev;
+};
+
+static struct cntry_locales_custom brcm_wlan_translate_custom_table[] = {
+	/* Table should be filled out based
+ on custom platform regulatory requirement */
+	{"",   "XY", 4},  /* universal */
+	{"US", "US", 69}, /* input ISO "US" to : US regrev 69 */
+	{"CA", "US", 69}, /* input ISO "CA" to : US regrev 69 */
+	{"EU", "EU", 5},  /* European union countries */
+	{"AT", "EU", 5},
+	{"BE", "EU", 5},
+	{"BG", "EU", 5},
+	{"CY", "EU", 5},
+	{"CZ", "EU", 5},
+	{"DK", "EU", 5},
+	{"EE", "EU", 5},
+	{"FI", "EU", 5},
+	{"FR", "EU", 5},
+	{"DE", "EU", 5},
+	{"GR", "EU", 5},
+	{"HU", "EU", 5},
+	{"IE", "EU", 5},
+	{"IT", "EU", 5},
+	{"LV", "EU", 5},
+	{"LI", "EU", 5},
+	{"LT", "EU", 5},
+	{"LU", "EU", 5},
+	{"MT", "EU", 5},
+	{"NL", "EU", 5},
+	{"PL", "EU", 5},
+	{"PT", "EU", 5},
+	{"RO", "EU", 5},
+	{"SK", "EU", 5},
+	{"SI", "EU", 5},
+	{"ES", "EU", 5},
+	{"SE", "EU", 5},
+	{"GB", "EU", 5},  /* input ISO "GB" to : EU regrev 05 */
+	{"IL", "IL", 0},
+	{"CH", "CH", 0},
+	{"TR", "TR", 0},
+	{"NO", "NO", 0},
+	{"KR", "XY", 3},
+	{"AU", "XY", 3},
+	{"CN", "XY", 3},  /* input ISO "CN" to : XY regrev 03 */
+	{"TW", "XY", 3},
+	{"AR", "XY", 3},
+	{"MX", "XY", 3}
+};
+
+static void *brcm_wlan_get_country_code(char *ccode)
+{
+	int size = ARRAY_SIZE(brcm_wlan_translate_custom_table);
+	int i;
+
+	if (!ccode)
+		return NULL;
+
+	for (i = 0; i < size; i++)
+		if (strcmp(ccode,
+		brcm_wlan_translate_custom_table[i].iso_abbrev) == 0)
+			return &brcm_wlan_translate_custom_table[i];
+	return &brcm_wlan_translate_custom_table[0];
+}
+
+static struct resource brcm_wlan_resources[] = {
+	[0] = {
+		.name	= "bcmdhd_wlan_irq",
+		.start	= IRQ_EINT(21),
+		.end	= IRQ_EINT(21),
+		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL | IORESOURCE_IRQ_SHAREABLE,
+	},
+};
+
+static struct wifi_platform_data brcm_wlan_control = {
+	.set_power	= brcm_wlan_power,
+	.set_reset	= brcm_wlan_reset,
+	.set_carddetect	= brcm_wlan_set_carddetect,
+#ifdef CONFIG_BROADCOM_WIFI_RESERVED_MEM
+	.mem_prealloc	= brcm_wlan_mem_prealloc,
+#endif
+	.get_country_code = brcm_wlan_get_country_code,
+};
+
+static struct platform_device brcm_device_wlan = {
+	.name		= "bcmdhd_wlan",
+	.id		= 1,
+	.num_resources	= ARRAY_SIZE(brcm_wlan_resources),
+	.resource	= brcm_wlan_resources,
+	.dev		= {
+		.platform_data = &brcm_wlan_control,
+	},
+};
+
+int __init brcm_wlan_init(void)
+{
+	printk(KERN_INFO"%s: start\n", __func__);
+
+#ifdef CONFIG_BROADCOM_WIFI_RESERVED_MEM
+	brcm_init_wlan_mem();
+#endif
+
+	return platform_device_register(&brcm_device_wlan);
+}
diff --git a/arch/arm/mach-exynos/board-p4notepq-modems.c b/arch/arm/mach-exynos/board-p4notepq-modems.c
new file mode 100644
index 0000000..3ab6fbe
--- /dev/null
+++ b/arch/arm/mach-exynos/board-p4notepq-modems.c
@@ -0,0 +1,535 @@
+/* linux/arch/arm/mach-xxxx/board-m0-modems.c
+ * Copyright (C) 2010 Samsung Electronics. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* Modem configuraiton for M0 (P-Q + XMM6262)*/
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/gpio.h>
+#include <mach/gpio-exynos4.h>
+#include <plat/gpio-cfg.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+
+#include <linux/platform_data/modem.h>
+#include <mach/sec_modem.h>
+
+extern int s3c_gpio_slp_cfgpin(unsigned int pin, unsigned int config);
+/* umts target platform data */
+static struct modem_io_t umts_io_devices[] = {
+	[0] = {
+		.name = "umts_ipc0",
+		.id = 0x1,
+		.format = IPC_FMT,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[1] = {
+		.name = "umts_rfs0",
+		.id = 0x41,
+		.format = IPC_RFS,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[2] = {
+		.name = "umts_boot0",
+		.id = 0x0,
+		.format = IPC_BOOT,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[3] = {
+		.name = "multipdp",
+		.id = 0x1,
+		.format = IPC_MULTI_RAW,
+		.io_type = IODEV_DUMMY,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[4] = {
+#ifdef CONFIG_SLP
+		.name = "pdp0",
+#else
+		.name = "rmnet0",
+#endif
+		.id = 0x2A,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[5] = {
+#ifdef CONFIG_SLP
+		.name = "pdp1",
+#else
+		.name = "rmnet1",
+#endif
+		.id = 0x2B,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[6] = {
+#ifdef CONFIG_SLP
+		.name = "pdp2",
+#else
+		.name = "rmnet2",
+#endif
+		.id = 0x2C,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[7] = {
+		.name = "umts_router",
+		.id = 0x39,
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[8] = {
+		.name = "umts_csd",
+		.id = 0x21,
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[9] = {
+		.name = "umts_ramdump0",
+		.id = 0x0,
+		.format = IPC_RAMDUMP,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[10] = {
+		.name = "umts_loopback0",
+		.id = 0x3f,
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+};
+
+/* To get modem state, register phone active irq using resource */
+static struct resource umts_modem_res[] = {
+};
+
+static int umts_link_ldo_enble(bool enable)
+{
+	/* Exynos HSIC V1.2 LDO was controlled by kernel */
+	return 0;
+}
+
+static int umts_link_reconnect(void);
+static struct modemlink_pm_data modem_link_pm_data = {
+	.name = "link_pm",
+	.link_ldo_enable = umts_link_ldo_enble,
+	.gpio_link_enable = 0,
+	.gpio_link_active = GPIO_ACTIVE_STATE,
+	.gpio_link_hostwake = GPIO_IPC_HOST_WAKEUP,
+	.gpio_link_slavewake = GPIO_IPC_SLAVE_WAKEUP,
+	.link_reconnect = umts_link_reconnect,
+};
+
+static struct modemlink_pm_link_activectl active_ctl;
+
+static void xmm_gpio_revers_bias_clear(void);
+static void xmm_gpio_revers_bias_restore(void);
+
+#ifndef GPIO_AP_DUMP_INT
+#define GPIO_AP_DUMP_INT 0
+#endif
+static struct modem_data umts_modem_data = {
+	.name = "xmm6262",
+
+	.gpio_cp_on = GPIO_PHONE_ON,
+	.gpio_reset_req_n = GPIO_CP_REQ_RESET,
+	.gpio_cp_reset = GPIO_CP_RST,
+	.gpio_pda_active = GPIO_PDA_ACTIVE,
+	.gpio_phone_active = GPIO_PHONE_ACTIVE,
+	.gpio_cp_dump_int = GPIO_CP_DUMP_INT,
+	.gpio_ap_dump_int = GPIO_AP_DUMP_INT,
+	.gpio_flm_uart_sel = 0,
+	.gpio_cp_warm_reset = 0,
+#if defined(CONFIG_SIM_DETECT)
+	.gpio_sim_detect = GPIO_SIM_DETECT,
+#endif
+
+	.modem_type = IMC_XMM6262,
+	.link_types = LINKTYPE(LINKDEV_HSIC),
+	.modem_net = UMTS_NETWORK,
+	.use_handover = false,
+
+	.num_iodevs = ARRAY_SIZE(umts_io_devices),
+	.iodevs = umts_io_devices,
+
+	.link_pm_data = &modem_link_pm_data,
+	.gpio_revers_bias_clear = xmm_gpio_revers_bias_clear,
+	.gpio_revers_bias_restore = xmm_gpio_revers_bias_restore,
+};
+
+/* HSIC specific function */
+void set_slave_wake(void)
+{
+	if (gpio_get_value(modem_link_pm_data.gpio_link_hostwake)) {
+		pr_info("[MODEM_IF]Slave Wake\n");
+		if (gpio_get_value(modem_link_pm_data.gpio_link_slavewake)) {
+			pr_info("[MODEM_IF]Slave Wake set _-\n");
+			gpio_direction_output(
+			modem_link_pm_data.gpio_link_slavewake, 0);
+			mdelay(10);
+		}
+		gpio_direction_output(
+			modem_link_pm_data.gpio_link_slavewake, 1);
+	}
+}
+
+void set_host_states(struct platform_device *pdev, int type)
+{
+	int val = gpio_get_value(umts_modem_data.gpio_cp_reset);
+
+	if (!val) {
+		pr_info("CP not ready, Active State low\n");
+		return;
+	}
+
+	if (active_ctl.gpio_initialized) {
+		pr_err(LOG_TAG "Active States =%d, %s\n", type, pdev->name);
+		gpio_direction_output(modem_link_pm_data.gpio_link_active,
+			type);
+	} else
+		active_ctl.gpio_request_host_active = 1;
+}
+
+void set_hsic_lpa_states(int states)
+{
+	int val = gpio_get_value(umts_modem_data.gpio_cp_reset);
+
+	mif_trace("\n");
+
+	if (val) {
+		switch (states) {
+		case STATE_HSIC_LPA_ENTER:
+			gpio_set_value(modem_link_pm_data.gpio_link_active, 0);
+			gpio_set_value(umts_modem_data.gpio_pda_active, 0);
+			pr_info(LOG_TAG "set hsic lpa enter: "
+				"active state (%d)" ", pda active (%d)\n",
+				gpio_get_value(
+					modem_link_pm_data.gpio_link_active),
+				gpio_get_value(umts_modem_data.gpio_pda_active)
+				);
+			break;
+		case STATE_HSIC_LPA_WAKE:
+			gpio_set_value(umts_modem_data.gpio_pda_active, 1);
+			pr_info(LOG_TAG "set hsic lpa wake: "
+				"pda active (%d)\n",
+				gpio_get_value(umts_modem_data.gpio_pda_active)
+				);
+			break;
+		case STATE_HSIC_LPA_PHY_INIT:
+			gpio_set_value(umts_modem_data.gpio_pda_active, 1);
+			set_slave_wake();
+			pr_info(LOG_TAG "set hsic lpa phy init: "
+				"slave wake-up (%d)\n",
+				gpio_get_value(
+					modem_link_pm_data.gpio_link_slavewake)
+				);
+			break;
+		}
+	}
+}
+
+int get_cp_active_state(void)
+{
+	return gpio_get_value(umts_modem_data.gpio_phone_active);
+}
+
+static int umts_link_reconnect(void)
+{
+	if (gpio_get_value(umts_modem_data.gpio_phone_active) &&
+		gpio_get_value(umts_modem_data.gpio_cp_reset)) {
+		pr_info("[MODEM_IF] trying reconnect link\n");
+		gpio_set_value(modem_link_pm_data.gpio_link_active, 0);
+		mdelay(10);
+		set_slave_wake();
+		gpio_set_value(modem_link_pm_data.gpio_link_active, 1);
+	} else
+		return -ENODEV;
+
+	return 0;
+}
+
+/* if use more than one modem device, then set id num */
+static struct platform_device umts_modem = {
+	.name = "modem_if",
+	.id = -1,
+	.num_resources = ARRAY_SIZE(umts_modem_res),
+	.resource = umts_modem_res,
+	.dev = {
+		.platform_data = &umts_modem_data,
+	},
+};
+
+static void umts_modem_cfg_gpio(void)
+{
+	int err = 0;
+
+	unsigned gpio_reset_req_n = umts_modem_data.gpio_reset_req_n;
+	unsigned gpio_cp_on = umts_modem_data.gpio_cp_on;
+	unsigned gpio_cp_rst = umts_modem_data.gpio_cp_reset;
+	unsigned gpio_pda_active = umts_modem_data.gpio_pda_active;
+	unsigned gpio_phone_active = umts_modem_data.gpio_phone_active;
+	unsigned gpio_cp_dump_int = umts_modem_data.gpio_cp_dump_int;
+	unsigned gpio_ap_dump_int = umts_modem_data.gpio_ap_dump_int;
+	unsigned gpio_flm_uart_sel = umts_modem_data.gpio_flm_uart_sel;
+	unsigned gpio_sim_detect = umts_modem_data.gpio_sim_detect;
+	unsigned irq_phone_active = umts_modem_res[0].start;
+
+	if (gpio_reset_req_n) {
+		err = gpio_request(gpio_reset_req_n, "RESET_REQ_N");
+		if (err) {
+			pr_err(LOG_TAG "fail to request gpio %s : %d\n",
+			"RESET_REQ_N", err);
+		}
+		s3c_gpio_slp_cfgpin(gpio_reset_req_n, S3C_GPIO_SLP_OUT1);
+		gpio_direction_output(gpio_reset_req_n, 0);
+	}
+
+	if (gpio_cp_on) {
+		err = gpio_request(gpio_cp_on, "CP_ON");
+		if (err) {
+			pr_err(LOG_TAG "fail to request gpio %s : %d\n",
+			       "CP_ON", err);
+		}
+		gpio_direction_output(gpio_cp_on, 0);
+	}
+
+	if (gpio_cp_rst) {
+		err = gpio_request(gpio_cp_rst, "CP_RST");
+		if (err) {
+			pr_err(LOG_TAG "fail to request gpio %s : %d\n",
+			       "CP_RST", err);
+		}
+		s3c_gpio_slp_cfgpin(gpio_cp_rst, S3C_GPIO_SLP_OUT1);
+		gpio_direction_output(gpio_cp_rst, 0);
+	}
+
+	if (gpio_pda_active) {
+		err = gpio_request(gpio_pda_active, "PDA_ACTIVE");
+		if (err) {
+			pr_err(LOG_TAG "fail to request gpio %s : %d\n",
+			       "PDA_ACTIVE", err);
+		}
+		gpio_direction_output(gpio_pda_active, 0);
+	}
+
+	if (gpio_phone_active) {
+		err = gpio_request(gpio_phone_active, "PHONE_ACTIVE");
+		if (err) {
+			pr_err(LOG_TAG "fail to request gpio %s : %d\n",
+			       "PHONE_ACTIVE", err);
+		}
+		gpio_direction_input(gpio_phone_active);
+		pr_err(LOG_TAG "check phone active = %d\n", irq_phone_active);
+	}
+
+	if (gpio_sim_detect) {
+		err = gpio_request(gpio_sim_detect, "SIM_DETECT");
+		if (err)
+			printk(KERN_ERR "fail to request gpio %s: %d\n",
+				"SIM_DETECT", err);
+
+		/* gpio_direction_input(gpio_sim_detect); */
+		s3c_gpio_cfgpin(gpio_sim_detect, S3C_GPIO_SFN(0xF));
+		s3c_gpio_setpull(gpio_sim_detect, S3C_GPIO_PULL_NONE);
+		irq_set_irq_type(gpio_to_irq(gpio_sim_detect),
+							IRQ_TYPE_EDGE_BOTH);
+	}
+
+	if (gpio_cp_dump_int) {
+		err = gpio_request(gpio_cp_dump_int, "CP_DUMP_INT");
+		if (err) {
+			pr_err(LOG_TAG "fail to request gpio %s : %d\n",
+			       "CP_DUMP_INT", err);
+		}
+		gpio_direction_input(gpio_cp_dump_int);
+	}
+
+	if (gpio_ap_dump_int) {
+		err = gpio_request(gpio_ap_dump_int, "AP_DUMP_INT");
+		if (err) {
+			pr_err(LOG_TAG "fail to request gpio %s : %d\n",
+			       "AP_DUMP_INT", err);
+		}
+		gpio_direction_output(gpio_ap_dump_int, 0);
+	}
+
+	if (gpio_flm_uart_sel) {
+		err = gpio_request(gpio_flm_uart_sel, "GPS_UART_SEL");
+		if (err) {
+			pr_err(LOG_TAG "fail to request gpio %s : %d\n",
+			       "GPS_UART_SEL", err);
+		}
+		gpio_direction_output(gpio_reset_req_n, 0);
+	}
+
+	if (gpio_phone_active)
+		irq_set_irq_type(gpio_to_irq(gpio_phone_active),
+							IRQ_TYPE_LEVEL_HIGH);
+	/* set low unused gpios between AP and CP */
+	err = gpio_request(GPIO_FLM_RXD, "FLM_RXD");
+	if (err)
+		pr_err(LOG_TAG "fail to request gpio %s : %d\n", "FLM_RXD",
+		err);
+	else {
+		gpio_direction_output(GPIO_FLM_RXD, 0);
+		s3c_gpio_setpull(GPIO_FLM_RXD, S3C_GPIO_PULL_NONE);
+	}
+	err = gpio_request(GPIO_FLM_TXD, "FLM_TXD");
+	if (err)
+		pr_err(LOG_TAG "fail to request gpio %s : %d\n", "FLM_TXD",
+		err);
+	else {
+		gpio_direction_output(GPIO_FLM_TXD, 0);
+		s3c_gpio_setpull(GPIO_FLM_TXD, S3C_GPIO_PULL_NONE);
+	}
+	err = gpio_request(GPIO_SUSPEND_REQUEST, "SUS_REQ");
+	if (err)
+		pr_err(LOG_TAG "fail to request gpio %s : %d\n", "SUS_REQ",
+		err);
+	else {
+		gpio_direction_output(GPIO_SUSPEND_REQUEST, 0);
+		s3c_gpio_setpull(GPIO_SUSPEND_REQUEST, S3C_GPIO_PULL_NONE);
+	}
+	err = gpio_request(GPIO_GPS_CNTL, "GPS_CNTL");
+	if (err)
+		pr_err(LOG_TAG "fail to request gpio %s : %d\n", "GPS_CNTL",
+		err);
+	else {
+		gpio_direction_output(GPIO_GPS_CNTL, 0);
+		s3c_gpio_setpull(GPIO_GPS_CNTL, S3C_GPIO_PULL_NONE);
+	}
+
+	pr_info(LOG_TAG "umts_modem_cfg_gpio done\n");
+}
+
+static void xmm_gpio_revers_bias_clear(void)
+{
+	gpio_direction_output(umts_modem_data.gpio_pda_active, 0);
+	gpio_direction_output(umts_modem_data.gpio_phone_active, 0);
+	gpio_direction_output(umts_modem_data.gpio_cp_dump_int, 0);
+	gpio_direction_output(modem_link_pm_data.gpio_link_active, 0);
+	gpio_direction_output(modem_link_pm_data.gpio_link_hostwake, 0);
+	gpio_direction_output(modem_link_pm_data.gpio_link_slavewake, 0);
+
+	if (umts_modem_data.gpio_sim_detect)
+		gpio_direction_output(umts_modem_data.gpio_sim_detect, 0);
+
+	msleep(20);
+}
+
+static void xmm_gpio_revers_bias_restore(void)
+{
+	unsigned gpio_sim_detect = umts_modem_data.gpio_sim_detect;
+
+	s3c_gpio_cfgpin(umts_modem_data.gpio_phone_active, S3C_GPIO_SFN(0xF));
+	s3c_gpio_cfgpin(modem_link_pm_data.gpio_link_hostwake,
+		S3C_GPIO_SFN(0xF));
+	gpio_direction_input(umts_modem_data.gpio_cp_dump_int);
+
+	if (umts_modem_data.gpio_sim_detect) {
+		gpio_direction_input(gpio_sim_detect);
+		s3c_gpio_cfgpin(gpio_sim_detect, S3C_GPIO_SFN(0xF));
+		s3c_gpio_setpull(gpio_sim_detect, S3C_GPIO_PULL_NONE);
+		irq_set_irq_type(gpio_to_irq(gpio_sim_detect),
+				IRQ_TYPE_EDGE_BOTH);
+		enable_irq_wake(gpio_to_irq(gpio_sim_detect));
+	}
+}
+
+static void modem_link_pm_config_gpio(void)
+{
+	int err = 0;
+
+	unsigned gpio_link_enable = modem_link_pm_data.gpio_link_enable;
+	unsigned gpio_link_active = modem_link_pm_data.gpio_link_active;
+	unsigned gpio_link_hostwake = modem_link_pm_data.gpio_link_hostwake;
+	unsigned gpio_link_slavewake = modem_link_pm_data.gpio_link_slavewake;
+	/* unsigned irq_link_hostwake = umts_modem_res[1].start; */
+
+	if (gpio_link_enable) {
+		err = gpio_request(gpio_link_enable, "LINK_EN");
+		if (err) {
+			pr_err(LOG_TAG "fail to request gpio %s : %d\n",
+			       "LINK_EN", err);
+		}
+		gpio_direction_output(gpio_link_enable, 0);
+	}
+
+	if (gpio_link_active) {
+		err = gpio_request(gpio_link_active, "LINK_ACTIVE");
+		if (err) {
+			pr_err(LOG_TAG "fail to request gpio %s : %d\n",
+			       "LINK_ACTIVE", err);
+		}
+		gpio_direction_output(gpio_link_active, 0);
+	}
+
+	if (gpio_link_hostwake) {
+		err = gpio_request(gpio_link_hostwake, "HOSTWAKE");
+		if (err) {
+			pr_err(LOG_TAG "fail to request gpio %s : %d\n",
+			       "HOSTWAKE", err);
+		}
+		gpio_direction_input(gpio_link_hostwake);
+	}
+
+	if (gpio_link_slavewake) {
+		err = gpio_request(gpio_link_slavewake, "SLAVEWAKE");
+		if (err) {
+			pr_err(LOG_TAG "fail to request gpio %s : %d\n",
+			       "SLAVEWAKE", err);
+		}
+		gpio_direction_output(gpio_link_slavewake, 0);
+	}
+
+	if (gpio_link_hostwake)
+		irq_set_irq_type(gpio_to_irq(gpio_link_hostwake),
+							IRQ_TYPE_EDGE_BOTH);
+
+	active_ctl.gpio_initialized = 1;
+	if (active_ctl.gpio_request_host_active) {
+		pr_err(LOG_TAG "Active States = 1, %s\n", __func__);
+		gpio_direction_output(modem_link_pm_data.gpio_link_active, 1);
+	}
+
+	pr_info(LOG_TAG "modem_link_pm_config_gpio done\n");
+}
+
+static int __init init_modem(void)
+{
+	int ret;
+	pr_info(LOG_TAG "init_modem, system_rev = %d\n", system_rev);
+
+	/* umts gpios configuration */
+	umts_modem_cfg_gpio();
+	modem_link_pm_config_gpio();
+	ret = platform_device_register(&umts_modem);
+	if (ret < 0)
+		return ret;
+
+	return ret;
+}
+late_initcall(init_modem);
diff --git a/arch/arm/mach-exynos/board-s2plus-modems.c b/arch/arm/mach-exynos/board-s2plus-modems.c
new file mode 100644
index 0000000..38ee0b2
--- /dev/null
+++ b/arch/arm/mach-exynos/board-s2plus-modems.c
@@ -0,0 +1,479 @@
+/* linux/arch/arm/mach-xxxx/board-m0-modems.c
+ * Copyright (C) 2010 Samsung Electronics. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* Modem configuraiton for M0 (P-Q + XMM6262)*/
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+#include <mach/gpio-exynos4.h>
+#include <plat/gpio-cfg.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+
+#include <linux/platform_data/modem.h>
+#include <mach/sec_modem.h>
+
+extern int s3c_gpio_slp_cfgpin(unsigned int pin, unsigned int config);
+/* umts target platform data */
+static struct modem_io_t umts_io_devices[] = {
+	[0] = {
+		.name = "umts_ipc0",
+		.id = 0x1,
+		.format = IPC_FMT,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[1] = {
+		.name = "umts_rfs0",
+		.id = 0x41,
+		.format = IPC_RFS,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[2] = {
+		.name = "umts_boot0",
+		.id = 0x0,
+		.format = IPC_BOOT,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[3] = {
+		.name = "multipdp",
+		.id = 0x1,
+		.format = IPC_MULTI_RAW,
+		.io_type = IODEV_DUMMY,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[4] = {
+		.name = "rmnet0",
+		.id = 0x2A,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[5] = {
+		.name = "rmnet1",
+		.id = 0x2B,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[6] = {
+		.name = "rmnet2",
+		.id = 0x2C,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[7] = {
+		.name = "umts_router",
+		.id = 0x39,
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[8] = {
+		.name = "umts_csd",
+		.id = 0x21,
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[9] = {
+		.name = "umts_ramdump0",
+		.id = 0x0,
+		.format = IPC_RAMDUMP,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[10] = {
+		.name = "umts_loopback0",
+		.id = 0x3f,
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+};
+
+/* To get modem state, register phone active irq using resource */
+static struct resource umts_modem_res[] = {
+};
+
+static int umts_link_ldo_enble(bool enable)
+{
+	/* Exynos HSIC V1.2 LDO was controlled by kernel */
+	return 0;
+}
+
+static int umts_link_reconnect(void);
+static struct modemlink_pm_data modem_link_pm_data = {
+	.name = "link_pm",
+	.link_ldo_enable = umts_link_ldo_enble,
+	.gpio_link_enable = 0,
+	.gpio_link_active = GPIO_ACTIVE_STATE,
+	.gpio_link_hostwake = GPIO_IPC_HOST_WAKEUP,
+	.gpio_link_slavewake = GPIO_IPC_SLAVE_WAKEUP,
+	.link_reconnect = umts_link_reconnect,
+};
+
+static struct modemlink_pm_link_activectl active_ctl;
+
+static void xmm_gpio_revers_bias_clear(void);
+static void xmm_gpio_revers_bias_restore(void);
+static struct modem_data umts_modem_data = {
+	.name = "xmm6262",
+
+	.gpio_cp_on = GPIO_PHONE_ON,
+	.gpio_reset_req_n = GPIO_CP_REQ_RESET,
+	.gpio_cp_reset = GPIO_CP_RST,
+	.gpio_pda_active = GPIO_PDA_ACTIVE,
+	.gpio_phone_active = GPIO_PHONE_ACTIVE,
+	.gpio_cp_dump_int = GPIO_CP_DUMP_INT,
+	.gpio_flm_uart_sel = 0,
+	.gpio_cp_warm_reset = 0,
+
+	.modem_type = IMC_XMM6262,
+	.link_types = LINKTYPE(LINKDEV_HSIC),
+	.modem_net = UMTS_NETWORK,
+	.use_handover = false,
+
+	.num_iodevs = ARRAY_SIZE(umts_io_devices),
+	.iodevs = umts_io_devices,
+
+	.link_pm_data = &modem_link_pm_data,
+	.gpio_revers_bias_clear = xmm_gpio_revers_bias_clear,
+	.gpio_revers_bias_restore = xmm_gpio_revers_bias_restore,
+};
+
+/* HSIC specific function */
+void set_slave_wake(void)
+{
+	int spin = 20;
+	if (gpio_get_value(modem_link_pm_data.gpio_link_hostwake)) {
+		pr_info("[MODEM_IF]Slave Wake\n");
+		if (gpio_get_value(modem_link_pm_data.gpio_link_slavewake)) {
+			gpio_direction_output(
+			modem_link_pm_data.gpio_link_slavewake, 0);
+			mdelay(10);
+		}
+		gpio_direction_output(
+			modem_link_pm_data.gpio_link_slavewake, 1);
+		mdelay(10);
+		while (spin--) {
+			if (!gpio_get_value(
+				modem_link_pm_data.gpio_link_hostwake))
+				break;
+			mdelay(10);
+		}
+	}
+}
+
+void set_host_states(struct platform_device *pdev, int type)
+{
+	if (active_ctl.gpio_initialized) {
+		if (type)
+			set_slave_wake();
+		pr_err(LOG_TAG "Active States =%d, %s\n", type, pdev->name);
+		gpio_direction_output(modem_link_pm_data.gpio_link_active,
+			type);
+	} else
+		active_ctl.gpio_request_host_active = 1;
+}
+
+void set_hsic_lpa_states(int states)
+{
+	int val = gpio_get_value(umts_modem_data.gpio_cp_reset);
+
+	mif_trace("\n");
+
+	if (val) {
+		switch (states) {
+		case STATE_HSIC_LPA_ENTER:
+			gpio_set_value(modem_link_pm_data.gpio_link_active, 0);
+			gpio_set_value(umts_modem_data.gpio_pda_active, 0);
+			pr_info(LOG_TAG "set hsic lpa enter: "
+				"active state (%d)" ", pda active (%d)\n",
+				gpio_get_value(
+					modem_link_pm_data.gpio_link_active),
+				gpio_get_value(umts_modem_data.gpio_pda_active)
+				);
+			break;
+		case STATE_HSIC_LPA_WAKE:
+			gpio_set_value(umts_modem_data.gpio_pda_active, 1);
+			pr_info(LOG_TAG "set hsic lpa wake: "
+				"pda active (%d)\n",
+				gpio_get_value(umts_modem_data.gpio_pda_active)
+				);
+			break;
+		case STATE_HSIC_LPA_PHY_INIT:
+			gpio_set_value(umts_modem_data.gpio_pda_active, 1);
+			gpio_set_value(modem_link_pm_data.gpio_link_slavewake,
+				1);
+			pr_info(LOG_TAG "set hsic lpa phy init: "
+				"slave wake-up (%d)\n",
+				gpio_get_value(
+					modem_link_pm_data.gpio_link_slavewake)
+				);
+			break;
+		}
+	}
+}
+
+int get_cp_active_state(void)
+{
+	return gpio_get_value(umts_modem_data.gpio_phone_active);
+}
+
+static int umts_link_reconnect(void)
+{
+	if (gpio_get_value(umts_modem_data.gpio_phone_active) &&
+		gpio_get_value(umts_modem_data.gpio_cp_reset)) {
+		pr_info("[MODEM_IF] trying reconnect link\n");
+		gpio_set_value(modem_link_pm_data.gpio_link_active, 0);
+		mdelay(10);
+		set_slave_wake();
+		gpio_set_value(modem_link_pm_data.gpio_link_active, 1);
+	} else
+		return -ENODEV;
+
+	return 0;
+}
+
+/* if use more than one modem device, then set id num */
+static struct platform_device umts_modem = {
+	.name = "modem_if",
+	.id = -1,
+	.num_resources = ARRAY_SIZE(umts_modem_res),
+	.resource = umts_modem_res,
+	.dev = {
+		.platform_data = &umts_modem_data,
+	},
+};
+
+static void umts_modem_cfg_gpio(void)
+{
+	int err = 0;
+
+	unsigned gpio_reset_req_n = umts_modem_data.gpio_reset_req_n;
+	unsigned gpio_cp_on = umts_modem_data.gpio_cp_on;
+	unsigned gpio_cp_rst = umts_modem_data.gpio_cp_reset;
+	unsigned gpio_pda_active = umts_modem_data.gpio_pda_active;
+	unsigned gpio_phone_active = umts_modem_data.gpio_phone_active;
+	unsigned gpio_cp_dump_int = umts_modem_data.gpio_cp_dump_int;
+	unsigned gpio_flm_uart_sel = umts_modem_data.gpio_flm_uart_sel;
+	unsigned irq_phone_active = umts_modem_res[0].start;
+
+	if (gpio_reset_req_n) {
+		err = gpio_request(gpio_reset_req_n, "RESET_REQ_N");
+		if (err) {
+			pr_err(LOG_TAG "fail to request gpio %s : %d\n",
+			"RESET_REQ_N", err);
+		}
+		s3c_gpio_slp_cfgpin(gpio_reset_req_n, S3C_GPIO_SLP_OUT1);
+		gpio_direction_output(gpio_reset_req_n, 0);
+	}
+
+	if (gpio_cp_on) {
+		err = gpio_request(gpio_cp_on, "CP_ON");
+		if (err) {
+			pr_err(LOG_TAG "fail to request gpio %s : %d\n",
+			       "CP_ON", err);
+		}
+		gpio_direction_output(gpio_cp_on, 0);
+	}
+
+	if (gpio_cp_rst) {
+		err = gpio_request(gpio_cp_rst, "CP_RST");
+		if (err) {
+			pr_err(LOG_TAG "fail to request gpio %s : %d\n",
+			       "CP_RST", err);
+		}
+		s3c_gpio_slp_cfgpin(gpio_cp_rst, S3C_GPIO_SLP_OUT1);
+		gpio_direction_output(gpio_cp_rst, 0);
+	}
+
+	if (gpio_pda_active) {
+		err = gpio_request(gpio_pda_active, "PDA_ACTIVE");
+		if (err) {
+			pr_err(LOG_TAG "fail to request gpio %s : %d\n",
+			       "PDA_ACTIVE", err);
+		}
+		gpio_direction_output(gpio_pda_active, 0);
+	}
+
+	if (gpio_phone_active) {
+		err = gpio_request(gpio_phone_active, "PHONE_ACTIVE");
+		if (err) {
+			pr_err(LOG_TAG "fail to request gpio %s : %d\n",
+			       "PHONE_ACTIVE", err);
+		}
+		gpio_direction_input(gpio_phone_active);
+		pr_err(LOG_TAG "check phone active = %d\n", irq_phone_active);
+	}
+
+	if (gpio_cp_dump_int) {
+		err = gpio_request(gpio_cp_dump_int, "CP_DUMP_INT");
+		if (err) {
+			pr_err(LOG_TAG "fail to request gpio %s : %d\n",
+			       "CP_DUMP_INT", err);
+		}
+		gpio_direction_input(gpio_cp_dump_int);
+	}
+
+	if (gpio_flm_uart_sel) {
+		err = gpio_request(gpio_flm_uart_sel, "GPS_UART_SEL");
+		if (err) {
+			pr_err(LOG_TAG "fail to request gpio %s : %d\n",
+			       "GPS_UART_SEL", err);
+		}
+		gpio_direction_output(gpio_reset_req_n, 0);
+	}
+
+	if (gpio_phone_active)
+		irq_set_irq_type(gpio_to_irq(gpio_phone_active),
+							IRQ_TYPE_LEVEL_HIGH);
+	/* set low unused gpios between AP and CP */
+	err = gpio_request(GPIO_FLM_RXD, "FLM_RXD");
+	if (err)
+		pr_err(LOG_TAG "fail to request gpio %s : %d\n", "FLM_RXD",
+		err);
+	else {
+		gpio_direction_output(GPIO_FLM_RXD, 0);
+		s3c_gpio_setpull(GPIO_FLM_RXD, S3C_GPIO_PULL_NONE);
+	}
+	err = gpio_request(GPIO_FLM_TXD, "FLM_TXD");
+	if (err)
+		pr_err(LOG_TAG "fail to request gpio %s : %d\n", "FLM_TXD",
+		err);
+	else {
+		gpio_direction_output(GPIO_FLM_TXD, 0);
+		s3c_gpio_setpull(GPIO_FLM_TXD, S3C_GPIO_PULL_NONE);
+	}
+	err = gpio_request(GPIO_SUSPEND_REQUEST, "SUS_REQ");
+	if (err)
+		pr_err(LOG_TAG "fail to request gpio %s : %d\n", "SUS_REQ",
+		err);
+	else {
+		gpio_direction_output(GPIO_SUSPEND_REQUEST, 0);
+		s3c_gpio_setpull(GPIO_SUSPEND_REQUEST, S3C_GPIO_PULL_NONE);
+	}
+	err = gpio_request(GPIO_GPS_CNTL, "GPS_CNTL");
+	if (err)
+		pr_err(LOG_TAG "fail to request gpio %s : %d\n", "GPS_CNTL",
+		err);
+	else {
+		gpio_direction_output(GPIO_GPS_CNTL, 0);
+		s3c_gpio_setpull(GPIO_GPS_CNTL, S3C_GPIO_PULL_NONE);
+	}
+
+	pr_info(LOG_TAG "umts_modem_cfg_gpio done\n");
+}
+
+static void xmm_gpio_revers_bias_clear(void)
+{
+	gpio_direction_output(umts_modem_data.gpio_pda_active, 0);
+	gpio_direction_output(umts_modem_data.gpio_phone_active, 0);
+	gpio_direction_output(umts_modem_data.gpio_cp_dump_int, 0);
+	gpio_direction_output(modem_link_pm_data.gpio_link_active, 0);
+	gpio_direction_output(modem_link_pm_data.gpio_link_hostwake, 0);
+	gpio_direction_output(modem_link_pm_data.gpio_link_slavewake, 0);
+
+	msleep(20);
+}
+
+static void xmm_gpio_revers_bias_restore(void)
+{
+	s3c_gpio_cfgpin(umts_modem_data.gpio_phone_active, S3C_GPIO_SFN(0xF));
+	s3c_gpio_cfgpin(modem_link_pm_data.gpio_link_hostwake,
+		S3C_GPIO_SFN(0xF));
+	gpio_direction_input(umts_modem_data.gpio_cp_dump_int);
+}
+
+static void modem_link_pm_config_gpio(void)
+{
+	int err = 0;
+
+	unsigned gpio_link_enable = modem_link_pm_data.gpio_link_enable;
+	unsigned gpio_link_active = modem_link_pm_data.gpio_link_active;
+	unsigned gpio_link_hostwake = modem_link_pm_data.gpio_link_hostwake;
+	unsigned gpio_link_slavewake = modem_link_pm_data.gpio_link_slavewake;
+	/* unsigned irq_link_hostwake = umts_modem_res[1].start; */
+
+	if (gpio_link_enable) {
+		err = gpio_request(gpio_link_enable, "LINK_EN");
+		if (err) {
+			pr_err(LOG_TAG "fail to request gpio %s : %d\n",
+			       "LINK_EN", err);
+		}
+		gpio_direction_output(gpio_link_enable, 0);
+	}
+
+	if (gpio_link_active) {
+		err = gpio_request(gpio_link_active, "LINK_ACTIVE");
+		if (err) {
+			pr_err(LOG_TAG "fail to request gpio %s : %d\n",
+			       "LINK_ACTIVE", err);
+		}
+		gpio_direction_output(gpio_link_active, 0);
+	}
+
+	if (gpio_link_hostwake) {
+		err = gpio_request(gpio_link_hostwake, "HOSTWAKE");
+		if (err) {
+			pr_err(LOG_TAG "fail to request gpio %s : %d\n",
+			       "HOSTWAKE", err);
+		}
+		gpio_direction_input(gpio_link_hostwake);
+	}
+
+	if (gpio_link_slavewake) {
+		err = gpio_request(gpio_link_slavewake, "SLAVEWAKE");
+		if (err) {
+			pr_err(LOG_TAG "fail to request gpio %s : %d\n",
+			       "SLAVEWAKE", err);
+		}
+		gpio_direction_output(gpio_link_slavewake, 0);
+	}
+
+	if (gpio_link_hostwake)
+		irq_set_irq_type(gpio_to_irq(gpio_link_hostwake),
+							IRQ_TYPE_EDGE_BOTH);
+
+	active_ctl.gpio_initialized = 1;
+	if (active_ctl.gpio_request_host_active) {
+		pr_err(LOG_TAG "Active States = 1, %s\n", __func__);
+		gpio_direction_output(modem_link_pm_data.gpio_link_active, 1);
+	}
+
+	pr_info(LOG_TAG "modem_link_pm_config_gpio done\n");
+}
+
+static int __init init_modem(void)
+{
+	int ret;
+	pr_info(LOG_TAG "init_modem\n");
+
+	/* umts gpios configuration */
+	umts_modem_cfg_gpio();
+	modem_link_pm_config_gpio();
+	ret = platform_device_register(&umts_modem);
+	if (ret < 0)
+		return ret;
+
+	return ret;
+}
+late_initcall(init_modem);
diff --git a/arch/arm/mach-exynos/board-smdk5250-audio.c b/arch/arm/mach-exynos/board-smdk5250-audio.c
new file mode 100644
index 0000000..6cd1405
--- /dev/null
+++ b/arch/arm/mach-exynos/board-smdk5250-audio.c
@@ -0,0 +1,177 @@
+/* linux/arch/arm/mach-exynos/board-smdk5250-audio.c
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+#include <linux/mfd/wm8994/pdata.h>
+
+#include <plat/gpio-cfg.h>
+#include <plat/devs.h>
+#include <plat/iic.h>
+
+#include "board-smdk5250.h"
+
+static struct regulator_consumer_supply wm8994_fixed_voltage0_supplies[] = {
+	REGULATOR_SUPPLY("AVDD2", "1-001a"),
+	REGULATOR_SUPPLY("CPVDD", "1-001a"),
+};
+
+static struct regulator_consumer_supply wm8994_fixed_voltage1_supplies[] = {
+	REGULATOR_SUPPLY("SPKVDD1", "1-001a"),
+	REGULATOR_SUPPLY("SPKVDD2", "1-001a"),
+};
+
+static struct regulator_consumer_supply wm8994_fixed_voltage2_supplies =
+	REGULATOR_SUPPLY("DBVDD", "1-001a");
+
+static struct regulator_init_data wm8994_fixed_voltage0_init_data = {
+	.constraints = {
+		.always_on = 1,
+	},
+	.num_consumer_supplies	= ARRAY_SIZE(wm8994_fixed_voltage0_supplies),
+	.consumer_supplies	= wm8994_fixed_voltage0_supplies,
+};
+
+static struct regulator_init_data wm8994_fixed_voltage1_init_data = {
+	.constraints = {
+		.always_on = 1,
+	},
+	.num_consumer_supplies	= ARRAY_SIZE(wm8994_fixed_voltage1_supplies),
+	.consumer_supplies	= wm8994_fixed_voltage1_supplies,
+};
+
+static struct regulator_init_data wm8994_fixed_voltage2_init_data = {
+	.constraints = {
+		.always_on = 1,
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &wm8994_fixed_voltage2_supplies,
+};
+
+static struct fixed_voltage_config wm8994_fixed_voltage0_config = {
+	.supply_name	= "VDD_1.8V",
+	.microvolts	= 1800000,
+	.gpio		= -EINVAL,
+	.init_data	= &wm8994_fixed_voltage0_init_data,
+};
+
+static struct fixed_voltage_config wm8994_fixed_voltage1_config = {
+	.supply_name	= "DC_5V",
+	.microvolts	= 5000000,
+	.gpio		= -EINVAL,
+	.init_data	= &wm8994_fixed_voltage1_init_data,
+};
+
+static struct fixed_voltage_config wm8994_fixed_voltage2_config = {
+	.supply_name	= "VDD_3.3V",
+	.microvolts	= 3300000,
+	.gpio		= -EINVAL,
+	.init_data	= &wm8994_fixed_voltage2_init_data,
+};
+
+static struct platform_device wm8994_fixed_voltage0 = {
+	.name		= "reg-fixed-voltage",
+	.id		= 0,
+	.dev		= {
+		.platform_data	= &wm8994_fixed_voltage0_config,
+	},
+};
+
+static struct platform_device wm8994_fixed_voltage1 = {
+	.name		= "reg-fixed-voltage",
+	.id		= 1,
+	.dev		= {
+		.platform_data	= &wm8994_fixed_voltage1_config,
+	},
+};
+
+static struct platform_device wm8994_fixed_voltage2 = {
+	.name		= "reg-fixed-voltage",
+	.id		= 2,
+	.dev		= {
+		.platform_data	= &wm8994_fixed_voltage2_config,
+	},
+};
+
+static struct regulator_consumer_supply wm8994_avdd1_supply =
+	REGULATOR_SUPPLY("AVDD1", "1-001a");
+
+static struct regulator_consumer_supply wm8994_dcvdd_supply =
+	REGULATOR_SUPPLY("DCVDD", "1-001a");
+
+static struct regulator_init_data wm8994_ldo1_data = {
+	.constraints	= {
+		.name		= "AVDD1",
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &wm8994_avdd1_supply,
+};
+
+static struct regulator_init_data wm8994_ldo2_data = {
+	.constraints	= {
+		.name		= "DCVDD",
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &wm8994_dcvdd_supply,
+};
+
+static struct wm8994_pdata wm8994_platform_data = {
+	/* configure gpio1 function: 0x0001(Logic level input/output) */
+	.gpio_defaults[0] = 0x0001,
+	/* If the i2s0 and i2s2 is enabled simultaneously */
+	.gpio_defaults[7] = 0x8100, /* GPIO8  DACDAT3 in */
+	.gpio_defaults[8] = 0x0100, /* GPIO9  ADCDAT3 out */
+	.gpio_defaults[9] = 0x0100, /* GPIO10 LRCLK3  out */
+	.gpio_defaults[10] = 0x0100,/* GPIO11 BCLK3   out */
+	.ldo[0] = { 0, NULL, &wm8994_ldo1_data },
+	.ldo[1] = { 0, NULL, &wm8994_ldo2_data },
+};
+
+static struct i2c_board_info i2c_devs1[] __initdata = {
+	{
+		I2C_BOARD_INFO("wm8994", 0x1a),
+		.platform_data	= &wm8994_platform_data,
+	},
+};
+
+static struct platform_device *smdk5250_audio_devices[] __initdata = {
+	&s3c_device_i2c1,
+#ifdef CONFIG_SND_SAMSUNG_AC97
+	&exynos_device_ac97,
+#endif
+#ifdef CONFIG_SND_SAMSUNG_I2S
+	&exynos_device_i2s0,
+#endif
+#ifdef CONFIG_SND_SAMSUNG_PCM
+	&exynos_device_pcm0,
+#endif
+#ifdef CONFIG_SND_SAMSUNG_SPDIF
+	&exynos_device_spdif,
+#endif
+#if defined(CONFIG_SND_SAMSUNG_RP) || defined(CONFIG_SND_SAMSUNG_ALP)
+	&exynos_device_srp,
+#endif
+	&wm8994_fixed_voltage0,
+	&wm8994_fixed_voltage1,
+	&wm8994_fixed_voltage2,
+	&samsung_asoc_dma,
+	&samsung_asoc_idma,
+};
+
+void __init exynos5_smdk5250_audio_init(void)
+{
+	s3c_i2c1_set_platdata(NULL);
+	i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
+
+	platform_add_devices(smdk5250_audio_devices,
+			ARRAY_SIZE(smdk5250_audio_devices));
+}
diff --git a/arch/arm/mach-exynos/board-smdk5250-display.c b/arch/arm/mach-exynos/board-smdk5250-display.c
new file mode 100644
index 0000000..d247805
--- /dev/null
+++ b/arch/arm/mach-exynos/board-smdk5250-display.c
@@ -0,0 +1,695 @@
+/* linux/arch/arm/mach-exynos/board-smdk5250-display.c
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/gpio.h>
+#include <linux/pwm_backlight.h>
+#include <linux/fb.h>
+#include <linux/delay.h>
+
+#include <video/platform_lcd.h>
+#include <video/s5p-dp.h>
+
+#include <plat/cpu.h>
+#include <plat/clock.h>
+#include <plat/devs.h>
+#include <plat/fb.h>
+#include <plat/fb-s5p.h>
+#include <plat/fb-core.h>
+#include <plat/regs-fb-v4.h>
+#include <plat/dp.h>
+#include <plat/pd.h>
+#include <plat/backlight.h>
+
+#include <mach/map.h>
+#include <mach/dev.h>
+
+#ifdef CONFIG_FB_MIPI_DSIM
+#include <plat/dsim.h>
+#include <plat/mipi_dsi.h>
+#endif
+
+#if defined(CONFIG_LCD_MIPI_S6E8AB0)
+static void mipi_lcd_set_power(struct plat_lcd_data *pd,
+				unsigned int power)
+{
+	if (samsung_rev() >= EXYNOS5250_REV_1_0) {
+		if (!gpio_request(EXYNOS5_GPD1(5), "GPD1")) {
+			s3c_gpio_cfgpin(EXYNOS5_GPD1(5), S3C_GPIO_SFN(1));
+			gpio_direction_output(EXYNOS5_GPD1(5), 0);
+			gpio_direction_output(EXYNOS5_GPD1(5), 1);
+			gpio_free(EXYNOS5_GPD1(5));
+		}
+	}
+	/* reset */
+	gpio_request_one(EXYNOS5_GPX1(5), GPIOF_OUT_INIT_HIGH, "GPX1");
+
+	msleep(20);
+	if (power) {
+		/* fire nRESET on power up */
+		gpio_set_value(EXYNOS5_GPX1(5), 0);
+		msleep(20);
+		gpio_set_value(EXYNOS5_GPX1(5), 1);
+		msleep(20);
+		gpio_free(EXYNOS5_GPX1(5));
+	} else {
+		/* fire nRESET on power off */
+		gpio_set_value(EXYNOS5_GPX1(5), 0);
+		msleep(20);
+		gpio_set_value(EXYNOS5_GPX1(5), 1);
+		msleep(20);
+		gpio_free(EXYNOS5_GPX1(5));
+	}
+	msleep(20);
+	/* power */
+	gpio_request_one(EXYNOS5_GPX3(0), GPIOF_OUT_INIT_LOW, "GPX3");
+	if (power) {
+		/* fire nRESET on power up */
+		gpio_set_value(EXYNOS5_GPX3(0), 1);
+		gpio_free(EXYNOS5_GPX3(0));
+	} else {
+		/* fire nRESET on power off */
+		gpio_set_value(EXYNOS5_GPX3(0), 0);
+		gpio_free(EXYNOS5_GPX3(0));
+	}
+
+#ifndef CONFIG_BACKLIGHT_PWM
+	/* backlight */
+	gpio_request_one(EXYNOS5_GPB2(0), GPIOF_OUT_INIT_LOW, "GPB2");
+	if (power) {
+		/* fire nRESET on power up */
+		gpio_set_value(EXYNOS5_GPB2(0), 1);
+		gpio_free(EXYNOS5_GPB2(0));
+	} else {
+		/* fire nRESET on power off */
+		gpio_set_value(EXYNOS5_GPB2(0), 0);
+		gpio_free(EXYNOS5_GPB2(0));
+	}
+#endif /* CONFIG_BACKLIGHT_PWM */
+}
+
+static struct plat_lcd_data smdk5250_mipi_lcd_data = {
+	.set_power	= mipi_lcd_set_power,
+};
+
+static struct platform_device smdk5250_mipi_lcd = {
+	.name			= "platform-lcd",
+	.dev.platform_data	= &smdk5250_mipi_lcd_data,
+};
+
+static struct s3c_fb_pd_win smdk5250_fb_win0 = {
+	.win_mode = {
+		.left_margin	= 0x4,
+		.right_margin	= 0x4,
+		.upper_margin	= 4,
+		.lower_margin	= 4,
+		.hsync_len	= 4,
+		.vsync_len	= 4,
+		.xres		= 1280,
+		.yres		= 800,
+	},
+	.virtual_x		= 1280,
+	.virtual_y		= 840 * 2,
+	.width			= 223,
+	.height			= 125,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+};
+
+static struct s3c_fb_pd_win smdk5250_fb_win1 = {
+	.win_mode = {
+		.left_margin	= 0x2,
+		.right_margin	= 0x4,
+		.upper_margin	= 4,
+		.lower_margin	= 4,
+		.hsync_len	= 4,
+		.vsync_len	= 4,
+		.xres		= 1280,
+		.yres		= 800,
+	},
+	.virtual_x		= 1280,
+	.virtual_y		= 840 * 2,
+	.width			= 223,
+	.height			= 125,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+};
+
+static struct s3c_fb_pd_win smdk5250_fb_win2 = {
+	.win_mode = {
+		.left_margin	= 0x4,
+		.right_margin	= 0x4,
+		.upper_margin	= 4,
+		.lower_margin	= 4,
+		.hsync_len	= 4,
+		.vsync_len	= 4,
+		.xres		= 1280,
+		.yres		= 800,
+	},
+	.virtual_x		= 1280,
+	.virtual_y		= 800 * 2,
+	.width			= 223,
+	.height			= 125,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+};
+#elif defined(CONFIG_LCD_MIPI_TC358764)
+static void mipi_lcd_set_power(struct plat_lcd_data *pd,
+				unsigned int power)
+{
+	/* reset */
+	gpio_request_one(EXYNOS5_GPX1(5), GPIOF_OUT_INIT_HIGH, "GPX1");
+
+	msleep(20);
+	if (power) {
+		/* fire nRESET on power up */
+		gpio_set_value(EXYNOS5_GPX1(5), 0);
+		msleep(20);
+		gpio_set_value(EXYNOS5_GPX1(5), 1);
+		msleep(20);
+		gpio_free(EXYNOS5_GPX1(5));
+	} else {
+		/* fire nRESET on power off */
+		gpio_set_value(EXYNOS5_GPX1(5), 0);
+		msleep(20);
+		gpio_set_value(EXYNOS5_GPX1(5), 1);
+		msleep(20);
+		gpio_free(EXYNOS5_GPX1(5));
+	}
+	msleep(20);
+	/* power */
+	gpio_request_one(EXYNOS5_GPX3(0), GPIOF_OUT_INIT_LOW, "GPX3");
+	if (power) {
+		/* fire nRESET on power up */
+		gpio_set_value(EXYNOS5_GPX3(0), 1);
+		gpio_free(EXYNOS5_GPX3(0));
+	} else {
+		/* fire nRESET on power off */
+		gpio_set_value(EXYNOS5_GPX3(0), 0);
+		gpio_free(EXYNOS5_GPX3(0));
+	}
+
+#ifndef CONFIG_BACKLIGHT_PWM
+	/* backlight */
+	gpio_request_one(EXYNOS5_GPB2(0), GPIOF_OUT_INIT_LOW, "GPB2");
+	if (power) {
+		/* fire nRESET on power up */
+		gpio_set_value(EXYNOS5_GPB2(0), 1);
+		gpio_free(EXYNOS5_GPB2(0));
+	} else {
+		/* fire nRESET on power off */
+		gpio_set_value(EXYNOS5_GPB2(0), 0);
+		gpio_free(EXYNOS5_GPB2(0));
+	}
+#endif
+}
+
+static struct plat_lcd_data smdk5250_mipi_lcd_data = {
+	.set_power	= mipi_lcd_set_power,
+};
+
+static struct platform_device smdk5250_mipi_lcd = {
+	.name			= "platform-lcd",
+	.dev.platform_data	= &smdk5250_mipi_lcd_data,
+};
+
+static struct s3c_fb_pd_win smdk5250_fb_win0 = {
+	.win_mode = {
+		.left_margin	= 4,
+		.right_margin	= 4,
+		.upper_margin	= 4,
+		.lower_margin	= 4,
+		.hsync_len	= 4,
+		.vsync_len	= 4,
+		.xres		= 1280,
+		.yres		= 800,
+	},
+	.virtual_x		= 1280,
+	.virtual_y		= 840 * 2,
+	.width			= 223,
+	.height			= 125,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+};
+
+static struct s3c_fb_pd_win smdk5250_fb_win1 = {
+	.win_mode = {
+		.left_margin	= 4,
+		.right_margin	= 4,
+		.upper_margin	= 4,
+		.lower_margin	= 4,
+		.hsync_len	= 4,
+		.vsync_len	= 4,
+		.xres		= 1280,
+		.yres		= 800,
+	},
+	.virtual_x		= 1280,
+	.virtual_y		= 840 * 2,
+	.width			= 223,
+	.height			= 125,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+};
+
+static struct s3c_fb_pd_win smdk5250_fb_win2 = {
+	.win_mode = {
+		.left_margin	= 4,
+		.right_margin	= 4,
+		.upper_margin	= 4,
+		.lower_margin	= 4,
+		.hsync_len	= 4,
+		.vsync_len	= 4,
+		.xres		= 1280,
+		.yres		= 800,
+	},
+	.virtual_x		= 1280,
+	.virtual_y		= 800 * 2,
+	.width			= 223,
+	.height			= 125,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+};
+#elif defined(CONFIG_S5P_DP)
+static void dp_lcd_set_power(struct plat_lcd_data *pd,
+				unsigned int power)
+{
+#ifndef CONFIG_BACKLIGHT_PWM
+	/* LCD_PWM_IN_2.8V: LCD_B_PWM, GPB2_0 */
+	gpio_request(EXYNOS5_GPB2(0), "GPB2");
+#endif
+	/* LCD_APS_EN_2.8V: GPD0_6 */
+	gpio_request(EXYNOS5_GPD0(6), "GPD0");
+
+	/* LCD_EN: GPD0_5 */
+	gpio_request(EXYNOS5_GPD0(5), "GPD0");
+
+	/* LCD_EN: GPD0_5 */
+	gpio_direction_output(EXYNOS5_GPD0(5), power);
+	msleep(20);
+
+	/* LCD_APS_EN_2.8V: GPD0_6 */
+	gpio_direction_output(EXYNOS5_GPD0(6), power);
+	msleep(20);
+#ifndef CONFIG_BACKLIGHT_PWM
+	/* LCD_PWM_IN_2.8V: LCD_B_PWM, GPB2_0 */
+	gpio_direction_output(EXYNOS5_GPB2(0), power);
+
+	gpio_free(EXYNOS5_GPB2(0));
+#endif
+	gpio_free(EXYNOS5_GPD0(6));
+	gpio_free(EXYNOS5_GPD0(5));
+}
+
+static struct plat_lcd_data smdk5250_dp_lcd_data = {
+	.set_power	= dp_lcd_set_power,
+};
+
+static struct platform_device smdk5250_dp_lcd = {
+	.name	= "platform-lcd",
+	.dev	= {
+		.parent		= &s5p_device_fimd1.dev,
+		.platform_data	= &smdk5250_dp_lcd_data,
+	},
+};
+
+static struct s3c_fb_pd_win smdk5250_fb_win0 = {
+	.win_mode = {
+		.left_margin	= 80,
+		.right_margin	= 48,
+		.upper_margin	= 37,
+		.lower_margin	= 3,
+		.hsync_len	= 32,
+		.vsync_len	= 6,
+		.xres		= 2560,
+		.yres		= 1600,
+	},
+	.virtual_x		= 2560,
+	.virtual_y		= 1640 * 2,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+};
+
+static struct s3c_fb_pd_win smdk5250_fb_win1 = {
+	.win_mode = {
+		.left_margin	= 80,
+		.right_margin	= 48,
+		.upper_margin	= 37,
+		.lower_margin	= 3,
+		.hsync_len	= 32,
+		.vsync_len	= 6,
+		.xres		= 2560,
+		.yres		= 1600,
+	},
+	.virtual_x		= 2560,
+	.virtual_y		= 1640 * 2,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+};
+
+static struct s3c_fb_pd_win smdk5250_fb_win2 = {
+	.win_mode = {
+		.left_margin	= 80,
+		.right_margin	= 48,
+		.upper_margin	= 37,
+		.lower_margin	= 3,
+		.hsync_len	= 32,
+		.vsync_len	= 6,
+		.xres		= 2560,
+		.yres		= 1600,
+	},
+	.virtual_x		= 2560,
+	.virtual_y		= 1600 * 2,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+};
+#endif
+
+static void exynos_fimd_gpio_setup_24bpp(void)
+{
+	unsigned int reg = 0;
+
+#if defined(CONFIG_S5P_DP)
+	/* Set Hotplug detect for DP */
+	gpio_request(EXYNOS5_GPX0(7), "GPX0");
+	s3c_gpio_cfgpin(EXYNOS5_GPX0(7), S3C_GPIO_SFN(3));
+#endif
+
+	/*
+	 * Set DISP1BLK_CFG register for Display path selection
+	 *
+	 * FIMD of DISP1_BLK Bypass selection : DISP1BLK_CFG[15]
+	 * ---------------------
+	 *  0 | MIE/MDNIE
+	 *  1 | FIMD : selected
+	 */
+	reg = __raw_readl(S3C_VA_SYS + 0x0214);
+	reg &= ~(1 << 15);	/* To save other reset values */
+	reg |= (1 << 15);
+	__raw_writel(reg, S3C_VA_SYS + 0x0214);
+
+#if defined(CONFIG_S5P_DP)
+	/* Reference clcok selection for DPTX_PHY: PAD_OSC_IN */
+	reg = __raw_readl(S3C_VA_SYS + 0x04d4);
+	reg &= ~(1 << 0);
+	__raw_writel(reg, S3C_VA_SYS + 0x04d4);
+
+	/* DPTX_PHY: XXTI */
+	reg = __raw_readl(S3C_VA_SYS + 0x04d8);
+	reg &= ~(1 << 3);
+	__raw_writel(reg, S3C_VA_SYS + 0x04d8);
+#endif
+}
+
+static struct s3c_fb_platdata smdk5250_lcd1_pdata __initdata = {
+#if defined(CONFIG_LCD_MIPI_S6E8AB0) || defined(CONFIG_LCD_MIPI_TC358764) || \
+	defined(CONFIG_S5P_DP)
+	.win[0]		= &smdk5250_fb_win0,
+	.win[1]		= &smdk5250_fb_win1,
+	.win[2]		= &smdk5250_fb_win2,
+#endif
+	.default_win	= 2,
+	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+#if defined(CONFIG_LCD_MIPI_S6E8AB0) || defined(CONFIG_LCD_MIPI_TC358764)
+	.vidcon1	= VIDCON1_INV_VCLK,
+#elif defined(CONFIG_S5P_DP)
+	.vidcon1	= 0,
+#endif
+	.setup_gpio	= exynos_fimd_gpio_setup_24bpp,
+};
+
+#ifdef CONFIG_FB_MIPI_DSIM
+#if defined(CONFIG_LCD_MIPI_S6E8AB0)
+static struct mipi_dsim_config dsim_info = {
+	.e_interface	= DSIM_VIDEO,
+	.e_pixel_format	= DSIM_24BPP_888,
+	/* main frame fifo auto flush at VSYNC pulse */
+	.auto_flush	= false,
+	.eot_disable	= false,
+	.auto_vertical_cnt = true,
+	.hse = false,
+	.hfp = false,
+	.hbp = false,
+	.hsa = false,
+
+	.e_no_data_lane	= DSIM_DATA_LANE_4,
+	.e_byte_clk	= DSIM_PLL_OUT_DIV8,
+	.e_burst_mode	= DSIM_BURST,
+
+	.p = 2,
+	.m = 57,
+	.s = 1,
+
+	/* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */
+	.pll_stable_time = 500,
+
+	.esc_clk = 20 * 1000000,	/* escape clk : 10MHz */
+
+	/* stop state holding counter after bta change count 0 ~ 0xfff */
+	.stop_holding_cnt = 0x0fff,
+	.bta_timeout = 0xff,		/* bta timeout 0 ~ 0xff */
+	.rx_timeout = 0xffff,		/* lp rx timeout 0 ~ 0xffff */
+
+	.dsim_ddi_pd = &s6e8ab0_mipi_lcd_driver,
+};
+
+static struct mipi_dsim_lcd_config dsim_lcd_info = {
+	.rgb_timing.left_margin		= 0xa,
+	.rgb_timing.right_margin	= 0xa,
+	.rgb_timing.upper_margin	= 80,
+	.rgb_timing.lower_margin	= 48,
+	.rgb_timing.hsync_len		= 5,
+	.rgb_timing.vsync_len		= 32,
+	.cpu_timing.cs_setup		= 0,
+	.cpu_timing.wr_setup		= 1,
+	.cpu_timing.wr_act		= 0,
+	.cpu_timing.wr_hold		= 0,
+	.lcd_size.width			= 1280,
+	.lcd_size.height		= 800,
+};
+#elif defined(CONFIG_LCD_MIPI_S6E63M0)
+static struct mipi_dsim_config dsim_info = {
+	.e_interface	= DSIM_VIDEO,
+	.e_pixel_format	= DSIM_24BPP_888,
+	/* main frame fifo auto flush at VSYNC pulse */
+	.auto_flush	= false,
+	.eot_disable	= false,
+	.auto_vertical_cnt = true,
+	.hse = false,
+	.hfp = false,
+	.hbp = false,
+	.hsa = false,
+
+	.e_no_data_lane = DSIM_DATA_LANE_2,
+	.e_byte_clk = DSIM_PLL_OUT_DIV8,
+	.e_burst_mode = DSIM_NON_BURST_SYNC_PULSE,
+
+	.p = 3,
+	.m = 90,
+	.s = 1,
+
+	/* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */
+	.pll_stable_time = 500,
+
+	.esc_clk = 10 * 1000000,		/* escape clk : 10MHz */
+
+	/* stop state holding counter after bta change count 0 ~ 0xfff */
+	.stop_holding_cnt	= 0x0fff,
+	.bta_timeout		= 0xff,		/* bta timeout 0 ~ 0xff */
+	.rx_timeout		= 0xffff,	/* lp rx timeout 0 ~ 0xffff */
+
+	.dsim_ddi_pd = &s6e63m0_mipi_lcd_driver,
+};
+
+static struct mipi_dsim_lcd_config dsim_lcd_info = {
+	.rgb_timing.left_margin		= 0x16,
+	.rgb_timing.right_margin	= 0x16,
+	.rgb_timing.upper_margin	= 0x28,
+	.rgb_timing.lower_margin	= 0x1,
+	.rgb_timing.hsync_len		= 0x2,
+	.rgb_timing.vsync_len		= 0x3,
+	.cpu_timing.cs_setup		= 0,
+	.cpu_timing.wr_setup		= 1,
+	.cpu_timing.wr_act		= 0,
+	.cpu_timing.wr_hold		= 0,
+	.lcd_size.width			= 480,
+	.lcd_size.height		= 800,
+};
+#elif defined(CONFIG_LCD_MIPI_TC358764)
+static struct mipi_dsim_config dsim_info = {
+	.e_interface	= DSIM_VIDEO,
+	.e_pixel_format	= DSIM_24BPP_888,
+	/* main frame fifo auto flush at VSYNC pulse */
+	.auto_flush	= false,
+	.eot_disable	= false,
+	.auto_vertical_cnt = false,
+	.hse = false,
+	.hfp = false,
+	.hbp = false,
+	.hsa = false,
+
+	.e_no_data_lane	= DSIM_DATA_LANE_4,
+	.e_byte_clk	= DSIM_PLL_OUT_DIV8,
+	.e_burst_mode	= DSIM_BURST,
+
+	.p = 3,
+	.m = 115,
+	.s = 1,
+
+	/* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */
+	.pll_stable_time = 500,
+
+	.esc_clk = 0.4 * 1000000,		/* escape clk : 10MHz */
+
+	/* stop state holding counter after bta change count 0 ~ 0xfff */
+	.stop_holding_cnt	= 0x0f,
+	.bta_timeout		= 0xff,		/* bta timeout 0 ~ 0xff */
+	.rx_timeout		= 0xffff,	/* lp rx timeout 0 ~ 0xffff */
+
+	.dsim_ddi_pd = &tc358764_mipi_lcd_driver,
+};
+
+static struct mipi_dsim_lcd_config dsim_lcd_info = {
+	.rgb_timing.left_margin		= 0x4,
+	.rgb_timing.right_margin	= 0x4,
+	.rgb_timing.upper_margin	= 0x4,
+	.rgb_timing.lower_margin	= 0x4,
+	.rgb_timing.hsync_len		= 0x4,
+	.rgb_timing.vsync_len		= 0x4,
+	.cpu_timing.cs_setup		= 0,
+	.cpu_timing.wr_setup		= 1,
+	.cpu_timing.wr_act		= 0,
+	.cpu_timing.wr_hold		= 0,
+	.lcd_size.width			= 1280,
+	.lcd_size.height		= 800,
+};
+#endif
+
+static struct s5p_platform_mipi_dsim dsim_platform_data = {
+	.clk_name		= "dsim0",
+	.dsim_config		= &dsim_info,
+	.dsim_lcd_config	= &dsim_lcd_info,
+
+	.part_reset		= s5p_dsim_part_reset,
+	.init_d_phy		= s5p_dsim_init_d_phy,
+	.get_fb_frame_done	= NULL,
+	.trigger		= NULL,
+
+	/*
+	 * the stable time of needing to write data on SFR
+	 * when the mipi mode becomes LP mode.
+	 */
+	.delay_for_stabilization = 600,
+};
+#endif
+
+#ifdef CONFIG_S5P_DP
+static struct video_info smdk5250_dp_config = {
+	.name			= "WQXGA(2560x1600) LCD, for SMDK TEST",
+
+	.h_sync_polarity	= 0,
+	.v_sync_polarity	= 0,
+	.interlaced		= 0,
+
+	.color_space		= COLOR_RGB,
+	.dynamic_range		= VESA,
+	.ycbcr_coeff		= COLOR_YCBCR601,
+	.color_depth		= COLOR_8,
+
+	.link_rate		= LINK_RATE_2_70GBPS,
+	.lane_count		= LANE_COUNT4,
+};
+
+static void s5p_dp_backlight_on(void)
+{
+	/* LED_BACKLIGHT_RESET: GPX1_5 */
+	gpio_request(EXYNOS5_GPX1(5), "GPX1");
+
+	gpio_direction_output(EXYNOS5_GPX1(5), 1);
+	msleep(20);
+
+	gpio_free(EXYNOS5_GPX1(5));
+}
+
+static void s5p_dp_backlight_off(void)
+{
+	/* LED_BACKLIGHT_RESET: GPX1_5 */
+	gpio_request(EXYNOS5_GPX1(5), "GPX1");
+
+	gpio_direction_output(EXYNOS5_GPX1(5), 0);
+	msleep(20);
+
+	gpio_free(EXYNOS5_GPX1(5));
+}
+
+static struct s5p_dp_platdata smdk5250_dp_data __initdata = {
+	.video_info	= &smdk5250_dp_config,
+	.phy_init	= s5p_dp_phy_init,
+	.phy_exit	= s5p_dp_phy_exit,
+	.backlight_on	= s5p_dp_backlight_on,
+	.backlight_off	= s5p_dp_backlight_off,
+};
+#endif
+
+static struct platform_device *smdk5250_display_devices[] __initdata = {
+#ifdef CONFIG_FB_MIPI_DSIM
+	&smdk5250_mipi_lcd,
+	&s5p_device_mipi_dsim,
+#endif
+	&s5p_device_fimd1,
+#ifdef CONFIG_S5P_DP
+	&s5p_device_dp,
+	&smdk5250_dp_lcd,
+#endif
+};
+
+/* LCD Backlight data */
+static struct samsung_bl_gpio_info smdk5250_bl_gpio_info = {
+	.no = EXYNOS5_GPB2(0),
+	.func = S3C_GPIO_SFN(2),
+};
+
+static struct platform_pwm_backlight_data smdk5250_bl_data = {
+	.pwm_id = 0,
+	.pwm_period_ns = 30000,
+};
+
+void __init exynos5_smdk5250_display_init(void)
+{
+#ifdef CONFIG_FB_MIPI_DSIM
+	s5p_dsim_set_platdata(&dsim_platform_data);
+	s5p_device_mipi_dsim.dev.parent = &exynos5_device_pd[PD_DISP1].dev;
+#endif
+#ifdef CONFIG_S5P_DP
+	s5p_dp_set_platdata(&smdk5250_dp_data);
+	s5p_device_dp.dev.parent = &exynos5_device_pd[PD_DISP1].dev;
+#endif
+
+	s5p_device_fimd1.dev.parent = &exynos5_device_pd[PD_DISP1].dev;
+
+	dev_set_name(&s5p_device_fimd1.dev, "s3cfb.1");
+	clk_add_alias("lcd", "exynos5-fb.1", "lcd", &s5p_device_fimd1.dev);
+	clk_add_alias("sclk_fimd", "exynos5-fb.1", "sclk_fimd",
+			&s5p_device_fimd1.dev);
+	s5p_fb_setname(1, "exynos5-fb");
+
+	s5p_fimd1_set_platdata(&smdk5250_lcd1_pdata);
+
+	samsung_bl_set(&smdk5250_bl_gpio_info, &smdk5250_bl_data);
+
+	platform_add_devices(smdk5250_display_devices,
+			ARRAY_SIZE(smdk5250_display_devices));
+
+#ifdef CONFIG_S5P_DP
+	exynos4_fimd_setup_clock(&s5p_device_fimd1.dev,
+			"sclk_fimd", "mout_mpll_user", 267 * MHZ);
+#else
+	exynos4_fimd_setup_clock(&s5p_device_fimd1.dev,
+			"sclk_fimd", "mout_mpll_user", 800 * MHZ);
+#endif
+}
diff --git a/arch/arm/mach-exynos/board-smdk5250-input.c b/arch/arm/mach-exynos/board-smdk5250-input.c
new file mode 100644
index 0000000..f3ac26b
--- /dev/null
+++ b/arch/arm/mach-exynos/board-smdk5250-input.c
@@ -0,0 +1,117 @@
+/* linux/arch/arm/mach-exynos/board-smdk5250-input.c
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/gpio.h>
+#include <linux/gpio_event.h>
+#include <linux/i2c.h>
+#include <linux/input.h>
+
+#include <plat/gpio-cfg.h>
+#include <plat/devs.h>
+#include <plat/iic.h>
+
+#include <mach/irqs.h>
+
+#include "board-smdk5250.h"
+
+static struct gpio_event_direct_entry smdk5250_keypad_key_map[] = {
+	{
+		.gpio   = EXYNOS5_GPX0(0),
+		.code   = KEY_POWER,
+	}
+};
+
+static struct gpio_event_input_info smdk5250_keypad_key_info = {
+	.info.func              = gpio_event_input_func,
+	.info.no_suspend        = true,
+	.debounce_time.tv64	= 5 * NSEC_PER_MSEC,
+	.type                   = EV_KEY,
+	.keymap                 = smdk5250_keypad_key_map,
+	.keymap_size            = ARRAY_SIZE(smdk5250_keypad_key_map)
+};
+
+static struct gpio_event_info *smdk5250_input_info[] = {
+	&smdk5250_keypad_key_info.info,
+};
+
+static struct gpio_event_platform_data smdk5250_input_data = {
+	.names  = {
+		"smdk5250-keypad",
+		NULL,
+	},
+	.info           = smdk5250_input_info,
+	.info_count     = ARRAY_SIZE(smdk5250_input_info),
+};
+
+static struct platform_device smdk5250_input_device = {
+	.name   = GPIO_EVENT_DEV_NAME,
+	.id     = 0,
+	.dev    = {
+		.platform_data = &smdk5250_input_data,
+	},
+};
+
+static void __init smdk5250_gpio_power_init(void)
+{
+	int err = 0;
+
+	err = gpio_request_one(EXYNOS5_GPX0(0), 0, "GPX0");
+	if (err) {
+		printk(KERN_ERR "failed to request GPX0 for "
+				"suspend/resume control\n");
+		return;
+	}
+	s3c_gpio_setpull(EXYNOS5_GPX0(0), S3C_GPIO_PULL_NONE);
+
+	gpio_free(EXYNOS5_GPX0(0));
+}
+
+#ifdef CONFIG_WAKEUP_ASSIST
+static struct platform_device wakeup_assist_device = {
+	.name = "wakeup_assist",
+};
+#endif
+
+struct egalax_i2c_platform_data {
+	unsigned int gpio_int;
+	unsigned int gpio_en;
+	unsigned int gpio_rst;
+};
+
+static struct egalax_i2c_platform_data exynos5_egalax_data = {
+	.gpio_int	= EXYNOS5_GPX3(1),
+};
+
+static struct i2c_board_info i2c_devs7[] __initdata = {
+	{
+		I2C_BOARD_INFO("egalax_i2c", 0x04),
+		.irq		= IRQ_EINT(25),
+		.platform_data	= &exynos5_egalax_data,
+	},
+};
+
+static struct platform_device *smdk5250_input_devices[] __initdata = {
+	&s3c_device_i2c7,
+	&smdk5250_input_device,
+#ifdef CONFIG_WAKEUP_ASSIST
+	&wakeup_assist_device,
+#endif
+};
+
+void __init exynos5_smdk5250_input_init(void)
+{
+	s3c_i2c7_set_platdata(NULL);
+	i2c_register_board_info(7, i2c_devs7, ARRAY_SIZE(i2c_devs7));
+
+	smdk5250_gpio_power_init();
+
+	platform_add_devices(smdk5250_input_devices,
+			ARRAY_SIZE(smdk5250_input_devices));
+}
diff --git a/arch/arm/mach-exynos/board-smdk5250-mmc.c b/arch/arm/mach-exynos/board-smdk5250-mmc.c
new file mode 100644
index 0000000..f04a80a
--- /dev/null
+++ b/arch/arm/mach-exynos/board-smdk5250-mmc.c
@@ -0,0 +1,271 @@
+/* linux/arch/arm/mach-exynos/board-smdk5250-mmc.c
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/gpio.h>
+#include <linux/smsc911x.h>
+#include <linux/mmc/host.h>
+#include <linux/delay.h>
+
+#include <plat/gpio-cfg.h>
+#include <plat/cpu.h>
+#include <plat/clock.h>
+#include <plat/devs.h>
+#include <plat/sdhci.h>
+
+#include <mach/dwmci.h>
+
+#include "board-smdk5250.h"
+
+#ifdef CONFIG_EXYNOS4_DEV_DWMCI
+static void exynos_dwmci_cfg_gpio(int width)
+{
+	unsigned int gpio;
+
+	for (gpio = EXYNOS5_GPC0(0); gpio < EXYNOS5_GPC0(2); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV2);
+	}
+
+	switch (width) {
+	case MMC_BUS_WIDTH_8:
+		for (gpio = EXYNOS5_GPC1(3); gpio <= EXYNOS5_GPC1(6); gpio++) {
+			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
+			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+			s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV2);
+		}
+	case MMC_BUS_WIDTH_4:
+		for (gpio = EXYNOS5_GPC0(3); gpio <= EXYNOS5_GPC0(6); gpio++) {
+			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+			s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV2);
+		}
+		break;
+	case MMC_BUS_WIDTH_1:
+		gpio = EXYNOS5_GPC0(3);
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV2);
+	default:
+		break;
+	}
+}
+
+static struct dw_mci_board exynos_dwmci_pdata __initdata = {
+	.num_slots		= 1,
+	.quirks			= DW_MCI_QUIRK_BROKEN_CARD_DETECTION |
+				  DW_MCI_QUIRK_HIGHSPEED,
+	.bus_hz			= 66 * 1000 * 1000,
+	.caps			= MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR |
+				  MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
+	.fifo_depth             = 0x80,
+	.detect_delay_ms	= 200,
+	.hclk_name		= "dwmci",
+	.cclk_name		= "sclk_dwmci",
+	.cfg_gpio		= exynos_dwmci_cfg_gpio,
+};
+#endif
+
+static void exynos_dwmci0_cfg_gpio(int width)
+{
+	unsigned int gpio;
+
+	for (gpio = EXYNOS5_GPC0(0); gpio < EXYNOS5_GPC0(2); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+	}
+
+	switch (width) {
+	case MMC_BUS_WIDTH_8:
+		for (gpio = EXYNOS5_GPC1(0); gpio <= EXYNOS5_GPC1(3); gpio++) {
+			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+			s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+		}
+	case MMC_BUS_WIDTH_4:
+		for (gpio = EXYNOS5_GPC0(3); gpio <= EXYNOS5_GPC0(6); gpio++) {
+			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+			s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+		}
+		break;
+	case MMC_BUS_WIDTH_1:
+		gpio = EXYNOS5_GPC0(3);
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+	default:
+		break;
+	}
+}
+
+static struct dw_mci_board smdk5250_dwmci0_pdata __initdata = {
+	.num_slots		= 1,
+	.quirks			= DW_MCI_QUIRK_BROKEN_CARD_DETECTION |
+				  DW_MCI_QUIRK_HIGHSPEED,
+	.bus_hz			= 100 * 1000 * 1000,
+	.caps			= MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR |
+				  MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
+	.fifo_depth             = 0x80,
+	.detect_delay_ms	= 200,
+	.hclk_name		= "dwmci",
+	.cclk_name		= "sclk_dwmci",
+	.cfg_gpio		= exynos_dwmci0_cfg_gpio,
+};
+
+static int smdk5250_dwmci_get_ro(u32 slot_id)
+{
+	/* smdk5250 rev1.0 did not support SD/MMC card write pritect. */
+	return 0;
+}
+
+static void exynos_dwmci2_cfg_gpio(int width)
+{
+	unsigned int gpio;
+
+	for (gpio = EXYNOS5_GPC3(0); gpio < EXYNOS5_GPC3(2); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV2);
+	}
+
+	switch (width) {
+	case MMC_BUS_WIDTH_4:
+		for (gpio = EXYNOS5_GPC3(3); gpio <= EXYNOS5_GPC3(6); gpio++) {
+			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+			s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV2);
+		}
+		break;
+	case MMC_BUS_WIDTH_1:
+		gpio = EXYNOS5_GPC3(3);
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV2);
+	default:
+		break;
+	}
+
+	gpio = EXYNOS5_GPC3(2);
+	s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+	s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+	s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV2);
+}
+
+static struct dw_mci_board smdk5250_dwmci2_pdata __initdata = {
+	.num_slots		= 1,
+	.quirks			= DW_MCI_QUIRK_HIGHSPEED,
+	.bus_hz			= 100 * 1000 * 1000,
+	.caps			= MMC_CAP_CMD23,
+	.fifo_depth             = 0x80,
+	.detect_delay_ms	= 200,
+	.hclk_name		= "dwmci",
+	.cclk_name		= "sclk_dwmci",
+	.cfg_gpio		= exynos_dwmci2_cfg_gpio,
+	.get_ro		= smdk5250_dwmci_get_ro,
+};
+
+#ifdef CONFIG_S3C_DEV_HSMMC
+static struct s3c_sdhci_platdata smdk5250_hsmmc0_pdata __initdata = {
+	.cd_type		= S3C_SDHCI_CD_INTERNAL,
+	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
+#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
+	.max_width		= 8,
+	.host_caps		= MMC_CAP_8_BIT_DATA,
+#endif
+};
+#endif
+
+#ifdef CONFIG_S3C_DEV_HSMMC1
+static struct s3c_sdhci_platdata smdk5250_hsmmc1_pdata __initdata = {
+	.cd_type		= S3C_SDHCI_CD_INTERNAL,
+	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+#endif
+
+#ifdef CONFIG_S3C_DEV_HSMMC2
+static struct s3c_sdhci_platdata smdk5250_hsmmc2_pdata __initdata = {
+	.cd_type		= S3C_SDHCI_CD_INTERNAL,
+	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
+#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
+	.max_width		= 8,
+	.host_caps		= MMC_CAP_8_BIT_DATA,
+#endif
+};
+#endif
+
+#ifdef CONFIG_S3C_DEV_HSMMC3
+static struct s3c_sdhci_platdata smdk5250_hsmmc3_pdata __initdata = {
+	.cd_type		= S3C_SDHCI_CD_INTERNAL,
+	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+#endif
+
+static struct platform_device *smdk5250_mmc_devices[] __initdata = {
+#ifdef CONFIG_S3C_DEV_HSMMC
+	&s3c_device_hsmmc0,
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC1
+	&s3c_device_hsmmc1,
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC2
+	&s3c_device_hsmmc2,
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC3
+	&s3c_device_hsmmc3,
+#endif
+#ifdef CONFIG_EXYNOS4_DEV_DWMCI
+	&exynos_device_dwmci,
+	&exynos_device_dwmci0,
+	&exynos_device_dwmci2,
+#endif
+};
+
+void __init exynos5_smdk5250_mmc_init(void)
+{
+#ifdef CONFIG_EXYNOS4_DEV_DWMCI
+	if (samsung_rev() >= EXYNOS5250_REV_1_0) {
+		exynos_dwmci_set_platdata(&smdk5250_dwmci0_pdata, 0);
+		dev_set_name(&exynos_device_dwmci0.dev, "s3c-sdhci.0");
+		clk_add_alias("dwmci", "dw_mmc.0", "hsmmc",
+			&exynos_device_dwmci0.dev);
+		clk_add_alias("sclk_dwmci", "dw_mmc.0", "sclk_mmc",
+			&exynos_device_dwmci0.dev);
+
+		exynos_dwmci_set_platdata(&smdk5250_dwmci2_pdata, 2);
+		dev_set_name(&exynos_device_dwmci2.dev, "s3c-sdhci.2");
+		clk_add_alias("dwmci", "dw_mmc.2", "hsmmc",
+			&exynos_device_dwmci2.dev);
+		clk_add_alias("sclk_dwmci", "dw_mmc.2", "sclk_mmc",
+			&exynos_device_dwmci2.dev);
+	} else
+#endif
+	{
+#ifdef CONFIG_EXYNOS4_DEV_DWMCI
+	exynos_dwmci_set_platdata(&exynos_dwmci_pdata, 0);
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC
+	s3c_sdhci0_set_platdata(&smdk5250_hsmmc0_pdata);
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC1
+	s3c_sdhci1_set_platdata(&smdk5250_hsmmc1_pdata);
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC2
+	s3c_sdhci2_set_platdata(&smdk5250_hsmmc2_pdata);
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC3
+	s3c_sdhci3_set_platdata(&smdk5250_hsmmc3_pdata);
+#endif
+	}
+
+	platform_add_devices(smdk5250_mmc_devices,
+			ARRAY_SIZE(smdk5250_mmc_devices));
+}
diff --git a/arch/arm/mach-exynos/board-smdk5250-power.c b/arch/arm/mach-exynos/board-smdk5250-power.c
new file mode 100644
index 0000000..c47fe4f
--- /dev/null
+++ b/arch/arm/mach-exynos/board-smdk5250-power.c
@@ -0,0 +1,808 @@
+/* linux/arch/arm/mach-exynos/board-smdk5250-power.c
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+#include <linux/regulator/machine.h>
+#include <linux/mfd/max8997.h>
+#include <linux/mfd/max77686.h>
+#include <linux/notifier.h>
+#include <linux/reboot.h>
+
+#include <asm/io.h>
+
+#include <plat/devs.h>
+#include <plat/iic.h>
+#include <plat/pd.h>
+
+#include <mach/ppmu.h>
+#include <mach/dev.h>
+#include <mach/regs-pmu.h>
+
+#ifdef CONFIG_REGULATOR_S5M8767
+#include <linux/mfd/s5m87xx/s5m-core.h>
+#include <linux/mfd/s5m87xx/s5m-pmic.h>
+#endif
+
+#if defined(CONFIG_EXYNOS_SETUP_THERMAL)
+#include <plat/s5p-tmu.h>
+#endif
+
+#include "board-smdk5250.h"
+
+#define REG_INFORM4            (S5P_INFORM4)
+
+/* max8997 */
+static struct regulator_consumer_supply max8997_buck1 =
+	REGULATOR_SUPPLY("vdd_arm", NULL);
+
+static struct regulator_consumer_supply max8997_buck2 =
+	REGULATOR_SUPPLY("vdd_int", NULL);
+
+static struct regulator_consumer_supply max8997_buck3 =
+	REGULATOR_SUPPLY("vdd_g3d", NULL);
+
+static struct regulator_consumer_supply max8997_buck4 =
+	REGULATOR_SUPPLY("vdd_mif", NULL);
+
+static struct regulator_consumer_supply __initdata ldo2_consumer =
+	REGULATOR_SUPPLY("vdd_ldo2", NULL);
+
+static struct regulator_consumer_supply __initdata ldo3_consumer =
+	REGULATOR_SUPPLY("vdd_ldo3", NULL);
+
+static struct regulator_consumer_supply __initdata ldo4_consumer =
+	REGULATOR_SUPPLY("vdd_ldo4", NULL);
+
+static struct regulator_consumer_supply __initdata ldo5_consumer =
+	REGULATOR_SUPPLY("vdd_ldo5", NULL);
+
+static struct regulator_consumer_supply __initdata ldo6_consumer =
+	REGULATOR_SUPPLY("vdd_ldo6", NULL);
+
+static struct regulator_consumer_supply __initdata ldo7_consumer =
+	REGULATOR_SUPPLY("vdd_ldo7", NULL);
+
+static struct regulator_consumer_supply __initdata ldo8_consumer =
+	REGULATOR_SUPPLY("vdd_ldo8", NULL);
+
+static struct regulator_consumer_supply __initdata ldo9_consumer =
+	REGULATOR_SUPPLY("vdd_ldo9", NULL);
+
+static struct regulator_consumer_supply __initdata ldo10_consumer =
+	REGULATOR_SUPPLY("vdd_ldo10", NULL);
+
+static struct regulator_consumer_supply __initdata ldo11_consumer =
+	REGULATOR_SUPPLY("vdd_ldo11", NULL);
+
+static struct regulator_consumer_supply __initdata ldo14_consumer =
+	REGULATOR_SUPPLY("vdd_ldo14", NULL);
+
+static struct regulator_consumer_supply __initdata ldo21_consumer =
+	REGULATOR_SUPPLY("vdd_ldo21", NULL);
+
+static struct regulator_init_data __initdata __maybe_unused max8997_ldo2_data = {
+	.constraints	= {
+		.name		= "vdd_ldo2 range",
+		.min_uV		= 1000000,
+		.max_uV		= 1000000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.state_mem	= {
+			.enabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &ldo2_consumer,
+};
+
+static struct regulator_init_data __initdata __maybe_unused max8997_ldo3_data = {
+	.constraints	= {
+		.name		= "vdd_ldo3 range",
+		.min_uV		= 1000000,
+		.max_uV		= 1000000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.disabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &ldo3_consumer,
+};
+
+static struct regulator_init_data __initdata __maybe_unused max8997_ldo4_data = {
+	.constraints	= {
+		.name		= "vdd_ldo4 range",
+		.min_uV		= 1800000,
+		.max_uV		= 1800000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.disabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &ldo4_consumer,
+};
+
+static struct regulator_init_data __initdata __maybe_unused max8997_ldo5_data = {
+	.constraints	= {
+		.name		= "vdd_ldo5 range",
+		.min_uV		= 1000000,
+		.max_uV		= 1000000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.state_mem	= {
+			.enabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &ldo5_consumer,
+};
+
+static struct regulator_init_data __initdata __maybe_unused max8997_ldo6_data = {
+	.constraints	= {
+		.name		= "vdd_ldo6 range",
+		.min_uV		= 1800000,
+		.max_uV		= 1800000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.state_mem	= {
+			.enabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &ldo6_consumer,
+};
+
+static struct regulator_init_data __initdata __maybe_unused max8997_ldo7_data = {
+	.constraints	= {
+		.name		= "vdd_ldo7 range",
+		.min_uV		= 1800000,
+		.max_uV		= 1800000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.state_mem	= {
+			.enabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &ldo7_consumer,
+};
+
+static struct regulator_init_data __initdata __maybe_unused max8997_ldo8_data = {
+	.constraints	= {
+		.name		= "vdd_ldo8 range",
+		.min_uV		= 3300000,
+		.max_uV		= 3300000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.disabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &ldo8_consumer,
+};
+
+static struct regulator_init_data __initdata __maybe_unused max8997_ldo9_data = {
+	.constraints	= {
+		.name		= "vdd_ldo9 range",
+		.min_uV		= 2800000,
+		.max_uV		= 2800000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.state_mem	= {
+			.enabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &ldo9_consumer,
+};
+
+static struct regulator_init_data __initdata __maybe_unused max8997_ldo10_data = {
+	.constraints	= {
+		.name		= "vdd_ldo10 range",
+		.min_uV		= 1000000,
+		.max_uV		= 1000000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.disabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &ldo10_consumer,
+};
+
+static struct regulator_init_data __initdata __maybe_unused max8997_ldo11_data = {
+	.constraints	= {
+		.name		= "vdd_ldo11 range",
+		.min_uV		= 2800000,
+		.max_uV		= 2800000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.state_mem	= {
+			.enabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &ldo11_consumer,
+};
+
+static struct regulator_init_data __initdata __maybe_unused max8997_ldo14_data = {
+	.constraints	= {
+		.name		= "vdd_ldo14 range",
+		.min_uV		= 1800000,
+		.max_uV		= 1800000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.state_mem	= {
+			.enabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &ldo14_consumer,
+};
+
+static struct regulator_init_data __initdata __maybe_unused max8997_ldo21_data = {
+	.constraints	= {
+		.name		= "vdd_ldo21 range",
+		.min_uV		= 1200000,
+		.max_uV		= 1200000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.state_mem	= {
+			.enabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &ldo21_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_buck1_data = {
+	.constraints	= {
+		.name		= "vdd_arm range",
+		.min_uV		= 800000,
+		.max_uV		= 1500000,
+		.always_on	= 1,
+		.boot_on	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE,
+		.state_mem	= {
+			.disabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &max8997_buck1,
+};
+
+static struct regulator_init_data __initdata max8997_buck2_data = {
+	.constraints	= {
+		.name		= "vdd_int range",
+		.min_uV		= 950000,
+		.max_uV		= 1150000,
+		.always_on	= 1,
+		.boot_on	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE,
+		.state_mem	= {
+			.disabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &max8997_buck2,
+};
+
+static struct regulator_init_data __initdata max8997_buck3_data = {
+	.constraints	= {
+		.name		= "vdd_g3d range",
+		.min_uV		= 850000,
+		.max_uV		= 1200000,
+		.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE |
+				  REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.disabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &max8997_buck3,
+};
+
+static struct regulator_init_data __initdata max8997_buck4_data = {
+	.constraints	= {
+		.name		= "vdd_mif range",
+		.min_uV		= 950000,
+		.max_uV		= 1200000,
+		.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE |
+				  REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.disabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &max8997_buck4,
+};
+
+static struct max8997_regulator_data __initdata max8997_regulators[] = {
+	{ MAX8997_LDO14, &max8997_ldo14_data, },
+	{ MAX8997_BUCK1, &max8997_buck1_data, },
+	{ MAX8997_BUCK2, &max8997_buck2_data, },
+	{ MAX8997_BUCK3, &max8997_buck3_data, },
+	{ MAX8997_BUCK4, &max8997_buck4_data, },
+};
+
+static struct max8997_platform_data __initdata smdk5250_max8997_info = {
+	.num_regulators = ARRAY_SIZE(max8997_regulators),
+	.regulators     = max8997_regulators,
+
+	.buck1_voltage[0] = 1250000, /* 1.25V */
+	.buck1_voltage[1] = 1100000, /* 1.1V */
+	.buck1_voltage[2] = 1100000, /* 1.1V */
+	.buck1_voltage[3] = 1100000, /* 1.1V */
+	.buck1_voltage[4] = 1100000, /* 1.1V */
+	.buck1_voltage[5] = 1100000, /* 1.1V */
+	.buck1_voltage[6] = 1000000, /* 1.0V */
+	.buck1_voltage[7] = 950000, /* 0.95V */
+
+	.buck2_voltage[0] = 1150000, /* 1.15V */
+	.buck2_voltage[1] = 1000000, /* 1.0V */
+	.buck2_voltage[2] = 950000, /* 0.95V */
+	.buck2_voltage[3] = 900000, /* 0.9V */
+	.buck2_voltage[4] = 1000000, /* 1.0V */
+	.buck2_voltage[5] = 1000000, /* 1.0V */
+	.buck2_voltage[6] = 950000, /* 0.95V */
+	.buck2_voltage[7] = 900000, /* 0.9V */
+
+	.buck5_voltage[0] = 1100000, /* 1.2V */
+	.buck5_voltage[1] = 1100000, /* 1.1V */
+	.buck5_voltage[2] = 1100000, /* 1.1V */
+	.buck5_voltage[3] = 1100000, /* 1.1V */
+	.buck5_voltage[4] = 1100000, /* 1.1V */
+	.buck5_voltage[5] = 1100000, /* 1.1V */
+	.buck5_voltage[6] = 1100000, /* 1.1V */
+	.buck5_voltage[7] = 1100000, /* 1.1V */
+};
+
+/* max77686 */
+static struct regulator_consumer_supply max77686_buck1 =
+REGULATOR_SUPPLY("vdd_mif", NULL);
+
+static struct regulator_consumer_supply max77686_buck2 =
+REGULATOR_SUPPLY("vdd_arm", NULL);
+
+static struct regulator_consumer_supply max77686_buck3 =
+REGULATOR_SUPPLY("vdd_int", NULL);
+
+static struct regulator_consumer_supply max77686_buck4 =
+REGULATOR_SUPPLY("vdd_g3d", NULL);
+
+static struct regulator_consumer_supply max77686_ldo11_consumer =
+REGULATOR_SUPPLY("vdd_ldo11", NULL);
+
+static struct regulator_consumer_supply max77686_ldo14_consumer =
+REGULATOR_SUPPLY("vdd_ldo14", NULL);
+
+static struct regulator_init_data max77686_buck1_data = {
+	.constraints = {
+		.name = "vdd_mif range",
+		.min_uV = 950000,
+		.max_uV = 1300000,
+		.always_on = 1,
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+				REGULATOR_CHANGE_STATUS,
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &max77686_buck1,
+};
+
+static struct regulator_init_data max77686_buck2_data = {
+	.constraints = {
+		.name = "vdd_arm range",
+		.min_uV = 800000,
+		.max_uV = 1350000,
+		.always_on = 1,
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &max77686_buck2,
+};
+
+static struct regulator_init_data max77686_buck3_data = {
+	.constraints = {
+		.name = "vdd_int range",
+		.min_uV = 900000,
+		.max_uV = 1200000,
+		.always_on = 1,
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &max77686_buck3,
+};
+
+static struct regulator_init_data max77686_buck4_data = {
+	.constraints = {
+		.name = "vdd_g3d range",
+		.min_uV = 700000,
+		.max_uV = 1300000,
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+				  REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.disabled = 1,
+		},
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &max77686_buck4,
+};
+
+static struct regulator_init_data max77686_ldo11_data = {
+	.constraints	= {
+		.name		= "vdd_ldo11 range",
+		.min_uV		= 1900000,
+		.max_uV		= 1900000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.state_mem	= {
+			.enabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &max77686_ldo11_consumer,
+};
+
+static struct regulator_init_data max77686_ldo14_data = {
+	.constraints	= {
+		.name		= "vdd_ldo14 range",
+		.min_uV		= 1900000,
+		.max_uV		= 1900000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.state_mem	= {
+			.enabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &max77686_ldo14_consumer,
+};
+
+static struct max77686_regulator_data max77686_regulators[] = {
+	{MAX77686_BUCK1, &max77686_buck1_data,},
+	{MAX77686_BUCK2, &max77686_buck2_data,},
+	{MAX77686_BUCK3, &max77686_buck3_data,},
+	{MAX77686_BUCK4, &max77686_buck4_data,},
+	{MAX77686_LDO11, &max77686_ldo11_data,},
+	{MAX77686_LDO14, &max77686_ldo14_data,},
+};
+
+struct max77686_opmode_data max77686_opmode_data[MAX77686_REG_MAX] = {
+	[MAX77686_LDO11] = {MAX77686_LDO11, MAX77686_OPMODE_STANDBY},
+	[MAX77686_LDO14] = {MAX77686_LDO14, MAX77686_OPMODE_STANDBY},
+	[MAX77686_BUCK1] = {MAX77686_BUCK1, MAX77686_OPMODE_STANDBY},
+	[MAX77686_BUCK2] = {MAX77686_BUCK2, MAX77686_OPMODE_STANDBY},
+	[MAX77686_BUCK3] = {MAX77686_BUCK3, MAX77686_OPMODE_STANDBY},
+	[MAX77686_BUCK4] = {MAX77686_BUCK4, MAX77686_OPMODE_STANDBY},
+};
+
+static struct max77686_platform_data smdk5250_max77686_info = {
+	.num_regulators = ARRAY_SIZE(max77686_regulators),
+	.regulators = max77686_regulators,
+	.irq_gpio	= 0,
+	.irq_base	= 0,
+	.wakeup		= 0,
+
+	.opmode_data = max77686_opmode_data,
+	.ramp_rate = MAX77686_RAMP_RATE_27MV,
+
+	.buck2_voltage[0] = 1300000,	/* 1.3V */
+	.buck2_voltage[1] = 1000000,	/* 1.0V */
+	.buck2_voltage[2] = 950000,	/* 0.95V */
+	.buck2_voltage[3] = 900000,	/* 0.9V */
+	.buck2_voltage[4] = 1000000,	/* 1.0V */
+	.buck2_voltage[5] = 1000000,	/* 1.0V */
+	.buck2_voltage[6] = 950000,	/* 0.95V */
+	.buck2_voltage[7] = 900000,	/* 0.9V */
+
+	.buck3_voltage[0] = 1037500,	/* 1.0375V */
+	.buck3_voltage[1] = 1000000,	/* 1.0V */
+	.buck3_voltage[2] = 950000,	/* 0.95V */
+	.buck3_voltage[3] = 900000,	/* 0.9V */
+	.buck3_voltage[4] = 1000000,	/* 1.0V */
+	.buck3_voltage[5] = 1000000,	/* 1.0V */
+	.buck3_voltage[6] = 950000,	/* 0.95V */
+	.buck3_voltage[7] = 900000,	/* 0.9V */
+
+	.buck4_voltage[0] = 1100000,	/* 1.1V */
+	.buck4_voltage[1] = 1000000,	/* 1.0V */
+	.buck4_voltage[2] = 950000,	/* 0.95V */
+	.buck4_voltage[3] = 900000,	/* 0.9V */
+	.buck4_voltage[4] = 1000000,	/* 1.0V */
+	.buck4_voltage[5] = 1000000,	/* 1.0V */
+	.buck4_voltage[6] = 950000,	/* 0.95V */
+	.buck4_voltage[7] = 900000,	/* 0.9V */
+};
+
+#ifdef CONFIG_REGULATOR_S5M8767
+/* S5M8767 Regulator */
+static int s5m_cfg_irq(void)
+{
+	/* AP_PMIC_IRQ: EINT26 */
+	s3c_gpio_cfgpin(EXYNOS5_GPX3(2), S3C_GPIO_SFN(0xF));
+	s3c_gpio_setpull(EXYNOS5_GPX3(2), S3C_GPIO_PULL_UP);
+	return 0;
+}
+
+static struct regulator_consumer_supply s5m8767_buck1_consumer =
+	REGULATOR_SUPPLY("vdd_mif", NULL);
+
+static struct regulator_consumer_supply s5m8767_buck2_consumer =
+	REGULATOR_SUPPLY("vdd_arm", NULL);
+
+static struct regulator_consumer_supply s5m8767_buck3_consumer =
+	REGULATOR_SUPPLY("vdd_int", NULL);
+
+static struct regulator_consumer_supply s5m8767_buck4_consumer =
+	REGULATOR_SUPPLY("vdd_g3d", NULL);
+
+static struct regulator_init_data s5m8767_buck1_data = {
+	.constraints	= {
+		.name		= "vdd_mif range",
+		.min_uV		= 950000,
+		.max_uV		= 1300000,
+		.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE |
+				  REGULATOR_CHANGE_STATUS,
+		.always_on = 1,
+		.boot_on = 1,
+		.state_mem	= {
+			.disabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &s5m8767_buck1_consumer,
+};
+
+static struct regulator_init_data s5m8767_buck2_data = {
+	.constraints	= {
+		.name		= "vdd_arm range",
+		.min_uV		=  800000,
+		.max_uV		= 1350000,
+		.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE |
+				  REGULATOR_CHANGE_STATUS,
+		.always_on = 1,
+		.boot_on = 1,
+		.state_mem	= {
+			.disabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &s5m8767_buck2_consumer,
+};
+
+static struct regulator_init_data s5m8767_buck3_data = {
+	.constraints	= {
+		.name		= "vdd_int range",
+		.min_uV		=  900000,
+		.max_uV		= 1200000,
+		.apply_uV	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE,
+		.always_on = 1,
+		.boot_on = 1,
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &s5m8767_buck3_consumer,
+};
+
+static struct regulator_init_data s5m8767_buck4_data = {
+	.constraints	= {
+		.name		= "vdd_g3d range",
+		.min_uV		=  850000,
+		.max_uV		= 1300000,
+		.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE |
+				REGULATOR_CHANGE_STATUS,
+		.boot_on = 1,
+		.state_mem	= {
+			.disabled	= 1,
+		},
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &s5m8767_buck4_consumer,
+};
+
+static struct s5m_regulator_data gaia_regulators[] = {
+	{S5M8767_BUCK1, &s5m8767_buck1_data},
+	{S5M8767_BUCK2, &s5m8767_buck2_data},
+	{S5M8767_BUCK3, &s5m8767_buck3_data},
+	{S5M8767_BUCK4, &s5m8767_buck4_data},
+};
+
+struct s5m_opmode_data s5m8767_opmode_data[S5M8767_REG_MAX] = {
+	[S5M8767_BUCK1] = {S5M8767_BUCK1, S5M_OPMODE_STANDBY},
+	[S5M8767_BUCK2] = {S5M8767_BUCK2, S5M_OPMODE_STANDBY},
+	[S5M8767_BUCK3] = {S5M8767_BUCK3, S5M_OPMODE_STANDBY},
+	[S5M8767_BUCK4] = {S5M8767_BUCK4, S5M_OPMODE_STANDBY},
+};
+
+static struct s5m_platform_data smdk5250_s5m8767_pdata = {
+	.device_type		= S5M8767X,
+	.irq_base		= IRQ_BOARD_START,
+	.num_regulators		= ARRAY_SIZE(gaia_regulators),
+	.regulators		= gaia_regulators,
+	.cfg_pmic_irq		= s5m_cfg_irq,
+	.wakeup			= 1,
+	.opmode_data		= s5m8767_opmode_data,
+	.wtsr_smpl		= 1,
+
+	.buck2_voltage[0]	= 1250000,
+	.buck2_voltage[1]	= 1200000,
+	.buck2_voltage[2]	= 1150000,
+	.buck2_voltage[3]	= 1100000,
+	.buck2_voltage[4]	= 1050000,
+	.buck2_voltage[5]	= 1000000,
+	.buck2_voltage[6]	=  950000,
+	.buck2_voltage[7]	=  900000,
+
+	.buck3_voltage[0]	= 1100000,
+	.buck3_voltage[1]	= 1000000,
+	.buck3_voltage[2]	= 950000,
+	.buck3_voltage[3]	= 900000,
+	.buck3_voltage[4]	= 1100000,
+	.buck3_voltage[5]	= 1000000,
+	.buck3_voltage[6]	= 950000,
+	.buck3_voltage[7]	= 900000,
+
+	.buck4_voltage[0]	= 1200000,
+	.buck4_voltage[1]	= 1150000,
+	.buck4_voltage[2]	= 1200000,
+	.buck4_voltage[3]	= 1100000,
+	.buck4_voltage[4]	= 1100000,
+	.buck4_voltage[5]	= 1100000,
+	.buck4_voltage[6]	= 1100000,
+	.buck4_voltage[7]	= 1100000,
+
+	.buck_ramp_delay        = 25,
+	.buck2_ramp_enable      = true,
+	.buck3_ramp_enable      = true,
+	.buck4_ramp_enable      = true,
+};
+/* End of S5M8767 */
+#endif
+
+static struct i2c_board_info i2c_devs0[] __initdata = {
+#ifdef CONFIG_REGULATOR_S5M8767
+	{
+		I2C_BOARD_INFO("s5m87xx", 0xCC >> 1),
+		.platform_data = &smdk5250_s5m8767_pdata,
+		.irq		= IRQ_EINT(26),
+	},
+#else
+	{
+		I2C_BOARD_INFO("max8997", 0x66),
+		.platform_data	= &smdk5250_max8997_info,
+	}, {
+		I2C_BOARD_INFO("max77686", (0x12 >> 1)),
+		.platform_data	= &smdk5250_max77686_info,
+	},
+#endif
+};
+
+#ifdef CONFIG_BATTERY_SAMSUNG
+static struct platform_device samsung_device_battery = {
+	.name	= "samsung-fake-battery",
+	.id	= -1,
+};
+#endif
+
+#ifdef CONFIG_BUSFREQ_OPP
+/* BUSFREQ to control memory/bus*/
+static struct device_domain busfreq;
+#endif
+
+static struct platform_device exynos5_busfreq = {
+	.id = -1,
+	.name = "exynos-busfreq",
+};
+
+#ifdef CONFIG_EXYNOS_SETUP_THERMAL
+/* below temperature base on the celcius degree */
+struct tmu_data exynos_tmu_data __initdata = {
+	.ts = {
+		.stop_throttle  = 82,
+		.start_throttle = 85,
+		.stop_warning  = 95,
+		.start_warning = 103,
+		.start_tripping = 110, /* temp to do tripping */
+	},
+	.efuse_value = 55,
+	.slope = 0x10008802,
+	.mode = 0,
+};
+#endif
+
+static struct platform_device *smdk5250_power_devices[] __initdata = {
+	/* Samsung Power Domain */
+	&exynos5_device_pd[PD_MFC],
+	&exynos5_device_pd[PD_G3D],
+	&exynos5_device_pd[PD_ISP],
+	&exynos5_device_pd[PD_GSCL],
+	&exynos5_device_pd[PD_DISP1],
+	&s3c_device_i2c0,
+#ifdef CONFIG_BATTERY_SAMSUNG
+	&samsung_device_battery,
+#endif
+#ifdef CONFIG_EXYNOS_SETUP_THERMAL
+	&exynos_device_tmu,
+#endif
+	&exynos5_busfreq,
+};
+
+static int smdk5250_notifier_call(struct notifier_block *this,
+					unsigned long code, void *_cmd)
+{
+	int mode = 0;
+
+	if ((code == SYS_RESTART) && _cmd)
+		if (!strcmp((char *)_cmd, "recovery"))
+			mode = 0xf;
+
+	__raw_writel(mode, REG_INFORM4);
+
+	return NOTIFY_DONE;
+}
+
+static struct notifier_block smdk5250_reboot_notifier = {
+	.notifier_call = smdk5250_notifier_call,
+};
+
+void __init exynos5_smdk5250_power_init(void)
+{
+	s3c_i2c0_set_platdata(NULL);
+	i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
+
+#if defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME)
+	exynos_pd_enable(&exynos5_device_pd[PD_MFC].dev);
+	exynos_pd_enable(&exynos5_device_pd[PD_G3D].dev);
+	exynos_pd_enable(&exynos5_device_pd[PD_ISP].dev);
+	exynos_pd_enable(&exynos5_device_pd[PD_GSCL].dev);
+	exynos_pd_enable(&exynos5_device_pd[PD_DISP1].dev);
+#elif defined(CONFIG_EXYNOS_DEV_PD)
+	/*
+	 * These power domains should be always on
+	 * without runtime pm support.
+	 */
+	exynos_pd_enable(&exynos5_device_pd[PD_MFC].dev);
+	exynos_pd_enable(&exynos5_device_pd[PD_G3D].dev);
+	exynos_pd_enable(&exynos5_device_pd[PD_ISP].dev);
+	exynos_pd_enable(&exynos5_device_pd[PD_GSCL].dev);
+	exynos_pd_enable(&exynos5_device_pd[PD_DISP1].dev);
+#endif
+
+#ifdef CONFIG_EXYNOS_SETUP_THERMAL
+	s5p_tmu_set_platdata(&exynos_tmu_data);
+#endif
+
+#ifdef CONFIG_BUSFREQ_OPP
+	dev_add(&busfreq, &exynos5_busfreq.dev);
+	ppmu_init(&exynos_ppmu[PPMU_CPU], &exynos5_busfreq.dev);
+	ppmu_init(&exynos_ppmu[PPMU_DDR_C], &exynos5_busfreq.dev);
+	ppmu_init(&exynos_ppmu[PPMU_DDR_R1], &exynos5_busfreq.dev);
+	ppmu_init(&exynos_ppmu[PPMU_DDR_L], &exynos5_busfreq.dev);
+	ppmu_init(&exynos_ppmu[PPMU_RIGHT0_BUS], &exynos5_busfreq.dev);
+#endif
+	register_reboot_notifier(&smdk5250_reboot_notifier);
+
+	platform_add_devices(smdk5250_power_devices,
+			ARRAY_SIZE(smdk5250_power_devices));
+}
diff --git a/arch/arm/mach-exynos/board-smdk5250-spi.c b/arch/arm/mach-exynos/board-smdk5250-spi.c
new file mode 100644
index 0000000..0d149de
--- /dev/null
+++ b/arch/arm/mach-exynos/board-smdk5250-spi.c
@@ -0,0 +1,176 @@
+/* linux/arch/arm/mach-exynos/board-smdk5250-spi.c
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/clk.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi_gpio.h>
+#include <linux/gpio.h>
+#include <linux/err.h>
+
+#include <plat/gpio-cfg.h>
+#include <plat/clock.h>
+#include <plat/devs.h>
+#include <plat/s3c64xx-spi.h>
+
+#include <mach/spi-clocks.h>
+
+#include "board-smdk5250.h"
+
+#if defined(CONFIG_S3C64XX_DEV_SPI)
+static struct s3c64xx_spi_csinfo spi0_csi[] = {
+	[0] = {
+		.line = EXYNOS5_GPA2(1),
+		.set_level = gpio_set_value,
+		.fb_delay = 0x2,
+	},
+};
+
+static struct spi_board_info spi0_board_info[] __initdata = {
+	{
+		.modalias = "spidev",
+		.platform_data = NULL,
+		.max_speed_hz = 10*1000*1000,
+		.bus_num = 0,
+		.chip_select = 0,
+		.mode = SPI_MODE_0,
+		.controller_data = &spi0_csi[0],
+	}
+};
+
+static struct s3c64xx_spi_csinfo spi1_csi[] = {
+	[0] = {
+		.line = EXYNOS5_GPA2(5),
+		.set_level = gpio_set_value,
+		.fb_delay = 0x2,
+	},
+};
+
+static struct spi_board_info spi1_board_info[] __initdata = {
+	{
+		.modalias = "spidev",
+		.platform_data = NULL,
+		.max_speed_hz = 10*1000*1000,
+		.bus_num = 1,
+		.chip_select = 0,
+		.mode = SPI_MODE_0,
+		.controller_data = &spi1_csi[0],
+	}
+};
+
+static struct s3c64xx_spi_csinfo spi2_csi[] = {
+	[0] = {
+		.line = EXYNOS5_GPB1(2),
+		.set_level = gpio_set_value,
+		.fb_delay = 0x2,
+	},
+};
+
+static struct spi_board_info spi2_board_info[] __initdata = {
+	{
+		.modalias = "spidev",
+		.platform_data = NULL,
+		.max_speed_hz = 10*1000*1000,
+		.bus_num = 2,
+		.chip_select = 0,
+		.mode = SPI_MODE_0,
+		.controller_data = &spi2_csi[0],
+	}
+};
+
+static struct platform_device *smdk5250_spi_devices[] __initdata = {
+	&exynos_device_spi0,
+	&exynos_device_spi1,
+	&exynos_device_spi2,
+};
+
+void __init exynos5_smdk5250_spi_init(void)
+{
+	struct clk *sclk = NULL;
+	struct clk *prnt = NULL;
+	struct device *spi0_dev = &exynos_device_spi0.dev;
+	struct device *spi1_dev = &exynos_device_spi1.dev;
+	struct device *spi2_dev = &exynos_device_spi2.dev;
+
+	sclk = clk_get(spi0_dev, "sclk_spi0");
+	if (IS_ERR(sclk))
+		dev_err(spi0_dev, "failed to get sclk for SPI-0\n");
+	prnt = clk_get(spi0_dev, "mout_mpll_user");
+	if (IS_ERR(prnt))
+		dev_err(spi0_dev, "failed to get prnt\n");
+	if (clk_set_parent(sclk, prnt))
+		printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
+				prnt->name, sclk->name);
+
+	clk_set_rate(sclk, 800 * 1000 * 1000);
+	clk_put(sclk);
+	clk_put(prnt);
+
+	if (!gpio_request(EXYNOS5_GPA2(1), "SPI_CS0")) {
+		gpio_direction_output(EXYNOS5_GPA2(1), 1);
+		s3c_gpio_cfgpin(EXYNOS5_GPA2(1), S3C_GPIO_SFN(1));
+		s3c_gpio_setpull(EXYNOS5_GPA2(1), S3C_GPIO_PULL_UP);
+		exynos_spi_set_info(0, EXYNOS_SPI_SRCCLK_SCLK,
+			ARRAY_SIZE(spi0_csi));
+	}
+
+	spi_register_board_info(spi0_board_info, ARRAY_SIZE(spi0_board_info));
+
+	sclk = clk_get(spi1_dev, "sclk_spi1");
+	if (IS_ERR(sclk))
+		dev_err(spi1_dev, "failed to get sclk for SPI-1\n");
+	prnt = clk_get(spi1_dev, "mout_mpll_user");
+	if (IS_ERR(prnt))
+		dev_err(spi1_dev, "failed to get prnt\n");
+	if (clk_set_parent(sclk, prnt))
+		printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
+				prnt->name, sclk->name);
+
+	clk_set_rate(sclk, 800 * 1000 * 1000);
+	clk_put(sclk);
+	clk_put(prnt);
+
+	if (!gpio_request(EXYNOS5_GPA2(5), "SPI_CS1")) {
+		gpio_direction_output(EXYNOS5_GPA2(5), 1);
+		s3c_gpio_cfgpin(EXYNOS5_GPA2(5), S3C_GPIO_SFN(1));
+		s3c_gpio_setpull(EXYNOS5_GPA2(5), S3C_GPIO_PULL_UP);
+		exynos_spi_set_info(1, EXYNOS_SPI_SRCCLK_SCLK,
+			ARRAY_SIZE(spi1_csi));
+	}
+
+	spi_register_board_info(spi1_board_info, ARRAY_SIZE(spi1_board_info));
+
+	sclk = clk_get(spi2_dev, "sclk_spi2");
+	if (IS_ERR(sclk))
+		dev_err(spi2_dev, "failed to get sclk for SPI-2\n");
+	prnt = clk_get(spi2_dev, "mout_mpll_user");
+	if (IS_ERR(prnt))
+		dev_err(spi2_dev, "failed to get prnt\n");
+	if (clk_set_parent(sclk, prnt))
+		printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
+				prnt->name, sclk->name);
+
+	clk_set_rate(sclk, 800 * 1000 * 1000);
+	clk_put(sclk);
+	clk_put(prnt);
+
+	if (!gpio_request(EXYNOS5_GPB1(2), "SPI_CS2")) {
+		gpio_direction_output(EXYNOS5_GPB1(2), 1);
+		s3c_gpio_cfgpin(EXYNOS5_GPB1(2), S3C_GPIO_SFN(1));
+		s3c_gpio_setpull(EXYNOS5_GPB1(2), S3C_GPIO_PULL_UP);
+		exynos_spi_set_info(2, EXYNOS_SPI_SRCCLK_SCLK,
+			ARRAY_SIZE(spi2_csi));
+	}
+
+	spi_register_board_info(spi2_board_info, ARRAY_SIZE(spi2_board_info));
+
+	platform_add_devices(smdk5250_spi_devices,
+			ARRAY_SIZE(smdk5250_spi_devices));
+}
+#endif
diff --git a/arch/arm/mach-exynos/board-smdk5250-usb.c b/arch/arm/mach-exynos/board-smdk5250-usb.c
new file mode 100644
index 0000000..28b40da
--- /dev/null
+++ b/arch/arm/mach-exynos/board-smdk5250-usb.c
@@ -0,0 +1,201 @@
+/* linux/arch/arm/mach-exynos/board-smdk5250-usb.c
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/platform_data/exynos_usb3_drd.h>
+
+#include <plat/gpio-cfg.h>
+#include <plat/cpu.h>
+#include <plat/devs.h>
+
+#include <plat/ehci.h>
+#include <plat/usbgadget.h>
+#include <plat/usb-switch.h>
+
+#include "board-smdk5250.h"
+
+static struct s5p_ehci_platdata smdk5250_ehci_pdata;
+
+static void __init smdk5250_ehci_init(void)
+{
+	struct s5p_ehci_platdata *pdata = &smdk5250_ehci_pdata;
+
+#ifndef CONFIG_USB_EXYNOS_SWITCH
+	if (samsung_rev() >= EXYNOS5250_REV_1_0) {
+		if (gpio_request_one(EXYNOS5_GPX2(6), GPIOF_OUT_INIT_HIGH,
+			"HOST_VBUS_CONTROL"))
+			printk(KERN_ERR "failed to request gpio_host_vbus\n");
+		else {
+			s3c_gpio_setpull(EXYNOS5_GPX2(6), S3C_GPIO_PULL_NONE);
+			gpio_free(EXYNOS5_GPX2(6));
+		}
+	}
+#endif
+	s5p_ehci_set_platdata(pdata);
+}
+
+static struct s5p_ohci_platdata smdk5250_ohci_pdata;
+
+static void __init smdk5250_ohci_init(void)
+{
+	struct s5p_ohci_platdata *pdata = &smdk5250_ohci_pdata;
+
+	s5p_ohci_set_platdata(pdata);
+}
+
+/* USB GADGET */
+static struct s5p_usbgadget_platdata smdk5250_usbgadget_pdata;
+
+static void __init smdk5250_usbgadget_init(void)
+{
+	struct s5p_usbgadget_platdata *pdata = &smdk5250_usbgadget_pdata;
+
+	s5p_usbgadget_set_platdata(pdata);
+}
+
+static struct exynos_usb3_drd_pdata smdk5250_ss_udc_pdata;
+
+static void __init smdk5250_ss_udc_init(void)
+{
+	struct exynos_usb3_drd_pdata *pdata = &smdk5250_ss_udc_pdata;
+
+	exynos_ss_udc_set_platdata(pdata);
+}
+
+static struct exynos_usb3_drd_pdata smdk5250_xhci_pdata;
+
+static void __init smdk5250_xhci_init(void)
+{
+	struct exynos_usb3_drd_pdata *pdata = &smdk5250_xhci_pdata;
+
+	exynos_xhci_set_platdata(pdata);
+}
+
+static struct s5p_usbswitch_platdata smdk5250_usbswitch_pdata;
+
+static void __init smdk5250_usbswitch_init(void)
+{
+	struct s5p_usbswitch_platdata *pdata = &smdk5250_usbswitch_pdata;
+	int err;
+
+	/* USB 2.0 detect GPIO */
+	if (samsung_rev() < EXYNOS5250_REV_1_0) {
+		pdata->gpio_device_detect = 0;
+		pdata->gpio_host_vbus = 0;
+	} else {
+#if defined(CONFIG_USB_EHCI_S5P) || defined(CONFIG_USB_OHCI_S5P)
+		pdata->gpio_host_detect = EXYNOS5_GPX1(6);
+		err = gpio_request_one(pdata->gpio_host_detect, GPIOF_IN,
+			"HOST_DETECT");
+		if (err) {
+			printk(KERN_ERR "failed to request host gpio\n");
+			return;
+		}
+
+		s3c_gpio_cfgpin(pdata->gpio_host_detect, S3C_GPIO_SFN(0xF));
+		s3c_gpio_setpull(pdata->gpio_host_detect, S3C_GPIO_PULL_NONE);
+		gpio_free(pdata->gpio_host_detect);
+
+		pdata->gpio_host_vbus = EXYNOS5_GPX2(6);
+		err = gpio_request_one(pdata->gpio_host_vbus,
+			GPIOF_OUT_INIT_LOW,
+			"HOST_VBUS_CONTROL");
+		if (err) {
+			printk(KERN_ERR "failed to request host_vbus gpio\n");
+			return;
+		}
+
+		s3c_gpio_setpull(pdata->gpio_host_vbus, S3C_GPIO_PULL_NONE);
+		gpio_free(pdata->gpio_host_vbus);
+#endif
+
+#ifdef CONFIG_USB_S3C_OTGD
+		pdata->gpio_device_detect = EXYNOS5_GPX3(4);
+		err = gpio_request_one(pdata->gpio_device_detect, GPIOF_IN,
+			"DEVICE_DETECT");
+		if (err) {
+			printk(KERN_ERR "failed to request device gpio\n");
+			return;
+		}
+
+		s3c_gpio_cfgpin(pdata->gpio_device_detect, S3C_GPIO_SFN(0xF));
+		s3c_gpio_setpull(pdata->gpio_device_detect, S3C_GPIO_PULL_NONE);
+		gpio_free(pdata->gpio_device_detect);
+#endif
+	}
+
+	/* USB 3.0 DRD detect GPIO */
+	if (samsung_rev() < EXYNOS5250_REV_1_0) {
+		pdata->gpio_drd_host_detect = 0;
+		pdata->gpio_drd_device_detect = 0;
+	} else {
+#ifdef CONFIG_USB_XHCI_EXYNOS
+		pdata->gpio_drd_host_detect = EXYNOS5_GPX1(7);
+		err = gpio_request_one(pdata->gpio_drd_host_detect, GPIOF_IN,
+			"DRD_HOST_DETECT");
+		if (err) {
+			printk(KERN_ERR "failed to request drd_host gpio\n");
+			return;
+		}
+
+		s3c_gpio_cfgpin(pdata->gpio_drd_host_detect, S3C_GPIO_SFN(0xF));
+		s3c_gpio_setpull(pdata->gpio_drd_host_detect,
+			S3C_GPIO_PULL_NONE);
+		gpio_free(pdata->gpio_drd_host_detect);
+#endif
+
+#ifdef CONFIG_USB_EXYNOS_SS_UDC
+		pdata->gpio_drd_device_detect = EXYNOS5_GPX0(6);
+		err = gpio_request_one(pdata->gpio_drd_device_detect, GPIOF_IN,
+			"DRD_DEVICE_DETECT");
+		if (err) {
+			printk(KERN_ERR "failed to request drd_device\n");
+			return;
+		}
+
+		s3c_gpio_cfgpin(pdata->gpio_drd_device_detect,
+			S3C_GPIO_SFN(0xF));
+		s3c_gpio_setpull(pdata->gpio_drd_device_detect,
+			S3C_GPIO_PULL_NONE);
+		gpio_free(pdata->gpio_drd_device_detect);
+#endif
+	}
+
+	s5p_usbswitch_set_platdata(pdata);
+}
+
+static struct platform_device *smdk5250_usb_devices[] __initdata = {
+	&s5p_device_ehci,
+	&s5p_device_ohci,
+	&s3c_device_usbgadget,
+#ifdef CONFIG_USB_ANDROID_RNDIS
+	&s3c_device_rndis,
+#endif
+#ifdef CONFIG_USB_ANDROID
+	&s3c_device_android_usb,
+	&s3c_device_usb_mass_storage,
+#endif
+	&exynos_device_ss_udc,
+	&exynos_device_xhci,
+};
+
+void __init exynos5_smdk5250_usb_init(void)
+{
+	smdk5250_ehci_init();
+	smdk5250_ohci_init();
+	smdk5250_usbgadget_init();
+	smdk5250_ss_udc_init();
+	smdk5250_xhci_init();
+	smdk5250_usbswitch_init();
+
+	platform_add_devices(smdk5250_usb_devices,
+			ARRAY_SIZE(smdk5250_usb_devices));
+}
diff --git a/arch/arm/mach-exynos/board-smdk5250.h b/arch/arm/mach-exynos/board-smdk5250.h
new file mode 100644
index 0000000..0395d9c
--- /dev/null
+++ b/arch/arm/mach-exynos/board-smdk5250.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_EXYNOS_BOARD_SMDK5250_H
+#define __MACH_EXYNOS_BOARD_SMDK5250_H
+
+void exynos5_smdk5250_mmc_init(void);
+void exynos5_smdk5250_display_init(void);
+void exynos5_smdk5250_power_init(void);
+void exynos5_smdk5250_audio_init(void);
+void exynos5_smdk5250_usb_init(void);
+void exynos5_smdk5250_input_init(void);
+void exynos5_smdk5250_spi_init(void);
+
+#endif
diff --git a/arch/arm/mach-exynos/board-u1-lgt-modems.c b/arch/arm/mach-exynos/board-u1-lgt-modems.c
new file mode 100644
index 0000000..9fce9e3
--- /dev/null
+++ b/arch/arm/mach-exynos/board-u1-lgt-modems.c
@@ -0,0 +1,1461 @@
+/* linux/arch/arm/mach-xxxx/board-u1-lgt-modems.c
+ * Copyright (C) 2010 Samsung Electronics. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/regulator/consumer.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/vmalloc.h>
+#include <linux/if_arp.h>
+
+/* inlcude platform specific file */
+#include <linux/platform_data/modem.h>
+#include <mach/sec_modem.h>
+#include <mach/gpio.h>
+#include <mach/gpio-exynos4.h>
+#include <plat/gpio-cfg.h>
+#include <mach/regs-mem.h>
+#include <plat/regs-srom.h>
+
+#include <plat/devs.h>
+#include <plat/ehci.h>
+
+#define SROM_CS0_BASE		0x04000000
+#define SROM_WIDTH		0x01000000
+#define SROM_NUM_ADDR_BITS	14
+
+/* For "bus width and wait control (BW)" register */
+enum sromc_attr {
+	SROMC_DATA_16   = 0x1,	/* 16-bit data bus	*/
+	SROMC_BYTE_ADDR = 0x2,	/* Byte base address	*/
+	SROMC_WAIT_EN   = 0x4,	/* Wait enabled		*/
+	SROMC_BYTE_EN   = 0x8,	/* Byte access enabled	*/
+	SROMC_MASK      = 0xF
+};
+
+/* DPRAM configuration */
+struct sromc_cfg {
+	enum sromc_attr attr;
+	unsigned size;
+	unsigned csn;		/* CSn #			*/
+	unsigned addr;		/* Start address (physical)	*/
+	unsigned end;		/* End address (physical)	*/
+};
+
+/* DPRAM access timing configuration */
+struct sromc_access_cfg {
+	u32 tacs;		/* Address set-up before CSn		*/
+	u32 tcos;		/* Chip selection set-up before OEn	*/
+	u32 tacc;		/* Access cycle				*/
+	u32 tcoh;		/* Chip selection hold on OEn		*/
+	u32 tcah;		/* Address holding time after CSn	*/
+	u32 tacp;		/* Page mode access cycle at Page mode	*/
+	u32 pmc;		/* Page Mode config			*/
+};
+
+/* For CBP7.2 EDPRAM (External DPRAM) */
+#define CBP_EDPRAM_SIZE		0x8000	/* 32 KB */
+
+
+#define INT_MASK_REQ_ACK_F	0x0020
+#define INT_MASK_REQ_ACK_R	0x0010
+#define INT_MASK_RES_ACK_F	0x0008
+#define INT_MASK_RES_ACK_R	0x0004
+#define INT_MASK_SEND_F		0x0002
+#define INT_MASK_SEND_R		0x0001
+
+#define INT_MASK_REQ_ACK_RFS	0x0400 /* Request RES_ACK_RFS		*/
+#define INT_MASK_RES_ACK_RFS	0x0200 /* Response of REQ_ACK_RFS	*/
+#define INT_MASK_SEND_RFS	0x0100 /* Indicate sending RFS data	*/
+
+
+/* Function prototypes */
+static void config_dpram_port_gpio(void);
+static void init_sromc(void);
+static void setup_sromc(unsigned csn, struct sromc_cfg *cfg,
+		struct sromc_access_cfg *acc_cfg);
+static int __init init_modem(void);
+
+static struct sromc_cfg cbp_edpram_cfg = {
+	.attr = (SROMC_DATA_16 | SROMC_WAIT_EN | SROMC_BYTE_EN),
+	.size = CBP_EDPRAM_SIZE,
+};
+
+static struct sromc_access_cfg cbp_edpram_access_cfg[] = {
+	[DPRAM_SPEED_LOW] = {
+		.tacs = 0x2 << 28,
+		.tcos = 0x2 << 24,
+		.tacc = 0x3 << 16,
+		.tcoh = 0x2 << 12,
+		.tcah = 0x2 << 8,
+		.tacp = 0x2 << 4,
+		.pmc  = 0x0 << 0,
+	},
+};
+
+/*
+	magic_code +
+	access_enable +
+	fmt_tx_head + fmt_tx_tail + fmt_tx_buff +
+	raw_tx_head + raw_tx_tail + raw_tx_buff +
+	fmt_rx_head + fmt_rx_tail + fmt_rx_buff +
+	raw_rx_head + raw_rx_tail + raw_rx_buff +
+	padding +
+	mbx_cp2ap +
+	mbx_ap2cp
+ =	2 +
+	2 +
+	2 + 2 + 4092 +
+	2 + 2 + 12272 +
+	2 + 2 + 4092 +
+	2 + 2 + 12272 +
+	16 +
+	2 +
+	2
+ =	32768
+*/
+
+#define CBP_DP_FMT_TX_BUFF_SZ	4092
+#define CBP_DP_RAW_TX_BUFF_SZ	12272
+#define CBP_DP_FMT_RX_BUFF_SZ	4092
+#define CBP_DP_RAW_RX_BUFF_SZ	12272
+
+#define MAX_CBP_EDPRAM_IPC_DEV	2	/* FMT, RAW */
+
+struct cbp_edpram_ipc_cfg {
+	u16 magic;
+	u16 access;
+
+	u16 fmt_tx_head;
+	u16 fmt_tx_tail;
+	u8  fmt_tx_buff[CBP_DP_FMT_TX_BUFF_SZ];
+
+	u16 raw_tx_head;
+	u16 raw_tx_tail;
+	u8  raw_tx_buff[CBP_DP_RAW_TX_BUFF_SZ];
+
+	u16 fmt_rx_head;
+	u16 fmt_rx_tail;
+	u8  fmt_rx_buff[CBP_DP_FMT_RX_BUFF_SZ];
+
+	u16 raw_rx_head;
+	u16 raw_rx_tail;
+	u8  raw_rx_buff[CBP_DP_RAW_RX_BUFF_SZ];
+
+	u8  padding[16];
+	u16 mbx_ap2cp;
+	u16 mbx_cp2ap;
+};
+
+struct cbp_edpram_boot_map {
+	u8  __iomem *buff;
+	u16  __iomem *frame_size;
+	u16  __iomem *tag;
+	u16  __iomem *count;
+};
+
+static struct dpram_ipc_map cbp_ipc_map;
+
+struct _param_nv {
+	unsigned char *addr;
+	unsigned int size;
+	unsigned int count;
+	unsigned int tag;
+};
+
+/*
+------------------
+Buffer : 31KByte
+------------------
+Reserved: 1014Byte
+------------------
+SIZE: 2Byte
+------------------
+TAG: 2Byte
+------------------
+COUNT: 2Byte
+------------------
+AP -> CP Intr : 2Byte
+------------------
+CP -> AP Intr : 2Byte
+------------------
+*/
+#define DP_BOOT_CLEAR_OFFSET	4
+#define DP_BOOT_RSRVD_OFFSET	0x7C00
+#define DP_BOOT_SIZE_OFFSET	    0x7FF6
+#define DP_BOOT_TAG_OFFSET	    0x7FF8
+#define DP_BOOT_COUNT_OFFSET	0x7FFA
+
+
+#define DP_BOOT_FRAME_SIZE_LIMIT     0x7C00 /* 31KB = 31744byte = 0x7C00 */
+
+
+struct _param_check {
+	unsigned int total_size;
+	unsigned int rest_size;
+	unsigned int send_size;
+	unsigned int copy_start;
+	unsigned int copy_complete;
+	unsigned int boot_complete;
+};
+
+static struct _param_nv *data_param;
+static struct _param_check check_param;
+
+static unsigned int boot_start_complete;
+static struct cbp_edpram_boot_map cbp_edpram_bt_map;
+
+static void cbp_edpram_reset(void);
+static void cbp_edpram_clr_intr(void);
+static u16  cbp_edpram_recv_intr(void);
+static void cbp_edpram_send_intr(u16 irq_mask);
+static u16  cbp_edpram_recv_msg(void);
+static void cbp_edpram_send_msg(u16 msg);
+
+static u16  cbp_edpram_get_magic(void);
+static void cbp_edpram_set_magic(u16 value);
+static u16  cbp_edpram_get_access(void);
+static void cbp_edpram_set_access(u16 value);
+
+static u32  cbp_edpram_get_tx_head(int dev_id);
+static u32  cbp_edpram_get_tx_tail(int dev_id);
+static void cbp_edpram_set_tx_head(int dev_id, u32 head);
+static void cbp_edpram_set_tx_tail(int dev_id, u32 tail);
+static u8 __iomem *cbp_edpram_get_tx_buff(int dev_id);
+static u32  cbp_edpram_get_tx_buff_size(int dev_id);
+
+static u32  cbp_edpram_get_rx_head(int dev_id);
+static u32  cbp_edpram_get_rx_tail(int dev_id);
+static void cbp_edpram_set_rx_head(int dev_id, u32 head);
+static void cbp_edpram_set_rx_tail(int dev_id, u32 tail);
+static u8 __iomem *cbp_edpram_get_rx_buff(int dev_id);
+static u32  cbp_edpram_get_rx_buff_size(int dev_id);
+
+static u16  cbp_edpram_get_mask_req_ack(int dev_id);
+static u16  cbp_edpram_get_mask_res_ack(int dev_id);
+static u16  cbp_edpram_get_mask_send(int dev_id);
+
+static void msm_vbus_on(void);
+static void msm_vbus_off(void);
+
+static void mdm_log_disp(struct modemlink_dpram_control *dpctl);
+static int mdm_uload_step1(struct modemlink_dpram_control *dpctl);
+static int mdm_uload_step2(void *arg, struct modemlink_dpram_control *dpctl);
+static int mdm_dload_prep(struct modemlink_dpram_control *dpctl);
+static int mdm_dload(void *arg, struct modemlink_dpram_control *dpctl);
+static int mdm_nv_load(void *arg, struct modemlink_dpram_control *dpctl);
+static int mdm_boot_start(struct modemlink_dpram_control *dpctl);
+static int mdm_boot_start_post_proc(void);
+static void mdm_boot_start_handler(struct modemlink_dpram_control *dpctl);
+static void mdm_dload_handler(struct modemlink_dpram_control *dpctl, u16 cmd);
+static void mdm_bt_map_init(struct modemlink_dpram_control *dpctl);
+static void mdm_load_init(struct modemlink_dpram_control *dpctl);
+
+static struct modemlink_dpram_control cbp_edpram_ctrl = {
+	.reset      = cbp_edpram_reset,
+
+	.clear_intr = cbp_edpram_clr_intr,
+	.recv_intr  = cbp_edpram_recv_intr,
+	.send_intr  = cbp_edpram_send_intr,
+	.recv_msg   = cbp_edpram_recv_msg,
+	.send_msg   = cbp_edpram_send_msg,
+
+	.get_magic  = cbp_edpram_get_magic,
+	.set_magic  = cbp_edpram_set_magic,
+	.get_access = cbp_edpram_get_access,
+	.set_access = cbp_edpram_set_access,
+
+	.get_tx_head = cbp_edpram_get_tx_head,
+	.get_tx_tail = cbp_edpram_get_tx_tail,
+	.set_tx_head = cbp_edpram_set_tx_head,
+	.set_tx_tail = cbp_edpram_set_tx_tail,
+	.get_tx_buff = cbp_edpram_get_tx_buff,
+	.get_tx_buff_size = cbp_edpram_get_tx_buff_size,
+
+	.get_rx_head = cbp_edpram_get_rx_head,
+	.get_rx_tail = cbp_edpram_get_rx_tail,
+	.set_rx_head = cbp_edpram_set_rx_head,
+	.set_rx_tail = cbp_edpram_set_rx_tail,
+	.get_rx_buff = cbp_edpram_get_rx_buff,
+	.get_rx_buff_size = cbp_edpram_get_rx_buff_size,
+
+	.get_mask_req_ack = cbp_edpram_get_mask_req_ack,
+	.get_mask_res_ack = cbp_edpram_get_mask_res_ack,
+	.get_mask_send    = cbp_edpram_get_mask_send,
+
+	.log_disp          = mdm_log_disp,
+	.cpupload_step1    = mdm_uload_step1,
+	.cpupload_step2    = mdm_uload_step2,
+	.cpimage_load_prepare	  = mdm_dload_prep,
+	.cpimage_load    = mdm_dload,
+	.nvdata_load    = mdm_nv_load,
+	.phone_boot_start    = mdm_boot_start,
+	.phone_boot_start_post_process    = mdm_boot_start_post_proc,
+	.phone_boot_start_handler         = mdm_boot_start_handler,
+	.dload_cmd_hdlr    = mdm_dload_handler,
+	.bt_map_init	  = mdm_bt_map_init,
+	.load_init    = mdm_load_init,
+
+	.dp_base = NULL,
+	.dp_size = 0,
+	.dp_type = EXT_DPRAM,
+
+	.dpram_irq        = IRQ_EINT(8),
+	.dpram_irq_flags  = IRQF_TRIGGER_FALLING,
+	.dpram_irq_name   = "MDM6600_EDPRAM_IRQ",
+	.dpram_wlock_name = "MDM6600_EDPRAM_WLOCK",
+
+	.max_ipc_dev = IPC_RFS,
+};
+
+/*
+** CDMA target platform data
+*/
+static struct modem_io_t cdma_io_devices[] = {
+	[0] = {
+		.name = "cdma_boot0",
+		.id = 0x1,
+		.format = IPC_BOOT,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[1] = {
+		.name = "cdma_ipc0",
+		.id = 0x1,
+		.format = IPC_FMT,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[2] = {
+		.name = "cdma_multipdp",
+		.id = 0x1,
+		.format = IPC_MULTI_RAW,
+		.io_type = IODEV_DUMMY,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[3] = {
+		.name = "cdma_CSD",
+		.id = (1|0x20),
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[4] = {
+		.name = "cdma_FOTA",
+		.id = (2|0x20),
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[5] = {
+		.name = "cdma_GPS",
+		.id = (5|0x20),
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[6] = {
+		.name = "cdma_XTRA",
+		.id = (6|0x20),
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[7] = {
+		.name = "cdma_CDMA",
+		.id = (7|0x20),
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[8] = {
+		.name = "cdma_EFS",
+		.id = (8|0x20),
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[9] = {
+		.name = "cdma_TRFB",
+		.id = (9|0x20),
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[10] = {
+		.name = "rmnet0",
+		.id = 0x2A,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[11] = {
+		.name = "rmnet1",
+		.id = 0x2B,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[12] = {
+		.name = "rmnet2",
+		.id = 0x2C,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[13] = {
+		.name = "rmnet3",
+		.id = 0x2D,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[14] = {
+		.name = "cdma_SMD",
+		.id = (25|0x20),
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[15] = {
+		.name = "cdma_VTVD",
+		.id = (26|0x20),
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[16] = {
+		.name = "cdma_VTAD",
+		.id = (27|0x20),
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[17] = {
+		.name = "cdma_VTCTRL",
+		.id = (28|0x20),
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[18] = {
+		.name = "cdma_VTENT",
+		.id = (29|0x20),
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[19] = {
+		.name = "cdma_ramdump0",
+		.id = 0x1,
+		.format = IPC_RAMDUMP,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+	[20] = {
+		.name = "umts_loopback0",
+		.id = (31|0x20),
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_DPRAM),
+	},
+};
+
+static struct modem_data cdma_modem_data = {
+	.name = "mdm6600",
+
+	.gpio_cp_on = GPIO_PHONE_ON,
+	.gpio_cp_reset = GPIO_CP_RST,
+	.gpio_pda_active = GPIO_PDA_ACTIVE,
+	.gpio_phone_active = GPIO_PHONE_ACTIVE,
+	.gpio_cp_reset_msm = GPIO_CP_RST_MSM,
+	.gpio_boot_sw_sel = GPIO_BOOT_SW_SEL,
+	.vbus_on = msm_vbus_on,
+	.vbus_off = msm_vbus_off,
+	.cp_vbus = NULL,
+	.gpio_cp_dump_int   = 0,
+	.gpio_cp_warm_reset = 0,
+
+	.modem_net = CDMA_NETWORK,
+	.modem_type = QC_MDM6600,
+	.link_types = LINKTYPE(LINKDEV_DPRAM),
+	.link_name  = "mdm6600_edpram",
+	.dpram_ctl  = &cbp_edpram_ctrl,
+
+	.num_iodevs = ARRAY_SIZE(cdma_io_devices),
+	.iodevs = cdma_io_devices,
+
+	.use_handover = false,
+
+	.ipc_version = SIPC_VER_41,
+};
+
+static struct resource cdma_modem_res[] = {
+	[0] = {
+		.name  = "cp_active_irq",
+		.start = IRQ_EINT(14),
+		.end   = IRQ_EINT(14),
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device cdma_modem = {
+	.name = "modem_if",
+	.id = 2,
+	.num_resources = ARRAY_SIZE(cdma_modem_res),
+	.resource = cdma_modem_res,
+	.dev = {
+		.platform_data = &cdma_modem_data,
+	},
+};
+
+static void cbp_edpram_reset(void)
+{
+	return;
+}
+
+static void cbp_edpram_clr_intr(void)
+{
+	ioread16(cbp_ipc_map.mbx_cp2ap);
+}
+
+static u16 cbp_edpram_recv_intr(void)
+{
+	return ioread16(cbp_ipc_map.mbx_cp2ap);
+}
+
+static void cbp_edpram_send_intr(u16 irq_mask)
+{
+	iowrite16(irq_mask, cbp_ipc_map.mbx_ap2cp);
+}
+
+static u16 cbp_edpram_recv_msg(void)
+{
+	return ioread16(cbp_ipc_map.mbx_cp2ap);
+}
+
+static void cbp_edpram_send_msg(u16 msg)
+{
+	iowrite16(msg, cbp_ipc_map.mbx_ap2cp);
+}
+
+static u16 cbp_edpram_get_magic(void)
+{
+	return ioread16(cbp_ipc_map.magic);
+}
+
+static void cbp_edpram_set_magic(u16 value)
+{
+	iowrite16(value, cbp_ipc_map.magic);
+}
+
+static u16 cbp_edpram_get_access(void)
+{
+	return ioread16(cbp_ipc_map.access);
+}
+
+static void cbp_edpram_set_access(u16 value)
+{
+	iowrite16(value, cbp_ipc_map.access);
+}
+
+static u32 cbp_edpram_get_tx_head(int dev_id)
+{
+	return ioread16(cbp_ipc_map.dev[dev_id].txq.head);
+}
+
+static u32 cbp_edpram_get_tx_tail(int dev_id)
+{
+	return ioread16(cbp_ipc_map.dev[dev_id].txq.tail);
+}
+
+static void cbp_edpram_set_tx_head(int dev_id, u32 head)
+{
+	iowrite16((u16)head, cbp_ipc_map.dev[dev_id].txq.head);
+}
+
+static void cbp_edpram_set_tx_tail(int dev_id, u32 tail)
+{
+	iowrite16((u16)tail, cbp_ipc_map.dev[dev_id].txq.tail);
+}
+
+static u8 __iomem *cbp_edpram_get_tx_buff(int dev_id)
+{
+	return cbp_ipc_map.dev[dev_id].txq.buff;
+}
+
+static u32 cbp_edpram_get_tx_buff_size(int dev_id)
+{
+	return cbp_ipc_map.dev[dev_id].txq.size;
+}
+
+static u32 cbp_edpram_get_rx_head(int dev_id)
+{
+	return ioread16(cbp_ipc_map.dev[dev_id].rxq.head);
+}
+
+static u32 cbp_edpram_get_rx_tail(int dev_id)
+{
+	return ioread16(cbp_ipc_map.dev[dev_id].rxq.tail);
+}
+
+static void cbp_edpram_set_rx_head(int dev_id, u32 head)
+{
+	return iowrite16((u16)head, cbp_ipc_map.dev[dev_id].rxq.head);
+}
+
+static void cbp_edpram_set_rx_tail(int dev_id, u32 tail)
+{
+	return iowrite16((u16)tail, cbp_ipc_map.dev[dev_id].rxq.tail);
+}
+
+static u8 __iomem *cbp_edpram_get_rx_buff(int dev_id)
+{
+	return cbp_ipc_map.dev[dev_id].rxq.buff;
+}
+
+static u32 cbp_edpram_get_rx_buff_size(int dev_id)
+{
+	return cbp_ipc_map.dev[dev_id].rxq.size;
+}
+
+static u16 cbp_edpram_get_mask_req_ack(int dev_id)
+{
+	return cbp_ipc_map.dev[dev_id].mask_req_ack;
+}
+
+static u16 cbp_edpram_get_mask_res_ack(int dev_id)
+{
+	return cbp_ipc_map.dev[dev_id].mask_res_ack;
+}
+
+static u16 cbp_edpram_get_mask_send(int dev_id)
+{
+	return cbp_ipc_map.dev[dev_id].mask_send;
+}
+
+static void msm_vbus_on(void)
+{
+	int err;
+
+	if (system_rev >= 0x06) {
+#ifdef GPIO_USB_BOOT_EN
+		pr_info("%s : set USB_BOOT_EN\n", __func__);
+		gpio_request(GPIO_USB_BOOT_EN, "USB_BOOT_EN");
+		gpio_direction_output(GPIO_USB_BOOT_EN, 1);
+		gpio_free(GPIO_USB_BOOT_EN);
+#endif
+	} else {
+#ifdef GPIO_USB_OTG_EN
+		gpio_request(GPIO_USB_OTG_EN, "USB_OTG_EN");
+		gpio_direction_output(GPIO_USB_OTG_EN, 1);
+		gpio_free(GPIO_USB_OTG_EN);
+#endif
+	}
+	mdelay(10);
+
+	if (!cdma_modem_data.cp_vbus) {
+		cdma_modem_data.cp_vbus = regulator_get(NULL, "safeout2");
+		if (IS_ERR(cdma_modem_data.cp_vbus)) {
+			err = PTR_ERR(cdma_modem_data.cp_vbus);
+			pr_err(" <%s> regualtor: %d\n", __func__, err);
+			cdma_modem_data.cp_vbus = NULL;
+		}
+	}
+
+	if (cdma_modem_data.cp_vbus) {
+		pr_info("%s\n", __func__);
+		regulator_enable(cdma_modem_data.cp_vbus);
+	}
+}
+
+static void msm_vbus_off(void)
+{
+	if (cdma_modem_data.cp_vbus) {
+		pr_info("%s\n", __func__);
+		regulator_disable(cdma_modem_data.cp_vbus);
+	}
+
+	if (system_rev >= 0x06) {
+#ifdef GPIO_USB_BOOT_EN
+		gpio_request(GPIO_USB_BOOT_EN, "USB_BOOT_EN");
+		gpio_direction_output(GPIO_USB_BOOT_EN, 0);
+		gpio_free(GPIO_USB_BOOT_EN);
+#endif
+	} else {
+#ifdef GPIO_USB_OTG_EN
+		gpio_request(GPIO_USB_OTG_EN, "USB_OTG_EN");
+		gpio_direction_output(GPIO_USB_OTG_EN, 0);
+		gpio_free(GPIO_USB_OTG_EN);
+#endif
+	}
+
+}
+
+static void mdm_log_disp(struct modemlink_dpram_control *dpctl)
+{
+	static unsigned char buf[151];
+	u8 __iomem *tmp_buff = NULL;
+
+	tmp_buff = dpctl->get_rx_buff(IPC_FMT);
+	memcpy(buf, tmp_buff, (sizeof(buf)-1));
+
+	pr_info("[LNK] | PHONE ERR MSG\t| CDMA Crash\n");
+	pr_info("[LNK] | PHONE ERR MSG\t| %s\n", buf);
+}
+
+static int mdm_data_upload(struct _param_nv *param,
+	struct modemlink_dpram_control *dpctl)
+{
+	int retval = 0;
+	u16 in_interrupt = 0;
+	int count = 0;
+
+	while (1) {
+		if (!gpio_get_value(GPIO_DPRAM_INT_N)) {
+			in_interrupt = dpctl->recv_msg();
+			if (in_interrupt == 0xDBAB) {
+				break;
+			} else {
+				pr_err("[LNK][intr]:0x%08x\n", in_interrupt);
+				pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+				return -1;
+			}
+		}
+		msleep_interruptible(1);
+		count++;
+		if (count > 200) {
+			pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+			return -1;
+		}
+	}
+
+	param->size = ioread16(cbp_edpram_bt_map.frame_size);
+	memcpy(param->addr, cbp_edpram_bt_map.buff, param->size);
+	param->tag = ioread16(cbp_edpram_bt_map.tag);
+	param->count = ioread16(cbp_edpram_bt_map.count);
+
+	dpctl->clear_intr();
+	dpctl->send_msg(0xDB12);
+
+	return retval;
+
+}
+
+static int mdm_data_load(struct _param_nv *param,
+	struct modemlink_dpram_control *dpctl)
+{
+	int retval = 0;
+
+	if (param->size <= DP_BOOT_FRAME_SIZE_LIMIT) {
+		memcpy(cbp_edpram_bt_map.buff, param->addr, param->size);
+		iowrite16(param->size, cbp_edpram_bt_map.frame_size);
+		iowrite16(param->tag, cbp_edpram_bt_map.tag);
+		iowrite16(param->count, cbp_edpram_bt_map.count);
+
+		dpctl->clear_intr();
+		dpctl->send_msg(0xDB12);
+
+	} else {
+		pr_err("[LNK/E]<%s> size:0x%x\n", __func__, param->size);
+	}
+
+	return retval;
+}
+
+static int mdm_uload_step1(struct modemlink_dpram_control *dpctl)
+{
+	int retval = 0;
+	int count = 0;
+	u16 in_interrupt = 0, out_interrupt = 0;
+
+	pr_info("[LNK] +---------------------------------------------+\n");
+	pr_info("[LNK] |            UPLOAD PHONE SDRAM               |\n");
+	pr_info("[LNK] +---------------------------------------------+\n");
+
+	while (1) {
+		if (!gpio_get_value(GPIO_DPRAM_INT_N)) {
+			in_interrupt = dpctl->recv_msg();
+			pr_info("[LNK] [in_interrupt] 0x%04x\n", in_interrupt);
+			if (in_interrupt == 0x1234) {
+				break;
+			} else {
+				pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+				return -1;
+			}
+		}
+		msleep_interruptible(1);
+		count++;
+		if (count > 200) {
+			pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+			in_interrupt = dpctl->recv_msg();
+			if (in_interrupt == 0x1234) {
+				pr_info("[LNK] [in_interrupt]: 0x%04x\n",
+							in_interrupt);
+				break;
+			}
+			return -1;
+		}
+	}
+	out_interrupt = 0xDEAD;
+	dpctl->send_msg(out_interrupt);
+
+	return retval;
+}
+
+static int mdm_uload_step2(void *arg,
+					struct modemlink_dpram_control *dpctl)
+{
+	int retval = 0;
+	struct _param_nv param;
+
+	retval = copy_from_user((void *)&param, (void *)arg, sizeof(param));
+	if (retval < 0) {
+		pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+		return -1;
+	}
+
+	retval = mdm_data_upload(&param, dpctl);
+	if (retval < 0) {
+		pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+		return -1;
+	}
+
+	if (!(param.count % 500))
+		pr_info("[LNK] [param->count]:%d\n", param.count);
+
+	if (param.tag == 4) {
+		dpctl->clear_intr();
+		enable_irq(cbp_edpram_ctrl.dpram_irq);
+		pr_info("[LNK] [param->tag]:%d\n", param.tag);
+	}
+
+	retval = copy_to_user((unsigned long *)arg, &param, sizeof(param));
+	if (retval < 0) {
+		pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+		return -1;
+	}
+
+	return retval;
+}
+
+static int mdm_dload_prep(struct modemlink_dpram_control *dpctl)
+{
+	int retval = 0;
+	int count = 0;
+
+	while (1) {
+		if (check_param.copy_start) {
+			check_param.copy_start = 0;
+			break;
+		}
+		msleep_interruptible(10);
+		count++;
+		if (count > 200) {
+			pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+			return -1;
+		}
+	}
+
+	return retval;
+}
+
+static int mdm_dload(void *arg, struct modemlink_dpram_control *dpctl)
+{
+	int retval = 0;
+	int count = 0;
+	unsigned char *img = NULL;
+	struct _param_nv param;
+
+	retval = copy_from_user((void *)&param, (void *)arg, sizeof(param));
+	if (retval < 0) {
+		pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+		return -1;
+	}
+
+	img = vmalloc(param.size);
+	if (img == NULL) {
+		pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+		return -1;
+	}
+	memset(img, 0, param.size);
+	memcpy(img, param.addr, param.size);
+
+	data_param = kzalloc(sizeof(struct _param_nv), GFP_KERNEL);
+	if (data_param == NULL)	{
+		pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+		vfree(img);
+		return -1;
+	}
+
+	check_param.total_size = param.size;
+	check_param.rest_size = param.size;
+	check_param.send_size = 0;
+	check_param.copy_complete = 0;
+
+	data_param->addr = img;
+	data_param->size = DP_BOOT_FRAME_SIZE_LIMIT;
+	data_param->count = param.count;
+	data_param->tag = param.tag;
+
+	if (check_param.rest_size < DP_BOOT_FRAME_SIZE_LIMIT)
+		data_param->size = check_param.rest_size;
+
+	retval = mdm_data_load(data_param, dpctl);
+
+	while (1) {
+		if (check_param.copy_complete) {
+			check_param.copy_complete = 0;
+
+			vfree(img);
+			kfree(data_param);
+
+			break;
+		}
+		msleep_interruptible(10);
+		count++;
+		if (count > 2000) {
+			pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+			vfree(img);
+			kfree(data_param);
+			return -1;
+		}
+	}
+
+	return retval;
+
+}
+
+static int mdm_nv_load(void *arg, struct modemlink_dpram_control *dpctl)
+{
+	int retval = 0;
+	int count = 0;
+	unsigned char *img = NULL;
+	struct _param_nv param;
+
+	retval = copy_from_user((void *)&param, (void *)arg, sizeof(param));
+	if (retval < 0) {
+		pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+		return -1;
+	}
+
+	img = vmalloc(param.size);
+	if (img == NULL) {
+		pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+		return -1;
+	}
+	memset(img, 0, param.size);
+	memcpy(img, param.addr, param.size);
+
+	data_param = kzalloc(sizeof(struct _param_nv), GFP_KERNEL);
+	if (data_param == NULL) {
+		pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+		vfree(img);
+		return -1;
+	}
+
+	check_param.total_size = param.size;
+	check_param.rest_size = param.size;
+	check_param.send_size = 0;
+	check_param.copy_complete = 0;
+
+	data_param->addr = img;
+	data_param->size = DP_BOOT_FRAME_SIZE_LIMIT;
+	data_param->count = param.count;
+	data_param->tag = param.tag;
+
+	if (check_param.rest_size < DP_BOOT_FRAME_SIZE_LIMIT)
+		data_param->size = check_param.rest_size;
+
+	retval = mdm_data_load(data_param, dpctl);
+
+	while (1) {
+		if (check_param.copy_complete) {
+			check_param.copy_complete = 0;
+
+			vfree(img);
+			kfree(data_param);
+
+			break;
+		}
+		msleep_interruptible(10);
+		count++;
+		if (count > 200) {
+			pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+			vfree(img);
+			kfree(data_param);
+			return -1;
+		}
+	}
+
+	return retval;
+
+}
+
+static int mdm_boot_start(struct modemlink_dpram_control *dpctl)
+{
+
+	u16 out_interrupt = 0;
+	int count = 0;
+
+	/* Send interrupt -> '0x4567' */
+	out_interrupt = 0x4567;
+	dpctl->send_msg(out_interrupt);
+
+	while (1) {
+		if (check_param.boot_complete) {
+			check_param.boot_complete = 0;
+			break;
+		}
+		msleep_interruptible(10);
+		count++;
+		if (count > 200) {
+			pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+			return -1;
+		}
+	}
+
+	return 0;
+}
+
+static struct modemlink_dpram_control *tasklet_dpctl;
+
+static void interruptable_load_tasklet_handler(unsigned long data);
+
+static DECLARE_TASKLET(interruptable_load_tasklet,
+	interruptable_load_tasklet_handler, (unsigned long) &tasklet_dpctl);
+
+static void interruptable_load_tasklet_handler(unsigned long data)
+{
+	struct modemlink_dpram_control *dpctl =
+		(struct modemlink_dpram_control *)
+		(*((struct modemlink_dpram_control **) data));
+
+	if (data_param == NULL) {
+		pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+		return;
+	}
+
+	check_param.send_size += data_param->size;
+	check_param.rest_size -= data_param->size;
+	data_param->addr += data_param->size;
+
+	if (check_param.send_size < check_param.total_size) {
+
+		if (check_param.rest_size < DP_BOOT_FRAME_SIZE_LIMIT)
+			data_param->size = check_param.rest_size;
+
+
+		data_param->count += 1;
+
+		mdm_data_load(data_param, dpctl);
+	} else {
+		data_param->tag = 0;
+		check_param.copy_complete = 1;
+	}
+
+}
+
+static int mdm_boot_start_post_proc(void)
+{
+	int count = 0;
+
+	while (1) {
+		if (boot_start_complete) {
+			boot_start_complete = 0;
+			break;
+		}
+		msleep_interruptible(10);
+		count++;
+		if (count > 200) {
+			pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__);
+			return -1;
+		}
+	}
+
+	return 0;
+}
+
+static void mdm_boot_start_handler(struct modemlink_dpram_control *dpctl)
+{
+	boot_start_complete = 1;
+
+	/* Send INIT_END code to CP */
+	pr_info("[LNK] <%s> Send 0x11C2 (INIT_END)\n", __func__);
+
+	/*
+	 * INT_MASK_VALID|INT_MASK_CMD|INT_MASK_CP_AIRPLANE_BOOT|
+	 * INT_MASK_CP_AP_ANDROID|INT_MASK_CMD_INIT_END
+	 */
+	dpctl->send_intr((0x0080|0x0040|0x1000|0x0100|0x0002));
+}
+
+static void mdm_dload_handler(struct modemlink_dpram_control *dpctl, u16 cmd)
+{
+	switch (cmd) {
+	case 0x1234:
+		check_param.copy_start = 1;
+		break;
+
+	case 0xDBAB:
+		tasklet_schedule(&interruptable_load_tasklet);
+		break;
+
+	case 0xABCD:
+		check_param.boot_complete = 1;
+		break;
+
+	default:
+		pr_err("[LNK/Err] <%s> Unknown command.. %x\n", __func__, cmd);
+	}
+}
+
+static void mdm_bt_map_init(struct modemlink_dpram_control *dpctl)
+{
+	cbp_edpram_bt_map.buff = (u8 *)(dpctl->dp_base);
+	cbp_edpram_bt_map.frame_size  =
+		(u16 *)(dpctl->dp_base + DP_BOOT_SIZE_OFFSET);
+	cbp_edpram_bt_map.tag =
+		(u16 *)(dpctl->dp_base + DP_BOOT_TAG_OFFSET);
+	cbp_edpram_bt_map.count =
+		(u16 *)(dpctl->dp_base + DP_BOOT_COUNT_OFFSET);
+}
+
+
+static void mdm_load_init(struct modemlink_dpram_control *dpctl)
+{
+	tasklet_dpctl = dpctl;
+	if (tasklet_dpctl == NULL)
+		pr_err("[LNK/Err] failed tasklet_dpctl remap\n");
+
+	check_param.total_size = 0;
+	check_param.rest_size = 0;
+	check_param.send_size = 0;
+	check_param.copy_start = 0;
+	check_param.copy_complete = 0;
+	check_param.boot_complete = 0;
+
+	dpctl->clear_intr();
+}
+
+static void config_cdma_modem_gpio(void)
+{
+	int err;
+
+	unsigned gpio_cp_on = cdma_modem_data.gpio_cp_on;
+	unsigned gpio_cp_rst = cdma_modem_data.gpio_cp_reset;
+	unsigned gpio_pda_active = cdma_modem_data.gpio_pda_active;
+	unsigned gpio_phone_active = cdma_modem_data.gpio_phone_active;
+	unsigned gpio_cp_reset_msm = cdma_modem_data.gpio_cp_reset_msm;
+	unsigned gpio_boot_sw_sel = cdma_modem_data.gpio_boot_sw_sel;
+
+	pr_info("[MDM] <%s>\n", __func__);
+
+	if (gpio_cp_on) {
+		err = gpio_request(gpio_cp_on, "CP_ON");
+		if (err) {
+			printk(KERN_ERR "fail to request gpio %s : %d\n",
+				   "CP_ON", err);
+		}
+		gpio_direction_output(gpio_cp_on, 0);
+	}
+
+	if (gpio_cp_rst) {
+		err = gpio_request(gpio_cp_rst, "CP_RST");
+		if (err) {
+			printk(KERN_ERR "fail to request gpio %s : %d\n",
+				   "CP_RST", err);
+		}
+		gpio_direction_output(gpio_cp_rst, 0);
+		s3c_gpio_setpull(gpio_cp_rst, S3C_GPIO_PULL_NONE);
+	}
+
+	if (gpio_cp_reset_msm) {
+		err = gpio_request(gpio_cp_reset_msm, "CP_RST_MSM");
+		if (err) {
+			printk(KERN_ERR "fail to request gpio %s : %d\n",
+				   "CP_RST_MSM", err);
+		}
+		gpio_direction_output(gpio_cp_reset_msm, 0);
+		s3c_gpio_cfgpin(gpio_cp_reset_msm, S3C_GPIO_SFN(0x1));
+		s3c_gpio_setpull(gpio_cp_reset_msm, S3C_GPIO_PULL_NONE);
+	}
+
+	if (gpio_boot_sw_sel) {
+		err = gpio_request(gpio_boot_sw_sel, "BOOT_SW_SEL");
+		if (err) {
+			printk(KERN_ERR "fail to request gpio %s : %d\n",
+				   "BOOT_SW_SEL", err);
+		}
+		gpio_direction_output(gpio_boot_sw_sel, 0);
+		s3c_gpio_setpull(gpio_boot_sw_sel, S3C_GPIO_PULL_NONE);
+	}
+
+	if (gpio_pda_active) {
+		err = gpio_request(gpio_pda_active, "PDA_ACTIVE");
+		if (err) {
+			printk(KERN_ERR "fail to request gpio %s : %d\n",
+				   "PDA_ACTIVE", err);
+		}
+		gpio_direction_output(gpio_pda_active, 0);
+	}
+
+	if (gpio_phone_active) {
+		err = gpio_request(gpio_phone_active, "PHONE_ACTIVE");
+		if (err) {
+			printk(KERN_ERR "fail to request gpio %s : %d\n",
+				   "PHONE_ACTIVE", err);
+		}
+		gpio_direction_input(gpio_phone_active);
+		s3c_gpio_cfgpin(gpio_phone_active, S3C_GPIO_SFN(0xF));
+		s3c_gpio_setpull(gpio_phone_active, S3C_GPIO_PULL_NONE);
+	}
+
+	printk(KERN_INFO "<%s> done\n", __func__);
+}
+
+
+static u8 *cbp_edpram_remap_mem_region(struct sromc_cfg *cfg)
+{
+	int			      dp_addr = 0;
+	int			      dp_size = 0;
+	u8 __iomem                   *dp_base = NULL;
+	struct cbp_edpram_ipc_cfg    *ipc_map = NULL;
+	struct dpram_ipc_device *dev = NULL;
+
+	dp_addr = cfg->addr;
+	dp_size = cfg->size;
+	dp_base = (u8 *)ioremap_nocache(dp_addr, dp_size);
+	if (!dp_base) {
+		pr_err("[MDM] <%s> dpram base ioremap fail\n", __func__);
+		return NULL;
+	}
+	pr_info("[MDM] <%s> DPRAM VA=0x%08X\n", __func__, (int)dp_base);
+
+	cbp_edpram_ctrl.dp_base = (u8 __iomem *)dp_base;
+	cbp_edpram_ctrl.dp_size = dp_size;
+
+	/* Map for IPC */
+	ipc_map = (struct cbp_edpram_ipc_cfg *)dp_base;
+
+	/* Magic code and access enable fields */
+	cbp_ipc_map.magic  = (u16 __iomem *)&ipc_map->magic;
+	cbp_ipc_map.access = (u16 __iomem *)&ipc_map->access;
+
+	/* FMT */
+	dev = &cbp_ipc_map.dev[IPC_FMT];
+
+	strcpy(dev->name, "FMT");
+	dev->id = IPC_FMT;
+
+	dev->txq.head = (u16 __iomem *)&ipc_map->fmt_tx_head;
+	dev->txq.tail = (u16 __iomem *)&ipc_map->fmt_tx_tail;
+	dev->txq.buff = (u8 __iomem *)&ipc_map->fmt_tx_buff[0];
+	dev->txq.size = CBP_DP_FMT_TX_BUFF_SZ;
+
+	dev->rxq.head = (u16 __iomem *)&ipc_map->fmt_rx_head;
+	dev->rxq.tail = (u16 __iomem *)&ipc_map->fmt_rx_tail;
+	dev->rxq.buff = (u8 __iomem *)&ipc_map->fmt_rx_buff[0];
+	dev->rxq.size = CBP_DP_FMT_RX_BUFF_SZ;
+
+	dev->mask_req_ack = INT_MASK_REQ_ACK_F;
+	dev->mask_res_ack = INT_MASK_RES_ACK_F;
+	dev->mask_send    = INT_MASK_SEND_F;
+
+	/* RAW */
+	dev = &cbp_ipc_map.dev[IPC_RAW];
+
+	strcpy(dev->name, "RAW");
+	dev->id = IPC_RAW;
+
+	dev->txq.head = (u16 __iomem *)&ipc_map->raw_tx_head;
+	dev->txq.tail = (u16 __iomem *)&ipc_map->raw_tx_tail;
+	dev->txq.buff = (u8 __iomem *)&ipc_map->raw_tx_buff[0];
+	dev->txq.size = CBP_DP_RAW_TX_BUFF_SZ;
+
+	dev->rxq.head = (u16 __iomem *)&ipc_map->raw_rx_head;
+	dev->rxq.tail = (u16 __iomem *)&ipc_map->raw_rx_tail;
+	dev->rxq.buff = (u8 __iomem *)&ipc_map->raw_rx_buff[0];
+	dev->rxq.size = CBP_DP_RAW_RX_BUFF_SZ;
+
+	dev->mask_req_ack = INT_MASK_REQ_ACK_R;
+	dev->mask_res_ack = INT_MASK_RES_ACK_R;
+	dev->mask_send    = INT_MASK_SEND_R;
+
+#if 0
+	/* RFS */
+	dev = &cbp_ipc_map.dev[IPC_RFS];
+
+	strcpy(dev->name, "RFS");
+	dev->id = IPC_RFS;
+
+	dev->txq.head = (u16 __iomem *)&ipc_map->rfs_tx_head;
+	dev->txq.tail = (u16 __iomem *)&ipc_map->rfs_tx_tail;
+	dev->txq.buff = (u8 __iomem *)&ipc_map->rfs_tx_buff[0];
+	dev->txq.size = CBP_DP_RFS_TX_BUFF_SZ;
+
+	dev->rxq.head = (u16 __iomem *)&ipc_map->rfs_rx_head;
+	dev->rxq.tail = (u16 __iomem *)&ipc_map->rfs_rx_tail;
+	dev->rxq.buff = (u8 __iomem *)&ipc_map->rfs_rx_buff[0];
+	dev->rxq.size = CBP_DP_RFS_RX_BUFF_SZ;
+
+	dev->mask_req_ack = INT_MASK_REQ_ACK_RFS;
+	dev->mask_res_ack = INT_MASK_RES_ACK_RFS;
+	dev->mask_send    = INT_MASK_SEND_RFS;
+#endif
+
+	/* Mailboxes */
+	cbp_ipc_map.mbx_ap2cp = (u16 __iomem *)&ipc_map->mbx_ap2cp;
+	cbp_ipc_map.mbx_cp2ap = (u16 __iomem *)&ipc_map->mbx_cp2ap;
+
+	return dp_base;
+}
+
+/**
+ *	DPRAM GPIO settings
+ *
+ *	SROM_NUM_ADDR_BITS value indicate the address line number or
+ *	the mux/demux dpram type. if you want to set mux mode, define the
+ *	SROM_NUM_ADDR_BITS to zero.
+ *
+ *	for CMC22x
+ *	CMC22x has 16KB + a SFR register address.
+ *	It used 14 bits (13bits for 16KB word address and 1 bit for SFR
+ *	register)
+ */
+static void config_dpram_port_gpio(void)
+{
+	int addr_bits = SROM_NUM_ADDR_BITS;
+
+	pr_info("[MDM] <%s> address line = %d bits\n", __func__, addr_bits);
+
+	/*
+	** Config DPRAM address/data GPIO pins
+	*/
+
+	/* Set GPIO for dpram address */
+	switch (addr_bits) {
+	case 0:
+		break;
+
+	case 13 ... 14:
+		s3c_gpio_cfgrange_nopull(EXYNOS4_GPY3(0), EXYNOS4_GPIO_Y3_NR,
+			S3C_GPIO_SFN(2));
+		s3c_gpio_cfgrange_nopull(EXYNOS4_GPY4(0),
+			addr_bits - EXYNOS4_GPIO_Y3_NR, S3C_GPIO_SFN(2));
+		pr_info("[MDM] <%s> last data gpio EXYNOS4_GPY4(0) ~ %d\n",
+			__func__, addr_bits - EXYNOS4_GPIO_Y3_NR);
+		break;
+
+	default:
+		pr_err("[MDM/E] <%s> Invalid addr_bits!!!\n", __func__);
+		return;
+	}
+
+	/* Set GPIO for dpram data - 16bit */
+	s3c_gpio_cfgrange_nopull(EXYNOS4_GPY5(0), 8, S3C_GPIO_SFN(2));
+	s3c_gpio_cfgrange_nopull(EXYNOS4_GPY6(0), 8, S3C_GPIO_SFN(2));
+
+	/* Setup SROMC CSn pins */
+	s3c_gpio_cfgpin(GPIO_DPRAM_CSN0, S3C_GPIO_SFN(2));
+
+	/* Config OEn, WEn */
+	s3c_gpio_cfgrange_nopull(GPIO_DPRAM_REN, 2, S3C_GPIO_SFN(2));
+
+	/* Config LBn, UBn */
+	s3c_gpio_cfgrange_nopull(GPIO_DPRAM_LBN, 2, S3C_GPIO_SFN(2));
+}
+
+static void init_sromc(void)
+{
+	struct clk *clk = NULL;
+
+	/* SROMC clk enable */
+	clk = clk_get(NULL, "sromc");
+	if (!clk) {
+		pr_err("[MDM/E] <%s> SROMC clock gate fail\n", __func__);
+		return;
+	}
+	clk_enable(clk);
+}
+
+static void setup_sromc
+(
+	unsigned csn,
+	struct sromc_cfg *cfg,
+	struct sromc_access_cfg *acc_cfg
+)
+{
+	unsigned bw = 0;
+	unsigned bc = 0;
+	void __iomem *bank_sfr = S5P_SROM_BC0 + (4 * csn);
+
+	pr_err("[MDM] <%s> SROMC settings for CS%d...\n", __func__, csn);
+
+	bw = __raw_readl(S5P_SROM_BW);
+	bc = __raw_readl(bank_sfr);
+	pr_err("[MDM] <%s> Old SROMC settings = BW(0x%08X), BC%d(0x%08X)\n",
+		__func__, bw, csn, bc);
+
+	/* Set the BW control field for the CSn */
+	bw &= ~(SROMC_MASK << (csn << 2));
+	bw |= (cfg->attr << (csn << 2));
+	writel(bw, S5P_SROM_BW);
+
+	/* Set SROMC memory access timing for the CSn */
+	bc = acc_cfg->tacs | acc_cfg->tcos | acc_cfg->tacc |
+	     acc_cfg->tcoh | acc_cfg->tcah | acc_cfg->tacp | acc_cfg->pmc;
+
+	writel(bc, bank_sfr);
+
+	/* Verify SROMC settings */
+	bw = __raw_readl(S5P_SROM_BW);
+	bc = __raw_readl(bank_sfr);
+	pr_err("[MDM] <%s> New SROMC settings = BW(0x%08X), BC%d(0x%08X)\n",
+		__func__, bw, csn, bc);
+}
+
+static int __init init_modem(void)
+{
+	struct sromc_cfg *cfg = NULL;
+	struct sromc_access_cfg *acc_cfg = NULL;
+
+	cbp_edpram_cfg.csn = 0;
+	cbp_edpram_ctrl.dpram_irq = IRQ_EINT(8);
+	cbp_edpram_cfg.addr = SROM_CS0_BASE + (SROM_WIDTH * cbp_edpram_cfg.csn);
+	cbp_edpram_cfg.end  = cbp_edpram_cfg.addr + cbp_edpram_cfg.size - 1;
+
+	config_dpram_port_gpio();
+	config_cdma_modem_gpio();
+
+	init_sromc();
+
+	cfg = &cbp_edpram_cfg;
+	acc_cfg = &cbp_edpram_access_cfg[DPRAM_SPEED_LOW];
+	setup_sromc(cfg->csn, cfg, acc_cfg);
+
+	if (!cbp_edpram_remap_mem_region(&cbp_edpram_cfg))
+		return -1;
+	platform_device_register(&cdma_modem);
+
+	return 0;
+}
+late_initcall(init_modem);
+/*device_initcall(init_modem);*/
diff --git a/arch/arm/mach-exynos/board-u1-modems.c b/arch/arm/mach-exynos/board-u1-modems.c
new file mode 100644
index 0000000..1b35070
--- /dev/null
+++ b/arch/arm/mach-exynos/board-u1-modems.c
@@ -0,0 +1,512 @@
+/* linux/arch/arm/mach-xxxx/board-midas-modems.c
+ * Copyright (C) 2010 Samsung Electronics. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+#include <linux/regulator/machine.h>
+
+#include <plat/gpio-cfg.h>
+
+#include <linux/platform_data/modem.h>
+#include <mach/sec_modem.h>
+#include <linux/interrupt.h>
+
+/* umts target platform data */
+static struct modem_io_t umts_io_devices[] = {
+	[0] = {
+		.name = "umts_ipc0",
+		.id = 0x1,
+		.format = IPC_FMT,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[1] = {
+		.name = "umts_rfs0",
+		.id = 0x41,
+		.format = IPC_RFS,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[2] = {
+		.name = "umts_boot0",
+		.id = 0x0,
+		.format = IPC_BOOT,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[3] = {
+		.name = "multipdp",
+		.id = 0x1,
+		.format = IPC_MULTI_RAW,
+		.io_type = IODEV_DUMMY,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[4] = {
+		.name = "rmnet0",
+		.id = 0x2A,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[5] = {
+		.name = "rmnet1",
+		.id = 0x2B,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[6] = {
+		.name = "rmnet2",
+		.id = 0x2C,
+		.format = IPC_RAW,
+		.io_type = IODEV_NET,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[7] = {
+		.name = "umts_router",
+		.id = 0x39,
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[8] = {
+		.name = "umts_csd",
+		.id = 0x21,
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[9] = {
+		.name = "umts_ramdump0",
+		.id = 0x0,
+		.format = IPC_RAMDUMP,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+	[10] = {
+		.name = "umts_loopback0",
+		.id = 0x3f,
+		.format = IPC_RAW,
+		.io_type = IODEV_MISC,
+		.links = LINKTYPE(LINKDEV_HSIC),
+	},
+};
+
+/* To get modem state, register phone active irq using resource */
+static struct resource umts_modem_res[] = {
+	[0] = {
+		.name = "umts_phone_active",
+		.start = IRQ_EINT14,	/* GPIO_PHONE_ACTIVE */
+		.end = IRQ_EINT14,	/* GPIO_PHONE_ACTIVE */
+		.flags = IORESOURCE_IRQ,
+	},
+	[1] = {
+		.name = "link_pm_hostwake",
+		.start = IRQ_EINT9,	/* GPIO_IPC_HOST_WAKEUP */
+		.end = IRQ_EINT9,		/* GPIO_IPC_HOST_WAKEUP */
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+static int umts_link_ldo_enble(bool enable)
+{
+	/* Exynos HSIC V1.2 LDO was controlled by kernel */
+	return 0;
+}
+
+
+static void xmm_gpio_revers_bias_clear(void);
+static void xmm_gpio_revers_bias_restore(void);
+
+
+static int umts_link_reconnect(void);
+static struct modemlink_pm_data modem_link_pm_data = {
+	.name = "link_pm",
+	.link_ldo_enable = umts_link_ldo_enble,
+	.gpio_link_enable = 0,
+	.gpio_link_active = GPIO_ACTIVE_STATE,
+	.gpio_link_hostwake = GPIO_IPC_HOST_WAKEUP,
+	.gpio_link_slavewake = GPIO_IPC_SLAVE_WAKEUP,
+	.link_reconnect = umts_link_reconnect,
+};
+
+static struct modemlink_pm_link_activectl active_ctl;
+
+static struct modem_data umts_modem_data = {
+	.name = "xmm6260",
+
+	.gpio_cp_on = GPIO_PHONE_ON,
+	.gpio_reset_req_n = GPIO_CP_REQ_RESET,
+	.gpio_cp_reset = GPIO_CP_RST,
+	.gpio_pda_active = GPIO_PDA_ACTIVE,
+	.gpio_phone_active = GPIO_PHONE_ACTIVE,
+	.gpio_cp_dump_int = GPIO_CP_DUMP_INT,
+	.gpio_flm_uart_sel = 0,
+	.gpio_cp_warm_reset = 0,
+#if defined(CONFIG_SIM_DETECT)
+	.gpio_sim_detect = GPIO_SIM_DETECT,
+#endif
+
+	.modem_type = IMC_XMM6260,
+	.link_types = LINKTYPE(LINKDEV_HSIC),
+	.modem_net = UMTS_NETWORK,
+	.use_handover = false,
+
+	.num_iodevs = ARRAY_SIZE(umts_io_devices),
+	.iodevs = umts_io_devices,
+
+	.link_pm_data = &modem_link_pm_data,
+	.gpio_revers_bias_clear = xmm_gpio_revers_bias_clear,
+	.gpio_revers_bias_restore = xmm_gpio_revers_bias_restore,
+
+};
+
+static void xmm_gpio_revers_bias_clear(void)
+{
+	gpio_direction_output(umts_modem_data.gpio_reset_req_n, 0);
+	gpio_direction_output(umts_modem_data.gpio_phone_active, 0);
+	gpio_direction_output(modem_link_pm_data.gpio_link_active, 0);
+	gpio_direction_output(modem_link_pm_data.gpio_link_slavewake, 0);
+	gpio_direction_output(modem_link_pm_data.gpio_link_hostwake, 0);
+	gpio_direction_output(umts_modem_data.gpio_cp_dump_int, 0);
+
+	if (umts_modem_data.gpio_sim_detect)
+		gpio_direction_output(umts_modem_data.gpio_sim_detect, 0);
+
+	msleep(20);
+}
+
+static void xmm_gpio_revers_bias_restore(void)
+{
+	unsigned gpio_link_hostwake = modem_link_pm_data.gpio_link_hostwake;
+	unsigned gpio_cp_dump_int = umts_modem_data.gpio_cp_dump_int;
+	unsigned gpio_sim_detect = umts_modem_data.gpio_sim_detect;
+
+	s3c_gpio_cfgpin(umts_modem_data.gpio_phone_active, S3C_GPIO_SFN(0xF));
+	gpio_direction_output(gpio_link_hostwake, 0);
+	s3c_gpio_cfgpin(gpio_link_hostwake, S3C_GPIO_SFN(0xF));
+	s3c_gpio_setpull(gpio_link_hostwake, S3C_GPIO_PULL_NONE);
+	irq_set_irq_type(gpio_to_irq(gpio_link_hostwake),
+			IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING);
+	enable_irq_wake(gpio_to_irq(gpio_link_hostwake));
+
+	gpio_direction_input(gpio_cp_dump_int);
+	/*
+	s3c_gpio_cfgpin(gpio_cp_dump_int, S3C_GPIO_SFN(0xF));
+	s3c_gpio_setpull(gpio_cp_dump_int, S3C_GPIO_PULL_DOWN);
+	irq_set_irq_type(gpio_to_irq(gpio_cp_dump_int),
+				IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING);
+	enable_irq_wake(gpio_to_irq(gpio_cp_dump_int));
+	*/
+
+	/* gpio_direction_input(mc->gpio_suspend_request); */
+
+	if (umts_modem_data.gpio_sim_detect) {
+		gpio_direction_output(gpio_sim_detect, 0);
+		s3c_gpio_cfgpin(gpio_sim_detect, S3C_GPIO_SFN(0xF));
+		s3c_gpio_setpull(gpio_sim_detect, S3C_GPIO_PULL_NONE);
+		irq_set_irq_type(gpio_to_irq(gpio_sim_detect),
+				IRQ_TYPE_EDGE_BOTH);
+		enable_irq_wake(gpio_to_irq(gpio_sim_detect));
+	}
+}
+
+/* HSIC specific function */
+void set_slave_wake(void)
+{
+	int spin = 20;
+	if (gpio_get_value(modem_link_pm_data.gpio_link_hostwake)) {
+		pr_info("[MODEM_IF]Slave Wake\n");
+		if (gpio_get_value(modem_link_pm_data.gpio_link_slavewake)) {
+			gpio_direction_output(
+			modem_link_pm_data.gpio_link_slavewake, 0);
+			mdelay(10);
+		}
+		gpio_direction_output(
+			modem_link_pm_data.gpio_link_slavewake, 1);
+	}
+}
+
+void set_host_states(struct platform_device *pdev, int type)
+{
+	int val = gpio_get_value(umts_modem_data.gpio_cp_reset);
+
+	if (!val) {
+		pr_info("CP not ready, Active State low\n");
+		return;
+	}
+
+	if (active_ctl.gpio_initialized) {
+		if (type)
+			set_slave_wake();
+		pr_err("[MODEM_IF]Active States =%d, %s\n", type, pdev->name);
+		gpio_direction_output(modem_link_pm_data.gpio_link_active,
+			type);
+	} else
+		active_ctl.gpio_request_host_active = 1;
+}
+
+void set_hsic_lpa_states(int states)
+{
+	int val = gpio_get_value(umts_modem_data.gpio_cp_reset);
+
+	mif_trace("\n");
+
+	if (val) {
+		switch (states) {
+		case STATE_HSIC_LPA_ENTER:
+			gpio_set_value(modem_link_pm_data.gpio_link_active, 0);
+			gpio_set_value(umts_modem_data.gpio_pda_active, 0);
+			pr_info(LOG_TAG "set hsic lpa enter: "
+				"active state (%d)" ", pda active (%d)\n",
+				gpio_get_value(
+					modem_link_pm_data.gpio_link_active),
+				gpio_get_value(umts_modem_data.gpio_pda_active)
+				);
+			break;
+		case STATE_HSIC_LPA_WAKE:
+			gpio_set_value(umts_modem_data.gpio_pda_active, 1);
+			pr_info(LOG_TAG "set hsic lpa wake: "
+				"pda active (%d)\n",
+				gpio_get_value(umts_modem_data.gpio_pda_active)
+				);
+			break;
+		case STATE_HSIC_LPA_PHY_INIT:
+			gpio_set_value(umts_modem_data.gpio_pda_active, 1);
+			gpio_set_value(modem_link_pm_data.gpio_link_slavewake,
+				1);
+			pr_info(LOG_TAG "set hsic lpa phy init: "
+				"slave wake-up (%d)\n",
+				gpio_get_value(
+					modem_link_pm_data.gpio_link_slavewake)
+				);
+			break;
+		}
+	}
+}
+
+int get_cp_active_state(void)
+{
+	return gpio_get_value(umts_modem_data.gpio_phone_active);
+}
+
+static int umts_link_reconnect(void)
+{
+	if (gpio_get_value(umts_modem_data.gpio_phone_active) &&
+		gpio_get_value(umts_modem_data.gpio_cp_reset)) {
+		pr_info("[MODEM_IF] trying reconnect link\n");
+		gpio_set_value(modem_link_pm_data.gpio_link_active, 0);
+		mdelay(10);
+		set_slave_wake();
+		gpio_set_value(modem_link_pm_data.gpio_link_active, 1);
+	} else
+		return -ENODEV;
+
+	return 0;
+}
+
+/* if use more than one modem device, then set id num */
+static struct platform_device umts_modem = {
+	.name = "modem_if",
+	.id = -1,
+	.num_resources = ARRAY_SIZE(umts_modem_res),
+	.resource = umts_modem_res,
+	.dev = {
+		.platform_data = &umts_modem_data,
+	},
+};
+
+static void umts_modem_cfg_gpio(void)
+{
+	int err = 0;
+
+	unsigned gpio_reset_req_n = umts_modem_data.gpio_reset_req_n;
+	unsigned gpio_cp_on = umts_modem_data.gpio_cp_on;
+	unsigned gpio_cp_rst = umts_modem_data.gpio_cp_reset;
+	unsigned gpio_pda_active = umts_modem_data.gpio_pda_active;
+	unsigned gpio_phone_active = umts_modem_data.gpio_phone_active;
+	unsigned gpio_cp_dump_int = umts_modem_data.gpio_cp_dump_int;
+	unsigned gpio_flm_uart_sel = umts_modem_data.gpio_flm_uart_sel;
+	unsigned gpio_sim_detect = umts_modem_data.gpio_sim_detect;
+	unsigned irq_phone_active = umts_modem_res[0].start;
+
+	if (gpio_reset_req_n) {
+		err = gpio_request(gpio_reset_req_n, "RESET_REQ_N");
+		if (err) {
+			printk(KERN_ERR "fail to request gpio %s : %d\n",
+			       "RESET_REQ_N", err);
+		}
+		gpio_direction_output(gpio_reset_req_n, 0);
+	}
+
+	if (gpio_cp_on) {
+		err = gpio_request(gpio_cp_on, "CP_ON");
+		if (err) {
+			printk(KERN_ERR "fail to request gpio %s : %d\n",
+			       "CP_ON", err);
+		}
+		gpio_direction_output(gpio_cp_on, 0);
+	}
+
+	if (gpio_cp_rst) {
+		err = gpio_request(gpio_cp_rst, "CP_RST");
+		if (err) {
+			printk(KERN_ERR "fail to request gpio %s : %d\n",
+			       "CP_RST", err);
+		}
+		gpio_direction_output(gpio_cp_rst, 0);
+		s3c_gpio_setpull(gpio_cp_rst, S3C_GPIO_PULL_NONE);
+	}
+
+	if (gpio_pda_active) {
+		err = gpio_request(gpio_pda_active, "PDA_ACTIVE");
+		if (err) {
+			printk(KERN_ERR "fail to request gpio %s : %d\n",
+			       "PDA_ACTIVE", err);
+		}
+		gpio_direction_output(gpio_pda_active, 0);
+	}
+
+	if (gpio_phone_active) {
+		err = gpio_request(gpio_phone_active, "PHONE_ACTIVE");
+		if (err) {
+			printk(KERN_ERR "fail to request gpio %s : %d\n",
+			       "PHONE_ACTIVE", err);
+		}
+		/* gpio_direction_input(gpio_phone_active); */
+		s3c_gpio_cfgpin(gpio_phone_active, S3C_GPIO_SFN(0xF));
+		s3c_gpio_setpull(gpio_phone_active, S3C_GPIO_PULL_NONE);
+		pr_err("check phone active = %d\n", irq_phone_active);
+	}
+
+	if (gpio_cp_dump_int) {
+		err = gpio_request(gpio_cp_dump_int, "CP_DUMP_INT");
+		if (err) {
+			printk(KERN_ERR "fail to request gpio %s : %d\n",
+			       "CP_DUMP_INT", err);
+		}
+		gpio_direction_input(gpio_cp_dump_int);
+	}
+
+	if (gpio_flm_uart_sel) {
+		err = gpio_request(gpio_flm_uart_sel, "GPS_UART_SEL");
+		if (err) {
+			printk(KERN_ERR "fail to request gpio %s : %d\n",
+			       "GPS_UART_SEL", err);
+		}
+		gpio_direction_output(gpio_reset_req_n, 0);
+	}
+
+	if (gpio_phone_active)
+		irq_set_irq_type(gpio_to_irq(gpio_phone_active),
+							IRQ_TYPE_LEVEL_HIGH);
+
+	if (gpio_sim_detect) {
+		err = gpio_request(gpio_sim_detect, "SIM_DETECT");
+		if (err)
+			printk(KERN_ERR "fail to request gpio %s: %d\n",
+				"SIM_DETECT", err);
+
+		/* gpio_direction_input(gpio_sim_detect); */
+		s3c_gpio_cfgpin(gpio_sim_detect, S3C_GPIO_SFN(0xF));
+		s3c_gpio_setpull(gpio_sim_detect, S3C_GPIO_PULL_NONE);
+		irq_set_irq_type(gpio_to_irq(gpio_sim_detect),
+							IRQ_TYPE_EDGE_BOTH);
+	}
+
+	printk(KERN_INFO "umts_modem_cfg_gpio done\n");
+}
+
+static void modem_link_pm_config_gpio(void)
+{
+	int err = 0;
+
+	unsigned gpio_link_enable = modem_link_pm_data.gpio_link_enable;
+	unsigned gpio_link_active = modem_link_pm_data.gpio_link_active;
+	unsigned gpio_link_hostwake = modem_link_pm_data.gpio_link_hostwake;
+	unsigned gpio_link_slavewake = modem_link_pm_data.gpio_link_slavewake;
+	/* unsigned irq_link_hostwake = umts_modem_res[1].start; */
+
+	if (gpio_link_enable) {
+		err = gpio_request(gpio_link_enable, "LINK_EN");
+		if (err) {
+			printk(KERN_ERR "fail to request gpio %s : %d\n",
+			       "LINK_EN", err);
+		}
+		gpio_direction_output(gpio_link_enable, 0);
+	}
+
+	if (gpio_link_active) {
+		err = gpio_request(gpio_link_active, "LINK_ACTIVE");
+		if (err) {
+			printk(KERN_ERR "fail to request gpio %s : %d\n",
+			       "LINK_ACTIVE", err);
+		}
+		gpio_direction_output(gpio_link_active, 0);
+	}
+
+	if (gpio_link_hostwake) {
+		err = gpio_request(gpio_link_hostwake, "HOSTWAKE");
+		if (err) {
+			printk(KERN_ERR "fail to request gpio %s : %d\n",
+			       "HOSTWAKE", err);
+		}
+		gpio_direction_input(gpio_link_hostwake);
+		s3c_gpio_cfgpin(gpio_link_hostwake, S3C_GPIO_SFN(0xF));
+		s3c_gpio_setpull(gpio_link_hostwake, S3C_GPIO_PULL_NONE);
+	}
+
+	if (gpio_link_slavewake) {
+		err = gpio_request(gpio_link_slavewake, "SLAVEWAKE");
+		if (err) {
+			printk(KERN_ERR "fail to request gpio %s : %d\n",
+			       "SLAVEWAKE", err);
+		}
+		gpio_direction_output(gpio_link_slavewake, 0);
+		s3c_gpio_setpull(gpio_link_slavewake, S3C_GPIO_PULL_NONE);
+	}
+
+	if (gpio_link_hostwake)
+		irq_set_irq_type(gpio_to_irq(gpio_link_hostwake),
+				IRQ_TYPE_EDGE_BOTH);
+
+	active_ctl.gpio_initialized = 1;
+	if (active_ctl.gpio_request_host_active) {
+		pr_err(" [MODEM_IF] Active States = 1, %s\n", __func__);
+		gpio_direction_output(modem_link_pm_data.gpio_link_active, 1);
+	}
+
+	printk(KERN_INFO "modem_link_pm_config_gpio done\n");
+}
+
+static int __init init_modem(void)
+{
+	int ret;
+	printk(KERN_INFO "[MODEM_IF] init_modem\n");
+
+	/* umts gpios configuration */
+	umts_modem_cfg_gpio();
+	modem_link_pm_config_gpio();
+	ret = platform_device_register(&umts_modem);
+	if (ret < 0)
+		return ret;
+
+	return ret;
+}
+late_initcall(init_modem);
diff --git a/arch/arm/mach-exynos/bts.c b/arch/arm/mach-exynos/bts.c
new file mode 100644
index 0000000..7b60750
--- /dev/null
+++ b/arch/arm/mach-exynos/bts.c
@@ -0,0 +1,545 @@
+/* linux/arch/arm/mach-exynos/bts.c
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+
+#include <plat/devs.h>
+#include <plat/irqs.h>
+#ifdef CONFIG_EXYNOS_DEV_PD
+#include <plat/pd.h>
+#endif
+
+#include <mach/map.h>
+#include <mach/irqs.h>
+
+#include <plat/cpu.h>
+#include <plat/bts.h>
+#include <mach/map-exynos5.h>
+
+
+static struct resource exynos_bts_cpu_resource[] = {
+	[0] = {
+		.start  = EXYNOS5_PA_BTS_CPU,
+		.end    = EXYNOS5_PA_BTS_CPU + SZ_1K,
+		.flags = IORESOURCE_MEM,
+	},
+};
+
+static struct resource exynos_bts_jpeg_resource[] = {
+	[0] = {
+		.start  = EXYNOS5_PA_BTS_JPEG,
+		.end    = EXYNOS5_PA_BTS_JPEG + SZ_1K,
+		.flags = IORESOURCE_MEM,
+	},
+};
+
+static struct resource exynos_bts_mdma1_resource[] = {
+	[0] = {
+		.start  = EXYNOS5_PA_BTS_MDMA1,
+		.end    = EXYNOS5_PA_BTS_MDMA1 + SZ_1K,
+		.flags = IORESOURCE_MEM,
+	},
+};
+
+static struct resource exynos_bts_rotator_resource[] = {
+	[0] = {
+		.start  = EXYNOS5_PA_BTS_ROTATOR,
+		.end    = EXYNOS5_PA_BTS_ROTATOR + SZ_1K,
+		.flags = IORESOURCE_MEM,
+	},
+};
+
+static struct resource exynos_bts_gscl0_resource[] = {
+	[0] = {
+		.start  = EXYNOS5_PA_BTS_GSCL0,
+		.end    = EXYNOS5_PA_BTS_GSCL0 + SZ_1K,
+		.flags = IORESOURCE_MEM,
+	},
+};
+
+static struct resource exynos_bts_gscl1_resource[] = {
+	[0] = {
+		.start  = EXYNOS5_PA_BTS_GSCL1,
+		.end    = EXYNOS5_PA_BTS_GSCL1 + SZ_1K,
+		.flags = IORESOURCE_MEM,
+	},
+};
+
+static struct resource exynos_bts_gscl2_resource[] = {
+	[0] = {
+		.start  = EXYNOS5_PA_BTS_GSCL2,
+		.end    = EXYNOS5_PA_BTS_GSCL2 + SZ_1K,
+		.flags = IORESOURCE_MEM,
+	},
+};
+
+static struct resource exynos_bts_gscl3_resource[] = {
+	[0] = {
+		.start  = EXYNOS5_PA_BTS_GSCL3,
+		.end    = EXYNOS5_PA_BTS_GSCL3 + SZ_1K,
+		.flags = IORESOURCE_MEM,
+	},
+};
+
+static struct resource exynos_bts_mfc_resource[] = {
+	[0] = {
+		.start  = EXYNOS5_PA_BTS_MFC0,
+		.end    = EXYNOS5_PA_BTS_MFC0 + SZ_1K,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start  = EXYNOS5_PA_BTS_MFC1,
+		.end    = EXYNOS5_PA_BTS_MFC1 + SZ_1K,
+		.flags = IORESOURCE_MEM,
+	},
+};
+
+static struct resource exynos_bts_g3dacp_resource[] = {
+	[0] = {
+		.start  = EXYNOS5_PA_BTS_G3D_ACP,
+		.end    = EXYNOS5_PA_BTS_G3D_ACP + SZ_1K,
+		.flags = IORESOURCE_MEM,
+	},
+};
+
+static struct resource exynos_bts_isp0_resource[] = {
+	[0] = {
+		.start  = EXYNOS5_PA_BTS_FIMC_ISP,
+		.end    = EXYNOS5_PA_BTS_FIMC_ISP + SZ_1K,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start  = EXYNOS5_PA_BTS_FIMC_FD,
+		.end    = EXYNOS5_PA_BTS_FIMC_FD + SZ_1K,
+		.flags = IORESOURCE_MEM,
+	},
+	[2] = {
+		.start  = EXYNOS5_PA_BTS_FIMC_SCALER_C,
+		.end    = EXYNOS5_PA_BTS_FIMC_SCALER_C + SZ_1K,
+		.flags = IORESOURCE_MEM,
+	},
+	[3] = {
+		.start  = EXYNOS5_PA_BTS_FIMC_SCALER_P,
+		.end    = EXYNOS5_PA_BTS_FIMC_SCALER_P + SZ_1K,
+		.flags = IORESOURCE_MEM,
+	},
+};
+
+static struct resource exynos_bts_isp1_resource[] = {
+	[0] = {
+		.start  = EXYNOS5_PA_BTS_FIMC_ODC,
+		.end    = EXYNOS5_PA_BTS_FIMC_ODC + SZ_1K,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start  = EXYNOS5_PA_BTS_FIMC_DIS0,
+		.end    = EXYNOS5_PA_BTS_FIMC_DIS0 + SZ_1K,
+		.flags = IORESOURCE_MEM,
+	},
+	[2] = {
+		.start  = EXYNOS5_PA_BTS_FIMC_DIS1,
+		.end    = EXYNOS5_PA_BTS_FIMC_DIS1 + SZ_1K,
+		.flags = IORESOURCE_MEM,
+	},
+	[3] = {
+		.start  = EXYNOS5_PA_BTS_FIMC_3DNR,
+		.end    = EXYNOS5_PA_BTS_FIMC_3DNR + SZ_1K,
+		.flags = IORESOURCE_MEM,
+	},
+};
+
+static struct resource exynos_bts_disp_resource[] = {
+	[0] = {
+		.start  = EXYNOS5_PA_BTS_DISP10,
+		.end    = EXYNOS5_PA_BTS_DISP10 + SZ_1K,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start  = EXYNOS5_PA_BTS_DISP11,
+		.end    = EXYNOS5_PA_BTS_DISP11 + SZ_1K,
+		.flags = IORESOURCE_MEM,
+	},
+};
+
+static struct resource exynos_bts_tv_resource[] = {
+	[0] = {
+		.start  = EXYNOS5_PA_BTS_TV0,
+		.end    = EXYNOS5_PA_BTS_TV0 + SZ_1K,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start  = EXYNOS5_PA_BTS_TV1,
+		.end    = EXYNOS5_PA_BTS_TV1 + SZ_1K,
+		.flags = IORESOURCE_MEM,
+	},
+};
+
+static struct resource exynos_bts_c2c_resource[] = {
+	[0] = {
+		.start  = EXYNOS5_PA_BTS_C2C,
+		.end    = EXYNOS5_PA_BTS_C2C + SZ_1K,
+		.flags = IORESOURCE_MEM,
+	},
+};
+
+struct exynos_fbm_resource fbm_res[] = {
+	{
+		.fbm_group = BTS_FBM_G1_R,
+		.priority = BTS_BE,
+		.base = EXYNOS5_PA_FBM_DDR_R1,
+	}, {
+		.fbm_group = BTS_FBM_G1_L,
+		.priority = BTS_HARDTIME,
+		.base = EXYNOS5_PA_FBM_DDR_R0,
+	}
+};
+
+struct exynos_fbm_pdata fbm_pdata = {
+	.res = fbm_res,
+	.res_num = ARRAY_SIZE(fbm_res),
+};
+
+struct exynos_bts_pdata bts_cpu_res = {
+	.id = BTS_CPU,
+	.def_priority = BTS_BE,
+	.pd_block = PD_TOP,
+	.clk_name = NULL,
+	.fbm = &fbm_pdata,
+	.res_num = ARRAY_SIZE(exynos_bts_cpu_resource),
+};
+
+struct exynos_bts_pdata bts_jpeg_res = {
+	.id = BTS_JPEG,
+	.def_priority = BTS_BE,
+	.pd_block = PD_GSCL,
+	.clk_name = "jpeg",
+	.fbm = &fbm_pdata,
+	.res_num = ARRAY_SIZE(exynos_bts_jpeg_resource),
+};
+
+struct exynos_bts_pdata bts_mdma1_res = {
+	.id = BTS_MDMA1,
+	.def_priority = BTS_BE,
+	.clk_name = "pdma",
+	.pd_block = PD_TOP,
+	.fbm = &fbm_pdata,
+	.res_num = ARRAY_SIZE(exynos_bts_mdma1_resource),
+};
+
+struct exynos_bts_pdata bts_rotator_res = {
+	.id = BTS_ROTATOR,
+	.def_priority = BTS_BE,
+	.pd_block = PD_DISP1,
+	.clk_name = "rotator",
+	.fbm = &fbm_pdata,
+	.res_num = ARRAY_SIZE(exynos_bts_rotator_resource),
+};
+
+struct exynos_bts_pdata bts_gscl0_res = {
+	.id = BTS_GSCL,
+	.def_priority = BTS_BE,
+	.pd_block = PD_GSCL,
+	.clk_name = "gscl",
+	.fbm = &fbm_pdata,
+	.res_num = ARRAY_SIZE(exynos_bts_gscl0_resource),
+};
+
+struct exynos_bts_pdata bts_gscl1_res = {
+	.id = BTS_GSCL,
+	.def_priority = BTS_BE,
+	.pd_block = PD_GSCL,
+	.clk_name = "gscl",
+	.fbm = &fbm_pdata,
+	.res_num = ARRAY_SIZE(exynos_bts_gscl1_resource),
+};
+
+struct exynos_bts_pdata bts_gscl2_res = {
+	.id = BTS_GSCL,
+	.def_priority = BTS_BE,
+	.pd_block = PD_GSCL,
+	.clk_name = "gscl",
+	.fbm = &fbm_pdata,
+	.res_num = ARRAY_SIZE(exynos_bts_gscl2_resource),
+};
+
+struct exynos_bts_pdata bts_gscl3_res = {
+	.id = BTS_GSCL,
+	.def_priority = BTS_BE,
+	.pd_block = PD_GSCL,
+	.clk_name = "gscl",
+	.fbm = &fbm_pdata,
+	.res_num = ARRAY_SIZE(exynos_bts_gscl3_resource),
+};
+
+struct exynos_bts_pdata bts_mfc_res = {
+	.id = BTS_MFC,
+	.def_priority = BTS_BE,
+	.pd_block = PD_MFC,
+	.clk_name = "mfc",
+	.fbm = &fbm_pdata,
+	.res_num = ARRAY_SIZE(exynos_bts_mfc_resource),
+};
+
+struct exynos_bts_pdata bts_g3dacp_res = {
+	.id = BTS_G3D_ACP,
+	.def_priority = BTS_BE,
+	.pd_block = PD_G3D,
+	.clk_name = "g3d",
+	.fbm = &fbm_pdata,
+	.res_num = ARRAY_SIZE(exynos_bts_g3dacp_resource),
+};
+
+struct exynos_bts_pdata bts_isp0_res = {
+	.id = BTS_ISP0,
+	.def_priority = BTS_BE,
+	.pd_block = PD_MFC,
+	.clk_name = "isp0",
+	.fbm = &fbm_pdata,
+	.res_num = ARRAY_SIZE(exynos_bts_isp0_resource),
+};
+
+struct exynos_bts_pdata bts_isp1_res = {
+	.id = BTS_ISP1,
+	.def_priority = BTS_BE,
+	.pd_block = PD_MFC,
+	.clk_name = "isp1",
+	.fbm = &fbm_pdata,
+	.res_num = ARRAY_SIZE(exynos_bts_isp1_resource),
+};
+
+struct exynos_bts_pdata bts_disp_res = {
+	.id = BTS_DISP,
+	.def_priority = BTS_HARDTIME,
+	.pd_block = PD_DISP1,
+	.clk_name = "lcd",
+	.fbm = &fbm_pdata,
+	.res_num = ARRAY_SIZE(exynos_bts_disp_resource),
+};
+
+struct exynos_bts_pdata bts_tv_res = {
+	.id = BTS_TV,
+	.def_priority = BTS_HARDTIME,
+	.pd_block = PD_DISP1,
+	.clk_name = "mixer",
+	.fbm = &fbm_pdata,
+	.res_num = ARRAY_SIZE(exynos_bts_tv_resource),
+};
+
+struct exynos_bts_pdata bts_c2c_res = {
+	.id = BTS_C2C,
+	.def_priority = BTS_HARDTIME,
+	.clk_name = "c2c",
+	.fbm = &fbm_pdata,
+	.res_num = ARRAY_SIZE(exynos_bts_c2c_resource),
+};
+
+/* bts platform device lists */
+struct platform_device exynos_device_bts_disp = {
+	.name		= "exynos-bts",
+	.id		= 0,
+	.num_resources	= ARRAY_SIZE(exynos_bts_disp_resource),
+	.resource	= exynos_bts_disp_resource,
+	.dev		= {
+		.platform_data = &bts_disp_res,
+		.parent = &s5p_device_fimd1.dev,
+	},
+};
+
+struct platform_device exynos_device_bts_tv = {
+	.name		= "exynos-bts",
+	.id		= 1,
+	.num_resources	= ARRAY_SIZE(exynos_bts_tv_resource),
+	.resource	= exynos_bts_tv_resource,
+	.dev		= {
+		.platform_data = &bts_tv_res,
+		.parent = &s5p_device_mixer.dev,
+	},
+};
+
+#if defined(CONFIG_EXYNOS_C2C)
+struct platform_device exynos_device_bts_c2c = {
+	.name		= "exynos-bts",
+	.id		= 2,
+	.num_resources	= ARRAY_SIZE(exynos_bts_c2c_resource),
+	.resource	= exynos_bts_c2c_resource,
+	.dev		= {
+		.platform_data = &bts_c2c_res,
+		.parent = &exynos_device_c2c.dev,
+	},
+};
+#endif
+
+struct platform_device exynos_device_bts_g3dacp = {
+	.name		= "exynos-bts",
+	.id		= 3,
+	.num_resources	= ARRAY_SIZE(exynos_bts_g3dacp_resource),
+	.resource	= exynos_bts_g3dacp_resource,
+	.dev		= {
+		.platform_data = &bts_g3dacp_res,
+	},
+};
+
+struct platform_device exynos_device_bts_rotator = {
+	.name		= "exynos-bts",
+	.id		= 4,
+	.num_resources	= ARRAY_SIZE(exynos_bts_rotator_resource),
+	.resource	= exynos_bts_rotator_resource,
+	.dev		= {
+		.platform_data = &bts_rotator_res,
+		.parent = &exynos_device_rotator.dev,
+	},
+};
+
+struct platform_device exynos_device_bts_jpeg = {
+	.name		= "exynos-bts",
+	.id		= 5,
+	.num_resources	= ARRAY_SIZE(exynos_bts_jpeg_resource),
+	.resource	= exynos_bts_jpeg_resource,
+	.dev		= {
+		.platform_data = &bts_jpeg_res,
+	},
+};
+
+struct platform_device exynos_device_bts_mdma1 = {
+	.name		= "exynos-bts",
+	.id		= 6,
+	.num_resources	= ARRAY_SIZE(exynos_bts_mdma1_resource),
+	.resource	= exynos_bts_mdma1_resource,
+	.dev		= {
+		.platform_data = &bts_mdma1_res,
+		.parent = &exynos_device_mdma.dev,
+	},
+};
+
+struct platform_device exynos_device_bts_gscl0 = {
+	.name		= "exynos-bts",
+	.id		= 7,
+	.num_resources	= ARRAY_SIZE(exynos_bts_gscl0_resource),
+	.resource	= exynos_bts_gscl0_resource,
+	.dev		= {
+		.platform_data = &bts_gscl0_res,
+		.parent = &exynos5_device_gsc0.dev,
+	},
+};
+
+struct platform_device exynos_device_bts_gscl1 = {
+	.name		= "exynos-bts",
+	.id		= 8,
+	.num_resources	= ARRAY_SIZE(exynos_bts_gscl1_resource),
+	.resource	= exynos_bts_gscl1_resource,
+	.dev		= {
+		.platform_data = &bts_gscl1_res,
+		.parent = &exynos5_device_gsc1.dev,
+	},
+};
+
+struct platform_device exynos_device_bts_gscl2 = {
+	.name		= "exynos-bts",
+	.id		= 9,
+	.num_resources	= ARRAY_SIZE(exynos_bts_gscl2_resource),
+	.resource	= exynos_bts_gscl2_resource,
+	.dev		= {
+		.platform_data = &bts_gscl2_res,
+		.parent = &exynos5_device_gsc2.dev,
+	},
+};
+
+struct platform_device exynos_device_bts_gscl3 = {
+	.name		= "exynos-bts",
+	.id		= 10,
+	.num_resources	= ARRAY_SIZE(exynos_bts_gscl3_resource),
+	.resource	= exynos_bts_gscl3_resource,
+	.dev		= {
+		.platform_data = &bts_gscl3_res,
+		.parent = &exynos5_device_gsc3.dev,
+	},
+};
+
+struct platform_device exynos_device_bts_mfc = {
+	.name		= "exynos-bts",
+	.id		= 11,
+	.num_resources	= ARRAY_SIZE(exynos_bts_mfc_resource),
+	.resource	= exynos_bts_mfc_resource,
+	.dev		= {
+		.platform_data = &bts_mfc_res,
+		.parent = &s5p_device_mfc.dev,
+	},
+};
+
+#if defined(CONFIG_EXYNOS4_DEV_FIMC_IS)
+struct platform_device exynos_device_bts_isp0 = {
+	.name		= "exynos-bts",
+	.id		= 12,
+	.num_resources	= ARRAY_SIZE(exynos_bts_isp0_resource),
+	.resource	= exynos_bts_isp0_resource,
+	.dev		= {
+		.platform_data = &bts_isp0_res,
+		.parent = &exynos5_device_fimc_is.dev,
+	},
+};
+
+struct platform_device exynos_device_bts_isp1 = {
+	.name		= "exynos-bts",
+	.id		= 13,
+	.num_resources	= ARRAY_SIZE(exynos_bts_isp1_resource),
+	.resource	= exynos_bts_isp1_resource,
+	.dev		= {
+		.platform_data = &bts_isp1_res,
+		.parent = &exynos5_device_fimc_is.dev,
+	},
+};
+#endif
+
+struct platform_device exynos_device_bts_cpu = {
+	.name		= "exynos-bts",
+	.id		= 14,
+	.num_resources	= ARRAY_SIZE(exynos_bts_cpu_resource),
+	.resource	= exynos_bts_cpu_resource,
+	.dev		= {
+		.platform_data = &bts_cpu_res,
+	},
+};
+
+static struct platform_device *exynos_bts[] __initdata = {
+	&exynos_device_bts_disp,
+	&exynos_device_bts_tv,
+#if defined(CONFIG_EXYNOS_C2C)
+	&exynos_device_bts_c2c,
+#endif
+	&exynos_device_bts_g3dacp,
+	&exynos_device_bts_rotator,
+	&exynos_device_bts_jpeg,
+	&exynos_device_bts_mdma1,
+	&exynos_device_bts_gscl0,
+	&exynos_device_bts_gscl1,
+	&exynos_device_bts_gscl2,
+	&exynos_device_bts_gscl3,
+	&exynos_device_bts_mfc,
+	&exynos_device_bts_isp0,
+	&exynos_device_bts_isp1,
+	&exynos_device_bts_cpu,
+};
+
+static int __init exynos_bts_init(void)
+{
+	return platform_add_devices(exynos_bts, ARRAY_SIZE(exynos_bts));
+}
+arch_initcall(exynos_bts_init);
diff --git a/arch/arm/mach-exynos/busfreq.c b/arch/arm/mach-exynos/busfreq.c
new file mode 100644
index 0000000..38a31b1
--- /dev/null
+++ b/arch/arm/mach-exynos/busfreq.c
@@ -0,0 +1,974 @@
+/* linux/arch/arm/mach-exynos/busfreq.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * EXYNOS4 - BUS clock frequency scaling support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/types.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/regulator/consumer.h>
+#include <linux/sysfs.h>
+#include <linux/platform_device.h>
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/cpu.h>
+#include <linux/ktime.h>
+#include <linux/tick.h>
+#include <linux/kernel_stat.h>
+#include <linux/cpufreq.h>
+#include <linux/suspend.h>
+#include <linux/reboot.h>
+#include <linux/clk.h>
+#include <linux/pm_qos_params.h>
+
+#include <asm/mach-types.h>
+
+#include <mach/ppmu.h>
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/gpio.h>
+#include <mach/regs-mem.h>
+#include <mach/cpufreq.h>
+#include <mach/asv.h>
+#include <mach/sec_debug.h>
+
+#include <plat/map-s5p.h>
+#include <plat/gpio-cfg.h>
+#include <plat/cpu.h>
+
+#define MAX_LOAD		100
+#define DIVIDING_FACTOR		10000
+#define UP_THRESHOLD_DEFAULT	23
+
+#define SYSFS_DEBUG_BUSFREQ
+
+static unsigned up_threshold;
+static struct regulator *int_regulator;
+static struct exynos4_ppmu_hw dmc[2];
+static struct exynos4_ppmu_hw cpu;
+static unsigned int bus_utilization[2];
+static struct cpufreq_freqs *freqs;
+
+static unsigned int g_busfreq_lock_id;
+static enum busfreq_level_request g_busfreq_lock_val[DVFS_LOCK_ID_END];
+static enum busfreq_level_request g_busfreq_lock_level;
+
+const char *const cpufreq_lock_name[DVFS_LOCK_ID_END] = {
+	[DVFS_LOCK_ID_G2D] = "G2D",
+	[DVFS_LOCK_ID_TV] = "TV",
+	[DVFS_LOCK_ID_MFC] = "MFC",
+	[DVFS_LOCK_ID_USB] = "USB",
+	[DVFS_LOCK_ID_CAM] = "CAM",
+	[DVFS_LOCK_ID_PM] = "PM",
+	[DVFS_LOCK_ID_USER] = "USER",
+	[DVFS_LOCK_ID_LCD] = "LCD",
+	[DVFS_LOCK_ID_ROTATION_BOOSTER] = "ROTATION_BOOSTER",
+};
+
+static DEFINE_MUTEX(set_bus_freq_lock);
+
+enum busfreq_level_idx {
+	LV_0,
+	LV_1,
+	LV_2,
+	LV_END
+};
+
+#ifdef SYSFS_DEBUG_BUSFREQ
+static unsigned int time_in_state[LV_END];
+unsigned long prejiffies;
+unsigned long curjiffies;
+#endif
+
+static unsigned int p_idx;
+static unsigned int curr_idx;
+static bool init_done;
+
+struct busfreq_table {
+	unsigned int idx;
+	unsigned int mem_clk;
+	unsigned int volt;
+	unsigned int clk_topdiv;
+	unsigned int clk_dmcdiv;
+};
+
+static struct busfreq_table exynos4_busfreq_table[] = {
+	{LV_0, 400000, 1100000, 0, 0},
+	{LV_1, 267000, 1000000, 0, 0},
+#ifdef CONFIG_BUSFREQ_L2_160M
+	/*L2: 160MHz */
+	{LV_2, 160000, 1000000, 0, 0},
+#else
+	/* L2: 133MHz */
+	{LV_2, 133000, 950000, 0, 0},
+#endif
+	{0, 0, 0, 0, 0},
+};
+
+#ifdef CONFIG_BUSFREQ_QOS
+enum busfreq_qos_target {
+	BUS_QOS_0,
+	BUS_QOS_1,
+	BUS_QOS_MAX,
+};
+
+static enum busfreq_qos_target busfreq_qos = BUS_QOS_0;
+
+/*  GDL: [3] MFC_L, [2] G3D, [1] TV, [0] Image */
+/*  GDR: [5] MAUDIO, [4] MFC_R, [3] FSYS, [2] LCD1, [1] LCD0, [0] CAM */
+#if defined(CONFIG_BUSFREQ_QOS_NONE)
+static unsigned int exynos4_qos_value[BUS_QOS_MAX][LV_END][4] = {
+	{
+		{0x00, 0x00, 0x00, 0x00},
+		{0x00, 0x00, 0x00, 0x00},
+		{0x00, 0x00, 0x00, 0x00},
+	},
+	{
+		{0x00, 0x00, 0x00, 0x00},
+		{0x00, 0x00, 0x00, 0x00},
+		{0x00, 0x00, 0x00, 0x00},
+	}
+};
+#elif defined(CONFIG_BUSFREQ_QOS_1024X600)	/* For P2 */
+static unsigned int exynos4_qos_value[BUS_QOS_MAX][LV_END][4] = {
+	{
+		{0x00, 0x00, 0x00, 0x00},
+		{0x00, 0x00, 0x00, 0x00},
+		{0x06, 0x0b, 0x00, 0x00},
+	},
+	{
+		{0x00, 0x00, 0x00, 0x00},
+		{0x00, 0x00, 0x00, 0x00},
+		{0x06, 0x0b, 0x00, 0x00},
+	}
+};
+#elif defined(CONFIG_BUSFREQ_QOS_1280X800)	/* For Q1, P8 */
+static unsigned int exynos4_qos_value[BUS_QOS_MAX][LV_END][4] = {
+	{
+		{0x07, 0x03, 0x07, 0x0f},
+		{0x07, 0x03, 0x07, 0x0f},
+		{0x03, 0x0b, 0x00, 0x00},
+	},
+	{
+		{0x06, 0x0b, 0x00, 0x00},
+		{0x06, 0x0b, 0x00, 0x00},
+		{0x03, 0x0b, 0x00, 0x00},
+	}
+};
+#endif
+#endif
+
+#define ASV_GROUP	5
+static unsigned int exynos4_asv_volt[ASV_GROUP][LV_END] = {
+	{1150000, 1050000, 1050000},
+	{1125000, 1025000, 1025000},
+	{1100000, 1000000, 1000000},
+	{1075000, 975000, 975000},
+	{1050000, 950000, 950000},
+};
+
+static unsigned int clkdiv_dmc0[LV_END][8] = {
+	/*
+	 * Clock divider value for following
+	 * { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD
+	 *              DIVDMCP, DIVCOPY2, DIVCORE_TIMERS }
+	 */
+
+	/* DMC L0: 400MHz */
+	{ 3, 2, 1, 1, 1, 1, 3, 1 },
+
+	/* DMC L1: 266.7MHz */
+	{ 4, 2, 1, 2, 1, 1, 3, 1 },
+
+#ifdef CONFIG_BUSFREQ_L2_160M
+	/* DMC L2: 160MHz */
+	{ 5, 1, 1, 4, 1, 1, 3, 1 },
+#else
+	/* DMC L2: 133MHz */
+	{ 5, 2, 1, 5, 1, 1, 3, 1 },
+#endif
+};
+
+static unsigned int clkdiv_top[LV_END][5] = {
+	/*
+	 * Clock divider value for following
+	 * { DIVACLK200, DIVACLK100, DIVACLK160, DIVACLK133, DIVONENAND }
+	 */
+
+	/* ACLK200 L0: 200MHz */
+	{ 3, 7, 4, 5, 1 },
+
+	/* ACLK200 L1: 160MHz */
+	{ 4, 7, 5, 6, 1 },
+
+	/* ACLK200 L2: 133MHz */
+	{ 5, 7, 7, 7, 1 },
+};
+
+static unsigned int clkdiv_lr_bus[LV_END][2] = {
+	/*
+	 * Clock divider value for following
+	 * { DIVGDL/R, DIVGPL/R }
+	 */
+
+	/* ACLK_GDL/R L1: 200MHz */
+	{ 3, 1 },
+
+	/* ACLK_GDL/R L2: 160MHz */
+	{ 4, 1 },
+
+	/* ACLK_GDL/R L3: 133MHz */
+	{ 5, 1 },
+};
+
+static unsigned int clkdiv_ip_bus[LV_END][3] = {
+	/*
+	 * Clock divider value for following
+	 * { DIV_MFC, DIV_G2D, DIV_FIMC }
+	 */
+
+	/* L0: MFC 200MHz G2D 266MHz FIMC 160MHz */
+	{ 3, 2, 4 },
+
+	/* L1: MFC 200MHz G2D 160MHz FIMC 133MHz */
+	/* { 4, 4, 5 }, */
+	{ 3, 4, 5 },
+
+	/* L2: MFC 200MHz G2D 133MHz FIMC 100MHz */
+	/* { 5, 5, 7 }, */
+	{ 3, 5, 7 },
+};
+
+#ifdef CONFIG_BUSFREQ_QOS
+static void exynos4_set_qos(unsigned int index)
+{
+	/* printk(KERN_INFO "exynos4_set_qos level %d\n", index); */
+	__raw_writel(exynos4_qos_value[busfreq_qos][index][0], S5P_VA_GDL + 0x400);
+	__raw_writel(exynos4_qos_value[busfreq_qos][index][1], S5P_VA_GDL + 0x404);
+	__raw_writel(exynos4_qos_value[busfreq_qos][index][2], S5P_VA_GDR + 0x400);
+	__raw_writel(exynos4_qos_value[busfreq_qos][index][3], S5P_VA_GDR + 0x404);
+}
+#endif
+
+static void exynos4_set_busfreq(unsigned int div_index)
+{
+	unsigned int tmp, val;
+
+	sec_debug_aux_log(SEC_DEBUG_AUXLOG_CPU_BUS_CLOCK_CHANGE,
+			"%s: div_index=%d(%ps)", __func__, div_index,
+			__builtin_return_address(0));
+
+	/* Change Divider - DMC0 */
+	tmp = exynos4_busfreq_table[div_index].clk_dmcdiv;
+
+	__raw_writel(tmp, EXYNOS4_CLKDIV_DMC0);
+
+	do {
+		tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC0);
+	} while (tmp & 0x11111111);
+
+	/* Change Divider - TOP */
+	tmp = exynos4_busfreq_table[div_index].clk_topdiv;
+
+	__raw_writel(tmp, EXYNOS4_CLKDIV_TOP);
+
+	do {
+		tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_TOP);
+	} while (tmp & 0x11111);
+
+	/* Change Divider - LEFTBUS */
+	tmp = __raw_readl(EXYNOS4_CLKDIV_LEFTBUS);
+
+	tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK);
+
+	tmp |= ((clkdiv_lr_bus[div_index][0] << EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) |
+		(clkdiv_lr_bus[div_index][1] << EXYNOS4_CLKDIV_BUS_GPLR_SHIFT));
+
+	__raw_writel(tmp, EXYNOS4_CLKDIV_LEFTBUS);
+
+	do {
+		tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_LEFTBUS);
+	} while (tmp & 0x11);
+
+	/* Change Divider - RIGHTBUS */
+	tmp = __raw_readl(EXYNOS4_CLKDIV_RIGHTBUS);
+
+	tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK);
+
+	tmp |= ((clkdiv_lr_bus[div_index][0] << EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) |
+		(clkdiv_lr_bus[div_index][1] << EXYNOS4_CLKDIV_BUS_GPLR_SHIFT));
+
+	__raw_writel(tmp, EXYNOS4_CLKDIV_RIGHTBUS);
+
+	do {
+		tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_RIGHTBUS);
+	} while (tmp & 0x11);
+
+	/* Change Divider - SCLK_MFC */
+	tmp = __raw_readl(EXYNOS4_CLKDIV_MFC);
+
+	tmp &= ~EXYNOS4_CLKDIV_MFC_MASK;
+
+	tmp |= (clkdiv_ip_bus[div_index][0] << EXYNOS4_CLKDIV_MFC_SHIFT);
+
+	__raw_writel(tmp, EXYNOS4_CLKDIV_MFC);
+
+	do {
+		tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_MFC);
+	} while (tmp & 0x1);
+
+	/* Change Divider - SCLK_G2D */
+	tmp = __raw_readl(EXYNOS4_CLKDIV_IMAGE);
+
+	tmp &= ~EXYNOS4_CLKDIV_IMAGE_MASK;
+
+	tmp |= (clkdiv_ip_bus[div_index][1] << EXYNOS4_CLKDIV_IMAGE_SHIFT);
+
+	__raw_writel(tmp, EXYNOS4_CLKDIV_IMAGE);
+
+	do {
+		tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_IMAGE);
+	} while (tmp & 0x1);
+
+	/* Change Divider - SCLK_FIMC */
+	tmp = __raw_readl(EXYNOS4_CLKDIV_CAM);
+
+	tmp &= ~EXYNOS4_CLKDIV_CAM_MASK;
+
+	val = clkdiv_ip_bus[div_index][2];
+	tmp |= ((val << 0) | (val << 4) | (val << 8) | (val << 12));
+
+	__raw_writel(tmp, EXYNOS4_CLKDIV_CAM);
+
+	do {
+		tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_CAM);
+	} while (tmp & 0x1111);
+}
+
+static unsigned int calc_bus_utilization(struct exynos4_ppmu_hw *ppmu)
+{
+	if (ppmu->ccnt == 0) {
+		pr_err("%s: 0 value is not permitted\n", __func__);
+		return MAX_LOAD;
+	}
+
+	if (!(ppmu->ccnt >> 7))
+		return (ppmu->count[0] * 100) / ppmu->ccnt;
+	else
+		return ((ppmu->count[0] >> 7) * 100) / (ppmu->ccnt >> 7);
+}
+
+static int busfreq_target(struct busfreq_table *freq_table,
+			  unsigned int ppc_load,
+			  unsigned int ppmu_load,
+			  unsigned int pre_idx,
+			  unsigned int *index)
+{
+	unsigned int i, target_freq, idx = 0;
+
+	if (ppc_load > MAX_LOAD)
+		return -EINVAL;
+
+	if (ppc_load > 50) {
+		pr_debug("Busfreq: Bus Load is larger than 40(%d)\n", ppc_load);
+		ppc_load = 50;
+	}
+
+#ifdef CONFIG_BUSFREQ_L2_160M
+		target_freq = (ppc_load * freq_table[p_idx].mem_clk) /
+							(up_threshold);
+
+		for (i = 1; i <= LV_END; i++) {
+			if (target_freq >= freq_table[i].mem_clk) {
+				idx = i - 1;
+				break;
+			}
+		}
+
+		idx = freq_table[idx].idx;
+#else
+	if (ppc_load >= up_threshold) {
+		target_freq = freq_table[0].mem_clk;
+	} else {
+		target_freq = (ppc_load * freq_table[pre_idx].mem_clk) /
+			up_threshold;
+
+		if (target_freq >= freq_table[pre_idx].mem_clk) {
+			for (i = 0; (freq_table[i].mem_clk != 0); i++) {
+				unsigned int freq = freq_table[i].mem_clk;
+
+				if (freq <= target_freq) {
+					idx = i;
+					break;
+				}
+			}
+
+		} else {
+			for (i = 0; (freq_table[i].mem_clk != 0); i++) {
+				unsigned int freq = freq_table[i].mem_clk;
+
+				if (freq >= target_freq) {
+					idx = i;
+					continue;
+				}
+
+				if (freq < target_freq)
+					break;
+			}
+		}
+	}
+
+	if ((freqs->new == exynos_info->freq_table[exynos_info->max_support_idx].frequency)
+			&& (ppc_load == 0))
+		idx = pre_idx;
+#endif
+
+	if ((idx > LV_1) && (ppmu_load > 5))
+		idx = LV_1;
+
+	if (idx > g_busfreq_lock_level)
+		idx = g_busfreq_lock_level;
+
+	*index = idx;
+
+	return 0;
+}
+
+static void busfreq_mon_reset(void)
+{
+	unsigned int i;
+
+	for (i = 0; i < 2; i++) {
+		exynos4_ppc_reset(&dmc[i]);
+		exynos4_ppc_setevent(&dmc[i], 0x6);
+		exynos4_ppc_start(&dmc[i]);
+	}
+
+	exynos4_ppmu_reset(&cpu);
+
+	exynos4_ppmu_setevent(&cpu, 3);
+
+	exynos4_ppmu_start(&cpu);
+}
+
+static unsigned int busfreq_monitor(void)
+{
+	unsigned int i, index = 0, ret;
+	unsigned long long ppcload, ppmuload;
+#ifdef SYSFS_DEBUG_BUSFREQ
+	unsigned long level_state_jiffies;
+#endif
+
+	for (i = 0; i < 2; i++) {
+		exynos4_ppc_stop(&dmc[i]);
+		exynos4_ppc_update(&dmc[i]);
+		bus_utilization[i] = calc_bus_utilization(&dmc[i]);
+	}
+
+	exynos4_ppmu_stop(&cpu);
+	ppmuload = exynos4_ppmu_update(&cpu, 3);
+
+	if (ppmuload > 10) {
+		index = LV_0;
+		goto out;
+	}
+
+	ppcload = max(bus_utilization[0], bus_utilization[1]);
+	index = p_idx;
+
+	/* Change bus frequency */
+	ret = busfreq_target(exynos4_busfreq_table, ppcload,
+		ppmuload, p_idx, &index);
+	if (ret)
+		pr_err("%s: (%d)\n", __func__, ret);
+
+#ifdef SYSFS_DEBUG_BUSFREQ
+	curjiffies = jiffies;
+	if (prejiffies != 0)
+		level_state_jiffies = curjiffies - prejiffies;
+	else
+		level_state_jiffies = 0;
+
+	prejiffies = jiffies;
+
+	switch (p_idx) {
+	case LV_0:
+		time_in_state[LV_0] += level_state_jiffies;
+		break;
+	case LV_1:
+		time_in_state[LV_1] += level_state_jiffies;
+		break;
+	case LV_2:
+		time_in_state[LV_2] += level_state_jiffies;
+		break;
+	default:
+		break;
+	}
+#endif
+
+out:
+	pr_debug("Bus freq(%d-%d)\n", p_idx, index);
+
+	busfreq_mon_reset();
+
+	return index;
+}
+
+static int exynos4_busfreq_notifier_event(struct notifier_block *this,
+		unsigned long event, void *ptr)
+{
+	unsigned int voltage;
+
+	switch (event) {
+	case CPUFREQ_PRECHANGE:
+		freqs = (struct cpufreq_freqs *)ptr;
+		curr_idx = busfreq_monitor();
+		break;
+	case CPUFREQ_POSTCHANGE:
+		voltage = exynos4_busfreq_table[curr_idx].volt;
+		if (p_idx > curr_idx)
+			regulator_set_voltage(int_regulator, voltage,
+					voltage);
+
+		if (p_idx != curr_idx) {
+#ifdef CONFIG_BUSFREQ_QOS
+			exynos4_set_qos(curr_idx);
+#endif
+			exynos4_set_busfreq(curr_idx);
+		}
+
+		if (p_idx < curr_idx)
+			regulator_set_voltage(int_regulator, voltage,
+					voltage);
+		p_idx = curr_idx;
+		break;
+	case CPUFREQ_RESUMECHANGE:
+		break;
+	default:
+		/* ignore */
+		break;
+	}
+
+	return NOTIFY_OK;
+}
+
+static struct notifier_block exynos4_busfreq_notifier = {
+	.notifier_call = exynos4_busfreq_notifier_event,
+};
+
+static int exynos4_buspm_notifier_event(struct notifier_block *this,
+		unsigned long event, void *ptr)
+{
+	switch (event) {
+	case PM_SUSPEND_PREPARE:
+		exynos4_busfreq_lock(DVFS_LOCK_ID_PM, BUS_L0);
+		return NOTIFY_OK;
+	case PM_POST_RESTORE:
+	case PM_POST_SUSPEND:
+		exynos4_busfreq_lock_free(DVFS_LOCK_ID_PM);
+		busfreq_mon_reset();
+		return NOTIFY_OK;
+	}
+	return NOTIFY_DONE;
+}
+
+static struct notifier_block exynos4_buspm_notifier = {
+	.notifier_call = exynos4_buspm_notifier_event,
+};
+
+static int exynos4_busfreq_reboot_notify(struct notifier_block *this,
+		unsigned long code, void *unused)
+{
+	if (exynos4_busfreq_lock(DVFS_LOCK_ID_PM, BUS_L0) < 0)
+		return NOTIFY_BAD;
+
+	printk(KERN_INFO "REBOOT Notifier for BUSFREQ\n");
+	return NOTIFY_DONE;
+}
+
+static struct notifier_block exynos4_busfreq_reboot_notifier = {
+	.notifier_call = exynos4_busfreq_reboot_notify,
+};
+
+#ifdef CONFIG_BUSFREQ_QOS
+static int exynos4_bus_qos_notify(struct notifier_block *nb,
+		unsigned long l, void *v)
+{
+	busfreq_qos = (int)l;
+	printk(KERN_INFO "exynos4_bus_qos_notify table %d\n", busfreq_qos);
+	exynos4_set_qos(curr_idx);
+
+	return NOTIFY_OK;
+}
+
+static struct notifier_block exynos4_busqos_notifier = {
+	.notifier_call = exynos4_bus_qos_notify,
+};
+#endif
+
+int exynos4_busfreq_lock(unsigned int nId,
+	enum busfreq_level_request busfreq_level)
+{
+	int ret = 0;
+	unsigned int int_volt;
+
+	if (!init_done) {
+		pr_debug("Busfreq does not support on this system\n");
+		return -ENODEV;
+	}
+
+	mutex_lock(&set_bus_freq_lock);
+	if (g_busfreq_lock_id & (1 << nId)) {
+		pr_err("This device [%d] already locked busfreq\n", nId);
+		ret = -EINVAL;
+		goto err;
+	}
+	g_busfreq_lock_id |= (1 << nId);
+	g_busfreq_lock_val[nId] = busfreq_level;
+
+	/* If the requested cpufreq is higher than current min frequency */
+	if (busfreq_level < g_busfreq_lock_level) {
+		g_busfreq_lock_level = busfreq_level;
+		/* get the voltage value */
+		int_volt = exynos4_busfreq_table[busfreq_level].volt;
+#ifdef CONFIG_BUSFREQ_QOS
+		exynos4_set_qos(curr_idx);
+#endif
+		regulator_set_voltage(int_regulator, int_volt,
+				int_volt);
+		exynos4_set_busfreq(busfreq_level);
+	}
+err:
+	mutex_unlock(&set_bus_freq_lock);
+
+	return ret;
+}
+
+void exynos4_busfreq_lock_free(unsigned int nId)
+{
+	unsigned int i;
+
+	if (!init_done) {
+		pr_debug("Busfreq does not support on this system\n");
+		return;
+	}
+
+	mutex_lock(&set_bus_freq_lock);
+	g_busfreq_lock_id &= ~(1 << nId);
+	g_busfreq_lock_val[nId] = BUS_LEVEL_END - 1;
+	g_busfreq_lock_level = BUS_LEVEL_END - 1;
+
+	if (g_busfreq_lock_id) {
+		for (i = 0; i < DVFS_LOCK_ID_END; i++) {
+			if (g_busfreq_lock_val[i] < g_busfreq_lock_level)
+				g_busfreq_lock_level = g_busfreq_lock_val[i];
+		}
+	}
+	mutex_unlock(&set_bus_freq_lock);
+}
+
+void exynos4_request_apply(unsigned long freq, struct device *dev)
+{
+	/* not supported yet */
+}
+
+static void __init exynos4_set_bus_volt(void)
+{
+	unsigned int asv_group;
+	unsigned int i;
+
+	asv_group = exynos_result_of_asv & 0xF;
+
+	printk(KERN_INFO "DVFS : VDD_INT Voltage table set with %d Group\n", asv_group);
+
+	for (i = 0 ; i < LV_END ; i++) {
+
+		switch (asv_group) {
+		case 0:
+			exynos4_busfreq_table[i].volt =
+				exynos4_asv_volt[0][i];
+			break;
+		case 1:
+		case 2:
+			exynos4_busfreq_table[i].volt =
+				exynos4_asv_volt[1][i];
+			break;
+		case 3:
+		case 4:
+			exynos4_busfreq_table[i].volt =
+				exynos4_asv_volt[2][i];
+			break;
+		case 5:
+		case 6:
+			exynos4_busfreq_table[i].volt =
+				exynos4_asv_volt[3][i];
+			break;
+		case 7:
+			exynos4_busfreq_table[i].volt =
+				exynos4_asv_volt[4][i];
+			break;
+		}
+	}
+
+	return;
+}
+
+#ifdef SYSFS_DEBUG_BUSFREQ
+static ssize_t show_time_in_state(struct kobject *kobj,
+		struct attribute *attr, char *buf)
+{
+	ssize_t len = 0;
+	int i;
+
+	for (i = 0; i < LV_END; i++)
+		len += sprintf(buf + len, "%u: %u\n",
+			exynos4_busfreq_table[i].mem_clk, time_in_state[i]);
+
+	return len;
+}
+
+static ssize_t store_time_in_state(struct kobject *kobj,
+		struct attribute *attr, const char *buf, size_t count)
+{
+	return count;
+}
+
+static struct global_attr busfreq_time_in_state_attr = __ATTR(busfreq_time_in_state,
+		0644, show_time_in_state, store_time_in_state);
+
+static ssize_t show_up_threshold(struct kobject *kobj,
+		struct attribute *attr, char *buf)
+{
+	return sprintf(buf, "%u\n", up_threshold);
+}
+
+static ssize_t store_up_threshold(struct kobject *kobj,
+		struct attribute *attr, const char *buf, size_t count)
+{
+	int ret;
+
+	ret = sscanf(buf, "%u", &up_threshold);
+	if (ret != 1)
+		return -EINVAL;
+	printk(KERN_ERR "** Up_Threshold is changed to %u **\n", up_threshold);
+
+	return count;
+}
+
+static struct global_attr busfreq_up_threshold_attr = __ATTR(busfreq_up_threshold,
+		0644, show_up_threshold, store_up_threshold);
+
+static ssize_t show_busfreq_level_lock(struct kobject *kobj,
+		struct attribute *attr, char *buf)
+{
+	return sprintf(buf, "%d\n", g_busfreq_lock_level);
+}
+
+static ssize_t store_busfreq_level_lock(struct kobject *kobj,
+		struct attribute *attr, const char *buf, size_t count)
+{
+	int level;
+	sscanf(buf, "%d", &level);
+	if (level >= BUS_LEVEL_END)
+		return -EINVAL;
+
+	if (level < 0)
+		exynos4_busfreq_lock_free(DVFS_LOCK_ID_USER);
+	else
+		exynos4_busfreq_lock(DVFS_LOCK_ID_USER, level);
+	return count;
+}
+
+static struct global_attr busfreq_level__lock_attr = __ATTR(busfreq_level_lock,
+		0644, show_busfreq_level_lock, store_busfreq_level_lock);
+
+static ssize_t show_busfreq_level(struct kobject *kobj,
+		struct attribute *attr, char *buf)
+{
+	int i;
+	int ret = 0;
+	ret = sprintf(buf, "Lock Name = ");
+	for (i = 0; i < DVFS_LOCK_ID_END; i++) {
+		if (g_busfreq_lock_id & (1 << i))
+			ret += sprintf(&buf[ret], "%s - %d\n",
+				cpufreq_lock_name[i], g_busfreq_lock_val[i]);
+	}
+	ret += sprintf(&buf[ret], "\nCurrent Busfreq Level : %d\n", p_idx);
+	return ret;
+}
+
+static struct global_attr busfreq_level_attr = __ATTR(busfreq_current_level,
+		S_IRUGO, show_busfreq_level, NULL);
+#endif
+
+static int __init busfreq_mon_init(void)
+{
+	unsigned int i;
+	unsigned int tmp;
+	unsigned int val;
+	struct clk *ppmu_clk = NULL;
+
+	if (!soc_is_exynos4210())
+		return -ENODEV;
+
+	val = __raw_readl(S5P_VA_DMC0 + 0x4);
+	val = (val >> 8) & 0xf;
+
+	/* Check Memory Type Only support -> 0x5: 0xLPDDR2 */
+	if (val != 0x05) {
+		pr_err("[ %x ] Memory Type Undertermined.\n", val);
+		return -ENODEV;
+	}
+
+	init_done = true;
+
+	for (i = 0; i < DVFS_LOCK_ID_END; i++)
+		g_busfreq_lock_val[i] = BUS_LEVEL_END - 1;
+
+	g_busfreq_lock_level = BUS_LEVEL_END - 1;
+
+	cpu.hw_base = S5P_VA_PPMU_CPU;
+	cpu.weight = 1;
+	cpu.event[3] = 0x7;
+
+	dmc[DMC0].hw_base = S5P_VA_DMC0;
+	dmc[DMC0].weight = 1;
+	dmc[DMC1].hw_base = S5P_VA_DMC1;
+	dmc[DMC1].weight = 1;
+
+	p_idx = LV_0;
+	up_threshold = UP_THRESHOLD_DEFAULT;
+
+	tmp = __raw_readl(EXYNOS4_CLKDIV_DMC0);
+
+	for (i = 0; i <  LV_END; i++) {
+		tmp &= ~(EXYNOS4_CLKDIV_DMC0_ACP_MASK |
+			EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK |
+			EXYNOS4_CLKDIV_DMC0_DPHY_MASK |
+			EXYNOS4_CLKDIV_DMC0_DMC_MASK |
+			EXYNOS4_CLKDIV_DMC0_DMCD_MASK |
+			EXYNOS4_CLKDIV_DMC0_DMCP_MASK |
+			EXYNOS4_CLKDIV_DMC0_COPY2_MASK |
+			EXYNOS4_CLKDIV_DMC0_CORETI_MASK);
+
+		tmp |= ((clkdiv_dmc0[i][0] << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT) |
+			(clkdiv_dmc0[i][1] << EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT) |
+			(clkdiv_dmc0[i][2] << EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT) |
+			(clkdiv_dmc0[i][3] << EXYNOS4_CLKDIV_DMC0_DMC_SHIFT) |
+			(clkdiv_dmc0[i][4] << EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT) |
+			(clkdiv_dmc0[i][5] << EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT) |
+			(clkdiv_dmc0[i][6] << EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT) |
+			(clkdiv_dmc0[i][7] << EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT));
+
+		exynos4_busfreq_table[i].clk_dmcdiv = tmp;
+	}
+
+	tmp = __raw_readl(EXYNOS4_CLKDIV_TOP);
+
+	for (i = 0; i <  LV_END; i++) {
+		tmp &= ~(EXYNOS4_CLKDIV_TOP_ACLK200_MASK |
+			EXYNOS4_CLKDIV_TOP_ACLK100_MASK |
+			EXYNOS4_CLKDIV_TOP_ACLK160_MASK |
+			EXYNOS4_CLKDIV_TOP_ACLK133_MASK |
+			EXYNOS4_CLKDIV_TOP_ONENAND_MASK);
+
+		tmp |= ((clkdiv_top[i][0] << EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT) |
+			(clkdiv_top[i][1] << EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT) |
+			(clkdiv_top[i][2] << EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT) |
+			(clkdiv_top[i][3] << EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT) |
+			(clkdiv_top[i][4] << EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT));
+
+		exynos4_busfreq_table[i].clk_topdiv = tmp;
+	}
+
+	exynos4_set_bus_volt();
+
+	int_regulator = regulator_get(NULL, "vdd_int");
+	if (IS_ERR(int_regulator)) {
+		pr_err("failed to get resource %s\n", "vdd_int");
+		return -ENODEV;
+	}
+
+	/* PPMUs using for cpufreq get clk from clk_list */
+	ppmu_clk = clk_get(NULL, "ppmudmc0");
+	if (IS_ERR(ppmu_clk)) {
+		pr_err("Failed to get ppmudmc0 clock\n");
+		goto err_clk;
+	}
+	clk_enable(ppmu_clk);
+	clk_put(ppmu_clk);
+
+	ppmu_clk = clk_get(NULL, "ppmudmc1");
+	if (IS_ERR(ppmu_clk)) {
+		pr_err("Failed to get ppmudmc1 clock\n");
+		goto err_clk;
+	}
+	clk_enable(ppmu_clk);
+	clk_put(ppmu_clk);
+
+	ppmu_clk = clk_get(NULL, "ppmucpu");
+	if (IS_ERR(ppmu_clk)) {
+		pr_err("Failed to get ppmucpu clock\n");
+		goto err_clk;
+	}
+	clk_enable(ppmu_clk);
+	clk_put(ppmu_clk);
+
+	busfreq_mon_reset();
+
+	if (cpufreq_register_notifier(&exynos4_busfreq_notifier,
+				CPUFREQ_TRANSITION_NOTIFIER)) {
+		pr_err("Failed to setup cpufreq notifier\n");
+		goto err_cpufreq;
+	}
+
+	if (register_pm_notifier(&exynos4_buspm_notifier)) {
+		pr_err("Failed to setup buspm notifier\n");
+		goto err_pm;
+	}
+
+	if (register_reboot_notifier(&exynos4_busfreq_reboot_notifier))
+		pr_err("Failed to setup reboot notifier\n");
+
+#ifdef SYSFS_DEBUG_BUSFREQ
+	if (sysfs_create_file(cpufreq_global_kobject,
+			&busfreq_level__lock_attr.attr))
+		pr_err("Failed to create sysfs file(lock)\n");
+
+	if (sysfs_create_file(cpufreq_global_kobject,
+			&busfreq_time_in_state_attr.attr))
+		pr_err("Failed to create sysfs file(time_in_state)\n");
+
+	if (sysfs_create_file(cpufreq_global_kobject,
+			&busfreq_up_threshold_attr.attr))
+		pr_err("Failed to create sysfs file(up_threshold)\n");
+
+	if (sysfs_create_file(cpufreq_global_kobject, &busfreq_level_attr.attr))
+		pr_err("Failed to create sysfs file(level)\n");
+#endif
+#ifdef CONFIG_BUSFREQ_QOS
+	pm_qos_add_notifier(PM_QOS_BUS_QOS, &exynos4_busqos_notifier);
+#endif
+
+	return 0;
+
+err_pm:
+	cpufreq_unregister_notifier(&exynos4_busfreq_notifier,
+				CPUFREQ_TRANSITION_NOTIFIER);
+err_cpufreq:
+err_clk:
+	if (!IS_ERR(int_regulator))
+		regulator_put(int_regulator);
+
+	return -ENODEV;
+}
+late_initcall(busfreq_mon_init);
diff --git a/arch/arm/mach-exynos/busfreq_opp_4210.c b/arch/arm/mach-exynos/busfreq_opp_4210.c
new file mode 100644
index 0000000..d566fea
--- /dev/null
+++ b/arch/arm/mach-exynos/busfreq_opp_4210.c
@@ -0,0 +1,298 @@
+/* linux/arch/arm/mach-exynos/busfreq_opp_4210.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * EXYNOS4 - BUS clock frequency scaling support with OPP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/types.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/regulator/consumer.h>
+#include <linux/sysfs.h>
+#include <linux/platform_device.h>
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/cpu.h>
+#include <linux/ktime.h>
+#include <linux/tick.h>
+#include <linux/kernel_stat.h>
+#include <linux/reboot.h>
+#include <linux/slab.h>
+#include <linux/opp.h>
+#include <mach/busfreq.h>
+
+#include <asm/mach-types.h>
+
+#include <mach/ppmu.h>
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/gpio.h>
+#include <mach/regs-mem.h>
+#include <mach/cpufreq.h>
+#include <mach/dev.h>
+#include <mach/asv.h>
+
+#include <plat/map-s5p.h>
+#include <plat/gpio-cfg.h>
+
+enum busfreq_level_idx {
+	LV_0,
+	LV_1,
+	LV_2,
+	LV_END
+};
+
+static struct busfreq_table exynos4_busfreq_table[] = {
+	{LV_0, 400000, 1100000, 0, 0, 0},
+	{LV_1, 267000, 1000000, 0, 0, 0},
+	{LV_2, 133000, 950000, 0, 0, 0},
+	{0, 0, 0, 0, 0, 0},
+};
+
+#define ASV_GROUP	5
+static unsigned int exynos4_asv_volt[ASV_GROUP][LV_END] = {
+	{1150000, 1050000, 1000000},
+	{1125000, 1025000, 1000000},
+	{1100000, 1000000, 975000},
+	{1075000, 975000, 950000},
+	{1050000, 950000, 950000},
+};
+
+static unsigned int clkdiv_dmc0[LV_END][8] = {
+	/*
+	 * Clock divider value for following
+	 * { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD
+	 *              DIVDMCP, DIVCOPY2, DIVCORE_TIMERS }
+	 */
+
+	/* DMC L0: 400MHz */
+	{3, 1, 1, 1, 1, 1, 3, 1},
+
+	/* DMC L1: 266.7MHz */
+	{4, 1, 1, 2, 1, 1, 3, 1},
+
+	/* DMC L2: 133MHz */
+	{5, 1, 1, 5, 1, 1, 3, 1},
+};
+
+static unsigned int clkdiv_top[LV_END][5] = {
+	/*
+	 * Clock divider value for following
+	 * { DIVACLK200, DIVACLK100, DIVACLK160, DIVACLK133, DIVONENAND }
+	 */
+
+	/* ACLK200 L0: 200MHz */
+	{3, 7, 4, 5, 1},
+
+	/* ACLK200 L1: 160MHz */
+	{4, 7, 5, 6, 1},
+
+	/* ACLK200 L2: 133MHz */
+	{5, 7, 7, 7, 1},
+};
+
+static unsigned int clkdiv_lr_bus[LV_END][2] = {
+	/*
+	 * Clock divider value for following
+	 * { DIVGDL/R, DIVGPL/R }
+	 */
+
+	/* ACLK_GDL/R L1: 200MHz */
+	{3, 1},
+
+	/* ACLK_GDL/R L2: 160MHz */
+	{4, 1},
+
+	/* ACLK_GDL/R L3: 133MHz */
+	{5, 1},
+};
+
+static void exynos4210_set_bus_volt(void)
+{
+	unsigned int asv_group;
+	unsigned int i;
+
+	asv_group = exynos_asv->asv_result & 0xF;
+
+	asv_group = 0;
+	printk(KERN_INFO "DVFS : VDD_INT Voltage table set with %d Group\n", asv_group);
+
+	for (i = 0 ; i < LV_END ; i++) {
+		switch (asv_group) {
+		case 0:
+			exynos4_busfreq_table[i].volt =
+				exynos4_asv_volt[0][i];
+			break;
+		case 1:
+		case 2:
+			exynos4_busfreq_table[i].volt =
+				exynos4_asv_volt[1][i];
+			break;
+		case 3:
+		case 4:
+			exynos4_busfreq_table[i].volt =
+				exynos4_asv_volt[2][i];
+			break;
+		case 5:
+		case 6:
+			exynos4_busfreq_table[i].volt =
+				exynos4_asv_volt[3][i];
+			break;
+		case 7:
+			exynos4_busfreq_table[i].volt =
+				exynos4_asv_volt[4][i];
+			break;
+		}
+	}
+
+	return;
+}
+
+unsigned int exynos4210_target(unsigned int div_index)
+{
+	unsigned int tmp;
+
+	/* Change Divider - DMC0 */
+	tmp = exynos4_busfreq_table[div_index].clk_dmc0div;
+
+	__raw_writel(tmp, EXYNOS4_CLKDIV_DMC0);
+
+	do {
+		tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC0);
+	} while (tmp & 0x11111111);
+
+	/* Change Divider - TOP */
+	tmp = exynos4_busfreq_table[div_index].clk_topdiv;
+
+	__raw_writel(tmp, EXYNOS4_CLKDIV_TOP);
+
+	do {
+		tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_TOP);
+	} while (tmp & 0x11111);
+
+	/* Change Divider - LEFTBUS */
+	tmp = __raw_readl(EXYNOS4_CLKDIV_LEFTBUS);
+
+	tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK);
+
+	tmp |= ((clkdiv_lr_bus[div_index][0] << EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) |
+		(clkdiv_lr_bus[div_index][1] << EXYNOS4_CLKDIV_BUS_GPLR_SHIFT));
+
+	__raw_writel(tmp, EXYNOS4_CLKDIV_LEFTBUS);
+
+	do {
+		tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_LEFTBUS);
+	} while (tmp & 0x11);
+
+	/* Change Divider - RIGHTBUS */
+	tmp = __raw_readl(EXYNOS4_CLKDIV_RIGHTBUS);
+
+	tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK);
+
+	tmp |= ((clkdiv_lr_bus[div_index][0] << EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) |
+		(clkdiv_lr_bus[div_index][1] << EXYNOS4_CLKDIV_BUS_GPLR_SHIFT));
+
+	__raw_writel(tmp, EXYNOS4_CLKDIV_RIGHTBUS);
+
+	do {
+		tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_RIGHTBUS);
+	} while (tmp & 0x11);
+
+	return div_index;
+}
+
+unsigned int exynos4210_get_table_index(struct opp *opp)
+{
+	unsigned int index;
+
+	for (index = LV_0; index < LV_END; index++)
+		if (opp_get_freq(opp) == exynos4_busfreq_table[index].mem_clk)
+			break;
+
+	return index;
+}
+
+int exynos4210_init(struct device *dev, struct busfreq_data *data)
+{
+	unsigned int i;
+	unsigned int tmp;
+	unsigned long maxfreq = UINT_MAX;
+	int ret;
+
+	tmp = __raw_readl(EXYNOS4_CLKDIV_DMC0);
+
+	for (i = 0; i <  LV_END; i++) {
+		tmp &= ~(EXYNOS4_CLKDIV_DMC0_ACP_MASK |
+			EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK |
+			EXYNOS4_CLKDIV_DMC0_DPHY_MASK |
+			EXYNOS4_CLKDIV_DMC0_DMC_MASK |
+			EXYNOS4_CLKDIV_DMC0_DMCD_MASK |
+			EXYNOS4_CLKDIV_DMC0_DMCP_MASK |
+			EXYNOS4_CLKDIV_DMC0_COPY2_MASK |
+			EXYNOS4_CLKDIV_DMC0_CORETI_MASK);
+
+		tmp |= ((clkdiv_dmc0[i][0] << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT) |
+			(clkdiv_dmc0[i][1] << EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT) |
+			(clkdiv_dmc0[i][2] << EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT) |
+			(clkdiv_dmc0[i][3] << EXYNOS4_CLKDIV_DMC0_DMC_SHIFT) |
+			(clkdiv_dmc0[i][4] << EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT) |
+			(clkdiv_dmc0[i][5] << EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT) |
+			(clkdiv_dmc0[i][6] << EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT) |
+			(clkdiv_dmc0[i][7] << EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT));
+
+		exynos4_busfreq_table[i].clk_dmc0div = tmp;
+	}
+
+	tmp = __raw_readl(EXYNOS4_CLKDIV_TOP);
+
+	for (i = 0; i <  LV_END; i++) {
+		tmp &= ~(EXYNOS4_CLKDIV_TOP_ACLK200_MASK |
+			EXYNOS4_CLKDIV_TOP_ACLK100_MASK |
+			EXYNOS4_CLKDIV_TOP_ACLK160_MASK |
+			EXYNOS4_CLKDIV_TOP_ACLK133_MASK |
+			EXYNOS4_CLKDIV_TOP_ONENAND_MASK);
+
+		tmp |= ((clkdiv_top[i][0] << EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT) |
+			(clkdiv_top[i][1] << EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT) |
+			(clkdiv_top[i][2] << EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT) |
+			(clkdiv_top[i][3] << EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT) |
+			(clkdiv_top[i][4] << EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT));
+
+		exynos4_busfreq_table[i].clk_topdiv = tmp;
+	}
+
+	exynos4210_set_bus_volt();
+
+	for (i = 0; i < LV_END; i++) {
+		ret = opp_add(dev, exynos4_busfreq_table[i].mem_clk,
+				exynos4_busfreq_table[i].volt);
+		if (ret) {
+			dev_err(dev, "Fail to add opp entries.\n");
+			return ret;
+		}
+	}
+
+	data->table = exynos4_busfreq_table;
+	data->table_size = LV_END;
+
+	/* Find max frequency */
+	data->max_opp = opp_find_freq_floor(dev, &maxfreq);
+
+	data->vdd_int = regulator_get(NULL, "vdd_int");
+	if (IS_ERR(data->vdd_int)) {
+		pr_err("failed to get resource %s\n", "vdd_int");
+		return -ENODEV;
+	}
+
+	data->vdd_mif = ERR_PTR(-ENODEV);
+
+	return 0;
+}
diff --git a/arch/arm/mach-exynos/busfreq_opp_4x12.c b/arch/arm/mach-exynos/busfreq_opp_4x12.c
new file mode 100644
index 0000000..5f310ba
--- /dev/null
+++ b/arch/arm/mach-exynos/busfreq_opp_4x12.c
@@ -0,0 +1,939 @@
+/* linux/arch/arm/mach-exynos/busfreq_opp_4x12.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * EXYNOS4 - BUS clock frequency scaling support with OPP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/types.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/regulator/consumer.h>
+#include <linux/sysfs.h>
+#include <linux/platform_device.h>
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/cpu.h>
+#include <linux/ktime.h>
+#include <linux/tick.h>
+#include <linux/kernel_stat.h>
+#include <linux/reboot.h>
+#include <linux/slab.h>
+#include <linux/opp.h>
+#include <linux/clk.h>
+#include <linux/cpufreq.h>
+#include <linux/pm_qos_params.h>
+
+#include <mach/busfreq_exynos4.h>
+
+#include <asm/mach-types.h>
+
+#include <mach/ppmu.h>
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/gpio.h>
+#include <mach/regs-mem.h>
+#include <mach/dev.h>
+#include <mach/asv.h>
+#include <mach/smc.h>
+
+#include <plat/map-s5p.h>
+#include <plat/gpio-cfg.h>
+#include <plat/cpu.h>
+
+#define UP_THRESHOLD			30
+#define IDLE_THRESHOLD			4
+#define UP_CPU_THRESHOLD		11
+#define MAX_CPU_THRESHOLD		20
+#define CPU_SLOPE_SIZE			7
+#define PPMU_THRESHOLD                 5
+
+unsigned int up_threshold        = UP_THRESHOLD;
+unsigned int ppmu_threshold      = PPMU_THRESHOLD;
+unsigned int idle_threshold      = IDLE_THRESHOLD;
+unsigned int up_cpu_threshold    = UP_CPU_THRESHOLD;
+unsigned int max_cpu_threshold   = MAX_CPU_THRESHOLD;
+unsigned int cpu_slope_size      = CPU_SLOPE_SIZE;
+unsigned int dmc_max_threshold;
+unsigned int load_history_size   = LOAD_HISTORY_SIZE;
+
+/* To save/restore DMC_PAUSE_CTRL register */
+static unsigned int dmc_pause_ctrl;
+
+enum busfreq_level_idx {
+	LV_0,
+	LV_1,
+	LV_2,
+	LV_3,
+	LV_4,
+	LV_5,
+	LV_6,
+	LV_END
+};
+
+static struct busfreq_table exynos4_busfreq_table[] = {
+	{LV_0, 400266, 1100000, 0, 0, 0}, /* MIF : 400MHz INT : 200MHz */
+	{LV_1, 400200, 1100000, 0, 0, 0}, /* MIF : 400MHz INT : 200MHz */
+	{LV_2, 267200, 1000000, 0, 0, 0}, /* MIF : 267MHz INT : 200MHz */
+	{LV_3, 267160, 1000000, 0, 0, 0}, /* MIF : 267MHz INT : 160MHz */
+	{LV_4, 160160, 950000, 0, 0, 0},  /* MIF : 160MHz INT : 160MHz */
+	{LV_5, 133133, 950000, 0, 0, 0},  /* MIF : 133MHz INT : 133MHz */
+	{LV_6, 100100, 950000, 0, 0, 0},  /* MIF : 100MHz INT : 100MHz */
+};
+
+enum busfreq_qos_target {
+	BUS_QOS_0,
+	BUS_QOS_1,
+	BUS_QOS_MAX,
+};
+
+static enum busfreq_qos_target busfreq_qos = BUS_QOS_0;
+
+#if defined(CONFIG_BUSFREQ_QOS_1280X800) /* P4NOTE */
+static unsigned int exynos4_qos_value[BUS_QOS_MAX][LV_END][4] = {
+	{
+		{0x00, 0x00, 0x00, 0x00},
+		{0x00, 0x00, 0x00, 0x00},
+		{0x06, 0x03, 0x06, 0x0e},
+		{0x06, 0x03, 0x06, 0x0e},
+		{0x03, 0x03, 0x03, 0x0e},
+		{0x03, 0x03, 0x03, 0x0e},
+		{0x03, 0x0B, 0x00, 0x00},
+	},
+	{
+		{0x06, 0x0b, 0x06, 0x0f},
+		{0x06, 0x0b, 0x06, 0x0f},
+		{0x06, 0x0b, 0x06, 0x0f},
+		{0x06, 0x0b, 0x06, 0x0f},
+		{0x06, 0x03, 0x06, 0x0e},
+		{0x04, 0x03, 0x04, 0x0e},
+		{0x03, 0x0b, 0x00, 0x00},
+	},
+};
+#else
+static unsigned int exynos4_qos_value[BUS_QOS_MAX][LV_END][4] = {
+	{
+		{0x00, 0x00, 0x00, 0x00},
+		{0x00, 0x00, 0x00, 0x00},
+		{0x00, 0x00, 0x00, 0x00},
+		{0x00, 0x00, 0x00, 0x00},
+		{0x06, 0x03, 0x06, 0x0e},
+		{0x04, 0x03, 0x04, 0x0e},
+		{0x03, 0x0B, 0x00, 0x00},
+	},
+	{
+		{0x06, 0x0b, 0x06, 0x0f},
+		{0x06, 0x0b, 0x06, 0x0f},
+		{0x06, 0x0b, 0x06, 0x0f},
+		{0x06, 0x0b, 0x06, 0x0f},
+		{0x06, 0x03, 0x06, 0x0e},
+		{0x04, 0x03, 0x04, 0x0e},
+		{0x03, 0x0b, 0x00, 0x00},
+	},
+};
+#endif
+
+#define ASV_GROUP	12
+
+static unsigned int asv_group_index;
+
+static unsigned int (*exynos4_mif_volt)[LV_END];
+static unsigned int (*exynos4_int_volt)[LV_END];
+
+static unsigned int exynos4212_mif_volt[ASV_GROUP][LV_END] = {
+	/* 400      400      267      267      160     133     100 */
+	{1012500, 1012500, 962500,  962500,  912500, 912500, 912500}, /* RESERVED */
+	{1000000, 1000000, 950000,  950000,  900000, 900000, 900000}, /* ASV1 */
+	{1000000, 1000000, 950000,  950000,  900000, 900000, 900000}, /* ASV2 */
+	{1000000, 1000000, 950000,  950000,  900000, 900000, 900000}, /* ASV3 */
+	{1050000, 1050000, 1000000,  1000000,  900000, 900000, 900000}, /* ASV4 */
+	{1000000, 1000000, 950000,  950000,  900000, 900000, 900000}, /* ASV5 */
+	{1000000, 1000000, 950000,  950000,  900000, 900000, 900000}, /* ASV6 */
+	{950000, 950000, 900000,  900000,  900000, 900000, 900000}, /* ASV7 */
+	{950000, 950000, 900000,  900000,  900000, 900000, 850000}, /* ASV8 */
+	{950000, 950000, 900000,  900000,  900000, 900000, 850000}, /* ASV9 */
+	{950000, 950000, 900000,  900000,  900000, 850000, 850000}, /* ASV10 */
+	{937500, 937500, 887500,  887500,  887500, 850000, 850000}, /* RESERVED */
+};
+
+static unsigned int exynos4212_int_volt[ASV_GROUP][LV_END] = {
+	/* 266      200       200     160    160      133     100 */
+	{1300000, 1250000, 1250000, 950000, 950000, 912500, 887500}, /* RESERVED */
+	{1062500, 1012500, 1012500, 937500, 937500, 900000, 875000}, /* ASV1 */
+	{1050000, 1000000, 1000000, 925000, 925000, 887500, 875000}, /* ASV2 */
+	{1050000, 1000000, 1000000, 912500, 912500, 887500, 875000}, /* ASV3 */
+	{1062500, 1012500, 1012500, 925000, 925000, 900000, 875000}, /* ASV4 */
+	{1050000, 1000000, 1000000, 925000, 925000, 887500, 875000}, /* ASV5 */
+	{1050000, 1000000, 1000000, 912500, 912500, 887500, 875000}, /* ASV6 */
+	{1037500, 987500, 987500, 912500, 912500, 875000, 875000}, /* ASV7 */
+	{1037500, 987500, 987500, 900000, 900000, 875000, 875000}, /* ASV8 */
+	{1037500, 987500, 987500, 900000, 900000, 875000, 875000}, /* ASV9 */
+	{1037500, 987500, 987500, 900000, 900000, 862500, 850000}, /* ASV10 */
+	{1035000, 975000, 975000, 887500, 887500, 850000, 850000}, /* RESERVED */
+};
+#if 0
+/* 20120105 DVFS table */
+static unsigned int exynos4412_mif_volt[ASV_GROUP][LV_END] = {
+	/* 400      267      267      160     133     100 */
+	{1100000, 1000000, 1000000, 950000, 950000, 950000}, /* ASV 0 */
+	{1050000,  950000,  950000, 900000, 900000, 900000}, /* ASV 1 */
+	{1050000,  950000,  950000, 900000, 900000, 900000}, /* ASV 2 */
+	{1050000,  950000,  950000, 900000, 900000, 900000}, /* ASV 3 */
+	{1050000,  950000,  950000, 900000, 900000, 900000}, /* ASV 4 */
+	{1000000,  950000,  950000, 900000, 900000, 900000}, /* ASV 5 */
+	{1000000,  950000,  950000, 900000, 900000, 900000}, /* ASV 6 */
+	{1000000,  950000,  950000, 900000, 900000, 900000}, /* ASV 7 */
+	{1000000,  950000,  950000, 900000, 900000, 900000}, /* ASV 8 */
+	{1000000,  950000,  950000, 900000, 900000, 850000}, /* ASV 9 */
+	{1000000,  900000,  900000, 900000, 900000, 850000}, /* ASV10 */
+	{1000000,  900000,  900000, 900000, 900000, 850000}, /* ASV11 */
+};
+
+static unsigned int exynos4412_int_volt[ASV_GROUP][LV_END] = {
+	/* 200      200     160    160      133     100 */
+	{1062500, 1062500, 975000, 975000, 925000, 900000}, /* ASV 0 */
+	{1050000, 1050000, 962500, 962500, 912500, 887500}, /* ASV 1 */
+	{1037500, 1037500, 950000, 950000, 900000, 875000}, /* ASV 2 */
+	{1025000, 1025000, 950000, 950000, 875000, 862500}, /* ASV 3 */
+	{1025000, 1025000, 937500, 937500, 875000, 862500}, /* ASV 4 */
+	{1012500, 1012500, 937500, 937500, 862500, 850000}, /* ASV 5 */
+	{1012500, 1012500, 925000, 925000, 862500, 850000}, /* ASV 6 */
+	{1000000, 1000000, 925000, 925000, 850000, 850000}, /* ASV 7 */
+	{1000000, 1000000, 912500, 912500, 850000, 850000}, /* ASV 8 */
+	{1000000, 1000000, 912500, 912500, 850000, 850000}, /* ASV 9 */
+	{1000000, 1000000, 912500, 912500, 850000, 850000}, /* ASV10 */
+	{ 987500,  987500, 900000, 900000, 837500, 837500}, /* ASV11 */
+
+};
+#else
+/* 20120210 DVFS table */
+static unsigned int exynos4412_mif_volt[ASV_GROUP][LV_END] = {
+	/* 400      400      267      267      160     133     100 */
+	{1100000, 1100000, 1000000, 1000000, 950000, 950000, 950000}, /* RESERVED */
+	{1050000, 1050000, 950000,  950000,  900000, 900000, 900000}, /* RESERVED */
+	{1050000, 1050000, 950000,  950000,  900000, 900000, 900000}, /* ASV2 */
+	{1050000, 1050000, 950000,  950000,  900000, 900000, 900000}, /* ASV3 */
+	{1050000, 1050000, 950000,  950000,  900000, 900000, 900000}, /* ASV4 */
+	{1000000, 1000000, 950000,  950000,  900000, 900000, 900000}, /* ASV5 */
+	{1000000, 1000000, 950000,  950000,  900000, 900000, 900000}, /* ASV6 */
+	{1000000, 1000000, 950000,  950000,  900000, 900000, 900000}, /* ASV7 */
+	{1000000, 1000000, 950000,  950000,  900000, 900000, 900000}, /* ASV8 */
+	{1000000, 1000000, 950000,  950000,  900000, 900000, 850000}, /* ASV9 */
+	{1000000, 1000000, 900000,  900000,  900000, 900000, 850000}, /* ASV10 */
+	{1000000, 1000000, 900000,  900000,  900000, 900000, 850000}, /* RESERVED */
+};
+
+static unsigned int exynos4412_int_volt[ASV_GROUP][LV_END] = {
+  /* GDR : 266       200      200     160    160      133     100 */
+	{1112500, 1062500, 1062500, 975000, 975000, 937500, 900000}, /* RESERVED */
+	{1100000, 1050000, 1050000, 962500, 962500, 925000, 887500}, /* RESERVED */
+	{1075000, 1025000, 1025000, 937500, 937500, 912500, 875000}, /* ASV2 */
+	{1062500, 1012500, 1012500, 937500, 937500, 900000, 862500}, /* ASV3 */
+	{1062500, 1012500, 1012500, 925000, 925000, 900000, 862500}, /* ASV4 */
+	{1050000, 1000000, 1000000, 925000, 925000, 887500, 850000}, /* ASV5 */
+	{1050000, 1000000, 1000000, 912500, 912500, 875000, 850000}, /* ASV6 */
+	{1037500,  987500,  987500, 912500, 912500, 862500, 850000}, /* ASV7 */
+	{1037500,  987500,  987500, 900000, 900000, 862500, 850000}, /* ASV8 */
+	{1037500,  987500,  987500, 900000, 900000, 862500, 850000}, /* ASV9 */
+	{1037500,  987500,  987500, 900000, 900000, 862500, 850000}, /* ASV10 */
+	{1025000,  975000,  975000, 887500, 887500, 850000, 850000}, /* RESERVED */
+};
+
+#endif
+static unsigned int exynos4x12_timingrow[LV_END] = {
+	0x34498691, 0x34498691, 0x24488490, 0x24488490, 0x154882D0, 0x154882D0, 0x0D488210
+};
+
+static unsigned int clkdiv_dmc0[LV_END][6] = {
+	/*
+	 * Clock divider value for following
+	 * { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD
+	 *              DIVDMCP}
+	 */
+
+	/* DMC L0: 400MHz */
+	{3, 1, 1, 1, 1, 1},
+
+	/* DMC L1: 400MHz */
+	{3, 1, 1, 1, 1, 1},
+
+	/* DMC L2: 266.7MHz */
+	{4, 1, 1, 2, 1, 1},
+
+	/* DMC L3: 266.7MHz */
+	{4, 1, 1, 2, 1, 1},
+
+	/* DMC L4: 160MHz */
+	{5, 1, 1, 4, 1, 1},
+
+	/* DMC L5: 133MHz */
+	{5, 1, 1, 5, 1, 1},
+
+	/* DMC L6: 100MHz */
+	{7, 1, 1, 7, 1, 1},
+};
+
+static unsigned int clkdiv_dmc1[LV_END][6] = {
+	/*
+	 * Clock divider value for following
+	 * { G2DACP, DIVC2C, DIVC2C_ACLK }
+	 */
+
+	/* DMC L0: 400MHz */
+	{3, 1, 1},
+
+	/* DMC L1: 400MHz */
+	{3, 1, 1},
+
+	/* DMC L2: 266.7MHz */
+	{4, 2, 1},
+
+	/* DMC L3: 266.7MHz */
+	{4, 2, 1},
+
+	/* DMC L4: 160MHz */
+	{5, 4, 1},
+
+	/* DMC L5: 133MHz */
+	{5, 5, 1},
+
+	/* DMC L6: 100MHz */
+	{7, 7, 1},
+};
+
+static unsigned int clkdiv_top[LV_END][5] = {
+	/*
+	 * Clock divider value for following
+	 * { DIVACLK266_GPS, DIVACLK100, DIVACLK160,
+		DIVACLK133, DIVONENAND }
+	 */
+
+	/* ACLK_GDL/R L0: 266MHz */
+	{2, 7, 4, 5, 1},
+
+	/* ACLK_GDL/R L1: 200MHz */
+	{2, 7, 4, 5, 1},
+
+	/* ACLK_GDL/R L2: 200MHz */
+	{2, 7, 4, 5, 1},
+
+	/* ACLK_GDL/R L3: 160MHz */
+	{4, 7, 5, 7, 1},
+
+	/* ACLK_GDL/R L4: 160MHz */
+	{4, 7, 5, 7, 1},
+
+	/* ACLK_GDL/R L5: 133MHz */
+	{5, 7, 5, 7, 1},
+
+	/* ACLK_GDL/R L6: 100MHz */
+	{7, 7, 7, 7, 1},
+};
+
+static unsigned int clkdiv_l_bus[LV_END][2] = {
+	/*
+	 * Clock divider value for following
+	 * { DIVGDL, DIVGPL }
+	 */
+
+	/* ACLK_GDL L0: 200MHz */
+	{3, 1},
+
+	/* ACLK_GDL L1: 200MHz */
+	{3, 1},
+
+	/* ACLK_GDL L2: 200MHz */
+	{3, 1},
+
+	/* ACLK_GDL L3: 160MHz */
+	{4, 1},
+
+	/* ACLK_GDL L4: 160MHz */
+	{4, 1},
+
+	/* ACLK_GDL L5: 133MHz */
+	{5, 1},
+
+	/* ACLK_GDL L6: 100MHz */
+	{7, 1},
+};
+
+static unsigned int clkdiv_r_bus[LV_END][2] = {
+	/*
+	 * Clock divider value for following
+	 * { DIVGDR, DIVGPR }
+	 */
+
+	/* ACLK_GDR L0: 266MHz */
+	{2, 1},
+
+	/* ACLK_GDR L1: 200MHz */
+	{3, 1},
+
+	/* ACLK_GDR L2: 200MHz */
+	{3, 1},
+
+	/* ACLK_GDR L3: 160MHz */
+	{4, 1},
+
+	/* ACLK_GDR L4: 160MHz */
+	{4, 1},
+
+	/* ACLK_GDR L5: 133MHz */
+	{5, 1},
+
+	/* ACLK_GDR L6: 100MHz */
+	{7, 1},
+};
+
+static unsigned int clkdiv_sclkip[LV_END][3] = {
+	/*
+	 * Clock divider value for following
+	 * { DIVMFC, DIVJPEG, DIVFIMC0~3}
+	 */
+
+	/* SCLK_MFC: 200MHz */
+	{3, 3, 4},
+
+	/* SCLK_MFC: 200MHz */
+	{3, 3, 4},
+
+	/* SCLK_MFC: 200MHz */
+	{3, 3, 4},
+
+	/* SCLK_MFC: 160MHz */
+	{4, 4, 5},
+
+	/* SCLK_MFC: 160MHz */
+	{4, 4, 5},
+
+	/* SCLK_MFC: 133MHz */
+	{5, 5, 5},
+
+	/* SCLK_MFC: 100MHz */
+	{7, 7, 7},
+};
+
+static void exynos4x12_set_bus_volt(void)
+{
+	unsigned int i;
+
+	asv_group_index = exynos_result_of_asv;
+
+	if (asv_group_index == 0xff)
+		asv_group_index = 0;
+
+	printk(KERN_INFO "DVFS : VDD_INT Voltage table set with %d Group\n", asv_group_index);
+
+	for (i = 0 ; i < LV_END ; i++)
+		exynos4_busfreq_table[i].volt =
+			exynos4_mif_volt[asv_group_index][i];
+
+	return;
+}
+
+void exynos4x12_target(int index)
+{
+	unsigned int tmp;
+
+	/* Change Divider - DMC0 */
+	tmp = exynos4_busfreq_table[index].clk_dmc0div;
+
+	__raw_writel(tmp, EXYNOS4_CLKDIV_DMC0);
+
+	do {
+		tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC0);
+	} while (tmp & 0x111111);
+
+	/* Change Divider - DMC1 */
+	tmp = __raw_readl(EXYNOS4_CLKDIV_DMC1);
+
+	tmp &= ~(EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK |
+		EXYNOS4_CLKDIV_DMC1_C2C_MASK |
+		EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK);
+
+	tmp |= ((clkdiv_dmc1[index][0] << EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT) |
+		(clkdiv_dmc1[index][1] << EXYNOS4_CLKDIV_DMC1_C2C_SHIFT) |
+		(clkdiv_dmc1[index][2] << EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT));
+
+	__raw_writel(tmp, EXYNOS4_CLKDIV_DMC1);
+
+	do {
+		tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC1);
+	} while (tmp & 0x1011);
+
+	/* Change Divider - TOP */
+	tmp = __raw_readl(EXYNOS4_CLKDIV_TOP);
+
+	tmp &= ~(EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK |
+		EXYNOS4_CLKDIV_TOP_ACLK100_MASK |
+		EXYNOS4_CLKDIV_TOP_ACLK160_MASK |
+		EXYNOS4_CLKDIV_TOP_ACLK133_MASK |
+		EXYNOS4_CLKDIV_TOP_ONENAND_MASK);
+
+	tmp |= ((clkdiv_top[index][0] << EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT) |
+		(clkdiv_top[index][1] << EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT) |
+		(clkdiv_top[index][2] << EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT) |
+		(clkdiv_top[index][3] << EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT) |
+		(clkdiv_top[index][4] << EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT));
+
+	__raw_writel(tmp, EXYNOS4_CLKDIV_TOP);
+
+	do {
+		tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_TOP);
+	} while (tmp & 0x11111);
+
+	/* Change Divider - LEFTBUS */
+	tmp = __raw_readl(EXYNOS4_CLKDIV_LEFTBUS);
+
+	tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK);
+
+	tmp |= ((clkdiv_l_bus[index][0] << EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) |
+		(clkdiv_l_bus[index][1] << EXYNOS4_CLKDIV_BUS_GPLR_SHIFT));
+
+	__raw_writel(tmp, EXYNOS4_CLKDIV_LEFTBUS);
+
+	do {
+		tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_LEFTBUS);
+	} while (tmp & 0x11);
+
+	/* Change Divider - RIGHTBUS */
+	tmp = __raw_readl(EXYNOS4_CLKDIV_RIGHTBUS);
+
+	tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK);
+
+	tmp |= ((clkdiv_r_bus[index][0] << EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) |
+		(clkdiv_r_bus[index][1] << EXYNOS4_CLKDIV_BUS_GPLR_SHIFT));
+
+	__raw_writel(tmp, EXYNOS4_CLKDIV_RIGHTBUS);
+
+	do {
+		tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_RIGHTBUS);
+	} while (tmp & 0x11);
+
+	/* Change Divider - MFC */
+	tmp = __raw_readl(EXYNOS4_CLKDIV_MFC);
+
+	tmp &= ~(EXYNOS4_CLKDIV_MFC_MASK);
+
+	tmp |= ((clkdiv_sclkip[index][0] << EXYNOS4_CLKDIV_MFC_SHIFT));
+
+	__raw_writel(tmp, EXYNOS4_CLKDIV_MFC);
+
+	do {
+		tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_MFC);
+	} while (tmp & 0x1);
+
+	/* Change Divider - JPEG */
+	tmp = __raw_readl(EXYNOS4_CLKDIV_CAM1);
+
+	tmp &= ~(EXYNOS4_CLKDIV_CAM1_JPEG_MASK);
+
+	tmp |= ((clkdiv_sclkip[index][1] << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT));
+
+	__raw_writel(tmp, EXYNOS4_CLKDIV_CAM1);
+
+	do {
+		tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_CAM1);
+	} while (tmp & 0x1);
+
+	/* Change Divider - FIMC0~3 */
+	tmp = __raw_readl(EXYNOS4_CLKDIV_CAM);
+
+	tmp &= ~(EXYNOS4_CLKDIV_CAM_FIMC0_MASK | EXYNOS4_CLKDIV_CAM_FIMC1_MASK |
+		EXYNOS4_CLKDIV_CAM_FIMC2_MASK | EXYNOS4_CLKDIV_CAM_FIMC3_MASK);
+
+	tmp |= ((clkdiv_sclkip[index][2] << EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT) |
+		(clkdiv_sclkip[index][2] << EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT) |
+		(clkdiv_sclkip[index][2] << EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT) |
+		(clkdiv_sclkip[index][2] << EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT));
+
+	__raw_writel(tmp, EXYNOS4_CLKDIV_CAM);
+
+	do {
+		tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_CAM1);
+	} while (tmp & 0x1111);
+
+	if (soc_is_exynos4412() && (exynos_result_of_asv > 3)) {
+		if (index == LV_6) { /* MIF:100 / INT:100 */
+			exynos4x12_set_abb_member(ABB_INT, ABB_MODE_100V);
+			exynos4x12_set_abb_member(ABB_MIF, ABB_MODE_100V);
+		} else {
+			exynos4x12_set_abb_member(ABB_INT, ABB_MODE_130V);
+			exynos4x12_set_abb_member(ABB_MIF, ABB_MODE_130V);
+		}
+	}
+}
+
+unsigned int exynos4x12_get_table_index(struct opp *opp)
+{
+	unsigned int index;
+
+	for (index = LV_0; index < LV_END; index++)
+		if (opp_get_freq(opp) == exynos4_busfreq_table[index].mem_clk)
+			break;
+
+	return index;
+}
+
+void exynos4x12_prepare(unsigned int index)
+{
+	unsigned int timing0 = 0;
+
+#ifdef CONFIG_ARM_TRUSTZONE
+	exynos_smc_readsfr(EXYNOS4_PA_DMC0_4212 + TIMINGROW_OFFSET, &timing0);
+	timing0 |= exynos4x12_timingrow[index];
+	exynos_smc(SMC_CMD_REG, SMC_REG_ID_SFR_W(EXYNOS4_PA_DMC0_4212 + TIMINGROW_OFFSET),
+			timing0, 0);
+	exynos_smc(SMC_CMD_REG, SMC_REG_ID_SFR_W(EXYNOS4_PA_DMC0_4212 + TIMINGROW_OFFSET),
+			exynos4x12_timingrow[index], 0);
+	exynos_smc(SMC_CMD_REG, SMC_REG_ID_SFR_W(EXYNOS4_PA_DMC1_4212 + TIMINGROW_OFFSET),
+			timing0, 0);
+	exynos_smc(SMC_CMD_REG, SMC_REG_ID_SFR_W(EXYNOS4_PA_DMC1_4212 + TIMINGROW_OFFSET),
+			exynos4x12_timingrow[index], 0);
+#else
+	timing0 = __raw_readl(S5P_VA_DMC0 + TIMINGROW_OFFSET);
+	timing0 |= exynos4x12_timingrow[index];
+	__raw_writel(timing0, S5P_VA_DMC0 + TIMINGROW_OFFSET);
+	__raw_writel(exynos4x12_timingrow[index], S5P_VA_DMC0 + TIMINGROW_OFFSET);
+	__raw_writel(timing0, S5P_VA_DMC1 + TIMINGROW_OFFSET);
+	__raw_writel(exynos4x12_timingrow[index], S5P_VA_DMC1 + TIMINGROW_OFFSET);
+#endif
+}
+
+void exynos4x12_post(unsigned int index)
+{
+	unsigned int timing0 = 0;
+
+#ifdef CONFIG_ARM_TRUSTZONE
+	exynos_smc_readsfr(EXYNOS4_PA_DMC0_4212 + TIMINGROW_OFFSET, &timing0);
+	timing0 |= exynos4x12_timingrow[index];
+	exynos_smc(SMC_CMD_REG, SMC_REG_ID_SFR_W(EXYNOS4_PA_DMC0_4212 + TIMINGROW_OFFSET),
+			timing0, 0);
+	exynos_smc(SMC_CMD_REG, SMC_REG_ID_SFR_W(EXYNOS4_PA_DMC0_4212 + TIMINGROW_OFFSET),
+			exynos4x12_timingrow[index], 0);
+	exynos_smc(SMC_CMD_REG, SMC_REG_ID_SFR_W(EXYNOS4_PA_DMC1_4212 + TIMINGROW_OFFSET),
+			timing0, 0);
+	exynos_smc(SMC_CMD_REG, SMC_REG_ID_SFR_W(EXYNOS4_PA_DMC1_4212 + TIMINGROW_OFFSET),
+			exynos4x12_timingrow[index], 0);
+#else
+	timing0 = __raw_readl(S5P_VA_DMC0 + TIMINGROW_OFFSET);
+	timing0 |= exynos4x12_timingrow[index];
+	__raw_writel(timing0, S5P_VA_DMC0 + TIMINGROW_OFFSET);
+	__raw_writel(exynos4x12_timingrow[index], S5P_VA_DMC0 + TIMINGROW_OFFSET);
+	__raw_writel(timing0, S5P_VA_DMC1 + TIMINGROW_OFFSET);
+	__raw_writel(exynos4x12_timingrow[index], S5P_VA_DMC1 + TIMINGROW_OFFSET);
+#endif
+}
+
+void exynos4x12_set_qos(unsigned int index)
+{
+	__raw_writel(exynos4_qos_value[busfreq_qos][index][0], S5P_VA_GDL + 0x400);
+	__raw_writel(exynos4_qos_value[busfreq_qos][index][1], S5P_VA_GDL + 0x404);
+	__raw_writel(exynos4_qos_value[busfreq_qos][index][2], S5P_VA_GDR + 0x400);
+	__raw_writel(exynos4_qos_value[busfreq_qos][index][3], S5P_VA_GDR + 0x404);
+}
+
+void exynos4x12_suspend(void)
+{
+	/* Nothing to do */
+}
+
+void exynos4x12_resume(void)
+{
+	__raw_writel(dmc_pause_ctrl, EXYNOS4_DMC_PAUSE_CTRL);
+}
+
+/**
+ * exynos4x12_find_busfreq_by_volt - find busfreq by requested
+ * voltage.
+ *
+ * This function finds the busfreq to set for voltage above req_volt
+ * and return its value.
+ */
+int exynos4x12_find_busfreq_by_volt(unsigned int req_volt, unsigned int *freq)
+{
+	unsigned int volt_cmp;
+	int i;
+
+	/* check if req_volt has value or not */
+	if (!req_volt) {
+		pr_err("%s: req_volt has no value.\n", __func__);
+		return -EINVAL;
+	}
+
+	/* find busfreq level in busfreq_table */
+	for (i = LV_END - 1; i >= 0; i--) {
+		volt_cmp = min(exynos4_int_volt[asv_group_index][i],
+				exynos4_mif_volt[asv_group_index][i]);
+
+		if (volt_cmp >= req_volt) {
+			*freq = exynos4_busfreq_table[i].mem_clk;
+			return 0;
+		}
+	}
+	pr_err("%s: %u volt can't support\n", __func__, req_volt);
+
+	return -EINVAL;
+}
+EXPORT_SYMBOL_GPL(exynos4x12_find_busfreq_by_volt);
+
+unsigned int exynos4x12_get_int_volt(unsigned long index)
+{
+	return exynos4_int_volt[asv_group_index][index];
+}
+
+struct opp *exynos4x12_monitor(struct busfreq_data *data)
+{
+	struct opp *opp = data->curr_opp;
+	int i;
+	unsigned int cpu_load_average = 0;
+	unsigned int dmc0_load_average = 0;
+	unsigned int dmc1_load_average = 0;
+	unsigned int dmc_load_average;
+	unsigned long cpufreq = 0;
+	unsigned long lockfreq;
+	unsigned long dmcfreq;
+	unsigned long newfreq;
+	unsigned long currfreq = opp_get_freq(data->curr_opp) / 1000;
+	unsigned long maxfreq = opp_get_freq(data->max_opp) / 1000;
+	unsigned long cpu_load;
+	unsigned long dmc0_load;
+	unsigned long dmc1_load;
+	unsigned long dmc_load;
+	int cpu_load_slope;
+
+	ppmu_update(data->dev, 3);
+
+	/* Convert from base xxx to base maxfreq */
+	cpu_load = ppmu_load[PPMU_CPU];
+	dmc0_load = div64_u64(ppmu_load[PPMU_DMC0] * currfreq, maxfreq);
+	dmc1_load = div64_u64(ppmu_load[PPMU_DMC1] * currfreq, maxfreq);
+
+	cpu_load_slope = cpu_load -
+		data->load_history[PPMU_CPU]
+		[data->index ? data->index - 1 : load_history_size - 1];
+
+	data->load_history[PPMU_CPU][data->index] = cpu_load;
+	data->load_history[PPMU_DMC0][data->index] = dmc0_load;
+	data->load_history[PPMU_DMC1][data->index++] = dmc1_load;
+
+	if (data->index >= load_history_size)
+		data->index = 0;
+
+	for (i = 0; i < load_history_size; i++) {
+		cpu_load_average += data->load_history[PPMU_CPU][i];
+		dmc0_load_average += data->load_history[PPMU_DMC0][i];
+		dmc1_load_average += data->load_history[PPMU_DMC1][i];
+	}
+
+	/* Calculate average Load */
+	cpu_load_average /= load_history_size;
+	dmc0_load_average /= load_history_size;
+	dmc1_load_average /= load_history_size;
+
+	if (dmc0_load >= dmc1_load) {
+		dmc_load = dmc0_load;
+		dmc_load_average = dmc0_load_average;
+	} else {
+		dmc_load = dmc1_load;
+		dmc_load_average = dmc1_load_average;
+	}
+
+	if (cpu_load >= up_cpu_threshold) {
+		cpufreq = opp_get_freq(data->max_opp);
+		if (cpu_load < max_cpu_threshold) {
+			opp = data->curr_opp;
+			if (cpu_load_slope > cpu_slope_size) {
+				cpufreq--;
+				opp = opp_find_freq_floor(data->dev, &cpufreq);
+			}
+			cpufreq = opp_get_freq(opp);
+		}
+	}
+
+	if (dmc_load >= dmc_max_threshold) {
+		dmcfreq = opp_get_freq(data->max_opp);
+	} else if (dmc_load < idle_threshold) {
+		if (dmc_load_average < idle_threshold)
+			opp = step_down(data, 1);
+		else
+			opp = data->curr_opp;
+		dmcfreq = opp_get_freq(opp);
+	} else {
+		if (dmc_load < dmc_load_average) {
+			dmc_load = dmc_load_average;
+			if (dmc_load >= dmc_max_threshold)
+				dmc_load = dmc_max_threshold;
+		}
+		dmcfreq = div64_u64(maxfreq * dmc_load * 1000, dmc_max_threshold);
+	}
+
+	lockfreq = dev_max_freq(data->dev);
+
+	newfreq = max3(lockfreq, dmcfreq, cpufreq);
+
+	if (samsung_rev() < EXYNOS4412_REV_1_0)
+		newfreq = opp_get_freq(data->max_opp);
+
+	pr_debug("curfreq %ld, newfreq %ld, dmc0_load %ld, dmc1_load %ld, cpu_load %ld\n",
+		currfreq, newfreq, dmc0_load, dmc1_load, cpu_load);
+
+	opp = opp_find_freq_ceil(data->dev, &newfreq);
+	if (IS_ERR(opp))
+		opp = data->max_opp;
+
+	return opp;
+}
+
+static int exynos4x12_bus_qos_notifiy(struct notifier_block *nb,
+		unsigned long l, void *v)
+{
+	struct busfreq_data *bus_data = container_of(nb, struct busfreq_data,
+			exynos_busqos_notifier);
+
+	busfreq_qos = (int)l;
+	exynos4x12_set_qos(bus_data->get_table_index(bus_data->curr_opp));
+
+	return NOTIFY_OK;
+}
+
+static inline void exynos4x12_bus_qos_notifier_init(struct notifier_block *n)
+{
+	pm_qos_add_notifier(PM_QOS_BUS_QOS, n);
+}
+
+#define ARM_INT_CORRECTION 160160
+
+static int exynos4x12_busfreq_cpufreq_transition(struct notifier_block *nb,
+					    unsigned long val, void *data)
+{
+	struct cpufreq_freqs *freqs = (struct cpufreq_freqs *)data;
+	struct busfreq_data *bus_data = container_of(nb, struct busfreq_data,
+			exynos_cpufreq_notifier);
+
+	switch (val) {
+	case CPUFREQ_PRECHANGE:
+		if (freqs->new > 900000 && freqs->old < 1000000)
+			dev_lock(bus_data->dev, bus_data->dev, ARM_INT_CORRECTION);
+		break;
+	case CPUFREQ_POSTCHANGE:
+		if (freqs->old > 900000 && freqs->new < 1000000)
+			dev_unlock(bus_data->dev, bus_data->dev);
+		break;
+	}
+	return NOTIFY_DONE;
+}
+
+int exynos4x12_init(struct device *dev, struct busfreq_data *data)
+{
+	unsigned int i;
+	unsigned int tmp;
+	unsigned long maxfreq = 400200;
+	unsigned long minfreq = 0;
+	unsigned long freq;
+	struct clk *sclk_dmc;
+	int ret;
+
+	if (soc_is_exynos4212()) {
+		exynos4_mif_volt = exynos4212_mif_volt;
+		exynos4_int_volt = exynos4212_int_volt;
+		dmc_max_threshold = EXYNOS4212_DMC_MAX_THRESHOLD;
+	} else if (soc_is_exynos4412()) {
+		exynos4_mif_volt = exynos4412_mif_volt;
+		exynos4_int_volt = exynos4412_int_volt;
+		dmc_max_threshold = EXYNOS4412_DMC_MAX_THRESHOLD;
+	} else {
+		pr_err("Unsupported model.\n");
+		return -EINVAL;
+	}
+
+	/* Enable pause function for DREX2 DVFS */
+	dmc_pause_ctrl = __raw_readl(EXYNOS4_DMC_PAUSE_CTRL);
+	dmc_pause_ctrl |= DMC_PAUSE_ENABLE;
+	__raw_writel(dmc_pause_ctrl, EXYNOS4_DMC_PAUSE_CTRL);
+
+	tmp = __raw_readl(EXYNOS4_CLKDIV_DMC0);
+
+	for (i = 0; i <  LV_END; i++) {
+		tmp &= ~(EXYNOS4_CLKDIV_DMC0_ACP_MASK |
+			EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK |
+			EXYNOS4_CLKDIV_DMC0_DPHY_MASK |
+			EXYNOS4_CLKDIV_DMC0_DMC_MASK |
+			EXYNOS4_CLKDIV_DMC0_DMCD_MASK |
+			EXYNOS4_CLKDIV_DMC0_DMCP_MASK);
+
+		tmp |= ((clkdiv_dmc0[i][0] << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT) |
+			(clkdiv_dmc0[i][1] << EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT) |
+			(clkdiv_dmc0[i][2] << EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT) |
+			(clkdiv_dmc0[i][3] << EXYNOS4_CLKDIV_DMC0_DMC_SHIFT) |
+			(clkdiv_dmc0[i][4] << EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT) |
+			(clkdiv_dmc0[i][5] << EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT));
+
+		exynos4_busfreq_table[i].clk_dmc0div = tmp;
+	}
+
+	exynos4x12_set_bus_volt();
+
+	for (i = 0; i < LV_END; i++) {
+		ret = opp_add(dev, exynos4_busfreq_table[i].mem_clk,
+				exynos4_busfreq_table[i].volt);
+		if (ret) {
+			dev_err(dev, "Fail to add opp entries.\n");
+			return ret;
+		}
+	}
+
+	/* Disable MIF 267 INT 200 Level */
+	/* opp_disable(dev, 267200); */
+
+	data->table = exynos4_busfreq_table;
+	data->table_size = LV_END;
+
+	/* Find max frequency */
+	data->max_opp = opp_find_freq_floor(dev, &maxfreq);
+	data->min_opp = opp_find_freq_ceil(dev, &minfreq);
+
+	sclk_dmc = clk_get(NULL, "sclk_dmc");
+
+	if (IS_ERR(sclk_dmc)) {
+		pr_err("Failed to get sclk_dmc.!\n");
+		data->curr_opp = data->max_opp;
+	} else {
+		freq = clk_get_rate(sclk_dmc) / 1000;
+		clk_put(sclk_dmc);
+		data->curr_opp = opp_find_freq_ceil(dev, &freq);
+	}
+
+	data->vdd_int = regulator_get(NULL, "vdd_int");
+	if (IS_ERR(data->vdd_int)) {
+		pr_err("failed to get resource %s\n", "vdd_int");
+		return -ENODEV;
+	}
+
+	data->vdd_mif = regulator_get(NULL, "vdd_mif");
+	if (IS_ERR(data->vdd_mif)) {
+		pr_err("failed to get resource %s\n", "vdd_mif");
+		regulator_put(data->vdd_int);
+		return -ENODEV;
+	}
+
+	data->exynos_cpufreq_notifier.notifier_call =
+				exynos4x12_busfreq_cpufreq_transition;
+
+	if (cpufreq_register_notifier(&data->exynos_cpufreq_notifier,
+	   CPUFREQ_TRANSITION_NOTIFIER))
+		pr_err("Falied to register cpufreq notifier\n");
+
+	data->exynos_busqos_notifier.notifier_call = exynos4x12_bus_qos_notifiy;
+	exynos4x12_bus_qos_notifier_init(&data->exynos_busqos_notifier);
+
+	return 0;
+}
diff --git a/arch/arm/mach-exynos/busfreq_opp_5250.c b/arch/arm/mach-exynos/busfreq_opp_5250.c
new file mode 100644
index 0000000..bcedb46
--- /dev/null
+++ b/arch/arm/mach-exynos/busfreq_opp_5250.c
@@ -0,0 +1,892 @@
+/* linux/arch/arm/mach-exynos/busfreq_opp_5250.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * EXYNOS5 - BUS clock frequency scaling support with OPP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/types.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/regulator/consumer.h>
+#include <linux/sysfs.h>
+#include <linux/platform_device.h>
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/cpu.h>
+#include <linux/ktime.h>
+#include <linux/tick.h>
+#include <linux/kernel_stat.h>
+#include <linux/reboot.h>
+#include <linux/slab.h>
+#include <linux/opp.h>
+#include <linux/clk.h>
+#include <mach/busfreq_exynos5.h>
+
+#include <asm/mach-types.h>
+
+#include <mach/ppmu.h>
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/gpio.h>
+#include <mach/regs-mem.h>
+#include <mach/dev.h>
+#include <mach/asv.h>
+#include <mach/regs-pmu-5250.h>
+
+#include <plat/map-s5p.h>
+#include <plat/gpio-cfg.h>
+#include <plat/cpu.h>
+#include <plat/clock.h>
+
+#undef BUSFREQ_PROFILE_DEBUG
+
+#define IDLE_THRESHOLD		4
+#define MIF_R1_THRESHOLD	20
+#define MIF_MAX_THRESHOLD	20
+#define INT_MAX_THRESHOLD	20
+#define INT_RIGHT0_THRESHOLD	25
+#define INT_VIDEOPLAY_LIMIT_FREQ 200000UL
+#define INT_RBB		6	/* +300mV */
+
+static struct device busfreq_for_int;
+
+/* To save/restore DREX2_PAUSE_CTRL register */
+static unsigned int drex2_pause_ctrl;
+
+static struct busfreq_table exynos5_busfreq_table_for800[] = {
+	{LV_0, 800000, 1000000, 0, 0, 0},
+	{LV_1, 400000, 1000000, 0, 0, 0},
+	{LV_2, 160000, 1000000, 0, 0, 0},
+};
+
+static struct busfreq_table exynos5_busfreq_table_for667[] = {
+	{LV_0, 667000, 1000000, 0, 0, 0},
+	{LV_1, 334000, 1000000, 0, 0, 0},
+	{LV_2, 111000, 1000000, 0, 0, 0},
+};
+
+static struct busfreq_table exynos5_busfreq_table_for533[] = {
+	{LV_0, 533000, 1000000, 0, 0, 0},
+	{LV_1, 267000, 1000000, 0, 0, 0},
+	{LV_2, 107000, 1000000, 0, 0, 0},
+};
+
+static struct busfreq_table exynos5_busfreq_table_for400[] = {
+	{LV_0, 400000, 1000000, 0, 0, 0},
+	{LV_1, 267000, 1000000, 0, 0, 0},
+	{LV_2, 100000, 1000000, 0, 0, 0},
+};
+#define ASV_GROUP	10
+static unsigned int asv_group_index;
+
+static unsigned int exynos5_mif_volt_for800[ASV_GROUP+1][LV_MIF_END] = {
+	/* L0        L1      L2 */
+	{      0,       0,      0}, /* ASV0 */
+	{1200000, 1000000, 950000}, /* ASV1 */
+	{1200000, 1000000, 900000}, /* ASV2 */
+	{1200000, 1050000, 950000}, /* ASV3 */
+	{1150000, 1000000, 900000}, /* ASV4 */
+	{1150000, 1050000, 950000}, /* ASV5 */
+	{1150000, 1050000, 950000}, /* ASV6 */
+	{1100000, 1000000, 900000}, /* ASV7 */
+	{1100000, 1000000, 900000}, /* ASV8 */
+	{1100000, 1000000, 900000}, /* ASV9 */
+	{1100000, 1000000, 900000}, /* ASV10 */
+};
+
+static unsigned int exynos5_mif_volt_for667[ASV_GROUP+1][LV_MIF_END] = {
+	/* L0        L1      L2 */
+	{      0,       0,       0}, /* ASV0 */
+	{1100000, 1000000,  950000}, /* ASV1 */
+	{1050000, 1000000,  950000}, /* ASV2 */
+	{1050000, 1050000,  950000}, /* ASV3 */
+	{1050000, 1000000,  950000}, /* ASV4 */
+	{1050000, 1050000, 1000000}, /* ASV5 */
+	{1050000, 1050000,  950000}, /* ASV6 */
+	{1050000, 1000000,  900000}, /* ASV7 */
+	{1050000, 1000000,  900000}, /* ASV8 */
+	{1050000, 1000000,  900000}, /* ASV9 */
+	{1050000, 1000000,  900000}, /* ASV10 */
+};
+
+static unsigned int exynos5_mif_volt_for533[ASV_GROUP+1][LV_MIF_END] = {
+	/* L0        L1      L2 */
+	{      0,       0,       0}, /* ASV0 */
+	{1050000, 1000000,  950000}, /* ASV1 */
+	{1000000,  950000,  950000}, /* ASV2 */
+	{1050000, 1000000,  950000}, /* ASV3 */
+	{1000000,  950000,  950000}, /* ASV4 */
+	{1050000, 1000000, 1000000}, /* ASV5 */
+	{1050000,  950000,  950000}, /* ASV6 */
+	{1000000,  950000,  900000}, /* ASV7 */
+	{1000000,  950000,  900000}, /* ASV8 */
+	{1000000,  950000,  900000}, /* ASV9 */
+	{1000000,  950000,  900000}, /* ASV10 */
+};
+
+static unsigned int exynos5_mif_volt_for400[ASV_GROUP+1][LV_MIF_END] = {
+	/* L0        L1      L2 */
+	{      0,       0,      0}, /* ASV0 */
+	{1000000, 1000000, 950000}, /* ASV1 */
+	{1000000,  950000, 900000}, /* ASV2 */
+	{1050000, 1000000, 950000}, /* ASV3 */
+	{1000000,  950000, 900000}, /* ASV4 */
+	{1050000, 1000000, 950000}, /* ASV5 */
+	{1050000,  950000, 950000}, /* ASV6 */
+	{1000000,  950000, 900000}, /* ASV7 */
+	{1000000,  950000, 900000}, /* ASV8 */
+	{1000000,  950000, 900000}, /* ASV9 */
+	{1000000,  950000, 900000}, /* ASV10 */
+};
+
+static struct busfreq_table *exynos5_busfreq_table_mif;
+
+static unsigned int (*exynos5_mif_volt)[LV_MIF_END];
+
+static struct busfreq_table exynos5_busfreq_table_int[] = {
+	{LV_0, 267000, 1000000, 0, 0, 0},
+	{LV_1, 200000, 1000000, 0, 0, 0},
+	{LV_2, 160000, 1000000, 0, 0, 0},
+	{LV_3, 133000, 1000000, 0, 0, 0},
+};
+
+static unsigned int exynos5_int_volt[ASV_GROUP+1][LV_INT_END] = {
+	/* L0        L1       L2       L3 */
+	{      0,      0,      0,      0}, /* ASV0 */
+	{1025000, 987500, 975000, 950000}, /* ASV1 */
+	{1012500, 975000, 962500, 937500}, /* ASV2 */
+	{1012500, 987500, 975000, 950000}, /* ASV3 */
+	{1000000, 975000, 962500, 937500}, /* ASV4 */
+	{1012500, 987500, 975000, 950000}, /* ASV5 */
+	{1000000, 975000, 962500, 937500}, /* ASV6 */
+	{ 987500, 962500, 950000, 925000}, /* ASV7 */
+	{ 975000, 950000, 937500, 912500}, /* ASV8 */
+	{ 962500, 937500, 925000, 900000}, /* ASV9 */
+	{ 962500, 937500, 925000, 900000}, /* ASV10 */
+};
+
+
+/* For CMU_LEX */
+static unsigned int clkdiv_lex[LV_INT_END][2] = {
+	/*
+	 * Clock divider value for following
+	 * { DIVATCLK_LEX, DIVPCLK_LEX }
+	 */
+
+	/* ATCLK_LEX L0 : 200MHz */
+	{0, 1},
+
+	/* ATCLK_LEX L1 : 166MHz */
+	{0, 1},
+
+	/* ATCLK_LEX L2 : 133MHz */
+	{0, 1},
+
+	/* ATCLK_LEX L3 : 114MHz */
+	{0, 1},
+};
+
+/* For CMU_R0X */
+static unsigned int clkdiv_r0x[LV_INT_END][1] = {
+	/*
+	 * Clock divider value for following
+	 * { DIVPCLK_R0X }
+	 */
+
+	/* ACLK_PR0X L0 : 133MHz */
+	{1},
+
+	/* ACLK_DR0X L1 : 100MHz */
+	{1},
+
+	/* ACLK_PR0X L2 : 80MHz */
+	{1},
+
+	/* ACLK_PR0X L3 : 67MHz */
+	{1},
+};
+
+/* For CMU_R1X */
+static unsigned int clkdiv_r1x[LV_INT_END][1] = {
+	/*
+	 * Clock divider value for following
+	 * { DIVPCLK_R1X }
+	 */
+
+	/* ACLK_PR1X L0 : 133MHz */
+	{1},
+
+	/* ACLK_DR1X L1 : 100MHz */
+	{1},
+
+	/* ACLK_PR1X L2 : 80MHz */
+	{1},
+
+	/* ACLK_PR1X L3 : 67MHz */
+	{1},
+};
+
+/* For CMU_TOP */
+static unsigned int clkdiv_top[LV_INT_END][10] = {
+	/*
+	 * Clock divider value for following
+	 * { DIVACLK400_ISP, DIVACLK400_IOP, DIVACLK266, DIVACLK_200, DIVACLK_66_PRE,
+	 DIVACLK_66, DIVACLK_333, DIVACLK_166, DIVACLK_300_DISP1, DIVACLK300_GSCL }
+	 */
+
+	/* ACLK_400_ISP L0 : 400MHz */
+	{1, 1, 2, 3, 1, 5, 0, 1, 2, 2},
+
+	/* ACLK_400_ISP L1 : 267MHz */
+	{2, 3, 3, 4, 1, 5, 1, 2, 2, 2},
+
+	/* ACLK_400_ISP L2 : 200MHz */
+	{3, 3, 4, 4, 1, 5, 2, 3, 2, 2},
+
+	/* ACLK_400_ISP L3 : 160MHz */
+	{4, 4, 5, 5, 1, 5, 2, 3, 5, 5},
+};
+
+/* For CMU_CDREX */
+static unsigned int clkdiv_cdrex_for800[LV_MIF_END][9] = {
+	/*
+	 * Clock divider value for following
+	 * { DIVMCLK_DPHY, DIVMCLK_CDREX2, DIVACLK_CDREX, DIVMCLK_CDREX,
+		DIVPCLK_CDREX, DIVC2C, DIVC2C_ACLK, DIVMCLK_EFPHY, DIVACLK_EFCON }
+	 */
+
+	/* MCLK_CDREX L0: 800MHz */
+	{0, 0, 1, 0, 5, 1, 1, 4, 1},
+
+	/* MCLK_CDREX L1: 400MHz */
+	{0, 1, 1, 1, 3, 2, 1, 5, 1},
+
+	/* MCLK_CDREX L2: 100MHz */
+	{0, 4, 1, 1, 7, 7, 1, 15, 1},
+};
+
+static unsigned int clkdiv_cdrex_for667[LV_MIF_END][9] = {
+	/*
+	 * Clock divider value for following
+	 * { DIVMCLK_DPHY, DIVMCLK_CDREX2, DIVACLK_CDREX, DIVMCLK_CDREX,
+		DIVPCLK_CDREX, DIVC2C, DIVC2C_ACLK, DIVMCLK_EFPHY, DIVACLK_EFCON }
+	 */
+
+	/* MCLK_CDREX L0: 667MHz */
+	{0, 0, 1, 0, 4, 1, 1, 4, 1},
+
+	/* MCLK_CDREX L1: 334MHz */
+	{0, 1, 1, 1, 4, 2, 1, 5, 1},
+
+	/* MCLK_CDREX L2: 111MHz */
+	{0, 5, 1, 4, 4, 5, 1, 8, 1},
+};
+
+static unsigned int clkdiv_cdrex_for533[LV_MIF_END][9] = {
+	/*
+	 * Clock divider value for following
+	 * { DIVMCLK_DPHY, DIVMCLK_CDREX2, DIVACLK_CDREX, DIVMCLK_CDREX,
+		DIVPCLK_CDREX, DIVC2C, DIVC2C_ACLK, DIVMCLK_EFPHY, DIVACLK_EFCON }
+	 */
+
+	/* MCLK_CDREX L0: 533MHz */
+	{0, 0, 1, 0, 3, 1, 1, 4, 1},
+
+	/* MCLK_CDREX L1: 267MHz */
+	{0, 1, 1, 1, 3, 2, 1, 5, 1},
+
+	/* MCLK_CDREX L2: 107MHz */
+	{0, 4, 1, 4, 3, 5, 1, 8, 1},
+};
+
+static unsigned int __maybe_unused clkdiv_cdrex_for400[LV_MIF_END][9] = {
+	/*
+	 * Clock divider value for following
+	 * { DIVMCLK_DPHY, DIVMCLK_CDREX2, DIVACLK_CDREX, DIVMCLK_CDREX,
+		DIVPCLK_CDREX, DIVC2C, DIVC2C_ACLK, DIVMCLK_EFPHY, DIVACLK_EFCON }
+	 */
+
+	/* MCLK_CDREX L0: 400MHz */
+	{1, 1, 1, 0, 5, 1, 1, 4, 1},
+
+	/* MCLK_CDREX L1: 267MHz */
+	{1, 2, 1, 2, 2, 2, 1, 5, 1},
+
+	/* MCLK_CDREX L2: 100MHz */
+	{1, 7, 1, 2, 7, 7, 1, 15, 1},
+};
+
+static unsigned int (*clkdiv_cdrex)[9];
+
+static void exynos5250_set_bus_volt(void)
+{
+	unsigned int i;
+
+	if (soc_is_exynos5250() && samsung_rev() < EXYNOS5250_REV_1_0)
+		asv_group_index = 0;
+	else
+		asv_group_index = exynos_result_of_asv;
+
+	if (asv_group_index == 0xff)
+		asv_group_index = 0;
+
+	printk(KERN_INFO "DVFS : VDD_INT Voltage table set with %d Group\n", asv_group_index);
+	printk(KERN_INFO "DVFS : VDD_INT Voltage of L0 level is %d \n", exynos5_mif_volt[asv_group_index][0]);
+
+	for (i = LV_0; i < LV_MIF_END; i++)
+		exynos5_busfreq_table_mif[i].volt =
+			exynos5_mif_volt[asv_group_index][i];
+
+	for (i = LV_0; i < LV_INT_END; i++)
+		exynos5_busfreq_table_int[i].volt =
+			exynos5_int_volt[asv_group_index][i];
+	return;
+}
+
+static void exynos5250_target_for_mif(struct busfreq_data *data, int div_index)
+{
+	unsigned int tmp;
+
+	/* Change Divider - CDREX */
+	tmp = data->cdrex_divtable[div_index];
+
+	__raw_writel(tmp, EXYNOS5_CLKDIV_CDREX);
+
+	if (samsung_rev() < EXYNOS5250_REV_1_0) {
+		do {
+			tmp = __raw_readl(EXYNOS5_CLKDIV_STAT_CDREX);
+		} while (tmp & 0x11111111);
+	} else {
+		do {
+			tmp = __raw_readl(EXYNOS5_CLKDIV_STAT_CDREX);
+		} while (tmp & 0x11110011);		\
+	}
+
+	if (samsung_rev() < EXYNOS5250_REV_1_0) {
+		tmp = data->cdrex2_divtable[div_index];
+
+		__raw_writel(tmp, EXYNOS5_CLKDIV_CDREX2);
+
+		do {
+			tmp = __raw_readl(EXYNOS5_CLKDIV_STAT_CDREX2);
+		} while (tmp & 0x1);
+	}
+}
+
+static void exynos5250_target_for_int(struct busfreq_data *data, int div_index)
+{
+	unsigned int tmp;
+	unsigned int tmp2;
+
+	/* Change Divider - TOP */
+	tmp = __raw_readl(EXYNOS5_CLKDIV_TOP0);
+
+	tmp &= ~(EXYNOS5_CLKDIV_TOP0_ACLK266_MASK |
+		EXYNOS5_CLKDIV_TOP0_ACLK200_MASK |
+		EXYNOS5_CLKDIV_TOP0_ACLK66_MASK |
+		EXYNOS5_CLKDIV_TOP0_ACLK333_MASK |
+		EXYNOS5_CLKDIV_TOP0_ACLK166_MASK |
+		EXYNOS5_CLKDIV_TOP0_ACLK300_DISP1_MASK);
+
+	tmp |= ((clkdiv_top[div_index][2] << EXYNOS5_CLKDIV_TOP0_ACLK266_SHIFT) |
+		(clkdiv_top[div_index][3] << EXYNOS5_CLKDIV_TOP0_ACLK200_SHIFT) |
+		(clkdiv_top[div_index][5] << EXYNOS5_CLKDIV_TOP0_ACLK66_SHIFT) |
+		(clkdiv_top[div_index][6] << EXYNOS5_CLKDIV_TOP0_ACLK333_SHIFT) |
+		(clkdiv_top[div_index][7] << EXYNOS5_CLKDIV_TOP0_ACLK166_SHIFT) |
+		(clkdiv_top[div_index][8] << EXYNOS5_CLKDIV_TOP0_ACLK300_DISP1_SHIFT));
+
+	__raw_writel(tmp, EXYNOS5_CLKDIV_TOP0);
+
+	do {
+		tmp = __raw_readl(EXYNOS5_CLKDIV_STAT_TOP0);
+	} while (tmp & 0x151101);
+
+	tmp = __raw_readl(EXYNOS5_CLKDIV_TOP1);
+
+	tmp &= ~(EXYNOS5_CLKDIV_TOP1_ACLK400_ISP_MASK |
+		EXYNOS5_CLKDIV_TOP1_ACLK400_IOP_MASK |
+		EXYNOS5_CLKDIV_TOP1_ACLK66_PRE_MASK |
+		EXYNOS5_CLKDIV_TOP1_ACLK300_GSCL_MASK);
+
+	tmp |= ((clkdiv_top[div_index][0] << EXYNOS5_CLKDIV_TOP1_ACLK400_ISP_SHIFT) |
+		(clkdiv_top[div_index][1] << EXYNOS5_CLKDIV_TOP1_ACLK400_IOP_SHIFT) |
+		(clkdiv_top[div_index][4] << EXYNOS5_CLKDIV_TOP1_ACLK66_PRE_SHIFT) |
+		(clkdiv_top[div_index][9] << EXYNOS5_CLKDIV_TOP1_ACLK300_GSCL_SHIFT));
+
+
+	__raw_writel(tmp, EXYNOS5_CLKDIV_TOP1);
+
+	do {
+		tmp = __raw_readl(EXYNOS5_CLKDIV_STAT_TOP1);
+		tmp2 = __raw_readl(EXYNOS5_CLKDIV_STAT_TOP0);
+	} while ((tmp & 0x1110000) && (tmp2 & 0x80000));
+
+	/* Change Divider - LEX */
+	tmp = data->lex_divtable[div_index];
+
+	__raw_writel(tmp, EXYNOS5_CLKDIV_LEX);
+
+	do {
+		tmp = __raw_readl(EXYNOS5_CLKDIV_STAT_LEX);
+	} while (tmp & 0x110);
+
+	/* Change Divider - R0X */
+	tmp = __raw_readl(EXYNOS5_CLKDIV_R0X);
+
+	tmp &= ~EXYNOS5_CLKDIV_R0X_PCLK_R0X_MASK;
+
+	tmp |= (clkdiv_r0x[div_index][0] << EXYNOS5_CLKDIV_R0X_PCLK_R0X_SHIFT);
+
+	__raw_writel(tmp, EXYNOS5_CLKDIV_R0X);
+
+	do {
+		tmp = __raw_readl(EXYNOS5_CLKDIV_STAT_R0X);
+	} while (tmp & 0x10);
+
+	/* Change Divider - R1X */
+	tmp = data->r1x_divtable[div_index];
+
+	__raw_writel(tmp, EXYNOS5_CLKDIV_R1X);
+
+	do {
+		tmp = __raw_readl(EXYNOS5_CLKDIV_STAT_R1X);
+	} while (tmp & 0x10);
+}
+
+static void exynos5250_target(struct busfreq_data *data, enum ppmu_type type,
+			      int index)
+{
+	if (type == PPMU_MIF)
+		exynos5250_target_for_mif(data, index);
+	else
+		exynos5250_target_for_int(data, index);
+}
+
+static int exynos5250_get_table_index(unsigned long freq, enum ppmu_type type)
+{
+	int index;
+
+	if (type == PPMU_MIF) {
+		for (index = LV_0; index < LV_MIF_END; index++)
+			if (freq == exynos5_busfreq_table_mif[index].mem_clk)
+				return index;
+	} else {
+		for (index = LV_0; index < LV_INT_END; index++)
+			if (freq == exynos5_busfreq_table_int[index].mem_clk)
+				return index;
+	}
+	return -EINVAL;
+}
+
+static void exynos5250_suspend(void)
+{
+	/* Nothing to do */
+}
+
+static void exynos5250_resume(void)
+{
+	__raw_writel(drex2_pause_ctrl, EXYNOS5_DREX2_PAUSE);
+}
+
+static void exynos5250_monitor(struct busfreq_data *data,
+			struct opp **mif_opp, struct opp **int_opp)
+{
+	int i;
+	unsigned int cpu_load_average = 0;
+	unsigned int ddr_c_load_average = 0;
+	unsigned int ddr_l_load_average = 0;
+	unsigned int ddr_r1_load_average = 0;
+	unsigned int right0_load_average = 0;
+	unsigned int ddr_load_average;
+	unsigned long cpufreq = 0;
+	unsigned long freq_int_right0 = 0;
+	unsigned long lockfreq[PPMU_TYPE_END];
+	unsigned long freq[PPMU_TYPE_END];
+	unsigned long cpu_load;
+	unsigned long ddr_load=0;
+	unsigned long ddr_load_int=0;
+	unsigned long ddr_c_load;
+	unsigned long ddr_r1_load;
+	unsigned long ddr_l_load;
+	unsigned long right0_load;
+	struct opp *opp[PPMU_TYPE_END];
+	unsigned long newfreq[PPMU_TYPE_END];
+
+	ppmu_update(data->dev[PPMU_MIF], 3);
+
+	/* Convert from base xxx to base maxfreq */
+	cpu_load = div64_u64(ppmu_load[PPMU_CPU] * data->curr_freq[PPMU_MIF], data->max_freq[PPMU_MIF]);
+	ddr_c_load = div64_u64(ppmu_load[PPMU_DDR_C] * data->curr_freq[PPMU_MIF], data->max_freq[PPMU_MIF]);
+	ddr_r1_load = div64_u64(ppmu_load[PPMU_DDR_R1] * data->curr_freq[PPMU_MIF], data->max_freq[PPMU_MIF]);
+	ddr_l_load = div64_u64(ppmu_load[PPMU_DDR_L] * data->curr_freq[PPMU_MIF], data->max_freq[PPMU_MIF]);
+	right0_load = div64_u64(ppmu_load[PPMU_RIGHT0_BUS] * data->curr_freq[PPMU_INT], data->max_freq[PPMU_INT]);
+
+	data->load_history[PPMU_CPU][data->index] = cpu_load;
+	data->load_history[PPMU_DDR_C][data->index] = ddr_c_load;
+	data->load_history[PPMU_DDR_R1][data->index] = ddr_r1_load;
+	data->load_history[PPMU_DDR_L][data->index] = ddr_l_load;
+	data->load_history[PPMU_RIGHT0_BUS][data->index++] = right0_load;
+
+	if (data->index >= LOAD_HISTORY_SIZE)
+		data->index = 0;
+
+	for (i = 0; i < LOAD_HISTORY_SIZE; i++) {
+		cpu_load_average += data->load_history[PPMU_CPU][i];
+		ddr_c_load_average += data->load_history[PPMU_DDR_C][i];
+		ddr_r1_load_average += data->load_history[PPMU_DDR_R1][i];
+		ddr_l_load_average += data->load_history[PPMU_DDR_L][i];
+		right0_load_average += data->load_history[PPMU_RIGHT0_BUS][i];
+	}
+
+	/* Calculate average Load */
+	cpu_load_average /= LOAD_HISTORY_SIZE;
+	ddr_c_load_average /= LOAD_HISTORY_SIZE;
+	ddr_r1_load_average /= LOAD_HISTORY_SIZE;
+	ddr_l_load_average /= LOAD_HISTORY_SIZE;
+	right0_load_average /= LOAD_HISTORY_SIZE;
+
+	if (ddr_c_load >= ddr_l_load) {
+		ddr_load = ddr_c_load;
+		ddr_load_average = ddr_c_load_average;
+	} else {
+		ddr_load = ddr_l_load;
+		ddr_load_average = ddr_l_load_average;
+	}
+
+	ddr_load_int = ddr_load;
+
+	//Calculate MIF/INT frequency level
+	if (ddr_r1_load >= MIF_R1_THRESHOLD) {
+		freq[PPMU_MIF] = data->max_freq[PPMU_MIF];
+		if (right0_load >= INT_RIGHT0_THRESHOLD) {
+			freq[PPMU_INT] = data->max_freq[PPMU_INT];
+			goto go_max;
+		} else {
+			freq_int_right0 = div64_u64(data->max_freq[PPMU_INT] * right0_load, INT_RIGHT0_THRESHOLD);
+		}
+	} else {
+		// Caculate next MIF frequency
+		if (ddr_load >= MIF_MAX_THRESHOLD) {
+			freq[PPMU_MIF] = data->max_freq[PPMU_MIF];
+		} else if ( ddr_load < IDLE_THRESHOLD) {
+			if (ddr_load_average < IDLE_THRESHOLD)
+				freq[PPMU_MIF] = step_down(data, PPMU_MIF, 1);
+			else
+				freq[PPMU_MIF] = data->curr_freq[PPMU_MIF];
+		} else {
+			if (ddr_load < ddr_load_average) {
+				ddr_load = ddr_load_average;
+				if (ddr_load >= MIF_MAX_THRESHOLD)
+					ddr_load = MIF_MAX_THRESHOLD;
+			}
+			freq[PPMU_MIF] = div64_u64(data->max_freq[PPMU_MIF] * ddr_load, MIF_MAX_THRESHOLD);
+		}
+
+		freq_int_right0 = div64_u64(data->max_freq[PPMU_INT] * right0_load, INT_RIGHT0_THRESHOLD);
+	}
+
+	// Caculate next INT frequency
+	if (ddr_load_int >= INT_MAX_THRESHOLD) {
+		freq[PPMU_INT] = data->max_freq[PPMU_INT];
+	} else if ( ddr_load_int < IDLE_THRESHOLD) {
+		if (ddr_load_average < IDLE_THRESHOLD)
+			freq[PPMU_INT] = step_down(data, PPMU_INT, 1);
+		else
+			freq[PPMU_INT] = data->curr_freq[PPMU_INT];
+	} else {
+		if (ddr_load_int < ddr_load_average) {
+			ddr_load_int = ddr_load_average;
+			if (ddr_load_int >= INT_MAX_THRESHOLD)
+				ddr_load_int = INT_MAX_THRESHOLD;
+		}
+		freq[PPMU_INT] = div64_u64(data->max_freq[PPMU_INT] * ddr_load_int, INT_MAX_THRESHOLD);
+	}
+
+	freq[PPMU_INT] = max(freq[PPMU_INT], freq_int_right0);
+
+	if (freq[PPMU_INT] == data->max_freq[PPMU_INT])
+		freq[PPMU_MIF] = data->max_freq[PPMU_MIF];
+
+go_max:
+#ifdef BUSFREQ_PROFILE_DEBUG
+	printk(KERN_DEBUG "cpu[%ld] l[%ld] c[%ld] r1[%ld] rt[%ld] m_load[%ld] i_load[%ld]\n",
+			cpu_load, ddr_l_load, ddr_c_load, ddr_r1_load, right0_load, ddr_load, ddr_load_int);
+#endif
+	lockfreq[PPMU_MIF] = (dev_max_freq(data->dev[PPMU_MIF])/1000)*1000;
+	lockfreq[PPMU_INT] = (dev_max_freq(data->dev[PPMU_MIF])%1000)*1000;
+#ifdef BUSFREQ_PROFILE_DEBUG
+	printk(KERN_DEBUG "i_cf[%ld] m_cf[%ld] i_nf[%ld] m_nf[%ld] lock_Mfreq[%ld] lock_Ifreq[%ld]\n",
+			data->curr_freq[PPMU_INT],data->curr_freq[PPMU_MIF],freq[PPMU_INT], freq[PPMU_MIF], lockfreq[PPMU_MIF], lockfreq[PPMU_INT]);
+#endif
+	newfreq[PPMU_MIF] = max(lockfreq[PPMU_MIF], freq[PPMU_MIF]);
+	newfreq[PPMU_INT] = max(lockfreq[PPMU_INT], freq[PPMU_INT]);
+	opp[PPMU_MIF] = opp_find_freq_ceil(data->dev[PPMU_MIF], &newfreq[PPMU_MIF]);
+	opp[PPMU_INT] = opp_find_freq_ceil(data->dev[PPMU_INT], &newfreq[PPMU_INT]);
+
+	*mif_opp = opp[PPMU_MIF];
+	*int_opp = opp[PPMU_INT];
+}
+
+static void busfreq_early_suspend(struct early_suspend *h)
+{
+	unsigned long freq;
+	struct busfreq_data *data = container_of(h, struct busfreq_data,
+			busfreq_early_suspend_handler);
+	freq = data->min_freq[PPMU_MIF] + data->min_freq[PPMU_INT] / 1000;
+	//dev_lock(data->dev[PPMU_MIF], data->dev[PPMU_MIF], freq);
+	dev_unlock(data->dev[PPMU_MIF], data->dev[PPMU_MIF]);
+}
+
+static void busfreq_late_resume(struct early_suspend *h)
+{
+	struct busfreq_data *data = container_of(h, struct busfreq_data,
+			busfreq_early_suspend_handler);
+	/* Request min MIF/INT 300MHz */
+	dev_lock(data->dev[PPMU_MIF], data->dev[PPMU_MIF], 300150);
+}
+
+int exynos5250_init(struct device *dev, struct busfreq_data *data)
+{
+	unsigned int i, tmp;
+	unsigned long maxfreq = ULONG_MAX;
+	unsigned long minfreq = 0;
+	unsigned long cdrexfreq;
+	unsigned long lrbusfreq;
+	struct clk *clk;
+	int ret;
+
+	/* Enable pause function for DREX2 DVFS */
+	drex2_pause_ctrl = __raw_readl(EXYNOS5_DREX2_PAUSE);
+	drex2_pause_ctrl |= DMC_PAUSE_ENABLE;
+	__raw_writel(drex2_pause_ctrl, EXYNOS5_DREX2_PAUSE);
+
+	clk = clk_get(NULL, "mclk_cdrex");
+	if (IS_ERR(clk)) {
+		dev_err(dev, "Fail to get mclk_cdrex clock");
+		ret = PTR_ERR(clk);
+		return ret;
+	}
+	cdrexfreq = clk_get_rate(clk) / 1000;
+	clk_put(clk);
+
+	clk = clk_get(NULL, "aclk_266");
+	if (IS_ERR(clk)) {
+		dev_err(dev, "Fail to get aclk_266 clock");
+		ret = PTR_ERR(clk);
+		return ret;
+	}
+	lrbusfreq = clk_get_rate(clk) / 1000;
+	clk_put(clk);
+
+	if (cdrexfreq == 800000) {
+		clkdiv_cdrex = clkdiv_cdrex_for800;
+		exynos5_busfreq_table_mif = exynos5_busfreq_table_for800;
+		exynos5_mif_volt = exynos5_mif_volt_for800;
+	} else if (cdrexfreq == 666857) {
+		clkdiv_cdrex = clkdiv_cdrex_for667;
+		exynos5_busfreq_table_mif = exynos5_busfreq_table_for667;
+		exynos5_mif_volt = exynos5_mif_volt_for667;
+	} else if (cdrexfreq == 533000) {
+		clkdiv_cdrex = clkdiv_cdrex_for533;
+		exynos5_busfreq_table_mif = exynos5_busfreq_table_for533;
+		exynos5_mif_volt = exynos5_mif_volt_for533;
+	} else if (cdrexfreq == 400000) {
+		clkdiv_cdrex = clkdiv_cdrex_for400;
+		exynos5_busfreq_table_mif = exynos5_busfreq_table_for400;
+		exynos5_mif_volt = exynos5_mif_volt_for400;
+	} else {
+		dev_err(dev, "Don't support cdrex table\n");
+		return -EINVAL;
+	}
+
+	tmp = __raw_readl(EXYNOS5_CLKDIV_LEX);
+
+	for (i = LV_0; i < LV_INT_END; i++) {
+		tmp &= ~(EXYNOS5_CLKDIV_LEX_ATCLK_LEX_MASK | EXYNOS5_CLKDIV_LEX_PCLK_LEX_MASK);
+
+		tmp |= ((clkdiv_lex[i][0] << EXYNOS5_CLKDIV_LEX_ATCLK_LEX_SHIFT) |
+			(clkdiv_lex[i][1] << EXYNOS5_CLKDIV_LEX_PCLK_LEX_SHIFT));
+
+		data->lex_divtable[i] = tmp;
+	}
+
+	tmp = __raw_readl(EXYNOS5_CLKDIV_R0X);
+
+	for (i = LV_0; i < LV_INT_END; i++) {
+
+		tmp &= ~EXYNOS5_CLKDIV_R0X_PCLK_R0X_MASK;
+
+		tmp |= (clkdiv_r0x[i][0] << EXYNOS5_CLKDIV_R0X_PCLK_R0X_SHIFT);
+
+		data->r0x_divtable[i] = tmp;
+	}
+
+	tmp = __raw_readl(EXYNOS5_CLKDIV_R1X);
+
+	for (i = LV_0; i < LV_INT_END; i++) {
+		tmp &= ~EXYNOS5_CLKDIV_R1X_PCLK_R1X_MASK;
+
+		tmp |= (clkdiv_r1x[i][0] << EXYNOS5_CLKDIV_R1X_PCLK_R1X_SHIFT);
+
+		data->r1x_divtable[i] = tmp;
+	}
+
+	tmp = __raw_readl(EXYNOS5_CLKDIV_CDREX);
+
+	if (samsung_rev() < EXYNOS5250_REV_1_0) {
+		for (i = LV_0; i < LV_MIF_END; i++) {
+			tmp &= ~(EXYNOS5_CLKDIV_CDREX_MCLK_DPHY_MASK |
+				 EXYNOS5_CLKDIV_CDREX_MCLK_CDREX2_MASK |
+				 EXYNOS5_CLKDIV_CDREX_ACLK_CDREX_MASK |
+				 EXYNOS5_CLKDIV_CDREX_MCLK_CDREX_MASK |
+				 EXYNOS5_CLKDIV_CDREX_PCLK_CDREX_MASK |
+				 EXYNOS5_CLKDIV_CDREX_ACLK_CLK400_MASK |
+				 EXYNOS5_CLKDIV_CDREX_ACLK_C2C200_MASK |
+				 EXYNOS5_CLKDIV_CDREX_ACLK_EFCON_MASK);
+
+			tmp |= ((clkdiv_cdrex[i][0] << EXYNOS5_CLKDIV_CDREX_MCLK_DPHY_SHIFT) |
+				(clkdiv_cdrex[i][1] << EXYNOS5_CLKDIV_CDREX_MCLK_CDREX2_SHIFT) |
+				(clkdiv_cdrex[i][2] << EXYNOS5_CLKDIV_CDREX_ACLK_CDREX_SHIFT) |
+				(clkdiv_cdrex[i][3] << EXYNOS5_CLKDIV_CDREX_MCLK_CDREX_SHIFT) |
+				(clkdiv_cdrex[i][4] << EXYNOS5_CLKDIV_CDREX_PCLK_CDREX_SHIFT) |
+				(clkdiv_cdrex[i][5] << EXYNOS5_CLKDIV_CDREX_ACLK_CLK400_SHIFT) |
+				(clkdiv_cdrex[i][6] << EXYNOS5_CLKDIV_CDREX_ACLK_C2C200_SHIFT) |
+				(clkdiv_cdrex[i][8] << EXYNOS5_CLKDIV_CDREX_ACLK_EFCON_SHIFT));
+
+				data->cdrex_divtable[i] = tmp;
+		}
+	} else {
+		for (i = LV_0; i < LV_MIF_END; i++) {
+			tmp &= ~(EXYNOS5_CLKDIV_CDREX_MCLK_DPHY_MASK |
+				 EXYNOS5_CLKDIV_CDREX_MCLK_CDREX2_MASK |
+				 EXYNOS5_CLKDIV_CDREX_ACLK_CDREX_MASK |
+				 EXYNOS5_CLKDIV_CDREX_MCLK_CDREX_MASK |
+				 EXYNOS5_CLKDIV_CDREX_PCLK_CDREX_MASK |
+				 EXYNOS5_CLKDIV_CDREX_ACLK_EFCON_MASK);
+
+			tmp |= ((clkdiv_cdrex[i][0] << EXYNOS5_CLKDIV_CDREX_MCLK_DPHY_SHIFT) |
+				(clkdiv_cdrex[i][1] << EXYNOS5_CLKDIV_CDREX_MCLK_CDREX2_SHIFT) |
+				(clkdiv_cdrex[i][2] << EXYNOS5_CLKDIV_CDREX_ACLK_CDREX_SHIFT) |
+				(clkdiv_cdrex[i][3] << EXYNOS5_CLKDIV_CDREX_MCLK_CDREX_SHIFT) |
+				(clkdiv_cdrex[i][4] << EXYNOS5_CLKDIV_CDREX_PCLK_CDREX_SHIFT) |
+				(clkdiv_cdrex[i][8] << EXYNOS5_CLKDIV_CDREX_ACLK_EFCON_SHIFT));
+
+				data->cdrex_divtable[i] = tmp;
+		}
+	}
+
+	if (samsung_rev() < EXYNOS5250_REV_1_0) {
+		tmp = __raw_readl(EXYNOS5_CLKDIV_CDREX2);
+
+		for (i = LV_0; i < LV_MIF_END; i++) {
+			tmp &= ~EXYNOS5_CLKDIV_CDREX2_MCLK_EFPHY_MASK;
+
+			tmp |= clkdiv_cdrex[i][7] << EXYNOS5_CLKDIV_CDREX2_MCLK_EFPHY_SHIFT;
+
+			data->cdrex2_divtable[i] = tmp;
+
+		}
+	}
+
+	exynos5250_set_bus_volt();
+
+	data->dev[PPMU_MIF] = dev;
+	data->dev[PPMU_INT] = &busfreq_for_int;
+
+	for (i = LV_0; i < LV_MIF_END; i++) {
+		ret = opp_add(data->dev[PPMU_MIF], exynos5_busfreq_table_mif[i].mem_clk,
+				exynos5_busfreq_table_mif[i].volt);
+		if (ret) {
+			dev_err(dev, "Fail to add opp entries.\n");
+			return ret;
+		}
+	}
+
+#if defined(CONFIG_DP_60HZ_P11) || defined(CONFIG_DP_60HZ_P10)
+	if (cdrexfreq == 666857) {
+		opp_disable(data->dev[PPMU_MIF], 334000);
+		opp_disable(data->dev[PPMU_MIF], 110000);
+	} else if (cdrexfreq == 533000) {
+		opp_disable(data->dev[PPMU_MIF], 267000);
+		opp_disable(data->dev[PPMU_MIF], 107000);
+	} else if (cdrexfreq == 400000) {
+		opp_disable(data->dev[PPMU_MIF], 267000);
+		opp_disable(data->dev[PPMU_MIF], 100000);
+	}
+#endif
+
+	for (i = LV_0; i < LV_INT_END; i++) {
+		ret = opp_add(data->dev[PPMU_INT], exynos5_busfreq_table_int[i].mem_clk,
+				exynos5_busfreq_table_int[i].volt);
+		if (ret) {
+			dev_err(dev, "Fail to add opp entries.\n");
+			return ret;
+		}
+	}
+
+	data->target = exynos5250_target;
+	data->get_table_index = exynos5250_get_table_index;
+	data->monitor = exynos5250_monitor;
+	data->busfreq_suspend = exynos5250_suspend;
+	data->busfreq_resume = exynos5250_resume;
+	data->sampling_rate = usecs_to_jiffies(100000);
+
+	data->table[PPMU_MIF] = exynos5_busfreq_table_mif;
+	data->table[PPMU_INT] = exynos5_busfreq_table_int;
+
+	/* Find max frequency for mif */
+	data->max_freq[PPMU_MIF] =
+			opp_get_freq(opp_find_freq_floor(data->dev[PPMU_MIF], &maxfreq));
+	data->min_freq[PPMU_MIF] =
+			opp_get_freq(opp_find_freq_ceil(data->dev[PPMU_MIF], &minfreq));
+	data->curr_freq[PPMU_MIF] =
+			opp_get_freq(opp_find_freq_ceil(data->dev[PPMU_MIF], &cdrexfreq));
+	/* Find max frequency for int */
+	maxfreq = ULONG_MAX;
+	minfreq = 0;
+	data->max_freq[PPMU_INT] =
+			opp_get_freq(opp_find_freq_floor(data->dev[PPMU_INT], &maxfreq));
+	data->min_freq[PPMU_INT] =
+			opp_get_freq(opp_find_freq_ceil(data->dev[PPMU_INT], &minfreq));
+	data->curr_freq[PPMU_INT] =
+			opp_get_freq(opp_find_freq_ceil(data->dev[PPMU_INT], &lrbusfreq));
+
+	data->vdd_reg[PPMU_INT] = regulator_get(NULL, "vdd_int");
+	if (IS_ERR(data->vdd_reg[PPMU_INT])) {
+		pr_err("failed to get resource %s\n", "vdd_int");
+		return -ENODEV;
+	}
+
+	data->vdd_reg[PPMU_MIF] = regulator_get(NULL, "vdd_mif");
+	if (IS_ERR(data->vdd_reg[PPMU_MIF])) {
+		pr_err("failed to get resource %s\n", "vdd_mif");
+		regulator_put(data->vdd_reg[PPMU_INT]);
+		return -ENODEV;
+	}
+
+        data->busfreq_early_suspend_handler.suspend = &busfreq_early_suspend;
+	data->busfreq_early_suspend_handler.resume = &busfreq_late_resume;
+
+	data->busfreq_early_suspend_handler.suspend = &busfreq_early_suspend;
+	data->busfreq_early_suspend_handler.resume = &busfreq_late_resume;
+
+	/* Request min 300MHz for MIF and 150MHz for  INT*/
+	dev_lock(dev, dev, 300150);
+
+	register_early_suspend(&data->busfreq_early_suspend_handler);
+
+	tmp = __raw_readl(EXYNOS5_ABBG_INT_CONTROL);
+	tmp &= ~(0x1f | (1 << 31) | (1 << 7));
+	tmp |= ((8 + INT_RBB) | (1 << 31) | (1 << 7));
+	__raw_writel(tmp, EXYNOS5_ABBG_INT_CONTROL);
+
+	return 0;
+}
diff --git a/arch/arm/mach-exynos/busfreq_opp_exynos4.c b/arch/arm/mach-exynos/busfreq_opp_exynos4.c
new file mode 100644
index 0000000..e6b28c9
--- /dev/null
+++ b/arch/arm/mach-exynos/busfreq_opp_exynos4.c
@@ -0,0 +1,677 @@
+/* linux/arch/arm/mach-exynos/busfreq_opp_exynos4.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * EXYNOS4 - BUS clock frequency scaling support with OPP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/types.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/regulator/consumer.h>
+#include <linux/sysfs.h>
+#include <linux/platform_device.h>
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/cpu.h>
+#include <linux/ktime.h>
+#include <linux/tick.h>
+#include <linux/kernel_stat.h>
+#include <linux/suspend.h>
+#include <linux/reboot.h>
+#include <linux/slab.h>
+#include <linux/opp.h>
+#include <linux/clk.h>
+#include <linux/workqueue.h>
+
+#include <asm/mach-types.h>
+
+#include <mach/ppmu.h>
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/gpio.h>
+#include <mach/regs-mem.h>
+#include <mach/cpufreq.h>
+#include <mach/dev.h>
+#include <mach/busfreq_exynos4.h>
+#include <mach/smc.h>
+
+#include <plat/map-s5p.h>
+#include <plat/cpu.h>
+#include <plat/clock.h>
+
+#define BUSFREQ_DEBUG	1
+
+static DEFINE_MUTEX(busfreq_lock);
+
+struct busfreq_control {
+	struct opp *opp_lock;
+	struct device *dev;
+	struct busfreq_data *data;
+	bool init_done;
+};
+
+static struct busfreq_control bus_ctrl;
+
+void update_busfreq_stat(struct busfreq_data *data, unsigned int index)
+{
+#ifdef BUSFREQ_DEBUG
+	unsigned long long cur_time = get_jiffies_64();
+	data->time_in_state[index] = cputime64_add(data->time_in_state[index], cputime_sub(cur_time, data->last_time));
+	data->last_time = cur_time;
+#endif
+}
+
+static struct opp __maybe_unused *step_up(struct busfreq_data *data, int step)
+{
+	int i;
+	struct opp *opp = data->curr_opp;
+	unsigned long newfreq;
+
+	if (data->max_opp == data->curr_opp)
+		return data->curr_opp;
+
+	for (i = 0; i < step; i++) {
+		newfreq = opp_get_freq(opp) + 1;
+		opp = opp_find_freq_ceil(data->dev, &newfreq);
+
+		if (opp == data->max_opp)
+			break;
+	}
+
+	return opp;
+}
+
+struct opp *step_down(struct busfreq_data *data, int step)
+{
+	int i;
+	struct opp *opp = data->curr_opp;
+	unsigned long newfreq;
+
+	if (data->min_opp == data->curr_opp)
+		return data->curr_opp;
+
+	for (i = 0; i < step; i++) {
+		newfreq = opp_get_freq(opp) - 1;
+		opp = opp_find_freq_floor(data->dev, &newfreq);
+
+		if (opp == data->min_opp)
+			break;
+	}
+
+	return opp;
+}
+
+static unsigned int _target(struct busfreq_data *data, struct opp *new)
+{
+	unsigned int index;
+	unsigned int voltage;
+	unsigned long newfreq;
+	unsigned long currfreq;
+
+	newfreq = opp_get_freq(new);
+	currfreq = opp_get_freq(data->curr_opp);
+
+	index = data->get_table_index(new);
+
+	if (newfreq == 0 || newfreq == currfreq || data->use == false)
+		return data->get_table_index(data->curr_opp);
+
+	voltage = opp_get_voltage(new);
+	if (newfreq > currfreq) {
+		regulator_set_voltage(data->vdd_mif, voltage,
+				voltage + 25000);
+		voltage = data->get_int_volt(index);
+		regulator_set_voltage(data->vdd_int, voltage,
+				voltage + 25000);
+		/*if (data->busfreq_prepare)
+			data->busfreq_prepare(index);*/
+	}
+	if (data->set_qos)
+		data->set_qos(index);
+
+	data->target(index);
+
+	if (newfreq < currfreq) {
+		/*if (data->busfreq_post)
+			data->busfreq_post(index);*/
+		regulator_set_voltage(data->vdd_mif, voltage,
+				voltage + 25000);
+		voltage = data->get_int_volt(index);
+		regulator_set_voltage(data->vdd_int, voltage,
+				voltage + 25000);
+	}
+	data->curr_opp = new;
+
+	return index;
+}
+
+static void exynos_busfreq_timer(struct work_struct *work)
+{
+	struct delayed_work *delayed_work = to_delayed_work(work);
+	struct busfreq_data *data = container_of(delayed_work, struct busfreq_data,
+			worker);
+	struct opp *opp;
+	unsigned int index;
+
+	opp = data->monitor(data);
+
+	ppmu_start(data->dev);
+
+	mutex_lock(&busfreq_lock);
+
+	if (bus_ctrl.opp_lock)
+		opp = bus_ctrl.opp_lock;
+
+	index = _target(data, opp);
+
+	update_busfreq_stat(data, index);
+	mutex_unlock(&busfreq_lock);
+	queue_delayed_work(system_freezable_wq, &data->worker, data->sampling_rate);
+}
+
+static int exynos_buspm_notifier_event(struct notifier_block *this,
+		unsigned long event, void *ptr)
+{
+	struct busfreq_data *data = container_of(this, struct busfreq_data,
+			exynos_buspm_notifier);
+
+	switch (event) {
+	case PM_SUSPEND_PREPARE:
+		mutex_lock(&busfreq_lock);
+		_target(data, data->max_opp);
+		data->use = false;
+		mutex_unlock(&busfreq_lock);
+		return NOTIFY_OK;
+	case PM_POST_RESTORE:
+	case PM_POST_SUSPEND:
+		data->use = true;
+		return NOTIFY_OK;
+	}
+
+	return NOTIFY_DONE;
+}
+
+static int exynos_busfreq_reboot_event(struct notifier_block *this,
+		unsigned long code, void *unused)
+{
+	struct busfreq_data *data = container_of(this, struct busfreq_data,
+			exynos_reboot_notifier);
+
+	unsigned long voltage = opp_get_voltage(data->max_opp);
+	unsigned int index = data->get_table_index(data->max_opp);
+
+	mutex_lock(&busfreq_lock);
+
+	regulator_set_voltage(data->vdd_mif, voltage, voltage + 25000);
+	voltage = data->get_int_volt(index);
+	regulator_set_voltage(data->vdd_int, voltage, voltage + 25000);
+	data->use = false;
+
+	mutex_unlock(&busfreq_lock);
+
+	printk(KERN_INFO "REBOOT Notifier for BUSFREQ\n");
+	return NOTIFY_DONE;
+}
+
+int exynos_busfreq_lock(unsigned int nId,
+	enum busfreq_level_request busfreq_level)
+{
+	return 0;
+}
+
+void exynos_busfreq_lock_free(unsigned int nId)
+{
+}
+
+static ssize_t show_level_lock(struct device *device,
+		struct device_attribute *attr, char *buf)
+{
+	struct platform_device *pdev = to_platform_device(bus_ctrl.dev);
+	struct busfreq_data *data = (struct busfreq_data *)platform_get_drvdata(pdev);
+	int len = 0;
+	unsigned long freq;
+
+	freq = bus_ctrl.opp_lock == NULL ? 0 : opp_get_freq(bus_ctrl.opp_lock);
+
+	len = sprintf(buf, "Current Freq(MIF/INT) : %lu\n", opp_get_freq(data->curr_opp));
+	len += sprintf(buf + len, "Current Lock Freq(MIF/INT) : %lu\n", freq);
+
+	return len;
+}
+
+static ssize_t store_level_lock(struct device *device, struct device_attribute *attr,
+		const char *buf, size_t count)
+{
+	struct platform_device *pdev = to_platform_device(bus_ctrl.dev);
+	struct busfreq_data *data = (struct busfreq_data *)platform_get_drvdata(pdev);
+	struct opp *opp;
+	unsigned long freq;
+	unsigned long maxfreq = opp_get_freq(data->max_opp);
+	int ret;
+
+	ret = sscanf(buf, "%lu", &freq);
+	if ((freq == 0) || (ret == 0)) {
+		pr_info("Release bus level lock.\n");
+		bus_ctrl.opp_lock = NULL;
+		return count;
+	}
+
+	if (freq > maxfreq)
+		freq = maxfreq;
+
+	opp = opp_find_freq_ceil(bus_ctrl.dev, &freq);
+	bus_ctrl.opp_lock = opp;
+	pr_info("Lock Freq : %lu\n", opp_get_freq(opp));
+	return count;
+}
+
+static ssize_t show_locklist(struct device *device,
+		struct device_attribute *attr, char *buf)
+{
+	return dev_lock_list(bus_ctrl.dev, buf);
+}
+
+static ssize_t show_time_in_state(struct device *device,
+		struct device_attribute *attr, char *buf)
+{
+	struct platform_device *pdev = to_platform_device(bus_ctrl.dev);
+	struct busfreq_data *data = (struct busfreq_data *)platform_get_drvdata(pdev);
+	ssize_t len = 0;
+	int i;
+
+	for (i = 0; i < data->table_size; i++)
+		len += sprintf(buf + len, "%u %llu\n", data->table[i].mem_clk,
+				(unsigned long long)cputime64_to_clock_t(data->time_in_state[i]));
+
+	return len;
+}
+
+static ssize_t show_up_threshold(struct device *device,
+		 struct device_attribute *attr, char *buf)
+{
+	int len = 0;
+	len = sprintf(buf, "%d\n", up_threshold);
+
+	return len;
+}
+static ssize_t store_up_threshold(struct device *device,
+		struct device_attribute *attr,
+		const char *buf, size_t count)
+{
+	int ret;
+
+	ret = sscanf(buf, "%d", &up_threshold);
+	return count;
+}
+
+static ssize_t show_ppmu_threshold(struct device *device,
+		struct device_attribute *attr, char *buf)
+{
+	int len = 0;
+	len = sprintf(buf, "%d\n", ppmu_threshold);
+
+	return len;
+}
+static ssize_t store_ppmu_threshold(struct device *device,
+		struct device_attribute *attr,
+		const char *buf, size_t count)
+{
+	int ret;
+
+	ret = sscanf(buf, "%d", &ppmu_threshold);
+	return count;
+}
+
+static ssize_t show_idle_threshold(struct device *device,
+		struct device_attribute *attr, char *buf)
+{
+	int len = 0;
+	len = sprintf(buf, "%d\n", idle_threshold);
+
+	return len;
+}
+static ssize_t store_idle_threshold(struct device *device,
+		struct device_attribute *attr,
+		const char *buf, size_t count)
+{
+	int ret;
+
+	ret = sscanf(buf, "%d", &idle_threshold);
+	return count;
+}
+
+static ssize_t show_up_cpu_threshold(struct device *device,
+		struct device_attribute *attr, char *buf)
+{
+	int len = 0;
+	len = sprintf(buf, "%d\n", up_cpu_threshold);
+
+	return len;
+}
+static ssize_t store_up_cpu_threshold(struct device *device,
+		struct device_attribute *attr,
+		const char *buf, size_t count)
+{
+	int ret;
+
+	ret = sscanf(buf, "%d", &up_cpu_threshold);
+	return count;
+}
+
+static ssize_t show_max_cpu_threshold(struct device *device,
+		struct device_attribute *attr, char *buf)
+{
+	int len = 0;
+	len = sprintf(buf, "%d\n", max_cpu_threshold);
+
+	return len;
+}
+static ssize_t store_max_cpu_threshold(struct device *device,
+		struct device_attribute *attr,
+		const char *buf, size_t count)
+{
+	int ret;
+
+	ret = sscanf(buf, "%d", &max_cpu_threshold);
+	return count;
+}
+
+static ssize_t show_cpu_slope_size(struct device *device,
+		struct device_attribute *attr, char *buf)
+{
+	int len = 0;
+	len = sprintf(buf, "%d\n", cpu_slope_size);
+
+	return len;
+}
+static ssize_t store_cpu_slope_size(struct device *device,
+		struct device_attribute *attr,
+		const char *buf, size_t count)
+{
+	int ret;
+
+	ret = sscanf(buf, "%d", &cpu_slope_size);
+	return count;
+}
+
+static ssize_t show_dmc_max_threshold(struct device *device,
+		struct device_attribute *attr, char *buf)
+{
+	int len = 0;
+	len = sprintf(buf, "%d\n", dmc_max_threshold);
+
+	return len;
+}
+static ssize_t store_dmc_max_threshold(struct device *device,
+		struct device_attribute *attr,
+		const char *buf, size_t count)
+{
+	int ret;
+
+	ret = sscanf(buf, "%d", &dmc_max_threshold);
+	if (dmc_max_threshold < 1)
+		dmc_max_threshold = 1;
+	return count;
+}
+
+static ssize_t show_load_history_size(struct device *device,
+		struct device_attribute *attr, char *buf)
+{
+	int len = 0;
+	len = sprintf(buf, "%d\n", load_history_size);
+
+	return len;
+}
+static ssize_t store_load_history_size(struct device *device,
+		struct device_attribute *attr,
+		const char *buf, size_t count)
+{
+	int ret;
+
+	ret = sscanf(buf, "%d", &load_history_size);
+	if (load_history_size < 1)
+		load_history_size = 1;
+	if (load_history_size > LOAD_HISTORY_SIZE)
+		load_history_size = LOAD_HISTORY_SIZE;
+	return count;
+}
+
+static DEVICE_ATTR(curr_freq, 0664, show_level_lock, store_level_lock);
+static DEVICE_ATTR(lock_list, 0664, show_locklist, NULL);
+static DEVICE_ATTR(time_in_state, 0664, show_time_in_state, NULL);
+static DEVICE_ATTR(up_threshold, 0664, show_up_threshold, store_up_threshold);
+static DEVICE_ATTR(ppmu_threshold, 0664, show_ppmu_threshold,
+					store_ppmu_threshold);
+static DEVICE_ATTR(idle_threshold, 0664, show_idle_threshold,
+					store_idle_threshold);
+static DEVICE_ATTR(up_cpu_threshold, 0664, show_up_cpu_threshold,
+					store_up_cpu_threshold);
+static DEVICE_ATTR(max_cpu_threshold, 0664, show_max_cpu_threshold,
+					store_max_cpu_threshold);
+static DEVICE_ATTR(cpu_slope_size, 0664, show_cpu_slope_size,
+					store_cpu_slope_size);
+static DEVICE_ATTR(dmc_max_threshold, 0664, show_dmc_max_threshold,
+					store_dmc_max_threshold);
+static DEVICE_ATTR(load_history_size, 0664, show_load_history_size,
+					store_load_history_size);
+
+static struct attribute *busfreq_attributes[] = {
+	&dev_attr_curr_freq.attr,
+	&dev_attr_lock_list.attr,
+	&dev_attr_time_in_state.attr,
+	&dev_attr_up_threshold.attr,
+	&dev_attr_ppmu_threshold.attr,
+	&dev_attr_idle_threshold.attr,
+	&dev_attr_up_cpu_threshold.attr,
+	&dev_attr_max_cpu_threshold.attr,
+	&dev_attr_cpu_slope_size.attr,
+	&dev_attr_dmc_max_threshold.attr,
+	&dev_attr_load_history_size.attr,
+
+	NULL
+};
+
+void exynos_request_apply(unsigned long freq)
+{
+	struct opp *opp;
+	unsigned int index;
+
+	mutex_lock(&busfreq_lock);
+
+	if (!bus_ctrl.init_done)
+		goto out;
+
+	opp = bus_ctrl.data->curr_opp;
+
+	opp = opp_find_freq_ceil(bus_ctrl.data->dev, &freq);
+
+	if (bus_ctrl.opp_lock)
+		opp = bus_ctrl.opp_lock;
+
+	if (opp_get_freq(bus_ctrl.data->curr_opp) >= opp_get_freq(opp))
+		goto out;
+
+	index = _target(bus_ctrl.data, opp);
+
+	update_busfreq_stat(bus_ctrl.data, index);
+
+out:
+	mutex_unlock(&busfreq_lock);
+}
+
+static __devinit int exynos_busfreq_probe(struct platform_device *pdev)
+{
+	struct busfreq_data *data;
+	unsigned int val = 0;
+
+#ifdef CONFIG_ARM_TRUSTZONE
+	exynos_smc_readsfr(EXYNOS4_PA_DMC0_4212 + 0x4, &val);
+#else
+	val = __raw_readl(S5P_VA_DMC0 + 0x4);
+#endif
+	val = (val >> 8) & 0xf;
+
+	/* Check Memory Type Only support -> 0x5: 0xLPDDR2 */
+	if (val != 0x05) {
+		pr_err("[ %x ] Memory Type Undertermined.\n", val);
+		return -ENODEV;
+	}
+
+	data = kzalloc(sizeof(struct busfreq_data), GFP_KERNEL);
+	if (!data) {
+		pr_err("Unable to create busfreq_data struct.\n");
+		return -ENOMEM;
+	}
+
+	data->exynos_buspm_notifier.notifier_call =
+		exynos_buspm_notifier_event;
+	data->exynos_reboot_notifier.notifier_call =
+		exynos_busfreq_reboot_event;
+	data->busfreq_attr_group.attrs = busfreq_attributes;
+
+	if (soc_is_exynos4212() || soc_is_exynos4412()) {
+		data->init = exynos4x12_init;
+		data->target = exynos4x12_target;
+		data->get_int_volt = exynos4x12_get_int_volt;
+		data->get_table_index = exynos4x12_get_table_index;
+		data->monitor = exynos4x12_monitor;
+		data->busfreq_prepare = exynos4x12_prepare;
+		data->busfreq_post = exynos4x12_post;
+		data->set_qos = exynos4x12_set_qos;
+		data->busfreq_suspend = exynos4x12_suspend;
+		data->busfreq_resume = exynos4x12_resume;
+	} else {
+		pr_err("Unsupport device type.\n");
+		goto err_busfreq;
+	}
+
+	data->dev = &pdev->dev;
+	data->sampling_rate = usecs_to_jiffies(100000);
+	bus_ctrl.opp_lock =  NULL;
+	bus_ctrl.dev =  data->dev;
+	bus_ctrl.data =  data;
+
+	INIT_DELAYED_WORK(&data->worker, exynos_busfreq_timer);
+
+	if (data->init(&pdev->dev, data)) {
+		pr_err("Failed to init busfreq.\n");
+		goto err_busfreq;
+	}
+
+	data->time_in_state = kzalloc(sizeof(cputime64_t) * data->table_size, GFP_KERNEL);
+	if (!data->time_in_state) {
+		pr_err("Unable to create time_in_state.\n");
+		goto err_busfreq;
+	}
+
+
+	data->last_time = get_jiffies_64();
+
+	data->busfreq_kobject = kobject_create_and_add("busfreq",
+				&cpu_sysdev_class.kset.kobj);
+	if (!data->busfreq_kobject)
+		pr_err("Failed to create busfreq kobject.!\n");
+
+	if (sysfs_create_group(data->busfreq_kobject, &data->busfreq_attr_group))
+		pr_err("Failed to create attributes group.!\n");
+
+	if (register_pm_notifier(&data->exynos_buspm_notifier)) {
+		pr_err("Failed to setup buspm notifier\n");
+		goto err_pm_notifier;
+	}
+
+	data->use = true;
+	bus_ctrl.init_done = true;
+
+	if (register_reboot_notifier(&data->exynos_reboot_notifier))
+		pr_err("Failed to setup reboot notifier\n");
+
+	platform_set_drvdata(pdev, data);
+
+	queue_delayed_work(system_freezable_wq, &data->worker, 10 * data->sampling_rate);
+	return 0;
+
+err_pm_notifier:
+	kfree(data->time_in_state);
+
+err_busfreq:
+	if (!IS_ERR(data->vdd_int))
+		regulator_put(data->vdd_int);
+
+	if (!IS_ERR(data->vdd_mif))
+		regulator_put(data->vdd_mif);
+
+	kfree(data);
+	return -ENODEV;
+}
+
+static __devexit int exynos_busfreq_remove(struct platform_device *pdev)
+{
+	struct busfreq_data *data = platform_get_drvdata(pdev);
+
+	unregister_pm_notifier(&data->exynos_buspm_notifier);
+	unregister_reboot_notifier(&data->exynos_reboot_notifier);
+	regulator_put(data->vdd_int);
+	regulator_put(data->vdd_mif);
+	sysfs_remove_group(data->busfreq_kobject, &data->busfreq_attr_group);
+	kfree(data->time_in_state);
+	kfree(data);
+
+	return 0;
+}
+
+static int exynos_busfreq_suspend(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct busfreq_data *data = (struct busfreq_data *)platform_get_drvdata(pdev);
+
+	if (data->busfreq_suspend)
+		data->busfreq_suspend();
+	return 0;
+}
+
+static int exynos_busfreq_resume(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct busfreq_data *data = (struct busfreq_data *)platform_get_drvdata(pdev);
+	ppmu_reset(dev);
+
+	if (data->busfreq_resume)
+		data->busfreq_resume();
+	return 0;
+}
+
+static const struct dev_pm_ops exynos_busfreq_pm = {
+	.suspend = exynos_busfreq_suspend,
+	.resume = exynos_busfreq_resume,
+};
+
+static struct platform_driver exynos_busfreq_driver = {
+	.probe  = exynos_busfreq_probe,
+	.remove = __devexit_p(exynos_busfreq_remove),
+	.driver = {
+		.name   = "exynos-busfreq",
+		.owner  = THIS_MODULE,
+		.pm     = &exynos_busfreq_pm,
+	},
+};
+
+static int __init exynos_busfreq_init(void)
+{
+	return platform_driver_register(&exynos_busfreq_driver);
+}
+late_initcall(exynos_busfreq_init);
+
+static void __exit exynos_busfreq_exit(void)
+{
+	platform_driver_unregister(&exynos_busfreq_driver);
+}
+module_exit(exynos_busfreq_exit);
diff --git a/arch/arm/mach-exynos/busfreq_opp_exynos5.c b/arch/arm/mach-exynos/busfreq_opp_exynos5.c
new file mode 100644
index 0000000..b685cd2
--- /dev/null
+++ b/arch/arm/mach-exynos/busfreq_opp_exynos5.c
@@ -0,0 +1,498 @@
+/* linux/arch/arm/mach-exynos/busfreq_opp_exynos5.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * EXYNOS4 - BUS clock frequency scaling support with OPP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/types.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/regulator/consumer.h>
+#include <linux/sysfs.h>
+#include <linux/platform_device.h>
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/cpu.h>
+#include <linux/ktime.h>
+#include <linux/tick.h>
+#include <linux/kernel_stat.h>
+#include <linux/suspend.h>
+#include <linux/reboot.h>
+#include <linux/slab.h>
+#include <linux/opp.h>
+#include <linux/clk.h>
+#include <linux/workqueue.h>
+
+#include <asm/mach-types.h>
+
+#include <mach/ppmu.h>
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/gpio.h>
+#include <mach/regs-mem.h>
+#include <mach/cpufreq.h>
+#include <mach/dev.h>
+#include <mach/busfreq_exynos5.h>
+
+#include <plat/map-s5p.h>
+#include <plat/cpu.h>
+#include <plat/clock.h>
+
+#define BUSFREQ_DEBUG	1
+
+static DEFINE_MUTEX(busfreq_lock);
+BLOCKING_NOTIFIER_HEAD(exynos_busfreq_notifier_list);
+
+struct busfreq_control {
+	struct opp *lock[PPMU_TYPE_END];
+	struct device *dev[PPMU_TYPE_END];
+};
+
+static struct busfreq_control bus_ctrl;
+
+void update_busfreq_stat(struct busfreq_data *data,
+		enum ppmu_type type, unsigned int index)
+{
+#ifdef BUSFREQ_DEBUG
+	unsigned long long cur_time = get_jiffies_64();
+	data->time_in_state[type][index] =
+		cputime64_add(data->time_in_state[type][index], cputime_sub(cur_time, data->last_time[type]));
+	data->last_time[type] = cur_time;
+#endif
+}
+
+
+static unsigned long __maybe_unused step_up(struct busfreq_data *data,
+				enum ppmu_type type, int step)
+{
+	int i;
+	struct opp *opp;
+	unsigned long newfreq = data->curr_freq[type];
+
+	if (data->max_freq[type] == data->curr_freq[type])
+		return newfreq;
+
+	for (i = 0; i < step; i++) {
+		newfreq += 1;
+		opp = opp_find_freq_ceil(data->dev[type], &newfreq);
+
+		if (opp_get_freq(opp) == data->max_freq[type])
+			break;
+	}
+
+	return newfreq;
+}
+
+unsigned long step_down(struct busfreq_data *data,
+			enum ppmu_type type, int step)
+{
+	int i;
+	struct opp *opp;
+	unsigned long newfreq = data->curr_freq[type];
+
+	if (data->min_freq[type] == data->curr_freq[type])
+		return newfreq;
+
+	for (i = 0; i < step; i++) {
+		newfreq -= 1;
+		opp = opp_find_freq_floor(data->dev[type], &newfreq);
+
+		if (opp_get_freq(opp) == data->min_freq[type])
+			break;
+	}
+
+	return newfreq;
+}
+
+static void _target(struct busfreq_data *data,
+		enum ppmu_type type, unsigned long newfreq)
+{
+	struct opp *opp;
+	unsigned int voltage;
+	int index;
+
+	opp = opp_find_freq_exact(data->dev[type], newfreq, true);
+
+	if (bus_ctrl.lock[type]) {
+		opp = bus_ctrl.lock[type];
+		newfreq = opp_get_freq(opp);
+	}
+
+	index = data->get_table_index(newfreq, type);
+
+	if (newfreq == 0 || newfreq == data->curr_freq[type] ||
+			data->use == false) {
+		update_busfreq_stat(data, type, index);
+		return;
+	}
+
+	voltage = opp_get_voltage(opp);
+
+	if (newfreq > data->curr_freq[type]) {
+		regulator_set_voltage(data->vdd_reg[type], voltage,
+				voltage + 25000);
+		if (type == PPMU_MIF && data->busfreq_prepare)
+			data->busfreq_prepare(index);
+	}
+
+	data->target(data, type, index);
+
+	if (newfreq < data->curr_freq[type]) {
+		if (type == PPMU_MIF && data->busfreq_post)
+			data->busfreq_post(index);
+		regulator_set_voltage(data->vdd_reg[type], voltage,
+				voltage + 25000);
+	}
+	data->curr_freq[type] = newfreq;
+
+	update_busfreq_stat(data, type, index);
+}
+
+static void exynos_busfreq_timer(struct work_struct *work)
+{
+	struct delayed_work *delayed_work = to_delayed_work(work);
+	struct busfreq_data *data = container_of(delayed_work, struct busfreq_data,
+			worker);
+	int i;
+	struct opp *opp[PPMU_TYPE_END];
+	unsigned long newfreq;
+
+	data->monitor(data, &opp[PPMU_MIF], &opp[PPMU_INT]);
+
+	ppmu_start(data->dev[PPMU_MIF]);
+
+	mutex_lock(&busfreq_lock);
+
+	for (i = PPMU_MIF; i < PPMU_TYPE_END; i++) {
+		newfreq = opp_get_freq(opp[i]);
+		_target(data, i, newfreq);
+	}
+
+	mutex_unlock(&busfreq_lock);
+	queue_delayed_work(system_freezable_wq, &data->worker, data->sampling_rate);
+}
+
+static int exynos_buspm_notifier_event(struct notifier_block *this,
+		unsigned long event, void *ptr)
+{
+	struct busfreq_data *data = container_of(this, struct busfreq_data,
+			exynos_buspm_notifier);
+	int i;
+
+	switch (event) {
+	case PM_SUSPEND_PREPARE:
+		mutex_lock(&busfreq_lock);
+		for (i = PPMU_MIF; i < PPMU_TYPE_END; i++)
+			_target(data, i, data->max_freq[i]);
+		mutex_unlock(&busfreq_lock);
+		data->use = false;
+		return NOTIFY_OK;
+	case PM_POST_RESTORE:
+	case PM_POST_SUSPEND:
+		data->use = true;
+		return NOTIFY_OK;
+	}
+	return NOTIFY_DONE;
+}
+
+static int exynos_busfreq_reboot_event(struct notifier_block *this,
+		unsigned long code, void *unused)
+{
+	struct busfreq_data *data = container_of(this, struct busfreq_data,
+			exynos_reboot_notifier);
+	int i;
+	struct opp *opp;
+	unsigned int voltage[PPMU_TYPE_END];
+	for (i = PPMU_MIF; i < PPMU_TYPE_END; i++) {
+		opp = opp_find_freq_exact(data->dev[i], data->max_freq[i], true);
+		voltage[i] = opp_get_voltage(opp);
+
+		regulator_set_voltage(data->vdd_reg[i], voltage[i], voltage[i] + 25000);
+	}
+	data->use = false;
+
+	printk(KERN_INFO "REBOOT Notifier for BUSFREQ\n");
+	return NOTIFY_DONE;
+}
+
+static int exynos_busfreq_request_event(struct notifier_block *this,
+		unsigned long req_newfreq, void *device)
+{
+	struct busfreq_data *data = container_of(this, struct busfreq_data,
+			exynos_request_notifier);
+	int i;
+	struct opp *opp[PPMU_TYPE_END];
+	unsigned long newfreq[PPMU_TYPE_END];
+	unsigned long freq;
+
+	if (req_newfreq == 0 || data->use == false)
+		return -EINVAL;
+
+	mutex_lock(&busfreq_lock);
+
+	newfreq[PPMU_MIF] = (req_newfreq / 1000) * 1000;
+	newfreq[PPMU_INT] = (req_newfreq % 1000) * 1000;
+
+	for (i = PPMU_MIF; i < PPMU_TYPE_END; i++) {
+		opp[i] = opp_find_freq_ceil(data->dev[i], &newfreq[i]);
+		freq = opp_get_freq(opp[i]);
+		if (freq > data->curr_freq[i])
+			_target(data, i, freq);
+	}
+
+	mutex_unlock(&busfreq_lock);
+	printk(KERN_INFO "REQUEST Notifier for BUSFREQ\n");
+	return NOTIFY_DONE;
+}
+
+int exynos_busfreq_lock(unsigned int nId,
+	enum busfreq_level_request busfreq_level)
+{
+	return 0;
+}
+
+void exynos_busfreq_lock_free(unsigned int nId)
+{
+}
+
+static ssize_t show_level_lock(struct device *device,
+		struct device_attribute *attr, char *buf)
+{
+	struct platform_device *pdev = to_platform_device(bus_ctrl.dev[PPMU_MIF]);
+	struct busfreq_data *data = (struct busfreq_data *)platform_get_drvdata(pdev);
+	int len = 0;
+	unsigned long mif_freq, int_freq;
+
+	mif_freq = bus_ctrl.lock[PPMU_MIF] == NULL ? 0 : opp_get_freq(bus_ctrl.lock[PPMU_MIF]);
+	int_freq = bus_ctrl.lock[PPMU_INT] == NULL ? 0 : opp_get_freq(bus_ctrl.lock[PPMU_INT]);
+
+	len = sprintf(buf, "Current Freq(MIF/INT) : (%lu - %lu)\n",
+			data->curr_freq[PPMU_MIF], data->curr_freq[PPMU_INT]);
+	len += sprintf(buf + len, "Current Lock Freq(MIF/INT) : (%lu - %lu)\n", mif_freq, int_freq);
+
+	return len;
+}
+
+static ssize_t store_level_lock(struct device *device, struct device_attribute *attr,
+		const char *buf, size_t count)
+{
+	struct platform_device *pdev = to_platform_device(bus_ctrl.dev[PPMU_MIF]);
+	struct busfreq_data *data = (struct busfreq_data *)platform_get_drvdata(pdev);
+	struct opp *opp[PPMU_TYPE_END];
+	unsigned long freq[PPMU_TYPE_END];
+	int i;
+	int ret;
+
+	ret = sscanf(buf, "%lu %lu", &freq[PPMU_MIF], &freq[PPMU_INT]);
+	if (freq[PPMU_MIF] == 0 || freq[PPMU_INT] == 0 || ret != 2) {
+		pr_info("Release bus level lock.\n");
+		bus_ctrl.lock[PPMU_MIF] = NULL;
+		bus_ctrl.lock[PPMU_INT] = NULL;
+		return count;
+	}
+
+	for (i = PPMU_MIF; i < PPMU_TYPE_END; i++) {
+		if (freq[i] > data->max_freq[i])
+			freq[i] = data->max_freq[i];
+
+		opp[i] = opp_find_freq_ceil(bus_ctrl.dev[i], &freq[i]);
+		bus_ctrl.lock[i] = opp[i];
+	}
+	pr_info("Lock Freq : MIF/INT(%lu - %lu)\n", opp_get_freq(opp[PPMU_MIF]), opp_get_freq(opp[PPMU_INT]));
+	return count;
+}
+
+static ssize_t show_locklist(struct device *device,
+		struct device_attribute *attr, char *buf)
+{
+	return dev_lock_list(bus_ctrl.dev[PPMU_MIF], buf);
+}
+
+static ssize_t show_time_in_state(struct device *device,
+		struct device_attribute *attr, char *buf)
+{
+	struct platform_device *pdev = to_platform_device(bus_ctrl.dev[PPMU_MIF]);
+	struct busfreq_data *data = (struct busfreq_data *)platform_get_drvdata(pdev);
+	struct busfreq_table *table;
+	ssize_t len = 0;
+	int i;
+
+	table = data->table[PPMU_MIF];
+	len += sprintf(buf, "%s\n", "MIF stat");
+	for (i = LV_0; i < LV_MIF_END; i++)
+		len += sprintf(buf + len, "%u %llu\n", table[i].mem_clk,
+				(unsigned long long)cputime64_to_clock_t(data->time_in_state[PPMU_MIF][i]));
+
+	table = data->table[PPMU_INT];
+	len += sprintf(buf + len, "\n%s\n", "INT stat");
+	for (i = LV_0; i < LV_INT_END; i++)
+		len += sprintf(buf + len, "%u %llu\n", table[i].mem_clk,
+				(unsigned long long)cputime64_to_clock_t(data->time_in_state[PPMU_INT][i]));
+	return len;
+}
+
+static DEVICE_ATTR(curr_freq, 0664, show_level_lock, store_level_lock);
+static DEVICE_ATTR(lock_list, 0664, show_locklist, NULL);
+static DEVICE_ATTR(time_in_state, 0664, show_time_in_state, NULL);
+
+static struct attribute *busfreq_attributes[] = {
+	&dev_attr_curr_freq.attr,
+	&dev_attr_lock_list.attr,
+	&dev_attr_time_in_state.attr,
+	NULL
+};
+
+int exynos_request_register(struct notifier_block *n)
+{
+	return blocking_notifier_chain_register(&exynos_busfreq_notifier_list, n);
+}
+
+void exynos_request_apply(unsigned long freq)
+{
+	blocking_notifier_call_chain(&exynos_busfreq_notifier_list, freq, NULL);
+}
+
+static __devinit int exynos_busfreq_probe(struct platform_device *pdev)
+{
+	struct busfreq_data *data;
+
+	data = kzalloc(sizeof(struct busfreq_data), GFP_KERNEL);
+	if (!data) {
+		pr_err("Unable to create busfreq_data struct.\n");
+		return -ENOMEM;
+	}
+
+	data->exynos_buspm_notifier.notifier_call =
+		exynos_buspm_notifier_event;
+	data->exynos_reboot_notifier.notifier_call =
+		exynos_busfreq_reboot_event;
+	data->busfreq_attr_group.attrs = busfreq_attributes;
+	data->exynos_request_notifier.notifier_call =
+		exynos_busfreq_request_event;
+
+	INIT_DELAYED_WORK(&data->worker, exynos_busfreq_timer);
+
+	if (soc_is_exynos5250()) {
+		data->init = exynos5250_init;
+	} else {
+		pr_err("Unsupport device type.\n");
+		goto err_busfreq;
+	}
+
+	if (data->init(&pdev->dev, data)) {
+		pr_err("Failed to init busfreq.\n");
+		goto err_busfreq;
+	}
+
+	bus_ctrl.dev[PPMU_MIF] =  data->dev[PPMU_MIF];
+	bus_ctrl.dev[PPMU_INT] =  data->dev[PPMU_INT];
+
+	data->last_time[PPMU_MIF] = get_jiffies_64();
+	data->last_time[PPMU_INT] = get_jiffies_64();
+
+	data->busfreq_kobject = kobject_create_and_add("busfreq",
+				&cpu_sysdev_class.kset.kobj);
+	if (!data->busfreq_kobject)
+		pr_err("Failed to create busfreq kobject.!\n");
+
+	if (sysfs_create_group(data->busfreq_kobject, &data->busfreq_attr_group))
+		pr_err("Failed to create attributes group.!\n");
+
+	if (register_pm_notifier(&data->exynos_buspm_notifier)) {
+		pr_err("Failed to setup buspm notifier\n");
+		goto err_busfreq;
+	}
+
+	data->use = true;
+
+	if (register_reboot_notifier(&data->exynos_reboot_notifier))
+		pr_err("Failed to setup reboot notifier\n");
+
+	if (exynos_request_register(&data->exynos_request_notifier))
+		pr_err("Failed to setup request notifier\n");
+
+	platform_set_drvdata(pdev, data);
+
+	queue_delayed_work(system_freezable_wq, &data->worker, data->sampling_rate);
+	return 0;
+
+err_busfreq:
+	if (!IS_ERR(data->vdd_reg[PPMU_INT]))
+		regulator_put(data->vdd_reg[PPMU_INT]);
+
+	if (!IS_ERR(data->vdd_reg[PPMU_MIF]))
+		regulator_put(data->vdd_reg[PPMU_MIF]);
+
+	kfree(data);
+	return -ENODEV;
+}
+
+static __devexit int exynos_busfreq_remove(struct platform_device *pdev)
+{
+	struct busfreq_data *data = platform_get_drvdata(pdev);
+
+	unregister_pm_notifier(&data->exynos_buspm_notifier);
+	unregister_reboot_notifier(&data->exynos_reboot_notifier);
+	regulator_put(data->vdd_reg[PPMU_INT]);
+	regulator_put(data->vdd_reg[PPMU_MIF]);
+	sysfs_remove_group(data->busfreq_kobject, &data->busfreq_attr_group);
+	kfree(data);
+
+	return 0;
+}
+
+static int exynos_busfreq_suspend(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct busfreq_data *data = (struct busfreq_data *)platform_get_drvdata(pdev);
+
+	if (data->busfreq_suspend)
+		data->busfreq_suspend();
+	return 0;
+}
+
+static int exynos_busfreq_resume(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct busfreq_data *data = (struct busfreq_data *)platform_get_drvdata(pdev);
+	ppmu_reset(dev);
+
+	if (data->busfreq_resume)
+		data->busfreq_resume();
+	return 0;
+}
+
+static const struct dev_pm_ops exynos_busfreq_pm = {
+	.suspend = exynos_busfreq_suspend,
+	.resume = exynos_busfreq_resume,
+};
+
+static struct platform_driver exynos_busfreq_driver = {
+	.probe  = exynos_busfreq_probe,
+	.remove = __devexit_p(exynos_busfreq_remove),
+	.driver = {
+		.name   = "exynos-busfreq",
+		.owner  = THIS_MODULE,
+		.pm     = &exynos_busfreq_pm,
+	},
+};
+
+static int __init exynos_busfreq_init(void)
+{
+	return platform_driver_register(&exynos_busfreq_driver);
+}
+late_initcall(exynos_busfreq_init);
+
+static void __exit exynos_busfreq_exit(void)
+{
+	platform_driver_unregister(&exynos_busfreq_driver);
+}
+module_exit(exynos_busfreq_exit);
diff --git a/arch/arm/mach-exynos/clock-domain.c b/arch/arm/mach-exynos/clock-domain.c
new file mode 100644
index 0000000..187dfa1
--- /dev/null
+++ b/arch/arm/mach-exynos/clock-domain.c
@@ -0,0 +1,105 @@
+/* linux/arch/arm/mach-exynos/clock-domain.c
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS - Clock Domain support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/cpufreq.h>
+#include <linux/list.h>
+#include <linux/rculist.h>
+#include <linux/rcupdate.h>
+#include <linux/device.h>
+
+#include <plat/clock.h>
+
+#include <mach/clock-domain.h>
+
+static LIST_HEAD(clock_domain_list);
+/* Lock to allow exclusive modification to the clock domain list */
+static DEFINE_MUTEX(clock_domain_list_lock);
+
+static struct clock_domain *find_clock_domain(unsigned int flag)
+{
+	struct clock_domain *tmp_domain, *domain = ERR_PTR(-ENODEV);
+
+	list_for_each_entry_rcu(tmp_domain, &clock_domain_list, node) {
+		if (tmp_domain->flag & flag) {
+			domain = tmp_domain;
+			break;
+		}
+	}
+
+	return domain;
+}
+
+int clock_domain_enabled(unsigned int flag)
+{
+	struct clock_domain *domain;
+	struct clock *clock;
+
+	domain = find_clock_domain(flag);
+	if (IS_ERR(domain)) {
+		pr_err("Unable to find Clock Domain\n");
+		return -EINVAL;
+	}
+
+	list_for_each_entry_rcu(clock, &domain->domain_list, node) {
+		if (clock->clk->usage)
+			return -EINVAL;
+	}
+
+	return 0;
+}
+
+int clock_add_domain(unsigned int flag, struct clk *clk)
+{
+	struct clock_domain *domain = NULL;
+	struct clock *clock;
+
+	/* allocate new clock node */
+	clock = kzalloc(sizeof(struct clock), GFP_KERNEL);
+	if (!clock) {
+		pr_err("Unable to create new Clock node\n");
+		return -ENOMEM;
+	}
+
+	/* Hold our list modification lock here */
+	mutex_lock(&clock_domain_list_lock);
+
+	/* Check for existing list for 'dev' */
+	domain = find_clock_domain(flag);
+	if (IS_ERR(domain)) {
+		/*
+		 * Allocate a new Clock Doamin.*/
+		domain = kzalloc(sizeof(struct clock_domain), GFP_KERNEL);
+		if (!domain) {
+			mutex_unlock(&clock_domain_list_lock);
+			kfree(clock);
+			pr_err("Unable to create Clock Domain structure\n");
+			return -ENOMEM;
+		}
+
+		domain->flag = flag;
+		INIT_LIST_HEAD(&domain->domain_list);
+
+		list_add_rcu(&domain->node, &clock_domain_list);
+	}
+
+	clock->clk = clk;
+
+	list_add_rcu(&clock->node, &domain->domain_list);
+	mutex_unlock(&clock_domain_list_lock);
+
+	return 0;
+}
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
new file mode 100644
index 0000000..ad5d5b4
--- /dev/null
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -0,0 +1,2480 @@
+/* linux/arch/arm/mach-exynos/clock-exynos4.c
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS4 - Clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/syscore_ops.h>
+
+#include <plat/cpu-freq.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/pll.h>
+#include <plat/s5p-clock.h>
+#include <plat/clock-clksrc.h>
+#include <plat/devs.h>
+#include <plat/pm.h>
+
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/regs-audss.h>
+#include <mach/dev-sysmmu.h>
+#include <mach/exynos-clock.h>
+#include <mach/clock-domain.h>
+
+#ifdef CONFIG_PM
+static struct sleep_save exynos4_clock_save[] = {
+	/* CMU side */
+	SAVE_ITEM(EXYNOS4_CLKSRC_MASK_CAM),
+	SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TV),
+	SAVE_ITEM(EXYNOS4_CLKSRC_MASK_LCD0),
+	SAVE_ITEM(EXYNOS4_CLKSRC_MASK_MAUDIO),
+	SAVE_ITEM(EXYNOS4_CLKSRC_MASK_FSYS),
+	SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL0),
+	SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL1),
+	SAVE_ITEM(EXYNOS4_CLKSRC_MASK_DMC),
+	SAVE_ITEM(EXYNOS4_CLKGATE_IP_LEFTBUS),
+	SAVE_ITEM(EXYNOS4_CLKGATE_IP_RIGHTBUS),
+	SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCAM),
+	SAVE_ITEM(EXYNOS4_CLKGATE_IP_CAM),
+	SAVE_ITEM(EXYNOS4_CLKGATE_IP_TV),
+	SAVE_ITEM(EXYNOS4_CLKGATE_IP_MFC),
+	SAVE_ITEM(EXYNOS4_CLKGATE_IP_G3D),
+	SAVE_ITEM(EXYNOS4_CLKGATE_IP_LCD0),
+	SAVE_ITEM(EXYNOS4_CLKGATE_IP_FSYS),
+	SAVE_ITEM(EXYNOS4_CLKGATE_IP_GPS),
+	SAVE_ITEM(EXYNOS4_CLKGATE_IP_PERIL),
+	SAVE_ITEM(EXYNOS4_CLKGATE_BLOCK),
+	SAVE_ITEM(EXYNOS4_CLKGATE_IP_DMC),
+	SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCPU),
+	SAVE_ITEM(EXYNOS4_CLKGATE_IP_CPU),
+	SAVE_ITEM(EXYNOS4_CLKDIV_LEFTBUS),
+	SAVE_ITEM(EXYNOS4_CLKDIV_RIGHTBUS),
+	SAVE_ITEM(EXYNOS4_CLKDIV_CAM),
+	SAVE_ITEM(EXYNOS4_CLKDIV_TV),
+	SAVE_ITEM(EXYNOS4_CLKDIV_MFC),
+	SAVE_ITEM(EXYNOS4_CLKDIV_G3D),
+	SAVE_ITEM(EXYNOS4_CLKDIV_LCD0),
+	SAVE_ITEM(EXYNOS4_CLKDIV_MAUDIO),
+	SAVE_ITEM(EXYNOS4_CLKDIV_FSYS0),
+	SAVE_ITEM(EXYNOS4_CLKDIV_FSYS1),
+	SAVE_ITEM(EXYNOS4_CLKDIV_FSYS2),
+	SAVE_ITEM(EXYNOS4_CLKDIV_FSYS3),
+	SAVE_ITEM(EXYNOS4_CLKDIV_PERIL0),
+	SAVE_ITEM(EXYNOS4_CLKDIV_PERIL1),
+	SAVE_ITEM(EXYNOS4_CLKDIV_PERIL2),
+	SAVE_ITEM(EXYNOS4_CLKDIV_PERIL3),
+	SAVE_ITEM(EXYNOS4_CLKDIV_PERIL4),
+	SAVE_ITEM(EXYNOS4_CLKDIV_PERIL5),
+	SAVE_ITEM(EXYNOS4_CLKDIV_TOP),
+	SAVE_ITEM(EXYNOS4_CLKSRC_TOP0),
+	SAVE_ITEM(EXYNOS4_CLKSRC_TOP1),
+	SAVE_ITEM(EXYNOS4_CLKSRC_CAM),
+	SAVE_ITEM(EXYNOS4_CLKSRC_MFC),
+	SAVE_ITEM(EXYNOS4_CLKSRC_LCD0),
+	SAVE_ITEM(EXYNOS4_CLKSRC_MAUDIO),
+	SAVE_ITEM(EXYNOS4_CLKSRC_FSYS),
+	SAVE_ITEM(EXYNOS4_CLKSRC_PERIL0),
+	SAVE_ITEM(EXYNOS4_CLKSRC_PERIL1),
+	SAVE_ITEM(EXYNOS4_CLKSRC_DMC),
+	SAVE_ITEM(EXYNOS4_CLKSRC_CPU),
+};
+#endif
+
+struct clk exynos4_clk_sclk_hdmi27m = {
+	.name		= "sclk_hdmi27m",
+	.rate		= 27000000,
+};
+
+struct clk exynos4_clk_sclk_hdmiphy = {
+	.name		= "sclk_hdmiphy",
+};
+
+struct clk exynos4_clk_sclk_usbphy0 = {
+	.name		= "sclk_usbphy0",
+	.rate		= 27000000,
+};
+
+struct clk exynos4_clk_sclk_usbphy1 = {
+	.name		= "sclk_usbphy1",
+};
+
+static struct clk exynos4_clk_audiocdclk1 = {
+	.name           = "audiocdclk",
+};
+
+static struct clk exynos4_clk_audiocdclk2 = {
+	.name		= "audiocdclk",
+};
+
+static struct clk exynos4_clk_spdifcdclk = {
+	.name		= "spdifcdclk",
+};
+
+static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TOP, clk, enable);
+}
+
+static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_CAM, clk, enable);
+}
+
+static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_LCD0, clk, enable);
+}
+
+int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_LCD1, clk, enable);
+}
+
+int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_FSYS, clk, enable);
+}
+
+static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL0, clk, enable);
+}
+
+static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL1, clk, enable);
+}
+
+static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TV, clk, enable);
+}
+
+int exynos4_clk_ip_leftbus_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_LEFTBUS, clk, enable);
+}
+
+static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_MFC, clk, enable);
+}
+
+int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_CAM, clk, enable);
+}
+
+int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV, clk, enable);
+}
+
+static int exynos4_clk_ip_g3d_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_G3D, clk, enable);
+}
+
+int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE, clk, enable);
+}
+
+int exynos4_clk_ip_rightbus_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_RIGHTBUS, clk, enable);
+}
+
+static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_LCD0, clk, enable);
+}
+
+int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_FSYS, clk, enable);
+}
+
+int exynos4_clk_ip_gps_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_GPS, clk, enable);
+}
+
+int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIL, clk, enable);
+}
+
+int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable);
+}
+
+static int exynos4_clksrc_mask_maudio_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_MAUDIO, clk, enable);
+}
+
+static int exynos4_clk_audss_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(S5P_CLKGATE_AUDSS, clk, enable);
+}
+
+static int __maybe_unused exynos4_clk_epll_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_EPLL_CON0, clk, enable);
+}
+
+static int exynos4_clk_vpll_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_VPLL_CON0, clk, enable);
+}
+
+int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_DMC, clk, enable);
+}
+
+static int exynos4_clk_sclkapll_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_CLKGATE_SCLKCPU, clk, enable);
+}
+
+static int exynos4_clk_ip_cpu_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_CPU, clk, enable);
+}
+
+static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
+}
+
+static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
+}
+
+/* Core list of CMU_CPU side */
+
+static struct clksrc_clk exynos4_clk_mout_apll = {
+	.clk	= {
+		.name		= "mout_apll",
+	},
+	.sources = &clk_src_apll,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 0, .size = 1 },
+};
+
+struct clksrc_clk exynos4_clk_sclk_apll = {
+	.clk	= {
+		.name		= "sclk_apll",
+		.parent		= &exynos4_clk_mout_apll.clk,
+		.enable		= exynos4_clk_sclkapll_ctrl,
+		.ctrlbit	= (1 << 0),
+	},
+	.reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 24, .size = 3 },
+};
+
+struct clksrc_clk exynos4_clk_audiocdclk0 = {
+	.clk	= {
+		.name		= "audiocdclk",
+		.rate		= 16934400,
+	},
+};
+
+struct clksrc_clk exynos4_clk_mout_epll = {
+	.clk	= {
+		.name		= "mout_epll",
+		.parent = &clk_fout_epll,
+	},
+	.sources = &clk_src_epll,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 4, .size = 1 },
+};
+
+struct clksrc_clk exynos4_clk_mout_mpll = {
+	.clk = {
+		.name		= "mout_mpll",
+	},
+	.sources = &clk_src_mpll,
+	/* reg_src will be added in SoC's clock */
+};
+
+static struct clk *exynos4_clkset_moutcore_list[] = {
+	[0] = &exynos4_clk_mout_apll.clk,
+	[1] = &exynos4_clk_mout_mpll.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_moutcore = {
+	.sources	= exynos4_clkset_moutcore_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_moutcore_list),
+};
+
+static struct clksrc_clk exynos4_clk_moutcore = {
+	.clk	= {
+		.name		= "moutcore",
+	},
+	.sources = &exynos4_clkset_moutcore,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 16, .size = 1 },
+};
+
+static struct clksrc_clk exynos4_clk_coreclk = {
+	.clk	= {
+		.name		= "core_clk",
+		.parent		= &exynos4_clk_moutcore.clk,
+	},
+	.reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_armclk = {
+	.clk	= {
+		.name		= "armclk",
+		.parent		= &exynos4_clk_coreclk.clk,
+	},
+};
+
+static struct clksrc_clk exynos4_clk_aclk_corem0 = {
+	.clk	= {
+		.name		= "aclk_corem0",
+		.parent		= &exynos4_clk_coreclk.clk,
+	},
+	.reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_aclk_cores = {
+	.clk	= {
+		.name		= "aclk_cores",
+		.parent		= &exynos4_clk_coreclk.clk,
+	},
+	.reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_aclk_corem1 = {
+	.clk	= {
+		.name		= "aclk_corem1",
+		.parent		= &exynos4_clk_coreclk.clk,
+	},
+	.reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 8, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_periphclk = {
+	.clk	= {
+		.name		= "periphclk",
+		.parent		= &exynos4_clk_coreclk.clk,
+	},
+	.reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 12, .size = 3 },
+};
+
+/* Core list of CMU_CORE side */
+
+struct clk *exynos4_clkset_corebus_list[] = {
+	[0] = &exynos4_clk_mout_mpll.clk,
+	[1] = &exynos4_clk_sclk_apll.clk,
+};
+
+struct clksrc_sources exynos4_clkset_mout_corebus = {
+	.sources	= exynos4_clkset_corebus_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_corebus_list),
+};
+
+static struct clksrc_clk exynos4_clk_mout_corebus = {
+	.clk	= {
+		.name		= "mout_corebus",
+	},
+	.sources = &exynos4_clkset_mout_corebus,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 4, .size = 1 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_dmc = {
+	.clk	= {
+		.name		= "sclk_dmc",
+		.parent		= &exynos4_clk_mout_corebus.clk,
+	},
+	.reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 12, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_aclk_cored = {
+	.clk	= {
+		.name		= "aclk_cored",
+		.parent		= &exynos4_clk_sclk_dmc.clk,
+	},
+	.reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 16, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_aclk_corep = {
+	.clk	= {
+		.name		= "aclk_corep",
+		.parent		= &exynos4_clk_aclk_cored.clk,
+	},
+	.reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 20, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_aclk_acp = {
+	.clk	= {
+		.name		= "aclk_acp",
+		.parent		= &exynos4_clk_mout_corebus.clk,
+	},
+	.reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_pclk_acp = {
+	.clk	= {
+		.name		= "pclk_acp",
+		.parent		= &exynos4_clk_aclk_acp.clk,
+	},
+	.reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 4, .size = 3 },
+};
+
+static struct clk *exynos4_clkset_c2c_list[] = {
+	[0] = &exynos4_clk_mout_mpll.clk,
+	[1] = &exynos4_clk_sclk_apll.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_mout_c2c = {
+	.sources	= exynos4_clkset_c2c_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_c2c_list),
+};
+
+static struct clksrc_clk exynos4_clk_sclk_c2c = {
+	.clk	= {
+		.name		= "sclk_c2c",
+		.id		= -1,
+	},
+	.sources = &exynos4_clkset_mout_c2c,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 0, .size = 1 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_DMC1, .shift = 4, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_aclk_c2c = {
+	.clk	= {
+		.name	= "aclk_c2c",
+		.id	= -1,
+		.parent	= &exynos4_clk_sclk_c2c.clk,
+	},
+	.reg_div = { .reg = EXYNOS4_CLKDIV_DMC1, .shift = 12, .size = 3 },
+};
+
+/* Core list of CMU_TOP side */
+
+struct clk *exynos4_clkset_aclk_top_list[] = {
+	[0] = &exynos4_clk_mout_mpll.clk,
+	[1] = &exynos4_clk_sclk_apll.clk,
+};
+
+struct clksrc_sources exynos4_clkset_aclk = {
+	.sources	= exynos4_clkset_aclk_top_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_aclk_top_list),
+};
+
+struct clksrc_clk exynos4_clk_aclk_200 = {
+	.clk	= {
+		.name		= "aclk_200",
+	},
+};
+
+static struct clksrc_clk exynos4_clk_aclk_100 = {
+	.clk	= {
+		.name		= "aclk_100",
+	},
+	.sources = &exynos4_clkset_aclk,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 16, .size = 1 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 4, .size = 4 },
+};
+
+struct clksrc_clk exynos4_clk_aclk_160 = {
+	.clk	= {
+		.name		= "aclk_160",
+	},
+	.sources = &exynos4_clkset_aclk,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 20, .size = 1 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 8, .size = 3 },
+};
+
+struct clksrc_clk exynos4_clk_aclk_133 = {
+	.clk	= {
+		.name		= "aclk_133",
+	},
+	.sources = &exynos4_clkset_aclk,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 24, .size = 1 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 12, .size = 3 },
+};
+
+/* CMU_LEFT/RIGHTBUS side */
+static struct clk *exynos4_clkset_aclk_lrbus_list[] = {
+	[0] = &exynos4_clk_mout_mpll.clk,
+	[1] = &exynos4_clk_sclk_apll.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_aclk_lrbus = {
+	.sources	= exynos4_clkset_aclk_lrbus_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_aclk_lrbus_list),
+};
+
+static struct clksrc_clk exynos4_clk_aclk_gdl = {
+	.clk	= {
+		.name		= "aclk_gdl",
+	},
+	.sources = &exynos4_clkset_aclk_lrbus,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_LEFTBUS, .shift = 0, .size = 1 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_LEFTBUS, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_aclk_gdr = {
+	.clk	= {
+		.name		= "aclk_gdr",
+	},
+	.sources = &exynos4_clkset_aclk_lrbus,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_RIGHTBUS, .shift = 0, .size = 1 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_RIGHTBUS, .shift = 0, .size = 3 },
+};
+
+static struct clk *exynos4_clkset_vpllsrc_list[] = {
+	[0] = &clk_fin_vpll,
+	[1] = &exynos4_clk_sclk_hdmi27m,
+};
+
+static struct clksrc_sources exynos4_clkset_vpllsrc = {
+	.sources	= exynos4_clkset_vpllsrc_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_vpllsrc_list),
+};
+
+static struct clksrc_clk exynos4_clk_vpllsrc = {
+	.clk	= {
+		.name		= "vpll_src",
+		.enable		= exynos4_clksrc_mask_top_ctrl,
+		.ctrlbit	= (1 << 0),
+	},
+	.sources = &exynos4_clkset_vpllsrc,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_TOP1, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos4_clkset_sclk_vpll_list[] = {
+	[0] = &exynos4_clk_vpllsrc.clk,
+	[1] = &clk_fout_vpll,
+};
+
+static struct clksrc_sources exynos4_clkset_sclk_vpll = {
+	.sources	= exynos4_clkset_sclk_vpll_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_sclk_vpll_list),
+};
+
+struct clksrc_clk exynos4_clk_sclk_vpll = {
+	.clk	= {
+		.name		= "sclk_vpll",
+	},
+	.sources = &exynos4_clkset_sclk_vpll,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 8, .size = 1 },
+};
+
+static struct clk *exynos4_clkset_sclk_dac_list[] = {
+	[0] = &exynos4_clk_sclk_vpll.clk,
+	[1] = &exynos4_clk_sclk_hdmiphy,
+};
+
+static struct clksrc_sources exynos4_clkset_sclk_dac = {
+	.sources	= exynos4_clkset_sclk_dac_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_sclk_dac_list),
+};
+
+static struct clksrc_clk exynos4_clk_sclk_dac = {
+	.clk	= {
+		.name		= "sclk_dac",
+		.enable		= exynos4_clksrc_mask_tv_ctrl,
+		.ctrlbit	= (1 << 8),
+	},
+	.sources = &exynos4_clkset_sclk_dac,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 8, .size = 1 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_pixel = {
+	.clk	= {
+		.name		= "sclk_pixel",
+		.parent		= &exynos4_clk_sclk_vpll.clk,
+	},
+	.reg_div	= { .reg = EXYNOS4_CLKDIV_TV, .shift = 0, .size = 4 },
+};
+
+static struct clk *exynos4_clkset_sclk_hdmi_list[] = {
+	[0] = &exynos4_clk_sclk_pixel.clk,
+	[1] = &exynos4_clk_sclk_hdmiphy,
+};
+
+static struct clksrc_sources exynos4_clkset_sclk_hdmi = {
+	.sources	= exynos4_clkset_sclk_hdmi_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_sclk_hdmi_list),
+};
+
+static struct clksrc_clk exynos4_clk_sclk_hdmi = {
+	.clk	= {
+		.name		= "sclk_hdmi",
+		.enable		= exynos4_clksrc_mask_tv_ctrl,
+		.ctrlbit	= (1 << 0),
+	},
+	.sources = &exynos4_clkset_sclk_hdmi,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos4_clkset_sclk_mixer_list[] = {
+	[0] = &exynos4_clk_sclk_dac.clk,
+	[1] = &exynos4_clk_sclk_hdmi.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_sclk_mixer = {
+	.sources	= exynos4_clkset_sclk_mixer_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_sclk_mixer_list),
+};
+
+static struct clksrc_clk exynos4_clk_sclk_mixer = {
+	.clk    = {
+		.name           = "sclk_mixer",
+		.id             = -1,
+		.enable         = exynos4_clksrc_mask_tv_ctrl,
+		.ctrlbit        = (1 << 4),
+	},
+	.sources = &exynos4_clkset_sclk_mixer,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 4, .size = 1 },
+};
+
+static struct clksrc_clk *exynos4_sclk_tv[] = {
+	&exynos4_clk_sclk_dac,
+	&exynos4_clk_sclk_pixel,
+	&exynos4_clk_sclk_hdmi,
+	&exynos4_clk_sclk_mixer,
+};
+
+static struct clk exynos4_init_clocks_off[] = {
+	{
+		.name		= "ppmuright",
+		.enable		= exynos4_clk_ip_rightbus_ctrl,
+		.ctrlbit	= (1 << 1),
+	}, {
+		.name		= "ppmuleft",
+		.enable		= exynos4_clk_ip_leftbus_ctrl,
+		.ctrlbit	= (1 << 1),
+	}, {
+		.name		= "timers",
+		.parent		= &exynos4_clk_aclk_100.clk,
+		.enable		= exynos4_clk_ip_peril_ctrl,
+		.ctrlbit	= (1<<24),
+	}, {
+		.name		= "csis",
+		.devname	= "s3c-csis.0",
+		.enable		= exynos4_clk_ip_cam_ctrl,
+		.ctrlbit	= (1 << 4),
+	}, {
+		.name		= "csis",
+		.devname	= "s3c-csis.1",
+		.enable		= exynos4_clk_ip_cam_ctrl,
+		.ctrlbit	= (1 << 5),
+	}, {
+		.name		= "fimc",
+		.devname	= "s3c-fimc.0",
+		.enable		= exynos4_clk_ip_cam_ctrl,
+		.ctrlbit	= (1 << 0),
+	}, {
+		.name		= "fimc",
+		.devname	= "s3c-fimc.1",
+		.enable		= exynos4_clk_ip_cam_ctrl,
+		.ctrlbit	= (1 << 1),
+	}, {
+		.name		= "fimc",
+		.devname	= "s3c-fimc.2",
+		.enable		= exynos4_clk_ip_cam_ctrl,
+		.ctrlbit	= (1 << 2),
+	}, {
+		.name		= "fimc",
+		.devname	= "s3c-fimc.3",
+		.enable		= exynos4_clk_ip_cam_ctrl,
+		.ctrlbit	= (1 << 3),
+	}, {
+		.name		= "jpeg",
+		.enable		= exynos4_clk_ip_cam_ctrl,
+		.ctrlbit	= ((1 << 11) | (1 << 6)),
+	}, {
+		.name		= "pxl_async0",
+		.enable		= exynos4_clk_ip_cam_ctrl,
+		.ctrlbit	= (1 << 17),
+	}, {
+		.name		= "pxl_async1",
+		.enable		= exynos4_clk_ip_cam_ctrl,
+		.ctrlbit	= (1 << 18),
+	}, {
+		.name		= "ppmucamif",
+		.enable		= exynos4_clk_ip_cam_ctrl,
+		.ctrlbit	= (1 << 16),
+	}, {
+		.name		= "jpeg",
+		.enable		= exynos4_clk_ip_cam_ctrl,
+		.ctrlbit	= (1 << 6),
+	}, {
+		.name		= "rotator",
+		.devname	= "exynos-rot",
+		.enable		= exynos4_clk_ip_image_ctrl,
+		.ctrlbit	= (1 << 1),
+	}, {
+		.name		= "hsmmc",
+		.devname	= "s3c-sdhci.0",
+		.enable		= exynos4_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 5),
+	}, {
+		.name		= "hsmmc",
+		.devname	= "s3c-sdhci.1",
+		.enable		= exynos4_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 6),
+	}, {
+		.name		= "hsmmc",
+		.devname	= "s3c-sdhci.2",
+		.enable		= exynos4_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 7),
+	}, {
+		.name		= "hsmmc",
+		.devname	= "s3c-sdhci.3",
+		.enable		= exynos4_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 8),
+	}, {
+		.name		= "dwmci",
+		.enable		= exynos4_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 9),
+	}, {
+		.name		= "adc",
+		.enable		= exynos4_clk_ip_peril_ctrl,
+		.ctrlbit	= (1 << 15),
+	}, {
+		.name		= "keypad",
+		.enable		= exynos4_clk_ip_perir_ctrl,
+		.ctrlbit	= (1 << 16),
+	}, {
+		.name		= "rtc",
+		.enable		= exynos4_clk_ip_perir_ctrl,
+		.ctrlbit	= (1 << 15),
+	}, {
+		.name		= "watchdog",
+		.enable		= exynos4_clk_ip_perir_ctrl,
+		.ctrlbit	= (1 << 14),
+	}, {
+		.name		= "hdmicec",
+		.enable		= exynos4_clk_ip_perir_ctrl,
+		.ctrlbit	= (1 << 11),
+	}, {
+		.name		= "sromc",
+		.enable		= exynos4_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 11),
+	}, {
+		.name		= "usbhost",
+		.enable		= exynos4_clk_ip_fsys_ctrl ,
+		.ctrlbit	= (1 << 12),
+	}, {
+		.name		= "usbotg",
+		.enable		= exynos4_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 13),
+	}, {
+		.name		= "spi",
+		.devname	= "s3c64xx-spi.0",
+		.enable		= exynos4_clk_ip_peril_ctrl,
+		.ctrlbit	= (1 << 16),
+	}, {
+		.name		= "spi",
+		.devname	= "s3c64xx-spi.1",
+		.enable		= exynos4_clk_ip_peril_ctrl,
+		.ctrlbit	= (1 << 17),
+	}, {
+		.name		= "spi",
+		.devname	= "s3c64xx-spi.2",
+		.enable		= exynos4_clk_ip_peril_ctrl,
+		.ctrlbit	= (1 << 18),
+	}, {
+		.name		= "iis",
+		.devname	= "samsung-i2s.1",
+		.enable		= exynos4_clk_ip_peril_ctrl,
+		.ctrlbit	= (1 << 20),
+	}, {
+		.name		= "iis",
+		.devname	= "samsung-i2s.2",
+		.enable		= exynos4_clk_ip_peril_ctrl,
+		.ctrlbit	= (1 << 21),
+	}, {
+		.name		= "pcm",
+		.devname	= "samsung-pcm.1",
+		.enable		= exynos4_clk_ip_peril_ctrl,
+		.ctrlbit	= (1 << 22),
+	}, {
+		.name		= "pcm",
+		.devname	= "samsung-pcm.2",
+		.enable		= exynos4_clk_ip_peril_ctrl,
+		.ctrlbit	= (1 << 23),
+	}, {
+		.name		= "slimbus",
+		.enable		= exynos4_clk_ip_peril_ctrl,
+		.ctrlbit	= (1 << 25),
+	}, {
+		.name		= "spdif",
+		.devname	= "samsung-spdif",
+		.enable		= exynos4_clk_ip_peril_ctrl,
+		.ctrlbit	= (1 << 26),
+	}, {
+		.name		= "ac97",
+		.devname	= "samsung-ac97",
+		.enable		= exynos4_clk_ip_peril_ctrl,
+		.ctrlbit	= (1 << 27),
+	}, {
+		.name		= "i2c-hdmiphy",
+		.enable		= exynos4_clk_ip_peril_ctrl,
+		.ctrlbit	= (1 << 14),
+	}, {
+		.name		= "ppmutv",
+		.enable		= exynos4_clk_ip_tv_ctrl,
+		.ctrlbit	= (1 << 5),
+	}, {
+		.name		= "hdmi",
+		.enable		= exynos4_clk_ip_tv_ctrl,
+		.ctrlbit	= (1 << 3),
+	}, {
+		.name		= "dac",
+		.devname        = "s5p-sdo",
+		.enable		= exynos4_clk_ip_tv_ctrl,
+		.ctrlbit	= (1 << 2),
+	}, {
+		.name		= "mixer",
+		.enable		= exynos4_clk_ip_tv_ctrl,
+		.ctrlbit	= (1 << 1),
+	}, {
+		.name		= "vp",
+		.enable		= exynos4_clk_ip_tv_ctrl,
+		.ctrlbit	= (1 << 0),
+	}, {
+		.name		= "ppmuimage",
+		.enable		= exynos4_clk_ip_image_ctrl,
+		.ctrlbit	= (1 << 9),
+	}, {
+		.name		= "qerotator",
+		.enable		= exynos4_clk_ip_image_ctrl,
+		.ctrlbit	= (1 << 7),
+	}, {
+		.name		= "rotator",
+		.enable		= exynos4_clk_ip_image_ctrl,
+		.ctrlbit	= (1 << 1),
+	}, {
+		.name           = "hdmiphy",
+		.devname        = "exynos4-hdmi",
+		.enable         = exynos4_clk_hdmiphy_ctrl,
+		.ctrlbit        = (1 << 0),
+	}, {
+		.name           = "dacphy",
+		.devname        = "s5p-sdo",
+		.enable         = exynos4_clk_dac_ctrl,
+		.ctrlbit        = (1 << 0),
+	}, {
+		.name		= "sysmmu",
+		.devname	= SYSMMU_CLOCK_NAME(sss, 0),
+		.enable		= exynos4_clk_ip_dmc_ctrl,
+		.ctrlbit	= (1 << 12),
+	}, {
+		.name		= "sysmmu",
+		.devname	= SYSMMU_CLOCK_NAME(fimc0, 1),
+		.enable		= exynos4_clk_ip_cam_ctrl,
+		.ctrlbit	= (1 << 7),
+	}, {
+		.name		= "sysmmu",
+		.devname	= SYSMMU_CLOCK_NAME(fimc1, 2),
+		.enable		= exynos4_clk_ip_cam_ctrl,
+		.ctrlbit	= (1 << 8),
+	}, {
+		.name		= "sysmmu",
+		.devname	= SYSMMU_CLOCK_NAME(fimc2, 3),
+		.enable		= exynos4_clk_ip_cam_ctrl,
+		.ctrlbit	= (1 << 9),
+	}, {
+		.name		= "sysmmu",
+		.devname	= SYSMMU_CLOCK_NAME(fimc3, 4),
+		.enable		= exynos4_clk_ip_cam_ctrl,
+		.ctrlbit	= (1 << 10),
+	}, {
+		.name		= "sysmmu",
+		.devname	= SYSMMU_CLOCK_NAME(jpeg, 5),
+		.enable		= exynos4_clk_ip_cam_ctrl,
+		.ctrlbit	= (1 << 11),
+	}, {
+		.name		= "sysmmu",
+		.devname	= SYSMMU_CLOCK_NAME(fimd0, 6),
+		.enable		= exynos4_clk_ip_lcd0_ctrl,
+		.ctrlbit	= (1 << 4),
+	}, {
+		.name		= "sysmmu",
+		.devname	= SYSMMU_CLOCK_NAME(rot, 10),
+		.enable		= exynos4_clk_ip_image_ctrl,
+		.ctrlbit	= (1 << 4),
+	}, {
+		.name		= "sysmmu",
+
+		.devname	= SYSMMU_CLOCK_NAME(mdma, 11),
+		.enable		= exynos4_clk_ip_image_ctrl,
+		.ctrlbit	= (1 << 5),
+	}, {
+		.name		= "sysmmu",
+		.devname	= SYSMMU_CLOCK_NAME(tv, 12),
+		.enable		= exynos4_clk_ip_tv_ctrl,
+		.ctrlbit	= (1 << 4),
+	}, {
+		.name		= "sysmmu",
+		.devname	= SYSMMU_CLOCK_NAME(mfc_l, 13),
+		.enable		= exynos4_clk_ip_mfc_ctrl,
+		.ctrlbit	= (1 << 1),
+	}, {
+		.name		= "sysmmu",
+		.devname	= SYSMMU_CLOCK_NAME(mfc_r, 14),
+		.enable		= exynos4_clk_ip_mfc_ctrl,
+		.ctrlbit	= (1 << 2),
+	}, {
+		.name		= "sysmmu",
+		.devname	= SYSMMU_CLOCK_NAME(gps, 16),
+		.enable		= exynos4_clk_ip_gps_ctrl,
+		.ctrlbit	= (1 << 1),
+	}, {
+		.name		= "gps",
+		.enable		= exynos4_clk_ip_gps_ctrl,
+		.ctrlbit	= (1 << 0),
+	}, {
+		.name		= "ppmumfc",
+		.enable		= exynos4_clk_ip_mfc_ctrl,
+		.ctrlbit	= ((0x1 << 4) | (0x1 << 3)),
+	}, {
+		.name		= "mfc",
+		.devname	= "s3c-mfc",
+		.enable		= exynos4_clk_ip_mfc_ctrl,
+		.ctrlbit	= (0x1 << 0),
+	}, {
+		.name		= "tsi",
+		.enable		= exynos4_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 4),
+	}, {
+		.name		= "onenand",
+		.enable		= exynos4_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 15),
+	}, {
+		.name		= "nfcon",
+		.enable		= exynos4_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 16),
+	}, {
+		.name		= "ppmufsys",
+		.enable		= exynos4_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 17),
+	}, {
+		.name		= "ppmug3d",
+		.enable		= exynos4_clk_ip_g3d_ctrl,
+		.ctrlbit	= (1 << 1),
+	}, {
+		.name		= "ppmucam",
+		.enable		= exynos4_clk_ip_cam_ctrl,
+		.ctrlbit	= (1 << 16),
+	}, {
+		.name		= "hpm",
+		.enable		= exynos4_clk_ip_cpu_ctrl,
+		.ctrlbit	= (1 << 0),
+	}, {
+		.name		= "iec",
+		.enable		= exynos4_clk_ip_dmc_ctrl,
+		.ctrlbit	= (1 << 18),
+	}, {
+		.name		= "apc",
+		.enable		= exynos4_clk_ip_dmc_ctrl,
+		.ctrlbit	= (1 << 17),
+	}, {
+		.name		= "ppmuacp",
+		.enable		= exynos4_clk_ip_dmc_ctrl,
+		.ctrlbit	= (1 << 16),
+	}, {
+		.name		= "ppmucpu",
+		.enable		= exynos4_clk_ip_dmc_ctrl,
+		.ctrlbit	= (1 << 10),
+	}, {
+		.name		= "ppmudmc1",
+		.enable		= exynos4_clk_ip_dmc_ctrl,
+		.ctrlbit	= (1 << 9),
+	}, {
+		.name		= "ppmudmc0",
+		.enable		= exynos4_clk_ip_dmc_ctrl,
+		.ctrlbit	= (1 << 8),
+#ifdef CONFIG_CPU_EXYNOS4210
+	}, {
+		.name		= "qesss",
+		.enable		= exynos4_clk_ip_dmc_ctrl,
+		.ctrlbit	= (1 << 15),
+	}, {
+		.name		= "id_remapper",
+		.enable		= exynos4_clk_ip_dmc_ctrl,
+		.ctrlbit	= (1 << 13),
+	}, {
+		.name		= "qecpu",
+		.enable		= exynos4_clk_ip_dmc_ctrl,
+		.ctrlbit	= (1 << 7),
+	}, {
+		.name		= "fbm_dmc1",
+		.enable		= exynos4_clk_ip_dmc_ctrl,
+		.ctrlbit	= (1 << 6),
+	}, {
+		.name		= "seckey",
+		.enable		= exynos4_clk_ip_perir_ctrl,
+		.ctrlbit	= (1 << 12),
+	}, {
+		.name		= "tzpc",
+		.devname	= "exnos4-tzpc.5",
+		.enable		= exynos4_clk_ip_perir_ctrl,
+		.ctrlbit	= (1 << 10),
+	}, {
+		.name		= "tzpc",
+		.devname	= "exnos4-tzpc.4",
+		.enable		= exynos4_clk_ip_perir_ctrl,
+		.ctrlbit	= (1 << 9),
+	}, {
+		.name		= "tzpc",
+		.devname	= "exnos4-tzpc.3",
+		.enable		= exynos4_clk_ip_perir_ctrl,
+		.ctrlbit	= (1 << 8),
+	}, {
+		.name		= "tzpc",
+		.devname	= "exnos4-tzpc.2",
+		.enable		= exynos4_clk_ip_perir_ctrl,
+		.ctrlbit	= (1 << 7),
+	}, {
+		.name		= "tzpc",
+		.devname	= "exnos4-tzpc.1",
+		.enable		= exynos4_clk_ip_perir_ctrl,
+		.ctrlbit	= (1 << 6),
+	}, {
+		.name		= "tzpc",
+		.devname	= "exnos4-tzpc.0",
+		.enable		= exynos4_clk_ip_perir_ctrl,
+		.ctrlbit	= (1 << 5),
+#endif
+	}, {
+		.name		= "qefimc",
+		.devname	= "s5p-qe.3",
+		.enable		= exynos4_clk_ip_cam_ctrl,
+		.ctrlbit	= (1 << 15),
+	}, {
+		.name		= "qefimc",
+		.devname	= "s5p-qe.2",
+		.enable		= exynos4_clk_ip_cam_ctrl,
+		.ctrlbit	= (1 << 14),
+	}, {
+		.name		= "qefimc",
+		.devname	= "s5p-qe.1",
+		.enable		= exynos4_clk_ip_cam_ctrl,
+		.ctrlbit	= (1 << 13),
+	}, {
+		.name		= "qefimc",
+		.devname	= "s5p-qe.0",
+		.enable		= exynos4_clk_ip_cam_ctrl,
+		.ctrlbit	= (1 << 12),
+	}, {
+		.name		= "qeg3d",
+		.enable		= exynos4_clk_ip_g3d_ctrl,
+		.ctrlbit	= (1 << 2),
+	}, {
+		.name		= "secss",
+		.parent		= &exynos4_clk_aclk_acp.clk,
+		.enable		= exynos4_clk_ip_dmc_ctrl,
+		.ctrlbit	= (1 << 4),
+	},
+};
+
+static struct clk exynos4_i2cs_clocks[] = {
+	{
+		.name		= "i2c",
+		.devname	= "s3c2440-i2c.0",
+		.parent		= &exynos4_clk_aclk_100.clk,
+		.enable		= exynos4_clk_ip_peril_ctrl,
+		.ctrlbit	= (1 << 6),
+	}, {
+		.name		= "i2c",
+		.devname	= "s3c2440-i2c.1",
+		.parent		= &exynos4_clk_aclk_100.clk,
+		.enable		= exynos4_clk_ip_peril_ctrl,
+		.ctrlbit	= (1 << 7),
+	}, {
+		.name		= "i2c",
+		.devname	= "s3c2440-i2c.2",
+		.parent		= &exynos4_clk_aclk_100.clk,
+		.enable		= exynos4_clk_ip_peril_ctrl,
+		.ctrlbit	= (1 << 8),
+	}, {
+		.name		= "i2c",
+		.devname	= "s3c2440-i2c.3",
+		.parent		= &exynos4_clk_aclk_100.clk,
+		.enable		= exynos4_clk_ip_peril_ctrl,
+		.ctrlbit	= (1 << 9),
+	}, {
+		.name		= "i2c",
+		.devname	= "s3c2440-i2c.4",
+		.parent		= &exynos4_clk_aclk_100.clk,
+		.enable		= exynos4_clk_ip_peril_ctrl,
+		.ctrlbit	= (1 << 10),
+	}, {
+		.name		= "i2c",
+		.devname	= "s3c2440-i2c.5",
+		.parent		= &exynos4_clk_aclk_100.clk,
+		.enable		= exynos4_clk_ip_peril_ctrl,
+		.ctrlbit	= (1 << 11),
+	}, {
+		.name		= "i2c",
+		.devname	= "s3c2440-i2c.6",
+		.parent		= &exynos4_clk_aclk_100.clk,
+		.enable		= exynos4_clk_ip_peril_ctrl,
+		.ctrlbit	= (1 << 12),
+	}, {
+		.name		= "i2c",
+		.devname	= "s3c2440-i2c.7",
+		.parent		= &exynos4_clk_aclk_100.clk,
+		.enable		= exynos4_clk_ip_peril_ctrl,
+		.ctrlbit	= (1 << 13),
+	}, {
+		.name		= "i2c",
+		.devname	= "s3c2440-hdmiphy-i2c",
+		.parent		= &exynos4_clk_aclk_100.clk,
+		.enable		= exynos4_clk_ip_peril_ctrl,
+		.ctrlbit	= (1 << 14),
+	}
+};
+
+static struct clk *clkset_sclk_audio0_list[] = {
+	[0] = &exynos4_clk_audiocdclk0.clk,
+	[1] = NULL,
+	[2] = &exynos4_clk_sclk_hdmi27m,
+	[3] = &exynos4_clk_sclk_usbphy0,
+	[4] = &clk_ext_xtal_mux,
+	[5] = &clk_xusbxti,
+	[6] = &exynos4_clk_mout_mpll.clk,
+	[7] = &exynos4_clk_mout_epll.clk,
+	[8] = &exynos4_clk_sclk_vpll.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_sclk_audio0 = {
+	.sources	= clkset_sclk_audio0_list,
+	.nr_sources	= ARRAY_SIZE(clkset_sclk_audio0_list),
+};
+
+static struct clksrc_clk exynos4_clk_sclk_audio0 = {
+	.clk	= {
+		.name		= "audio-bus",
+		.enable		= exynos4_clksrc_mask_maudio_ctrl,
+		.ctrlbit	= (1 << 0),
+	},
+	.sources = &exynos4_clkset_sclk_audio0,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_MAUDIO, .shift = 0, .size = 4 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_MAUDIO, .shift = 0, .size = 4 },
+};
+
+static struct clk *exynos4_clkset_mout_audss_list[] = {
+	&clk_ext_xtal_mux,
+	&clk_fout_epll,
+};
+
+static struct clksrc_sources clkset_mout_audss = {
+	.sources	= exynos4_clkset_mout_audss_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_mout_audss_list),
+};
+
+static struct clksrc_clk exynos4_clk_mout_audss = {
+	.clk	= {
+		.name		= "mout_audss",
+	},
+	.sources = &clkset_mout_audss,
+	.reg_src = { .reg = S5P_CLKSRC_AUDSS, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos4_clkset_sclk_audss_list[] = {
+	&exynos4_clk_mout_audss.clk,
+	&exynos4_clk_audiocdclk0.clk,
+	&exynos4_clk_sclk_audio0.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_sclk_audss = {
+	.sources	= exynos4_clkset_sclk_audss_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_sclk_audss_list),
+};
+
+static struct clksrc_clk exynos4_clk_sclk_audss_i2s = {
+	.clk		= {
+		.name		= "i2sclk",
+		.parent		= &exynos4_clk_mout_audss.clk,
+		.enable		= exynos4_clk_audss_ctrl,
+		.ctrlbit	= S5P_AUDSS_CLKGATE_I2SSPECIAL,
+	},
+	.sources = &exynos4_clkset_sclk_audss,
+	.reg_src = { .reg = S5P_CLKSRC_AUDSS, .shift = 2, .size = 2 },
+	.reg_div = { .reg = S5P_CLKDIV_AUDSS, .shift = 8, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_dout_audss_srp = {
+	.clk	= {
+		.name		= "dout_srp",
+		.parent		= &exynos4_clk_mout_audss.clk,
+	},
+	.reg_div = { .reg = S5P_CLKDIV_AUDSS, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_audss_bus = {
+	.clk	= {
+		.name		= "busclk",
+		.parent		= &exynos4_clk_dout_audss_srp.clk,
+		.enable		= exynos4_clk_audss_ctrl,
+		.ctrlbit	= S5P_AUDSS_CLKGATE_I2SBUS,
+	},
+	.reg_div = { .reg = S5P_CLKDIV_AUDSS, .shift = 4, .size = 4 },
+};
+
+static struct clk exynos4_init_audss_clocks[] = {
+	{
+		.name		= "srpclk",
+		.enable		= exynos4_clk_audss_ctrl,
+		.parent		= &exynos4_clk_dout_audss_srp.clk,
+		.ctrlbit	= S5P_AUDSS_CLKGATE_RP | S5P_AUDSS_CLKGATE_UART
+				| S5P_AUDSS_CLKGATE_TIMER,
+	}, {
+		.name		= "iis",
+		.devname	= "samsung-i2s.0",
+		.enable		= exynos4_clk_audss_ctrl,
+		.ctrlbit	= S5P_AUDSS_CLKGATE_I2SSPECIAL | S5P_AUDSS_CLKGATE_I2SBUS,
+	}, {
+		.name		= "pcm",
+		.devname	= "samsung-pcm.0",
+		.enable		= exynos4_clk_audss_ctrl,
+		.ctrlbit	= S5P_AUDSS_CLKGATE_PCMSPECIAL | S5P_AUDSS_CLKGATE_PCMBUS,
+	},
+};
+
+static struct clk *exynos4_clkset_sclk_audio1_list[] = {
+	[0] = &exynos4_clk_audiocdclk1,
+	[1] = NULL,
+	[2] = &exynos4_clk_sclk_hdmi27m,
+	[3] = &exynos4_clk_sclk_usbphy0,
+	[4] = &clk_ext_xtal_mux,
+	[5] = &clk_xusbxti,
+	[6] = &exynos4_clk_mout_mpll.clk,
+	[7] = &exynos4_clk_mout_epll.clk,
+	[8] = &exynos4_clk_sclk_vpll.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_sclk_audio1 = {
+	.sources	= exynos4_clkset_sclk_audio1_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_sclk_audio1_list),
+};
+
+static struct clksrc_clk exynos4_clk_sclk_audio1 = {
+	.clk	= {
+		.name		= "audio-bus1",
+		.enable		= exynos4_clksrc_mask_peril1_ctrl,
+		.ctrlbit	= (1 << 0),
+	},
+	.sources = &exynos4_clkset_sclk_audio1,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 0, .size = 4 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL4, .shift = 0, .size = 8 },
+};
+
+static struct clk *exynos4_clkset_sclk_audio2_list[] = {
+	[0] = &exynos4_clk_audiocdclk2,
+	[1] = NULL,
+	[2] = &exynos4_clk_sclk_hdmi27m,
+	[3] = &exynos4_clk_sclk_usbphy0,
+	[4] = &clk_ext_xtal_mux,
+	[5] = &clk_xusbxti,
+	[6] = &exynos4_clk_mout_mpll.clk,
+	[7] = &exynos4_clk_mout_epll.clk,
+	[8] = &exynos4_clk_sclk_vpll.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_sclk_audio2 = {
+	.sources	= exynos4_clkset_sclk_audio2_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_sclk_audio2_list),
+};
+
+static struct clksrc_clk exynos4_clk_sclk_audio2 = {
+	.clk	= {
+		.name		= "audio-bus2",
+		.enable		= exynos4_clksrc_mask_peril1_ctrl,
+		.ctrlbit	= (1 << 4),
+	},
+	.sources = &exynos4_clkset_sclk_audio2,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 4, .size = 4 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL4, .shift = 16, .size = 4 },
+};
+
+static struct clk *exynos4_clkset_sclk_spdif_list[] = {
+	[0] = &exynos4_clk_sclk_audio0.clk,
+	[1] = &exynos4_clk_sclk_audio1.clk,
+	[2] = &exynos4_clk_sclk_audio2.clk,
+	[3] = &exynos4_clk_spdifcdclk,
+};
+
+static struct clksrc_sources exynos4_clkset_sclk_spdif = {
+	.sources	= exynos4_clkset_sclk_spdif_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_sclk_spdif_list),
+};
+
+static struct clksrc_clk exynos4_clk_sclk_spdif = {
+	.clk	= {
+		.name		= "sclk_spdif",
+		.enable		= exynos4_clksrc_mask_peril1_ctrl,
+		.ctrlbit	= (1 << 8),
+		.ops		= &s5p_sclk_spdif_ops,
+	},
+	.sources = &exynos4_clkset_sclk_spdif,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 8, .size = 2 },
+};
+
+struct clk exynos4_init_dmaclocks[] = {
+	{
+		.name		= "pdma",
+		.devname	= "s3c-pl330.0",
+		.enable		= exynos4_clk_ip_image_ctrl,
+		.ctrlbit	= ((1 << 8) | (1 << 5) | (1 << 2)),
+	}, {
+		.name		= "pdma",
+		.devname	= "s3c-pl330.1",
+		.enable		= exynos4_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 0),
+	}, {
+		.name		= "pdma",
+		.devname	= "s3c-pl330.2",
+		.enable		= exynos4_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 1),
+	},
+};
+
+static struct clk exynos4_init_clocks[] = {
+	{
+#ifndef CONFIG_CPU_EXYNOS4210
+		.name		= "seckey",
+		.enable		= exynos4_clk_ip_perir_ctrl,
+		.ctrlbit	= (1 << 12),
+	}, {
+		.name		= "tzpc",
+		.devname	= "exnos4-tzpc.5",
+		.enable		= exynos4_clk_ip_perir_ctrl,
+		.ctrlbit	= (1 << 10),
+	}, {
+		.name		= "tzpc",
+		.devname	= "exnos4-tzpc.4",
+		.enable		= exynos4_clk_ip_perir_ctrl,
+		.ctrlbit	= (1 << 9),
+	}, {
+		.name		= "tzpc",
+		.devname	= "exnos4-tzpc.3",
+		.enable		= exynos4_clk_ip_perir_ctrl,
+		.ctrlbit	= (1 << 8),
+	}, {
+		.name		= "tzpc",
+		.devname	= "exnos4-tzpc.2",
+		.enable		= exynos4_clk_ip_perir_ctrl,
+		.ctrlbit	= (1 << 7),
+	}, {
+		.name		= "tzpc",
+		.devname	= "exnos4-tzpc.1",
+		.enable		= exynos4_clk_ip_perir_ctrl,
+		.ctrlbit	= (1 << 6),
+	}, {
+		.name		= "tzpc",
+		.devname	= "exnos4-tzpc.0",
+		.enable		= exynos4_clk_ip_perir_ctrl,
+		.ctrlbit	= (1 << 5),
+	}, {
+#endif
+		.name		= "cssys",
+		.enable		= exynos4_clk_ip_cpu_ctrl,
+		.ctrlbit	= (1 << 1),
+	}, {
+		.name		= "gic",
+		.enable		= exynos4_clk_ip_dmc_ctrl,
+		.ctrlbit	= (1 << 20),
+#ifndef CONFIG_CPU_EXYNOS4210
+	}, {
+		.name		= "qesss",
+		.enable		= exynos4_clk_ip_dmc_ctrl,
+		.ctrlbit	= (1 << 15),
+	}, {
+		.name		= "id_remapper",
+		.enable		= exynos4_clk_ip_dmc_ctrl,
+		.ctrlbit	= (1 << 13),
+	}, {
+		.name		= "qecpu",
+		.enable		= exynos4_clk_ip_dmc_ctrl,
+		.ctrlbit	= (1 << 7),
+	}, {
+		.name		= "fbm_dmc1",
+		.enable		= exynos4_clk_ip_dmc_ctrl,
+		.ctrlbit	= (1 << 6),
+#endif
+	}, {
+		.name		= "fbm_dmc0",
+		.enable		= exynos4_clk_ip_dmc_ctrl,
+		.ctrlbit	= (1 << 5),
+	}, {
+		.name		= "int_comb",
+		.enable		= exynos4_clk_ip_dmc_ctrl,
+		.ctrlbit	= (1 << 2),
+	}, {
+		.name		= "g3d",
+		.enable		= exynos4_clk_ip_g3d_ctrl,
+		.ctrlbit	= (1 << 0),
+	}, {
+		.name		= "tmu",
+		.enable		= exynos4_clk_ip_perir_ctrl,
+		.ctrlbit	= (1 << 17),
+	}, {
+		.name		= "mct",
+		.enable		= exynos4_clk_ip_perir_ctrl,
+		.ctrlbit	= (1 << 13),
+	}, {
+		.name		= "cmu_top",
+		.enable		= exynos4_clk_ip_perir_ctrl,
+		.ctrlbit	= (1 << 3),
+	}, {
+		.name		= "pmu_apb",
+		.enable		= exynos4_clk_ip_perir_ctrl,
+		.ctrlbit	= (1 << 2),
+	}, {
+		.name		= "sysreg",
+		.enable		= exynos4_clk_ip_perir_ctrl ,
+		.ctrlbit	= (1 << 1),
+	}, {
+		.name		= "chipid",
+		.enable		= exynos4_clk_ip_perir_ctrl,
+		.ctrlbit	= (1 << 0),
+	}, {
+		.name		= "uart",
+		.devname	= "s5pv210-uart.0",
+		.enable		= exynos4_clk_ip_peril_ctrl,
+		.ctrlbit	= (1 << 0),
+	}, {
+		.name		= "uart",
+		.devname	= "s5pv210-uart.1",
+		.enable		= exynos4_clk_ip_peril_ctrl,
+		.ctrlbit	= (1 << 1),
+	}, {
+		.name		= "uart",
+		.devname	= "s5pv210-uart.2",
+		.enable		= exynos4_clk_ip_peril_ctrl,
+		.ctrlbit	= (1 << 2),
+	}, {
+		.name		= "uart",
+		.devname	= "s5pv210-uart.3",
+		.enable		= exynos4_clk_ip_peril_ctrl,
+		.ctrlbit	= (1 << 3),
+	}, {
+		.name		= "uart",
+		.devname	= "s5pv210-uart.4",
+		.enable		= exynos4_clk_ip_peril_ctrl,
+		.ctrlbit	= (1 << 4),
+	}, {
+#if 1
+		.name		= "lcd",
+		.devname	= "s3cfb.0",
+		.enable 	= exynos4_clk_ip_lcd0_ctrl,
+		.ctrlbit	= (1 << 0),
+	}, {
+		.name		= "mie0",
+		.enable 	= exynos4_clk_ip_lcd0_ctrl,
+		.ctrlbit	= (1 << 1),
+	}, {
+		.name		= "mdnie0",
+		.enable 	= exynos4_clk_ip_lcd0_ctrl,
+		.ctrlbit	= (1 << 2),
+	}, {
+		.name		= "dsim0",
+		.enable 	= exynos4_clk_ip_lcd0_ctrl,
+		.ctrlbit	= (1 << 3),
+	}, {
+		.name		= "ppmulcd",
+		.enable 	= exynos4_clk_ip_lcd0_ctrl,
+		.ctrlbit	= (1 << 5),
+	},
+#endif
+};
+
+struct clk *exynos4_clkset_group_list[] = {
+	[0] = &clk_ext_xtal_mux,
+	[1] = &clk_xusbxti,
+	[2] = &exynos4_clk_sclk_hdmi27m,
+	[3] = &exynos4_clk_sclk_usbphy0,
+	[4] = &exynos4_clk_sclk_usbphy1,
+	[5] = &exynos4_clk_sclk_hdmiphy,
+	[6] = &exynos4_clk_mout_mpll.clk,
+	[7] = &exynos4_clk_mout_epll.clk,
+	[8] = &exynos4_clk_sclk_vpll.clk,
+};
+
+struct clksrc_sources exynos4_clkset_group = {
+	.sources	= exynos4_clkset_group_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_group_list),
+};
+
+static struct clksrc_clk clk_sclk_mipidphy4l = {
+	.clk    = {
+		.name           = "sclk_mipidphy4l",
+		.id             = -1,
+		.enable         = exynos4_clksrc_mask_lcd0_ctrl,
+		.ctrlbit        = (1 << 12),
+	},
+	.sources        = &exynos4_clkset_group,
+	.reg_src        = { .reg = EXYNOS4_CLKSRC_LCD0, .shift = 12, .size = 4 },
+	.reg_div	= { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_mipidphy2l = {
+	.clk    = {
+		.name           = "sclk_mipidphy2l",
+		.id             = -1,
+		.enable         = exynos4_clksrc_mask_lcd0_ctrl,
+		.ctrlbit        = (1 << 12),
+	},
+	.sources        = &exynos4_clkset_group,
+	.reg_src        = { .reg = EXYNOS4_CLKSRC_LCD1, .shift = 12, .size = 4 },
+	.reg_div	= { .reg = EXYNOS4_CLKDIV_LCD1, .shift = 16, .size = 4 },
+};
+
+static struct clk *exynos4_clkset_mout_g2d0_list[] = {
+	[0] = &exynos4_clk_mout_mpll.clk,
+	[1] = &exynos4_clk_sclk_apll.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_mout_g2d0 = {
+	.sources	= exynos4_clkset_mout_g2d0_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_mout_g2d0_list),
+};
+
+struct clksrc_clk exynos4_clk_mout_g2d0 = {
+	.clk	= {
+		.name		= "mout_g2d0",
+	},
+	.sources = &exynos4_clkset_mout_g2d0,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos4_clkset_mout_g2d1_list[] = {
+	[0] = &exynos4_clk_mout_epll.clk,
+	[1] = &exynos4_clk_sclk_vpll.clk,
+};
+
+struct clksrc_sources exynos4_clkset_mout_g2d1 = {
+	.sources	= exynos4_clkset_mout_g2d1_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_mout_g2d1_list),
+};
+
+struct clksrc_clk exynos4_clk_mout_g2d1 = {
+	.clk	= {
+		.name		= "mout_g2d1",
+	},
+	.sources = &exynos4_clkset_mout_g2d1,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 },
+};
+
+static struct clk *exynos4_clkset_mout_g2d_list[] = {
+	[0] = &exynos4_clk_mout_g2d0.clk,
+	[1] = &exynos4_clk_mout_g2d1.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_mout_g2d = {
+	.sources	= exynos4_clkset_mout_g2d_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_mout_g2d_list),
+};
+
+struct clksrc_clk exynos4_clk_sclk_fimg2d = {
+	.clk    = {
+		.name           = "sclk_fimg2d",
+		.devname	= "s5p-fimg2d",
+	},
+	.sources = &exynos4_clkset_mout_g2d,
+};
+
+struct clk exynos4_clk_fimg2d = {
+	.name           = "fimg2d",
+	.devname	= "s5p-fimg2d",
+};
+
+struct clk *exynos4_clkset_mout_mfc0_list[] = {
+	[0] = &exynos4_clk_mout_mpll.clk,
+	[1] = &exynos4_clk_sclk_apll.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_mout_mfc0 = {
+	.sources	= exynos4_clkset_mout_mfc0_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_mout_mfc0_list),
+};
+
+static struct clksrc_clk exynos4_clk_mout_mfc0 = {
+	.clk	= {
+		.name		= "mout_mfc0",
+	},
+	.sources = &exynos4_clkset_mout_mfc0,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos4_clkset_mout_mfc1_list[] = {
+	[0] = &exynos4_clk_mout_epll.clk,
+	[1] = &exynos4_clk_sclk_vpll.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_mout_mfc1 = {
+	.sources	= exynos4_clkset_mout_mfc1_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_mout_mfc1_list),
+};
+
+static struct clksrc_clk exynos4_clk_mout_mfc1 = {
+	.clk	= {
+		.name		= "mout_mfc1",
+	},
+	.sources = &exynos4_clkset_mout_mfc1,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 4, .size = 1 },
+};
+
+static struct clk *exynos4_clkset_mout_mfc_list[] = {
+	[0] = &exynos4_clk_mout_mfc0.clk,
+	[1] = &exynos4_clk_mout_mfc1.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_mout_mfc = {
+	.sources	= exynos4_clkset_mout_mfc_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_mout_mfc_list),
+};
+
+static struct clk *exynos4_clkset_mout_g3d0_list[] = {
+	[0] = &exynos4_clk_mout_mpll.clk,
+	[1] = &exynos4_clk_sclk_apll.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_mout_g3d0 = {
+	.sources	= exynos4_clkset_mout_g3d0_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_mout_g3d0_list),
+};
+
+static struct clksrc_clk exynos4_clk_mout_g3d0 = {
+	.clk	= {
+		.name		= "mout_g3d0",
+	},
+	.sources = &exynos4_clkset_mout_g3d0,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_G3D, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos4_clkset_mout_g3d1_list[] = {
+	[0] = &exynos4_clk_mout_epll.clk,
+	[1] = &exynos4_clk_sclk_vpll.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_mout_g3d1 = {
+	.sources	= exynos4_clkset_mout_g3d1_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_mout_g3d1_list),
+};
+
+static struct clksrc_clk exynos4_clk_mout_g3d1 = {
+	.clk	= {
+		.name		= "mout_g3d1",
+	},
+	.sources = &exynos4_clkset_mout_g3d1,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_G3D, .shift = 4, .size = 1 },
+};
+
+static struct clk *exynos4_clkset_mout_g3d_list[] = {
+	[0] = &exynos4_clk_mout_g3d0.clk,
+	[1] = &exynos4_clk_mout_g3d1.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_mout_g3d = {
+	.sources	= exynos4_clkset_mout_g3d_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_mout_g3d_list),
+};
+
+static struct clksrc_clk exynos4_clk_dout_mmc0 = {
+	.clk		= {
+		.name		= "dout_mmc0",
+	},
+	.sources = &exynos4_clkset_group,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 0, .size = 4 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_dout_mmc1 = {
+	.clk		= {
+		.name		= "dout_mmc1",
+	},
+	.sources = &exynos4_clkset_group,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 4, .size = 4 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_dout_mmc2 = {
+	.clk		= {
+		.name		= "dout_mmc2",
+	},
+	.sources = &exynos4_clkset_group,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 8, .size = 4 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_dout_mmc3 = {
+	.clk		= {
+		.name		= "dout_mmc3",
+	},
+	.sources = &exynos4_clkset_group,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 12, .size = 4 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_dout_mmc4 = {
+	.clk		= {
+		.name		= "dout_mmc4",
+	},
+	.sources = &exynos4_clkset_group,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 16, .size = 4 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 0, .size = 4 },
+};
+
+static struct clk *exynos4_clkset_mout_hpm_list[] = {
+	[0] = &exynos4_clk_mout_apll.clk,
+	[1] = &exynos4_clk_mout_mpll.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_sclk_hpm = {
+	.sources	= exynos4_clkset_mout_hpm_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_mout_hpm_list),
+};
+
+static struct clksrc_clk exynos4_clk_dout_copy = {
+	.clk	= {
+		.name		= "dout_copy",
+	},
+	.sources = &exynos4_clkset_sclk_hpm,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 20, .size = 1 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_CPU1, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_dout_spi0 = {
+	.clk		= {
+		.name		= "dout_spi0",
+	},
+	.sources = &exynos4_clkset_group,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_dout_spi1 = {
+	.clk		= {
+		.name		= "dout_spi1",
+	},
+	.sources = &exynos4_clkset_group,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_dout_spi2 = {
+	.clk		= {
+		.name		= "dout_spi2",
+	},
+	.sources = &exynos4_clkset_group,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clksrcs[] = {
+	{
+		.clk	= {
+			.name		= "uclk1",
+			.devname	= "s5pv210-uart.0",
+			.enable		= exynos4_clksrc_mask_peril0_ctrl,
+			.ctrlbit	= (1 << 0),
+		},
+		.sources = &exynos4_clkset_group,
+		.reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 0, .size = 4 },
+		.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 0, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "uclk1",
+			.devname	= "s5pv210-uart.1",
+			.enable		= exynos4_clksrc_mask_peril0_ctrl,
+			.ctrlbit	= (1 << 4),
+		},
+		.sources = &exynos4_clkset_group,
+		.reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 4, .size = 4 },
+		.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 4, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "uclk1",
+			.devname	= "s5pv210-uart.2",
+			.enable		= exynos4_clksrc_mask_peril0_ctrl,
+			.ctrlbit	= (1 << 8),
+		},
+		.sources = &exynos4_clkset_group,
+		.reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 8, .size = 4 },
+		.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 8, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "uclk1",
+			.devname	= "s5pv210-uart.3",
+			.enable		= exynos4_clksrc_mask_peril0_ctrl,
+			.ctrlbit	= (1 << 12),
+		},
+		.sources = &exynos4_clkset_group,
+		.reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 12, .size = 4 },
+		.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 12, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "sclk_csis",
+			.devname	= "s3c-csis.0",
+			.enable		= exynos4_clksrc_mask_cam_ctrl,
+			.ctrlbit	= (1 << 24),
+		},
+		.sources = &exynos4_clkset_group,
+		.reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 24, .size = 4 },
+		.reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 24, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "sclk_csis",
+			.devname	= "s3c-csis.1",
+			.enable		= exynos4_clksrc_mask_cam_ctrl,
+			.ctrlbit	= (1 << 28),
+		},
+		.sources = &exynos4_clkset_group,
+		.reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 28, .size = 4 },
+		.reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 28, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "sclk_cam0",
+			.enable		= exynos4_clksrc_mask_cam_ctrl,
+			.ctrlbit	= (1 << 16),
+		},
+		.sources = &exynos4_clkset_group,
+		.reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 16, .size = 4 },
+		.reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 16, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "sclk_cam1",
+			.enable		= exynos4_clksrc_mask_cam_ctrl,
+			.ctrlbit	= (1 << 20),
+		},
+		.sources = &exynos4_clkset_group,
+		.reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 20, .size = 4 },
+		.reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 20, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "sclk_fimc",
+			.devname	= "s3c-fimc.0",
+			.enable		= exynos4_clksrc_mask_cam_ctrl,
+			.ctrlbit	= (1 << 0),
+		},
+		.sources = &exynos4_clkset_group,
+		.reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 0, .size = 4 },
+		.reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 0, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "sclk_fimc",
+			.devname	= "s3c-fimc.1",
+			.enable		= exynos4_clksrc_mask_cam_ctrl,
+			.ctrlbit	= (1 << 4),
+		},
+		.sources = &exynos4_clkset_group,
+		.reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 4, .size = 4 },
+		.reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 4, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "sclk_fimc",
+			.devname	= "s3c-fimc.2",
+			.enable		= exynos4_clksrc_mask_cam_ctrl,
+			.ctrlbit	= (1 << 8),
+		},
+		.sources = &exynos4_clkset_group,
+		.reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 8, .size = 4 },
+		.reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 8, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "sclk_fimc",
+			.devname	= "s3c-fimc.3",
+			.enable		= exynos4_clksrc_mask_cam_ctrl,
+			.ctrlbit	= (1 << 12),
+		},
+		.sources = &exynos4_clkset_group,
+		.reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 12, .size = 4 },
+		.reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 12, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "sclk_fimd",
+			.devname	= "s3cfb.0",
+			.enable		= exynos4_clksrc_mask_lcd0_ctrl,
+			.ctrlbit	= (1 << 0),
+		},
+		.sources = &exynos4_clkset_group,
+		.reg_src = { .reg = EXYNOS4_CLKSRC_LCD0, .shift = 0, .size = 4 },
+		.reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 0, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "sclk_fimd",
+			.devname	= "s3cfb.1",
+			.enable		= exynos4_clksrc_mask_lcd1_ctrl,
+			.ctrlbit	= (1 << 0),
+		},
+		.sources = &exynos4_clkset_group,
+		.reg_src = { .reg = EXYNOS4_CLKSRC_LCD1, .shift = 0, .size = 4 },
+		.reg_div = { .reg = EXYNOS4_CLKDIV_LCD1, .shift = 0, .size = 4 },
+#if defined(CONFIG_FB_S5P_MDNIE) || defined(CONFIG_MDNIE_SUPPORT)
+	}, {
+		.clk		= {
+			.name		= "sclk_mdnie",
+			.id		= -1,
+			.enable		= exynos4_clksrc_mask_lcd0_ctrl,
+			.ctrlbit	= (1 << 4),
+		},
+		.sources = &exynos4_clkset_group,
+		.reg_src = { .reg = EXYNOS4_CLKSRC_LCD0, .shift = 4, .size = 4 },
+		.reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 4, .size = 4 },
+	}, {
+		.clk		= {
+			.name		= "sclk_mdnie",
+			.id		= 1,
+			.enable		= exynos4_clksrc_mask_lcd1_ctrl,
+			.ctrlbit	= (1 << 4),
+		},
+		.sources = &exynos4_clkset_group,
+		.reg_src = { .reg = EXYNOS4_CLKSRC_LCD1, .shift = 4, .size = 4 },
+		.reg_div = { .reg = EXYNOS4_CLKDIV_LCD1, .shift = 4, .size = 4 },
+	}, {
+		.clk		= {
+			.name		= "sclk_mdnie_pwm",
+			.id		= -1,
+			.enable		= exynos4_clksrc_mask_lcd0_ctrl,
+			.ctrlbit	= (1 << 8),
+		},
+		.sources = &exynos4_clkset_group,
+		.reg_src = { .reg = EXYNOS4_CLKSRC_LCD0, .shift = 8, .size = 4 },
+		.reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 8, .size = 4 },
+	}, {
+		.clk		= {
+			.name		= "sclk_mdnie_pwm",
+			.id		= 1,
+			.enable		= exynos4_clksrc_mask_lcd1_ctrl,
+			.ctrlbit	= (1 << 8),
+		},
+		.sources = &exynos4_clkset_group,
+		.reg_src = { .reg = EXYNOS4_CLKSRC_LCD1, .shift = 8, .size = 4 },
+		.reg_div = { .reg = EXYNOS4_CLKDIV_LCD1, .shift = 8, .size = 4 },
+#endif
+#ifdef CONFIG_FB_MDNIE_PWM
+	}, {
+		.clk		= {
+			.name		= "sclk_mdnie_pwm_pre",
+			.id		= -1,
+			.enable		= exynos4_clksrc_mask_lcd0_ctrl,
+			.ctrlbit	= (1 << 12),
+		},
+		.sources = &exynos4_clkset_group,
+		.reg_src = { .reg = EXYNOS4_CLKSRC_LCD0, .shift = 8, .size = 4 },
+		.reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 12, .size = 4 },
+	}, {
+		.clk		= {
+			.name		= "sclk_mdnie_pwm_pre",
+			.id		= 1,
+			.enable		= exynos4_clksrc_mask_lcd1_ctrl,
+			.ctrlbit	= (1 << 12),
+		},
+		.sources = &exynos4_clkset_group,
+		.reg_src = { .reg = EXYNOS4_CLKSRC_LCD1, .shift = 8, .size = 4 },
+		.reg_div = { .reg = EXYNOS4_CLKDIV_LCD1, .shift = 12, .size = 4 },
+#endif
+	}, {
+		.clk		= {
+			.name		= "sclk_mipi",
+#ifdef CONFIG_FB_S5P_MIPI_DSIM
+			.id		= -1,
+#else
+			.id		= 0,
+#endif
+			.parent		= &clk_sclk_mipidphy4l.clk,
+			.enable		= exynos4_clksrc_mask_lcd0_ctrl,
+			.ctrlbit	= (1 << 12),
+		},
+		.reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 20, .size = 4 },
+	}, {
+		.clk		= {
+			.name		= "sclk_mipi",
+			.id		= 1,
+			.parent		= &clk_sclk_mipidphy2l.clk,
+			.enable		= exynos4_clksrc_mask_lcd1_ctrl,
+			.ctrlbit	= (1 << 12),
+		},
+		.reg_div = { .reg = EXYNOS4_CLKDIV_LCD1, .shift = 20, .size = 4 },
+	}, {
+		.clk		= {
+			.name		= "sclk_mmc",
+			.id		= 0,
+			.parent		= &exynos4_clk_dout_mmc0.clk,
+			.enable		= exynos4_clksrc_mask_fsys_ctrl,
+			.ctrlbit	= (1 << 0),
+		},
+		.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 8, .size = 8 },
+	}, {
+		.clk		= {
+			.name		= "sclk_mmc",
+			.id		= 1,
+			.parent         = &exynos4_clk_dout_mmc1.clk,
+			.enable		= exynos4_clksrc_mask_fsys_ctrl,
+			.ctrlbit	= (1 << 4),
+		},
+		.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 24, .size = 8 },
+	}, {
+		.clk		= {
+			.name		= "sclk_mmc",
+			.id		= 2,
+			.parent         = &exynos4_clk_dout_mmc2.clk,
+			.enable		= exynos4_clksrc_mask_fsys_ctrl,
+			.ctrlbit	= (1 << 8),
+		},
+		.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 8, .size = 8 },
+	}, {
+		.clk		= {
+			.name		= "sclk_mmc",
+			.id		= 3,
+			.parent         = &exynos4_clk_dout_mmc3.clk,
+			.enable		= exynos4_clksrc_mask_fsys_ctrl,
+			.ctrlbit	= (1 << 12),
+		},
+		.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
+	}, {
+		.clk		= {
+			.name		= "sclk_dwmci",
+			.id		= -1,
+			.parent         = &exynos4_clk_dout_mmc4.clk,
+			.enable		= exynos4_clksrc_mask_fsys_ctrl,
+			.ctrlbit	= (1 << 16),
+		},
+		.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 8, .size = 8 },
+	}, {
+		.clk	= {
+			.name		= "sclk_spi",
+			.devname	= "s3c64xx-spi.0",
+			.parent		= &exynos4_clk_dout_spi0.clk,
+			.enable		= exynos4_clksrc_mask_peril1_ctrl,
+			.ctrlbit	= (1 << 16),
+		},
+		.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 8, .size = 8 },
+	}, {
+		.clk	= {
+			.name		= "sclk_spi",
+			.devname	= "s3c64xx-spi.1",
+			.parent		= &exynos4_clk_dout_spi1.clk,
+			.enable		= exynos4_clksrc_mask_peril1_ctrl,
+			.ctrlbit	= (1 << 20),
+		},
+		.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 24, .size = 8 },
+	}, {
+		.clk	= {
+			.name		= "sclk_spi",
+			.devname	= "s3c64xx-spi.2",
+			.parent		= &exynos4_clk_dout_spi2.clk,
+			.enable		= exynos4_clksrc_mask_peril1_ctrl,
+			.ctrlbit	= (1 << 24),
+		},
+		.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 8, .size = 8 },
+	}, {
+		.clk	= {
+			.name		= "sclk_mfc",
+		},
+		.sources = &exynos4_clkset_mout_mfc,
+		.reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 8, .size = 1 },
+		.reg_div = { .reg = EXYNOS4_CLKDIV_MFC, .shift = 0, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "sclk_g3d",
+			.enable		= exynos4_clk_ip_g3d_ctrl,
+			.ctrlbit	= (1 << 0),
+		},
+		.sources = &exynos4_clkset_mout_g3d,
+		.reg_src = { .reg = EXYNOS4_CLKSRC_G3D, .shift = 8, .size = 1 },
+		.reg_div = { .reg = EXYNOS4_CLKDIV_G3D, .shift = 0, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "sclk_mmc",
+			.devname	= "s3c-sdhci.0",
+			.parent		= &exynos4_clk_dout_mmc0.clk,
+			.enable		= exynos4_clksrc_mask_fsys_ctrl,
+			.ctrlbit	= (1 << 0),
+		},
+		.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 8, .size = 8 },
+	}, {
+		.clk	= {
+			.name		= "sclk_mmc",
+			.devname	= "s3c-sdhci.1",
+			.parent         = &exynos4_clk_dout_mmc1.clk,
+			.enable		= exynos4_clksrc_mask_fsys_ctrl,
+			.ctrlbit	= (1 << 4),
+		},
+		.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 24, .size = 8 },
+	}, {
+		.clk	= {
+			.name		= "sclk_mmc",
+			.devname	= "s3c-sdhci.2",
+			.parent         = &exynos4_clk_dout_mmc2.clk,
+			.enable		= exynos4_clksrc_mask_fsys_ctrl,
+			.ctrlbit	= (1 << 8),
+		},
+		.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 8, .size = 8 },
+	}, {
+		.clk	= {
+			.name		= "sclk_mmc",
+			.devname	= "s3c-sdhci.3",
+			.parent         = &exynos4_clk_dout_mmc3.clk,
+			.enable		= exynos4_clksrc_mask_fsys_ctrl,
+			.ctrlbit	= (1 << 12),
+		},
+		.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
+	}, {
+		.clk	= {
+			.name		= "sclk_dwmci",
+			.parent         = &exynos4_clk_dout_mmc4.clk,
+			.enable		= exynos4_clksrc_mask_fsys_ctrl,
+			.ctrlbit	= (1 << 16),
+		},
+		.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 8, .size = 8 },
+	}, {
+		.clk	= {
+			.name		= "sclk_pcm",
+			.parent		= &exynos4_clk_sclk_audio0.clk,
+		},
+			.reg_div = { .reg = EXYNOS4_CLKDIV_MAUDIO, .shift = 4, .size = 8 },
+	}, {
+		.clk	= {
+			.name		= "sclk_pcm",
+			.parent		= &exynos4_clk_sclk_audio1.clk,
+		},
+			.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL4, .shift = 4, .size = 8 },
+	}, {
+		.clk	= {
+			.name		= "sclk_pcm",
+			.parent		= &exynos4_clk_sclk_audio2.clk,
+		},
+			.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL4, .shift = 20, .size = 8 },
+	}, {
+		.clk	= {
+			.name		= "sclk_i2s",
+			.parent		= &exynos4_clk_sclk_audio1.clk,
+		},
+			.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL5, .shift = 0, .size = 6 },
+	}, {
+		.clk	= {
+			.name		= "sclk_i2s",
+			.parent		= &exynos4_clk_sclk_audio2.clk,
+		},
+			.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL5, .shift = 8, .size = 6 },
+	}, {
+		.clk	= {
+			.name		= "sclk_hpm",
+			.parent		= &exynos4_clk_dout_copy.clk,
+		},
+		.reg_div = { .reg = EXYNOS4_CLKDIV_CPU1, .shift = 4, .size = 3 },
+	}, {
+		.clk	= {
+			.name		= "sclk_pwi",
+		},
+		.sources = &exynos4_clkset_group,
+		.reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 16, .size = 4 },
+		.reg_div = { .reg = EXYNOS4_CLKDIV_DMC1, .shift = 8, .size = 4 },
+	},
+};
+
+/* Clock initialization code */
+static struct clksrc_clk *exynos4_sysclks[] = {
+	&exynos4_clk_audiocdclk0,
+	&exynos4_clk_mout_apll,
+	&exynos4_clk_sclk_apll,
+	&exynos4_clk_mout_epll,
+	&exynos4_clk_mout_mpll,
+	&exynos4_clk_moutcore,
+	&exynos4_clk_coreclk,
+	&exynos4_clk_armclk,
+	&exynos4_clk_aclk_corem0,
+	&exynos4_clk_aclk_cores,
+	&exynos4_clk_aclk_corem1,
+	&exynos4_clk_periphclk,
+	&exynos4_clk_mout_corebus,
+	&exynos4_clk_sclk_dmc,
+	&exynos4_clk_aclk_cored,
+	&exynos4_clk_aclk_corep,
+	&exynos4_clk_aclk_acp,
+	&exynos4_clk_pclk_acp,
+	&exynos4_clk_vpllsrc,
+	&exynos4_clk_sclk_vpll,
+	&exynos4_clk_aclk_200,
+	&exynos4_clk_aclk_100,
+	&exynos4_clk_aclk_160,
+	&exynos4_clk_aclk_133,
+	&exynos4_clk_aclk_gdl,
+	&exynos4_clk_aclk_gdr,
+	&exynos4_clk_mout_mfc0,
+	&exynos4_clk_mout_mfc1,
+	&exynos4_clk_dout_mmc0,
+	&exynos4_clk_dout_mmc1,
+	&exynos4_clk_dout_mmc2,
+	&exynos4_clk_dout_mmc3,
+	&exynos4_clk_dout_mmc4,
+	&exynos4_clk_mout_audss,
+	&exynos4_clk_sclk_audss_bus,
+	&exynos4_clk_sclk_audss_i2s,
+	&exynos4_clk_dout_audss_srp,
+	&exynos4_clk_sclk_audio0,
+	&exynos4_clk_sclk_audio1,
+	&exynos4_clk_sclk_audio2,
+	&exynos4_clk_sclk_spdif,
+	&exynos4_clk_mout_g2d0,
+	&exynos4_clk_mout_g2d1,
+	&exynos4_clk_dout_copy,
+	&exynos4_clk_mout_g3d0,
+	&exynos4_clk_mout_g3d1,
+	&exynos4_clk_dout_spi0,
+	&exynos4_clk_dout_spi1,
+	&exynos4_clk_dout_spi2,
+#ifdef CONFIG_CPU_EXYNOS4212
+	&exynos4_clk_sclk_c2c,
+	&exynos4_clk_aclk_c2c,
+#endif
+	&exynos4_clk_sclk_fimg2d,
+};
+
+struct clk_ops exynos4_epll_ops;
+struct clk_ops exynos4_vpll_ops;
+
+static int xtal_rate;
+
+static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
+{
+	if (soc_is_exynos4210())
+		return s5p_get_pll45xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0), pll_4508);
+	else
+		return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0));
+}
+
+static struct clk_ops exynos4_fout_apll_ops = {
+	.get_rate = exynos4_fout_apll_get_rate,
+};
+
+void __init_or_cpufreq exynos4_setup_clocks(void)
+{
+	struct clk *xtal_clk;
+	unsigned long apll;
+	unsigned long mpll;
+	unsigned long epll;
+	unsigned long vpll;
+	unsigned long vpllsrc;
+	unsigned long xtal;
+	unsigned long armclk;
+	unsigned long sclk_dmc;
+	unsigned long aclk_200;
+	unsigned long aclk_160;
+	unsigned long aclk_133;
+	unsigned long aclk_100;
+	unsigned int ptr;
+
+	printk(KERN_DEBUG "%s: registering clocks\n", __func__);
+
+	xtal_clk = clk_get(NULL, "xtal");
+	BUG_ON(IS_ERR(xtal_clk));
+
+	xtal = clk_get_rate(xtal_clk);
+
+	xtal_rate = xtal;
+
+	clk_put(xtal_clk);
+
+	printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
+
+	if (soc_is_exynos4210()) {
+		apll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_APLL_CON0), pll_4508);
+		mpll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0), pll_4508);
+		epll = s5p_get_pll46xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
+				__raw_readl(EXYNOS4_EPLL_CON1), pll_4600);
+
+		vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
+		vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
+				__raw_readl(EXYNOS4_VPLL_CON1), pll_4650c);
+	} else {
+		apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_APLL_CON0));
+		mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0));
+		epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
+				__raw_readl(EXYNOS4_EPLL_CON1));
+
+		vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
+		vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
+				__raw_readl(EXYNOS4_VPLL_CON1));
+	}
+
+	clk_fout_apll.ops = &exynos4_fout_apll_ops;
+	clk_fout_mpll.rate = mpll;
+	clk_fout_epll.rate = epll;
+	clk_fout_vpll.rate = vpll;
+
+	printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
+			apll, mpll, epll, vpll);
+
+	armclk = clk_get_rate(&exynos4_clk_armclk.clk);
+	sclk_dmc = clk_get_rate(&exynos4_clk_sclk_dmc.clk);
+
+	aclk_200 = clk_get_rate(&exynos4_clk_aclk_200.clk);
+	aclk_100 = clk_get_rate(&exynos4_clk_aclk_100.clk);
+	aclk_160 = clk_get_rate(&exynos4_clk_aclk_160.clk);
+	aclk_133 = clk_get_rate(&exynos4_clk_aclk_133.clk);
+
+	printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
+			"ACLK160=%ld, ACLK133=%ld, ACLK100=%ld\n",
+			armclk, sclk_dmc, aclk_200,
+			aclk_160, aclk_133, aclk_100);
+#ifdef CONFIG_CPU_EXYNOS4212
+	printk(KERN_INFO "EXYNOS4: ACLK400=%ld ACLK266=%ld\n",
+			clk_get_rate(&exynos4212_clk_aclk_400_mcuisp.clk), clk_get_rate(&exynos4212_clk_aclk_266.clk));
+#endif
+
+	clk_f.rate = armclk;
+	clk_h.rate = sclk_dmc;
+	clk_p.rate = aclk_100;
+
+	clk_fout_epll.ops = &exynos4_epll_ops;
+
+#if defined(CONFIG_MACH_M0) && defined(CONFIG_TARGET_LOCALE_EUR)
+	if (clk_set_parent(&exynos4_clk_dout_mmc3.clk, &exynos4_clk_mout_epll.clk))
+		printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
+				 exynos4_clk_mout_epll.clk.name, exynos4_clk_dout_mmc3.clk.name);
+#endif
+
+#ifdef CONFIG_EXYNOS4_MSHC_EPLL_45MHZ
+	if (clk_set_parent(&exynos4_clk_dout_mmc4.clk, &exynos4_clk_mout_epll.clk))
+		printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
+				 exynos4_clk_mout_epll.clk.name, exynos4_clk_dout_mmc4.clk.name);
+#endif
+#ifdef CONFIG_EXYNOS4_MSHC_VPLL_46MHZ
+	if (clk_set_parent(&exynos4_clk_dout_mmc4.clk, &exynos4_clk_sclk_vpll.clk))
+		printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
+				exynos4_clk_sclk_vpll.clk.name, exynos4_clk_dout_mmc4.clk.name);
+	if (clk_set_parent(&exynos4_clk_sclk_vpll.clk, &exynos4_clk_fout_vpll))
+		printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
+				exynos4_clk_fout_vpll.clk.name, exynos4_clk_sclk_vpll.clk.name);
+#endif
+
+	if (clk_set_parent(&exynos4_clk_mout_audss.clk, &clk_fout_epll))
+		printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
+				clk_fout_epll.name, exynos4_clk_mout_audss.clk.name);
+
+#if defined(CONFIG_SND_SAMSUNG_PCM) && !defined(CONFIG_SND_SAMSUNG_PCM_USE_EPLL)
+	if (clk_set_parent(&exynos4_clk_sclk_audio0.clk, &exynos4_clk_audiocdclk0.clk))
+		printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
+				exynos4_clk_audiocdclk0.clk.name, exynos4_clk_sclk_audio0.clk.name);
+#else
+	if (clk_set_parent(&exynos4_clk_sclk_audio0.clk, &exynos4_clk_mout_epll.clk))
+		printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
+				exynos4_clk_mout_epll.clk.name, exynos4_clk_sclk_audio0.clk.name);
+#endif
+
+	if (clk_set_parent(&exynos4_clk_sclk_audio1.clk, &exynos4_clk_mout_epll.clk))
+		printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
+				exynos4_clk_mout_epll.clk.name, exynos4_clk_sclk_audio1.clk.name);
+	if (clk_set_parent(&exynos4_clk_sclk_audio2.clk, &exynos4_clk_mout_epll.clk))
+		printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
+				exynos4_clk_mout_epll.clk.name, exynos4_clk_sclk_audio2.clk.name);
+	if (clk_set_parent(&exynos4_clk_mout_epll.clk, &clk_fout_epll))
+		printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
+				clk_fout_epll.name, exynos4_clk_mout_epll.clk.name);
+
+	clk_fout_vpll.enable = exynos4_clk_vpll_ctrl;
+	clk_fout_vpll.ops = &exynos4_vpll_ops;
+
+	clk_set_rate(&exynos4_clk_sclk_apll.clk, 100000000);
+
+	for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrcs); ptr++)
+		s3c_set_clksrc(&exynos4_clksrcs[ptr], true);
+}
+
+static struct clk *exynos4_clks[] __initdata = {
+	&exynos4_clk_sclk_hdmi27m,
+	&exynos4_clk_sclk_hdmiphy,
+};
+
+#ifdef CONFIG_PM
+static int exynos4_clock_suspend(void)
+{
+	unsigned int tmp;
+
+	if (!soc_is_exynos4210()) {
+		tmp = __raw_readl(EXYNOS4_CLKSRC_TOP1);
+		tmp &= ~(0x1 << EXYNOS4_CLKDIV_TOP1_ACLK200_SUB_SHIFT |
+			0x1 << EXYNOS4_CLKDIV_TOP1_ACLK400_MCUISP_SUB_SHIFT);
+		__raw_writel(tmp, EXYNOS4_CLKSRC_TOP1);
+	}
+
+	s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
+
+	return 0;
+}
+
+static void exynos4_clock_resume(void)
+{
+	s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
+}
+#else
+#define exynos4_clock_suspend NULL
+#define exynos4_clock_resume NULL
+#endif
+
+struct syscore_ops exynos4_clock_syscore_ops = {
+	.suspend        = exynos4_clock_suspend,
+	.resume         = exynos4_clock_resume,
+};
+
+void __init exynos4_register_clocks(void)
+{
+	int ptr;
+
+	s3c24xx_register_clocks(exynos4_clks, ARRAY_SIZE(exynos4_clks));
+
+	for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sysclks); ptr++)
+		s3c_register_clksrc(exynos4_sysclks[ptr], 1);
+
+	for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sclk_tv); ptr++)
+		s3c_register_clksrc(exynos4_sclk_tv[ptr], 1);
+
+	s3c_register_clksrc(exynos4_clksrcs, ARRAY_SIZE(exynos4_clksrcs));
+	s3c_register_clocks(exynos4_init_clocks, ARRAY_SIZE(exynos4_init_clocks));
+
+	s3c_register_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
+	s3c_disable_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
+
+	s3c_register_clocks(exynos4_init_audss_clocks, ARRAY_SIZE(exynos4_init_audss_clocks));
+	s3c_disable_clocks(exynos4_init_audss_clocks, ARRAY_SIZE(exynos4_init_audss_clocks));
+
+	/* Register DMA Clock */
+	s3c_register_clocks(exynos4_init_dmaclocks, ARRAY_SIZE(exynos4_init_dmaclocks));
+	s3c_disable_clocks(exynos4_init_dmaclocks, ARRAY_SIZE(exynos4_init_dmaclocks));
+	s3c_register_clocks(exynos4_i2cs_clocks, ARRAY_SIZE(exynos4_i2cs_clocks));
+	s3c_disable_clocks(exynos4_i2cs_clocks, ARRAY_SIZE(exynos4_i2cs_clocks));
+
+	s3c_register_clocks(&exynos4_clk_fimg2d, 1);
+	s3c_disable_clocks(&exynos4_clk_fimg2d, 1);
+
+	register_syscore_ops(&exynos4_clock_syscore_ops);
+	s3c_pwmclk_init();
+}
+
+static int __init clock_domain_init(void)
+{
+	int index;
+
+	clock_add_domain(LPA_DOMAIN, &exynos4_init_dmaclocks[0]);
+	clock_add_domain(LPA_DOMAIN, &exynos4_init_dmaclocks[1]);
+	clock_add_domain(LPA_DOMAIN, &exynos4_init_dmaclocks[2]);
+	for (index = 0; index < ARRAY_SIZE(exynos4_i2cs_clocks); index++)
+		clock_add_domain(LPA_DOMAIN, &exynos4_i2cs_clocks[index]);
+
+	return 0;
+}
+late_initcall(clock_domain_init);
diff --git a/arch/arm/mach-exynos/clock-exynos4210.c b/arch/arm/mach-exynos/clock-exynos4210.c
new file mode 100644
index 0000000..569c523
--- /dev/null
+++ b/arch/arm/mach-exynos/clock-exynos4210.c
@@ -0,0 +1,426 @@
+/*
+ * linux/arch/arm/mach-exynos/clock-exynos4210.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS4210 - Clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/syscore_ops.h>
+
+#include <plat/cpu-freq.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/pll.h>
+#include <plat/s5p-clock.h>
+#include <plat/clock-clksrc.h>
+#include <plat/exynos4.h>
+#include <plat/pm.h>
+
+#include <mach/hardware.h>
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/dev-sysmmu.h>
+#include <mach/exynos-clock.h>
+#include <mach/dev-sysmmu.h>
+
+static struct clksrc_clk *sysclks[] = {
+	/* nothing here yet */
+};
+
+#ifdef CONFIG_PM
+static struct sleep_save exynos4210_clock_save[] = {
+	/* CMU side */
+	SAVE_ITEM(EXYNOS4_CLKSRC_MASK_LCD1),
+	SAVE_ITEM(EXYNOS4_CLKGATE_IP_IMAGE_4210),
+	SAVE_ITEM(EXYNOS4_CLKGATE_IP_LCD1),
+	SAVE_ITEM(EXYNOS4_CLKGATE_IP_PERIR_4210),
+	SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
+	SAVE_ITEM(EXYNOS4_CLKDIV_LCD1),
+	SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
+	SAVE_ITEM(EXYNOS4_CLKSRC_LCD1),
+};
+
+static struct sleep_save exynos4210_epll_save[] = {
+       SAVE_ITEM(EXYNOS4_EPLL_LOCK),
+       SAVE_ITEM(EXYNOS4_EPLL_CON0),
+       SAVE_ITEM(EXYNOS4_EPLL_CON1),
+};
+
+static struct sleep_save exynos4210_vpll_save[] = {
+       SAVE_ITEM(EXYNOS4_VPLL_LOCK),
+       SAVE_ITEM(EXYNOS4_VPLL_CON0),
+       SAVE_ITEM(EXYNOS4_VPLL_CON1),
+};
+#endif
+
+static int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_LCD1, clk, enable);
+}
+
+static struct clk init_clocks_off[] = {
+	{
+		.name		= "qeg2d",
+		.enable		= exynos4_clk_ip_image_ctrl,
+		.ctrlbit	= (1 << 6),
+	}, {
+		.name		= "fimg2d",
+		.enable		= exynos4_clk_ip_image_ctrl,
+		.ctrlbit	= (1 << 0),
+	}, {
+		.name		= "tvenc",
+		.parent		= &exynos4_clk_aclk_160.clk,
+		.enable		= exynos4_clk_ip_tv_ctrl,
+		.ctrlbit	= (1 << 2),
+#if !defined(CONFIG_VIDEO_TSI)
+	}, {
+		.name		= "tsi",
+		.enable		= exynos4_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 4),
+#endif
+	}, {
+		.name		= "sataphy",
+		.parent		= &exynos4_clk_aclk_133.clk,
+		.enable		= exynos4_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 3),
+	}, {
+		.name		= "sata",
+		.parent		= &exynos4_clk_aclk_133.clk,
+		.enable		= exynos4_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 10),
+	}, {
+		.name		= "ppmulcd1",
+		.enable		= exynos4_clk_ip_lcd1_ctrl,
+		.ctrlbit	= (1 << 5),
+	}, {
+		.name           = "sysmmu",
+		.devname        = SYSMMU_CLOCK_NAME(fimd1, 7),
+		.enable         = exynos4_clk_ip_lcd1_ctrl,
+		.ctrlbit        = (1 << 4),
+	}, {
+		.name		= "sysmmu",
+		.devname	= SYSMMU_CLOCK_NAME(g2d, 9),
+		.enable		= exynos4_clk_ip_image_ctrl,
+		.ctrlbit	= (1 << 3),
+	}, {
+		.name           = "dsim1",
+		.enable         = exynos4_clk_ip_lcd1_ctrl,
+		.ctrlbit        = (1 << 3),
+	}, {
+		.name           = "mdnie1",
+		.enable         = exynos4_clk_ip_lcd1_ctrl,
+		.ctrlbit        = (1 << 2),
+	}, {
+		.name           = "mie1",
+		.enable         = exynos4_clk_ip_lcd1_ctrl,
+		.ctrlbit        = (1 << 1),
+	}, {
+		.name           = "lcd",
+		.devname        = "s3cfb.1",
+		.enable         = exynos4_clk_ip_lcd1_ctrl,
+		.ctrlbit        = (1 << 0),
+	}, {
+		.name		= "pciephy",
+		.enable		= exynos4_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 2),
+	}, {
+		.name		= "pcie",
+		.enable		= exynos4_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 14),
+	}, {
+		.name		= "sysmmu",
+		.devname	= SYSMMU_CLOCK_NAME(pcie, 8),
+		.enable		= exynos4_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 18),
+	}, {
+		.name		= "sysmmu",
+		.devname	= SYSMMU_CLOCK_NAME(2d, 9),
+		.enable		= exynos4_clk_ip_image_ctrl,
+		.ctrlbit	= (1 << 3),
+	}, {
+		.name		= "modem",
+		.enable		= exynos4_clk_ip_peril_ctrl,
+		.ctrlbit	= (1 << 28),
+	}
+};
+
+static struct clk init_clocks[] = {
+	{
+		.name		= "cmu_dmcpart",
+		.enable		= exynos4_clk_ip_perir_ctrl,
+		.ctrlbit	= (1 << 4),
+#if defined(CONFIG_VIDEO_TSI)
+	}, {
+		.name		= "tsi",
+		.enable		= exynos4_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 4),
+#endif
+	}, {
+		.name		= "dmc1",
+		.enable		= exynos4_clk_ip_dmc_ctrl,
+		.ctrlbit	= (1 << 1),
+	}, {
+		.name		= "dmc0",
+		.enable		= exynos4_clk_ip_dmc_ctrl,
+		.ctrlbit	= (1 << 0),
+	},
+};
+
+static struct clksrc_clk clksrcs[] = {
+	{
+		.clk	= {
+			.name		= "sclk_sata",
+			.enable		= exynos4_clksrc_mask_fsys_ctrl,
+			.ctrlbit	= (1 << 24),
+		},
+		.sources = &exynos4_clkset_mout_corebus,
+		.reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 24, .size = 1 },
+		.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS0, .shift = 20, .size = 4 },
+	},
+};
+
+
+static u32 epll_div_4210[][6] = {
+	{ 192000000, 0, 48, 3, 1, 0 },
+	{ 180000000, 0, 45, 3, 1, 0 },
+	{  73728000, 1, 73, 3, 3, 47710 },
+	{  67737600, 1, 90, 4, 3, 20762 },
+	{  49152000, 0, 49, 3, 3, 9961 },
+	{  45158400, 0, 45, 3, 3, 10381 },
+	{ 180633600, 0, 45, 3, 1, 10381 },
+};
+
+static unsigned long exynos4210_epll_get_rate(struct clk *clk)
+{
+	return clk->rate;
+}
+
+static int exynos4210_epll_set_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned int epll_con, epll_con_k;
+	unsigned int i;
+	unsigned int tmp;
+	unsigned int epll_rate;
+	unsigned int locktime;
+	unsigned int lockcnt;
+
+	/* Return if nothing changed */
+	if (clk->rate == rate)
+		return 0;
+
+	if (clk->parent)
+		epll_rate = clk_get_rate(clk->parent);
+	else
+		epll_rate = clk_ext_xtal_mux.rate;
+
+	if (epll_rate != 24000000) {
+		pr_err("Invalid Clock : recommended clock is 24MHz.\n");
+		return -EINVAL;
+	}
+
+
+	epll_con = __raw_readl(EXYNOS4_EPLL_CON0);
+	epll_con &= ~(0x1 << 27 | \
+			PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |   \
+			PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
+			PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
+
+	for (i = 0; i < ARRAY_SIZE(epll_div_4210); i++) {
+		if (epll_div_4210[i][0] == rate) {
+			epll_con_k = epll_div_4210[i][5] << 0;
+			epll_con |= epll_div_4210[i][1] << 27;
+			epll_con |= epll_div_4210[i][2] << PLL46XX_MDIV_SHIFT;
+			epll_con |= epll_div_4210[i][3] << PLL46XX_PDIV_SHIFT;
+			epll_con |= epll_div_4210[i][4] << PLL46XX_SDIV_SHIFT;
+			break;
+		}
+	}
+
+	if (i == ARRAY_SIZE(epll_div_4210)) {
+		printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
+				__func__);
+		return -EINVAL;
+	}
+
+	epll_rate /= 1000000;
+
+	/* 3000 max_cycls : specification data */
+	locktime = 3000 / epll_rate * epll_div_4210[i][3];
+	lockcnt = locktime * 10000 / (10000 / epll_rate);
+
+	__raw_writel(lockcnt, EXYNOS4_EPLL_LOCK);
+
+	__raw_writel(epll_con, EXYNOS4_EPLL_CON0);
+	__raw_writel(epll_con_k, EXYNOS4_EPLL_CON1);
+
+	do {
+		tmp = __raw_readl(EXYNOS4_EPLL_CON0);
+	} while (!(tmp & 0x1 << EXYNOS4_EPLLCON0_LOCKED_SHIFT));
+
+	clk->rate = rate;
+
+	return 0;
+}
+
+
+static struct vpll_div_data vpll_div_4210[] = {
+	{54000000, 3, 53, 3, 1024, 0, 17, 0},
+	{108000000, 3, 53, 2, 1024, 0, 17, 0},
+	{260000000, 3, 63, 1, 1950, 0, 20, 1},
+	{330000000, 2, 53, 1, 2048, 1,  1, 1},
+#ifdef CONFIG_EXYNOS4_MSHC_VPLL_46MHZ
+	{370882812, 3, 44, 0, 2417, 0, 14, 0},
+#endif
+};
+
+static unsigned long exynos4210_vpll_get_rate(struct clk *clk)
+{
+	return clk->rate;
+}
+
+static int exynos4210_vpll_set_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned int vpll_con0, vpll_con1;
+	unsigned int i;
+
+	/* Return if nothing changed */
+	if (clk->rate == rate)
+		return 0;
+
+	vpll_con0 = __raw_readl(EXYNOS4_VPLL_CON0);
+	vpll_con0 &= ~(0x1 << 27 |					\
+			PLL90XX_MDIV_MASK << PLL90XX_MDIV_SHIFT |	\
+			PLL90XX_PDIV_MASK << PLL90XX_PDIV_SHIFT |	\
+			PLL90XX_SDIV_MASK << PLL90XX_SDIV_SHIFT);
+
+	vpll_con1 = __raw_readl(EXYNOS4_VPLL_CON1);
+	vpll_con1 &= ~(0x1f << 24 |	\
+			0x3f << 16 |	\
+			0xfff << 0);
+
+	for (i = 0; i < ARRAY_SIZE(vpll_div_4210); i++) {
+		if (vpll_div_4210[i].rate == rate) {
+			vpll_con0 |= vpll_div_4210[i].vsel << 27;
+			vpll_con0 |= vpll_div_4210[i].pdiv << PLL90XX_PDIV_SHIFT;
+			vpll_con0 |= vpll_div_4210[i].mdiv << PLL90XX_MDIV_SHIFT;
+			vpll_con0 |= vpll_div_4210[i].sdiv << PLL90XX_SDIV_SHIFT;
+			vpll_con1 |= vpll_div_4210[i].mrr << 24;
+			vpll_con1 |= vpll_div_4210[i].mfr << 16;
+			vpll_con1 |= vpll_div_4210[i].k << 0;
+			break;
+		}
+	}
+
+	if (i == ARRAY_SIZE(vpll_div_4210)) {
+		printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
+				__func__);
+		return -EINVAL;
+	}
+
+	__raw_writel(vpll_con0, EXYNOS4_VPLL_CON0);
+	__raw_writel(vpll_con1, EXYNOS4_VPLL_CON1);
+
+	clk->rate = rate;
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int exynos4210_clock_suspend(void)
+{
+	s3c_pm_do_save(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
+	s3c_pm_do_save(exynos4210_epll_save, ARRAY_SIZE(exynos4210_epll_save));
+	s3c_pm_do_save(exynos4210_vpll_save, ARRAY_SIZE(exynos4210_vpll_save));
+
+	return 0;
+}
+
+static void exynos4210_clock_resume(void)
+{
+	unsigned int tmp;
+
+	s3c_pm_do_restore_core(exynos4210_epll_save, ARRAY_SIZE(exynos4210_epll_save));
+	s3c_pm_do_restore_core(exynos4210_vpll_save, ARRAY_SIZE(exynos4210_vpll_save));
+
+	/* waiting epll & vpll locking time */
+	do {
+		tmp = __raw_readl(EXYNOS4_EPLL_CON0);
+	} while (!(tmp & 0x1 << EXYNOS4_EPLLCON0_LOCKED_SHIFT));
+
+	do {
+		tmp = __raw_readl(EXYNOS4_VPLL_CON0);
+	} while (!(tmp & 0x1 << EXYNOS4_VPLLCON0_LOCKED_SHIFT));
+
+	s3c_pm_do_restore_core(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
+}
+#else
+#define exynos4210_clock_suspend NULL
+#define exynos4210_clock_resume NULL
+#endif
+
+struct syscore_ops exynos4210_clock_syscore_ops = {
+	.suspend        = exynos4210_clock_suspend,
+	.resume         = exynos4210_clock_resume,
+};
+
+void __init exynos4210_register_clocks(void)
+{
+	int ptr;
+
+	exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_CPU;
+	exynos4_clk_mout_mpll.reg_src.shift = 8;
+	exynos4_clk_mout_mpll.reg_src.size = 1;
+
+	exynos4_clk_aclk_200.sources = &exynos4_clkset_aclk;
+	exynos4_clk_aclk_200.reg_src.reg = EXYNOS4_CLKSRC_TOP0;
+	exynos4_clk_aclk_200.reg_src.shift = 12;
+	exynos4_clk_aclk_200.reg_src.size = 1;
+	exynos4_clk_aclk_200.reg_div.reg = EXYNOS4_CLKDIV_TOP;
+	exynos4_clk_aclk_200.reg_div.shift = 0;
+	exynos4_clk_aclk_200.reg_div.size = 3;
+
+	exynos4_clk_fimg2d.enable = exynos4_clk_ip_image_ctrl;
+	exynos4_clk_fimg2d.ctrlbit = (1 << 3) | (1 << 0);
+
+	exynos4_clk_mout_g2d0.reg_src.reg = EXYNOS4_CLKSRC_IMAGE;
+	exynos4_clk_mout_g2d0.reg_src.shift = 0;
+	exynos4_clk_mout_g2d0.reg_src.size = 1;
+
+	exynos4_clk_mout_g2d1.reg_src.reg = EXYNOS4_CLKSRC_IMAGE;
+	exynos4_clk_mout_g2d1.reg_src.shift = 4;
+	exynos4_clk_mout_g2d1.reg_src.size = 1;
+
+	exynos4_clk_sclk_fimg2d.reg_src.reg = EXYNOS4_CLKSRC_IMAGE;
+	exynos4_clk_sclk_fimg2d.reg_src.shift = 8;
+	exynos4_clk_sclk_fimg2d.reg_src.size = 1;
+	exynos4_clk_sclk_fimg2d.reg_div.reg = EXYNOS4_CLKDIV_IMAGE;
+	exynos4_clk_sclk_fimg2d.reg_div.shift = 0;
+	exynos4_clk_sclk_fimg2d.reg_div.size = 4;
+
+	exynos4_init_dmaclocks[2].parent = &exynos4_init_dmaclocks[1];
+
+	exynos4_epll_ops.get_rate = exynos4210_epll_get_rate;
+	exynos4_epll_ops.set_rate = exynos4210_epll_set_rate;
+	exynos4_vpll_ops.get_rate = exynos4210_vpll_get_rate;
+	exynos4_vpll_ops.set_rate = exynos4210_vpll_set_rate;
+
+	for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
+		s3c_register_clksrc(sysclks[ptr], 1);
+
+	s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
+	s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
+
+	s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+	s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+	register_syscore_ops(&exynos4210_clock_syscore_ops);
+}
diff --git a/arch/arm/mach-exynos/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c
new file mode 100644
index 0000000..9e14ed9
--- /dev/null
+++ b/arch/arm/mach-exynos/clock-exynos4212.c
@@ -0,0 +1,1151 @@
+/*
+ * linux/arch/arm/mach-exynos/clock-exynos4212.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS4212 - Clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/syscore_ops.h>
+
+#include <plat/cpu-freq.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/pll.h>
+#include <plat/s5p-clock.h>
+#include <plat/clock-clksrc.h>
+#include <plat/exynos4.h>
+#include <plat/pm.h>
+
+#include <mach/hardware.h>
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/dev-sysmmu.h>
+#include <mach/exynos-clock.h>
+#include <mach/dev-sysmmu.h>
+
+#ifdef CONFIG_PM
+static struct sleep_save exynos4212_clock_save[] = {
+	/* CMU side */
+	SAVE_ITEM(EXYNOS4_DMC_PAUSE_CTRL),
+	SAVE_ITEM(EXYNOS4_CLKGATE_IP_ISP),
+	SAVE_ITEM(EXYNOS4_CLKGATE_IP_DMC1),
+	SAVE_ITEM(EXYNOS4_CLKGATE_IP_IMAGE_4212),
+	SAVE_ITEM(EXYNOS4_CLKGATE_IP_PERIR_4212),
+	SAVE_ITEM(EXYNOS4_CLKGATE_BUS_LEFTBUS),
+	SAVE_ITEM(EXYNOS4_CLKGATE_BUS_IMAGE),
+	SAVE_ITEM(EXYNOS4_CLKGATE_BUS_RIGHTBUS),
+	SAVE_ITEM(EXYNOS4_CLKGATE_BUS_PERIR),
+	SAVE_ITEM(EXYNOS4_CLKGATE_BUS_PERIL),
+	SAVE_ITEM(EXYNOS4_CLKGATE_BUS_DMC0),
+	SAVE_ITEM(EXYNOS4_CLKGATE_BUS_DMC1),
+	SAVE_ITEM(EXYNOS4_CLKGATE_SCLK_DMC),
+	SAVE_ITEM(EXYNOS4_CLKDIV_CAM1),
+	SAVE_ITEM(EXYNOS4_CLKDIV_ISP),
+	SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
+	SAVE_ITEM(EXYNOS4_CLKSRC_MASK_ISP),
+	SAVE_ITEM(EXYNOS4_CLKSRC_ISP),
+	SAVE_ITEM(EXYNOS4_CLKSRC_CAM1),
+	SAVE_ITEM(EXYNOS4_CLKOUT_CMU_LEFTBUS),
+	SAVE_ITEM(EXYNOS4_CLKOUT_CMU_RIGHTBUS),
+	SAVE_ITEM(EXYNOS4_CLKOUT_CMU_TOP),
+	SAVE_ITEM(EXYNOS4_CLKOUT_CMU_DMC),
+	SAVE_ITEM(EXYNOS4_CLKOUT_CMU_CPU),
+#ifdef CONFIG_EXYNOS4_ENABLE_CLOCK_DOWN
+	SAVE_ITEM(EXYNOS4_PWR_CTRL1),
+	SAVE_ITEM(EXYNOS4_PWR_CTRL2),
+#endif
+};
+
+static struct sleep_save exynos4212_epll_save[] = {
+	SAVE_ITEM(EXYNOS4_EPLL_LOCK),
+	SAVE_ITEM(EXYNOS4_EPLL_CON0),
+	SAVE_ITEM(EXYNOS4_EPLL_CON1),
+	SAVE_ITEM(EXYNOS4_EPLL_CON2),
+};
+
+static struct sleep_save exynos4212_vpll_save[] = {
+	SAVE_ITEM(EXYNOS4_VPLL_LOCK),
+	SAVE_ITEM(EXYNOS4_VPLL_CON0),
+	SAVE_ITEM(EXYNOS4_VPLL_CON1),
+	SAVE_ITEM(EXYNOS4_VPLL_CON2),
+};
+#endif
+
+struct exynos4_cmu_conf {
+	void __iomem *reg;
+	unsigned long val;
+};
+
+static struct exynos4_cmu_conf exynos4x12_cmu_config[] = {
+	/* Register Address		Value */
+	{ EXYNOS4_CLKOUT_CMU_LEFTBUS,	0x0},
+	{ EXYNOS4_CLKOUT_CMU_RIGHTBUS,	0x0},
+	{ EXYNOS4_CLKOUT_CMU_TOP,	0x0},
+	{ EXYNOS4_CLKOUT_CMU_DMC,	0x0},
+	{ EXYNOS4_CLKOUT_CMU_CPU,	0x0},
+	{ EXYNOS4_CLKOUT_CMU_ISP,	0x0},
+};
+
+static int exynos4212_clk_bus_dmc0_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_CLKGATE_BUS_DMC0, clk, enable);
+}
+
+static int exynos4212_clk_bus_dmc1_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_CLKGATE_BUS_DMC1, clk, enable);
+}
+
+static int exynos4212_clk_sclk_dmc_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_CLKGATE_SCLK_DMC, clk, enable);
+}
+
+static int __maybe_unused exynos4212_clk_bus_peril_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_CLKGATE_BUS_PERIL, clk, enable);
+}
+
+static int __maybe_unused exynos4212_clk_bus_perir_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_CLKGATE_BUS_PERIR, clk, enable);
+}
+
+static int exynos4212_clk_ip_audio_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_MAUDIO, clk, enable);
+}
+
+static int exynos4212_clk_ip_dmc1_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_DMC1, clk, enable);
+}
+
+static int exynos4212_clk_ip_isp_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP, clk, enable);
+}
+
+static int exynos4212_clk_ip_isp0_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP0, clk, enable);
+}
+
+static int exynos4212_clk_ip_isp1_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP1, clk, enable);
+}
+
+static struct clk *exynos4212_clk_src_mpll_user_list[] = {
+	[0] = &clk_fin_mpll,
+	[1] = &exynos4_clk_mout_mpll.clk,
+};
+
+static struct clksrc_sources exynos4212_clk_src_mpll_user = {
+	.sources	= exynos4212_clk_src_mpll_user_list,
+	.nr_sources	= ARRAY_SIZE(exynos4212_clk_src_mpll_user_list),
+};
+
+static struct clksrc_clk exynos4212_clk_mout_mpll_user = {
+	.clk	= {
+		.name		= "mout_mpll_user",
+	},
+	.sources = &exynos4212_clk_src_mpll_user,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 },
+};
+
+static struct clk *exynos4212_clkset_aclk_lrbus_user_list[] = {
+	[0] = &clk_fin_mpll,
+	[1] = &exynos4_clk_mout_mpll.clk,
+};
+
+static struct clksrc_sources exynos4212_clkset_aclk_lrbus_user = {
+	.sources	= exynos4212_clkset_aclk_lrbus_user_list,
+	.nr_sources	= ARRAY_SIZE(exynos4212_clkset_aclk_lrbus_user_list),
+};
+
+static struct clksrc_clk exynos4212_clk_aclk_gdl_user = {
+	.clk	= {
+		.name		= "aclk_gdl_user",
+	},
+	.sources = &exynos4212_clkset_aclk_lrbus_user,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_LEFTBUS, .shift = 4, .size = 1 },
+};
+
+static struct clksrc_clk exynos4212_clk_aclk_gdr_user = {
+	.clk	= {
+		.name		= "aclk_gdr_user",
+	},
+	.sources = &exynos4212_clkset_aclk_lrbus_user,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_RIGHTBUS, .shift = 4, .size = 1 },
+};
+
+static struct clksrc_clk exynos4212_clk_mout_aclk_266 = {
+	.clk	= {
+		.name		= "mout_aclk_266",
+	},
+	.sources = &exynos4_clkset_aclk,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_TOP1, .shift = 4, .size = 1 },
+};
+
+static struct clksrc_clk exynos4212_clk_dout_aclk_266 = {
+	.clk	= {
+		.name		= "dout_aclk_266",
+		.parent		= &exynos4212_clk_mout_aclk_266.clk,
+	},
+	.reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 20, .size = 3 },
+};
+
+static struct clksrc_clk exynos4212_clk_mout_aclk_200 = {
+	.clk	= {
+		.name		= "mout_aclk_200",
+	},
+	.sources = &exynos4_clkset_aclk,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 12, .size = 1 },
+};
+
+static struct clksrc_clk exynos4212_clk_dout_aclk_200 = {
+	.clk	= {
+		.name		= "dout_aclk_200",
+		.parent		= &exynos4212_clk_mout_aclk_200.clk,
+	},
+	.reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk exynos4212_clk_mout_aclk_400_mcuisp = {
+	.clk	= {
+		.name		= "mout_aclk_400_mcuisp",
+	},
+	.sources = &exynos4_clkset_aclk,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_TOP1, .shift = 8, .size = 1 },
+};
+
+static struct clksrc_clk exynos4212_clk_dout_aclk_400_mcuisp = {
+	.clk	= {
+		.name		= "dout_aclk_400_mcuisp",
+		.parent		= &exynos4212_clk_mout_aclk_400_mcuisp.clk,
+	},
+	.reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 24, .size = 3 },
+};
+
+static struct clk *exynos4212_clk_aclk_400_mcuisp_list[] = {
+	[0] = &clk_fin_mpll,
+	[1] = &exynos4212_clk_dout_aclk_400_mcuisp.clk,
+};
+
+static struct clksrc_sources exynos4212_clkset_aclk_400_mcuisp = {
+	.sources	= exynos4212_clk_aclk_400_mcuisp_list,
+	.nr_sources	= ARRAY_SIZE(exynos4212_clk_aclk_400_mcuisp_list),
+};
+
+struct clksrc_clk exynos4212_clk_aclk_400_mcuisp = {
+	.clk	= {
+		.name		= "aclk_400_mcuisp",
+	},
+	.sources = &exynos4212_clkset_aclk_400_mcuisp,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_TOP1, .shift = 24, .size = 1 },
+};
+
+static struct clk *exynos4212_clk_aclk_266_list[] = {
+	[0] = &clk_fin_mpll,
+	[1] = &exynos4212_clk_dout_aclk_266.clk,
+};
+
+static struct clksrc_sources exynos4212_clkset_aclk_266 = {
+	.sources	= exynos4212_clk_aclk_266_list,
+	.nr_sources	= ARRAY_SIZE(exynos4212_clk_aclk_266_list),
+};
+
+struct clksrc_clk exynos4212_clk_aclk_266 = {
+	.clk	= {
+		.name		= "aclk_266",
+	},
+	.sources = &exynos4212_clkset_aclk_266,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_TOP1, .shift = 16, .size = 1 },
+};
+
+static struct clk *exynos4212_clk_aclk_200_list[] = {
+	[0] = &clk_fin_mpll,
+	[1] = &exynos4212_clk_dout_aclk_200.clk,
+};
+
+static struct clksrc_sources exynos4212_clkset_aclk_200 = {
+	.sources	= exynos4212_clk_aclk_200_list,
+	.nr_sources	= ARRAY_SIZE(exynos4212_clk_aclk_200_list),
+};
+
+static struct clk *exynos4212_clkset_mout_jpeg0_list[] = {
+	[0] = &exynos4212_clk_mout_mpll_user.clk,
+	[1] = &exynos4_clk_sclk_apll.clk,
+};
+
+static struct clksrc_sources exynos4212_clkset_mout_jpeg0 = {
+	.sources	= exynos4212_clkset_mout_jpeg0_list,
+	.nr_sources	= ARRAY_SIZE(exynos4212_clkset_mout_jpeg0_list),
+};
+
+struct clksrc_clk exynos4212_clk_mout_jpeg0 = {
+	.clk	= {
+		.name		= "mout_jpeg0",
+	},
+	.sources = &exynos4212_clkset_mout_jpeg0,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_CAM1, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos4212_clkset_mout_jpeg1_list[] = {
+	[0] = &exynos4_clk_mout_epll.clk,
+	[1] = &exynos4_clk_sclk_vpll.clk,
+};
+
+struct clksrc_sources exynos4212_clkset_mout_jpeg1 = {
+	.sources	= exynos4212_clkset_mout_jpeg1_list,
+	.nr_sources	= ARRAY_SIZE(exynos4212_clkset_mout_jpeg1_list),
+};
+
+struct clksrc_clk exynos4212_clk_mout_jpeg1 = {
+	.clk	= {
+		.name		= "mout_jpeg1",
+	},
+	.sources = &exynos4212_clkset_mout_jpeg1,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_CAM1, .shift = 4, .size = 1 },
+};
+
+static struct clk *exynos4212_clkset_mout_jpeg_list[] = {
+	[0] = &exynos4212_clk_mout_jpeg0.clk,
+	[1] = &exynos4212_clk_mout_jpeg1.clk,
+};
+
+static struct clksrc_sources exynos4212_clkset_mout_jpeg = {
+	.sources	= exynos4212_clkset_mout_jpeg_list,
+	.nr_sources	= ARRAY_SIZE(exynos4212_clkset_mout_jpeg_list),
+};
+
+struct clksrc_clk exynos4212_clk_aclk_jpeg = {
+	.clk	= {
+		.name		= "aclk_clk_jpeg",
+	},
+	.sources = &exynos4212_clkset_mout_jpeg,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_CAM1, .shift = 8, .size = 1 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_CAM1, .shift = 0, .size = 4 },
+};
+
+static struct clk *exynos4212_clkset_c2c_list[] = {
+	[0] = &exynos4_clk_mout_mpll.clk,
+	[1] = &exynos4_clk_sclk_apll.clk,
+};
+
+static struct clksrc_sources exynos4212_clkset_sclk_c2c = {
+	.sources	= exynos4212_clkset_c2c_list,
+	.nr_sources	= ARRAY_SIZE(exynos4212_clkset_c2c_list),
+};
+
+static struct clksrc_clk exynos4212_clk_sclk_c2c = {
+	.clk	= {
+		.name		= "sclk_c2c",
+		.id		= -1,
+	},
+	.sources = &exynos4212_clkset_sclk_c2c,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 0, .size = 1 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_DMC1, .shift = 4, .size = 3 },
+};
+
+static struct clksrc_clk exynos4212_clk_aclk_c2c = {
+	.clk	= {
+		.name		= "aclk_c2c",
+		.id		= -1,
+		.parent		= &exynos4212_clk_sclk_c2c.clk,
+	},
+	.reg_div = { .reg = EXYNOS4_CLKDIV_DMC1, .shift = 12, .size = 3 },
+};
+
+static struct clksrc_clk *exynos4212_sysclks[] = {
+	&exynos4212_clk_mout_mpll_user,
+	&exynos4212_clk_aclk_gdl_user,
+	&exynos4212_clk_aclk_gdr_user,
+	&exynos4212_clk_mout_aclk_400_mcuisp,
+	&exynos4212_clk_mout_aclk_266,
+	&exynos4212_clk_mout_aclk_200,
+	&exynos4212_clk_dout_aclk_200,
+	&exynos4212_clk_aclk_400_mcuisp,
+	&exynos4212_clk_aclk_266,
+	&exynos4212_clk_mout_jpeg0,
+	&exynos4212_clk_mout_jpeg1,
+	&exynos4212_clk_aclk_jpeg,
+	&exynos4212_clk_sclk_c2c,
+	&exynos4212_clk_aclk_c2c,
+};
+
+static struct clk exynos4212_init_clocks_off[] = {
+	{
+		.name		= "qejpeg",
+		.enable		= exynos4_clk_ip_cam_ctrl,
+		.ctrlbit	= (1 << 19),
+	}, {
+		.name		= "async_tvx",
+		.enable		= exynos4_clk_ip_leftbus_ctrl,
+		.ctrlbit	= (1 << 3),
+	}, {
+		.name		= "mipihsi",
+		.parent		= &exynos4_clk_aclk_133.clk,
+		.enable		= exynos4_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 10),
+	}, {
+		.name		= "ppmuisp",
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 21 | 1 << 20),
+	}, {
+		.name		= "qegps",
+		.enable		= exynos4_clk_ip_gps_ctrl,
+		.ctrlbit	= (1 << 3),
+	}, {
+		.name		= "ppmugps",
+		.enable		= exynos4_clk_ip_gps_ctrl,
+		.ctrlbit	= (1 << 2),
+	}, {
+		.name		= "sysmmu",
+		.devname	= SYSMMU_CLOCK_NAME(g2d_acp, 15),
+		.enable		= exynos4_clk_ip_dmc_ctrl,
+		.ctrlbit	= (1 << 24),
+	}, {
+		.name		= "sysmmu",
+		.devname	= SYSMMU_CLOCK_NAME(ispcx, 22),
+		.enable		= exynos4212_clk_ip_isp1_ctrl,
+		.ctrlbit	= (1 << 4),
+	}, {
+		.name		= "sysmmu",
+		.devname	= SYSMMU_CLOCK_NAME(lite1, 21),
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 12),
+	}, {
+		.name		= "sysmmu",
+		.devname	= SYSMMU_CLOCK_NAME(lite0, 20),
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 11),
+	}, {
+		.name		= "sysmmu",
+		.devname	= SYSMMU_CLOCK_NAME(is_isp, 16),
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 8),
+	}, {
+		.name		= "sysmmu",
+		.devname	= SYSMMU_CLOCK_NAME(is_drc, 17),
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 9),
+	}, {
+		.name		= "sysmmu",
+		.devname	= SYSMMU_CLOCK_NAME(is_fd, 18),
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 10),
+	}, {
+		.name		= "sysmmu",
+		.devname	= SYSMMU_CLOCK_NAME(is_cpu, 19),
+		.enable		= exynos4212_clk_ip_isp1_ctrl,
+		.ctrlbit	= (1 << 4),
+	}, {
+		.name		= "qec2c",
+		.enable		= exynos4_clk_ip_dmc_ctrl,
+		.ctrlbit	= (1 << 30),
+#ifndef CONFIG_SAMSUNG_C2C
+	}, {
+		.name		= "c2c",
+		.devname	= "samsung-c2c",
+		.enable		= exynos4_clk_ip_dmc_ctrl,
+#ifdef CONFIG_MACH_M0_CTC
+		.ctrlbit	= (1 << 26 | 1 << 27),
+#else
+		.ctrlbit	= (1 << 26 | 1 << 27 | 1 << 31),
+#endif
+	}, {
+		.name		= "sclk_c2c_off",
+		.enable		= exynos4212_clk_sclk_dmc_ctrl,
+		.ctrlbit	= (1 << 8),
+	}, {
+		.name		= "pclk_c2c_off",
+		.enable		= exynos4212_clk_bus_dmc1_ctrl,
+		.ctrlbit	= (1 << 27 | 1 << 30),
+	}, {
+		.name		= "aclk_c2c_off",
+		.enable		= exynos4212_clk_bus_dmc0_ctrl,
+		.ctrlbit	= (1 << 21 | 1 << 22 | 1 << 24),
+#endif
+	}, {
+		.name		= "mtcadc",
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 27),
+	}, {
+		.name		= "i2c0_isp",
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 25),
+	}, {
+		.name		= "mpwm_isp",
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 24),
+	}, {
+		.name		= "qelite1",
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 18),
+	}, {
+		.name		= "qelite0",
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 17),
+	}, {
+		.name		= "qefd",
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 16),
+	}, {
+		.name		= "qedrc",
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 15),
+	}, {
+		.name		= "qeisp",
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 14),
+	}, {
+		.name		= "lite0",
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 3),
+	}, {
+		.name		= "spi1_isp",
+		.enable		= exynos4212_clk_ip_isp1_ctrl,
+		.ctrlbit	= (1 << 13),
+	}, {
+		.name		= "spi0_isp",
+		.enable		= exynos4212_clk_ip_isp1_ctrl,
+		.ctrlbit	= (1 << 12),
+	},
+};
+
+static struct clk exynos4212_init_clocks[] = {
+	{
+		.name		= "cmu_isp",
+		.enable		= exynos4_clk_ip_perir_ctrl,
+		.ctrlbit	= (1 << 18),
+	}, {
+		.name		= "async_maudiox",
+		.enable		= exynos4_clk_ip_rightbus_ctrl,
+		.ctrlbit	= (1 << 7),
+	}, {
+		.name		= "async_mfcr",
+		.enable		= exynos4_clk_ip_rightbus_ctrl,
+		.ctrlbit	= (1 << 6),
+	}, {
+		.name		= "async_fsysd",
+		.enable		= exynos4_clk_ip_rightbus_ctrl,
+		.ctrlbit	= (1 << 5),
+	}, {
+		.name		= "async_camx",
+		.enable		= exynos4_clk_ip_rightbus_ctrl,
+		.ctrlbit	= (1 << 2),
+	}, {
+		.name		= "async_axim",
+		.enable		= exynos4212_clk_ip_isp1_ctrl,
+		.ctrlbit	= (1 << 0),
+	}, {
+		.name		= "uart_isp",
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 31),
+	}, {
+		.name		= "wdt_isp",
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 30),
+	}, {
+		.name		= "pwm_isp",
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 28),
+	}, {
+		.name		= "i2c1_isp",
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 26),
+	}, {
+		.name		= "mcuctl_isp",
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 23),
+	}, {
+		.name		= "gic_isp",
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 7),
+	}, {
+		.name		= "mcuisp",
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 5),
+	}, {
+		.name		= "lite1",
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 4),
+	}, {
+		.name		= "fimc_fd",
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 2),
+	}, {
+		.name		= "fimc_drc",
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 1),
+	}, {
+		.name		= "fimc_isp",
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 0),
+	}, {
+		.name		= "tzasc_lr",
+		.enable		= exynos4212_clk_ip_dmc1_ctrl,
+		.ctrlbit	= (1 << 3),
+	}, {
+		.name		= "tzasc_lw",
+		.enable		= exynos4212_clk_ip_dmc1_ctrl,
+		.ctrlbit	= (1 << 2),
+	}, {
+		.name		= "tzasc_rr",
+		.enable		= exynos4212_clk_ip_dmc1_ctrl,
+		.ctrlbit	= (1 << 1),
+	}, {
+		.name		= "tzasc_rw",
+		.enable		= exynos4212_clk_ip_dmc1_ctrl,
+		.ctrlbit	= (1 << 0),
+	}, {
+#ifdef CONFIG_MACH_M0_CTC
+		.name		= "gpioc2c",
+		.enable		= exynos4_clk_ip_dmc_ctrl,
+		.ctrlbit	= (1 << 31),
+	}, {
+#endif
+		.name		= "qegdl",
+		.enable		= exynos4_clk_ip_dmc_ctrl,
+		.ctrlbit	= (1 << 29),
+	}, {
+		.name		= "async_cpu_xiur",
+		.enable		= exynos4_clk_ip_dmc_ctrl,
+		.ctrlbit	= (1 << 28),
+	}, {
+		.name		= "async_gdr",
+		.enable		= exynos4_clk_ip_dmc_ctrl,
+		.ctrlbit	= (1 << 22),
+	}, {
+		.name		= "async_gdl",
+		.enable		= exynos4_clk_ip_dmc_ctrl,
+		.ctrlbit	= (1 << 21),
+	}, {
+		.name		= "drex2",
+		.enable		= exynos4_clk_ip_dmc_ctrl,
+		.ctrlbit	= (1 << 0),
+	}, {
+		.name		= "i2s0",
+		.enable		= exynos4212_clk_ip_audio_ctrl,
+		.ctrlbit	= (1 << 3),
+	}, {
+		.name		= "pcm0",
+		.enable		= exynos4212_clk_ip_audio_ctrl,
+		.ctrlbit	= (1 << 2),
+	}, {
+		.name		= "imem",
+		.enable		= exynos4212_clk_ip_audio_ctrl,
+		.ctrlbit	= (1 << 1),
+	}, {
+		.name		= "audioss",
+		.enable		= exynos4212_clk_ip_audio_ctrl,
+		.ctrlbit	= (1 << 0),
+	}, {
+		.name		= "async_ispmx",
+		.enable		= exynos4_clk_ip_rightbus_ctrl,
+		.ctrlbit	= (1 << 9),
+	}, {
+		.name		= "async_lcd0x",
+		.enable		= exynos4_clk_ip_rightbus_ctrl,
+		.ctrlbit	= (1 << 3),
+	}, {
+		.name		= "gpio_right",
+		.enable		= exynos4_clk_ip_rightbus_ctrl,
+		.ctrlbit	= (1 << 0),
+	}, {
+		.name		= "async_g3d",
+		.enable		= exynos4_clk_ip_leftbus_ctrl,
+		.ctrlbit	= (1 << 6),
+	}, {
+		.name		= "async_mfcl",
+		.enable		= exynos4_clk_ip_leftbus_ctrl,
+		.ctrlbit	= (1 << 4),
+	}, {
+		.name		= "gpio_left",
+		.enable		= exynos4_clk_ip_leftbus_ctrl,
+		.ctrlbit	= (1 << 0),
+	}, {
+		.name		= "qeg2d_acp",
+		.enable		= exynos4_clk_ip_dmc_ctrl,
+		.ctrlbit	= (1 << 25),
+	}, {
+		.name		= "g2d_acp",
+		.enable		= exynos4_clk_ip_dmc_ctrl,
+		.ctrlbit	= (1 << 23),
+	}, {
+		.name		= "uart_isp",
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 31),
+	}, {
+		.name		= "wdt_isp",
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 30),
+	}, {
+		.name		= "pwm_isp",
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 28),
+	}, {
+		.name		= "mtcadc",
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 27),
+	}, {
+		.name		= "i2c1_isp",
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 26),
+	}, {
+		.name		= "i2c0_isp",
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 25),
+	}, {
+		.name		= "mpwm_isp",
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 24),
+	}, {
+		.name		= "mcuctl_isp",
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 23),
+	}, {
+		.name		= "qelite1",
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 18),
+	}, {
+		.name		= "qelite0",
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 17),
+	}, {
+		.name		= "qefd",
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 16),
+	}, {
+		.name		= "qedrc",
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 15),
+	}, {
+		.name		= "qeisp",
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 14),
+	}, {
+		.name		= "sysmmu_lite1",
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 12),
+	}, {
+		.name		= "sysmmu_lite0",
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 11),
+	}, {
+		.name		= "gic_isp",
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 7),
+	}, {
+		.name		= "mcu_isp",
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 5),
+	}, {
+		.name		= "lite1",
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 4),
+	}, {
+		.name		= "lite0",
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 3),
+	}, {
+		.name		= "fd",
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 2),
+	}, {
+		.name		= "drc",
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 1),
+	}, {
+		.name		= "isp",
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 0),
+	}, {
+		.name		= "spi1_isp",
+		.enable		= exynos4212_clk_ip_isp1_ctrl,
+		.ctrlbit	= (1 << 13),
+	}, {
+		.name		= "spi0_isp",
+		.enable		= exynos4212_clk_ip_isp1_ctrl,
+		.ctrlbit	= (1 << 12),
+	}, {
+		.name		= "aync_caxim",
+		.enable		= exynos4212_clk_ip_isp1_ctrl,
+		.ctrlbit	= (1 << 0),
+	}, {
+		.name		= "sysmmu_fd",
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 10),
+	}, {
+		.name		= "sysmmu_drc",
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 9),
+	}, {
+		.name		= "sysmmu_isp",
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (1 << 8),
+	}, {
+		.name		= "sysmmu_ispcx",
+		.enable		= exynos4212_clk_ip_isp1_ctrl,
+		.ctrlbit	= (1 << 4),
+	},
+};
+
+static struct clksrc_clk exynos4212_clksrcs[] = {
+	{
+		.clk	= {
+			.name		= "sclk_mipihsi",
+			.enable		= exynos4_clksrc_mask_fsys_ctrl,
+			.ctrlbit	= (1 << 24),
+		},
+		.sources = &exynos4_clkset_mout_corebus,
+		.reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 24, .size = 1 },
+		.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS0, .shift = 20, .size = 4 },
+	},
+};
+
+static struct clk exynos4212_clk_isp[] = {
+	{
+		.name	= "aclk_400_mcuisp_muxed",
+		.parent = &exynos4212_clk_aclk_400_mcuisp.clk,
+	}, {
+		.name	= "aclk_200_muxed",
+		.parent	= &exynos4_clk_aclk_200.clk,
+	},
+};
+
+static struct clksrc_clk exynos4212_clk_isp_srcs_div0 = {
+	.clk		= {
+		.name		= "sclk_mcuisp_div0",
+		.parent		= &exynos4212_clk_aclk_400_mcuisp.clk,
+	},
+	.reg_div = { .reg = EXYNOS4_CLKDIV_ISP1, .shift = 4, .size = 3 },
+};
+
+static struct clksrc_clk exynos4212_clk_isp_srcs[] = {
+	{
+		.clk		= {
+			.name		= "sclk_mcuisp_div1",
+			.parent = &exynos4212_clk_isp_srcs_div0.clk,
+		},
+		.reg_div = { .reg = EXYNOS4_CLKDIV_ISP1, .shift = 8, .size = 3 },
+	}, {
+		.clk		= {
+			.name		= "sclk_aclk_div0",
+			.parent = &exynos4_clk_aclk_200.clk,
+		},
+		.reg_div = { .reg = EXYNOS4_CLKDIV_ISP0, .shift = 0, .size = 3 },
+	}, {
+		.clk		= {
+			.name		= "sclk_aclk_div1",
+			.parent = &exynos4_clk_aclk_200.clk,
+		},
+		.reg_div = { .reg = EXYNOS4_CLKDIV_ISP0, .shift = 4, .size = 3 },
+	}, {
+		.clk		= {
+			.name		= "sclk_uart_isp",
+			.enable		= exynos4212_clk_ip_isp_ctrl,
+			.ctrlbit	= (1 << 3),
+		},
+		.sources = &exynos4_clkset_group,
+		.reg_src = { .reg = EXYNOS4_CLKSRC_ISP, .shift = 12, .size = 4 },
+		.reg_div = { .reg = EXYNOS4_CLKDIV_ISP, .shift = 28, .size = 4 },
+	}, {
+		.clk		= {
+			.name		= "sclk_spi1_isp",
+			.enable		= exynos4212_clk_ip_isp_ctrl,
+			.ctrlbit	= (1 << 2),
+		},
+		.sources = &exynos4_clkset_group,
+		.reg_src = { .reg = EXYNOS4_CLKSRC_ISP, .shift = 8, .size = 4 },
+		.reg_div = { .reg = EXYNOS4_CLKDIV_ISP, .shift = 16, .size = 12 },
+	}, {
+		.clk		= {
+			.name		= "sclk_spi0_isp",
+			.enable		= exynos4212_clk_ip_isp_ctrl,
+			.ctrlbit	= (1 << 1),
+		},
+		.sources = &exynos4_clkset_group,
+		.reg_src = { .reg = EXYNOS4_CLKSRC_ISP, .shift = 4, .size = 4 },
+		.reg_div = { .reg = EXYNOS4_CLKDIV_ISP, .shift = 4, .size = 12 },
+	}, {
+		.clk		= {
+			.name		= "sclk_pwm_isp",
+			.enable		= exynos4212_clk_ip_isp_ctrl,
+			.ctrlbit	= (1 << 0),
+		},
+		.sources = &exynos4_clkset_group,
+		.reg_src = { .reg = EXYNOS4_CLKSRC_ISP, .shift = 0, .size = 4 },
+		.reg_div = { .reg = EXYNOS4_CLKDIV_ISP, .shift = 0, .size = 4 },
+	},
+};
+
+static u32 epll_div_4212[][6] = {
+	{ 416000000, 0, 104, 3, 1, 0 },
+	{ 408000000, 0,  68, 2, 1, 0 },
+	{ 400000000, 0, 100, 3, 1, 0 },
+	{ 200000000, 0, 100, 3, 2, 0 },
+	{ 192000000, 0,  64, 2, 2, 0 },
+	{ 180633600, 0,  90, 3, 2, 20762 },
+	{ 180000000, 0,  60, 2, 2,  0 },
+};
+
+static unsigned long exynos4212_epll_get_rate(struct clk *clk)
+{
+	return clk->rate;
+}
+
+static int exynos4212_epll_set_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned int epll_con, epll_con_k;
+	unsigned int i;
+	unsigned int tmp;
+	unsigned int epll_rate;
+	unsigned int locktime;
+	unsigned int lockcnt;
+
+	/* Return if nothing changed */
+	if (clk->rate == rate)
+		return 0;
+
+	if (clk->parent)
+		epll_rate = clk_get_rate(clk->parent);
+	else
+		epll_rate = clk_ext_xtal_mux.rate;
+
+	if (epll_rate != 24000000) {
+		pr_err("Invalid Clock : recommended clock is 24MHz.\n");
+		return -EINVAL;
+	}
+
+	epll_con = __raw_readl(EXYNOS4_EPLL_CON0);
+	epll_con &= ~(0x1 << 27 | \
+			PLL36XX_MDIV_MASK << PLL36XX_MDIV_SHIFT |   \
+			PLL36XX_PDIV_MASK << PLL36XX_PDIV_SHIFT | \
+			PLL36XX_SDIV_MASK << PLL36XX_SDIV_SHIFT);
+
+	for (i = 0; i < ARRAY_SIZE(epll_div_4212); i++) {
+		if (epll_div_4212[i][0] == rate) {
+			epll_con_k = epll_div_4212[i][5] << 0;
+			epll_con |= epll_div_4212[i][2] << PLL36XX_MDIV_SHIFT;
+			epll_con |= epll_div_4212[i][3] << PLL36XX_PDIV_SHIFT;
+			epll_con |= epll_div_4212[i][4] << PLL36XX_SDIV_SHIFT;
+			break;
+		}
+	}
+
+	if (i == ARRAY_SIZE(epll_div_4212)) {
+		printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
+				__func__);
+		return -EINVAL;
+	}
+
+	epll_rate /= 1000000;
+
+	/* 3000 max_cycls : specification data */
+	locktime = 3000 / epll_rate * epll_div_4212[i][3];
+	lockcnt = locktime * 10000 / (10000 / epll_rate);
+
+	__raw_writel(lockcnt, EXYNOS4_EPLL_LOCK);
+	__raw_writel(epll_con, EXYNOS4_EPLL_CON0);
+	__raw_writel(epll_con_k, EXYNOS4_EPLL_CON1);
+
+
+	do {
+		tmp = __raw_readl(EXYNOS4_EPLL_CON0);
+	} while (!(tmp & 0x1 << EXYNOS4_EPLLCON0_LOCKED_SHIFT));
+
+	clk->rate = rate;
+
+	return 0;
+}
+
+static struct vpll_div_data vpll_div_4212[] = {
+	{54000000, 2, 72, 4, 0, 0, 0, 0},
+	{108000000, 2, 72, 3, 0, 0, 0, 0},
+	{160000000, 3, 160, 3, 0, 0, 0, 0},
+	{266000000, 3, 133, 2, 0, 0, 0, 0},
+	{275000000, 2, 92, 2, 43692, 0, 0, 0},
+	{300000000, 2, 100, 2, 0, 0, 0, 0},
+	{333000000, 2, 111, 2, 0, 0, 0, 0},
+	{350000000, 3, 175, 2, 0, 0, 0, 0},
+	{440000000, 3, 110, 1, 0, 0, 0, 0},
+};
+
+static unsigned long exynos4212_vpll_get_rate(struct clk *clk)
+{
+	return clk->rate;
+}
+
+static int exynos4212_vpll_set_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned int vpll_con0, vpll_con1;
+	unsigned int i;
+
+	/* Return if nothing changed */
+	if (clk->rate == rate)
+		return 0;
+
+	vpll_con0 = __raw_readl(EXYNOS4_VPLL_CON0);
+	vpll_con0 &= ~(PLL36XX_MDIV_MASK << PLL36XX_MDIV_SHIFT |	\
+		       PLL36XX_PDIV_MASK << PLL36XX_PDIV_SHIFT |	\
+		       PLL36XX_SDIV_MASK << PLL36XX_SDIV_SHIFT);
+
+	vpll_con1 = __raw_readl(EXYNOS4_VPLL_CON1);
+	vpll_con1 &= ~(0xffff << 0);
+
+	for (i = 0; i < ARRAY_SIZE(vpll_div_4212); i++) {
+		if (vpll_div_4212[i].rate == rate) {
+			vpll_con0 |= vpll_div_4212[i].pdiv << PLL36XX_PDIV_SHIFT;
+			vpll_con0 |= vpll_div_4212[i].mdiv << PLL36XX_MDIV_SHIFT;
+			vpll_con0 |= vpll_div_4212[i].sdiv << PLL36XX_SDIV_SHIFT;
+			vpll_con1 |= vpll_div_4212[i].k << 0;
+			break;
+		}
+	}
+
+	if (i == ARRAY_SIZE(vpll_div_4212)) {
+		printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
+				__func__);
+		return -EINVAL;
+	}
+
+	__raw_writel(vpll_con0, EXYNOS4_VPLL_CON0);
+	__raw_writel(vpll_con1, EXYNOS4_VPLL_CON1);
+
+	do {
+		vpll_con0 = __raw_readl(EXYNOS4_VPLL_CON0);
+	} while (!(vpll_con0 & 0x1 << EXYNOS4_VPLLCON0_LOCKED_SHIFT));
+
+	clk->rate = rate;
+
+	return 0;
+}
+#ifdef CONFIG_PM
+static int exynos4212_clock_suspend(void)
+{
+	s3c_pm_do_save(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
+	s3c_pm_do_save(exynos4212_vpll_save, ARRAY_SIZE(exynos4212_vpll_save));
+#if defined(CONFIG_MACH_M0) && defined(CONFIG_TARGET_LOCALE_EUR)
+	s3c_pm_do_save(exynos4212_epll_save, ARRAY_SIZE(exynos4212_epll_save));
+#endif
+
+	return 0;
+}
+
+static void exynos4212_clock_resume(void)
+{
+	unsigned int tmp;
+
+	s3c_pm_do_restore_core(exynos4212_vpll_save, ARRAY_SIZE(exynos4212_vpll_save));
+#if defined(CONFIG_MACH_M0) && defined(CONFIG_TARGET_LOCALE_EUR)
+	s3c_pm_do_restore_core(exynos4212_epll_save, ARRAY_SIZE(exynos4212_epll_save));
+#endif
+
+	/* waiting epll & vpll locking time */
+	do {
+		tmp = __raw_readl(EXYNOS4_EPLL_CON0);
+	} while (!(tmp & 0x1 << EXYNOS4_EPLLCON0_LOCKED_SHIFT));
+
+	do {
+		tmp = __raw_readl(EXYNOS4_VPLL_CON0);
+	} while (!(tmp & 0x1 << EXYNOS4_VPLLCON0_LOCKED_SHIFT));
+
+	s3c_pm_do_restore_core(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
+}
+#else
+#define exynos4212_clock_suspend NULL
+#define exynos4212_clock_resume NULL
+#endif
+
+struct syscore_ops exynos4212_clock_syscore_ops = {
+	.suspend	= exynos4212_clock_suspend,
+	.resume		= exynos4212_clock_resume,
+};
+
+void __init exynos4212_register_clocks(void)
+{
+	int ptr;
+	unsigned int tmp;
+
+	/* usbphy1 is removed in exynos 4212 */
+	exynos4_clkset_group_list[4] = NULL;
+
+	/* mout_mpll_user is used instead of mout_mpll in exynos 4212 */
+	exynos4_clkset_group_list[6] = &exynos4212_clk_mout_mpll_user.clk;
+	exynos4_clkset_aclk_top_list[0] = &exynos4212_clk_mout_mpll_user.clk;
+	exynos4_clkset_mout_mfc0_list[0] = &exynos4212_clk_mout_mpll_user.clk;
+
+	exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_DMC;
+	exynos4_clk_mout_mpll.reg_src.shift = 12;
+	exynos4_clk_mout_mpll.reg_src.size = 1;
+
+	exynos4_clk_aclk_200.sources = &exynos4212_clkset_aclk_200;
+	exynos4_clk_aclk_200.reg_src.reg = EXYNOS4_CLKSRC_TOP1;
+	exynos4_clk_aclk_200.reg_src.shift = 20;
+	exynos4_clk_aclk_200.reg_src.size = 1;
+
+	exynos4_clk_fimg2d.enable = exynos4_clk_ip_dmc_ctrl;
+	exynos4_clk_fimg2d.ctrlbit = (1 << 23);
+
+	exynos4_clk_mout_g2d0.reg_src.reg = EXYNOS4_CLKSRC_DMC;
+	exynos4_clk_mout_g2d0.reg_src.shift = 20;
+	exynos4_clk_mout_g2d0.reg_src.size = 1;
+
+	exynos4_clk_mout_g2d1.reg_src.reg = EXYNOS4_CLKSRC_DMC;
+	exynos4_clk_mout_g2d1.reg_src.shift = 24;
+	exynos4_clk_mout_g2d1.reg_src.size = 1;
+
+	exynos4_clk_sclk_fimg2d.reg_src.reg = EXYNOS4_CLKSRC_DMC;
+	exynos4_clk_sclk_fimg2d.reg_src.shift = 28;
+	exynos4_clk_sclk_fimg2d.reg_src.size = 1;
+	exynos4_clk_sclk_fimg2d.reg_div.reg = EXYNOS4_CLKDIV_DMC1;
+	exynos4_clk_sclk_fimg2d.reg_div.shift = 0;
+	exynos4_clk_sclk_fimg2d.reg_div.size = 4;
+
+	exynos4_epll_ops.get_rate = exynos4212_epll_get_rate;
+	exynos4_epll_ops.set_rate = exynos4212_epll_set_rate;
+	exynos4_vpll_ops.get_rate = exynos4212_vpll_get_rate;
+	exynos4_vpll_ops.set_rate = exynos4212_vpll_set_rate;
+
+	for (ptr = 0; ptr < ARRAY_SIZE(exynos4212_sysclks); ptr++)
+		s3c_register_clksrc(exynos4212_sysclks[ptr], 1);
+
+	s3c_register_clksrc(exynos4212_clksrcs, ARRAY_SIZE(exynos4212_clksrcs));
+	s3c_register_clocks(exynos4212_init_clocks, ARRAY_SIZE(exynos4212_init_clocks));
+
+	s3c_register_clocks(exynos4212_init_clocks_off, ARRAY_SIZE(exynos4212_init_clocks_off));
+	s3c_disable_clocks(exynos4212_init_clocks_off, ARRAY_SIZE(exynos4212_init_clocks_off));
+
+	s3c_register_clksrc(&exynos4212_clk_isp_srcs_div0, 1);
+	s3c_register_clksrc(exynos4212_clk_isp_srcs, ARRAY_SIZE(exynos4212_clk_isp_srcs));
+	s3c_register_clocks(exynos4212_clk_isp, ARRAY_SIZE(exynos4212_clk_isp));
+	s3c_disable_clocks(&exynos4212_clk_isp_srcs[3].clk, 1);
+	s3c_disable_clocks(&exynos4212_clk_isp_srcs[4].clk, 1);
+	s3c_disable_clocks(&exynos4212_clk_isp_srcs[5].clk, 1);
+	s3c_disable_clocks(&exynos4212_clk_isp_srcs[6].clk, 1);
+
+	/* To save power,
+	 * Disable CLKOUT of LEFTBUS, RIGHTBUS, TOP, DMC, CPU and ISP
+	 */
+	for (ptr = 0 ; ptr < ARRAY_SIZE(exynos4x12_cmu_config) ; ptr++) {
+		tmp = __raw_readl(exynos4x12_cmu_config[ptr].reg);
+		tmp &= ~(0x1 << 16);
+		tmp |= (exynos4x12_cmu_config[ptr].val << 16);
+		__raw_writel(tmp, exynos4x12_cmu_config[ptr].reg);
+	}
+
+	register_syscore_ops(&exynos4212_clock_syscore_ops);
+}
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
new file mode 100644
index 0000000..8ee9e42
--- /dev/null
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -0,0 +1,2921 @@
+/* linux/arch/arm/mach-exynos/clock-exynos5.c
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS5 - Clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/syscore_ops.h>
+
+#include <plat/cpu-freq.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/pll.h>
+#include <plat/s5p-clock.h>
+#include <plat/clock-clksrc.h>
+#include <plat/devs.h>
+#include <plat/pm.h>
+
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/regs-audss.h>
+#include <mach/sysmmu.h>
+#include <mach/exynos-clock.h>
+#include <mach/clock-domain.h>
+
+#ifdef CONFIG_PM
+static struct sleep_save exynos5_clock_save[] = {
+	/* CMU side */
+	SAVE_ITEM(EXYNOS5_CLKSRC_MASK_TOP),
+	SAVE_ITEM(EXYNOS5_CLKSRC_MASK_GSCL),
+	SAVE_ITEM(EXYNOS5_CLKSRC_MASK_DISP1_0),
+	SAVE_ITEM(EXYNOS5_CLKSRC_MASK_FSYS),
+	SAVE_ITEM(EXYNOS5_CLKSRC_MASK_MAUDIO),
+	SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC0),
+	SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC1),
+	SAVE_ITEM(EXYNOS5_CLKSRC_MASK_ISP),
+	SAVE_ITEM(EXYNOS5_CLKGATE_IP_SYSRGT),
+	SAVE_ITEM(EXYNOS5_CLKGATE_IP_ACP),
+	SAVE_ITEM(EXYNOS5_CLKGATE_ISP0),
+	SAVE_ITEM(EXYNOS5_CLKGATE_ISP1),
+	SAVE_ITEM(EXYNOS5_CLKGATE_SCLK_ISP),
+	SAVE_ITEM(EXYNOS5_CLKGATE_IP_GSCL),
+	SAVE_ITEM(EXYNOS5_CLKGATE_IP_DISP1),
+	SAVE_ITEM(EXYNOS5_CLKGATE_IP_MFC),
+	SAVE_ITEM(EXYNOS5_CLKGATE_IP_G3D),
+	SAVE_ITEM(EXYNOS5_CLKGATE_IP_GEN),
+	SAVE_ITEM(EXYNOS5_CLKGATE_IP_FSYS),
+	SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIC),
+	SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIS),
+	SAVE_ITEM(EXYNOS5_CLKGATE_IP_CDREX),
+	SAVE_ITEM(EXYNOS5_CLKGATE_BLOCK),
+	SAVE_ITEM(EXYNOS5_CLKDIV_ACP),
+	SAVE_ITEM(EXYNOS5_CLKDIV_ISP0),
+	SAVE_ITEM(EXYNOS5_CLKDIV_ISP1),
+	SAVE_ITEM(EXYNOS5_CLKDIV_ISP2),
+	SAVE_ITEM(EXYNOS5_CLKDIV_TOP0),
+	SAVE_ITEM(EXYNOS5_CLKDIV_TOP1),
+	SAVE_ITEM(EXYNOS5_CLKDIV_GSCL),
+	SAVE_ITEM(EXYNOS5_CLKDIV_DISP1_0),
+	SAVE_ITEM(EXYNOS5_CLKDIV_GEN),
+	SAVE_ITEM(EXYNOS5_CLKDIV_MAUDIO),
+	SAVE_ITEM(EXYNOS5_CLKDIV_FSYS0),
+	SAVE_ITEM(EXYNOS5_CLKDIV_FSYS1),
+	SAVE_ITEM(EXYNOS5_CLKDIV_FSYS2),
+	SAVE_ITEM(EXYNOS5_CLKDIV_FSYS3),
+	SAVE_ITEM(EXYNOS5_CLKDIV_PERIC0),
+	SAVE_ITEM(EXYNOS5_CLKDIV_PERIC1),
+	SAVE_ITEM(EXYNOS5_CLKDIV_PERIC2),
+	SAVE_ITEM(EXYNOS5_CLKDIV_PERIC3),
+	SAVE_ITEM(EXYNOS5_CLKDIV_PERIC4),
+	SAVE_ITEM(EXYNOS5_CLKDIV_PERIC5),
+	SAVE_ITEM(EXYNOS5_SCLK_DIV_ISP),
+	SAVE_ITEM(EXYNOS5_CLKDIV2_RATIO0),
+	SAVE_ITEM(EXYNOS5_CLKDIV2_RATIO1),
+	SAVE_ITEM(EXYNOS5_CLKDIV4_RATIO),
+	SAVE_ITEM(EXYNOS5_CLKSRC_TOP0),
+	SAVE_ITEM(EXYNOS5_CLKSRC_TOP1),
+	SAVE_ITEM(EXYNOS5_CLKSRC_TOP2),
+	SAVE_ITEM(EXYNOS5_CLKSRC_TOP3),
+	SAVE_ITEM(EXYNOS5_CLKSRC_GSCL),
+	SAVE_ITEM(EXYNOS5_CLKSRC_DISP1_0),
+	SAVE_ITEM(EXYNOS5_CLKSRC_MAUDIO),
+	SAVE_ITEM(EXYNOS5_CLKSRC_FSYS),
+	SAVE_ITEM(EXYNOS5_CLKSRC_PERIC0),
+	SAVE_ITEM(EXYNOS5_CLKSRC_PERIC1),
+	SAVE_ITEM(EXYNOS5_SCLK_SRC_ISP),
+#ifdef CONFIG_EXYNOS5_ENABLE_CLOCK_DOWN
+	SAVE_ITEM(EXYNOS5_PWR_CTRL1),
+	SAVE_ITEM(EXYNOS5_PWR_CTRL2),
+#endif
+};
+
+static struct sleep_save exynos5_epll_save[] = {
+	SAVE_ITEM(EXYNOS5_EPLL_LOCK),
+	SAVE_ITEM(EXYNOS5_EPLL_CON0),
+	SAVE_ITEM(EXYNOS5_EPLL_CON1),
+	SAVE_ITEM(EXYNOS5_EPLL_CON2),
+};
+
+static struct sleep_save exynos5_vpll_save[] = {
+	SAVE_ITEM(EXYNOS5_VPLL_LOCK),
+	SAVE_ITEM(EXYNOS5_VPLL_CON0),
+	SAVE_ITEM(EXYNOS5_VPLL_CON1),
+	SAVE_ITEM(EXYNOS5_VPLL_CON2),
+#ifdef CONFIG_EXYNOS5_ENABLE_CLOCK_DOWN
+	SAVE_ITEM(EXYNOS5_PWR_CTRL1),
+	SAVE_ITEM(EXYNOS5_PWR_CTRL2),
+#endif
+};
+
+static struct sleep_save exynos5_gpll_save[] = {
+	SAVE_ITEM(EXYNOS5_GPLL_LOCK),
+	SAVE_ITEM(EXYNOS5_GPLL_CON0),
+	SAVE_ITEM(EXYNOS5_GPLL_CON1),
+};
+
+static struct sleep_save exynos5250_clock_save_rev0[] = {
+	SAVE_ITEM(EXYNOS5_CLKGATE_IP_GPS),
+};
+
+#endif
+
+static struct clk exynos5_clk_sclk_hdmi24m = {
+	.name		= "sclk_hdmi24m",
+	.rate		= 24000000,
+};
+
+static struct clk exynos5_clk_sclk_hdmi27m = {
+	.name		= "sclk_hdmi27m",
+	.rate		= 27000000,
+};
+
+static struct clk exynos5_clk_sclk_hdmiphy = {
+	.name		= "sclk_hdmiphy",
+};
+
+static struct clk exynos5_clk_sclk_dptxphy = {
+	.name		= "sclk_dptx",
+};
+
+static struct clk exynos5_clk_sclk_usbphy = {
+	.name		= "sclk_usbphy",
+	.rate		= 48000000,
+};
+
+struct clksrc_clk exynos5_clk_audiocdclk0 = {
+	.clk	= {
+		.name		= "audiocdclk",
+		.rate		= 16934400,
+	},
+};
+
+static struct clk exynos5_clk_audiocdclk1 = {
+	.name           = "audiocdclk",
+};
+
+static struct clk exynos5_clk_audiocdclk2 = {
+	.name		= "audiocdclk",
+};
+
+static struct clk exynos5_clk_spdifcdclk = {
+	.name		= "spdifcdclk",
+};
+
+static int exynos5_clksrc_mask_top_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_TOP, clk, enable);
+}
+
+static int exynos5_clk_ip_core_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CORE, clk, enable);
+}
+
+static int exynos5_clk_ip_sysrgt_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_SYSRGT, clk, enable);
+}
+
+static int exynos5_clk_ip_cpu_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CPU, clk, enable);
+}
+
+static int exynos5_clk_ip_gps_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GPS, clk, enable);
+}
+
+static int exynos5_clk_ip_peric_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIC, clk, enable);
+}
+
+static int exynos5_clk_ip_peris_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIS, clk, enable);
+}
+
+static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
+}
+
+static int exynos5_clksrc_mask_peric1_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC1, clk, enable);
+}
+
+static int exynos5_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_FSYS, clk, enable);
+}
+
+static int exynos5_clk_ip_fsys_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_FSYS, clk, enable);
+}
+
+static int exynos5_clk_ip_disp1_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_DISP1, clk, enable);
+}
+
+static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);
+}
+
+static int exynos5_clk_ip_g3d_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_G3D, clk, enable);
+}
+
+static int exynos5_clk_hdmiphy_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
+}
+
+static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable);
+}
+
+static int exynos5_clksrc_mask_disp1_0_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_DISP1_0, clk, enable);
+}
+
+static int exynos5_clksrc_mask_maudio_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_MAUDIO, clk, enable);
+}
+
+static int exynos5_clk_audss_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(S5P_CLKGATE_AUDSS, clk, enable);
+}
+
+static int exynos5_clk_ip_gscl_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GSCL, clk, enable);
+}
+
+static int exynos5_clksrc_mask_gscl_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_GSCL, clk, enable);
+}
+
+static int exynos5_clksrc_mask_gen_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_GEN, clk, enable);
+}
+
+static int exynos5_clk_gate_block(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_BLOCK, clk, enable);
+}
+
+static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable);
+}
+
+static int exynos5_clk_ip_isp0_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_ISP0, clk, enable);
+}
+
+static int exynos5_clk_ip_isp1_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_ISP1, clk, enable);
+}
+
+static int exynos5_clk_clkout_cpu_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKOUT_CMU_CPU, clk, enable);
+}
+
+static int exynos5_clk_clkout_core_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKOUT_CMU_CORE, clk, enable);
+}
+
+static int exynos5_clk_clkout_acp_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKOUT_CMU_ACP, clk, enable);
+}
+
+static int exynos5_clk_clkout_isp_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKOUT_CMU_ISP, clk, enable);
+}
+
+static int exynos5_clk_clkout_top_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKOUT_CMU_TOP, clk, enable);
+}
+
+static int exynos5_clk_clkout_lex_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKOUT_CMU_LEX, clk, enable);
+}
+
+static int exynos5_clk_clkout_r0x_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKOUT_CMU_R0X, clk, enable);
+}
+
+static int exynos5_clk_clkout_r1x_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKOUT_CMU_R1X, clk, enable);
+}
+
+static int exynos5_clk_clkout_cdrex_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKOUT_CMU_CDREX, clk, enable);
+}
+
+/* BPLL clock output
+ * No need .ctrlbit, this is always on
+*/
+static struct clk clk_fout_bpll = {
+	.name		= "fout_bpll",
+	.id		= -1,
+};
+
+/* MOUT_BPLL_FOUT
+ * No need .ctrlbit, this is always on
+*/
+static struct clk clk_fout_bpll_div2 = {
+	.name		= "fout_bpll_div2",
+	.id		= -1,
+};
+
+/* MOUT_MPLL_FOUT
+ * No need .ctrlbit, this is always on
+*/
+static struct clk clk_fout_mpll_div2 = {
+	.name		= "fout_mpll_div2",
+	.id		= -1,
+};
+
+/* Possible clock sources for BPLL Mux */
+static struct clk *clk_src_bpll_list[] = {
+	[0] = &clk_fin_bpll,
+	[1] = &clk_fout_bpll,
+};
+
+static struct clksrc_sources clk_src_bpll = {
+	.sources	= clk_src_bpll_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_bpll_list),
+};
+
+/* Possible clock source for BPLL_FOUT Mux */
+static struct clk *exynos5_clkset_mout_bpll_fout_list[] = {
+	[0] = &clk_fout_bpll_div2,
+	[1] = &clk_fout_bpll,
+};
+
+static struct clksrc_sources exynos5_clkset_mout_bpll_fout = {
+	.sources	= exynos5_clkset_mout_bpll_fout_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_mout_bpll_fout_list),
+};
+
+/* GPLL clock output */
+static struct clk clk_fout_gpll = {
+	.name		= "fout_gpll",
+	.id		= -1,
+};
+
+/* Possible clock sources for GPLL Mux */
+static struct clk *clk_src_gpll_list[] = {
+	[0] = &clk_fin_gpll,
+	[1] = &clk_fout_gpll,
+};
+
+static struct clksrc_sources clk_src_gpll = {
+	.sources	= clk_src_gpll_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_gpll_list),
+};
+
+/* CPLL clock output */
+static struct clk clk_fout_cpll = {
+	.name		= "fout_cpll",
+	.id		= -1,
+};
+
+/* Possible clock sources for CPLL Mux */
+static struct clk *clk_src_cpll_list[] = {
+	[0] = &clk_fin_cpll,
+	[1] = &clk_fout_cpll,
+};
+
+static struct clksrc_sources clk_src_cpll = {
+	.sources	= clk_src_cpll_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_cpll_list),
+};
+
+/* Possible clock source for MPLL_FOUT Mux */
+static struct clk *exynos5_clkset_mout_mpll_fout_list[] = {
+	[0] = &clk_fout_mpll_div2,
+	[1] = &clk_fout_mpll,
+};
+
+static struct clksrc_sources exynos5_clkset_mout_mpll_fout = {
+	.sources	= exynos5_clkset_mout_mpll_fout_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_mout_mpll_fout_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_mpll_fout = {
+	.clk	= {
+		.name		= "mout_mpll_fout",
+	},
+	.sources = &exynos5_clkset_mout_mpll_fout,
+	.reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 4, .size = 1 },
+};
+
+/* Possible clock source for MPLL Mux */
+static struct clk *exynos5_clkset_mout_mpll_list[] = {
+	[0] = &clk_fin_mpll,
+	[1] = &exynos5_clk_mout_mpll_fout.clk,
+};
+
+static struct clksrc_sources exynos5_clkset_mout_mpll = {
+	.sources	= exynos5_clkset_mout_mpll_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_mout_mpll_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_bpll_fout = {
+	.clk	= {
+		.name		= "mout_bpll_fout",
+	},
+	.sources = &exynos5_clkset_mout_bpll_fout,
+	.reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 0, .size = 1 },
+};
+
+/* Possible clock source for BPLL Mux */
+static struct clk *exynos5_clkset_mout_bpll_list[] = {
+	[0] = &clk_fin_bpll,
+	[1] = &exynos5_clk_mout_bpll_fout.clk,
+};
+
+static struct clksrc_sources exynos5_clkset_mout_bpll = {
+	.sources	= exynos5_clkset_mout_bpll_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_mout_bpll_list),
+};
+
+/* Core list of CMU_CPU side */
+static struct clksrc_clk exynos5_clk_mout_apll = {
+	.clk	= {
+		.name		= "mout_apll",
+	},
+	.sources = &clk_src_apll,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 0, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_apll = {
+	.clk	= {
+		.name		= "sclk_apll",
+		.parent		= &exynos5_clk_mout_apll.clk,
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_mout_bpll = {
+	.clk	= {
+		.name		= "mout_bpll",
+	},
+	.sources = &clk_src_bpll,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_mout_gpll = {
+	.clk	= {
+		.name		= "mout_gpll",
+	},
+	.sources = &clk_src_gpll,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 24, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_mout_cpll = {
+	.clk	= {
+		.name		= "mout_cpll",
+	},
+	.sources = &clk_src_cpll,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 8, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_mout_epll = {
+	.clk	= {
+		.name		= "mout_epll",
+	},
+	.sources = &clk_src_epll,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
+};
+
+struct clksrc_clk exynos5_clk_mout_mpll = {
+	.clk = {
+		.name		= "mout_mpll",
+	},
+	.sources = &clk_src_mpll,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
+};
+
+/* CMU_ACP */
+static struct clksrc_clk exynos5_clk_aclk_acp = {
+	.clk    = {
+		.name		= "aclk_acp",
+		.parent		= &exynos5_clk_mout_mpll.clk,
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_pclk_acp = {
+	.clk    = {
+		.name		= "pclk_acp",
+		.parent		= &exynos5_clk_aclk_acp.clk,
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 4, .size = 3 },
+};
+
+/* For VPLL */
+static struct clk *exynos5_clkset_mout_vpllsrc_list[] = {
+	[0] = &clk_fin_vpll,
+	[1] = &exynos5_clk_sclk_hdmi27m,
+};
+
+static struct clksrc_sources exynos5_clkset_mout_vpllsrc = {
+	.sources	= exynos5_clkset_mout_vpllsrc_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_mout_vpllsrc_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_vpllsrc = {
+	.clk	= {
+		.name		= "vpll_src",
+		.enable		= exynos5_clksrc_mask_top_ctrl,
+		.ctrlbit	= (1 << 0),
+	},
+	.sources = &exynos5_clkset_mout_vpllsrc,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos5_clkset_sclk_vpll_list[] = {
+	[0] = &exynos5_clk_mout_vpllsrc.clk,
+	[1] = &clk_fout_vpll,
+};
+
+static struct clksrc_sources exynos5_clkset_sclk_vpll = {
+	.sources	= exynos5_clkset_sclk_vpll_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_sclk_vpll_list),
+};
+
+static struct clksrc_clk exynos5_clk_sclk_vpll = {
+	.clk	= {
+		.name		= "sclk_vpll",
+	},
+	.sources = &exynos5_clkset_sclk_vpll,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 16, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_pixel = {
+	.clk	= {
+		.name		= "sclk_pixel",
+		.parent		= &exynos5_clk_sclk_vpll.clk,
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 28, .size = 4 },
+};
+
+static struct clk *exynos5_clkset_sclk_hdmi_list[] = {
+	[0] = &exynos5_clk_sclk_pixel.clk,
+	[1] = &exynos5_clk_sclk_hdmiphy,
+};
+
+static struct clksrc_sources exynos5_clkset_sclk_hdmi = {
+	.sources	= exynos5_clkset_sclk_hdmi_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_sclk_hdmi_list),
+};
+
+static struct clksrc_clk exynos5_clk_sclk_hdmi = {
+	.clk	= {
+		.name           = "sclk_hdmi",
+		.enable		= exynos5_clksrc_mask_disp1_0_ctrl,
+		.ctrlbit	= (1 << 20),
+	},
+	.sources = &exynos5_clkset_sclk_hdmi,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 20, .size = 1 },
+};
+
+static struct clk *exynos5_clkset_sclk_cec_list[] = {
+	[0] = &exynos5_clk_sclk_pixel.clk,
+	[1] = &exynos5_clk_sclk_hdmiphy,
+};
+
+static struct clksrc_sources exynos5_clkset_sclk_cec = {
+	.sources	= exynos5_clkset_sclk_cec_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_sclk_cec_list),
+};
+
+static struct clksrc_clk exynos5_clk_sclk_cec = {
+	.clk	= {
+		.name           = "sclk_cec",
+		.enable		= exynos5_clksrc_mask_disp1_0_ctrl,
+		.ctrlbit	= (1 << 20),
+	},
+	.sources = &exynos5_clkset_sclk_cec,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 20, .size = 1 },
+};
+
+static struct clksrc_clk *exynos5_sclk_tv[] = {
+	&exynos5_clk_sclk_pixel,
+	&exynos5_clk_sclk_hdmi,
+	&exynos5_clk_sclk_cec,
+};
+
+/* BPLL USER */
+static struct clk *exynos5_clk_src_bpll_user_list[] = {
+	[0] = &clk_fin_mpll,
+	[1] = &exynos5_clk_mout_bpll.clk,
+};
+
+static struct clksrc_sources exynos5_clk_src_bpll_user = {
+	.sources	= exynos5_clk_src_bpll_user_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clk_src_bpll_user_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_bpll_user = {
+	.clk	= {
+		.name		= "mout_bpll_user",
+	},
+	.sources = &exynos5_clk_src_bpll_user,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 24, .size = 1 },
+};
+
+/* MPLL USER */
+static struct clk *exynos5_clk_src_mpll_user_list[] = {
+	[0] = &clk_fin_mpll,
+	[1] = &exynos5_clk_mout_mpll.clk,
+};
+
+static struct clksrc_sources exynos5_clk_src_mpll_user = {
+	.sources	= exynos5_clk_src_mpll_user_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clk_src_mpll_user_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_mpll_user = {
+	.clk	= {
+		.name		= "mout_mpll_user",
+	},
+	.sources = &exynos5_clk_src_mpll_user,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 20, .size = 1 },
+};
+
+static struct clk *exynos5_clkset_mout_cpu_list[] = {
+	[0] = &exynos5_clk_mout_apll.clk,
+	[1] = &exynos5_clk_mout_mpll.clk,
+};
+
+static struct clksrc_sources exynos5_clkset_mout_cpu = {
+	.sources	= exynos5_clkset_mout_cpu_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_mout_cpu_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_cpu = {
+	.clk	= {
+		.name		= "moutcpu",
+	},
+	.sources = &exynos5_clkset_mout_cpu,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 16, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_armclk = {
+	.clk	= {
+		.name		= "dout_arm_clk",
+		.parent		= &exynos5_clk_mout_cpu.clk,
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_arm2clk = {
+	.clk	= {
+		.name		= "dout_arm_clk",
+		.parent		= &exynos5_clk_dout_armclk.clk,
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 28, .size = 3 },
+};
+
+static struct clk exynos5_clk_armclk = {
+	.name		= "armclk",
+	.parent		= &exynos5_clk_dout_arm2clk.clk,
+};
+
+/* Core list of CMU_CDREX side */
+
+static struct clk *exynos5_clkset_cdrex_list[] = {
+	[0] = &exynos5_clk_mout_mpll.clk,
+	[1] = &exynos5_clk_mout_bpll.clk,
+};
+
+static struct clksrc_sources exynos5_clkset_mclk_cdrex = {
+	.sources	= exynos5_clkset_cdrex_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_cdrex_list),
+};
+
+static struct clksrc_clk exynos5_clk_mclk_cdrex = {
+	.clk	= {
+		.name		= "mclk_cdrex",
+	},
+	.sources = &exynos5_clkset_mclk_cdrex,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 8, .size = 1 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_CDREX, .shift = 28, .size = 3 },
+};
+
+/* Core list of CMU_TOP side */
+
+struct clk *exynos5_clkset_aclk_top_list[] = {
+	[0] = &exynos5_clk_mout_mpll_user.clk,
+	[1] = &exynos5_clk_mout_bpll_user.clk,
+};
+
+struct clksrc_sources exynos5_clkset_aclk = {
+	.sources	= exynos5_clkset_aclk_top_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_aclk_top_list),
+};
+
+/* For ACLK_400_G3D_MID */
+static struct clksrc_clk exynos5_clk_aclk_400_g3d_mid = {
+	.clk	= {
+		.name		= "aclk_400_g3d_mid",
+	},
+	.sources = &exynos5_clkset_aclk,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
+};
+
+/* For ACLK_400_G3D */
+struct clk *exynos5_clkset_aclk_g3d_list[] = {
+	[0] = &exynos5_clk_aclk_400_g3d_mid.clk,
+	[1] = &exynos5_clk_mout_gpll.clk,
+};
+
+struct clksrc_sources exynos5_clkset_aclk_g3d = {
+	.sources	= exynos5_clkset_aclk_g3d_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_aclk_g3d_list),
+};
+
+static struct clksrc_clk exynos5_clk_aclk_400 = {
+	.clk	= {
+		.name		= "aclk_400",
+	},
+	.sources = &exynos5_clkset_aclk,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP1, .shift = 28, .size = 1 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
+};
+
+/* For ACLK_333 */
+struct clk *exynos5_clkset_mout_aclk_333_166_list[] = {
+	[0] = &exynos5_clk_mout_cpll.clk,
+	[1] = &exynos5_clk_mout_mpll_user.clk,
+};
+
+struct clksrc_sources exynos5_clkset_mout_aclk_333_166 = {
+	.sources	= exynos5_clkset_mout_aclk_333_166_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_mout_aclk_333_166_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_aclk_333 = {
+	.clk	= {
+		.name		= "mout_aclk_333",
+	},
+	.sources = &exynos5_clkset_mout_aclk_333_166,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 16, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_aclk_333 = {
+	.clk	= {
+		.name		= "dout_aclk_333",
+		.parent		= &exynos5_clk_mout_aclk_333.clk,
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 20, .size = 3 },
+};
+
+struct clk *exynos5_clkset_aclk_333_sub_list[] = {
+	[0] = &clk_ext_xtal_mux,
+	[1] = &exynos5_clk_dout_aclk_333.clk,
+};
+
+struct clksrc_sources exynos5_clkset_aclk_333_sub = {
+	.sources	= exynos5_clkset_aclk_333_sub_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_aclk_333_sub_list),
+};
+
+static struct clksrc_clk exynos5_clk_aclk_333 = {
+	.clk	= {
+		.name		= "aclk_333",
+	},
+	.sources = &exynos5_clkset_aclk_333_sub,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 24, .size = 1 },
+};
+
+/* For ACLK_300_disp1_mid */
+static struct clksrc_clk exynos5_clk_mout_aclk_300_disp1_mid = {
+	.clk	= {
+		.name		= "mout_aclk_300_disp1_mid",
+	},
+	.sources = &exynos5_clkset_aclk,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 14, .size = 1 },
+};
+
+static struct clk *clk_src_mid1_list[] = {
+	[0] = &exynos5_clk_sclk_vpll.clk,
+	[1] = &exynos5_clk_mout_cpll.clk,
+};
+
+static struct clksrc_sources exynos5_clkset_mid1 = {
+	.sources	= clk_src_mid1_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_mid1_list),
+};
+
+/* For ACLK_300_disp1_mid1 */
+static struct clksrc_clk exynos5_clk_mout_aclk_300_disp1_mid1 = {
+	.clk	= {
+		.name		= "mout_aclk_300_disp1_mid1",
+	},
+	.sources = &exynos5_clkset_mid1,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP1, .shift = 8, .size = 1 },
+};
+
+/* For ACLK_300_disp1 */
+struct clk *exynos5_clkset_mout_aclk_300_disp1_list[] = {
+	[0] = &exynos5_clk_mout_aclk_300_disp1_mid.clk,
+	[1] = &exynos5_clk_sclk_vpll.clk,
+};
+
+struct clksrc_sources exynos5_clkset_mout_aclk_300_disp1 = {
+	.sources	= exynos5_clkset_mout_aclk_300_disp1_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_mout_aclk_300_disp1_list),
+};
+
+struct clk *exynos5_clkset_mout_aclk_300_disp1_rev1_list[] = {
+	[0] = &exynos5_clk_mout_aclk_300_disp1_mid.clk,
+	[1] = &exynos5_clk_mout_aclk_300_disp1_mid1.clk,
+};
+
+struct clksrc_sources exynos5_clkset_mout_aclk_300_disp1_rev1 = {
+	.sources	= exynos5_clkset_mout_aclk_300_disp1_rev1_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_mout_aclk_300_disp1_rev1_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_aclk_300_disp1 = {
+	.clk	= {
+		.name		= "mout_aclk_300_disp1",
+	},
+	.sources = &exynos5_clkset_mout_aclk_300_disp1,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 15, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_aclk_300_disp1 = {
+	.clk	= {
+		.name		= "dout_aclk_300_disp1",
+		.parent		= &exynos5_clk_mout_aclk_300_disp1.clk,
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 28, .size = 3 },
+};
+
+static struct clk *clk_src_aclk_300_disp1_list[] = {
+	[0] = &clk_ext_xtal_mux,
+	[1] = &exynos5_clk_dout_aclk_300_disp1.clk,
+};
+
+static struct clksrc_sources exynos5_clkset_aclk_300_disp1 = {
+	.sources	= clk_src_aclk_300_disp1_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_aclk_300_disp1_list),
+};
+
+static struct clksrc_clk exynos5_clk_aclk_300_disp1 = {
+	.clk	= {
+		.name		= "aclk_300_disp1",
+	},
+	.sources = &exynos5_clkset_aclk_300_disp1,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 6, .size = 1 },
+};
+
+/* For ACLK_300_gscl_mid */
+static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid = {
+	.clk	= {
+		.name		= "mout_aclk_300_gscl_mid",
+	},
+	.sources = &exynos5_clkset_aclk,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 24, .size = 1 },
+};
+
+/* For ACLK_300_gscl_mid1 */
+static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid1 = {
+	.clk	= {
+		.name		= "mout_aclk_300_gscl_mid1",
+	},
+	.sources = &exynos5_clkset_mid1,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP1, .shift = 12, .size = 1 },
+};
+
+/* For ACLK_300_gscl */
+struct clk *exynos5_clkset_aclk_300_gscl_list[] = {
+	[0] = &exynos5_clk_mout_aclk_300_gscl_mid.clk,
+	[1] = &exynos5_clk_sclk_vpll.clk,
+};
+
+struct clksrc_sources exynos5_clkset_aclk_300_gscl = {
+	.sources	= exynos5_clkset_aclk_300_gscl_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_aclk_300_gscl_list),
+};
+
+struct clk *exynos5_clkset_aclk_300_gscl_rev1_list[] = {
+	[0] = &exynos5_clk_mout_aclk_300_gscl_mid.clk,
+	[1] = &exynos5_clk_mout_aclk_300_gscl_mid1.clk,
+};
+
+struct clksrc_sources exynos5_clkset_aclk_300_gscl_rev1 = {
+	.sources	= exynos5_clkset_aclk_300_gscl_rev1_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_aclk_300_gscl_rev1_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl = {
+	.clk	= {
+		.name		= "mout_aclk_300_gscl",
+	},
+	.sources = &exynos5_clkset_aclk_300_gscl,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 25, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_aclk_300_gscl = {
+	.clk	= {
+		.name		= "dout_aclk_300_gscl",
+		.parent		= &exynos5_clk_mout_aclk_300_gscl.clk,
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 12, .size = 3 },
+};
+
+/* Possible clock sources for aclk_300_gscl_sub Mux */
+static struct clk *clk_src_gscl_300_list[] = {
+	[0] = &clk_ext_xtal_mux,
+	[1] = &exynos5_clk_dout_aclk_300_gscl.clk,
+};
+
+static struct clksrc_sources clk_src_gscl_300 = {
+	.sources	= clk_src_gscl_300_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_gscl_300_list),
+};
+
+static struct clksrc_clk exynos5_clk_aclk_300_gscl = {
+	.clk	= {
+		.name		= "aclk_300_gscl",
+	},
+	.sources = &clk_src_gscl_300,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 10, .size = 1 },
+};
+
+/* For ACLK_266 */
+static struct clksrc_clk exynos5_clk_aclk_266 = {
+	.clk	= {
+		.name		= "aclk_266",
+		.parent		= &exynos5_clk_mout_mpll_user.clk,
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 16, .size = 3 },
+};
+
+/* For ACLK_200 */
+static struct clksrc_clk exynos5_clk_aclk_200 = {
+	.clk	= {
+		.name		= "aclk_200",
+	},
+	.sources = &exynos5_clkset_aclk,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 12, .size = 1 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 12, .size = 3 },
+};
+
+/* For ACLK_166 */
+static struct clksrc_clk exynos5_clk_aclk_166 = {
+	.clk	= {
+		.name		= "aclk_166",
+	},
+	.sources = &exynos5_clkset_mout_aclk_333_166,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 8, .size = 1 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 8, .size = 3 },
+};
+
+/* For ACLK_66 */
+static struct clksrc_clk exynos5_clk_dout_aclk_66_pre = {
+	.clk	= {
+		.name		= "aclk_66_pre",
+		.parent		= &exynos5_clk_mout_mpll_user.clk,
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 24, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_66 = {
+	.clk	= {
+		.name		= "aclk_66",
+		.parent		= &exynos5_clk_dout_aclk_66_pre.clk,
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 0, .size = 3 },
+};
+
+static struct clk *clk_src_aclk_200_disp1_list[] = {
+	[0] = &clk_ext_xtal_mux,
+	[1] = &exynos5_clk_aclk_200.clk,
+};
+
+static struct clksrc_sources exynos5_clkset_aclk_200_disp1 = {
+	.sources	= clk_src_aclk_200_disp1_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_aclk_200_disp1_list),
+};
+
+static struct clksrc_clk exynos5_clk_aclk_200_disp1 = {
+	.clk	= {
+		.name		= "aclk_200_disp1",
+	},
+	.sources = &exynos5_clkset_aclk_200_disp1,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 4, .size = 1 },
+};
+
+static struct clk exynos5_init_clocks[] = {
+	{
+		.name		= "uart",
+		.devname	= "s5pv210-uart.0",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 0),
+	}, {
+		.name		= "uart",
+		.devname	= "s5pv210-uart.1",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 1),
+	}, {
+		.name		= "uart",
+		.devname	= "s5pv210-uart.2",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 2),
+	}, {
+		.name		= "uart",
+		.devname	= "s5pv210-uart.3",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 3),
+	}, {
+		.name		= "uart",
+		.devname	= "s5pv210-uart.4",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 4),
+	}, {
+		.name		= "uart",
+		.devname	= "s5pv210-uart.5",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 5),
+	},
+};
+
+
+/* TN Feature.. these clocks was enabled at booloader */
+
+static struct clk exynos5_init_clock_on[] = {
+	{
+		.name		= "timers",
+		.parent		= &exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1<<24),
+	}, {
+		.name		= "lcd",
+		.devname	= "s3cfb.1",
+		.enable		= exynos5_clk_ip_disp1_ctrl,
+		.ctrlbit	= ((0x7 << 10) | (1 << 0)),
+	}, {
+		.name		= "dp",
+		.devname	= "s5p-dp",
+		.enable		= exynos5_clk_ip_disp1_ctrl,
+		.ctrlbit	= (1 << 4),
+	},
+};
+
+static struct clk exynos5_init_clocks_off[] = {
+	 {
+		.name		= "watchdog",
+		.enable		= exynos5_clk_ip_peris_ctrl,
+		.ctrlbit	= (1 << 19),
+	}, {
+		.name		= "hdmicec",
+		.enable		= exynos5_clk_ip_peris_ctrl,
+		.ctrlbit	= (1 << 16),
+	}, {
+		.name		= "rtc",
+		.parent		= &exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peris_ctrl,
+		.ctrlbit	= (1<<20),
+	}, {
+		.name		= "hsmmc",
+		.devname	= "s3c-sdhci.0",
+		.parent		= &exynos5_clk_aclk_200.clk,
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 12),
+	}, {
+		.name		= "hsmmc",
+		.devname	= "s3c-sdhci.1",
+		.parent		= &exynos5_clk_aclk_200.clk,
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 13),
+	}, {
+		.name		= "hsmmc",
+		.devname	= "s3c-sdhci.2",
+		.parent		= &exynos5_clk_aclk_200.clk,
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 14),
+	}, {
+		.name		= "hsmmc",
+		.devname	= "s3c-sdhci.3",
+		.parent		= &exynos5_clk_aclk_200.clk,
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 15),
+	}, {
+		.name		= "dwmci",
+		.parent		= &exynos5_clk_aclk_200.clk,
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 16),
+	}, {
+		.name		= "sata",
+		.devname	= "ahci",
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 6),
+	}, {
+		.name		= "sata_phy",
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 24),
+	}, {
+		.name		= "sata_phy_i2c",
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 25),
+	}, {
+		.name		= "usbdrd30",
+		.parent		= &exynos5_clk_aclk_200.clk,
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 19),
+	}, {
+		.name		= "mfc",
+		.devname	= "s3c-mfc",
+		.enable		= exynos5_clk_ip_mfc_ctrl,
+		.ctrlbit	= ((1 << 4) | (1 << 3) | (1 << 0)),
+	}, {
+		.name		= "g3d",
+		.enable		= exynos5_clk_ip_g3d_ctrl,
+		.ctrlbit	= ((1 << 1) | (1 << 0)),
+	}, {
+		.name		= "g3d",
+		.enable		= exynos5_clk_ip_g3d_ctrl,
+		.ctrlbit	= ((1 << 1) | (1 << 0)),
+	}, {
+		.name		= "isp0",
+		.devname	= "exynos5-fimc-is",
+		.enable		= exynos5_clk_ip_isp0_ctrl,
+		.ctrlbit	= (0xDFFFC0FF << 0),
+	}, {
+		.name		= "isp1",
+		.devname	= "exynos5-fimc-is",
+		.enable		= exynos5_clk_ip_isp1_ctrl,
+		.ctrlbit	= (0x3F07 << 0),
+	}, {
+		.name		= "hdmi",
+		.devname	= "exynos5-hdmi",
+		.enable		= exynos5_clk_ip_disp1_ctrl,
+		.ctrlbit	= (1 << 6),
+	}, {
+		.name		= "mixer",
+		.devname	= "s5p-mixer",
+		.enable		= exynos5_clk_ip_disp1_ctrl,
+		.ctrlbit	= ((0x3 << 13) | (1 << 5)),
+	}, {
+		.name       = "hdmiphy",
+		.devname	= "exynos5-hdmi",
+		.enable     = exynos5_clk_hdmiphy_ctrl,
+		.ctrlbit    = (1 << 0),
+	}, {
+		.name		= "gscl",
+		.devname	= "exynos-gsc.0",
+		.enable		= exynos5_clk_ip_gscl_ctrl,
+		.ctrlbit	= ((1 << 15) | (1 << 0)),
+	}, {
+		.name		= "gscl",
+		.devname	= "exynos-gsc.1",
+		.enable		= exynos5_clk_ip_gscl_ctrl,
+		.ctrlbit	= ((1 << 16) | (1 << 1)),
+	}, {
+		.name		= "gscl",
+		.devname	= "exynos-gsc.2",
+		.enable		= exynos5_clk_ip_gscl_ctrl,
+		.ctrlbit	= ((1 << 17) | (1 << 2)),
+	}, {
+		.name		= "gscl",
+		.devname	= "exynos-gsc.3",
+		.enable		= exynos5_clk_ip_gscl_ctrl,
+		.ctrlbit	= ((1 << 18) | (1 << 3)),
+	}, {
+		.name		= "camif_top",
+		.enable		= exynos5_clk_ip_gscl_ctrl,
+		.ctrlbit	= (1 << 4),
+	}, {
+		.name		= "gscl_wrap0",
+		.devname	= "s5p-mipi-csis.0",
+		.enable		= exynos5_clk_ip_gscl_ctrl,
+		.ctrlbit	= (1 << 5),
+	}, {
+		.name		= "gscl_wrap1",
+		.devname	= "s5p-mipi-csis.1",
+		.enable		= exynos5_clk_ip_gscl_ctrl,
+		.ctrlbit	= (1 << 6),
+	}, {
+		.name		= "rotator",
+		.devname	= "exynos-rot",
+		.enable		= exynos5_clk_ip_gen_ctrl,
+		.ctrlbit	= ((1 << 11) | (1 << 1)),
+	}, {
+		.name		= "jpeg",
+		.enable		= exynos5_clk_ip_gen_ctrl,
+		.ctrlbit	= ((1 << 12) | (1 << 2)),
+	}, {
+		.name		= "dsim0",
+		.enable		= exynos5_clk_ip_disp1_ctrl,
+		.ctrlbit	= (1 << 3),
+	}, {
+		.name		= "iis",
+		.devname	= "samsung-i2s.1",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 20),
+	}, {
+		.name		= "iis",
+		.devname	= "samsung-i2s.2",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 21),
+	}, {
+		.name		= "pcm",
+		.devname	= "samsung-pcm.1",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 22),
+	}, {
+		.name		= "pcm",
+		.devname	= "samsung-pcm.2",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 23),
+	}, {
+		.name		= "spdif",
+		.devname	= "samsung-spdif",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 26),
+	}, {
+		.name		= "ac97",
+		.devname	= "samsung-ac97",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 27),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(mfc_lr, 0),
+		.enable		= &exynos5_clk_ip_mfc_ctrl,
+		.ctrlbit	= (3 << 1),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(tv, 2),
+		.enable		= &exynos5_clk_ip_disp1_ctrl,
+		.ctrlbit	= (1 << 9)
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(jpeg, 3),
+		.enable		= &exynos5_clk_ip_gen_ctrl,
+		.ctrlbit	= (1 << 7),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(rot, 4),
+		.enable		= &exynos5_clk_ip_gen_ctrl,
+		.ctrlbit	= (1 << 6)
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(gsc0, 5),
+		.enable		= &exynos5_clk_ip_gscl_ctrl,
+		.ctrlbit	= (1 << 7),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(gsc1, 6),
+		.enable		= &exynos5_clk_ip_gscl_ctrl,
+		.ctrlbit	= (1 << 8),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(gsc2, 7),
+		.enable		= &exynos5_clk_ip_gscl_ctrl,
+		.ctrlbit	= (1 << 9),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(gsc3, 8),
+		.enable		= &exynos5_clk_ip_gscl_ctrl,
+		.ctrlbit	= (1 << 10),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(isp, 9),
+		.enable		= &exynos5_clk_ip_isp0_ctrl,
+		.ctrlbit	= (0x3F << 8),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME2,
+		.devname	= SYSMMU_CLOCK_DEVNAME(isp, 9),
+		.enable		= &exynos5_clk_ip_isp1_ctrl,
+		.ctrlbit	= (0xF << 4),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(camif0, 12),
+		.enable		= &exynos5_clk_ip_gscl_ctrl,
+		.ctrlbit	= (1 << 11),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(camif1, 13),
+		.enable		= &exynos5_clk_ip_gscl_ctrl,
+		.ctrlbit	= (1 << 12),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(camif2, 14),
+		.enable		= &exynos5_clk_ip_gscl_ctrl,
+		.ctrlbit	= (1 << 20),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(2d, 15),
+		.enable		= &exynos5_clk_ip_acp_ctrl,
+		.ctrlbit	= (1 << 7)
+	}, {
+		.name		= "usbhost",
+		.enable		= exynos5_clk_ip_fsys_ctrl ,
+		.ctrlbit	= (1 << 18),
+	}, {
+		.name		= "usbotg",
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 7),
+	}, {
+		.name		= "fimg2d",
+		.devname	= "s5p-fimg2d",
+		.enable		= exynos5_clk_ip_acp_ctrl,
+		.ctrlbit	= (1 << 3),
+	}, {
+		.name		= "gps",
+		.enable		= exynos5_clk_ip_gps_ctrl,
+		.ctrlbit	= ((1 << 3) | (1 << 2) | (1 << 1) | (1 << 0)),
+	}, {
+		.name		= "nfcon",
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 22),
+	},
+#ifdef CONFIG_CPU_EXYNOS5250
+	{
+		.name		= "iop",
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= ((1 << 30) | (1 << 26) | (1 << 23)),
+	}, {
+		.name		= "core_iop",
+		.enable		= exynos5_clk_ip_core_ctrl,
+		.ctrlbit	= ((1 << 21) | (1 << 3)),
+	}, {
+		.name		= "mcu_iop",
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 0),
+	}, {
+		.name		= "adc",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 15),
+	}, {
+		.name		= "spi",
+		.devname	= "s3c64xx-spi.0",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 16),
+	}, {
+		.name		= "spi",
+		.devname	= "s3c64xx-spi.1",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 17),
+	}, {
+		.name		= "spi",
+		.devname	= "s3c64xx-spi.2",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 18),
+	},
+#endif
+	{
+		.name		= "ppmufsys",
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= ((1 << 29) | (1 << 28)),
+	}, {
+		.name		= "ppmudisp1",
+		.enable		= exynos5_clk_ip_disp1_ctrl,
+		.ctrlbit	= ((1 << 17) | (1 << 18)),
+	}, {
+		.name		= "ppmumfc",
+		.enable		= exynos5_clk_ip_mfc_ctrl,
+		.ctrlbit	= ((1 << 5) | (1 << 6)),
+	}, {
+		.name		= "ppmug3d",
+		.enable		= exynos5_clk_ip_g3d_ctrl,
+		.ctrlbit	= (1 << 2),
+	}, {
+		.name		= "ppmugen",
+		.enable		= exynos5_clk_ip_gen_ctrl,
+		.ctrlbit	= (1 << 15),
+	}, {
+		.name		= "ppmugscl",
+		.enable		= exynos5_clk_ip_gscl_ctrl,
+		.ctrlbit	= (1 << 19),
+	}, {
+		.name		= "acp",
+		.enable		= exynos5_clk_ip_acp_ctrl,
+		.ctrlbit	= (1 << 11),
+	}, {
+		.name		= "rtic",
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= ((1 << 11) | (1 << 9)),
+	}, {
+		.name		= "disp1",
+		.enable		= exynos5_clk_ip_disp1_ctrl,
+		.ctrlbit	= (1 << 8),
+	}, {
+		.name		= "gscl",
+		.enable		= exynos5_clk_ip_gscl_ctrl,
+		.ctrlbit	= ((0xF << 11) | (1 << 19)),
+	}, {
+		.name		= "secss",
+		.parent		= &exynos5_clk_aclk_acp.clk,
+		.enable		= exynos5_clk_ip_acp_ctrl,
+		.ctrlbit	= (1 << 2),
+	}, {
+		.name		= "sromc",
+		.enable		= exynos5_clk_ip_fsys_ctrl ,
+		.ctrlbit	= (1 << 17),
+	}, {
+		.name		= "mipi-hsi",
+		.enable		= exynos5_clk_ip_fsys_ctrl ,
+		.ctrlbit	= (1 << 8),
+	}, {
+		.name		= "mie",
+		.enable		= exynos5_clk_ip_disp1_ctrl ,
+		.ctrlbit	= (1 << 1),
+	}, {
+		.name		= "clkout_cpu",
+		.enable		= exynos5_clk_clkout_cpu_ctrl,
+		.ctrlbit	= (1 << 16),
+	}, {
+		.name		= "clkout_core",
+		.enable		= exynos5_clk_clkout_core_ctrl,
+		.ctrlbit	= (1 << 16),
+	}, {
+		.name		= "clkout_acp",
+		.enable		= exynos5_clk_clkout_acp_ctrl,
+		.ctrlbit	= (1 << 16),
+	}, {
+		.name		= "clkout_isp",
+		.enable		= exynos5_clk_clkout_isp_ctrl,
+		.ctrlbit	= (1 << 16),
+	}, {
+		.name		= "clkout_top",
+		.enable		= exynos5_clk_clkout_top_ctrl,
+		.ctrlbit	= (1 << 16),
+	}, {
+		.name		= "clkout_lex",
+		.enable		= exynos5_clk_clkout_lex_ctrl,
+		.ctrlbit	= (1 << 16),
+	}, {
+		.name		= "clkout_r0x",
+		.enable		= exynos5_clk_clkout_r0x_ctrl,
+		.ctrlbit	= (1 << 16),
+	}, {
+		.name		= "clkout_r1x",
+		.enable		= exynos5_clk_clkout_r1x_ctrl,
+		.ctrlbit	= (1 << 16),
+	}, {
+		.name		= "clkout_cdrex",
+		.enable		= exynos5_clk_clkout_cdrex_ctrl,
+		.ctrlbit	= (1 << 16),
+	}
+};
+
+static struct clk exynos5_i2cs_clocks[] = {
+	{
+		.name		= "i2c",
+		.devname	= "s3c2440-i2c.0",
+		.parent		= &exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 6),
+	}, {
+		.name		= "i2c",
+		.devname	= "s3c2440-i2c.1",
+		.parent		= &exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 7),
+	}, {
+		.name		= "i2c",
+		.devname	= "s3c2440-i2c.2",
+		.parent		= &exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 8),
+	}, {
+		.name		= "i2c",
+		.devname	= "s3c2440-i2c.3",
+		.parent		= &exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 9),
+	}, {
+		.name		= "i2c",
+		.devname	= "s3c2440-i2c.4",
+		.parent		= &exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 10),
+	}, {
+		.name		= "i2c",
+		.devname	= "s3c2440-i2c.5",
+		.parent		= &exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 11),
+	}, {
+		.name		= "i2c",
+		.devname	= "s3c2440-i2c.6",
+		.parent		= &exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 12),
+	}, {
+		.name		= "i2c",
+		.devname	= "s3c2440-i2c.7",
+		.parent		= &exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 13),
+	}, {
+		.name		= "i2c",
+		.devname	= "s3c2440-hdmiphy-i2c",
+		.parent		= &exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 14),
+	}
+};
+
+struct clk exynos5_uis_clocks[] = {
+	{
+		.name		= "uis",
+		.devname	= "s3c2440-uis.0",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 28),
+	}, {
+		.name		= "uis",
+		.devname	= "exynos-uis.1",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 29),
+	}, {
+		.name		= "uis",
+		.devname	= "exynos-uis.2",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 30),
+	}, {
+		.name		= "uis",
+		.devname	= "exynos-uis.3",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 31),
+	},
+};
+
+struct clk exynos5_init_dmaclocks[] = {
+	{
+		.name		= "pdma",
+		.devname	= "s3c-pl330.0",
+		.enable		= exynos5_clk_ip_gen_ctrl,
+		.ctrlbit	= ((1 << 4) | (1 << 14)),
+	}, {
+		.name		= "pdma",
+		.devname	= "s3c-pl330.1",
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 1),
+	}, {
+		.name		= "pdma",
+		.devname	= "s3c-pl330.2",
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 2),
+	}, {
+		.name		= "pdma",
+		.enable		= exynos5_clk_ip_acp_ctrl,
+		.ctrlbit	= ((1 << 1) | (1 << 8)),
+	},
+};
+
+#ifndef CONFIG_SAMSUNG_C2C
+struct clk exynos5_c2c_clock = {
+	.name		= "c2c",
+	.devname	= "samsung-c2c",
+	.enable		= exynos5_clk_ip_cpu_ctrl,
+	.ctrlbit	= (0x3f << 11),
+};
+#endif
+
+static struct clk *clkset_sclk_audio0_list[] = {
+	[0] = &exynos5_clk_audiocdclk0.clk,
+	[1] = &clk_ext_xtal_mux,
+	[2] = &exynos5_clk_sclk_hdmi27m,
+	[3] = &exynos5_clk_sclk_dptxphy,
+	[4] = &exynos5_clk_sclk_usbphy,
+	[5] = &exynos5_clk_sclk_hdmiphy,
+	[6] = &exynos5_clk_mout_mpll.clk,
+	[7] = &exynos5_clk_mout_epll.clk,
+	[8] = &exynos5_clk_sclk_vpll.clk,
+	[9] = &exynos5_clk_mout_cpll.clk,
+};
+
+static struct clksrc_sources exynos5_clkset_sclk_audio0 = {
+	.sources	= clkset_sclk_audio0_list,
+	.nr_sources	= ARRAY_SIZE(clkset_sclk_audio0_list),
+};
+
+static struct clksrc_clk exynos5_clk_sclk_audio0 = {
+	.clk	= {
+		.name		= "audio-bus",
+		.enable		= exynos5_clksrc_mask_maudio_ctrl,
+		.ctrlbit	= (1 << 0),
+	},
+	.sources = &exynos5_clkset_sclk_audio0,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_MAUDIO, .shift = 0, .size = 4 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_MAUDIO, .shift = 0, .size = 4 },
+};
+
+static struct clk *exynos5_clkset_mout_audss_list[] = {
+	&clk_ext_xtal_mux,
+	&clk_fout_epll,
+};
+
+static struct clksrc_sources clkset_mout_audss = {
+	.sources	= exynos5_clkset_mout_audss_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_mout_audss_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_audss = {
+	.clk	= {
+		.name		= "mout_audss",
+	},
+	.sources = &clkset_mout_audss,
+	.reg_src = { .reg = S5P_CLKSRC_AUDSS, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos5_clkset_sclk_audss_list[] = {
+	&exynos5_clk_mout_audss.clk,
+	&exynos5_clk_audiocdclk0.clk,
+	&exynos5_clk_sclk_audio0.clk,
+};
+
+static struct clksrc_sources exynos5_clkset_sclk_audss = {
+	.sources	= exynos5_clkset_sclk_audss_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_sclk_audss_list),
+};
+
+static struct clksrc_clk exynos5_clk_sclk_audss_i2s = {
+	.clk		= {
+		.name		= "i2sclk",
+		.enable		= exynos5_clk_audss_ctrl,
+		.ctrlbit	= S5P_AUDSS_CLKGATE_I2SSPECIAL,
+	},
+	.sources = &exynos5_clkset_sclk_audss,
+	.reg_src = { .reg = S5P_CLKSRC_AUDSS, .shift = 2, .size = 2 },
+	.reg_div = { .reg = S5P_CLKDIV_AUDSS, .shift = 8, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_audss_srp = {
+	.clk	= {
+		.name		= "dout_srp",
+		.parent		= &exynos5_clk_mout_audss.clk,
+	},
+	.reg_div = { .reg = S5P_CLKDIV_AUDSS, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_audss_bus = {
+	.clk	= {
+		.name		= "busclk",
+		.parent		= &exynos5_clk_dout_audss_srp.clk,
+		.enable		= exynos5_clk_audss_ctrl,
+		.ctrlbit	= S5P_AUDSS_CLKGATE_I2SBUS,
+	},
+	.reg_div = { .reg = S5P_CLKDIV_AUDSS, .shift = 4, .size = 4 },
+};
+
+static struct clk exynos5_init_audss_clocks[] = {
+	{
+		.name		= "srpclk",
+		.parent		= &exynos5_clk_dout_audss_srp.clk,
+		.enable		= exynos5_clk_audss_ctrl,
+		.ctrlbit	= S5P_AUDSS_CLKGATE_RP | S5P_AUDSS_CLKGATE_UART
+				| S5P_AUDSS_CLKGATE_TIMER,
+	}, {
+		.name		= "iis",
+		.devname	= "samsung-i2s.0",
+		.enable		= exynos5_clk_audss_ctrl,
+		.ctrlbit	= S5P_AUDSS_CLKGATE_I2SSPECIAL |
+					S5P_AUDSS_CLKGATE_I2SBUS,
+	}, {
+		.name		= "pcm",
+		.devname	= "samsung-pcm.0",
+		.enable		= exynos5_clk_audss_ctrl,
+		.ctrlbit	= S5P_AUDSS_CLKGATE_PCMSPECIAL |
+					S5P_AUDSS_CLKGATE_PCMBUS,
+	},
+};
+
+static struct clk *exynos5_clkset_sclk_audio1_list[] = {
+	[0] = &exynos5_clk_audiocdclk1,
+	[1] = &clk_ext_xtal_mux,
+	[2] = &exynos5_clk_sclk_hdmi27m,
+	[3] = &exynos5_clk_sclk_dptxphy,
+	[4] = &exynos5_clk_sclk_usbphy,
+	[5] = &exynos5_clk_sclk_hdmiphy,
+	[6] = &exynos5_clk_mout_mpll.clk,
+	[7] = &exynos5_clk_mout_epll.clk,
+	[8] = &exynos5_clk_sclk_vpll.clk,
+	[9] = &exynos5_clk_mout_cpll.clk,
+};
+
+static struct clksrc_sources exynos5_clkset_sclk_audio1 = {
+	.sources	= exynos5_clkset_sclk_audio1_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_sclk_audio1_list),
+};
+
+static struct clksrc_clk exynos5_clk_sclk_audio1 = {
+	.clk	= {
+		.name		= "audio-bus1",
+		.enable		= exynos5_clksrc_mask_peric1_ctrl,
+		.ctrlbit	= (1 << 0),
+	},
+	.sources = &exynos5_clkset_sclk_audio1,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 0, .size = 4 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC4, .shift = 0, .size = 4 },
+};
+
+static struct clk *exynos5_clkset_sclk_audio2_list[] = {
+	[0] = &exynos5_clk_audiocdclk2,
+	[1] = &clk_ext_xtal_mux,
+	[2] = &exynos5_clk_sclk_hdmi27m,
+	[3] = &exynos5_clk_sclk_dptxphy,
+	[4] = &exynos5_clk_sclk_usbphy,
+	[5] = &exynos5_clk_sclk_hdmiphy,
+	[6] = &exynos5_clk_mout_mpll.clk,
+	[7] = &exynos5_clk_mout_epll.clk,
+	[8] = &exynos5_clk_sclk_vpll.clk,
+	[9] = &exynos5_clk_mout_cpll.clk,
+};
+
+static struct clksrc_sources exynos5_clkset_sclk_audio2 = {
+	.sources	= exynos5_clkset_sclk_audio2_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_sclk_audio2_list),
+};
+
+static struct clksrc_clk exynos5_clk_sclk_audio2 = {
+	.clk	= {
+		.name		= "audio-bus2",
+		.enable		= exynos5_clksrc_mask_peric1_ctrl,
+		.ctrlbit	= (1 << 4),
+	},
+	.sources = &exynos5_clkset_sclk_audio2,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 4, .size = 4 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC4, .shift = 16, .size = 4 },
+};
+
+static struct clk *exynos5_clkset_sclk_spdif_list[] = {
+	[0] = &exynos5_clk_sclk_audio0.clk,
+	[1] = &exynos5_clk_sclk_audio1.clk,
+	[2] = &exynos5_clk_sclk_audio2.clk,
+	[3] = &exynos5_clk_spdifcdclk,
+};
+
+static struct clksrc_sources exynos5_clkset_sclk_spdif = {
+	.sources	= exynos5_clkset_sclk_spdif_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_sclk_spdif_list),
+};
+
+static struct clksrc_clk exynos5_clk_sclk_spdif = {
+	.clk	= {
+		.name		= "sclk_spdif",
+		.enable		= exynos5_clksrc_mask_peric1_ctrl,
+		.ctrlbit	= (1 << 8),
+		.ops		= &s5p_sclk_spdif_ops,
+	},
+	.sources = &exynos5_clkset_sclk_spdif,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 8, .size = 2 },
+};
+
+struct clk *exynos5_clkset_usbdrd30_list[] = {
+	[0] = &exynos5_clk_mout_mpll.clk,
+	[1] = &exynos5_clk_mout_cpll.clk,
+};
+
+struct clksrc_sources exynos5_clkset_usbdrd30 = {
+	.sources	= exynos5_clkset_usbdrd30_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_usbdrd30_list),
+};
+
+struct clk *exynos5_clkset_group_list[] = {
+	[0] = &clk_ext_xtal_mux,
+	[1] = NULL,
+	[2] = &exynos5_clk_sclk_hdmi24m,
+	[3] = &exynos5_clk_sclk_dptxphy,
+	[4] = &exynos5_clk_sclk_usbphy,
+	[5] = &exynos5_clk_sclk_hdmiphy,
+	[6] = &exynos5_clk_mout_mpll_user.clk,
+	[7] = &exynos5_clk_mout_epll.clk,
+	[8] = &exynos5_clk_sclk_vpll.clk,
+	[9] = &exynos5_clk_mout_cpll.clk,
+};
+
+struct clksrc_sources exynos5_clkset_group = {
+	.sources	= exynos5_clkset_group_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_group_list),
+};
+
+/* Possible clock sources for aclk_266_gscl_sub Mux */
+static struct clk *clk_src_gscl_266_list[] = {
+	[0] = &clk_ext_xtal_mux,
+	[1] = &exynos5_clk_aclk_266.clk,
+};
+
+static struct clksrc_sources clk_src_gscl_266 = {
+	.sources	= clk_src_gscl_266_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_gscl_266_list),
+};
+
+/* For ACLK_400_ISP */
+static struct clksrc_clk exynos5_clk_mout_aclk_400_isp = {
+	.clk    = {
+		.name	= "mout_aclk_400_isp",
+	},
+	.sources = &exynos5_clkset_aclk,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP1, .shift = 24, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_aclk_400_isp = {
+	.clk	= {
+		.name		= "dout_aclk_400_isp",
+		.parent		= &exynos5_clk_mout_aclk_400_isp.clk,
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 20, .size = 3 },
+};
+
+static struct clk *exynos5_clkset_aclk_400_isp_list[] = {
+	[0] = &clk_ext_xtal_mux,
+	[1] = &exynos5_clk_dout_aclk_400_isp.clk,
+};
+
+static struct clksrc_sources exynos5_clkset_aclk_400_isp = {
+	.sources	= exynos5_clkset_aclk_400_isp_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_aclk_400_isp_list),
+};
+
+static struct clksrc_clk exynos5_clk_aclk_400_isp = {
+	.clk	= {
+		.name		= "aclk_400_isp",
+	},
+	.sources = &exynos5_clkset_aclk_400_isp,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 20, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_uart_isp = {
+	.clk	= {
+		.name		= "sclk_uart_src_isp",
+	},
+	.sources = &exynos5_clkset_group,
+	.reg_src = { .reg = EXYNOS5_SCLK_SRC_ISP, .shift = 8, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_266_isp = {
+	.clk	= {
+		.name		= "aclk_266_isp",
+
+	},
+	.sources = &clk_src_gscl_266,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 16, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
+	.clk		= {
+		.name		= "sclk_mmc0",
+	},
+	.sources = &exynos5_clkset_group,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 0, .size = 4 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
+	.clk		= {
+		.name		= "sclk_mmc1",
+	},
+	.sources = &exynos5_clkset_group,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 4, .size = 4 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
+	.clk		= {
+		.name		= "sclk_mmc2",
+	},
+	.sources = &exynos5_clkset_group,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 8, .size = 4 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
+	.clk		= {
+		.name		= "sclk_mmc3",
+	},
+	.sources = &exynos5_clkset_group,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 12, .size = 4 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_mmc4 = {
+	.clk		= {
+		.name		= "sclk_mmc4",
+	},
+	.sources = &exynos5_clkset_group,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 16, .size = 4 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_spi0 = {
+	.clk		= {
+		.name		= "sclk_spi0",
+	},
+	.sources = &exynos5_clkset_group,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 16, .size = 4 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_spi1 = {
+	.clk		= {
+		.name		= "sclk_spi1",
+	},
+	.sources = &exynos5_clkset_group,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 20, .size = 4 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_spi2 = {
+	.clk		= {
+		.name		= "sclk_spi2",
+	},
+	.sources = &exynos5_clkset_group,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 24, .size = 4 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clksrcs[] = {
+	{
+		.clk	= {
+			.name		= "uclk1",
+			.devname	= "s5pv210-uart.0",
+			.enable		= exynos5_clksrc_mask_peric0_ctrl,
+			.ctrlbit	= (1 << 0),
+		},
+		.sources = &exynos5_clkset_group,
+		.reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0,
+				.shift = 0, .size = 4 },
+		.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0,
+				.shift = 0, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "uclk1",
+			.devname	= "s5pv210-uart.1",
+			.enable		= exynos5_clksrc_mask_peric0_ctrl,
+			.ctrlbit	= (1 << 4),
+		},
+		.sources = &exynos5_clkset_group,
+		.reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0,
+				.shift = 4, .size = 4 },
+		.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0,
+				.shift = 4, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "uclk1",
+			.devname	= "s5pv210-uart.2",
+			.enable		= exynos5_clksrc_mask_peric0_ctrl,
+			.ctrlbit	= (1 << 8),
+		},
+		.sources = &exynos5_clkset_group,
+		.reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 8, .size = 4 },
+		.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 8, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "uclk1",
+			.devname	= "s5pv210-uart.3",
+			.enable		= exynos5_clksrc_mask_peric0_ctrl,
+			.ctrlbit	= (1 << 12),
+		},
+		.sources = &exynos5_clkset_group,
+		.reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 12, .size = 4 },
+		.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 12, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "sclk_usbdrd30",
+			.enable		= exynos5_clksrc_mask_fsys_ctrl,
+			.ctrlbit	= (1 << 28),
+		},
+		.sources = &exynos5_clkset_usbdrd30,
+		.reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 28, .size = 1 },
+		.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 24, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "sclk_mmc",
+			.devname	= "s3c-sdhci.0",
+			.parent		= &exynos5_clk_sclk_mmc0.clk,
+			.enable		= exynos5_clksrc_mask_fsys_ctrl,
+			.ctrlbit	= (1 << 0),
+		},
+		.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 8, .size = 8 },
+	}, {
+		.clk	= {
+			.name		= "sclk_mmc",
+			.devname	= "s3c-sdhci.1",
+			.parent         = &exynos5_clk_sclk_mmc1.clk,
+			.enable		= exynos5_clksrc_mask_fsys_ctrl,
+			.ctrlbit	= (1 << 4),
+		},
+		.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 24, .size = 8 },
+	}, {
+		.clk	= {
+			.name		= "sclk_mmc",
+			.devname	= "s3c-sdhci.2",
+			.parent         = &exynos5_clk_sclk_mmc2.clk,
+			.enable		= exynos5_clksrc_mask_fsys_ctrl,
+			.ctrlbit	= (1 << 8),
+		},
+		.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 8, .size = 8 },
+	}, {
+		.clk	= {
+			.name		= "sclk_mmc",
+			.devname	= "s3c-sdhci.3",
+			.parent         = &exynos5_clk_sclk_mmc3.clk,
+			.enable		= exynos5_clksrc_mask_fsys_ctrl,
+			.ctrlbit	= (1 << 12),
+		},
+		.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 },
+	}, {
+		.clk	= {
+			.name		= "sclk_dwmci",
+			.parent         = &exynos5_clk_sclk_mmc4.clk,
+			.enable		= exynos5_clksrc_mask_fsys_ctrl,
+			.ctrlbit	= (1 << 16),
+		},
+		.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 8, .size = 8 },
+	}, {
+		.clk	= {
+			.name		= "sclk_pcm",
+			.parent		= &exynos5_clk_sclk_audio0.clk,
+		},
+			.reg_div = { .reg = EXYNOS5_CLKDIV_MAUDIO, .shift = 4, .size = 8 },
+	}, {
+		.clk	= {
+			.name		= "sclk_pcm",
+			.parent		= &exynos5_clk_sclk_audio1.clk,
+		},
+			.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC4, .shift = 4, .size = 8 },
+	}, {
+		.clk	= {
+			.name		= "sclk_pcm",
+			.parent		= &exynos5_clk_sclk_audio2.clk,
+		},
+			.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC4, .shift = 20, .size = 8 },
+	}, {
+		.clk	= {
+			.name		= "sclk_i2s",
+			.parent		= &exynos5_clk_sclk_audio1.clk,
+		},
+			.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC5, .shift = 0, .size = 6 },
+	}, {
+		.clk	= {
+			.name		= "sclk_i2s",
+			.parent		= &exynos5_clk_sclk_audio2.clk,
+		},
+			.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC5, .shift = 8, .size = 6 },
+	}, {
+		.clk	= {
+			.name		= "sclk_fimd",
+			.devname	= "s3cfb.1",
+			.enable		= exynos5_clksrc_mask_disp1_0_ctrl,
+			.ctrlbit	= (1 << 0),
+		},
+		.sources = &exynos5_clkset_group,
+		.reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
+		.reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "aclk_266_gscl",
+			.parent		= &exynos5_clk_aclk_266.clk,
+		},
+		.sources = &clk_src_gscl_266,
+		.reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 8, .size = 1 },
+	}, {
+		.clk	= {
+			.name		= "sclk_g3d",
+			.devname	= "mali-t604.0",
+			.enable		= exynos5_clk_gate_block,
+			.ctrlbit	= (1 << 1),
+		},
+		.sources = &exynos5_clkset_aclk,
+		.reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
+		.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
+	}, {
+		.clk	= {
+			.name           = "sclk_sata",
+			.devname        = "ahci",
+			.parent         = &exynos5_clk_mout_mpll_user.clk,
+			.enable		= exynos5_clk_ip_fsys_ctrl,
+			.ctrlbit	= (1 << 24),
+		},
+		.sources = &exynos5_clkset_aclk,
+		.reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 24, .size = 1 },
+		.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 20, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "sclk_gscl_wrap0",
+			.devname	= "s5p-mipi-csis.0",
+			.enable		= exynos5_clksrc_mask_gscl_ctrl,
+			.ctrlbit	= (1 << 24),
+		},
+		.sources = &exynos5_clkset_group,
+		.reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 24, .size = 4 },
+		.reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 24, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "sclk_gscl_wrap1",
+			.devname	= "s5p-mipi-csis.1",
+			.enable		= exynos5_clksrc_mask_gscl_ctrl,
+			.ctrlbit	= (1 << 28),
+		},
+		.sources = &exynos5_clkset_group,
+		.reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 28, .size = 4 },
+		.reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 28, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "sclk_cam0",
+			.enable		= exynos5_clksrc_mask_gscl_ctrl,
+			.ctrlbit	= (1 << 16),
+		},
+		.sources = &exynos5_clkset_group,
+		.reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 16, .size = 4 },
+		.reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 16, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "sclk_cam1",
+			.enable		= exynos5_clksrc_mask_gscl_ctrl,
+			.ctrlbit	= (1 << 20),
+		},
+		.sources = &exynos5_clkset_group,
+		.reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 20, .size = 4 },
+		.reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 20, .size = 4 },
+	}, {
+		.clk		= {
+			.name		= "aclk_266_isp_div0",
+			.parent     = &exynos5_clk_aclk_266_isp.clk,
+
+		},
+		.reg_div = { .reg = EXYNOS5_CLKDIV_ISP0, .shift = 0, .size = 3 },
+	}, {
+		.clk		= {
+			.name		= "aclk_266_isp_div1",
+			.parent     = &exynos5_clk_aclk_266_isp.clk,
+		},
+		.reg_div = { .reg = EXYNOS5_CLKDIV_ISP0, .shift = 4, .size = 3 },
+	}, {
+		.clk		= {
+			.name		= "aclk_266_isp_divmpwm",
+			.parent     = &exynos5_clk_aclk_266_isp.clk,
+		},
+		.reg_div = { .reg = EXYNOS5_CLKDIV_ISP2, .shift = 0, .size = 3 },
+	}, {
+		.clk		= {
+			.name		= "aclk_400_isp_div0",
+			.parent     = &exynos5_clk_aclk_400_isp.clk,
+		},
+		.reg_div = { .reg = EXYNOS5_CLKDIV_ISP1, .shift = 0, .size = 3 },
+	}, {
+		.clk		= {
+			.name		= "aclk_400_isp_div1",
+			.parent     = &exynos5_clk_aclk_400_isp.clk,
+		},
+		.reg_div = { .reg = EXYNOS5_CLKDIV_ISP1, .shift = 4, .size = 3 },
+	}, {
+		.clk		= {
+			.name		= "sclk_uart_isp",
+			.parent     = &exynos5_clk_sclk_uart_isp.clk,
+		},
+		.reg_div = { .reg = EXYNOS5_SCLK_DIV_ISP, .shift = 24, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "sclk_spi",
+			.devname	= "s3c64xx-spi.0",
+			.parent		= &exynos5_clk_sclk_spi0.clk,
+			.enable		= exynos5_clksrc_mask_peric1_ctrl,
+			.ctrlbit	= (1 << 16),
+		},
+		.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 8, .size = 8 },
+	}, {
+		.clk	= {
+			.name		= "sclk_spi",
+			.devname	= "s3c64xx-spi.1",
+			.parent		= &exynos5_clk_sclk_spi1.clk,
+			.enable		= exynos5_clksrc_mask_peric1_ctrl,
+			.ctrlbit	= (1 << 20),
+		},
+		.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 24, .size = 8 },
+	}, {
+		.clk	= {
+			.name		= "sclk_spi",
+			.devname	= "s3c64xx-spi.2",
+			.parent		= &exynos5_clk_sclk_spi2.clk,
+			.enable		= exynos5_clksrc_mask_peric1_ctrl,
+			.ctrlbit	= (1 << 24),
+		},
+		.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 },
+	},
+};
+
+static struct clksrc_clk exynos5_clk_sclk_jpeg = {
+	.clk	= {
+		.name		= "sclk_jpeg",
+		.enable		= exynos5_clksrc_mask_gen_ctrl,
+		.ctrlbit	= (1 << 0),
+	},
+	.sources = &exynos5_clkset_group,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_GEN, .shift = 0, .size = 4 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_c2c = {
+	.clk	= {
+		.name		= "sclk_c2c",
+		.id		= -1,
+	},
+	.sources = &exynos5_clkset_mout_mpll,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_SYSRGT, .shift = 4, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_c2c = {
+	.clk	= {
+		.name		= "aclk_c2c",
+		.id		= -1,
+		.parent		= &exynos5_clk_sclk_c2c.clk,
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_SYSRGT, .shift = 8, .size = 3 },
+};
+
+static struct clk *exynos5_clkset_c2c_list[] = {
+	[0] = &exynos5_clk_mout_mpll.clk,
+	[1] = &exynos5_clk_mout_bpll.clk,
+};
+
+static struct clksrc_sources exynos5_clkset_sclk_c2c = {
+	.sources	= exynos5_clkset_c2c_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_c2c_list),
+};
+
+static struct clksrc_clk exynos5_clk_sclk_c2c_rev0 = {
+	.clk	= {
+		.name		= "sclk_c2c",
+		.id		= -1,
+	},
+	.sources = &exynos5_clkset_sclk_c2c,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 12, .size = 1 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_CDREX, .shift = 8, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_c2c_rev0 = {
+	.clk	= {
+		.name		= "aclk_c2c",
+		.id		= -1,
+		.parent		= &exynos5_clk_sclk_c2c.clk,
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_CDREX, .shift = 12, .size = 3 },
+};
+
+/* Clock initialization code */
+static struct clksrc_clk *exynos5_sysclks[] = {
+	&exynos5_clk_audiocdclk0,
+	&exynos5_clk_mout_apll,
+	&exynos5_clk_sclk_apll,
+	&exynos5_clk_mout_bpll,
+	&exynos5_clk_mout_bpll_user,
+	&exynos5_clk_mout_gpll,
+	&exynos5_clk_mout_cpll,
+	&exynos5_clk_mout_epll,
+	&exynos5_clk_mout_mpll_fout,
+	&exynos5_clk_mout_bpll_fout,
+	&exynos5_clk_mout_mpll,
+	&exynos5_clk_mout_mpll_user,
+	&exynos5_clk_mout_vpllsrc,
+	&exynos5_clk_sclk_vpll,
+	&exynos5_clk_mout_cpu,
+	&exynos5_clk_dout_armclk,
+	&exynos5_clk_dout_arm2clk,
+	&exynos5_clk_mclk_cdrex,
+	&exynos5_clk_aclk_400,
+	&exynos5_clk_aclk_400_g3d_mid,
+	&exynos5_clk_mout_aclk_333,
+	&exynos5_clk_dout_aclk_333,
+	&exynos5_clk_aclk_333,
+	&exynos5_clk_mout_aclk_300_disp1_mid,
+	&exynos5_clk_mout_aclk_300_disp1_mid1,
+	&exynos5_clk_mout_aclk_300_disp1,
+	&exynos5_clk_dout_aclk_300_disp1,
+	&exynos5_clk_aclk_300_disp1,
+	&exynos5_clk_mout_aclk_300_gscl_mid,
+	&exynos5_clk_mout_aclk_300_gscl_mid1,
+	&exynos5_clk_mout_aclk_300_gscl,
+	&exynos5_clk_dout_aclk_300_gscl,
+	&exynos5_clk_aclk_300_gscl,
+	&exynos5_clk_aclk_266,
+	&exynos5_clk_aclk_200,
+	&exynos5_clk_aclk_166,
+	&exynos5_clk_dout_aclk_66_pre,
+	&exynos5_clk_aclk_200_disp1,
+	&exynos5_clk_mout_aclk_400_isp,
+	&exynos5_clk_dout_aclk_400_isp,
+	&exynos5_clk_aclk_400_isp,
+	&exynos5_clk_aclk_66,
+	&exynos5_clk_sclk_mmc0,
+	&exynos5_clk_sclk_mmc1,
+	&exynos5_clk_sclk_mmc2,
+	&exynos5_clk_sclk_mmc3,
+	&exynos5_clk_sclk_mmc4,
+	&exynos5_clk_mout_audss,
+	&exynos5_clk_sclk_audss_bus,
+	&exynos5_clk_sclk_audss_i2s,
+	&exynos5_clk_dout_audss_srp,
+	&exynos5_clk_sclk_audio0,
+	&exynos5_clk_sclk_audio1,
+	&exynos5_clk_sclk_audio2,
+	&exynos5_clk_sclk_spdif,
+	&exynos5_clk_aclk_acp,
+	&exynos5_clk_pclk_acp,
+	&exynos5_clk_aclk_266_isp,
+	&exynos5_clk_sclk_uart_isp,
+	&exynos5_clk_sclk_c2c,
+	&exynos5_clk_aclk_c2c,
+	&exynos5_clk_sclk_spi0,
+	&exynos5_clk_sclk_spi1,
+	&exynos5_clk_sclk_spi2,
+	&exynos5_clk_sclk_jpeg,
+};
+
+static unsigned long exynos5_epll_get_rate(struct clk *clk)
+{
+	return clk->rate;
+}
+
+static struct clk *exynos5_clks[] __initdata = {
+	&exynos5_clk_sclk_hdmi27m,
+	&exynos5_clk_sclk_hdmiphy,
+	&clk_fout_bpll,
+	&clk_fout_cpll,
+	&clk_fout_mpll_div2,
+	&clk_fout_bpll_div2,
+	&clk_fout_gpll,
+	&exynos5_clk_armclk,
+};
+
+static u32 epll_div[][6] = {
+	{ 192000000, 0, 48, 3, 1, 0 },
+	{ 180000000, 0, 45, 3, 1, 0 },
+	{  73728000, 1, 73, 3, 3, 47710 },
+	{  67737600, 1, 90, 4, 3, 20762 },
+	{  49152000, 0, 49, 3, 3, 9961 },
+	{  45158400, 0, 45, 3, 3, 10381 },
+	{ 180633600, 0, 45, 3, 1, 10381 },
+};
+
+static int exynos5_epll_set_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned int epll_con, epll_con_k;
+	unsigned int i;
+	unsigned int tmp;
+	unsigned int epll_rate;
+	unsigned int locktime;
+	unsigned int lockcnt;
+
+	/* Return if nothing changed */
+	if (clk->rate == rate)
+		return 0;
+
+	if (clk->parent)
+		epll_rate = clk_get_rate(clk->parent);
+	else
+		epll_rate = clk_ext_xtal_mux.rate;
+
+	if (epll_rate != 24000000) {
+		pr_err("Invalid Clock : recommended clock is 24MHz.\n");
+		return -EINVAL;
+	}
+
+	epll_con = __raw_readl(EXYNOS5_EPLL_CON0);
+	epll_con &= ~(0x1 << 27 | \
+			PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |   \
+			PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
+			PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
+
+	for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
+		if (epll_div[i][0] == rate) {
+			epll_con_k = epll_div[i][5] << 0;
+			epll_con |= epll_div[i][1] << 27;
+			epll_con |= epll_div[i][2] << PLL46XX_MDIV_SHIFT;
+			epll_con |= epll_div[i][3] << PLL46XX_PDIV_SHIFT;
+			epll_con |= epll_div[i][4] << PLL46XX_SDIV_SHIFT;
+			break;
+		}
+	}
+
+	if (i == ARRAY_SIZE(epll_div)) {
+		printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
+				__func__);
+		return -EINVAL;
+	}
+
+	epll_rate /= 1000000;
+
+	/* 3000 max_cycls : specification data */
+	locktime = 3000 / epll_rate * epll_div[i][3];
+	lockcnt = locktime * 10000 / (10000 / epll_rate);
+
+	__raw_writel(lockcnt, EXYNOS5_EPLL_LOCK);
+
+	__raw_writel(epll_con, EXYNOS5_EPLL_CON0);
+	__raw_writel(epll_con_k, EXYNOS5_EPLL_CON1);
+
+	do {
+		tmp = __raw_readl(EXYNOS5_EPLL_CON0);
+	} while (!(tmp & 0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT));
+
+	clk->rate = rate;
+
+	return 0;
+}
+
+static struct clk_ops exynos5_epll_ops = {
+	.get_rate = exynos5_epll_get_rate,
+	.set_rate = exynos5_epll_set_rate,
+};
+
+static int xtal_rate;
+
+static unsigned long exynos5_fout_apll_get_rate(struct clk *clk)
+{
+	return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS5_APLL_CON0));
+}
+
+static struct clk_ops exynos5_fout_apll_ops = {
+	.get_rate = exynos5_fout_apll_get_rate,
+};
+
+static struct vpll_div_data exynos5_vpll_div[] = {
+	{268000000, 6, 268, 2, 41104, 0,  0, 0},
+	{86000000, 6, 344, 4, 2936, 0,  0, 0},
+};
+
+static unsigned long exynos5_vpll_get_rate(struct clk *clk)
+{
+	return clk->rate;
+}
+
+static int exynos5_vpll_set_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned int vpll_con0, vpll_con1;
+	unsigned int tmp;
+
+	/* Return if nothing changed */
+	if (clk->rate == rate)
+		return 0;
+
+	vpll_con0 = __raw_readl(EXYNOS5_VPLL_CON0);
+	vpll_con0 &= ~(PLL36XX_MDIV_MASK << PLL36XX_MDIV_SHIFT |       \
+		       PLL36XX_PDIV_MASK << PLL36XX_PDIV_SHIFT |       \
+		       PLL36XX_SDIV_MASK << PLL36XX_SDIV_SHIFT);
+
+	vpll_con1 = __raw_readl(EXYNOS5_VPLL_CON1);
+	vpll_con1 &= ~(0xffff << 0);
+#if 0
+	for (i = 0; i < ARRAY_SIZE(exynos5_vpll_div); i++) {
+		if (exynos5_vpll_div[i].rate == rate) {
+			vpll_con0 |= exynos5_vpll_div[i].pdiv << PLL36XX_PDIV_SHIFT;
+			vpll_con0 |= exynos5_vpll_div[i].mdiv << PLL36XX_MDIV_SHIFT;
+			vpll_con0 |= exynos5_vpll_div[i].sdiv << PLL36XX_SDIV_SHIFT;
+			vpll_con1 |= exynos5_vpll_div[i].k << 0;
+			break;
+		}
+	}
+
+	if (i == ARRAY_SIZE(exynos5_vpll_div)) {
+		printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
+				__func__);
+		return -EINVAL;
+	}
+
+	/* 3000 max_cycls : specification data */
+	locktime = 3000 * exynos5_vpll_div[i].pdiv + 1;
+
+	__raw_writel(locktime, EXYNOS5_VPLL_LOCK);
+#endif
+#if defined(CONFIG_DP_40HZ_P11) || defined(CONFIG_DP_40HZ_P10)
+			vpll_con0 = 0xA0b30602;
+			vpll_con1 = 0x15b5;
+#elif defined(CONFIG_DP_60HZ_P11) || defined(CONFIG_DP_60HZ_P10)
+			vpll_con0 = 0xA10c0602;
+			vpll_con1 = 0xA090;
+#endif
+
+
+	__raw_writel(vpll_con0, EXYNOS5_VPLL_CON0);
+	__raw_writel(vpll_con1, EXYNOS5_VPLL_CON1);
+
+	do {
+		tmp = __raw_readl(EXYNOS5_VPLL_CON0);
+	} while (!(tmp & (0x1 << EXYNOS5_VPLLCON0_LOCKED_SHIFT)));
+
+	clk->rate = rate;
+
+	return 0;
+}
+
+static struct clk_ops exynos5_vpll_ops = {
+	.get_rate = exynos5_vpll_get_rate,
+	.set_rate = exynos5_vpll_set_rate,
+};
+
+static u32 exynos5_gpll_div[][6] = {
+	/*rate, P, M, S, AFC_DNB, AFC*/
+	{1400000000, 3, 175, 0, 0, 0}, /* for 466MHz */
+	{800000000, 3, 100, 0, 0, 0},  /* for 400MHz, 200MHz */
+	{667000000, 7, 389, 1, 0, 0},  /* for 333MHz, 222MHz, 166MHz */
+	{600000000, 4, 200, 1, 0, 0},  /* for 300MHz, 200MHz, 150MHz */
+	{533000000, 12, 533, 1, 0, 0}, /* for 533MHz, 266MHz, 133MHz */
+	{450000000, 12, 450, 1, 0, 0}, /* for 450 Hz */
+	{400000000, 3, 100, 1, 0, 0},
+	{333000000, 4, 222, 2, 0, 0},
+	{200000000, 3, 100, 2, 0, 0},
+};
+
+static unsigned long exynos5_gpll_get_rate(struct clk *clk)
+{
+	return clk->rate;
+}
+
+static int exynos5_gpll_set_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned int gpll_con0;
+	unsigned int locktime;
+	unsigned int tmp;
+	unsigned int i;
+
+	/* Return if nothing changed */
+	if (clk->rate == rate)
+		return 0;
+
+	gpll_con0 = __raw_readl(EXYNOS5_GPLL_CON0);
+	gpll_con0 &= ~(PLL35XX_MDIV_MASK << PLL35XX_MDIV_SHIFT |       \
+		       PLL35XX_PDIV_MASK << PLL35XX_PDIV_SHIFT |       \
+		       PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT);
+
+	for (i = 0; i < ARRAY_SIZE(exynos5_gpll_div); i++) {
+		if (exynos5_gpll_div[i][0] == rate) {
+			gpll_con0 |= exynos5_gpll_div[i][1] << PLL35XX_PDIV_SHIFT;
+			gpll_con0 |= exynos5_gpll_div[i][2] << PLL35XX_MDIV_SHIFT;
+			gpll_con0 |= exynos5_gpll_div[i][3] << PLL35XX_SDIV_SHIFT;
+			break;
+		}
+	}
+
+	if (i == ARRAY_SIZE(exynos5_gpll_div)) {
+		printk(KERN_ERR "%s: Invalid Clock GPLL Frequency\n",
+				__func__);
+		return -EINVAL;
+	}
+
+	/* 250 max_cycls : specification data */
+	/* 270@p=1, 1cycle=1/24=41.6ns */
+	/* calc >> p=5, 270 * 5 = 1350cycle * 41.6ns = 56.16us */
+
+	locktime = 270 * exynos5_gpll_div[i][1] + 1;
+
+	__raw_writel(locktime, EXYNOS5_GPLL_LOCK);
+
+	__raw_writel(gpll_con0, EXYNOS5_GPLL_CON0);
+
+	do {
+		tmp = __raw_readl(EXYNOS5_GPLL_CON0);
+	} while (!(tmp & (0x1 << EXYNOS5_GPLLCON0_LOCKED_SHIFT)));
+
+	clk->rate = rate;
+
+	return 0;
+}
+
+static struct clk_ops exynos5_gpll_ops = {
+	.get_rate = exynos5_gpll_get_rate,
+	.set_rate = exynos5_gpll_set_rate,
+};
+
+#ifdef CONFIG_PM
+static int exynos5_clock_suspend(void)
+{
+	s3c_pm_do_save(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
+
+	if (samsung_rev() < EXYNOS5250_REV_1_0)
+		s3c_pm_do_save(exynos5250_clock_save_rev0,
+				ARRAY_SIZE(exynos5250_clock_save_rev0));
+
+	s3c_pm_do_save(exynos5_epll_save, ARRAY_SIZE(exynos5_epll_save));
+	s3c_pm_do_save(exynos5_vpll_save, ARRAY_SIZE(exynos5_vpll_save));
+
+	if (samsung_rev() >= EXYNOS5250_REV_1_0)
+		s3c_pm_do_save(exynos5_gpll_save, ARRAY_SIZE(exynos5_gpll_save));
+	return 0;
+}
+
+static void exynos5_clock_resume(void)
+{
+	unsigned int tmp;
+
+	s3c_pm_do_restore_core(exynos5_epll_save, ARRAY_SIZE(exynos5_epll_save));
+	s3c_pm_do_restore_core(exynos5_vpll_save, ARRAY_SIZE(exynos5_vpll_save));
+
+	if (samsung_rev() >= EXYNOS5250_REV_1_0)
+		s3c_pm_do_restore_core(exynos5_gpll_save, ARRAY_SIZE(exynos5_gpll_save));
+
+	/* waiting epll & vpll locking time */
+	do {
+		tmp = __raw_readl(EXYNOS5_EPLL_CON0);
+	} while (!(tmp & 0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT));
+
+	do {
+		tmp = __raw_readl(EXYNOS5_VPLL_CON0);
+	} while (!(tmp & 0x1 << EXYNOS5_VPLLCON0_LOCKED_SHIFT));
+
+	if (samsung_rev() >= EXYNOS5250_REV_1_0) {
+		do {
+			tmp = __raw_readl(EXYNOS5_GPLL_CON0);
+		} while (!(tmp & (0x1 << EXYNOS5_GPLLCON0_LOCKED_SHIFT)));
+	}
+
+	if (samsung_rev() < EXYNOS5250_REV_1_0)
+		s3c_pm_do_restore_core(exynos5250_clock_save_rev0,
+					ARRAY_SIZE(exynos5250_clock_save_rev0));
+
+	s3c_pm_do_restore_core(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
+}
+#else
+#define exynos5_clock_suspend NULL
+#define exynos5_clock_resume NULL
+#endif
+
+struct syscore_ops exynos5_clock_syscore_ops = {
+	.suspend        = exynos5_clock_suspend,
+	.resume         = exynos5_clock_resume,
+};
+
+void __init_or_cpufreq exynos5_setup_clocks(void)
+{
+	struct clk *xtal_clk;
+	unsigned long apll;
+	unsigned long bpll;
+	unsigned long cpll;
+	unsigned long mpll;
+	unsigned long epll;
+	unsigned long vpll;
+	unsigned long gpll;
+	unsigned long vpllsrc;
+	unsigned long xtal;
+	unsigned long armclk;
+	unsigned long mclk_cdrex;
+	unsigned long aclk_400;
+	unsigned long aclk_333;
+	unsigned long aclk_266;
+	unsigned long aclk_200;
+	unsigned long aclk_166;
+	unsigned long aclk_66;
+	unsigned int ptr;
+
+	printk(KERN_DEBUG "%s: registering clocks\n", __func__);
+
+	xtal_clk = clk_get(NULL, "xtal");
+	BUG_ON(IS_ERR(xtal_clk));
+
+	xtal = clk_get_rate(xtal_clk);
+
+	xtal_rate = xtal;
+
+	clk_put(xtal_clk);
+
+	printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
+
+#if defined(CONFIG_MACH_P10_DP_01)
+	/* setting vpll 268627200 Hz */
+	if (exynos5_vpll_set_rate(&clk_fout_vpll, 268000000))
+		printk(KERN_ERR "Unable to set %s of clock vpll.\n", clk_fout_vpll.name);
+#elif defined(CONFIG_MACH_P10_DP_00)
+	/* setting vpll 86011199 Hz */
+	if (exynos5_vpll_set_rate(&clk_fout_vpll, 86000000))
+		printk(KERN_ERR "Unable to set %s of clock vpll.\n", clk_fout_vpll.name);
+#endif
+
+	/* Set and check PLLs */
+	apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_APLL_CON0));
+	bpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_BPLL_CON0));
+	cpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_CPLL_CON0));
+	mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_MPLL_CON0));
+	epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS5_EPLL_CON0),
+			__raw_readl(EXYNOS5_EPLL_CON1));
+
+	if ((soc_is_exynos5250() && samsung_rev() >= EXYNOS5250_REV_1_0))
+	    gpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_GPLL_CON0));
+	else
+	    gpll = 0;
+
+	vpllsrc = clk_get_rate(&exynos5_clk_mout_vpllsrc.clk);
+	vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS5_VPLL_CON0),
+			__raw_readl(EXYNOS5_VPLL_CON1));
+
+	clk_fout_apll.ops = &exynos5_fout_apll_ops;
+	clk_fout_bpll.rate = bpll;
+	clk_fout_bpll_div2.rate = bpll / 2;
+	clk_fout_cpll.rate = cpll;
+	clk_fout_mpll.rate = mpll;
+	clk_fout_mpll_div2.rate = mpll / 2;
+	clk_fout_epll.rate = epll;
+	clk_fout_vpll.rate = vpll;
+
+	if (soc_is_exynos5250() && samsung_rev() >= EXYNOS5250_REV_1_0) {
+		gpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_GPLL_CON0));
+		clk_fout_gpll.rate = gpll;
+
+		printk(KERN_INFO "EXYNOS5: PLL settings, A=%ld, B=%ld, C=%ld\n"
+			"M=%ld, E=%ld, V=%ld, G=%ld\n",
+			apll, bpll, cpll, mpll, epll, vpll, gpll);
+	} else {
+		printk(KERN_INFO "EXYNOS5: PLL settings, A=%ld, B=%ld, C=%ld\n"
+			"M=%ld, E=%ld, V=%ld\n",
+			apll, bpll, cpll, mpll, epll, vpll);
+	}
+
+	/* Set parent for bus clocks */
+	if ((soc_is_exynos5250() && samsung_rev() >= EXYNOS5250_REV_1_0))
+		clk_set_parent(&exynos5_clk_mout_mpll.clk,
+				&exynos5_clk_mout_mpll_fout.clk);
+
+	armclk = clk_get_rate(&exynos5_clk_armclk);
+	mclk_cdrex = clk_get_rate(&exynos5_clk_mclk_cdrex.clk);
+
+	aclk_400 = clk_get_rate(&exynos5_clk_aclk_400.clk);
+	aclk_333 = clk_get_rate(&exynos5_clk_aclk_333.clk);
+	aclk_266 = clk_get_rate(&exynos5_clk_aclk_266.clk);
+	aclk_200 = clk_get_rate(&exynos5_clk_aclk_200.clk);
+	aclk_166 = clk_get_rate(&exynos5_clk_aclk_166.clk);
+	aclk_66 = clk_get_rate(&exynos5_clk_aclk_66.clk);
+
+	printk(KERN_INFO "EXYNOS5: ARMCLK=%ld, CDREX=%ld, ACLK400=%ld\n"
+			"ACLK333=%ld, ACLK266=%ld, ACLK200=%ld\n"
+			"ACLK166=%ld, ACLK66=%ld\n",
+			armclk, mclk_cdrex, aclk_400,
+			aclk_333, aclk_266, aclk_200,
+			aclk_166, aclk_66);
+
+	clk_fout_epll.ops = &exynos5_epll_ops;
+	clk_fout_vpll.ops = &exynos5_vpll_ops;
+	clk_fout_gpll.ops = &exynos5_gpll_ops;
+
+	if (clk_set_parent(&exynos5_clk_mout_audss.clk, &clk_fout_epll))
+		printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
+				clk_fout_epll.name, exynos5_clk_mout_audss.clk.name);
+#if defined(CONFIG_SND_SAMSUNG_PCM) && !defined(CONFIG_SND_SAMSUNG_PCM_USE_EPLL)
+	if (clk_set_parent(&exynos5_clk_sclk_audio0.clk, &exynos5_clk_audiocdclk0.clk))
+		printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
+				exynos5_clk_audiocdclk0.clk.name, exynos5_clk_sclk_audio0.clk.name);
+#else
+	if (clk_set_parent(&exynos5_clk_sclk_audio0.clk, &exynos5_clk_mout_epll.clk))
+		printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
+				exynos5_clk_mout_epll.clk.name, exynos5_clk_sclk_audio0.clk.name);
+#endif
+	if (clk_set_parent(&exynos5_clk_sclk_audio1.clk, &exynos5_clk_mout_epll.clk))
+		printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
+				exynos5_clk_mout_epll.clk.name, exynos5_clk_sclk_audio1.clk.name);
+	if (clk_set_parent(&exynos5_clk_sclk_audio2.clk, &exynos5_clk_mout_epll.clk))
+		printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
+				exynos5_clk_mout_epll.clk.name, exynos5_clk_sclk_audio2.clk.name);
+	if (clk_set_parent(&exynos5_clk_mout_epll.clk, &clk_fout_epll))
+		printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
+				clk_fout_epll.name, exynos5_clk_mout_epll.clk.name);
+
+	if (clk_set_parent(&exynos5_clk_mout_aclk_400_isp.clk, &exynos5_clk_mout_mpll_user.clk))
+		printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
+			exynos5_clk_mout_mpll_user.clk.name, exynos5_clk_mout_aclk_400_isp.clk.name);
+	if (clk_set_parent(&exynos5_clk_aclk_266_isp.clk, &exynos5_clk_aclk_266.clk))
+		printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
+			exynos5_clk_aclk_266.clk.name, exynos5_clk_aclk_266_isp.clk.name);
+	if (clk_set_parent(&exynos5_clk_aclk_400_isp.clk, &exynos5_clk_dout_aclk_400_isp.clk))
+		printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
+			exynos5_clk_mout_aclk_400_isp.clk.name, exynos5_clk_aclk_400_isp.clk.name);
+	if (clk_set_parent(&exynos5_clk_sclk_uart_isp.clk, &exynos5_clk_mout_mpll_user.clk))
+		printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
+			exynos5_clk_mout_mpll_user.clk.name, exynos5_clk_sclk_uart_isp.clk.name);
+
+	clk_set_rate(&exynos5_clk_sclk_apll.clk, 100000000);
+	clk_set_rate(&exynos5_clk_aclk_266.clk, 300000000);
+
+	clk_set_rate(&exynos5_clk_aclk_acp.clk, 267000000);
+	clk_set_rate(&exynos5_clk_pclk_acp.clk, 134000000);
+
+	for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrcs); ptr++)
+		s3c_set_clksrc(&exynos5_clksrcs[ptr], true);
+}
+
+void __init exynos5_register_clocks(void)
+{
+	int ptr;
+
+	if (soc_is_exynos5250() && samsung_rev() >= EXYNOS5250_REV_1_0) {
+		exynos5_clk_mout_mpll.sources = &exynos5_clkset_mout_mpll;
+		exynos5_clk_mout_bpll.sources = &exynos5_clkset_mout_bpll;
+		exynos5_clk_aclk_400.sources = &exynos5_clkset_aclk_g3d;
+		exynos5_clk_mout_aclk_300_gscl.sources = &exynos5_clkset_aclk_300_gscl_rev1;
+		exynos5_clk_mout_aclk_300_disp1.sources = &exynos5_clkset_mout_aclk_300_disp1_rev1;
+	} else if (soc_is_exynos5250() && samsung_rev() < EXYNOS5250_REV_1_0) {
+		exynos5_clk_sclk_jpeg.sources = NULL;
+		exynos5_clk_sclk_jpeg.reg_src.reg = 0;
+		exynos5_clk_sclk_jpeg.clk.parent = &exynos5_clk_mout_cpll.clk;
+		exynos5_clk_sclk_jpeg.clk.enable = NULL;
+		exynos5_clk_sclk_jpeg.clk.ctrlbit = 0;
+	}
+
+	s3c24xx_register_clocks(exynos5_clks, ARRAY_SIZE(exynos5_clks));
+
+	for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sysclks); ptr++)
+		s3c_register_clksrc(exynos5_sysclks[ptr], 1);
+
+	for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sclk_tv); ptr++)
+		s3c_register_clksrc(exynos5_sclk_tv[ptr], 1);
+
+	s3c_register_clksrc(exynos5_clksrcs, ARRAY_SIZE(exynos5_clksrcs));
+	s3c_register_clocks(exynos5_init_clocks, ARRAY_SIZE(exynos5_init_clocks));
+
+	s3c_register_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
+	s3c_disable_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
+
+	/* TN Feature.. these clocks was enabled at booloader */
+	s3c_register_clocks(exynos5_init_clock_on, ARRAY_SIZE(exynos5_init_clock_on));
+
+	s3c_register_clocks(exynos5_init_audss_clocks, ARRAY_SIZE(exynos5_init_audss_clocks));
+	s3c_disable_clocks(exynos5_init_audss_clocks, ARRAY_SIZE(exynos5_init_audss_clocks));
+
+	if (soc_is_exynos5250() && (samsung_rev() < EXYNOS5250_REV_1_0))
+		exynos5_init_dmaclocks[2].ctrlbit = exynos5_init_dmaclocks[1].ctrlbit;
+	s3c_register_clocks(exynos5_init_dmaclocks, ARRAY_SIZE(exynos5_init_dmaclocks));
+	s3c_disable_clocks(exynos5_init_dmaclocks, ARRAY_SIZE(exynos5_init_dmaclocks));
+
+	s3c_register_clocks(exynos5_i2cs_clocks, ARRAY_SIZE(exynos5_i2cs_clocks));
+	s3c_disable_clocks(exynos5_i2cs_clocks, ARRAY_SIZE(exynos5_i2cs_clocks));
+
+	if (samsung_rev() >= EXYNOS5250_REV_1_0) {
+		s3c_register_clocks(exynos5_uis_clocks, ARRAY_SIZE(exynos5_uis_clocks));
+		s3c_disable_clocks(exynos5_uis_clocks, ARRAY_SIZE(exynos5_uis_clocks));
+	}
+
+	if (samsung_rev() < EXYNOS5250_REV_1_0) {
+		s3c_register_clksrc(&exynos5_clk_sclk_c2c_rev0, 1);
+		s3c_register_clksrc(&exynos5_clk_aclk_c2c_rev0, 1);
+	}
+
+#ifndef CONFIG_SAMSUNG_C2C
+	if (soc_is_exynos5250() && (samsung_rev() >= EXYNOS5250_REV_1_0)) {
+		exynos5_c2c_clock.enable = exynos5_clk_ip_sysrgt_ctrl;
+		exynos5_c2c_clock.ctrlbit = ((1 << 2) | (1 << 1));
+	}
+
+	s3c24xx_register_clock(&exynos5_c2c_clock);
+	s3c_disable_clocks(&exynos5_c2c_clock, 1);
+#endif
+
+	register_syscore_ops(&exynos5_clock_syscore_ops);
+	s3c_pwmclk_init();
+}
+
+static int __init clock_domain_init(void)
+{
+	int index;
+
+	/* Add dma clock */
+	for (index = 0; index < ARRAY_SIZE(exynos5_init_dmaclocks); index++)
+		clock_add_domain(LPA_DOMAIN, &exynos5_init_dmaclocks[index]);
+
+	/* Add i2c clock */
+	for (index = 0; index < ARRAY_SIZE(exynos5_i2cs_clocks); index++)
+		clock_add_domain(LPA_DOMAIN, &exynos5_i2cs_clocks[index]);
+
+	return 0;
+}
+late_initcall(clock_domain_init);
diff --git a/arch/arm/mach-exynos/cpu-exynos4.c b/arch/arm/mach-exynos/cpu-exynos4.c
new file mode 100644
index 0000000..ffd9387
--- /dev/null
+++ b/arch/arm/mach-exynos/cpu-exynos4.c
@@ -0,0 +1,466 @@
+/* linux/arch/arm/mach-exynos/cpu.c
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/sched.h>
+#include <linux/sysdev.h>
+#include <linux/delay.h>
+
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/proc-fns.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/hardware/gic.h>
+#include <asm/cacheflush.h>
+
+#include <plat/cpu.h>
+#include <plat/clock.h>
+#include <plat/devs.h>
+#include <plat/fb-core.h>
+#include <plat/exynos4.h>
+#include <plat/sdhci.h>
+#include <plat/mshci.h>
+#include <plat/fimc-core.h>
+#include <plat/adc-core.h>
+#include <plat/pm.h>
+#include <plat/iic-core.h>
+#include <plat/ace-core.h>
+#include <plat/reset.h>
+#include <plat/audio.h>
+#include <plat/tv-core.h>
+#include <plat/rtc-core.h>
+
+#include <mach/regs-irq.h>
+#include <mach/regs-pmu.h>
+#include <mach/smc.h>
+
+unsigned int gic_bank_offset __read_mostly;
+
+extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
+			 unsigned int irq_start);
+extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
+
+/* Initial IO mappings */
+static struct map_desc exynos4_iodesc[] __initdata = {
+	{
+		.virtual	= (unsigned long)S5P_VA_SYSTIMER,
+		.pfn		= __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_CMU,
+		.pfn		= __phys_to_pfn(EXYNOS4_PA_CMU),
+		.length		= SZ_128K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_PMU,
+		.pfn		= __phys_to_pfn(EXYNOS4_PA_PMU),
+		.length		= SZ_64K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_COMBINER_BASE,
+		.pfn		= __phys_to_pfn(EXYNOS4_PA_COMBINER),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_COREPERI_BASE,
+		.pfn		= __phys_to_pfn(EXYNOS4_PA_COREPERI),
+		.length		= SZ_8K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_L2CC,
+		.pfn		= __phys_to_pfn(EXYNOS4_PA_L2CC),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_GPIO1,
+		.pfn		= __phys_to_pfn(EXYNOS4_PA_GPIO1),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_GPIO2,
+		.pfn		= __phys_to_pfn(EXYNOS4_PA_GPIO2),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_GPIO3,
+		.pfn		= __phys_to_pfn(EXYNOS4_PA_GPIO3),
+		.length		= SZ_256,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_GPIO4,
+		.pfn		= __phys_to_pfn(EXYNOS4_PA_GPIO4),
+		.length		= SZ_256,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S3C_VA_UART,
+		.pfn		= __phys_to_pfn(S3C_PA_UART),
+		.length		= SZ_512K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_SROMC,
+		.pfn		= __phys_to_pfn(EXYNOS4_PA_SROMC),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S3C_VA_USB_HSPHY,
+		.pfn		= __phys_to_pfn(EXYNOS4_PA_HSPHY),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_GIC_CPU,
+		.pfn		= __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
+		.length		= SZ_64K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_GIC_DIST,
+		.pfn		= __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
+		.length		= SZ_64K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual        = (unsigned long)S5P_VA_AUDSS,
+		.pfn            = __phys_to_pfn(EXYNOS4_PA_AUDSS),
+		.length         = SZ_4K,
+		.type           = MT_DEVICE,
+	}, {
+		.virtual        = (unsigned long)S5P_VA_PPMU_CPU,
+		.pfn            = __phys_to_pfn(EXYNOS4_PA_PPMU_CPU),
+		.length         = SZ_8K,
+		.type           = MT_DEVICE,
+	}, {
+		.virtual        = (unsigned long)S5P_VA_PPMU_DMC0,
+		.pfn            = __phys_to_pfn(EXYNOS4_PA_PPMU_DMC0),
+		.length         = SZ_8K,
+		.type           = MT_DEVICE,
+	}, {
+		.virtual        = (unsigned long)S5P_VA_PPMU_DMC1,
+		.pfn            = __phys_to_pfn(EXYNOS4_PA_PPMU_DMC1),
+		.length         = SZ_8K,
+		.type           = MT_DEVICE,
+	}, {
+		.virtual        = (unsigned long)S5P_VA_GDL,
+		.pfn            = __phys_to_pfn(EXYNOS4_PA_GDL),
+		.length         = SZ_4K,
+		.type           = MT_DEVICE,
+	}, {
+		.virtual        = (unsigned long)S5P_VA_GDR,
+		.pfn            = __phys_to_pfn(EXYNOS4_PA_GDR),
+		.length         = SZ_4K,
+		.type           = MT_DEVICE,
+	},
+};
+
+static struct map_desc exynos4210_iodesc[] __initdata = {
+	{
+		.virtual	= (unsigned long)S5P_VA_DMC0,
+		.pfn		= __phys_to_pfn(EXYNOS4_PA_DMC0),
+		.length		= SZ_64K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_DMC1,
+		.pfn		= __phys_to_pfn(EXYNOS4_PA_DMC1),
+		.length		= SZ_64K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_SYSRAM_NS,
+		.pfn		= __phys_to_pfn(EXYNOS4_PA_SYSRAM_NS),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	},
+};
+
+static struct map_desc exynos4210_iodesc_rev_0[] __initdata = {
+	{
+		.virtual	= (unsigned long)S5P_VA_SYSRAM,
+		.pfn		= __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	},
+};
+
+static struct map_desc exynos4210_iodesc_rev_1[] __initdata = {
+	{
+		.virtual	= (unsigned long)S5P_VA_SYSRAM,
+		.pfn		= __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	},
+};
+
+static struct map_desc exynos4212_iodesc[] __initdata = {
+	{
+		.virtual	= (unsigned long)S5P_VA_DMC0,
+		.pfn		= __phys_to_pfn(EXYNOS4_PA_DMC0_4212),
+		.length		= SZ_64K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_DMC1,
+		.pfn		= __phys_to_pfn(EXYNOS4_PA_DMC1_4212),
+		.length		= SZ_64K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_SYSRAM,
+		.pfn		= __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_SYSRAM_NS,
+		.pfn		= __phys_to_pfn(EXYNOS4_PA_SYSRAM_NS_4212),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	},
+};
+
+static void exynos4_idle(void)
+{
+	if (!need_resched())
+		cpu_do_idle();
+
+	local_irq_enable();
+}
+
+/*
+ * exynos4_map_io
+ *
+ * register the standard cpu IO areas
+ */
+void __init exynos4_map_io(void)
+{
+	iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
+
+	if (soc_is_exynos4210()) {
+		iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc));
+		if (samsung_rev() == EXYNOS4210_REV_0)
+			iotable_init(exynos4210_iodesc_rev_0,
+				ARRAY_SIZE(exynos4210_iodesc_rev_0));
+		else
+			iotable_init(exynos4210_iodesc_rev_1,
+				ARRAY_SIZE(exynos4210_iodesc_rev_1));
+	} else {
+		iotable_init(exynos4212_iodesc, ARRAY_SIZE(exynos4212_iodesc));
+	}
+
+#ifdef CONFIG_S3C_DEV_HSMMC
+	exynos4_default_sdhci0();
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC1
+	exynos4_default_sdhci1();
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC2
+	exynos4_default_sdhci2();
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC3
+	exynos4_default_sdhci3();
+#endif
+#ifdef CONFIG_EXYNOS4_DEV_MSHC
+	exynos4_default_mshci();
+#endif
+	exynos4_i2sv3_setup_resource();
+
+	s3c_fimc_setname(0, "exynos4-fimc");
+	s3c_fimc_setname(1, "exynos4-fimc");
+	s3c_fimc_setname(2, "exynos4-fimc");
+	s3c_fimc_setname(3, "exynos4-fimc");
+#ifdef CONFIG_S3C_DEV_RTC
+	s3c_rtc_setname("exynos-rtc");
+#endif
+#ifdef CONFIG_FB_S3C
+	s5p_fb_setname(0, "exynos4-fb");	/* FIMD0 */
+#endif
+	if (soc_is_exynos4210())
+		s3c_adc_setname("samsung-adc-v3");
+	else
+		s3c_adc_setname("samsung-adc-v4");
+
+	s5p_hdmi_setname("exynos4-hdmi");
+
+	/* The I2C bus controllers are directly compatible with s3c2440 */
+	s3c_i2c0_setname("s3c2440-i2c");
+	s3c_i2c1_setname("s3c2440-i2c");
+	s3c_i2c2_setname("s3c2440-i2c");
+
+#ifdef CONFIG_S5P_DEV_ACE
+	s5p_ace_setname("exynos4-ace");
+#endif
+}
+
+void __init exynos4_init_clocks(int xtal)
+{
+	printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
+
+	s3c24xx_register_baseclocks(xtal);
+
+	if (soc_is_exynos4210())
+		exynos4210_register_clocks();
+	else
+		exynos4212_register_clocks();
+
+	s5p_register_clocks(xtal);
+	exynos4_register_clocks();
+	exynos4_setup_clocks();
+}
+
+#define COMBINER_MAP(x)	((x < 16) ? IRQ_SPI(x) :	\
+			(x == 16) ? IRQ_SPI(107) :	\
+			(x == 17) ? IRQ_SPI(108) :	\
+			(x == 18) ? IRQ_SPI(48) :	\
+			(x == 19) ? IRQ_SPI(49) : 0)
+
+void __init exynos4_init_irq(void)
+{
+	int irq;
+
+	gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
+
+	gic_init(0, IRQ_PPI_MCT_L, S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
+	gic_arch_extn.irq_set_wake = s3c_irq_wake;
+
+	for (irq = 0; irq < COMMON_COMBINER_NR; irq++) {
+		combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
+				COMBINER_IRQ(irq, 0));
+		combiner_cascade_irq(irq, COMBINER_MAP(irq));
+	}
+
+	if (soc_is_exynos4412() && (samsung_rev() >= EXYNOS4412_REV_1_0)) {
+		for (irq = COMMON_COMBINER_NR; irq < MAX_COMBINER_NR; irq++) {
+			combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
+					COMBINER_IRQ(irq, 0));
+			combiner_cascade_irq(irq, COMBINER_MAP(irq));
+		}
+	}
+
+	/* The parameters of s5p_init_irq() are for VIC init.
+	 * Theses parameters should be NULL and 0 because EXYNOS4
+	 * uses GIC instead of VIC.
+	 */
+	s5p_init_irq(NULL, 0);
+}
+
+struct sysdev_class exynos4_sysclass = {
+	.name	= "exynos4-core",
+};
+
+static struct sys_device exynos4_sysdev = {
+	.cls	= &exynos4_sysclass,
+};
+
+static int __init exynos4_core_init(void)
+{
+	return sysdev_class_register(&exynos4_sysclass);
+}
+
+core_initcall(exynos4_core_init);
+
+#ifdef CONFIG_CACHE_L2X0
+#ifdef CONFIG_ARM_TRUSTZONE
+#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
+static void exynos4_l2x0_set_debug(unsigned long val)
+{
+	exynos_smc(SMC_CMD_L2X0DEBUG, val, 0, 0);
+}
+#endif
+#endif
+
+static int __init exynos4_l2x0_cache_init(void)
+{
+	u32 tag_latency = 0x110;
+	u32 data_latency = soc_is_exynos4210() ? 0x110 : 0x120;
+	u32 prefetch = (soc_is_exynos4412() &&
+			samsung_rev() >= EXYNOS4412_REV_1_0) ?
+			0x71000007 : 0x30000007;
+	u32 aux_val = 0x7C470001;
+	u32 aux_mask = 0xC200FFFF;
+
+#ifdef CONFIG_ARM_TRUSTZONE
+	exynos_smc(SMC_CMD_L2X0SETUP1, tag_latency, data_latency, prefetch);
+	exynos_smc(SMC_CMD_L2X0SETUP2,
+		   L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
+		   aux_val, aux_mask);
+	exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0);
+	exynos_smc(SMC_CMD_L2X0CTRL, 1, 0, 0);
+#else
+	__raw_writel(tag_latency, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
+	__raw_writel(data_latency, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
+	__raw_writel(prefetch, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
+	__raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
+		     S5P_VA_L2CC + L2X0_POWER_CTRL);
+#endif
+
+	l2x0_init(S5P_VA_L2CC, aux_val, aux_mask);
+
+#ifdef CONFIG_ARM_TRUSTZONE
+#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
+	outer_cache.set_debug = exynos4_l2x0_set_debug;
+#endif
+#endif
+	/* Enable the full line of zero */
+	enable_cache_foz();
+	return 0;
+}
+
+//early_initcall(exynos4_l2x0_cache_init);
+early_initcall(exynos4_l2x0_cache_init);
+#endif
+
+static void exynos4_sw_reset(void)
+{
+	int count = 3;
+
+	while (count--) {
+		__raw_writel(0x1, S5P_SWRESET);
+		mdelay(500);
+	}
+}
+
+static void __iomem *exynos4_pmu_init_zero[] = {
+	S5P_CMU_RESET_ISP_SYS,
+	S5P_CMU_SYSCLK_ISP_SYS,
+};
+
+int __init exynos4_init(void)
+{
+	unsigned int value;
+	unsigned int tmp;
+	unsigned int i;
+
+	printk(KERN_INFO "EXYNOS4: Initializing architecture\n");
+
+	/* set idle function */
+	pm_idle = exynos4_idle;
+
+	/*
+	 * on exynos4x12, CMU reset system power register should to be set 0x0
+	 */
+	if (!soc_is_exynos4210()) {
+		for (i = 0; i < ARRAY_SIZE(exynos4_pmu_init_zero); i++)
+			__raw_writel(0x0, exynos4_pmu_init_zero[i]);
+	}
+
+	/* set sw_reset function */
+	s5p_reset_hook = exynos4_sw_reset;
+
+	/* Disable auto wakeup from power off mode */
+	for (i = 0; i < num_possible_cpus(); i++) {
+		tmp = __raw_readl(S5P_ARM_CORE_OPTION(i));
+		tmp &= ~S5P_CORE_OPTION_DIS;
+		__raw_writel(tmp, S5P_ARM_CORE_OPTION(i));
+	}
+
+	if (soc_is_exynos4212() || soc_is_exynos4412()) {
+		value = __raw_readl(S5P_AUTOMATIC_WDT_RESET_DISABLE);
+		value &= ~S5P_SYS_WDTRESET;
+		__raw_writel(value, S5P_AUTOMATIC_WDT_RESET_DISABLE);
+		value = __raw_readl(S5P_MASK_WDT_RESET_REQUEST);
+		value &= ~S5P_SYS_WDTRESET;
+		__raw_writel(value, S5P_MASK_WDT_RESET_REQUEST);
+	}
+
+	return sysdev_register(&exynos4_sysdev);
+}
diff --git a/arch/arm/mach-exynos/cpu-exynos5.c b/arch/arm/mach-exynos/cpu-exynos5.c
new file mode 100644
index 0000000..87f2bbd
--- /dev/null
+++ b/arch/arm/mach-exynos/cpu-exynos5.c
@@ -0,0 +1,381 @@
+/* linux/arch/arm/mach-exynos/cpu-exynos5.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/sched.h>
+#include <linux/sysdev.h>
+#include <linux/delay.h>
+
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/proc-fns.h>
+
+#include <plat/cpu.h>
+#include <plat/clock.h>
+#include <plat/devs.h>
+#include <plat/fb-core.h>
+#include <plat/exynos5.h>
+#include <plat/sdhci.h>
+#include <plat/pm.h>
+#include <plat/iic-core.h>
+#include <plat/tv-core.h>
+#include <plat/ace-core.h>
+#include <plat/reset.h>
+#include <plat/rtc-core.h>
+#include <plat/adc-core.h>
+
+#include <mach/regs-irq.h>
+#include <mach/regs-pmu.h>
+#include <mach/regs-pmu5.h>
+#include <mach/smc.h>
+
+unsigned int gic_bank_offset __read_mostly;
+
+extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
+			 unsigned int irq_start);
+extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
+
+/* Initial IO mappings */
+static struct map_desc exynos5_iodesc[] __initdata = {
+	{
+		.virtual	= (unsigned long)S5P_VA_SYSTIMER,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_SYSTIMER),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual        = (unsigned long)S5P_VA_SYSRAM,
+		.pfn            = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
+		.length         = SZ_4K,
+		.type           = MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_CMU,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_CMU),
+		.length		= 144 * SZ_1K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_PMU,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_PMU),
+		.length		= SZ_64K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_COMBINER_BASE,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_COMBINER),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S3C_VA_UART,
+		.pfn		= __phys_to_pfn(S3C_PA_UART),
+		.length		= SZ_512K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_GPIO1,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_GPIO1),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_GPIO2,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_GPIO2),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_GPIO3,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_GPIO3),
+		.length		= SZ_256,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_GPIO4,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_GPIO4),
+		.length		= SZ_256,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_AUDSS,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_AUDSS),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual        = (unsigned long)S3C_VA_USB_HSPHY,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_HSPHY),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual        = (unsigned long)S5P_VA_SS_PHY,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_SS_PHY),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+#ifdef CONFIG_ARM_TRUSTZONE
+	}, {
+		.virtual	= (unsigned long)S5P_VA_SYSRAM_NS,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_SYSRAM_NS),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+#endif
+	}, {
+		.virtual        = (unsigned long)S5P_VA_PPMU_CPU,
+		.pfn            = __phys_to_pfn(EXYNOS5_PA_PPMU_CPU),
+		.length         = SZ_8K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual        = (unsigned long)S5P_VA_PPMU_DDR_C,
+		.pfn            = __phys_to_pfn(EXYNOS5_PA_PPMU_DDR_C),
+		.length         = SZ_8K,
+		.type           = MT_DEVICE,
+	}, {
+		.virtual        = (unsigned long)S5P_VA_PPMU_DDR_R1,
+		.pfn            = __phys_to_pfn(EXYNOS5_PA_PPMU_DDR_R1),
+		.length         = SZ_8K,
+		.type           = MT_DEVICE,
+	}, {
+		.virtual        = (unsigned long)S5P_VA_PPMU_DDR_L,
+		.pfn            = __phys_to_pfn(EXYNOS5_PA_PPMU_DDR_L),
+		.length         = SZ_8K,
+		.type           = MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_PPMU_RIGHT0_BUS,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_PPMU_RIGHT0_BUS),
+		.length		= SZ_8K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_FIMCLITE0,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_FIMC_LITE0),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_FIMCLITE1,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_FIMC_LITE1),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_FIMCLITE2,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_FIMC_LITE2),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_MIPICSI0,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_MIPI_CSIS0),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_MIPICSI1,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_MIPI_CSIS1),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_DMC0,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_DMC),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	},
+};
+
+static struct map_desc exynos5250_rev_0_iodesc[] __initdata = {
+	{
+		.virtual	= (unsigned long)S5P_VA_GIC_CPU,
+		.pfn		= __phys_to_pfn(EXYNOS5250_REV0_PA_GIC_CPU),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_GIC_DIST,
+		.pfn		= __phys_to_pfn(EXYNOS5250_REV0_PA_GIC_DIST),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	},
+};
+
+static struct map_desc exynos5250_rev_1_iodesc[] __initdata = {
+	{
+		.virtual	= (unsigned long)S5P_VA_GIC_CPU,
+		.pfn		= __phys_to_pfn(EXYNOS5250_REV1_PA_GIC_CPU),
+		.length		= SZ_8K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_GIC_DIST,
+		.pfn		= __phys_to_pfn(EXYNOS5250_REV1_PA_GIC_DIST),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	},
+};
+
+static void exynos5_idle(void)
+{
+	if (!need_resched())
+		cpu_do_idle();
+
+	local_irq_enable();
+}
+
+/*
+ * exynos5_map_io
+ *
+ * register the standard cpu IO areas
+ */
+void __init exynos5_map_io(void)
+{
+	iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
+
+	if (soc_is_exynos5250()) {
+		if (samsung_rev() >= EXYNOS5250_REV_1_0)
+			iotable_init(exynos5250_rev_1_iodesc,
+				ARRAY_SIZE(exynos5250_rev_1_iodesc));
+		else
+			iotable_init(exynos5250_rev_0_iodesc,
+				ARRAY_SIZE(exynos5250_rev_0_iodesc));
+	}
+
+#ifdef CONFIG_S3C_DEV_HSMMC
+	exynos5_default_sdhci0();
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC1
+	exynos5_default_sdhci1();
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC2
+	exynos5_default_sdhci2();
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC3
+	exynos5_default_sdhci3();
+#endif
+#ifdef CONFIG_S3C_DEV_RTC
+	s3c_rtc_setname("exynos-rtc");
+#endif
+
+	s5p_fb_setname(1, "exynos5-fb");        /* FIMD1 */
+
+	s3c_adc_setname("samsung-adc-v4");
+
+	s5p_hdmi_setname("exynos5-hdmi");
+
+	/* The I2C bus controllers are directly compatible with s3c2440 */
+	s3c_i2c0_setname("s3c2440-i2c");
+	s3c_i2c1_setname("s3c2440-i2c");
+	s3c_i2c2_setname("s3c2440-i2c");
+
+#ifdef CONFIG_S5P_DEV_ACE
+	s5p_ace_setname("exynos4-ace");
+#endif
+}
+
+void __init exynos5_init_clocks(int xtal)
+{
+	printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
+
+	s3c24xx_register_baseclocks(xtal);
+
+	s5p_register_clocks(xtal);
+	exynos5_register_clocks();
+	exynos5_setup_clocks();
+}
+
+void __init exynos5_init_irq(void)
+{
+	int irq;
+
+	gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
+	gic_arch_extn.irq_set_wake = s3c_irq_wake;
+
+	for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
+		combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
+				COMBINER_IRQ(irq, 0));
+		combiner_cascade_irq(irq, IRQ_SPI(irq));
+	}
+
+	/* The parameters of s5p_init_irq() are for VIC init.
+	 * Theses parameters should be NULL and 0 because EXYNOS5
+	 * uses GIC instead of VIC.
+	 */
+	s5p_init_irq(NULL, 0);
+}
+
+struct sysdev_class exynos5_sysclass = {
+	.name	= "exynos5-core",
+};
+
+static struct sys_device exynos5_sysdev = {
+	.cls	= &exynos5_sysclass,
+};
+
+static int __init exynos5_core_init(void)
+{
+	return sysdev_class_register(&exynos5_sysclass);
+}
+
+core_initcall(exynos5_core_init);
+
+#define TAG_RAM_SETUP_SHIFT		(9)
+#define DATA_RAM_SETUP_SHIFT		(5)
+#define TAG_RAM_LATENCY_SHIFT		(6)
+#define DATA_RAM_LATENCY_SHIFT		(0)
+
+static int __init exynos5_l2_cache_init(void)
+{
+	unsigned int val;
+
+	if (soc_is_exynos5250()) {
+		asm volatile(
+			"mrc p15, 0, %0, c1, c0, 0\n"
+			"bic %0, %0, #(1 << 2)\n"	/* cache disable */
+			"mcr p15, 0, %0, c1, c0, 0\n"
+			"mrc p15, 1, %0, c9, c0, 2\n"
+			: "=r"(val));
+
+		val |= (1 << TAG_RAM_SETUP_SHIFT) |
+			(1 << DATA_RAM_SETUP_SHIFT) |
+			(2 << TAG_RAM_LATENCY_SHIFT) |
+			(2 << DATA_RAM_LATENCY_SHIFT);
+
+#ifdef CONFIG_ARM_TRUSTZONE
+		exynos_smc(SMC_CMD_REG, SMC_REG_ID_CP15(9, 1, 0, 2), val, 0);
+#else
+		asm volatile("mcr p15, 1, %0, c9, c0, 2\n": : "r"(val));
+#endif
+		asm volatile(
+			"mrc p15, 0, %0, c1, c0, 0\n"
+			"orr %0, %0, #(1 << 2)\n"	/* cache enable */
+			"mcr p15, 0, %0, c1, c0, 0\n"
+			: : "r"(val));
+	}
+
+	return 0;
+}
+
+early_initcall(exynos5_l2_cache_init);
+
+static void exynos5_sw_reset(void)
+{
+	int count = 3;
+
+	while (count--) {
+		__raw_writel(0x1, S5P_SWRESET);
+		mdelay(500);
+	}
+}
+
+int __init exynos5_init(void)
+{
+	unsigned int value;
+	printk(KERN_INFO "EXYNOS5: Initializing architecture\n");
+
+	/* set idle function */
+	pm_idle = exynos5_idle;
+
+	/* set sw_reset function */
+	s5p_reset_hook = exynos5_sw_reset;
+
+	value = __raw_readl(EXYNOS5_AUTOMATIC_WDT_RESET_DISABLE);
+	value &= ~EXYNOS5_SYS_WDTRESET;
+	__raw_writel(value, EXYNOS5_AUTOMATIC_WDT_RESET_DISABLE);
+	value = __raw_readl(EXYNOS5_MASK_WDT_RESET_REQUEST);
+	value &= ~EXYNOS5_SYS_WDTRESET;
+	__raw_writel(value, EXYNOS5_MASK_WDT_RESET_REQUEST);
+
+	if (soc_is_exynos5250() && samsung_rev() >= EXYNOS5250_REV_1_0) {
+		__raw_writel(0x1, EXYNOS5_ADC_PHY_CONTROL);
+	}
+
+	return sysdev_register(&exynos5_sysdev);
+}
diff --git a/arch/arm/mach-exynos/cpufreq-4210.c b/arch/arm/mach-exynos/cpufreq-4210.c
new file mode 100644
index 0000000..7b93045
--- /dev/null
+++ b/arch/arm/mach-exynos/cpufreq-4210.c
@@ -0,0 +1,453 @@
+/* linux/arch/arm/mach-exynos/cpufreq-4210.c
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS4210 - CPU frequency scaling support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/cpufreq.h>
+
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/cpufreq.h>
+#include <mach/asv.h>
+#include <mach/sec_debug.h>
+
+#include <plat/clock.h>
+
+#define CPUFREQ_LEVEL_END	L6
+
+static int max_support_idx;
+static int min_support_idx = (CPUFREQ_LEVEL_END - 1);
+static struct clk *cpu_clk;
+static struct clk *moutcore;
+static struct clk *mout_mpll;
+static struct clk *mout_apll;
+
+struct cpufreq_clkdiv {
+	unsigned int	index;
+	unsigned int	clkdiv;
+};
+
+static unsigned int exynos4210_volt_table[CPUFREQ_LEVEL_END];
+
+static struct cpufreq_frequency_table exynos4210_freq_table[] = {
+	{L0, 1400*1000},
+	{L1, 1200*1000},
+	{L2, 1000*1000},
+	{L3, 800*1000},
+	{L4, 500*1000},
+	{L5, 200*1000},
+	{0, CPUFREQ_TABLE_END},
+};
+
+static struct cpufreq_clkdiv exynos4210_clkdiv_table[] = {
+	{L0, 0},
+	{L1, 0},
+	{L2, 0},
+	{L3, 0},
+	{L4, 0},
+	{L5, 0},
+};
+
+static unsigned int clkdiv_cpu0[CPUFREQ_LEVEL_END][7] = {
+	/*
+	 * Clock divider value for following
+	 * { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH,
+	 *		DIVATB, DIVPCLK_DBG, DIVAPLL }
+	 */
+	/* ARM L0: 1400MHz */
+	{ 0, 3, 7, 3, 4, 1, 7 },
+
+	/* ARM L1: 1200MHz */
+	{ 0, 3, 7, 3, 4, 1, 7 },
+
+	/* ARM L2: 1000MHz */
+	{ 0, 3, 7, 3, 4, 1, 7 },
+
+	/* ARM L3: 800MHz */
+	{ 0, 3, 7, 3, 3, 1, 7 },
+
+	/* ARM L4: 500MHz */
+	{ 0, 3, 7, 3, 3, 1, 7 },
+
+	/* ARM L5: 200MHz */
+	{ 0, 1, 3, 1, 3, 1, 0 },
+};
+
+static unsigned int clkdiv_cpu1[CPUFREQ_LEVEL_END][2] = {
+	/* Clock divider value for following
+	 * { DIVCOPY, DIVHPM }
+	 */
+	/* ARM L0: 1400MHz */
+	{ 5, 0 },
+
+	/* ARM L1: 1200MHz */
+	{ 5, 0 },
+
+	/* ARM L2: 1000MHz */
+	{ 4, 0 },
+
+	/* ARM L3: 800MHz */
+	{ 3, 0 },
+
+	/* ARM L4: 500MHz */
+	{ 3, 0 },
+
+	/* ARM L5: 200MHz */
+	{ 3, 0 },
+};
+
+static unsigned int exynos4_apll_pms_table[CPUFREQ_LEVEL_END] = {
+	/* APLL FOUT L0: 1400MHz */
+	((350<<16)|(6<<8)|(0x1)),
+
+	/* APLL FOUT L1: 1200MHz */
+	((150<<16)|(3<<8)|(0x1)),
+
+	/* APLL FOUT L2: 1000MHz */
+	((250<<16)|(6<<8)|(0x1)),
+
+	/* APLL FOUT L3: 800MHz */
+	((200<<16)|(6<<8)|(0x1)),
+
+	/* APLL FOUT L4: 500MHz */
+	((250<<16)|(6<<8)|(0x2)),
+
+	/* APLL FOUT L5: 200MHz */
+	((200<<16)|(6<<8)|(0x3)),
+};
+
+/*
+ * ASV group voltage table
+ */
+
+static const unsigned int asv_voltage_A[CPUFREQ_LEVEL_END][8] = {
+	/*
+	 *	   SS, A1, A2, B1, B2, C1, C2, D
+	 * @Dummy:
+	 * @1200 :
+	 * @1000 :
+	 * @800	 :	ASV_VOLTAGE_TABLE
+	 * @500  :
+	 * @200  :
+	 */
+	{ 0, 0, 0, 0, 0, 0, 0, 0 },
+	{ 1350000, 1350000, 1300000, 1275000, 1250000, 1225000, 1200000, 1175000 },
+	{ 1300000, 1250000, 1200000, 1175000, 1150000, 1125000, 1100000, 1075000 },
+	{ 1200000, 1150000, 1100000, 1075000, 1050000, 1025000, 1000000, 975000 },
+	{ 1100000, 1050000, 1000000, 975000, 975000, 950000, 925000, 925000 },
+	{ 1050000, 1000000, 975000, 950000, 950000, 925000, 925000, 925000 },
+
+};
+
+static const unsigned int asv_voltage_B[CPUFREQ_LEVEL_END][5] = {
+	/*
+	 *	   S, A, B, C, D
+	 * @1400 :
+	 * @1200 :
+	 * @1000 :
+	 * @800	 :	ASV_VOLTAGE_TABLE
+	 * @500	 :
+	 * @200	 :
+	 */
+	{ 1350000, 1350000, 1300000, 1250000, 1225000 },
+	{ 1325000, 1275000, 1225000, 1175000, 1150000 },
+	{ 1225000, 1175000, 1125000, 1075000, 1050000 },
+	{ 1150000, 1100000, 1050000, 1000000, 975000 },
+	{ 1050000, 1000000, 950000, 950000, 950000 },
+	{ 1025000, 975000, 950000, 950000, 950000 },
+
+};
+
+static void set_clkdiv(unsigned int div_index)
+{
+	unsigned int tmp;
+	/* Change Divider - CPU0 */
+
+	tmp = exynos4210_clkdiv_table[div_index].clkdiv;
+
+	__raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
+
+	do {
+		tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU);
+	} while (tmp & 0x1111111);
+
+	/* Change Divider - CPU1 */
+	tmp = __raw_readl(EXYNOS4_CLKDIV_CPU1);
+
+	tmp &= ~((0x7 << 4) | (0x7));
+
+	tmp |= ((clkdiv_cpu1[div_index][0] << 4) |
+		(clkdiv_cpu1[div_index][1] << 0));
+
+	__raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
+
+	do {
+		tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU1);
+	} while (tmp & 0x11);
+}
+
+static void set_apll(unsigned int new_index,
+			     unsigned int old_index)
+{
+	unsigned int tmp;
+
+	/* 1. MUX_CORE_SEL = MPLL,
+	 * ARMCLK uses MPLL for lock time */
+	if (clk_set_parent(moutcore, mout_mpll))
+		printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
+				mout_mpll->name, moutcore->name);
+
+	do {
+		tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU)
+			>> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
+		tmp &= 0x7;
+	} while (tmp != 0x2);
+
+	/* 2. Set APLL Lock time */
+	__raw_writel(EXYNOS4_APLL_LOCKTIME, EXYNOS4_APLL_LOCK);
+
+	/* 3. Change PLL PMS values */
+	tmp = __raw_readl(EXYNOS4_APLL_CON0);
+	tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
+	tmp |= exynos4_apll_pms_table[new_index];
+	__raw_writel(tmp, EXYNOS4_APLL_CON0);
+
+	/* 4. wait_lock_time */
+	do {
+		tmp = __raw_readl(EXYNOS4_APLL_CON0);
+	} while (!(tmp & (0x1 << EXYNOS4_APLLCON0_LOCKED_SHIFT)));
+
+	/* 5. MUX_CORE_SEL = APLL */
+	if (clk_set_parent(moutcore, mout_apll))
+		printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
+				mout_apll->name, moutcore->name);
+
+	do {
+		tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU);
+		tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
+	} while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
+
+}
+
+bool exynos4210_pms_change(unsigned int old_index, unsigned int new_index)
+{
+	unsigned int old_pm = (exynos4_apll_pms_table[old_index] >> 8);
+	unsigned int new_pm = (exynos4_apll_pms_table[new_index] >> 8);
+
+	return (old_pm == new_pm) ? 0 : 1;
+}
+
+static void exynos4210_set_frequency(unsigned int old_index,
+				  unsigned int new_index)
+{
+	unsigned int tmp;
+
+	sec_debug_aux_log(SEC_DEBUG_AUXLOG_CPU_BUS_CLOCK_CHANGE,
+			"%s: old_index=%d, new_index=%d(%ps)",
+			__func__, old_index, new_index,
+			__builtin_return_address(0));
+
+	if (old_index > new_index) {
+		if (!exynos4210_pms_change(old_index, new_index)) {
+			/* 1. Change the system clock divider values */
+			set_clkdiv(new_index);
+			/* 2. Change just s value in apll m,p,s value */
+			tmp = __raw_readl(EXYNOS4_APLL_CON0);
+			tmp &= ~(0x7 << 0);
+			tmp |= (exynos4_apll_pms_table[new_index] & 0x7);
+			__raw_writel(tmp, EXYNOS4_APLL_CON0);
+
+		} else {
+			/* Clock Configuration Procedure */
+			/* 1. Change the system clock divider values */
+			set_clkdiv(new_index);
+			/* 2. Change the apll m,p,s value */
+			set_apll(new_index, old_index);
+		}
+	} else if (old_index < new_index) {
+		if (!exynos4210_pms_change(old_index, new_index)) {
+			/* 1. Change just s value in apll m,p,s value */
+			tmp = __raw_readl(EXYNOS4_APLL_CON0);
+			tmp &= ~(0x7 << 0);
+			tmp |= (exynos4_apll_pms_table[new_index] & 0x7);
+			__raw_writel(tmp, EXYNOS4_APLL_CON0);
+			/* 2. Change the system clock divider values */
+			set_clkdiv(new_index);
+		} else {
+			/* Clock Configuration Procedure */
+			/* 1. Change the apll m,p,s value */
+			set_apll(new_index, old_index);
+			/* 2. Change the system clock divider values */
+			set_clkdiv(new_index);
+		}
+	}
+}
+
+static void __init set_volt_table(void)
+{
+	unsigned int asv_group = 0;
+	bool for_1400 = false, for_1200 = false, for_1000 = false;
+	unsigned int tmp;
+	unsigned int i;
+
+	tmp = exynos_result_of_asv;
+
+	asv_group = (tmp & 0xF);
+
+	switch (tmp  & (SUPPORT_FREQ_MASK << SUPPORT_FREQ_SHIFT)) {
+	case SUPPORT_1400MHZ:
+#if defined(CONFIG_EXYNOS4210_1200MHZ_SUPPORT)
+		for_1200 = true;
+		max_support_idx = L1;
+#else
+		for_1400 = true;
+		max_support_idx = L0;
+#endif
+		break;
+	case SUPPORT_1200MHZ:
+		for_1200 = true;
+		max_support_idx = L1;
+		break;
+	case SUPPORT_1000MHZ:
+		for_1000 = true;
+		max_support_idx = L2;
+		break;
+	default:
+		for_1000 = true;
+		max_support_idx = L2;
+		break;
+	}
+
+	/*
+	 * If ASV group is S, can not support 1.4GHz
+	 * Disabling table entry
+	 */
+	if ((asv_group == 0) || !for_1400)
+		exynos4210_freq_table[L0].frequency = CPUFREQ_ENTRY_INVALID;
+
+	if (for_1000)
+		exynos4210_freq_table[L1].frequency = CPUFREQ_ENTRY_INVALID;
+
+	printk(KERN_INFO "DVFS : VDD_ARM Voltage table set with %d Group\n", asv_group);
+
+	if (for_1400) {
+		for (i = 0 ; i < CPUFREQ_LEVEL_END ; i++) {
+				exynos4210_volt_table[i] =
+					asv_voltage_B[i][asv_group];
+		}
+	} else {
+		for (i = 0 ; i < CPUFREQ_LEVEL_END ; i++) {
+				exynos4210_volt_table[i] =
+					asv_voltage_A[i][asv_group];
+		}
+	}
+}
+
+#if defined(CONFIG_REGULATOR_MAX8997)
+extern void max8997_set_arm_voltage_table(int *voltage_table, int arr_size);
+
+static void exynos4210_cpufreq_set_pmic_vol_table(void)
+{
+	int vol_table[CPUFREQ_LEVEL_END];
+	int i;
+
+	for (i = 0; i < CPUFREQ_LEVEL_END; i++)
+		vol_table[i] = exynos4210_volt_table[i];
+
+	max8997_set_arm_voltage_table(vol_table, CPUFREQ_LEVEL_END);
+}
+#else
+static void exynos4210_cpufreq_set_pmic_vol_table(void)
+{
+	/*Do Nothing*/
+}
+#endif /* CONFIG_MACH_U1 */
+
+
+int exynos4210_cpufreq_init(struct exynos_dvfs_info *info)
+{
+	int i;
+	unsigned int tmp;
+	unsigned long rate;
+
+	set_volt_table();
+	exynos4210_cpufreq_set_pmic_vol_table();
+
+	cpu_clk = clk_get(NULL, "armclk");
+	if (IS_ERR(cpu_clk))
+		return PTR_ERR(cpu_clk);
+
+	moutcore = clk_get(NULL, "moutcore");
+	if (IS_ERR(moutcore))
+		goto err_moutcore;
+
+	mout_mpll = clk_get(NULL, "mout_mpll");
+	if (IS_ERR(mout_mpll))
+		goto err_mout_mpll;
+
+	rate = clk_get_rate(mout_mpll) / 1000;
+
+	mout_apll = clk_get(NULL, "mout_apll");
+	if (IS_ERR(mout_apll))
+		goto err_mout_apll;
+
+	tmp = __raw_readl(EXYNOS4_CLKDIV_CPU);
+
+	for (i = L0; i <  CPUFREQ_LEVEL_END; i++) {
+		tmp &= ~(EXYNOS4_CLKDIV_CPU0_CORE_MASK |
+			EXYNOS4_CLKDIV_CPU0_COREM0_MASK |
+			EXYNOS4_CLKDIV_CPU0_COREM1_MASK |
+			EXYNOS4_CLKDIV_CPU0_PERIPH_MASK |
+			EXYNOS4_CLKDIV_CPU0_ATB_MASK |
+			EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK |
+			EXYNOS4_CLKDIV_CPU0_APLL_MASK);
+
+		tmp |= ((clkdiv_cpu0[i][0] << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT) |
+			(clkdiv_cpu0[i][1] << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT) |
+			(clkdiv_cpu0[i][2] << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT) |
+			(clkdiv_cpu0[i][3] << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT) |
+			(clkdiv_cpu0[i][4] << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT) |
+			(clkdiv_cpu0[i][5] << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT) |
+			(clkdiv_cpu0[i][6] << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT));
+
+		exynos4210_clkdiv_table[i].clkdiv = tmp;
+	}
+
+	info->mpll_freq_khz = rate;
+	info->pm_lock_idx = L3;
+	info->pll_safe_idx = L2;
+	info->max_support_idx = max_support_idx;
+	info->min_support_idx = min_support_idx;
+	info->cpu_clk = cpu_clk;
+	info->volt_table = exynos4210_volt_table;
+	info->freq_table = exynos4210_freq_table;
+	info->set_freq = exynos4210_set_frequency;
+	info->need_apll_change = exynos4210_pms_change;
+
+	return 0;
+
+err_mout_apll:
+	if (!IS_ERR(mout_mpll))
+		clk_put(mout_mpll);
+err_mout_mpll:
+	if (!IS_ERR(moutcore))
+		clk_put(moutcore);
+err_moutcore:
+	if (!IS_ERR(cpu_clk))
+		clk_put(cpu_clk);
+
+	pr_debug("%s: failed initialization\n", __func__);
+	return -EINVAL;
+}
+EXPORT_SYMBOL(exynos4210_cpufreq_init);
diff --git a/arch/arm/mach-exynos/cpufreq-4x12.c b/arch/arm/mach-exynos/cpufreq-4x12.c
new file mode 100644
index 0000000..d5dd249
--- /dev/null
+++ b/arch/arm/mach-exynos/cpufreq-4x12.c
@@ -0,0 +1,736 @@
+/* linux/arch/arm/mach-exynos/cpufreq-4x12.c
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS4X12 - CPU frequency scaling support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/cpufreq.h>
+
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/pmu.h>
+#include <mach/cpufreq.h>
+#include <mach/asv.h>
+
+#include <plat/clock.h>
+#include <plat/cpu.h>
+
+#define CPUFREQ_LEVEL_END	(L13 + 1)
+
+#undef PRINT_DIV_VAL
+
+#undef ENABLE_CLKOUT
+
+static int max_support_idx;
+static int min_support_idx = (CPUFREQ_LEVEL_END - 1);
+static struct clk *cpu_clk;
+static struct clk *moutcore;
+static struct clk *mout_mpll;
+static struct clk *mout_apll;
+
+struct cpufreq_clkdiv {
+	unsigned int	index;
+	unsigned int	clkdiv;
+	unsigned int	clkdiv1;
+};
+
+static unsigned int exynos4x12_volt_table[CPUFREQ_LEVEL_END];
+
+static struct cpufreq_frequency_table exynos4x12_freq_table[] = {
+	{L0, 1500*1000},
+	{L1, 1400*1000},
+	{L2, 1300*1000},
+	{L3, 1200*1000},
+	{L4, 1100*1000},
+	{L5, 1000*1000},
+	{L6, 900*1000},
+	{L7, 800*1000},
+	{L8, 700*1000},
+	{L9, 600*1000},
+	{L10, 500*1000},
+	{L11, 400*1000},
+	{L12, 300*1000},
+	{L13, 200*1000},
+	{0, CPUFREQ_TABLE_END},
+};
+
+static struct cpufreq_clkdiv exynos4x12_clkdiv_table[CPUFREQ_LEVEL_END];
+
+static unsigned int clkdiv_cpu0_4212[CPUFREQ_LEVEL_END][8] = {
+	/*
+	 * Clock divider value for following
+	 * { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH,
+	 *		DIVATB, DIVPCLK_DBG, DIVAPLL, DIVCORE2 }
+	 */
+	/* ARM L0: 1500Mhz */
+	{ 0, 3, 7, 0, 6, 1, 2, 0 },
+
+	/* ARM L1: 1400Mhz */
+	{ 0, 3, 7, 0, 6, 1, 2, 0 },
+
+	/* ARM L2: 1300Mhz */
+	{ 0, 3, 7, 0, 5, 1, 2, 0 },
+
+	/* ARM L3: 1200Mhz */
+	{ 0, 3, 7, 0, 5, 1, 2, 0 },
+
+	/* ARM L4: 1100MHz */
+	{ 0, 3, 6, 0, 4, 1, 2, 0 },
+
+	/* ARM L5: 1000MHz */
+	{ 0, 2, 5, 0, 4, 1, 1, 0 },
+
+	/* ARM L6: 900MHz */
+	{ 0, 2, 5, 0, 3, 1, 1, 0 },
+
+	/* ARM L7: 800MHz */
+	{ 0, 2, 5, 0, 3, 1, 1, 0 },
+
+	/* ARM L8: 700MHz */
+	{ 0, 2, 4, 0, 3, 1, 1, 0 },
+
+	/* ARM L9: 600MHz */
+	{ 0, 2, 4, 0, 3, 1, 1, 0 },
+
+	/* ARM L10: 500MHz */
+	{ 0, 2, 4, 0, 3, 1, 1, 0 },
+
+	/* ARM L11: 400MHz */
+	{ 0, 2, 4, 0, 3, 1, 1, 0 },
+
+	/* ARM L12: 300MHz */
+	{ 0, 2, 4, 0, 2, 1, 1, 0 },
+
+	/* ARM L13: 200MHz */
+	{ 0, 1, 3, 0, 1, 1, 1, 0 },
+};
+
+static unsigned int clkdiv_cpu0_4412[CPUFREQ_LEVEL_END][8] = {
+	/*
+	 * Clock divider value for following
+	 * { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH,
+	 *		DIVATB, DIVPCLK_DBG, DIVAPLL, DIVCORE2 }
+	 */
+	/* ARM L0: 1500Mhz */
+	{ 0, 3, 7, 0, 6, 1, 2, 0 },
+
+	/* ARM L1: 1400Mhz */
+	{ 0, 3, 7, 0, 6, 1, 2, 0 },
+
+	/* ARM L2: 1300Mhz */
+	{ 0, 3, 7, 0, 5, 1, 2, 0 },
+
+	/* ARM L3: 1200Mhz */
+	{ 0, 3, 7, 0, 5, 1, 2, 0 },
+
+	/* ARM L4: 1100MHz */
+	{ 0, 3, 6, 0, 4, 1, 2, 0 },
+
+	/* ARM L5: 1000MHz */
+	{ 0, 2, 5, 0, 4, 1, 1, 0 },
+
+	/* ARM L6: 900MHz */
+	{ 0, 2, 5, 0, 3, 1, 1, 0 },
+
+	/* ARM L7: 800MHz */
+	{ 0, 2, 5, 0, 3, 1, 1, 0 },
+
+	/* ARM L8: 700MHz */
+	{ 0, 2, 4, 0, 3, 1, 1, 0 },
+
+	/* ARM L9: 600MHz */
+	{ 0, 2, 4, 0, 3, 1, 1, 0 },
+
+	/* ARM L10: 500MHz */
+	{ 0, 2, 4, 0, 3, 1, 1, 0 },
+
+	/* ARM L11: 400MHz */
+	{ 0, 2, 4, 0, 3, 1, 1, 0 },
+
+	/* ARM L12: 300MHz */
+	{ 0, 2, 4, 0, 2, 1, 1, 0 },
+
+	/* ARM L13: 200MHz */
+	{ 0, 1, 3, 0, 1, 1, 1, 0 },
+};
+
+static unsigned int clkdiv_cpu1_4212[CPUFREQ_LEVEL_END][2] = {
+	/* Clock divider value for following
+	 * { DIVCOPY, DIVHPM }
+	 */
+	/* ARM L0: 1500MHz */
+	{ 6, 0 },
+
+	/* ARM L1: 1400MHz */
+	{ 6, 0 },
+
+	/* ARM L2: 1300MHz */
+	{ 5, 0 },
+
+	/* ARM L3: 1200MHz */
+	{ 5, 0 },
+
+	/* ARM L4: 1100MHz */
+	{ 4, 0 },
+
+	/* ARM L5: 1000MHz */
+	{ 4, 0 },
+
+	/* ARM L6: 900MHz */
+	{ 3, 0 },
+
+	/* ARM L7: 800MHz */
+	{ 3, 0 },
+
+	/* ARM L8: 700MHz */
+	{ 3, 0 },
+
+	/* ARM L9: 600MHz */
+	{ 3, 0 },
+
+	/* ARM L10: 500MHz */
+	{ 3, 0 },
+
+	/* ARM L11: 400MHz */
+	{ 3, 0 },
+
+	/* ARM L12: 300MHz */
+	{ 3, 0 },
+
+	/* ARM L13: 200MHz */
+	{ 3, 0 },
+};
+
+static unsigned int clkdiv_cpu1_4412[CPUFREQ_LEVEL_END][3] = {
+	/* Clock divider value for following
+	 * { DIVCOPY, DIVHPM, DIVCORES }
+	 */
+	/* ARM L0: 1500MHz */
+	{ 6, 0, 7 },
+
+	/* ARM L1: 1400MHz */
+	{ 6, 0, 6 },
+
+	/* ARM L2: 1300MHz */
+	{ 5, 0, 6 },
+
+	/* ARM L3: 1200MHz */
+	{ 5, 0, 5 },
+
+	/* ARM L4: 1100MHz */
+	{ 4, 0, 5 },
+
+	/* ARM L5: 1000MHz */
+	{ 4, 0, 4 },
+
+	/* ARM L6: 900MHz */
+	{ 3, 0, 4 },
+
+	/* ARM L7: 800MHz */
+	{ 3, 0, 3 },
+
+	/* ARM L8: 700MHz */
+	{ 3, 0, 3 },
+
+	/* ARM L9: 600MHz */
+	{ 3, 0, 2 },
+
+	/* ARM L10: 500MHz */
+	{ 3, 0, 2 },
+
+	/* ARM L11: 400MHz */
+	{ 3, 0, 1 },
+
+	/* ARM L12: 300MHz */
+	{ 3, 0, 1 },
+
+	/* ARM L13: 200MHz */
+	{ 3, 0, 0 },
+};
+
+static unsigned int exynos4x12_apll_pms_table[CPUFREQ_LEVEL_END] = {
+	/* APLL FOUT L0: 1500MHz */
+	((250<<16)|(4<<8)|(0x0)),
+
+	/* APLL FOUT L1: 1400MHz */
+	((175<<16)|(3<<8)|(0x0)),
+
+	/* APLL FOUT L2: 1300MHz */
+	((325<<16)|(6<<8)|(0x0)),
+
+	/* APLL FOUT L3: 1200MHz */
+	((200<<16)|(4<<8)|(0x0)),
+
+	/* APLL FOUT L4: 1100MHz */
+	((275<<16)|(6<<8)|(0x0)),
+
+	/* APLL FOUT L5: 1000MHz */
+	((125<<16)|(3<<8)|(0x0)),
+
+	/* APLL FOUT L6: 900MHz */
+	((150<<16)|(4<<8)|(0x0)),
+
+	/* APLL FOUT L7: 800MHz */
+	((100<<16)|(3<<8)|(0x0)),
+
+	/* APLL FOUT L8: 700MHz */
+	((175<<16)|(3<<8)|(0x1)),
+
+	/* APLL FOUT L9: 600MHz */
+	((200<<16)|(4<<8)|(0x1)),
+
+	/* APLL FOUT L10: 500MHz */
+	((125<<16)|(3<<8)|(0x1)),
+
+	/* APLL FOUT L11 400MHz */
+	((100<<16)|(3<<8)|(0x1)),
+
+	/* APLL FOUT L12: 300MHz */
+	((200<<16)|(4<<8)|(0x2)),
+
+	/* APLL FOUT L13: 200MHz */
+	((100<<16)|(3<<8)|(0x2)),
+
+};
+
+/*
+ * ASV group voltage table
+ */
+
+#define NO_ABB_LIMIT	L8
+
+static const unsigned int asv_voltage_4212[CPUFREQ_LEVEL_END][12] = {
+	/*   ASV0,    ASV1,    ASV2,    ASV3,	 ASV4,	  ASV5,	   ASV6,    ASV7,    ASV8,    ASV9,   ASV10,   ASV11 */
+	{	0, 1300000, 1300000, 1275000, 1300000, 1287500,	1275000, 1250000, 1237500, 1225000, 1225000, 1212500 }, /* L0 */
+	{ 1300000, 1287500, 1250000, 1225000, 1237500, 1237500,	1225000, 1200000, 1187500, 1175000, 1175000, 1162500 }, /* L1 */
+	{ 1237500, 1225000, 1200000, 1175000, 1187500, 1187500,	1162500, 1150000, 1137500, 1125000, 1125000, 1112500 }, /* L2 */
+	{ 1187500, 1175000, 1150000, 1137500, 1150000, 1137500,	1125000, 1100000, 1087500, 1075000, 1075000, 1062500 }, /* L3 */
+	{ 1137500, 1125000, 1112500, 1087500, 1112500, 1112500,	1075000, 1062500, 1050000, 1025000, 1025000, 1012500 }, /* L4 */
+	{ 1100000, 1087500, 1075000, 1050000, 1075000, 1062500,	1037500, 1025000, 1012500, 1000000,  987500,  975000 }, /* L5 */
+	{ 1050000, 1037500, 1025000, 1000000, 1025000, 1025000,	 987500,  975000,  962500,  950000,  937500,  925000 }, /* L6 */
+	{ 1012500, 1000000,  987500,  962500,  987500,	975000,	 962500,  937500,  925000,  912500,  912500,  900000 }, /* L7 */
+	{  962500,  950000,  937500,  912500,  937500,	937500,	 925000,  900000,  900000,  900000,  900000,  900000 }, /* L8 */
+	{  925000,  912500,  912500,  900000,  912500,	900000,	 900000,  900000,  900000,  900000,  900000,  900000 }, /* L9 */
+	{  912500,  900000,  900000,  900000,  900000,	900000,	 900000,  900000,  900000,  900000,  900000,  900000 }, /* L10 */
+	{  912500,  900000,  900000,  900000,  900000,	900000,	 900000,  900000,  900000,  900000,  900000,  900000 }, /* L11 */
+	{  912500,  900000,  900000,  900000,  900000,	900000,	 900000,  900000,  900000,  900000,  900000,  900000 }, /* L12 */
+	{  912500,  900000,  900000,  900000,  900000,	900000,	 900000,  900000,  900000,  900000,  900000,  900000 }, /* L13 */
+};
+
+static const unsigned int asv_voltage_s[CPUFREQ_LEVEL_END] = {
+	1300000, 1300000, 1300000, 1250000, 1200000, 1175000, 1100000,
+	1050000, 1025000, 1000000, 1000000, 1000000, 950000, 950000
+};
+
+/* ASV table for 12.5mV step */
+#if 0
+/* 20120105 DVFS table version */
+static const unsigned int asv_voltage_step_12_5[CPUFREQ_LEVEL_END][12] = {
+	/*   ASV0,    ASV1,    ASV2,    ASV3,	 ASV4,	  ASV5,	   ASV6,    ASV7,    ASV8,    ASV9,   ASV10,   ASV11 */
+	{	0,       0,	  0,	   0,	    0,	     0,	      0,       0,       0,       0,	  0,       0 },	/* L0 - Not used */
+	{ 1300000, 1300000, 1300000, 1287500, 1300000, 1287500,	1275000, 1250000, 1250000, 1237500, 1225000, 1212500 },
+	{ 1300000, 1300000, 1237500, 1237500, 1250000, 1250000,	1237500, 1212500, 1200000, 1200000, 1187500, 1175000 },
+	{ 1225000, 1212500, 1200000, 1187500, 1200000, 1187500,	1175000, 1150000, 1137500, 1125000, 1125000, 1112500 },
+	{ 1175000, 1162500, 1150000, 1137500, 1150000, 1137500,	1125000, 1100000, 1100000, 1075000, 1075000, 1062500 },
+	{ 1125000, 1112500, 1100000, 1087500, 1100000, 1087500,	1075000, 1050000, 1037500, 1025000, 1025000, 1012500 },
+	{ 1075000, 1062500, 1050000, 1050000, 1050000, 1037500,	1025000, 1012500, 1000000,  987500,  987500,  975000 },
+	{ 1037500, 1025000, 1012500, 1012500, 1012500, 1000000,	 987500,  975000,  975000,  975000,  975000,  962500 },
+	{ 1012500, 1000000,  987500,  987500,  987500,  987500,	 975000,  975000,  962500,  962500,  962500,  950000 },
+	{ 1000000,  987500,  975000,  975000,  975000,  975000,	 962500,  962500,  950000,  950000,  950000,  937500 },
+	{  987500,  975000,  962500,  950000,  962500,  950000,	 950000,  950000,  925000,  925000,  925000,  912500 },
+	{  975000,  962500,  950000,  925000,  950000,  925000,	 925000,  925000,  900000,  900000,  900000,  887500 },
+	{  950000,  937500,  925000,  900000,  925000,  900000,	 900000,  900000,  900000,  887500,  875000,  862500 },
+	{  925000,  912500,  900000,  900000,  900000,  900000,	 900000,  900000,  887500,  875000,  875000,  862500 },
+};
+#else
+/* 20120210 DVFS table version */
+static const unsigned int asv_voltage_step_12_5[CPUFREQ_LEVEL_END][12] = {
+	/*   ASV0,    ASV1,    ASV2,    ASV3,	 ASV4,	  ASV5,	   ASV6,    ASV7,    ASV8,    ASV9,   ASV10,   ASV11 */
+	{	0,       0,	  0,	   0,	    0,	     0,	      0,       0,       0,       0,	  0,       0 },	/* L0 - Not used */
+	{ 1325000, 1312500, 1300000, 1287500, 1300000, 1287500,	1275000, 1250000, 1250000, 1237500, 1225000, 1212500 },
+	{ 1300000, 1275000, 1237500, 1237500, 1250000, 1250000,	1237500, 1212500, 1200000, 1200000, 1187500, 1175000 },
+	{ 1225000, 1212500, 1200000, 1187500, 1200000, 1187500,	1175000, 1150000, 1137500, 1125000, 1125000, 1112500 },
+	{ 1175000, 1162500, 1150000, 1137500, 1150000, 1137500,	1125000, 1100000, 1100000, 1075000, 1075000, 1062500 },
+	{ 1125000, 1112500, 1100000, 1087500, 1100000, 1087500,	1075000, 1050000, 1037500, 1025000, 1025000, 1012500 },
+	{ 1075000, 1062500, 1050000, 1050000, 1050000, 1037500,	1025000, 1012500, 1000000,  987500,  987500,  975000 },
+	{ 1037500, 1025000, 1000000, 1000000, 1000000,  987500,	 975000,  962500,  962500,  962500,  962500,  950000 },
+	{ 1012500, 1000000,  975000,  975000,  975000,  975000,	 962500,  962500,  950000,  950000,  950000,  937500 },
+	{ 1000000,  987500,  962500,  962500,  962500,  962500,	 950000,  950000,  937500,  937500,  937500,  925000 },
+	{  987500,  975000,  950000,  937500,  950000,  937500,	 937500,  937500,  912500,  912500,  912500,  900000 },
+	{  975000,  962500,  950000,  925000,  950000,  925000,	 925000,  925000,  900000,  900000,  900000,  887500 },
+	{  950000,  937500,  925000,  900000,  925000,  900000,	 900000,  900000,  900000,  887500,  875000,  862500 },
+	{  925000,  912500,  900000,  900000,  900000,  900000,	 900000,  900000,  887500,  875000,  875000,  862500 },
+};
+#endif
+static void set_clkdiv(unsigned int div_index)
+{
+	unsigned int tmp;
+	unsigned int stat_cpu1;
+
+	/* Change Divider - CPU0 */
+
+	tmp = exynos4x12_clkdiv_table[div_index].clkdiv;
+
+	__raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
+
+	do {
+		tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU);
+	} while (tmp & 0x11111111);
+
+#ifdef PRINT_DIV_VAL
+	tmp = __raw_readl(EXYNOS4_CLKDIV_CPU);
+	pr_info("DIV_CPU0[0x%x]\n", tmp);
+
+#endif
+
+	/* Change Divider - CPU1 */
+	tmp = exynos4x12_clkdiv_table[div_index].clkdiv1;
+
+	__raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
+	if (soc_is_exynos4212())
+		stat_cpu1 = 0x11;
+	else
+		stat_cpu1 = 0x111;
+
+	do {
+		tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU1);
+	} while (tmp & stat_cpu1);
+#ifdef PRINT_DIV_VAL
+	tmp = __raw_readl(EXYNOS4_CLKDIV_CPU1);
+	pr_info("DIV_CPU1[0x%x]\n", tmp);
+#endif
+}
+
+static void set_apll(unsigned int new_index,
+			     unsigned int old_index)
+{
+	unsigned int tmp, pdiv;
+
+	/* 1. MUX_CORE_SEL = MPLL,
+	 * ARMCLK uses MPLL for lock time */
+	if (clk_set_parent(moutcore, mout_mpll))
+		printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
+				mout_mpll->name, moutcore->name);
+
+	do {
+		tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU)
+			>> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
+		tmp &= 0x7;
+	} while (tmp != 0x2);
+
+	/* 2. Set APLL Lock time */
+	pdiv = ((exynos4x12_apll_pms_table[new_index] >> 8) & 0x3f);
+
+	__raw_writel((pdiv * 250), EXYNOS4_APLL_LOCK);
+
+	/* 3. Change PLL PMS values */
+	tmp = __raw_readl(EXYNOS4_APLL_CON0);
+	tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
+	tmp |= exynos4x12_apll_pms_table[new_index];
+	__raw_writel(tmp, EXYNOS4_APLL_CON0);
+
+	/* 4. wait_lock_time */
+	do {
+		tmp = __raw_readl(EXYNOS4_APLL_CON0);
+	} while (!(tmp & (0x1 << EXYNOS4_APLLCON0_LOCKED_SHIFT)));
+
+	/* 5. MUX_CORE_SEL = APLL */
+	if (clk_set_parent(moutcore, mout_apll))
+		printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
+				mout_apll->name, moutcore->name);
+
+	do {
+		tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU);
+		tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
+	} while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
+
+}
+
+bool exynos4x12_pms_change(unsigned int old_index, unsigned int new_index)
+{
+	unsigned int old_pm = (exynos4x12_apll_pms_table[old_index] >> 8);
+	unsigned int new_pm = (exynos4x12_apll_pms_table[new_index] >> 8);
+
+	return (old_pm == new_pm) ? 0 : 1;
+}
+
+static void exynos4x12_set_frequency(unsigned int old_index,
+				  unsigned int new_index)
+{
+	unsigned int tmp;
+
+	if (old_index > new_index) {
+		if (!exynos4x12_pms_change(old_index, new_index)) {
+			/* 1. Change the system clock divider values */
+			set_clkdiv(new_index);
+			/* 2. Change just s value in apll m,p,s value */
+			tmp = __raw_readl(EXYNOS4_APLL_CON0);
+			tmp &= ~(0x7 << 0);
+			tmp |= (exynos4x12_apll_pms_table[new_index] & 0x7);
+			__raw_writel(tmp, EXYNOS4_APLL_CON0);
+
+		} else {
+			/* Clock Configuration Procedure */
+			/* 1. Change the system clock divider values */
+			set_clkdiv(new_index);
+			/* 2. Change the apll m,p,s value */
+			set_apll(new_index, old_index);
+		}
+	} else if (old_index < new_index) {
+		if (!exynos4x12_pms_change(old_index, new_index)) {
+			/* 1. Change just s value in apll m,p,s value */
+			tmp = __raw_readl(EXYNOS4_APLL_CON0);
+			tmp &= ~(0x7 << 0);
+			tmp |= (exynos4x12_apll_pms_table[new_index] & 0x7);
+			__raw_writel(tmp, EXYNOS4_APLL_CON0);
+			/* 2. Change the system clock divider values */
+			set_clkdiv(new_index);
+		} else {
+			/* Clock Configuration Procedure */
+			/* 1. Change the apll m,p,s value */
+			set_apll(new_index, old_index);
+			/* 2. Change the system clock divider values */
+			set_clkdiv(new_index);
+		}
+	}
+
+	/* ABB value is changed in below case */
+	if (soc_is_exynos4412() && (exynos_result_of_asv > 3)) {
+		if (new_index == L13)
+			exynos4x12_set_abb_member(ABB_ARM, ABB_MODE_100V);
+		else
+			exynos4x12_set_abb_member(ABB_ARM, ABB_MODE_130V);
+	}
+}
+
+static void __init set_volt_table(void)
+{
+	bool for_1500 = false, for_1200 = false, for_1400 = false;
+	unsigned int i;
+
+#ifdef CONFIG_EXYNOS4X12_1500MHZ_SUPPORT
+	for_1500 = true;
+	max_support_idx = L0;
+#elif defined(CONFIG_EXYNOS4X12_1200MHZ_SUPPORT)
+	for_1200 = true;
+	max_support_idx = L3;
+#elif defined(CONFIG_EXYNOS4X12_1400MHZ_SUPPORT)
+	for_1400 = true;
+	max_support_idx = L1;
+
+	/* It doesn't support 1400Mhz under EVT1 or when IDS >= 40 */
+	if (samsung_rev() < EXYNOS4412_REV_1_0 || exynos_result_of_asv > 9) {
+		for_1200 = true;
+		max_support_idx = L3;
+	}
+#else
+	max_support_idx = L5;
+#endif
+	/*
+	 * Should be fixed !!!
+	 */
+#if 0
+	if ((asv_group == 0) || !for_1400)
+		exynos4212_freq_table[L0].frequency = CPUFREQ_ENTRY_INVALID;
+#else
+	if (!for_1500 && !for_1200 && !for_1400) {
+		exynos4x12_freq_table[L0].frequency = CPUFREQ_ENTRY_INVALID;
+		exynos4x12_freq_table[L1].frequency = CPUFREQ_ENTRY_INVALID;
+		exynos4x12_freq_table[L2].frequency = CPUFREQ_ENTRY_INVALID;
+		exynos4x12_freq_table[L3].frequency = CPUFREQ_ENTRY_INVALID;
+		exynos4x12_freq_table[L4].frequency = CPUFREQ_ENTRY_INVALID;
+	} else if (for_1200) {
+		exynos4x12_freq_table[L0].frequency = CPUFREQ_ENTRY_INVALID;
+		exynos4x12_freq_table[L1].frequency = CPUFREQ_ENTRY_INVALID;
+		exynos4x12_freq_table[L2].frequency = CPUFREQ_ENTRY_INVALID;
+	} else if (for_1400) {
+		exynos4x12_freq_table[L0].frequency = CPUFREQ_ENTRY_INVALID;
+	}
+
+#endif
+
+	pr_info("DVFS : VDD_ARM Voltage table set with %d Group\n", exynos_result_of_asv);
+
+	if (exynos_result_of_asv == 0xff) {
+		for (i = 0 ; i < CPUFREQ_LEVEL_END ; i++)
+			exynos4x12_volt_table[i] = asv_voltage_s[i];
+	} else {
+		if (soc_is_exynos4212()) {
+			for (i = 0 ; i < CPUFREQ_LEVEL_END ; i++)
+				exynos4x12_volt_table[i] =
+					asv_voltage_4212[i][exynos_result_of_asv];
+		} else if (soc_is_exynos4412()) {
+			for (i = 0 ; i < CPUFREQ_LEVEL_END ; i++)
+				exynos4x12_volt_table[i] =
+					asv_voltage_step_12_5[i][exynos_result_of_asv];
+		} else {
+			pr_err("%s: Can't find SoC type \n", __func__);
+		}
+	}
+}
+
+/*
+ * The values of the table is not correct.
+ * Copied from C210 as prototype assuming that unmapping 512KiB
+ * requires 128 DMA operations.
+ */
+#ifdef CONFIG_SLP
+static struct dvfs_qos_info exynos4x12_dma_lat_qos[] = {
+	{ 118,	200000, L13 },
+	{ 40,	500000, L10 },
+	{ 24,	800000, L7 },
+	{ 16,	1000000, L5 },
+	{},
+};
+#endif
+
+int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
+{
+	int i;
+	unsigned int tmp;
+	unsigned long rate;
+
+	set_volt_table();
+
+	cpu_clk = clk_get(NULL, "armclk");
+	if (IS_ERR(cpu_clk))
+		return PTR_ERR(cpu_clk);
+
+	moutcore = clk_get(NULL, "moutcore");
+	if (IS_ERR(moutcore))
+		goto err_moutcore;
+
+	mout_mpll = clk_get(NULL, "mout_mpll");
+	if (IS_ERR(mout_mpll))
+		goto err_mout_mpll;
+
+	rate = clk_get_rate(mout_mpll) / 1000;
+
+	mout_apll = clk_get(NULL, "mout_apll");
+	if (IS_ERR(mout_apll))
+		goto err_mout_apll;
+
+	for (i = L0; i <  CPUFREQ_LEVEL_END; i++) {
+
+		exynos4x12_clkdiv_table[i].index = i;
+
+		tmp = __raw_readl(EXYNOS4_CLKDIV_CPU);
+
+		tmp &= ~(EXYNOS4_CLKDIV_CPU0_CORE_MASK |
+			EXYNOS4_CLKDIV_CPU0_COREM0_MASK |
+			EXYNOS4_CLKDIV_CPU0_COREM1_MASK |
+			EXYNOS4_CLKDIV_CPU0_PERIPH_MASK |
+			EXYNOS4_CLKDIV_CPU0_ATB_MASK |
+			EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK |
+			EXYNOS4_CLKDIV_CPU0_APLL_MASK |
+			EXYNOS4_CLKDIV_CPU0_CORE2_MASK);
+
+		if (soc_is_exynos4212()) {
+			tmp |= ((clkdiv_cpu0_4212[i][0] << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT) |
+				(clkdiv_cpu0_4212[i][1] << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT) |
+				(clkdiv_cpu0_4212[i][2] << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT) |
+				(clkdiv_cpu0_4212[i][3] << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT) |
+				(clkdiv_cpu0_4212[i][4] << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT) |
+				(clkdiv_cpu0_4212[i][5] << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT) |
+				(clkdiv_cpu0_4212[i][6] << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT) |
+				(clkdiv_cpu0_4212[i][7] << EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT));
+		} else {
+			tmp |= ((clkdiv_cpu0_4412[i][0] << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT) |
+				(clkdiv_cpu0_4412[i][1] << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT) |
+				(clkdiv_cpu0_4412[i][2] << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT) |
+				(clkdiv_cpu0_4412[i][3] << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT) |
+				(clkdiv_cpu0_4412[i][4] << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT) |
+				(clkdiv_cpu0_4412[i][5] << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT) |
+				(clkdiv_cpu0_4412[i][6] << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT) |
+				(clkdiv_cpu0_4412[i][7] << EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT));
+		}
+
+		exynos4x12_clkdiv_table[i].clkdiv = tmp;
+
+		tmp = __raw_readl(EXYNOS4_CLKDIV_CPU1);
+
+		if (soc_is_exynos4212()) {
+			tmp &= ~(EXYNOS4_CLKDIV_CPU1_COPY_MASK |
+				EXYNOS4_CLKDIV_CPU1_HPM_MASK);
+			tmp |= ((clkdiv_cpu1_4212[i][0] << EXYNOS4_CLKDIV_CPU1_COPY_SHIFT) |
+				(clkdiv_cpu1_4212[i][1] << EXYNOS4_CLKDIV_CPU1_HPM_SHIFT));
+		} else {
+			tmp &= ~(EXYNOS4_CLKDIV_CPU1_COPY_MASK |
+				EXYNOS4_CLKDIV_CPU1_HPM_MASK |
+				EXYNOS4_CLKDIV_CPU1_CORES_MASK);
+			tmp |= ((clkdiv_cpu1_4412[i][0] << EXYNOS4_CLKDIV_CPU1_COPY_SHIFT) |
+				(clkdiv_cpu1_4412[i][1] << EXYNOS4_CLKDIV_CPU1_HPM_SHIFT) |
+				(clkdiv_cpu1_4412[i][2] << EXYNOS4_CLKDIV_CPU1_CORES_SHIFT));
+		}
+		exynos4x12_clkdiv_table[i].clkdiv1 = tmp;
+	}
+
+	info->mpll_freq_khz = rate;
+#ifdef CONFIG_SLP
+	/* S-Boot at 20120406 uses L7 at bootup */
+	info->pm_lock_idx = L7;
+
+	/*
+	 * However, the bootup frequency might get changed anytime.
+	 * Thus, we'd like to get the value at bootup time.
+	 */
+	rate = clk_get_rate(cpu_clk) / 1000;
+	for (i = 0; exynos4x12_freq_table[i].frequency != CPUFREQ_TABLE_END;
+	     i++) {
+		if (exynos4x12_freq_table[i].frequency == rate) {
+			info->pm_lock_idx = exynos4x12_freq_table[i].index;
+			break;
+		}
+	}
+	pr_info("Bootup CPU Frequency = [%d] %dMHz\n", info->pm_lock_idx,
+		rate / 1000);
+#else
+	info->pm_lock_idx = L5;
+#endif
+	info->pll_safe_idx = L7;
+	info->max_support_idx = max_support_idx;
+	info->min_support_idx = min_support_idx;
+	info->cpu_clk = cpu_clk;
+	info->volt_table = exynos4x12_volt_table;
+	info->freq_table = exynos4x12_freq_table;
+	info->set_freq = exynos4x12_set_frequency;
+	info->need_apll_change = exynos4x12_pms_change;
+#ifdef CONFIG_SLP
+	info->cpu_dma_latency = exynos4x12_dma_lat_qos;
+#endif
+
+#ifdef ENABLE_CLKOUT
+	tmp = __raw_readl(EXYNOS4_CLKOUT_CMU_CPU);
+	tmp &= ~0xffff;
+	tmp |= 0x1904;
+	__raw_writel(tmp, EXYNOS4_CLKOUT_CMU_CPU);
+
+	exynos4_pmu_xclkout_set(1, XCLKOUT_CMU_CPU);
+#endif
+
+	return 0;
+
+err_mout_apll:
+	if (!IS_ERR(mout_mpll))
+		clk_put(mout_mpll);
+err_mout_mpll:
+	if (!IS_ERR(moutcore))
+		clk_put(moutcore);
+err_moutcore:
+	if (!IS_ERR(cpu_clk))
+		clk_put(cpu_clk);
+
+	pr_debug("%s: failed initialization\n", __func__);
+	return -EINVAL;
+}
+EXPORT_SYMBOL(exynos4x12_cpufreq_init);
diff --git a/arch/arm/mach-exynos/cpufreq-5250.c b/arch/arm/mach-exynos/cpufreq-5250.c
new file mode 100644
index 0000000..cf78c81
--- /dev/null
+++ b/arch/arm/mach-exynos/cpufreq-5250.c
@@ -0,0 +1,526 @@
+/* linux/arch/arm/mach-exynos/cpufreq-5250.c
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS5250 - CPU frequency scaling support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/cpufreq.h>
+
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/regs-pmu.h>
+#include <mach/regs-pmu-5250.h>
+#include <mach/cpufreq.h>
+#include <mach/asv.h>
+
+#include <plat/clock.h>
+#include <plat/cpu.h>
+
+#define CPUFREQ_LEVEL_END	(L20 + 1)
+
+#undef PRINT_DIV_VAL
+
+#undef ENABLE_CLKOUT
+
+static int max_support_idx;
+static int min_support_idx = (CPUFREQ_LEVEL_END - 1);
+static struct clk *cpu_clk;
+static struct clk *moutcore;
+static struct clk *mout_mpll;
+static struct clk *mout_apll;
+
+struct cpufreq_clkdiv {
+	unsigned int	index;
+	unsigned int	clkdiv;
+	unsigned int	clkdiv1;
+};
+
+static unsigned int exynos5250_volt_table[CPUFREQ_LEVEL_END];
+
+static struct cpufreq_frequency_table exynos5250_freq_table[] = {
+	{L0, 2200*1000},
+	{L1, 2100*1000},
+	{L2, 2000*1000},
+	{L3, 1900*1000},
+	{L4, 1800*1000},
+	{L5, 1700*1000},
+	{L6, 1600*1000},
+	{L7, 1500*1000},
+	{L8, 1400*1000},
+	{L9, 1300*1000},
+	{L10, 1200*1000},
+	{L11, 1100*1000},
+	{L12, 1000*1000},
+	{L13, 900*1000},
+	{L14, 800*1000},
+	{L15, 700*1000},
+	{L16, 600*1000},
+	{L17, 500*1000},
+	{L18, 400*1000},
+	{L19, 300*1000},
+	{L20, 200*1000},
+	{0, CPUFREQ_TABLE_END},
+};
+
+static struct cpufreq_clkdiv exynos5250_clkdiv_table[CPUFREQ_LEVEL_END];
+
+static unsigned int clkdiv_cpu0_5250[CPUFREQ_LEVEL_END][8] = {
+	/*
+	 * Clock divider value for following
+	 * { ARM, CPUD, ACP, PERIPH, ATB, PCLK_DBG, APLL, ARM2 }
+	 */
+	{ 0, 5, 7, 7, 7, 1, 5, 0 },	/* L0: 2200Mhz */
+	{ 0, 5, 7, 7, 7, 1, 5, 0 },	/* L1: 2100Mhz */
+	{ 0, 5, 7, 7, 7, 1, 5, 0 },	/* L2: 2000Mhz */
+	{ 0, 4, 7, 7, 7, 1, 5, 0 },	/* L3: 1900Mhz */
+	{ 0, 4, 7, 7, 7, 1, 4, 0 },	/* L4: 1800Mhz */
+	{ 0, 3, 7, 7, 7, 3, 5, 0 },	/* L5: 1700Mhz */
+	{ 0, 3, 7, 7, 7, 1, 4, 0 },	/* L6: 1600MHz */
+	{ 0, 2, 7, 7, 7, 1, 4, 0 },	/* L7: 1500Mhz */
+	{ 0, 2, 7, 7, 6, 1, 4, 0 },	/* L8: 1400Mhz */
+	{ 0, 2, 7, 7, 6, 1, 3, 0 },	/* L9: 1300Mhz */
+	{ 0, 2, 7, 7, 5, 1, 3, 0 },	/* L10: 1200Mhz */
+	{ 0, 3, 7, 7, 5, 1, 3, 0 },	/* L11: 1100MHz */
+	{ 0, 1, 7, 7, 4, 1, 2, 0 },	/* L12: 1000MHz */
+	{ 0, 1, 7, 7, 4, 1, 2, 0 },	/* L13: 900MHz */
+	{ 0, 1, 7, 7, 4, 1, 2, 0 },	/* L14: 800MHz */
+	{ 0, 1, 7, 7, 3, 1, 1, 0 },	/* L15: 700MHz */
+	{ 0, 1, 7, 7, 3, 1, 1, 0 },	/* L16: 600MHz */
+	{ 0, 1, 7, 7, 2, 1, 1, 0 },	/* L17: 500MHz */
+	{ 0, 1, 7, 7, 2, 1, 1, 0 },	/* L18: 400MHz */
+	{ 0, 1, 7, 7, 1, 1, 1, 0 },	/* L19: 300MHz */
+	{ 0, 1, 7, 7, 1, 1, 1, 0 },	/* L20: 200MHz */
+};
+
+static unsigned int clkdiv_cpu1_5250[CPUFREQ_LEVEL_END][2] = {
+	/* Clock divider value for following
+	 * { COPY, HPM }
+	 */
+	{ 0, 2 },	/* L0: 2200Mhz */
+	{ 0, 2 },	/* L1: 2100Mhz */
+	{ 0, 2 },	/* L2: 2000Mhz */
+	{ 0, 2 },	/* L3: 1900Mhz */
+	{ 0, 2 },	/* L4: 1800Mhz */
+	{ 0, 2 },	/* L5: 1700Mhz */
+	{ 0, 2 },	/* L6: 1600MHz */
+	{ 0, 2 },	/* L7: 1500Mhz */
+	{ 0, 2 },	/* L8: 1400Mhz */
+	{ 0, 2 },	/* L9: 1300Mhz */
+	{ 0, 2 },	/* L10: 1200Mhz */
+	{ 0, 2 },	/* L11: 1100MHz */
+	{ 0, 2 },	/* L12: 1000MHz */
+	{ 0, 2 },	/* L13: 900MHz */
+	{ 0, 2 },	/* L14: 800MHz */
+	{ 0, 2 },	/* L15: 700MHz */
+	{ 0, 2 },	/* L16: 600MHz */
+	{ 0, 2 },	/* L17: 500MHz */
+	{ 0, 2 },	/* L18: 400MHz */
+	{ 0, 2 },	/* L19: 300MHz */
+	{ 0, 2 },	/* L20: 200MHz */
+};
+
+static unsigned int exynos5_apll_pms_table[CPUFREQ_LEVEL_END] = {
+	((275<<16)|(3<<8)|(0)),	/* L0: 2200Mhz */
+	((350<<16)|(4<<8)|(0)),	/* L1: 2100Mhz */
+	((250<<16)|(3<<8)|(0)),	/* L2: 2000Mhz */
+	((475<<16)|(6<<8)|(0)),	/* L3: 1900Mhz */
+	((225<<16)|(3<<8)|(0)),	/* L4: 1800Mhz */
+	((425<<16)|(6<<8)|(0)),	/* L5: 1700Mhz */
+	((200<<16)|(3<<8)|(0)),	/* L6: 1600MHz */
+	((250<<16)|(4<<8)|(0)),	/* L7: 1500Mhz */
+	((175<<16)|(3<<8)|(0)),	/* L8: 1400Mhz */
+	((325<<16)|(6<<8)|(0)),	/* L9: 1300Mhz */
+	((200<<16)|(4<<8)|(0)),	/* L10: 1200Mhz */
+	((275<<16)|(6<<8)|(0)),	/* L11: 1100MHz */
+	((125<<16)|(3<<8)|(0)),	/* L12: 1000MHz */
+	((150<<16)|(4<<8)|(0)),	/* L13: 900MHz */
+	((100<<16)|(3<<8)|(0)),	/* L14: 800MHz */
+	((175<<16)|(3<<8)|(1)),	/* L15: 700MHz */
+	((200<<16)|(4<<8)|(1)),	/* L16: 600MHz */
+	((125<<16)|(3<<8)|(1)),	/* L17: 500MHz */
+	((100<<16)|(3<<8)|(1)),	/* L18: 400MHz */
+	((200<<16)|(4<<8)|(2)),	/* L19: 300MHz */
+	((100<<16)|(3<<8)|(2)),	/* L20: 200MHz */
+};
+
+/*
+ * ASV group voltage table
+ */
+
+#define NUM_ASV_GROUP	L10
+
+
+static const unsigned int asv_voltage[CPUFREQ_LEVEL_END][NUM_ASV_GROUP+1] = {
+	/* ASV0 is not exist */
+	/* ASV0,  ASV1,    ASV2,     ASV3,    ASV4,    ASV5,    ASV6,    ASV7,    ASV8,    ASV9,   ASV10 */
+	{ 0 },  /* L0 */
+	{ 0 },  /* L1 */
+	{ 0 },  /* L2 */
+	{ 0 },  /* L3 */
+	{ 0 },  /* L4 */
+	{ 0,   1300000, 1275000, 1287500, 1275000, 1275000, 1262500, 1250000, 1237500, 1225000, 1225000 },    /* L5 */
+	{ 0,   1250000, 1237500, 1250000, 1237500, 1250000, 1237500, 1225000, 1212500, 1200000, 1200000 },    /* L6 */
+	{ 0,   1225000, 1200000, 1212500, 1200000, 1212500, 1200000, 1187500, 1175000, 1175000, 1150000 },    /* L7 */
+	{ 0,   1200000, 1175000, 1200000, 1175000, 1187500, 1175000, 1162500, 1150000, 1137500, 1125000 },    /* L8 */
+	{ 0,   1150000, 1125000, 1150000, 1125000, 1137500, 1125000, 1112500, 1100000, 1087500, 1075000 },    /* L9 */
+	{ 0,   1125000, 1112500, 1125000, 1112500, 1125000, 1112500, 1100000, 1087500, 1075000, 1062500 },    /* L10 */
+	{ 0,   1100000, 1075000, 1100000, 1087500, 1100000, 1087500, 1075000, 1062500, 1050000, 1037500 },    /* L11 */
+	{ 0,   1075000, 1050000, 1062500, 1050000, 1062500, 1050000, 1050000, 1037500, 1025000, 1012500 },    /* L12 */
+	{ 0,   1050000, 1025000, 1050000, 1037500, 1050000, 1037500, 1025000, 1012500, 1000000,  987500 },    /* L13 */
+	{ 0,   1025000, 1012500, 1025000, 1012500, 1025000, 1012500, 1000000, 1000000,  987500,  975000 },     /* L14 */
+	{ 0,   1012500, 1000000, 1012500, 1000000, 1012500, 1000000,  987500,  975000,  975000,  962500 },     /* L15 */
+	{ 0,   1000000,  975000, 1000000,  975000, 1000000,  987500,  975000,  962500,  962500,  950000 },     /* L16 */
+	{ 0,    975000,  962500,  975000,  962500,  975000,  962500,  950000,  937500,  925000,  925000 },     /* L17 */
+	{ 0,    950000,  937500,  950000,  937500,  950000,  937500,  925000,  925000,  925000,  912500 },     /* L18 */
+	{ 0,    937500,  925000,  937500,  925000,  937500,  925000,  912500,  912500,  900000,  900000 },     /* L19 */
+	{ 0,    925000,  912500,  925000,  912500,  925000,  912500,  900000,  900000,  887500,  887500  },    /* L20 */
+};
+
+static const unsigned int asv_voltage_rev0[CPUFREQ_LEVEL_END][NUM_ASV_GROUP] = {
+	{ 0 },	/* L0 */
+	{ 0 },	/* L1 */
+	{ 0 },	/* L2 */
+	{ 0 },	/* L3 */
+	{ 0 },	/* L4 */
+	{ 1200000 },	/* L5 */
+	{ 1200000 },	/* L6 */
+	{ 1200000 },	/* L7 */
+	{ 1200000 },	/* L8 */
+	{ 1200000 },	/* L9 */
+	{ 1200000 },	/* L10 */
+	{ 1200000 },	/* L11 */
+	{ 1175000 },	/* L12 */
+	{ 1125000 },	/* L13 */
+	{ 1075000 },	/* L14 */
+	{ 1050000 },	/* L15 */
+	{ 1000000 },	/* L16 */
+	{ 950000 },	/* L17 */
+	{ 925000 },	/* L18 */
+	{ 925000 },	/* L19 */
+	{ 900000 },	/* L20 */
+};
+
+#if defined(CONFIG_EXYNOS5250_ABB_WA)
+#define ARM_RBB		6	/* +300mV */
+unsigned int exynos5250_arm_volt;
+
+#define INT_VOLT	1050000
+#endif
+
+static void set_clkdiv(unsigned int div_index)
+{
+	unsigned int tmp;
+
+	/* Change Divider - CPU0 */
+
+	tmp = exynos5250_clkdiv_table[div_index].clkdiv;
+
+	__raw_writel(tmp, EXYNOS5_CLKDIV_CPU0);
+
+	do {
+		tmp = __raw_readl(EXYNOS5_CLKDIV_STATCPU0);
+	} while (tmp & 0x11111111);
+
+#ifdef PRINT_DIV_VAL
+	tmp = __raw_readl(EXYNOS5_CLKDIV_CPU0);
+	pr_info("DIV_CPU0[0x%x]\n", tmp);
+
+#endif
+
+	/* Change Divider - CPU1 */
+	tmp = exynos5250_clkdiv_table[div_index].clkdiv1;
+
+	__raw_writel(tmp, EXYNOS5_CLKDIV_CPU1);
+
+	do {
+		tmp = __raw_readl(EXYNOS5_CLKDIV_STATCPU1);
+	} while (tmp & 0x11);
+#ifdef PRINT_DIV_VAL
+	tmp = __raw_readl(EXYNOS5_CLKDIV_CPU1);
+	pr_info("DIV_CPU1[0x%x]\n", tmp);
+#endif
+}
+
+static void set_apll(unsigned int new_index,
+			     unsigned int old_index)
+{
+	unsigned int tmp, pdiv;
+
+	/* 1. MUX_CORE_SEL = MPLL,
+	 * ARMCLK uses MPLL for lock time */
+	if (clk_set_parent(moutcore, mout_mpll))
+		pr_err("Unable to set parent %s of clock %s.\n",
+			mout_mpll->name, moutcore->name);
+
+	do {
+		tmp = (__raw_readl(EXYNOS5_CLKMUX_STATCPU) >> 16);
+		tmp &= 0x7;
+	} while (tmp != 0x2);
+
+	/* 2. Set APLL Lock time */
+	pdiv = ((exynos5_apll_pms_table[new_index] >> 8) & 0x3f);
+
+	__raw_writel((pdiv * 250), EXYNOS5_APLL_LOCK);
+
+	/* 3. Change PLL PMS values */
+	tmp = __raw_readl(EXYNOS5_APLL_CON0);
+	tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
+	tmp |= exynos5_apll_pms_table[new_index];
+	__raw_writel(tmp, EXYNOS5_APLL_CON0);
+
+	/* 4. wait_lock_time */
+	do {
+		tmp = __raw_readl(EXYNOS5_APLL_CON0);
+	} while (!(tmp & (0x1 << 29)));
+
+	/* 5. MUX_CORE_SEL = APLL */
+	if (clk_set_parent(moutcore, mout_apll))
+		pr_err("Unable to set parent %s of clock %s.\n",
+			mout_apll->name, moutcore->name);
+
+	do {
+		tmp = __raw_readl(EXYNOS5_CLKMUX_STATCPU);
+		tmp &= (0x7 << 16);
+	} while (tmp != (0x1 << 16));
+
+}
+
+bool exynos5250_pms_change(unsigned int old_index, unsigned int new_index)
+{
+	unsigned int old_pm = (exynos5_apll_pms_table[old_index] >> 8);
+	unsigned int new_pm = (exynos5_apll_pms_table[new_index] >> 8);
+
+	return (old_pm == new_pm) ? 0 : 1;
+}
+
+#if defined(CONFIG_EXYNOS5250_ABB_WA)
+static DEFINE_SPINLOCK(abb_lock);
+void exynos5250_set_arm_abbg(unsigned int arm_volt, unsigned int int_volt)
+{
+	unsigned int setbits = 8;
+	unsigned int tmp, diff_volt;
+	unsigned long flag;
+
+	spin_lock_irqsave(&abb_lock, flag);
+	if (arm_volt >= int_volt) {
+		diff_volt = arm_volt - int_volt;
+		setbits += diff_volt / 50000;
+	} else {
+		diff_volt = int_volt - arm_volt;
+		setbits -= diff_volt / 50000;
+	}
+	tmp = __raw_readl(EXYNOS5_ABBG_ARM_CONTROL);
+	tmp &= ~(0x1f | (1 << 31) | (1 << 7));
+	tmp |= ((setbits + ARM_RBB) | (1 << 31) | (1 << 7));
+	__raw_writel(tmp, EXYNOS5_ABBG_ARM_CONTROL);
+	spin_unlock_irqrestore(&abb_lock, flag);
+}
+EXPORT_SYMBOL(exynos5250_set_arm_abbg);
+#endif
+
+static void exynos5250_set_frequency(unsigned int old_index,
+				  unsigned int new_index)
+{
+	unsigned int tmp;
+#if defined(CONFIG_EXYNOS5250_ABB_WA)
+	unsigned int voltage;
+
+	if (samsung_rev() < EXYNOS5250_REV_1_0) {
+		voltage = asv_voltage_rev0[new_index][0];
+		exynos5250_set_arm_abbg(voltage, INT_VOLT);
+	}
+#endif
+	if (old_index > new_index) {
+		if (!exynos5250_pms_change(old_index, new_index)) {
+			/* 1. Change the system clock divider values */
+			set_clkdiv(new_index);
+			/* 2. Change just s value in apll m,p,s value */
+			tmp = __raw_readl(EXYNOS5_APLL_CON0);
+			tmp &= ~(0x7 << 0);
+			tmp |= (exynos5_apll_pms_table[new_index] & 0x7);
+			__raw_writel(tmp, EXYNOS5_APLL_CON0);
+
+		} else {
+			/* Clock Configuration Procedure */
+			/* 1. Change the system clock divider values */
+			set_clkdiv(new_index);
+			/* 2. Change the apll m,p,s value */
+			set_apll(new_index, old_index);
+		}
+	} else if (old_index < new_index) {
+		if (!exynos5250_pms_change(old_index, new_index)) {
+			/* 1. Change just s value in apll m,p,s value */
+			tmp = __raw_readl(EXYNOS5_APLL_CON0);
+			tmp &= ~(0x7 << 0);
+			tmp |= (exynos5_apll_pms_table[new_index] & 0x7);
+			__raw_writel(tmp, EXYNOS5_APLL_CON0);
+			/* 2. Change the system clock divider values */
+			set_clkdiv(new_index);
+		} else {
+			/* Clock Configuration Procedure */
+			/* 1. Change the apll m,p,s value */
+			set_apll(new_index, old_index);
+			/* 2. Change the system clock divider values */
+			set_clkdiv(new_index);
+		}
+	}
+}
+
+static void __init set_volt_table(void)
+{
+	unsigned int asv_group;
+	unsigned int i;
+
+	if (soc_is_exynos5250()) {
+		exynos5250_freq_table[L0].frequency = CPUFREQ_ENTRY_INVALID;
+		exynos5250_freq_table[L1].frequency = CPUFREQ_ENTRY_INVALID;
+		exynos5250_freq_table[L2].frequency = CPUFREQ_ENTRY_INVALID;
+		exynos5250_freq_table[L3].frequency = CPUFREQ_ENTRY_INVALID;
+		exynos5250_freq_table[L4].frequency = CPUFREQ_ENTRY_INVALID;
+
+		switch (samsung_rev() & 0xf0) {
+		case EXYNOS5250_REV_0:
+			exynos5250_freq_table[L5].frequency = CPUFREQ_ENTRY_INVALID;
+			exynos5250_freq_table[L6].frequency = CPUFREQ_ENTRY_INVALID;
+			exynos5250_freq_table[L7].frequency = CPUFREQ_ENTRY_INVALID;
+			exynos5250_freq_table[L8].frequency = CPUFREQ_ENTRY_INVALID;
+			exynos5250_freq_table[L9].frequency = CPUFREQ_ENTRY_INVALID;
+			exynos5250_freq_table[L10].frequency = CPUFREQ_ENTRY_INVALID;
+			exynos5250_freq_table[L11].frequency = CPUFREQ_ENTRY_INVALID;
+
+			max_support_idx = L12;
+			break;
+		case EXYNOS5250_REV_1_0:
+			max_support_idx = L5;
+			break;
+		default:
+			pr_err("%s: Can't find cpu revision(%d) type\n", __func__,
+				samsung_rev());
+			break;
+		}
+	}
+
+	if (soc_is_exynos5250() && samsung_rev() < EXYNOS5250_REV_1_0)
+		asv_group = 0;
+	else
+		asv_group = exynos_result_of_asv;
+
+	pr_info("DVFS : VDD_ARM Voltage table set with %d Group\n", asv_group);
+	pr_info("DVFS : VDD_ARM Voltage of max level is %d\n", asv_voltage[max_support_idx][asv_group]);
+	
+	for (i = 0 ; i < CPUFREQ_LEVEL_END ; i++) {
+		if (samsung_rev() < EXYNOS5250_REV_1_0)
+			exynos5250_volt_table[i] = asv_voltage_rev0[i][asv_group];
+		else
+			exynos5250_volt_table[i] = asv_voltage[i][asv_group];
+	}
+}
+
+int exynos5250_cpufreq_init(struct exynos_dvfs_info *info)
+{
+	int i;
+	unsigned int tmp;
+	unsigned long rate;
+
+	set_volt_table();
+
+	cpu_clk = clk_get(NULL, "armclk");
+	if (IS_ERR(cpu_clk))
+		return PTR_ERR(cpu_clk);
+
+	moutcore = clk_get(NULL, "moutcpu");
+	if (IS_ERR(moutcore))
+		goto err_moutcore;
+
+	mout_mpll = clk_get(NULL, "mout_mpll");
+	if (IS_ERR(mout_mpll))
+		goto err_mout_mpll;
+
+	rate = clk_get_rate(mout_mpll) / 1000;
+
+	mout_apll = clk_get(NULL, "mout_apll");
+	if (IS_ERR(mout_apll))
+		goto err_mout_apll;
+
+	for (i = L0; i <  CPUFREQ_LEVEL_END; i++) {
+
+		exynos5250_clkdiv_table[i].index = i;
+
+		tmp = __raw_readl(EXYNOS5_CLKDIV_CPU0);
+
+		tmp &= ~((0x7 << 0) | (0x7 << 4) | (0x7 << 8) |
+			(0x7 << 12) | (0x7 << 16) | (0x7 << 20) |
+			(0x7 << 24) | (0x7 << 28));
+
+		tmp |= ((clkdiv_cpu0_5250[i][0] << 0) |
+			(clkdiv_cpu0_5250[i][1] << 4) |
+			(clkdiv_cpu0_5250[i][2] << 8) |
+			(clkdiv_cpu0_5250[i][3] << 12) |
+			(clkdiv_cpu0_5250[i][4] << 16) |
+			(clkdiv_cpu0_5250[i][5] << 20) |
+			(clkdiv_cpu0_5250[i][6] << 24) |
+			(clkdiv_cpu0_5250[i][7] << 28));
+
+		exynos5250_clkdiv_table[i].clkdiv = tmp;
+
+		tmp = __raw_readl(EXYNOS5_CLKDIV_CPU1);
+
+		tmp &= ~((0x7 << 0) | (0x7 << 4));
+
+		tmp |= ((clkdiv_cpu1_5250[i][0] << 0) |
+			(clkdiv_cpu1_5250[i][1] << 4));
+
+		exynos5250_clkdiv_table[i].clkdiv1 = tmp;
+	}
+
+	info->mpll_freq_khz = rate;
+	/* 1000Mhz */
+	info->pm_lock_idx = L12;
+	/* 800Mhz */
+	info->pll_safe_idx = L14;
+	info->max_support_idx = max_support_idx;
+	info->min_support_idx = min_support_idx;
+	info->cpu_clk = cpu_clk;
+	info->volt_table = exynos5250_volt_table;
+	info->freq_table = exynos5250_freq_table;
+	info->set_freq = exynos5250_set_frequency;
+	info->need_apll_change = exynos5250_pms_change;
+
+#ifdef ENABLE_CLKOUT
+	tmp = __raw_readl(EXYNOS5_CLKOUT_CMU_CPU);
+	p &= ~0xffff;
+	tmp |= 0x1904;
+	__raw_writel(tmp, EXYNOS5_CLKOUT_CMU_CPU);
+
+	tmp = __raw_readl(S5P_PMU_DEBUG);
+	tmp &= ~0xf00;
+	tmp |= 0x400;
+	__raw_writel(tmp, S5P_PMU_DEBUG);
+
+#endif
+	return 0;
+
+err_mout_apll:
+	if (!IS_ERR(mout_mpll))
+		clk_put(mout_mpll);
+err_mout_mpll:
+	if (!IS_ERR(moutcore))
+		clk_put(moutcore);
+err_moutcore:
+	if (!IS_ERR(cpu_clk))
+		clk_put(cpu_clk);
+
+	pr_err("%s: failed initialization\n", __func__);
+	return -EINVAL;
+}
+EXPORT_SYMBOL(exynos5250_cpufreq_init);
diff --git a/arch/arm/mach-exynos/cpufreq.c b/arch/arm/mach-exynos/cpufreq.c
new file mode 100644
index 0000000..e78dad9
--- /dev/null
+++ b/arch/arm/mach-exynos/cpufreq.c
@@ -0,0 +1,830 @@
+/* linux/arch/arm/mach-exynos/cpufreq.c
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS - CPU frequency scaling support for EXYNOS series
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/regulator/consumer.h>
+#include <linux/cpufreq.h>
+#include <linux/suspend.h>
+#include <linux/reboot.h>
+#include <linux/pm_qos_params.h>
+
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/regs-mem.h>
+#include <mach/cpufreq.h>
+#include <mach/asv.h>
+
+#include <plat/clock.h>
+#include <plat/pm.h>
+#include <plat/cpu.h>
+
+struct exynos_dvfs_info *exynos_info;
+
+static struct regulator *arm_regulator;
+static struct cpufreq_freqs freqs;
+
+static bool exynos_cpufreq_disable;
+static bool exynos_cpufreq_lock_disable;
+static bool exynos_cpufreq_init_done;
+static DEFINE_MUTEX(set_freq_lock);
+static DEFINE_MUTEX(set_cpu_freq_lock);
+
+unsigned int g_cpufreq_limit_id;
+unsigned int g_cpufreq_limit_val[DVFS_LOCK_ID_END];
+unsigned int g_cpufreq_limit_level;
+
+unsigned int g_cpufreq_lock_id;
+unsigned int g_cpufreq_lock_val[DVFS_LOCK_ID_END];
+unsigned int g_cpufreq_lock_level;
+
+int exynos_verify_speed(struct cpufreq_policy *policy)
+{
+	return cpufreq_frequency_table_verify(policy,
+					      exynos_info->freq_table);
+}
+
+unsigned int exynos_getspeed(unsigned int cpu)
+{
+	return clk_get_rate(exynos_info->cpu_clk) / 1000;
+}
+
+static unsigned int exynos_get_safe_armvolt(unsigned int old_index, unsigned int new_index)
+{
+	unsigned int safe_arm_volt = 0;
+	struct cpufreq_frequency_table *freq_table = exynos_info->freq_table;
+	unsigned int *volt_table = exynos_info->volt_table;
+
+	/*
+	 * ARM clock source will be changed APLL to MPLL temporary
+	 * To support this level, need to control regulator for
+	 * reguired voltage level
+	 */
+
+	if (exynos_info->need_apll_change != NULL) {
+		if (exynos_info->need_apll_change(old_index, new_index) &&
+			(freq_table[new_index].frequency < exynos_info->mpll_freq_khz) &&
+			(freq_table[old_index].frequency < exynos_info->mpll_freq_khz)) {
+				safe_arm_volt = volt_table[exynos_info->pll_safe_idx];
+			}
+
+	}
+
+	return safe_arm_volt;
+}
+
+static int exynos_target(struct cpufreq_policy *policy,
+			  unsigned int target_freq,
+			  unsigned int relation)
+{
+	unsigned int index, old_index = UINT_MAX;
+	unsigned int arm_volt, safe_arm_volt = 0;
+	int ret = 0, i;
+	struct cpufreq_frequency_table *freq_table = exynos_info->freq_table;
+	unsigned int *volt_table = exynos_info->volt_table;
+
+	mutex_lock(&set_freq_lock);
+
+	if (exynos_cpufreq_disable)
+		goto out;
+
+	freqs.old = policy->cur;
+
+	/*
+	 * cpufreq_frequency_table_target() cannot be used for freqs.old
+	 * because policy->min/max may have been changed. If changed, the
+	 * resulting old_index may be inconsistent with freqs.old, which
+	 * will lead to inconsistent voltage/frequency configurations later.
+	 */
+	for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
+		if (freq_table[i].frequency == freqs.old)
+			old_index = freq_table[i].index;
+	}
+	if (old_index == UINT_MAX) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	if (cpufreq_frequency_table_target(policy, freq_table,
+					   target_freq, relation, &index)) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	/* Need to set performance limitation */
+	if (!exynos_cpufreq_lock_disable && (index > g_cpufreq_lock_level))
+		index = g_cpufreq_lock_level;
+
+	if (!exynos_cpufreq_lock_disable && (index < g_cpufreq_limit_level))
+		index = g_cpufreq_limit_level;
+
+#if defined(CONFIG_CPU_EXYNOS4210)
+	/* Do NOT step up max arm clock directly to reduce power consumption */
+	if (index == exynos_info->max_support_idx && old_index > 3)
+		index = 3;
+#endif
+
+	freqs.new = freq_table[index].frequency;
+	freqs.cpu = policy->cpu;
+
+	safe_arm_volt = exynos_get_safe_armvolt(old_index, index);
+
+	arm_volt = volt_table[index];
+
+	cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+
+	/* When the new frequency is higher than current frequency */
+	if ((freqs.new > freqs.old) && !safe_arm_volt) {
+		/* Firstly, voltage up to increase frequency */
+		regulator_set_voltage(arm_regulator, arm_volt,
+				     arm_volt + 25000);
+	}
+
+	if (safe_arm_volt)
+		regulator_set_voltage(arm_regulator, safe_arm_volt,
+				     safe_arm_volt + 25000);
+	if (freqs.new != freqs.old)
+		exynos_info->set_freq(old_index, index);
+
+	cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+
+	/* When the new frequency is lower than current frequency */
+	if ((freqs.new < freqs.old) ||
+	   ((freqs.new > freqs.old) && safe_arm_volt)) {
+		/* down the voltage after frequency change */
+		regulator_set_voltage(arm_regulator, arm_volt,
+				     arm_volt + 25000);
+	}
+
+out:
+	mutex_unlock(&set_freq_lock);
+
+	return ret;
+}
+
+/**
+ * exynos_find_cpufreq_level_by_volt - find cpufreqi_level by requested
+ * arm voltage.
+ *
+ * This function finds the cpufreq_level to set for voltage above req_volt
+ * and return its value.
+ */
+int exynos_find_cpufreq_level_by_volt(unsigned int arm_volt,
+					unsigned int *level)
+{
+	struct cpufreq_frequency_table *table;
+	unsigned int *volt_table = exynos_info->volt_table;
+	int i;
+
+	if (!exynos_cpufreq_init_done)
+		return -EINVAL;
+
+	table = cpufreq_frequency_get_table(0);
+	if (!table) {
+		pr_err("%s: Failed to get the cpufreq table\n", __func__);
+		return -EINVAL;
+	}
+
+	/* check if arm_volt has value or not */
+	if (!arm_volt) {
+		pr_err("%s: req_volt has no value.\n", __func__);
+		return -EINVAL;
+	}
+
+	/* find cpufreq level in volt_table */
+	for (i = exynos_info->min_support_idx;
+			i >= exynos_info->max_support_idx; i--) {
+		if (volt_table[i] >= arm_volt) {
+			*level = (unsigned int)i;
+			return 0;
+		}
+	}
+
+	pr_err("%s: Failed to get level for %u uV\n", __func__, arm_volt);
+
+	return -EINVAL;
+}
+EXPORT_SYMBOL_GPL(exynos_find_cpufreq_level_by_volt);
+
+int exynos_cpufreq_get_level(unsigned int freq, unsigned int *level)
+{
+	struct cpufreq_frequency_table *table;
+	unsigned int i;
+
+	if (!exynos_cpufreq_init_done)
+		return -EINVAL;
+
+	table = cpufreq_frequency_get_table(0);
+	if (!table) {
+		pr_err("%s: Failed to get the cpufreq table\n", __func__);
+		return -EINVAL;
+	}
+
+	for (i = exynos_info->max_support_idx;
+		(table[i].frequency != CPUFREQ_TABLE_END); i++) {
+		if (table[i].frequency == freq) {
+			*level = i;
+			return 0;
+		}
+	}
+
+	pr_err("%s: %u KHz is an unsupported cpufreq\n", __func__, freq);
+
+	return -EINVAL;
+}
+EXPORT_SYMBOL_GPL(exynos_cpufreq_get_level);
+
+atomic_t exynos_cpufreq_lock_count;
+
+int exynos_cpufreq_lock(unsigned int nId,
+			 enum cpufreq_level_index cpufreq_level)
+{
+	int ret = 0, i, old_idx = -EINVAL;
+	unsigned int freq_old, freq_new, arm_volt, safe_arm_volt;
+	unsigned int *volt_table;
+	struct cpufreq_policy *policy;
+	struct cpufreq_frequency_table *freq_table;
+
+	if (!exynos_cpufreq_init_done)
+		return -EPERM;
+
+	if (!exynos_info)
+		return -EPERM;
+
+	if (exynos_cpufreq_disable && (nId != DVFS_LOCK_ID_TMU)) {
+		pr_info("CPUFreq is already fixed\n");
+		return -EPERM;
+	}
+
+	if (cpufreq_level < exynos_info->max_support_idx
+			|| cpufreq_level > exynos_info->min_support_idx) {
+		pr_warn("%s: invalid cpufreq_level(%d:%d)\n", __func__, nId,
+				cpufreq_level);
+		return -EINVAL;
+	}
+
+	policy = cpufreq_cpu_get(0);
+	if (!policy)
+		return -EPERM;
+
+	volt_table = exynos_info->volt_table;
+	freq_table = exynos_info->freq_table;
+
+	mutex_lock(&set_cpu_freq_lock);
+	if (g_cpufreq_lock_id & (1 << nId)) {
+		printk(KERN_ERR "%s:Device [%d] already locked cpufreq\n",
+				__func__,  nId);
+		mutex_unlock(&set_cpu_freq_lock);
+		return 0;
+	}
+
+	g_cpufreq_lock_id |= (1 << nId);
+	g_cpufreq_lock_val[nId] = cpufreq_level;
+
+	/* If the requested cpufreq is higher than current min frequency */
+	if (cpufreq_level < g_cpufreq_lock_level)
+		g_cpufreq_lock_level = cpufreq_level;
+
+	mutex_unlock(&set_cpu_freq_lock);
+
+	if ((g_cpufreq_lock_level < g_cpufreq_limit_level)
+				&& (nId != DVFS_LOCK_ID_PM))
+		return 0;
+
+	/* Do not setting cpufreq lock frequency
+	 * because current governor doesn't support dvfs level lock
+	 * except DVFS_LOCK_ID_PM */
+	if (exynos_cpufreq_lock_disable && (nId != DVFS_LOCK_ID_PM))
+		return 0;
+
+	/* If current frequency is lower than requested freq,
+	 * it needs to update
+	 */
+	mutex_lock(&set_freq_lock);
+	freq_old = policy->cur;
+	freq_new = freq_table[cpufreq_level].frequency;
+	if (freq_old < freq_new) {
+		/* Find out current level index */
+		for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
+			if (freq_old == freq_table[i].frequency) {
+				old_idx = freq_table[i].index;
+				break;
+			}
+		}
+		if (old_idx == -EINVAL) {
+			printk(KERN_ERR "%s: Level not found\n", __func__);
+			mutex_unlock(&set_freq_lock);
+			return -EINVAL;
+		}
+
+		freqs.old = freq_old;
+		freqs.new = freq_new;
+		cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+
+		/* get the voltage value */
+		safe_arm_volt = exynos_get_safe_armvolt(old_idx, cpufreq_level);
+		if (safe_arm_volt)
+			regulator_set_voltage(arm_regulator, safe_arm_volt,
+					     safe_arm_volt + 25000);
+
+		arm_volt = volt_table[cpufreq_level];
+		regulator_set_voltage(arm_regulator, arm_volt,
+				     arm_volt + 25000);
+
+		exynos_info->set_freq(old_idx, cpufreq_level);
+
+		cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+	}
+	mutex_unlock(&set_freq_lock);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(exynos_cpufreq_lock);
+
+void exynos_cpufreq_lock_free(unsigned int nId)
+{
+	unsigned int i;
+
+	if (!exynos_cpufreq_init_done)
+		return;
+
+	mutex_lock(&set_cpu_freq_lock);
+	g_cpufreq_lock_id &= ~(1 << nId);
+	g_cpufreq_lock_val[nId] = exynos_info->min_support_idx;
+	g_cpufreq_lock_level = exynos_info->min_support_idx;
+	if (g_cpufreq_lock_id) {
+		for (i = 0; i < DVFS_LOCK_ID_END; i++) {
+			if (g_cpufreq_lock_val[i] < g_cpufreq_lock_level)
+				g_cpufreq_lock_level = g_cpufreq_lock_val[i];
+		}
+	}
+	mutex_unlock(&set_cpu_freq_lock);
+}
+EXPORT_SYMBOL_GPL(exynos_cpufreq_lock_free);
+
+#ifdef CONFIG_SLP
+static int exynos_cpu_dma_qos_notify(struct notifier_block *nb,
+				     unsigned long value, void *data)
+{
+	int i;
+	struct dvfs_qos_info *table;
+	enum cpufreq_level_index last_lvl = L0;
+
+	if (!exynos_info || !exynos_info->cpu_dma_latency)
+		return NOTIFY_DONE;
+
+	if (value == 0 || value == PM_QOS_DEFAULT_VALUE ||
+	    value == PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE) {
+		exynos_cpufreq_lock_free(DVFS_LOCK_ID_QOS_DMA_LATENCY);
+		return NOTIFY_OK;
+	}
+
+	table = exynos_info->cpu_dma_latency;
+
+	for (i = 0; table[i].qos_value; i++) {
+		if (value >= table[i].qos_value) {
+			exynos_cpufreq_lock(DVFS_LOCK_ID_QOS_DMA_LATENCY,
+					    table[i].level);
+			return NOTIFY_OK;
+		}
+		last_lvl = table[i].level;
+	}
+
+	if (last_lvl > L0)
+		last_lvl--;
+
+	exynos_cpufreq_lock(DVFS_LOCK_ID_QOS_DMA_LATENCY, last_lvl);
+
+	return NOTIFY_OK;
+}
+
+static struct notifier_block pm_qos_cpu_dma_notifier = {
+	.notifier_call = exynos_cpu_dma_qos_notify,
+};
+#endif /* CONFIG_SLP */
+
+int exynos_cpufreq_upper_limit(unsigned int nId,
+				enum cpufreq_level_index cpufreq_level)
+{
+	int ret = 0, old_idx = 0, i;
+	unsigned int freq_old, freq_new, arm_volt, safe_arm_volt;
+	unsigned int *volt_table;
+	struct cpufreq_policy *policy;
+	struct cpufreq_frequency_table *freq_table;
+
+	if (!exynos_cpufreq_init_done)
+		return -EPERM;
+
+	if (!exynos_info)
+		return -EPERM;
+
+	if (exynos_cpufreq_disable) {
+		pr_info("CPUFreq is already fixed\n");
+		return -EPERM;
+	}
+
+	if (cpufreq_level < exynos_info->max_support_idx
+			|| cpufreq_level > exynos_info->min_support_idx) {
+		pr_warn("%s: invalid cpufreq_level(%d:%d)\n", __func__, nId,
+				cpufreq_level);
+		return -EINVAL;
+	}
+
+	policy = cpufreq_cpu_get(0);
+	if (!policy)
+		return -EPERM;
+
+	volt_table = exynos_info->volt_table;
+	freq_table = exynos_info->freq_table;
+
+	mutex_lock(&set_cpu_freq_lock);
+	if (g_cpufreq_limit_id & (1 << nId)) {
+		pr_err("[CPUFREQ]This device [%d] already limited cpufreq\n", nId);
+		mutex_unlock(&set_cpu_freq_lock);
+		return 0;
+	}
+
+	g_cpufreq_limit_id |= (1 << nId);
+	g_cpufreq_limit_val[nId] = cpufreq_level;
+
+	/* If the requested limit level is lower than current value */
+	if (cpufreq_level > g_cpufreq_limit_level)
+		g_cpufreq_limit_level = cpufreq_level;
+
+	mutex_unlock(&set_cpu_freq_lock);
+
+	mutex_lock(&set_freq_lock);
+	/* If cur frequency is higher than limit freq, it needs to update */
+	freq_old = policy->cur;
+	freq_new = freq_table[cpufreq_level].frequency;
+	if (freq_old > freq_new) {
+		/* Find out current level index */
+		for (i = 0; i <= exynos_info->min_support_idx; i++) {
+			if (freq_old == freq_table[i].frequency) {
+				old_idx = freq_table[i].index;
+				break;
+			} else if (i == exynos_info->min_support_idx) {
+				printk(KERN_ERR "%s: Level is not found\n", __func__);
+				mutex_unlock(&set_freq_lock);
+
+				return -EINVAL;
+			} else {
+				continue;
+			}
+		}
+		freqs.old = freq_old;
+		freqs.new = freq_new;
+
+		cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+
+		exynos_info->set_freq(old_idx, cpufreq_level);
+
+		safe_arm_volt = exynos_get_safe_armvolt(old_idx, cpufreq_level);
+		if (safe_arm_volt)
+			regulator_set_voltage(arm_regulator, safe_arm_volt,
+					     safe_arm_volt + 25000);
+
+		arm_volt = volt_table[cpufreq_level];
+		regulator_set_voltage(arm_regulator, arm_volt, arm_volt + 25000);
+
+		cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+	}
+
+	mutex_unlock(&set_freq_lock);
+
+	return ret;
+}
+
+void exynos_cpufreq_upper_limit_free(unsigned int nId)
+{
+	unsigned int i;
+
+	if (!exynos_cpufreq_init_done)
+		return;
+
+	mutex_lock(&set_cpu_freq_lock);
+	g_cpufreq_limit_id &= ~(1 << nId);
+	g_cpufreq_limit_val[nId] = exynos_info->max_support_idx;
+	g_cpufreq_limit_level = exynos_info->max_support_idx;
+
+	if (g_cpufreq_limit_id) {
+		for (i = 0; i < DVFS_LOCK_ID_END; i++) {
+			if (g_cpufreq_limit_val[i] > g_cpufreq_limit_level)
+				g_cpufreq_limit_level = g_cpufreq_limit_val[i];
+		}
+	}
+	mutex_unlock(&set_cpu_freq_lock);
+}
+
+/* This API serve highest priority level locking */
+int exynos_cpufreq_level_fix(unsigned int freq)
+{
+	struct cpufreq_policy *policy;
+	int ret = 0;
+
+	if (!exynos_cpufreq_init_done)
+		return -EPERM;
+
+	policy = cpufreq_cpu_get(0);
+	if (!policy)
+		return -EPERM;
+
+	if (exynos_cpufreq_disable) {
+		pr_info("CPUFreq is already fixed\n");
+		return -EPERM;
+	}
+	ret = exynos_target(policy, freq, CPUFREQ_RELATION_L);
+
+	exynos_cpufreq_disable = true;
+	return ret;
+
+}
+EXPORT_SYMBOL_GPL(exynos_cpufreq_level_fix);
+
+void exynos_cpufreq_level_unfix(void)
+{
+	if (!exynos_cpufreq_init_done)
+		return;
+
+	exynos_cpufreq_disable = false;
+}
+EXPORT_SYMBOL_GPL(exynos_cpufreq_level_unfix);
+
+int exynos_cpufreq_is_fixed(void)
+{
+	return exynos_cpufreq_disable;
+}
+EXPORT_SYMBOL_GPL(exynos_cpufreq_is_fixed);
+
+#ifdef CONFIG_PM
+static int exynos_cpufreq_suspend(struct cpufreq_policy *policy)
+{
+	return 0;
+}
+
+static int exynos_cpufreq_resume(struct cpufreq_policy *policy)
+{
+	return 0;
+}
+#endif
+
+static void exynos_save_gov_freq(void)
+{
+	unsigned int cpu = 0;
+
+	exynos_info->gov_support_freq = exynos_getspeed(cpu);
+	pr_debug("cur_freq[%d] saved to freq[%d]\n", exynos_getspeed(0),
+			exynos_info->gov_support_freq);
+}
+
+static void exynos_restore_gov_freq(struct cpufreq_policy *policy)
+{
+	unsigned int cpu = 0;
+
+	if (exynos_getspeed(cpu) != exynos_info->gov_support_freq)
+		exynos_target(policy, exynos_info->gov_support_freq,
+				CPUFREQ_RELATION_H);
+
+	pr_debug("freq[%d] restored to cur_freq[%d]\n",
+			exynos_info->gov_support_freq, exynos_getspeed(cpu));
+}
+
+static int exynos_cpufreq_notifier_event(struct notifier_block *this,
+		unsigned long event, void *ptr)
+{
+	int ret = 0;
+	unsigned int cpu = 0;
+	struct cpufreq_policy *policy = cpufreq_cpu_get(cpu);
+
+	switch (event) {
+	case PM_SUSPEND_PREPARE:
+	case PM_HIBERNATION_PREPARE:
+	case PM_RESTORE_PREPARE:
+		/* If current governor is userspace or performance or powersave,
+		 * save the current cpufreq before sleep.
+		 */
+		if (exynos_cpufreq_lock_disable)
+			exynos_save_gov_freq();
+
+		ret = exynos_cpufreq_lock(DVFS_LOCK_ID_PM,
+					   exynos_info->pm_lock_idx);
+		if (ret < 0)
+			return NOTIFY_BAD;
+#if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SLP)
+		ret = exynos_cpufreq_upper_limit(DVFS_LOCK_ID_PM,
+						exynos_info->pm_lock_idx);
+		if (ret < 0)
+			return NOTIFY_BAD;
+#endif
+		exynos_cpufreq_disable = true;
+
+#ifdef CONFIG_SLP
+		/*
+		 * Safe Voltage for Suspend/Wakeup: Falling back to the
+		 * default value of bootloaders.
+		 * Note that at suspended state, this 'high' voltage does
+		 * not incur higher power consumption because it is OFF.
+		 * This is for the stability during suspend/wakeup process.
+		 */
+		regulator_set_voltage(arm_regulator, 120000, 120000 + 25000);
+#endif
+
+		pr_debug("PM_SUSPEND_PREPARE for CPUFREQ\n");
+		return NOTIFY_OK;
+	case PM_POST_RESTORE:
+	case PM_POST_HIBERNATION:
+	case PM_POST_SUSPEND:
+		pr_debug("PM_POST_SUSPEND for CPUFREQ: %d\n", ret);
+		exynos_cpufreq_lock_free(DVFS_LOCK_ID_PM);
+#if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SLP)
+		exynos_cpufreq_upper_limit_free(DVFS_LOCK_ID_PM);
+#endif
+		exynos_cpufreq_disable = false;
+		/* If current governor is userspace or performance or powersave,
+		 * restore the saved cpufreq after waekup.
+		 */
+		if (exynos_cpufreq_lock_disable)
+			exynos_restore_gov_freq(policy);
+
+
+		return NOTIFY_OK;
+	}
+	return NOTIFY_DONE;
+}
+
+static struct notifier_block exynos_cpufreq_notifier = {
+	.notifier_call = exynos_cpufreq_notifier_event,
+};
+
+static int exynos_cpufreq_policy_notifier_call(struct notifier_block *this,
+				unsigned long code, void *data)
+{
+	struct cpufreq_policy *policy = data;
+
+	switch (code) {
+	case CPUFREQ_ADJUST:
+		if ((!strnicmp(policy->governor->name, "powersave", CPUFREQ_NAME_LEN))
+		|| (!strnicmp(policy->governor->name, "performance", CPUFREQ_NAME_LEN))
+		|| (!strnicmp(policy->governor->name, "userspace", CPUFREQ_NAME_LEN))) {
+			printk(KERN_DEBUG "cpufreq governor is changed to %s\n",
+							policy->governor->name);
+			exynos_cpufreq_lock_disable = true;
+		} else
+			exynos_cpufreq_lock_disable = false;
+
+	case CPUFREQ_INCOMPATIBLE:
+	case CPUFREQ_NOTIFY:
+	default:
+		break;
+	}
+
+	return NOTIFY_DONE;
+}
+
+static struct notifier_block exynos_cpufreq_policy_notifier = {
+	.notifier_call = exynos_cpufreq_policy_notifier_call,
+};
+
+
+static int exynos_cpufreq_cpu_init(struct cpufreq_policy *policy)
+{
+	policy->cur = policy->min = policy->max = exynos_getspeed(policy->cpu);
+
+	cpufreq_frequency_table_get_attr(exynos_info->freq_table, policy->cpu);
+
+	/* set the transition latency value */
+	policy->cpuinfo.transition_latency = 100000;
+
+	/*
+	 * EXYNOS4 multi-core processors has 2 cores
+	 * that the frequency cannot be set independently.
+	 * Each cpu is bound to the same speed.
+	 * So the affected cpu is all of the cpus.
+	 */
+	if (num_online_cpus() == 1) {
+		cpumask_copy(policy->related_cpus, cpu_possible_mask);
+		cpumask_copy(policy->cpus, cpu_online_mask);
+	} else {
+		cpumask_setall(policy->cpus);
+	}
+
+	return cpufreq_frequency_table_cpuinfo(policy, exynos_info->freq_table);
+}
+
+static int exynos_cpufreq_reboot_notifier_call(struct notifier_block *this,
+				   unsigned long code, void *_cmd)
+{
+	int ret = 0;
+
+	ret = exynos_cpufreq_lock(DVFS_LOCK_ID_PM, exynos_info->pm_lock_idx);
+	if (ret < 0)
+		return NOTIFY_BAD;
+
+	printk(KERN_INFO "REBOOT Notifier for CPUFREQ\n");
+	return NOTIFY_DONE;
+}
+
+static struct notifier_block exynos_cpufreq_reboot_notifier = {
+	.notifier_call = exynos_cpufreq_reboot_notifier_call,
+};
+
+static struct cpufreq_driver exynos_driver = {
+	.flags		= CPUFREQ_STICKY,
+	.verify		= exynos_verify_speed,
+	.target		= exynos_target,
+	.get		= exynos_getspeed,
+	.init		= exynos_cpufreq_cpu_init,
+	.name		= "exynos_cpufreq",
+#ifdef CONFIG_PM
+	.suspend	= exynos_cpufreq_suspend,
+	.resume		= exynos_cpufreq_resume,
+#endif
+};
+
+static int __init exynos_cpufreq_init(void)
+{
+	int ret = -EINVAL;
+	int i;
+
+	exynos_info = kzalloc(sizeof(struct exynos_dvfs_info), GFP_KERNEL);
+	if (!exynos_info)
+		return -ENOMEM;
+
+	if (soc_is_exynos4210())
+		ret = exynos4210_cpufreq_init(exynos_info);
+	else if (soc_is_exynos4212() || soc_is_exynos4412())
+		ret = exynos4x12_cpufreq_init(exynos_info);
+	else if (soc_is_exynos5250())
+		ret = exynos5250_cpufreq_init(exynos_info);
+	else
+		pr_err("%s: CPU type not found\n", __func__);
+
+	if (ret)
+		goto err_vdd_arm;
+
+	if (exynos_info->set_freq == NULL) {
+		printk(KERN_ERR "%s: No set_freq function (ERR)\n",
+				__func__);
+		goto err_vdd_arm;
+	}
+
+	arm_regulator = regulator_get(NULL, "vdd_arm");
+	if (IS_ERR(arm_regulator)) {
+		printk(KERN_ERR "failed to get resource %s\n", "vdd_arm");
+		goto err_vdd_arm;
+	}
+
+	exynos_cpufreq_disable = false;
+
+	register_pm_notifier(&exynos_cpufreq_notifier);
+	register_reboot_notifier(&exynos_cpufreq_reboot_notifier);
+	cpufreq_register_notifier(&exynos_cpufreq_policy_notifier,
+						CPUFREQ_POLICY_NOTIFIER);
+
+	exynos_cpufreq_init_done = true;
+
+	for (i = 0; i < DVFS_LOCK_ID_END; i++) {
+		g_cpufreq_lock_val[i] = exynos_info->min_support_idx;
+		g_cpufreq_limit_val[i] = exynos_info->max_support_idx;
+	}
+
+	g_cpufreq_lock_level = exynos_info->min_support_idx;
+	g_cpufreq_limit_level = exynos_info->max_support_idx;
+
+	if (cpufreq_register_driver(&exynos_driver)) {
+		pr_err("failed to register cpufreq driver\n");
+		goto err_cpufreq;
+	}
+
+#ifdef CONFIG_SLP
+	if (exynos_info->cpu_dma_latency)
+		pm_qos_add_notifier(PM_QOS_CPU_DMA_LATENCY,
+				    &pm_qos_cpu_dma_notifier);
+#endif
+
+	return 0;
+err_cpufreq:
+	unregister_reboot_notifier(&exynos_cpufreq_reboot_notifier);
+	unregister_pm_notifier(&exynos_cpufreq_notifier);
+
+	if (!IS_ERR(arm_regulator))
+		regulator_put(arm_regulator);
+err_vdd_arm:
+	kfree(exynos_info);
+	pr_debug("%s: failed initialization\n", __func__);
+	return -EINVAL;
+}
+late_initcall(exynos_cpufreq_init);
diff --git a/arch/arm/mach-exynos/cpuidle-exynos4.c b/arch/arm/mach-exynos/cpuidle-exynos4.c
new file mode 100644
index 0000000..6afdacd
--- /dev/null
+++ b/arch/arm/mach-exynos/cpuidle-exynos4.c
@@ -0,0 +1,1024 @@
+/* linux/arch/arm/mach-exynos/cpuidle-exynos4.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/cpuidle.h>
+#include <linux/io.h>
+#include <linux/suspend.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+
+#include <asm/proc-fns.h>
+#include <asm/tlbflush.h>
+#include <asm/cacheflush.h>
+
+#include <mach/regs-clock.h>
+#include <mach/regs-pmu.h>
+#include <mach/pmu.h>
+#include <mach/gpio.h>
+#include <mach/smc.h>
+#include <mach/clock-domain.h>
+#include <mach/regs-audss.h>
+#include <mach/asv.h>
+#include <mach/regs-usb-phy.h>
+
+#include <plat/regs-otg.h>
+#include <plat/exynos4.h>
+#include <plat/pm.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+#ifdef CONFIG_SEC_WATCHDOG_RESET
+#include <plat/regs-watchdog.h>
+#endif
+#include <mach/regs-usb-phy.h>
+#include <plat/usb-phy.h>
+
+
+#ifdef CONFIG_ARM_TRUSTZONE
+#define REG_DIRECTGO_ADDR	(S5P_VA_SYSRAM_NS + 0x24)
+#define REG_DIRECTGO_FLAG	(S5P_VA_SYSRAM_NS + 0x20)
+#else
+#define REG_DIRECTGO_ADDR	(samsung_rev() < EXYNOS4210_REV_1_1 ?\
+				(S5P_VA_SYSRAM + 0x24) : S5P_INFORM7)
+#define REG_DIRECTGO_FLAG	(samsung_rev() < EXYNOS4210_REV_1_1 ?\
+				(S5P_VA_SYSRAM + 0x20) : S5P_INFORM6)
+#endif
+
+#include <asm/hardware/gic.h>
+#include <plat/map-base.h>
+#include <plat/map-s5p.h>
+
+extern unsigned long sys_pwr_conf_addr;
+extern unsigned int l2x0_save[3];
+extern unsigned int scu_save[2];
+
+enum hc_type {
+	HC_SDHC,
+	HC_MSHC,
+};
+
+enum idle_clock_down {
+	HW_CLK_DWN,
+	SW_CLK_DWN,
+};
+
+unsigned int use_clock_down;
+
+struct check_device_op {
+	void __iomem		*base;
+	struct platform_device	*pdev;
+	enum hc_type		type;
+};
+
+#ifdef CONFIG_MACH_MIDAS
+unsigned int log_en = 1;
+#else
+unsigned int log_en;
+#endif
+module_param_named(log_en, log_en, uint, 0644);
+
+#if defined(CONFIG_MACH_MIDAS) || defined(CONFIG_SLP)
+#define CPUDILE_ENABLE_MASK (ENABLE_LPA)
+#else
+#define CPUDILE_ENABLE_MASK (ENABLE_AFTR | ENABLE_LPA)
+#endif
+
+static enum {
+	ENABLE_IDLE = 0x0,
+	ENABLE_AFTR = 0x1,
+	ENABLE_LPA  = 0x2
+} enable_mask = CPUDILE_ENABLE_MASK;
+module_param_named(enable_mask, enable_mask, uint, 0644);
+
+#define ENABLE_LOWPWRMASK (ENABLE_AFTR | ENABLE_LPA)
+
+static struct check_device_op chk_sdhc_op[] = {
+#if defined(CONFIG_EXYNOS4_DEV_DWMCI)
+	{.base = 0, .pdev = &exynos_device_dwmci, .type = HC_MSHC},
+#endif
+#if defined(CONFIG_EXYNOS4_DEV_MSHC)
+	{.base = 0, .pdev = &s3c_device_mshci, .type = HC_MSHC},
+#endif
+#if defined(CONFIG_S3C_DEV_HSMMC)
+	{.base = 0, .pdev = &s3c_device_hsmmc0, .type = HC_SDHC},
+#endif
+#if defined(CONFIG_S3C_DEV_HSMMC1)
+	{.base = 0, .pdev = &s3c_device_hsmmc1, .type = HC_SDHC},
+#endif
+#if defined(CONFIG_S3C_DEV_HSMMC2)
+	{.base = 0, .pdev = &s3c_device_hsmmc2, .type = HC_SDHC},
+#endif
+#if defined(CONFIG_S3C_DEV_HSMMC3)
+	{.base = 0, .pdev = &s3c_device_hsmmc3, .type = HC_SDHC},
+#endif
+};
+
+#if defined(CONFIG_USB_S3C_OTGD) && !defined(CONFIG_USB_EXYNOS_SWITCH)
+static struct check_device_op chk_usbotg_op = {
+	.base = 0, .pdev = &s3c_device_usbgadget, .type = 0
+};
+#endif
+
+#define S3C_HSMMC_PRNSTS	(0x24)
+#define S3C_HSMMC_CLKCON	(0x2c)
+#define S3C_HSMMC_CMD_INHIBIT	0x00000001
+#define S3C_HSMMC_DATA_INHIBIT	0x00000002
+#define S3C_HSMMC_CLOCK_CARD_EN	0x0004
+
+#define MSHCI_CLKENA	(0x10)  /* Clock enable */
+#define MSHCI_STATUS	(0x48)  /* Status */
+#define MSHCI_DATA_BUSY	(0x1<<9)
+#define MSHCI_DATA_STAT_BUSY	(0x1<<10)
+#define MSHCI_ENCLK	(0x1)
+
+#define GPIO_OFFSET		0x20
+#define GPIO_PUD_OFFSET		0x08
+#define GPIO_CON_PDN_OFFSET	0x10
+#define GPIO_PUD_PDN_OFFSET	0x14
+#define GPIO_END_OFFSET		0x200
+
+/* GPIO_END_OFFSET value of exynos4212 */
+#define GPIO1_END_OFFSET	0x280
+#define GPIO2_END_OFFSET	0x200
+#define GPIO4_END_OFFSET	0xE0
+
+static void exynos4_gpio_conpdn_reg(void)
+{
+	void __iomem *gpio_base = S5P_VA_GPIO;
+	unsigned int val;
+
+	do {
+		/* Keep the previous state in didle mode */
+		__raw_writel(0xffff, gpio_base + GPIO_CON_PDN_OFFSET);
+
+		/* Pull up-down state in didle is same as normal */
+		val = __raw_readl(gpio_base + GPIO_PUD_OFFSET);
+		__raw_writel(val, gpio_base + GPIO_PUD_PDN_OFFSET);
+
+		gpio_base += GPIO_OFFSET;
+
+		if (gpio_base == S5P_VA_GPIO + GPIO_END_OFFSET)
+			gpio_base = S5P_VA_GPIO2;
+
+	} while (gpio_base <= S5P_VA_GPIO2 + GPIO_END_OFFSET);
+
+	/* set the GPZ */
+	gpio_base = S5P_VA_GPIO3;
+	__raw_writel(0xffff, gpio_base + GPIO_CON_PDN_OFFSET);
+
+	val = __raw_readl(gpio_base + GPIO_PUD_OFFSET);
+	__raw_writel(val, gpio_base + GPIO_PUD_PDN_OFFSET);
+}
+
+static void exynos4212_gpio_conpdn_reg(void)
+{
+	void __iomem *gpio_base = S5P_VA_GPIO;
+	unsigned int val;
+
+	do {
+		/* Keep the previous state in didle mode */
+		__raw_writel(0xffff, gpio_base + GPIO_CON_PDN_OFFSET);
+
+		/* Pull up-down state in didle is same as normal */
+		val = __raw_readl(gpio_base + GPIO_PUD_OFFSET);
+		__raw_writel(val, gpio_base + GPIO_PUD_PDN_OFFSET);
+
+		gpio_base += GPIO_OFFSET;
+
+		/* Skip gpio_base there aren't gpios in part1 & part4 of exynos4212 */
+		if (gpio_base == (S5P_VA_GPIO + 0xE0))
+			gpio_base = S5P_VA_GPIO + 0x180;
+		else if (gpio_base == (S5P_VA_GPIO + 0x200))
+			gpio_base = S5P_VA_GPIO + 0x240;
+		else if (gpio_base == (S5P_VA_GPIO4 + 0x40))
+			gpio_base = S5P_VA_GPIO4 + 0x60;
+		else if (gpio_base == (S5P_VA_GPIO4 + 0xA0))
+			gpio_base = S5P_VA_GPIO4 + 0xC0;
+
+		if (gpio_base == S5P_VA_GPIO + GPIO1_END_OFFSET)
+			gpio_base = S5P_VA_GPIO2 + 0x40; /* GPK0CON */
+
+		if (gpio_base == S5P_VA_GPIO2 + GPIO2_END_OFFSET)
+			gpio_base = S5P_VA_GPIO4;
+
+	} while (gpio_base <= S5P_VA_GPIO4 + GPIO4_END_OFFSET);
+
+	/* set the GPZ */
+	gpio_base = S5P_VA_GPIO3;
+	__raw_writel(0xffff, gpio_base + GPIO_CON_PDN_OFFSET);
+
+	val = __raw_readl(gpio_base + GPIO_PUD_OFFSET);
+	__raw_writel(val, gpio_base + GPIO_PUD_PDN_OFFSET);
+}
+
+static int check_power_domain(void)
+{
+	unsigned long tmp;
+
+	tmp = __raw_readl(S5P_PMU_LCD0_CONF);
+	if ((tmp & S5P_INT_LOCAL_PWR_EN) == S5P_INT_LOCAL_PWR_EN)
+		return 1;
+
+	tmp = __raw_readl(S5P_PMU_MFC_CONF);
+	if ((tmp & S5P_INT_LOCAL_PWR_EN) == S5P_INT_LOCAL_PWR_EN)
+		return 1;
+
+	tmp = __raw_readl(S5P_PMU_G3D_CONF);
+	if ((tmp & S5P_INT_LOCAL_PWR_EN) == S5P_INT_LOCAL_PWR_EN)
+		return 1;
+
+	tmp = __raw_readl(S5P_PMU_CAM_CONF);
+	if ((tmp & S5P_INT_LOCAL_PWR_EN) == S5P_INT_LOCAL_PWR_EN)
+		return 1;
+
+	tmp = __raw_readl(S5P_PMU_TV_CONF);
+	if ((tmp & S5P_INT_LOCAL_PWR_EN) == S5P_INT_LOCAL_PWR_EN)
+		return 1;
+
+	tmp = __raw_readl(S5P_PMU_GPS_CONF);
+	if ((tmp & S5P_INT_LOCAL_PWR_EN) == S5P_INT_LOCAL_PWR_EN)
+		return 1;
+
+	return 0;
+}
+
+static int __maybe_unused check_clock_gating(void)
+{
+	unsigned long tmp;
+
+	tmp = __raw_readl(EXYNOS4_CLKGATE_IP_IMAGE);
+	if (tmp & (EXYNOS4_CLKGATE_IP_IMAGE_MDMA | EXYNOS4_CLKGATE_IP_IMAGE_SMMUMDMA
+		| EXYNOS4_CLKGATE_IP_IMAGE_QEMDMA))
+		return 1;
+
+	tmp = __raw_readl(EXYNOS4_CLKGATE_IP_FSYS);
+	if (tmp & (EXYNOS4_CLKGATE_IP_FSYS_PDMA0 | EXYNOS4_CLKGATE_IP_FSYS_PDMA1))
+		return 1;
+
+	tmp = __raw_readl(EXYNOS4_CLKGATE_IP_PERIL);
+	if (tmp & EXYNOS4_CLKGATE_IP_PERIL_I2C0_7)
+		return 1;
+
+	return 0;
+}
+
+static int sdmmc_dev_num;
+/* If SD/MMC interface is working: return = 1 or not 0 */
+static int check_sdmmc_op(unsigned int ch)
+{
+	unsigned int reg1, reg2;
+	void __iomem *base_addr;
+
+	if (unlikely(ch >= sdmmc_dev_num)) {
+		printk(KERN_ERR "Invalid ch[%d] for SD/MMC\n", ch);
+		return 0;
+	}
+
+	if (chk_sdhc_op[ch].type == HC_SDHC) {
+		base_addr = chk_sdhc_op[ch].base;
+		/* Check CLKCON [2]: ENSDCLK */
+		reg2 = readl(base_addr + S3C_HSMMC_CLKCON);
+		return !!(reg2 & (S3C_HSMMC_CLOCK_CARD_EN));
+	} else if (chk_sdhc_op[ch].type == HC_MSHC) {
+		base_addr = chk_sdhc_op[ch].base;
+		/* Check STATUS [9] for data busy */
+		reg1 = readl(base_addr + MSHCI_STATUS);
+		return (reg1 & (MSHCI_DATA_BUSY)) ||
+		       (reg1 & (MSHCI_DATA_STAT_BUSY));
+
+	}
+	/* should not be here */
+	return 0;
+}
+
+/* Check all sdmmc controller */
+static int loop_sdmmc_check(void)
+{
+	unsigned int iter;
+
+	for (iter = 0; iter < sdmmc_dev_num; iter++) {
+		if (check_sdmmc_op(iter))
+			return 1;
+	}
+	return 0;
+}
+
+/*
+ * Check USB Device and Host is working or not
+ * USB_S3C-OTGD can check GOTGCTL register
+ * GOTGCTL(0xEC000000)
+ * BSesVld (Indicates the Device mode transceiver status)
+ * BSesVld =	1b : B-session is valid
+ *		0b : B-session is not valiid
+ * USB_EXYNOS_SWITCH can check Both Host and Device status.
+ */
+static int check_usb_op(void)
+{
+#if defined(CONFIG_USB_S3C_OTGD) && !defined(CONFIG_USB_EXYNOS_SWITCH)
+	void __iomem *base_addr;
+	unsigned int val;
+
+	base_addr = chk_usbotg_op.base;
+	val = __raw_readl(base_addr + S3C_UDC_OTG_GOTGCTL);
+
+	return val & (A_SESSION_VALID | B_SESSION_VALID);
+#elif defined(CONFIG_USB_EXYNOS_SWITCH)
+	return exynos_check_usb_op();
+#else
+	return 0;
+#endif
+}
+
+#ifdef CONFIG_SND_SAMSUNG_RP
+extern int srp_get_op_level(void);	/* By srp driver */
+#endif
+
+#if defined(CONFIG_BT)
+static inline int check_bt_op(void)
+{
+	extern int bt_is_running;
+
+	return bt_is_running;
+}
+#endif
+
+static int gps_is_running;
+
+void set_gps_uart_op(int onoff)
+{
+	pr_info("%s: %s\n", __func__, onoff ? "on" : "off");
+	gps_is_running = onoff;
+}
+
+static inline int check_gps_uart_op(void)
+{
+	return gps_is_running;
+}
+
+static int exynos4_check_operation(void)
+{
+	if (check_power_domain())
+		return 1;
+
+	if (clock_domain_enabled(LPA_DOMAIN))
+		return 1;
+
+	if (loop_sdmmc_check())
+		return 1;
+#ifdef CONFIG_SND_SAMSUNG_RP
+	if (srp_get_op_level())
+		return 1;
+#endif
+	if (check_usb_op())
+		return 1;
+
+#if defined(CONFIG_BT)
+	if (check_bt_op())
+		return 1;
+#endif
+
+	if (check_gps_uart_op())
+		return 1;
+
+	if (exynos4_check_usb_op())
+		return 1;
+
+	return 0;
+}
+
+#ifdef CONFIG_SEC_WATCHDOG_RESET
+static struct sleep_save exynos4_aftr_save[] = {
+	SAVE_ITEM(S3C2410_WTDAT),
+	SAVE_ITEM(S3C2410_WTCNT),
+	SAVE_ITEM(S3C2410_WTCON),
+};
+#endif
+
+static struct sleep_save exynos4_lpa_save[] = {
+	/* CMU side */
+	SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TOP),
+	SAVE_ITEM(EXYNOS4_CLKSRC_MASK_CAM),
+	SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TV),
+	SAVE_ITEM(EXYNOS4_CLKSRC_MASK_LCD0),
+	SAVE_ITEM(EXYNOS4_CLKSRC_MASK_LCD1),
+	SAVE_ITEM(EXYNOS4_CLKSRC_MASK_MAUDIO),
+	SAVE_ITEM(EXYNOS4_CLKSRC_MASK_FSYS),
+	SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL0),
+	SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL1),
+	SAVE_ITEM(EXYNOS4_CLKSRC_MASK_DMC),
+#ifdef CONFIG_SEC_WATCHDOG_RESET
+	SAVE_ITEM(S3C2410_WTDAT),
+	SAVE_ITEM(S3C2410_WTCNT),
+	SAVE_ITEM(S3C2410_WTCON),
+#endif
+};
+
+static struct sleep_save exynos4_set_clksrc[] = {
+	{ .reg = EXYNOS4_CLKSRC_MASK_TOP		, .val = 0x00000001, },
+	{ .reg = EXYNOS4_CLKSRC_MASK_CAM		, .val = 0x11111111, },
+	{ .reg = EXYNOS4_CLKSRC_MASK_TV			, .val = 0x00000111, },
+	{ .reg = EXYNOS4_CLKSRC_MASK_LCD0		, .val = 0x00001111, },
+	{ .reg = EXYNOS4_CLKSRC_MASK_MAUDIO		, .val = 0x00000001, },
+	{ .reg = EXYNOS4_CLKSRC_MASK_FSYS		, .val = 0x01011111, },
+	{ .reg = EXYNOS4_CLKSRC_MASK_PERIL0		, .val = 0x01111111, },
+	{ .reg = EXYNOS4_CLKSRC_MASK_PERIL1		, .val = 0x01110111, },
+	{ .reg = EXYNOS4_CLKSRC_MASK_DMC		, .val = 0x00010000, },
+};
+
+static struct sleep_save exynos4210_set_clksrc[] = {
+	{ .reg = EXYNOS4_CLKSRC_MASK_LCD1		, .val = 0x00001111, },
+};
+
+static int exynos4_check_enter(void)
+{
+	unsigned int ret;
+	unsigned int check_val;
+
+	ret = 0;
+
+	/* Check UART for console is empty */
+	check_val = __raw_readl(S5P_VA_UART(CONFIG_S3C_LOWLEVEL_UART_PORT) +
+				0x18);
+
+	ret = ((check_val >> 16) & 0xff);
+
+	return ret;
+}
+
+void exynos4_flush_cache(void *addr, phys_addr_t phy_ttb_base)
+{
+	outer_clean_range(virt_to_phys(addr - 0x40),
+			  virt_to_phys(addr + 0x40));
+	outer_clean_range(virt_to_phys(cpu_resume),
+			  virt_to_phys(cpu_resume + 0x40));
+	outer_clean_range(phy_ttb_base, phy_ttb_base + 0xffff);
+	flush_cache_all();
+}
+
+static void exynos4_set_wakeupmask(void)
+{
+	__raw_writel(0x0000ff3e, S5P_WAKEUP_MASK);
+}
+
+static void vfp_enable(void *unused)
+{
+	u32 access = get_copro_access();
+
+	/*
+	 * Enable full access to VFP (cp10 and cp11)
+	 */
+	set_copro_access(access | CPACC_FULL(10) | CPACC_FULL(11));
+}
+
+static int exynos4_enter_core0_aftr(struct cpuidle_device *dev,
+				    struct cpuidle_state *state)
+{
+	struct timeval before, after;
+	int idle_time;
+	unsigned long tmp, abb_val;
+
+#ifdef CONFIG_SEC_WATCHDOG_RESET
+	s3c_pm_do_save(exynos4_aftr_save, ARRAY_SIZE(exynos4_aftr_save));
+#endif
+
+	local_irq_disable();
+
+	if (log_en)
+		pr_info("+++aftr\n");
+
+	do_gettimeofday(&before);
+
+	exynos4_set_wakeupmask();
+
+	__raw_writel(virt_to_phys(exynos4_idle_resume), REG_DIRECTGO_ADDR);
+	__raw_writel(0xfcba0d10, REG_DIRECTGO_FLAG);
+
+	/* Set value of power down register for aftr mode */
+	exynos4_sys_powerdown_conf(SYS_AFTR);
+
+	if (!soc_is_exynos4210())
+		exynos4_reset_assert_ctrl(0);
+
+#ifdef CONFIG_EXYNOS4_CPUFREQ
+	if (!soc_is_exynos4210()) {
+		abb_val = exynos4x12_get_abb_member(ABB_ARM);
+		exynos4x12_set_abb_member(ABB_ARM, ABB_MODE_075V);
+	}
+#endif
+
+	if (exynos4_enter_lp(0, PLAT_PHYS_OFFSET - PAGE_OFFSET) == 0) {
+
+		/*
+		 * Clear Central Sequence Register in exiting early wakeup
+		 */
+		tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+		tmp |= (S5P_CENTRAL_LOWPWR_CFG);
+		__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+
+		goto early_wakeup;
+	}
+	flush_tlb_all();
+
+	cpu_init();
+
+	vfp_enable(NULL);
+
+#ifdef CONFIG_SEC_WATCHDOG_RESET
+	s3c_pm_do_restore_core(exynos4_aftr_save,
+				ARRAY_SIZE(exynos4_aftr_save));
+#endif
+
+early_wakeup:
+#ifdef CONFIG_EXYNOS4_CPUFREQ
+	if ((exynos_result_of_asv > 1) && !soc_is_exynos4210())
+		exynos4x12_set_abb_member(ABB_ARM, abb_val);
+#endif
+
+	if (!soc_is_exynos4210())
+		exynos4_reset_assert_ctrl(1);
+
+	/* Clear wakeup state register */
+	__raw_writel(0x0, S5P_WAKEUP_STAT);
+
+	do_gettimeofday(&after);
+
+	if (log_en)
+		pr_info("---aftr\n");
+
+	local_irq_enable();
+	idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
+		    (after.tv_usec - before.tv_usec);
+
+	return idle_time;
+}
+
+extern void bt_uart_rts_ctrl(int flag);
+
+static int exynos4_enter_core0_lpa(struct cpuidle_device *dev,
+				   struct cpuidle_state *state)
+{
+	struct timeval before, after;
+	int idle_time;
+	unsigned long tmp, abb_val, abb_val_int;
+
+	s3c_pm_do_save(exynos4_lpa_save, ARRAY_SIZE(exynos4_lpa_save));
+
+	/*
+	 * Before enter central sequence mode, clock src register have to set
+	 */
+	s3c_pm_do_restore_core(exynos4_set_clksrc,
+			       ARRAY_SIZE(exynos4_set_clksrc));
+
+	if (soc_is_exynos4210())
+		s3c_pm_do_restore_core(exynos4210_set_clksrc, ARRAY_SIZE(exynos4210_set_clksrc));
+
+#if defined(CONFIG_BT)
+	/* BT-UART RTS Control (RTS High) */
+	bt_uart_rts_ctrl(1);
+#endif
+	local_irq_disable();
+
+	if (log_en)
+		pr_info("+++lpa\n");
+
+	do_gettimeofday(&before);
+
+	/*
+	 * Unmasking all wakeup source.
+	 */
+	__raw_writel(0x3ff0000, S5P_WAKEUP_MASK);
+
+	/* Configure GPIO Power down control register */
+#ifdef CONFIG_MIDAS_COMMON
+	if (exynos4_sleep_gpio_table_set)
+		exynos4_sleep_gpio_table_set();
+	else
+#endif
+		exynos4_gpio_conpdn_reg();
+
+	/* ensure at least INFORM0 has the resume address */
+	__raw_writel(virt_to_phys(exynos4_idle_resume), S5P_INFORM0);
+
+	__raw_writel(virt_to_phys(exynos4_idle_resume), REG_DIRECTGO_ADDR);
+	__raw_writel(0xfcba0d10, REG_DIRECTGO_FLAG);
+
+	__raw_writel(S5P_CHECK_LPA, S5P_INFORM1);
+	exynos4_sys_powerdown_conf(SYS_LPA);
+
+	/* Should be fixed on EVT1 */
+	if (!soc_is_exynos4210())
+		exynos4_reset_assert_ctrl(0);
+
+	do {
+		/* Waiting for flushing UART fifo */
+	} while (exynos4_check_enter());
+
+#ifdef CONFIG_EXYNOS4_CPUFREQ
+	if (!soc_is_exynos4210()) {
+		abb_val = exynos4x12_get_abb_member(ABB_ARM);
+		abb_val_int = exynos4x12_get_abb_member(ABB_INT);
+		exynos4x12_set_abb_member(ABB_ARM, ABB_MODE_075V);
+		exynos4x12_set_abb_member(ABB_INT, ABB_MODE_075V);
+	}
+#endif
+
+	if (exynos4_enter_lp(0, PLAT_PHYS_OFFSET - PAGE_OFFSET) == 0) {
+
+		/*
+		 * Clear Central Sequence Register in exiting early wakeup
+		 */
+		tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+		tmp |= (S5P_CENTRAL_LOWPWR_CFG);
+		__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+
+		goto early_wakeup;
+	}
+	flush_tlb_all();
+
+	cpu_init();
+
+	vfp_enable(NULL);
+
+	/* For release retention */
+	__raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
+	__raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
+	__raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
+	__raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
+	__raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
+	__raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
+
+early_wakeup:
+	s3c_pm_do_restore_core(exynos4_lpa_save,
+			       ARRAY_SIZE(exynos4_lpa_save));
+
+#ifdef CONFIG_EXYNOS4_CPUFREQ
+	if ((exynos_result_of_asv > 1) && !soc_is_exynos4210()) {
+		exynos4x12_set_abb_member(ABB_ARM, abb_val);
+		exynos4x12_set_abb_member(ABB_INT, abb_val_int);
+	}
+#endif
+
+	if (!soc_is_exynos4210())
+		exynos4_reset_assert_ctrl(1);
+
+	/* Clear wakeup state register */
+	__raw_writel(0x0, S5P_WAKEUP_STAT);
+
+	__raw_writel(0x0, S5P_WAKEUP_MASK);
+
+	do_gettimeofday(&after);
+
+	if (log_en)
+		pr_info("---lpa\n");
+
+	local_irq_enable();
+	idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
+		    (after.tv_usec - before.tv_usec);
+
+#if defined(CONFIG_BT)
+	/* BT-UART RTS Control (RTS Low) */
+	bt_uart_rts_ctrl(0);
+#endif
+
+	return idle_time;
+}
+
+static int exynos4_enter_idle(struct cpuidle_device *dev,
+			      struct cpuidle_state *state);
+
+static int exynos4_enter_lowpower(struct cpuidle_device *dev,
+				  struct cpuidle_state *state);
+
+static struct cpuidle_state exynos4_cpuidle_set[] = {
+	[0] = {
+		.enter			= exynos4_enter_idle,
+		.exit_latency		= 1,
+		.target_residency	= 10000,
+		.flags			= CPUIDLE_FLAG_TIME_VALID,
+		.name			= "IDLE",
+		.desc			= "ARM clock gating(WFI)",
+	},
+#ifdef CONFIG_EXYNOS4_LOWPWR_IDLE
+	[1] = {
+		.enter			= exynos4_enter_lowpower,
+		.exit_latency		= 300,
+		.target_residency	= 10000,
+		.flags			= CPUIDLE_FLAG_TIME_VALID,
+		.name			= "LOW_POWER",
+		.desc			= "ARM power down",
+	},
+#endif
+};
+
+static DEFINE_PER_CPU(struct cpuidle_device, exynos4_cpuidle_device);
+
+static struct cpuidle_driver exynos4_idle_driver = {
+	.name		= "exynos4_idle",
+	.owner		= THIS_MODULE,
+};
+
+static unsigned int cpu_core;
+static unsigned int old_div;
+static DEFINE_SPINLOCK(idle_lock);
+
+static int exynos4_enter_idle(struct cpuidle_device *dev,
+			      struct cpuidle_state *state)
+{
+	struct timeval before, after;
+	int idle_time;
+	int cpu;
+	unsigned int tmp;
+
+	local_irq_disable();
+	do_gettimeofday(&before);
+
+	if (use_clock_down == SW_CLK_DWN) {
+		/* USE SW Clock Down */
+		cpu = get_cpu();
+
+		spin_lock(&idle_lock);
+		cpu_core |= (1 << cpu);
+
+		if ((cpu_core == 0x3) || (cpu_online(1) == 0)) {
+			old_div = __raw_readl(EXYNOS4_CLKDIV_CPU);
+			tmp = old_div;
+			tmp |= ((0x7 << 28) | (0x7 << 0));
+			__raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
+
+			do {
+				tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU);
+			} while (tmp & 0x10000001);
+
+		}
+
+		spin_unlock(&idle_lock);
+
+		cpu_do_idle();
+
+		spin_lock(&idle_lock);
+
+		if ((cpu_core == 0x3) || (cpu_online(1) == 0)) {
+			__raw_writel(old_div, EXYNOS4_CLKDIV_CPU);
+
+			do {
+				tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU);
+			} while (tmp & 0x10000001);
+
+		}
+
+		cpu_core &= ~(1 << cpu);
+		spin_unlock(&idle_lock);
+
+		put_cpu();
+	} else
+		cpu_do_idle();
+
+	do_gettimeofday(&after);
+	local_irq_enable();
+	idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
+		    (after.tv_usec - before.tv_usec);
+
+	return idle_time;
+}
+
+static int exynos4_check_entermode(void)
+{
+	unsigned int ret;
+	unsigned int mask = (enable_mask & ENABLE_LOWPWRMASK);
+
+	if (!mask)
+		return 0;
+
+	if ((mask & ENABLE_LPA) && !exynos4_check_operation())
+		ret = S5P_CHECK_LPA;
+	else if (mask & ENABLE_AFTR)
+		ret = S5P_CHECK_DIDLE;
+	else
+		ret = 0;
+
+	return ret;
+}
+
+static int exynos4_enter_lowpower(struct cpuidle_device *dev,
+				  struct cpuidle_state *state)
+{
+	struct cpuidle_state *new_state = state;
+	unsigned int enter_mode;
+	unsigned int tmp;
+
+	/* This mode only can be entered when only Core0 is online */
+	if (num_online_cpus() != 1) {
+		BUG_ON(!dev->safe_state);
+		new_state = dev->safe_state;
+	}
+	dev->last_state = new_state;
+
+	if (!soc_is_exynos4210()) {
+		tmp = S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0;
+		__raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
+	}
+
+	if (new_state == &dev->states[0])
+		return exynos4_enter_idle(dev, new_state);
+
+	enter_mode = exynos4_check_entermode();
+	if (!enter_mode)
+		return exynos4_enter_idle(dev, new_state);
+	else if (enter_mode == S5P_CHECK_DIDLE)
+		return exynos4_enter_core0_aftr(dev, new_state);
+	else
+		return exynos4_enter_core0_lpa(dev, new_state);
+}
+
+static int exynos4_cpuidle_notifier_event(struct notifier_block *this,
+					  unsigned long event,
+					  void *ptr)
+{
+	switch (event) {
+	case PM_SUSPEND_PREPARE:
+		disable_hlt();
+		pr_debug("PM_SUSPEND_PREPARE for CPUIDLE\n");
+		return NOTIFY_OK;
+	case PM_POST_RESTORE:
+	case PM_POST_SUSPEND:
+		enable_hlt();
+		pr_debug("PM_POST_SUSPEND for CPUIDLE\n");
+		return NOTIFY_OK;
+	}
+	return NOTIFY_DONE;
+}
+
+static struct notifier_block exynos4_cpuidle_notifier = {
+	.notifier_call = exynos4_cpuidle_notifier_event,
+};
+
+#ifdef CONFIG_EXYNOS4_ENABLE_CLOCK_DOWN
+static void __init exynos4_core_down_clk(void)
+{
+	unsigned int tmp;
+
+	tmp = __raw_readl(EXYNOS4_PWR_CTRL1);
+
+	tmp &= ~(PWR_CTRL1_CORE2_DOWN_MASK | PWR_CTRL1_CORE1_DOWN_MASK);
+
+	/* set arm clock divider value on idle state */
+	tmp |= ((0x7 << PWR_CTRL1_CORE2_DOWN_RATIO) |
+		(0x7 << PWR_CTRL1_CORE1_DOWN_RATIO));
+
+	if (soc_is_exynos4212()) {
+	/* Set PWR_CTRL1 register to use clock down feature */
+		tmp |= (PWR_CTRL1_DIV2_DOWN_EN |
+			PWR_CTRL1_DIV1_DOWN_EN |
+			PWR_CTRL1_USE_CORE1_WFE |
+			PWR_CTRL1_USE_CORE0_WFE |
+			PWR_CTRL1_USE_CORE1_WFI |
+			PWR_CTRL1_USE_CORE0_WFI);
+	} else if (soc_is_exynos4412()) {
+		tmp |= (PWR_CTRL1_DIV2_DOWN_EN |
+			PWR_CTRL1_DIV1_DOWN_EN |
+			PWR_CTRL1_USE_CORE3_WFE |
+			PWR_CTRL1_USE_CORE2_WFE |
+			PWR_CTRL1_USE_CORE1_WFE |
+			PWR_CTRL1_USE_CORE0_WFE |
+			PWR_CTRL1_USE_CORE3_WFI |
+			PWR_CTRL1_USE_CORE2_WFI |
+			PWR_CTRL1_USE_CORE1_WFI |
+			PWR_CTRL1_USE_CORE0_WFI);
+	}
+
+	__raw_writel(tmp, EXYNOS4_PWR_CTRL1);
+
+	tmp = __raw_readl(EXYNOS4_PWR_CTRL2);
+
+	tmp &= ~(PWR_CTRL2_DUR_STANDBY2_MASK | PWR_CTRL2_DUR_STANDBY1_MASK |
+		PWR_CTRL2_CORE2_UP_MASK | PWR_CTRL2_CORE1_UP_MASK);
+
+	/* set duration value on middle wakeup step */
+	tmp |=  ((0x1 << PWR_CTRL2_DUR_STANDBY2) |
+		 (0x1 << PWR_CTRL2_DUR_STANDBY1));
+
+	/* set arm clock divier value on middle wakeup step */
+	tmp |= ((0x1 << PWR_CTRL2_CORE2_UP_RATIO) |
+		(0x1 << PWR_CTRL2_CORE1_UP_RATIO));
+
+	/* Set PWR_CTRL2 register to use step up for arm clock */
+	tmp |= (PWR_CTRL2_DIV2_UP_EN | PWR_CTRL2_DIV1_UP_EN);
+
+	__raw_writel(tmp, EXYNOS4_PWR_CTRL2);
+
+	printk(KERN_INFO "Exynos4 : ARM Clock down on idle mode is enabled\n");
+}
+#else
+#define exynos4_core_down_clk()	do { } while (0)
+#endif
+
+static int __init exynos4_init_cpuidle(void)
+{
+	int i, max_cpuidle_state, cpu_id, ret;
+	struct cpuidle_device *device;
+	struct platform_device *pdev;
+	struct resource *res;
+
+	if (soc_is_exynos4210())
+		use_clock_down = SW_CLK_DWN;
+	else
+		use_clock_down = HW_CLK_DWN;
+
+	/* Clock down feature can use only EXYNOS4212 */
+	if (use_clock_down == HW_CLK_DWN)
+		exynos4_core_down_clk();
+
+	ret = cpuidle_register_driver(&exynos4_idle_driver);
+
+	if(ret < 0){
+		printk(KERN_ERR "exynos4 idle register driver failed\n");
+		return ret;
+	}
+
+	for_each_cpu(cpu_id, cpu_online_mask) {
+		device = &per_cpu(exynos4_cpuidle_device, cpu_id);
+		device->cpu = cpu_id;
+
+		if (cpu_id == 0)
+			device->state_count = ARRAY_SIZE(exynos4_cpuidle_set);
+		else
+			device->state_count = 1;	/* Support IDLE only */
+
+		max_cpuidle_state = device->state_count;
+
+		for (i = 0; i < max_cpuidle_state; i++) {
+			memcpy(&device->states[i], &exynos4_cpuidle_set[i],
+					sizeof(struct cpuidle_state));
+		}
+
+		device->safe_state = &device->states[0];
+
+		if (cpuidle_register_device(device)) {
+			cpuidle_unregister_driver(&exynos4_idle_driver);
+			printk(KERN_ERR "CPUidle register device failed\n,");
+			return -EIO;
+		}
+	}
+
+	sdmmc_dev_num = ARRAY_SIZE(chk_sdhc_op);
+
+	for (i = 0; i < sdmmc_dev_num; i++) {
+
+		pdev = chk_sdhc_op[i].pdev;
+
+		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+		if (!res) {
+			printk(KERN_ERR "failed to get iomem region\n");
+			return -EINVAL;
+		}
+
+		chk_sdhc_op[i].base = ioremap(res->start, resource_size(res));
+
+		if (!chk_sdhc_op[i].base) {
+			printk(KERN_ERR "failed to map io region\n");
+			return -EINVAL;
+		}
+	}
+
+#if defined(CONFIG_USB_S3C_OTGD) && !defined(CONFIG_USB_EXYNOS_SWITCH)
+	pdev = chk_usbotg_op.pdev;
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		printk(KERN_ERR "failed to get iomem region\n");
+		return -EINVAL;
+	}
+
+	chk_usbotg_op.base = ioremap(res->start, resource_size(res));
+
+	if (!chk_usbotg_op.base) {
+		printk(KERN_ERR "failed to map io region\n");
+		return -EINVAL;
+	}
+#endif
+	register_pm_notifier(&exynos4_cpuidle_notifier);
+	sys_pwr_conf_addr = (unsigned long)S5P_CENTRAL_SEQ_CONFIGURATION;
+
+	/* Save register value for SCU */
+	scu_save[0] = __raw_readl(S5P_VA_SCU + 0x30);
+	scu_save[1] = __raw_readl(S5P_VA_SCU + 0x0);
+
+	/* Save register value for L2X0 */
+	l2x0_save[0] = __raw_readl(S5P_VA_L2CC + 0x108);
+	l2x0_save[1] = __raw_readl(S5P_VA_L2CC + 0x10C);
+	l2x0_save[2] = __raw_readl(S5P_VA_L2CC + 0xF60);
+
+	flush_cache_all();
+	outer_clean_range(virt_to_phys(l2x0_save), ARRAY_SIZE(l2x0_save));
+	outer_clean_range(virt_to_phys(scu_save), ARRAY_SIZE(scu_save));
+
+	return 0;
+}
+device_initcall(exynos4_init_cpuidle);
diff --git a/arch/arm/mach-exynos/cpuidle-exynos5.c b/arch/arm/mach-exynos/cpuidle-exynos5.c
new file mode 100644
index 0000000..fbe063d
--- /dev/null
+++ b/arch/arm/mach-exynos/cpuidle-exynos5.c
@@ -0,0 +1,674 @@
+/* linux/arch/arm/mach-exynos/cpuidle-exynos5.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/cpuidle.h>
+#include <linux/io.h>
+#include <linux/suspend.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+
+#include <asm/proc-fns.h>
+#include <asm/tlbflush.h>
+#include <asm/cacheflush.h>
+
+#include <plat/pm.h>
+#include <plat/gpio-cfg.h>
+#include <plat/gpio-core.h>
+#include <plat/regs-otg.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+
+#include <mach/regs-pmu5.h>
+#include <mach/pm-core.h>
+#include <mach/pmu.h>
+#include <mach/regs-clock.h>
+#include <mach/smc.h>
+#include <mach/clock-domain.h>
+#include <mach/regs-usb-phy.h>
+
+#ifdef CONFIG_ARM_TRUSTZONE
+#define REG_DIRECTGO_ADDR       (S5P_VA_SYSRAM_NS + 0x24)
+#define REG_DIRECTGO_FLAG       (S5P_VA_SYSRAM_NS + 0x20)
+#else
+#define REG_DIRECTGO_ADDR	(S5P_VA_SYSRAM + 0x24)
+#define REG_DIRECTGO_FLAG	(S5P_VA_SYSRAM + 0x20)
+#endif
+
+extern unsigned long sys_pwr_conf_addr;
+
+static int exynos5_enter_idle(struct cpuidle_device *dev,
+			      struct cpuidle_state *state);
+
+static int __maybe_unused exynos5_enter_lowpower(struct cpuidle_device *dev,
+						 struct cpuidle_state *state);
+
+struct check_reg_lpa {
+	void __iomem	*check_reg;
+	unsigned int	check_bit;
+};
+
+/*
+ * List of check power domain list for LPA mode
+ * These register are have to power off to enter LPA mode
+ */
+static struct check_reg_lpa exynos5_power_domain[] = {
+	{.check_reg = EXYNOS5_GSCL_STATUS,	.check_bit = 0x7},
+	{.check_reg = EXYNOS5_G3D_STATUS,	.check_bit = 0x7},
+};
+
+/*
+ * List of check clock gating list for LPA mode
+ * If clock of list is not gated, system can not enter LPA mode.
+ */
+static struct check_reg_lpa exynos5_clock_gating[] = {
+	{.check_reg = EXYNOS5_CLKSRC_MASK_DISP1_0,	.check_bit = 0x00000001},
+	{.check_reg = EXYNOS5_CLKGATE_IP_DISP1,		.check_bit = 0x00000010},
+	{.check_reg = EXYNOS5_CLKGATE_IP_MFC,		.check_bit = 0x00000001},
+	{.check_reg = EXYNOS5_CLKGATE_IP_GEN,		.check_bit = 0x00004016},
+	{.check_reg = EXYNOS5_CLKGATE_IP_FSYS,		.check_bit = 0x00000002},
+	{.check_reg = EXYNOS5_CLKGATE_IP_PERIC,		.check_bit = 0x00377FC0},
+};
+
+enum hc_type {
+	HC_SDHC,
+	HC_MSHC,
+};
+
+struct check_device_op {
+	void __iomem		*base;
+	struct platform_device	*pdev;
+	enum hc_type		type;
+};
+
+static struct check_device_op chk_sdhc_op[] = {
+#if defined(CONFIG_EXYNOS4_DEV_DWMCI)
+	{.base = 0, .pdev = &exynos_device_dwmci, .type = HC_MSHC},
+#endif
+#if defined(CONFIG_S3C_DEV_HSMMC)
+	{.base = 0, .pdev = &s3c_device_hsmmc0, .type = HC_SDHC},
+#endif
+#if defined(CONFIG_S3C_DEV_HSMMC1)
+	{.base = 0, .pdev = &s3c_device_hsmmc1, .type = HC_SDHC},
+#endif
+#if defined(CONFIG_S3C_DEV_HSMMC2)
+	{.base = 0, .pdev = &s3c_device_hsmmc2, .type = HC_SDHC},
+#endif
+#if defined(CONFIG_S3C_DEV_HSMMC3)
+	{.base = 0, .pdev = &s3c_device_hsmmc3, .type = HC_SDHC},
+#endif
+};
+
+static struct check_device_op chk_sdhc_op_exynos5250_rev1[] = {
+#if defined(CONFIG_EXYNOS4_DEV_DWMCI)
+	{.base = 0, .pdev = &exynos_device_dwmci0, .type = HC_MSHC},
+	{.base = 0, .pdev = &exynos_device_dwmci1, .type = HC_MSHC},
+	{.base = 0, .pdev = &exynos_device_dwmci2, .type = HC_MSHC},
+	{.base = 0, .pdev = &exynos_device_dwmci3, .type = HC_MSHC},
+#endif
+};
+
+#define S3C_HSMMC_PRNSTS	(0x24)
+#define S3C_HSMMC_CLKCON	(0x2c)
+#define S3C_HSMMC_CMD_INHIBIT	0x00000001
+#define S3C_HSMMC_DATA_INHIBIT	0x00000002
+#define S3C_HSMMC_CLOCK_CARD_EN	0x0004
+
+#define MSHCI_CLKENA	(0x10)  /* Clock enable */
+#define MSHCI_STATUS	(0x48)  /* Status */
+#define MSHCI_DATA_BUSY	(0x1<<9)
+#define MSHCI_DATA_STAT_BUSY	(0x1<<10)
+#define MSHCI_ENCLK	(0x1)
+
+static int sdmmc_dev_num;
+/* If SD/MMC interface is working: return = 1 or not 0 */
+static int check_sdmmc_op(unsigned int ch)
+{
+	unsigned int reg1, reg2;
+	void __iomem *base_addr;
+
+	if (unlikely(ch >= sdmmc_dev_num)) {
+		printk(KERN_ERR "Invalid ch[%d] for SD/MMC\n", ch);
+		return 0;
+	}
+
+	if (soc_is_exynos5250() && (samsung_rev() >= EXYNOS5250_REV_1_0)) {
+		if (chk_sdhc_op_exynos5250_rev1[ch].type == HC_MSHC) {
+			base_addr = chk_sdhc_op_exynos5250_rev1[ch].base;
+			/* Check STATUS [9] for data busy */
+			reg1 = readl(base_addr + MSHCI_STATUS);
+			return (reg1 & (MSHCI_DATA_BUSY)) ||
+			       (reg1 & (MSHCI_DATA_STAT_BUSY));
+		}
+	} else {
+		if (chk_sdhc_op[ch].type == HC_SDHC) {
+			base_addr = chk_sdhc_op[ch].base;
+			/* Check CLKCON [2]: ENSDCLK */
+			reg2 = readl(base_addr + S3C_HSMMC_CLKCON);
+			return !!(reg2 & (S3C_HSMMC_CLOCK_CARD_EN));
+		} else if (chk_sdhc_op[ch].type == HC_MSHC) {
+			base_addr = chk_sdhc_op[ch].base;
+			/* Check STATUS [9] for data busy */
+			reg1 = readl(base_addr + MSHCI_STATUS);
+			return (reg1 & (MSHCI_DATA_BUSY)) ||
+			       (reg1 & (MSHCI_DATA_STAT_BUSY));
+		}
+	}
+	/* should not be here */
+	return 0;
+}
+
+/* Check all sdmmc controller */
+static int loop_sdmmc_check(void)
+{
+	unsigned int iter;
+
+	for (iter = 0; iter < sdmmc_dev_num; iter++) {
+		if (check_sdmmc_op(iter)) {
+			printk(KERN_DEBUG "SDMMC [%d] working\n", iter);
+			return 1;
+		}
+	}
+	return 0;
+}
+
+static int exynos5_check_reg_status(struct check_reg_lpa *reg_list,
+				    unsigned int list_cnt)
+{
+	unsigned int i;
+	unsigned int tmp;
+
+	for (i = 0; i < list_cnt; i++) {
+		tmp = __raw_readl(reg_list[i].check_reg);
+		if (tmp & reg_list[i].check_bit)
+			return -EBUSY;
+	}
+
+	return 0;
+}
+
+static int exynos5_uart_fifo_check(void)
+{
+	unsigned int ret;
+	unsigned int check_val;
+
+	ret = 0;
+
+	/* Check UART for console is empty */
+	check_val = __raw_readl(S5P_VA_UART(CONFIG_S3C_LOWLEVEL_UART_PORT) +
+				0x18);
+
+	ret = ((check_val >> 16) & 0xff);
+
+	return ret;
+}
+
+static struct cpuidle_state exynos5_cpuidle_set[] = {
+	[0] = {
+		.enter			= exynos5_enter_idle,
+		.exit_latency		= 1,
+		.target_residency	= 10000,
+		.flags			= CPUIDLE_FLAG_TIME_VALID,
+		.name			= "IDLE",
+		.desc			= "ARM clock gating(WFI)",
+	},
+#ifdef CONFIG_EXYNOS5_LOWPWR_IDLE
+	[1] = {
+		.enter			= exynos5_enter_lowpower,
+		.exit_latency		= 300,
+		.target_residency	= 10000,
+		.flags			= CPUIDLE_FLAG_TIME_VALID,
+		.name			= "LOW_POWER",
+		.desc			= "ARM power down",
+	},
+#endif
+};
+
+static DEFINE_PER_CPU(struct cpuidle_device, exynos5_cpuidle_device);
+
+static struct cpuidle_driver exynos5_idle_driver = {
+	.name		= "exynos5_idle",
+	.owner		= THIS_MODULE,
+};
+
+/*
+ * To keep value of gpio on power down mode
+ * set Power down register of gpio
+ */
+static void exynos5_gpio_set_pd_reg(void)
+{
+	struct s3c_gpio_chip *target_chip;
+	unsigned int gpio_nr;
+	unsigned int tmp;
+
+	for (gpio_nr = 0; gpio_nr < EXYNOS5_GPIO_END; gpio_nr++) {
+		target_chip = s3c_gpiolib_getchip(gpio_nr);
+
+		if (!target_chip)
+			continue;
+
+		if (!target_chip->pm)
+			continue;
+
+		/* Keep the previous state in LPA mode */
+		s5p_gpio_set_pd_cfg(gpio_nr, 0x3);
+
+		/* Pull up-down state in LPA mode is same as normal */
+		tmp = s3c_gpio_getpull(gpio_nr);
+		s5p_gpio_set_pd_pull(gpio_nr, tmp);
+	}
+}
+
+static int exynos5_enter_idle(struct cpuidle_device *dev,
+			      struct cpuidle_state *state)
+{
+	struct timeval before, after;
+	int idle_time;
+
+	local_irq_disable();
+	do_gettimeofday(&before);
+
+	cpu_do_idle();
+
+	do_gettimeofday(&after);
+	local_irq_enable();
+	idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
+		    (after.tv_usec - before.tv_usec);
+
+	return idle_time;
+}
+
+static void exynos5_set_wakeupmask(void)
+{
+	__raw_writel(0x0000ff3e, EXYNOS5_WAKEUP_MASK);
+}
+
+static inline void vfp_enable(void *unused)
+{
+	u32 access = get_copro_access();
+
+	/*
+	 * Enable full access to VFP (cp10 and cp11)
+	 */
+	set_copro_access(access | CPACC_FULL(10) | CPACC_FULL(11));
+}
+
+static struct sleep_save exynos5_lpa_save[] = {
+	/* CMU side */
+	SAVE_ITEM(EXYNOS5_CLKSRC_MASK_TOP),
+	SAVE_ITEM(EXYNOS5_CLKSRC_MASK_GSCL),
+	SAVE_ITEM(EXYNOS5_CLKSRC_MASK_DISP1_0),
+	SAVE_ITEM(EXYNOS5_CLKSRC_MASK_MAUDIO),
+	SAVE_ITEM(EXYNOS5_CLKSRC_MASK_FSYS),
+	SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC0),
+	SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC1),
+	SAVE_ITEM(EXYNOS5_CLKSRC_TOP3),
+};
+
+static struct sleep_save exynos5_set_clksrc[] = {
+	{ .reg = EXYNOS5_CLKSRC_MASK_TOP		, .val = 0xffffffff, },
+	{ .reg = EXYNOS5_CLKSRC_MASK_GSCL		, .val = 0xffffffff, },
+	{ .reg = EXYNOS5_CLKSRC_MASK_DISP1_0		, .val = 0xffffffff, },
+	{ .reg = EXYNOS5_CLKSRC_MASK_MAUDIO		, .val = 0xffffffff, },
+	{ .reg = EXYNOS5_CLKSRC_MASK_FSYS		, .val = 0xffffffff, },
+	{ .reg = EXYNOS5_CLKSRC_MASK_PERIC0		, .val = 0xffffffff, },
+	{ .reg = EXYNOS5_CLKSRC_MASK_PERIC1		, .val = 0xffffffff, },
+};
+
+static int exynos5_enter_core0_lpa(struct cpuidle_device *dev,
+				   struct cpuidle_state *state)
+{
+	struct timeval before, after;
+	int idle_time;
+
+	unsigned long tmp;
+
+	s3c_pm_do_save(exynos5_lpa_save, ARRAY_SIZE(exynos5_lpa_save));
+	/*
+	 * Before enter central sequence mode, clock src register have to set
+	 */
+	s3c_pm_do_restore_core(exynos5_set_clksrc,
+			       ARRAY_SIZE(exynos5_set_clksrc));
+
+	local_irq_disable();
+
+	do_gettimeofday(&before);
+
+	/*
+	 * Unmasking all wakeup source.
+	 */
+	__raw_writel(0x0, S5P_WAKEUP_MASK);
+
+	/* Configure GPIO Power down control register */
+	exynos5_gpio_set_pd_reg();
+
+	/* ensure at least INFORM0 has the resume address */
+	__raw_writel(virt_to_phys(exynos5_idle_resume), REG_DIRECTGO_ADDR);
+	__raw_writel(0xfcba0d10, REG_DIRECTGO_FLAG);
+
+	__raw_writel(S5P_CHECK_LPA, EXYNOS5_INFORM1);
+
+	exynos5_sys_powerdown_conf(SYS_LPA);
+
+	/* Disable USE_RETENTION of JPEG_MEM_OPTION */
+	tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
+	tmp |= EXYNOS5_OPTION_USE_RETENTION;
+	__raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
+
+	do {
+		/* Waiting for flushing UART fifo */
+	} while (exynos5_uart_fifo_check());
+
+	/*
+	 * GPS can not turn off.
+	 */
+	if (samsung_rev() < EXYNOS5250_REV_1_0)
+		__raw_writel(0x10000, EXYNOS5_GPS_LPI);
+
+	if (exynos5_enter_lp(0, PLAT_PHYS_OFFSET - PAGE_OFFSET) == 0) {
+		/*
+		 * Clear Central Sequence Register in exiting early wakeup
+		 */
+		tmp = __raw_readl(EXYNOS5_CENTRAL_SEQ_CONFIGURATION);
+		tmp |= (EXYNOS5_CENTRAL_LOWPWR_CFG);
+		__raw_writel(tmp, EXYNOS5_CENTRAL_SEQ_CONFIGURATION);
+
+		goto early_wakeup;
+	}
+
+	flush_tlb_all();
+
+	cpu_init();
+
+	vfp_enable(NULL);
+
+	/* For release retention */
+	__raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_MAU_OPTION);
+	__raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_GPIO_OPTION);
+	__raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_UART_OPTION);
+	__raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_MMCA_OPTION);
+	__raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_MMCB_OPTION);
+	__raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_EBIA_OPTION);
+	__raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_EBIB_OPTION);
+	__raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_SPI_OPTION);
+	__raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_OPTION);
+
+early_wakeup:
+	s3c_pm_do_restore_core(exynos5_lpa_save,
+			       ARRAY_SIZE(exynos5_lpa_save));
+
+	/* Clear wakeup state register */
+	__raw_writel(0x0, EXYNOS5_WAKEUP_STAT);
+
+	__raw_writel(0x0, EXYNOS5_WAKEUP_MASK);
+
+	do_gettimeofday(&after);
+
+	local_irq_enable();
+
+	idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
+		    (after.tv_usec - before.tv_usec);
+
+	return idle_time;
+}
+
+static int exynos5_enter_core0_aftr(struct cpuidle_device *dev,
+				    struct cpuidle_state *state)
+{
+	struct timeval before, after;
+	int idle_time;
+	unsigned long tmp;
+
+	local_irq_disable();
+	do_gettimeofday(&before);
+
+	exynos5_set_wakeupmask();
+
+	__raw_writel(virt_to_phys(exynos5_idle_resume), REG_DIRECTGO_ADDR);
+	__raw_writel(0xfcba0d10, REG_DIRECTGO_FLAG);
+
+	/* Set value of power down register for aftr mode */
+	exynos5_sys_powerdown_conf(SYS_AFTR);
+
+	if (exynos5_enter_lp(0, PLAT_PHYS_OFFSET - PAGE_OFFSET) == 0) {
+		/*
+		 * Clear Central Sequence Register in exiting early wakeup
+		 */
+		tmp = __raw_readl(EXYNOS5_CENTRAL_SEQ_CONFIGURATION);
+		tmp |= EXYNOS5_CENTRAL_LOWPWR_CFG;
+		__raw_writel(tmp, EXYNOS5_CENTRAL_SEQ_CONFIGURATION);
+
+		goto early_wakeup;
+	}
+
+	flush_tlb_all();
+
+	cpu_init();
+
+	vfp_enable(NULL);
+
+early_wakeup:
+	/* Clear wakeup state register */
+	__raw_writel(0x0, EXYNOS5_WAKEUP_STAT);
+
+	do_gettimeofday(&after);
+
+	local_irq_enable();
+	idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
+		    (after.tv_usec - before.tv_usec);
+
+	return idle_time;
+}
+
+static int __maybe_unused exynos5_check_enter_mode(void)
+{
+	/* Check power domain */
+	if (exynos5_check_reg_status(exynos5_power_domain,
+				    ARRAY_SIZE(exynos5_power_domain)))
+		return S5P_CHECK_DIDLE;
+
+	/* Check clock gating */
+	if (exynos5_check_reg_status(exynos5_clock_gating,
+				    ARRAY_SIZE(exynos5_clock_gating)))
+		return S5P_CHECK_DIDLE;
+
+	if (clock_domain_enabled(LPA_DOMAIN))
+		return S5P_CHECK_DIDLE;
+
+	if (loop_sdmmc_check())
+		return S5P_CHECK_DIDLE;
+
+        if (exynos_check_usb_op())
+                return S5P_CHECK_DIDLE;
+
+	return S5P_CHECK_LPA;
+}
+
+static int __maybe_unused exynos5_enter_lowpower(struct cpuidle_device *dev,
+						 struct cpuidle_state *state)
+{
+	struct cpuidle_state *new_state = state;
+	unsigned int tmp;
+
+	/* This mode only can be entered when only Core0 is online */
+	if (num_online_cpus() != 1) {
+		BUG_ON(!dev->safe_state);
+		new_state = dev->safe_state;
+	}
+	dev->last_state = new_state;
+
+	if (new_state == &dev->states[0])
+		return exynos5_enter_idle(dev, new_state);
+
+	tmp = __raw_readl(EXYNOS5_CENTRAL_SEQ_OPTION);
+	tmp = (EXYNOS5_USE_STANDBYWFI_ARM_CORE0 |
+		EXYNOS5_USE_STANDBYWFE_ARM_CORE0);
+	__raw_writel(tmp, EXYNOS5_CENTRAL_SEQ_OPTION);
+
+	if (exynos5_check_enter_mode() == S5P_CHECK_DIDLE)
+		return exynos5_enter_core0_aftr(dev, new_state);
+	else
+		return exynos5_enter_core0_aftr(dev, new_state);
+		//return exynos5_enter_core0_lpa(dev, new_state);
+}
+
+static int exynos5_cpuidle_notifier_event(struct notifier_block *this,
+					  unsigned long event,
+					  void *ptr)
+{
+	switch (event) {
+	case PM_SUSPEND_PREPARE:
+		disable_hlt();
+		pr_debug("PM_SUSPEND_PREPARE for CPUIDLE\n");
+		return NOTIFY_OK;
+	case PM_POST_RESTORE:
+	case PM_POST_SUSPEND:
+		enable_hlt();
+		pr_debug("PM_POST_SUSPEND for CPUIDLE\n");
+		return NOTIFY_OK;
+	}
+	return NOTIFY_DONE;
+}
+
+static struct notifier_block exynos5_cpuidle_notifier = {
+	.notifier_call = exynos5_cpuidle_notifier_event,
+};
+
+#ifdef CONFIG_EXYNOS5_ENABLE_CLOCK_DOWN
+static void __init exynos5_core_down_clk(void)
+{
+	unsigned int tmp;
+
+	tmp = __raw_readl(EXYNOS5_PWR_CTRL1);
+
+	tmp &= ~(PWR_CTRL1_CORE2_DOWN_MASK | PWR_CTRL1_CORE1_DOWN_MASK);
+
+	/* set arm clock divider value on idle state */
+	tmp |= ((0x7 << PWR_CTRL1_CORE2_DOWN_RATIO) |
+		(0x7 << PWR_CTRL1_CORE1_DOWN_RATIO));
+
+	tmp |= (PWR_CTRL1_DIV2_DOWN_EN |
+		PWR_CTRL1_DIV1_DOWN_EN |
+		PWR_CTRL1_USE_CORE1_WFE |
+		PWR_CTRL1_USE_CORE0_WFE |
+		PWR_CTRL1_USE_CORE1_WFI |
+		PWR_CTRL1_USE_CORE0_WFI);
+
+	__raw_writel(tmp, EXYNOS5_PWR_CTRL1);
+
+	tmp = __raw_readl(EXYNOS5_PWR_CTRL2);
+
+	tmp &= ~(PWR_CTRL2_DUR_STANDBY2_MASK | PWR_CTRL2_DUR_STANDBY1_MASK |
+		PWR_CTRL2_CORE2_UP_MASK | PWR_CTRL2_CORE1_UP_MASK);
+
+	/* set duration value on middle wakeup step */
+	tmp |=  ((0x1 << PWR_CTRL2_DUR_STANDBY2) |
+		 (0x1 << PWR_CTRL2_DUR_STANDBY1));
+
+	/* set arm clock divier value on middle wakeup step */
+	tmp |= ((0x1 << PWR_CTRL2_CORE2_UP_RATIO) |
+		(0x1 << PWR_CTRL2_CORE1_UP_RATIO));
+
+	/* Set PWR_CTRL2 register to use step up for arm clock */
+	tmp |= (PWR_CTRL2_DIV2_UP_EN | PWR_CTRL2_DIV1_UP_EN);
+
+	__raw_writel(tmp, EXYNOS5_PWR_CTRL2);
+	printk(KERN_INFO "Exynos5 : ARM Clock down on idle mode is enabled\n");
+}
+#else
+#define exynos5_core_down_clk()	do { } while (0)
+#endif
+
+static int __init exynos5_init_cpuidle(void)
+{
+	int i, max_cpuidle_state, cpu_id, ret;
+	struct cpuidle_device *device;
+	struct platform_device *pdev;
+	struct resource *res;
+	void __iomem *base;
+
+	if (samsung_rev() >= EXYNOS5250_REV_1_0)
+		exynos4_reset_assert_ctrl(1);
+
+	exynos5_core_down_clk();
+
+	ret = cpuidle_register_driver(&exynos5_idle_driver);
+	
+	if(ret < 0){
+		printk(KERN_ERR "exynos5 idle register driver failed\n");
+		return ret;
+	}
+
+
+	for_each_cpu(cpu_id, cpu_online_mask) {
+		device = &per_cpu(exynos5_cpuidle_device, cpu_id);
+		device->cpu = cpu_id;
+
+		if (cpu_id == 0)
+			device->state_count = ARRAY_SIZE(exynos5_cpuidle_set);
+		else
+			device->state_count = 1;	/* Support IDLE only */
+
+		max_cpuidle_state = device->state_count;
+
+		for (i = 0; i < max_cpuidle_state; i++) {
+			memcpy(&device->states[i], &exynos5_cpuidle_set[i],
+					sizeof(struct cpuidle_state));
+		}
+
+		device->safe_state = &device->states[0];
+
+		if (cpuidle_register_device(device)) {
+			cpuidle_unregister_driver(&exynos5_idle_driver);
+			printk(KERN_ERR "CPUidle register device failed\n,");
+			return -EIO;
+		}
+	}
+
+	if (soc_is_exynos5250() && (samsung_rev() >= EXYNOS5250_REV_1_0))
+		sdmmc_dev_num = ARRAY_SIZE(chk_sdhc_op_exynos5250_rev1);
+	else
+		sdmmc_dev_num = ARRAY_SIZE(chk_sdhc_op);
+
+	for (i = 0; i < sdmmc_dev_num; i++) {
+
+		if (soc_is_exynos5250() && (samsung_rev() >= EXYNOS5250_REV_1_0))
+			pdev = chk_sdhc_op_exynos5250_rev1[i].pdev;
+		else
+			pdev = chk_sdhc_op[i].pdev;
+
+		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+		if (!res) {
+			printk(KERN_ERR "failed to get iomem region\n");
+			return -EINVAL;
+		}
+
+		if (soc_is_exynos5250() && (samsung_rev() >= EXYNOS5250_REV_1_0)) {
+			chk_sdhc_op_exynos5250_rev1[i].base = ioremap(res->start, resource_size(res));
+			base = chk_sdhc_op_exynos5250_rev1[i].base;
+		} else {
+			chk_sdhc_op[i].base = ioremap(res->start, resource_size(res));
+			base = chk_sdhc_op[i].base;
+		}
+
+
+		if (!base) {
+			printk(KERN_ERR "failed to map io region\n");
+			return -EINVAL;
+		}
+	}
+
+	register_pm_notifier(&exynos5_cpuidle_notifier);
+	sys_pwr_conf_addr = (unsigned long)EXYNOS5_CENTRAL_SEQ_CONFIGURATION;
+
+	return 0;
+}
+device_initcall(exynos5_init_cpuidle);
diff --git a/arch/arm/mach-exynos/dev-ahci-exynos5.c b/arch/arm/mach-exynos/dev-ahci-exynos5.c
new file mode 100644
index 0000000..7163446
--- /dev/null
+++ b/arch/arm/mach-exynos/dev-ahci-exynos5.c
@@ -0,0 +1,486 @@
+/* linux/arch/arm/mach-exynos/dev-ahci-exynos5.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ * Author: Srikanth TS <ts.srikanth@samsung.com> for Samsung
+ *
+ * EXYNOS5 - AHCI SATA3.0 support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/ahci_platform.h>
+
+#include <plat/cpu.h>
+
+#include <mach/irqs.h>
+#include <mach/map.h>
+#include <mach/regs-pmu.h>
+#include <mach/regs-pmu5.h>
+#include <mach/map-exynos5.h>
+
+#define SATA_TIME_LIMIT			10000
+#define PMU_BASE_ADDRS			0x10040000
+#define PMU_SATA_PHY_CTRL		0x724
+#define SATA_PHY_I2C_SLAVE_ADDRS	0x70
+
+#define SATA_RESET			0x4
+#define RESET_CMN_RST_N			(1 << 1)
+#define LINK_RESET			0xF0000
+
+#define SATA_MODE0			0x10
+
+#define SATA_CTRL0			0x14
+#define CTRL0_P0_PHY_CALIBRATED_SEL	(1 << 9)
+#define CTRL0_P0_PHY_CALIBRATED		(1 << 8)
+
+#define SATA_STAT0			0x18
+
+#define SATA_TBD			0x9C
+#define SATA_PHSATA_CTRLM		0xE0
+#define PHCTRLM_REF_RATE		(1 << 1)
+#define PHCTRLM_HIGH_SPEED		(1 << 0)
+
+#define SATA_PHSATA_CTRL0		0xE4
+
+#define SATA_PHSATA_STATM		0xF0
+#define PHSTATM_PLL_LOCKED		(1 << 0)
+
+#define SATA_PHSATA_STAT0		0xF4
+
+/********************** I2C**************/
+#define SATA_I2C_PHY_ADDR		0x70
+#define SATA_I2C_CON			0x00
+#define SATA_I2C_STAT			0x04
+#define SATA_I2C_ADDR			0x08
+#define SATA_I2C_DS			0x0C
+#define SATA_I2C_LC			0x10
+
+/* I2CCON reg */
+#define CON_ACKEN			(1 << 7)
+#define CON_CLK512			(1 << 6)
+#define CON_CLK16			(~CON_CLK512)
+#define CON_INTEN			(1 << 5)
+#define CON_INTPND			(1 << 4)
+#define CON_TXCLK_PS			(0xF)
+
+/* I2CSTAT reg */
+#define STAT_MSTR			(0x2 << 6)
+#define STAT_MSTT			(0x3 << 6)
+#define STAT_BSYST			(1 << 5)
+#define STAT_RTEN			(1 << 4)
+#define STAT_LAST			(1 << 0)
+
+#define LC_FLTR_EN			(1 << 2)
+
+#define SATA_PHY_CON_RESET		0xF003F
+
+#define HOST_PORTS_IMPL			0xC
+#define SCLK_SATA_FREQ			(66 * MHZ)
+
+enum {
+	GEN1 = 0,
+	GEN2 = 1,
+	GEN3 = 2,
+};
+
+static void __iomem *phy_i2c_base, *phy_ctrl;
+u32 time_limit_cnt;
+
+static bool sata_is_reg(void __iomem *base, u32 reg, u32 checkbit, u32 Status)
+{
+	if ((__raw_readl(base + reg) & checkbit) == Status)
+		return true;
+	else
+		return false;
+}
+
+static bool wait_for_reg_status(void __iomem *base, u32 reg, u32 checkbit,
+		u32 Status)
+{
+	time_limit_cnt = 0;
+	while (!sata_is_reg(base, reg, checkbit, Status)) {
+		if (time_limit_cnt == SATA_TIME_LIMIT) {
+			printk(KERN_ERR " Register Status wait FAIL\n");
+			return false;
+		}
+		udelay(1000);
+		time_limit_cnt++;
+	}
+	return true;
+}
+
+
+static void sata_set_gen(u8 gen)
+{
+	__raw_writel(gen, phy_ctrl + SATA_MODE0);
+}
+
+/* Address :I2C Address */
+static void sata_i2c_write_addrs(u8 data)
+{
+	__raw_writeb((data & 0xFE), phy_i2c_base + SATA_I2C_DS);
+}
+
+static void sata_i2c_write_data(u8 data)
+{
+	__raw_writeb((data), phy_i2c_base + SATA_I2C_DS);
+}
+
+static void sata_i2c_start(void)
+{
+	u32 val;
+	val = __raw_readl(phy_i2c_base + SATA_I2C_STAT);
+	val |= STAT_BSYST;
+	__raw_writel(val, phy_i2c_base + SATA_I2C_STAT);
+}
+
+static void sata_i2c_stop(void)
+{
+	u32 val;
+	val = __raw_readl(phy_i2c_base + SATA_I2C_STAT);
+	val &= ~STAT_BSYST;
+	__raw_writel(val, phy_i2c_base + SATA_I2C_STAT);
+}
+
+static bool sata_i2c_get_int_status(void)
+{
+	if ((__raw_readl(phy_i2c_base + SATA_I2C_CON)) & CON_INTPND)
+		return true;
+	else
+		return false;
+}
+
+static bool sata_i2c_is_tx_ack(void)
+{
+	if ((__raw_readl(phy_i2c_base + SATA_I2C_STAT)) & STAT_LAST)
+		return false;
+	else
+		return true;
+}
+
+static bool sata_i2c_is_bus_ready(void)
+{
+	if ((__raw_readl(phy_i2c_base + SATA_I2C_STAT)) & STAT_BSYST)
+		return false;
+	else
+		return true;
+}
+
+static bool sata_i2c_wait_for_busready(u32 time_out)
+{
+	while (--time_out) {
+		if (sata_i2c_is_bus_ready())
+			return true;
+		udelay(100);
+	}
+	printk(KERN_ERR "SATA I2C wait fail for bus ready...\n");
+	return false;
+}
+
+static bool sata_i2c_wait_for_tx_ack(u32 time_out)
+{
+	while (--time_out) {
+		if (sata_i2c_get_int_status()) {
+			if (sata_i2c_is_tx_ack())
+				return true;
+		}
+		udelay(100);
+	}
+	return false;
+}
+
+static void sata_i2c_clear_int_status(void)
+{
+	u32 val;
+	val = __raw_readl(phy_i2c_base + SATA_I2C_CON);
+	val &= ~CON_INTPND;
+	__raw_writel(val, phy_i2c_base + SATA_I2C_CON);
+}
+
+
+static void sata_i2c_set_ack_gen(bool enable)
+{
+	u32 val;
+	if (enable) {
+		val = (__raw_readl(phy_i2c_base + SATA_I2C_CON)) | CON_ACKEN;
+		__raw_writel(val, phy_i2c_base + SATA_I2C_CON);
+	} else {
+		val = __raw_readl(phy_i2c_base + SATA_I2C_CON);
+		val &= ~CON_ACKEN;
+		__raw_writel(val, phy_i2c_base + SATA_I2C_CON);
+	}
+
+}
+
+static void sata_i2c_set_master_tx(void)
+{
+	u32 val;
+	/* Disable I2C */
+	val = __raw_readl(phy_i2c_base + SATA_I2C_STAT);
+	val &= ~STAT_RTEN;
+	__raw_writel(val, phy_i2c_base + SATA_I2C_STAT);
+	/* Clear Mode */
+	val = __raw_readl(phy_i2c_base + SATA_I2C_STAT);
+	val &= ~STAT_MSTT;
+	__raw_writel(val, phy_i2c_base + SATA_I2C_STAT);
+
+	sata_i2c_clear_int_status();
+	/* interrupt disable */
+	val = __raw_readl(phy_i2c_base + SATA_I2C_CON);
+	val &= ~CON_INTEN;
+	__raw_writel(val, phy_i2c_base + SATA_I2C_CON);
+
+	/* Master, Send mode */
+	val = __raw_readl(phy_i2c_base + SATA_I2C_STAT);
+	val |=	STAT_MSTT;
+	__raw_writel(val, phy_i2c_base + SATA_I2C_STAT);
+
+	/* interrupt enable */
+	val = __raw_readl(phy_i2c_base + SATA_I2C_CON);
+	val |=	CON_INTEN;
+	__raw_writel(val, phy_i2c_base + SATA_I2C_CON);
+
+	/* Enable I2C */
+	val = __raw_readl(phy_i2c_base + SATA_I2C_STAT);
+	val |= STAT_RTEN;
+	__raw_writel(val, phy_i2c_base + SATA_I2C_STAT);
+}
+
+static void sata_i2c_init(void)
+{
+	u32 val;
+
+	val = __raw_readl(phy_i2c_base + SATA_I2C_CON);
+	val &= CON_CLK16;
+	__raw_writel(val, phy_i2c_base + SATA_I2C_CON);
+
+	val = __raw_readl(phy_i2c_base + SATA_I2C_CON);
+	val &= ~(CON_TXCLK_PS);
+	__raw_writel(val, phy_i2c_base + SATA_I2C_CON);
+
+	val = __raw_readl(phy_i2c_base + SATA_I2C_CON);
+	val |= (2 & CON_TXCLK_PS);
+	__raw_writel(val, phy_i2c_base + SATA_I2C_CON);
+
+	val = __raw_readl(phy_i2c_base + SATA_I2C_LC);
+	val &= ~(LC_FLTR_EN);
+	__raw_writel(val, phy_i2c_base + SATA_I2C_LC);
+
+	sata_i2c_set_ack_gen(false);
+}
+static bool sata_i2c_send(u8 slave_addrs, u8 addrs, u8 ucData)
+{
+	s32 ret = 0;
+	if (!sata_i2c_wait_for_busready(SATA_TIME_LIMIT))
+		return false;
+
+	sata_i2c_init();
+	sata_i2c_set_master_tx();
+
+	__raw_writel(SATA_PHY_CON_RESET, phy_ctrl + SATA_RESET);
+	sata_i2c_write_addrs(slave_addrs);
+	sata_i2c_start();
+	if (!sata_i2c_wait_for_tx_ack(SATA_TIME_LIMIT)) {
+		ret = false;
+		goto STOP;
+	}
+	sata_i2c_write_data(addrs);
+	sata_i2c_clear_int_status();
+	if (!sata_i2c_wait_for_tx_ack(SATA_TIME_LIMIT)) {
+		ret = false;
+		goto STOP;
+	}
+	sata_i2c_write_data(ucData);
+	sata_i2c_clear_int_status();
+	if (!sata_i2c_wait_for_tx_ack(SATA_TIME_LIMIT)) {
+		ret = false;
+		goto STOP;
+	}
+	ret = true;
+
+STOP:
+	sata_i2c_stop();
+	sata_i2c_clear_int_status();
+	sata_i2c_wait_for_busready(SATA_TIME_LIMIT);
+
+	return ret;
+}
+
+static int ahci_phy_init(void __iomem *mmio)
+{
+	u8 uCount, i = 0;
+	/* 0x3A for 40bit I/F */
+	u8 reg_addrs[] = {0x22, 0x21, 0x3A};
+	/* 0x0B for 40bit I/F */
+	u8 default_setting_value[] = {0x30, 0x4f, 0x0B};
+
+	uCount = sizeof(reg_addrs)/sizeof(u8);
+	while (i < uCount) {
+		if (!sata_i2c_send(SATA_PHY_I2C_SLAVE_ADDRS, reg_addrs[i],
+					default_setting_value[i]))
+			return false;
+		i++;
+	}
+	return 0;
+}
+
+static int exynos5_ahci_init(struct device *dev, void __iomem *mmio)
+{
+	struct clk *clk_sata, *clk_sataphy, *clk_sata_i2c, *clk_sclk_sata;
+	int val, ret;
+
+	phy_i2c_base = ioremap(EXYNOS5_PA_SATA_PHY_I2C, SZ_4K);
+	if (!phy_i2c_base) {
+		dev_err(dev, "failed to allocate memory for SATA PHY\n");
+		return -ENOMEM;
+	}
+
+	phy_ctrl = ioremap(EXYNOS5_PA_SATA_PHY_CTRL, SZ_64K);
+	if (!phy_ctrl) {
+		dev_err(dev, "failed to allocate memory for SATA PHY CTRL\n");
+		ret = -ENOMEM;
+		goto err1;
+	}
+
+	__raw_writel(S5P_PMU_SATA_PHY_CONTROL_EN, EXYNOS5_SATA_PHY_CONTROL);
+
+	val = 0;
+	__raw_writel(val, phy_ctrl + SATA_RESET);
+	val = __raw_readl(phy_ctrl + SATA_RESET);
+	val |= 0x3D;
+	__raw_writel(val, phy_ctrl + SATA_RESET);
+
+	clk_sata = clk_get(dev, "sata");
+	if (IS_ERR(clk_sata)) {
+		dev_err(dev, "failed to get sata clock\n");
+		ret = PTR_ERR(clk_sata);
+		clk_sata = NULL;
+		goto err2;
+
+	}
+	clk_enable(clk_sata);
+
+	clk_sataphy = clk_get(dev, "sata_phy");
+	if (IS_ERR(clk_sataphy)) {
+		dev_err(dev, "failed to get sataphy clock\n");
+		ret = PTR_ERR(clk_sataphy);
+		clk_sataphy = NULL;
+		goto err3;
+	}
+	clk_enable(clk_sataphy);
+
+	clk_sata_i2c = clk_get(dev, "sata_phy_i2c");
+	if (IS_ERR(clk_sata_i2c)) {
+		dev_err(dev, "failed to get sclk_sata\n");
+		ret = PTR_ERR(clk_sata_i2c);
+		clk_sata_i2c = NULL;
+		goto err4;
+	}
+	clk_enable(clk_sata_i2c);
+
+	clk_sclk_sata = clk_get(dev, "sclk_sata");
+	clk_enable(clk_sclk_sata);
+	if (IS_ERR(clk_sclk_sata)) {
+		dev_err(dev, "failed to get sclk_sata\n");
+		ret = PTR_ERR(clk_sclk_sata);
+		clk_sclk_sata = NULL;
+		goto err5;
+	}
+	clk_set_rate(clk_sclk_sata, SCLK_SATA_FREQ);
+
+	val = __raw_readl(phy_ctrl + SATA_RESET);
+	val |= LINK_RESET;
+	__raw_writel(val, phy_ctrl + SATA_RESET);
+
+	val = __raw_readl(phy_ctrl + SATA_RESET);
+	val |= RESET_CMN_RST_N;
+	__raw_writel(val, phy_ctrl + SATA_RESET);
+
+	val = __raw_readl(phy_ctrl + SATA_PHSATA_CTRLM);
+	val &= ~PHCTRLM_REF_RATE;
+	__raw_writel(val, phy_ctrl + SATA_PHSATA_CTRLM);
+
+	/* High speed enable for Gen3 */
+	val = __raw_readl(phy_ctrl + SATA_PHSATA_CTRLM);
+	val |= PHCTRLM_HIGH_SPEED;
+	__raw_writel(val, phy_ctrl + SATA_PHSATA_CTRLM);
+
+	/* Port0 is available */
+	__raw_writel(0x1, mmio + HOST_PORTS_IMPL);
+
+	ret = ahci_phy_init(mmio);
+
+	val = __raw_readl(phy_ctrl + SATA_CTRL0);
+	val |= CTRL0_P0_PHY_CALIBRATED_SEL|CTRL0_P0_PHY_CALIBRATED;
+	__raw_writel(val, phy_ctrl + SATA_CTRL0);
+	sata_set_gen(GEN3);
+
+	/* release cmu reset */
+	val = __raw_readl(phy_ctrl + SATA_RESET);
+	val &= ~RESET_CMN_RST_N;
+	__raw_writel(val, phy_ctrl + SATA_RESET);
+
+	val = __raw_readl(phy_ctrl + SATA_RESET);
+	val |= RESET_CMN_RST_N;
+	__raw_writel(val, phy_ctrl + SATA_RESET);
+
+	if (wait_for_reg_status(phy_ctrl, SATA_PHSATA_STATM,
+				PHSTATM_PLL_LOCKED, 1)) {
+		return ret;
+	}
+	dev_err(dev, " ahci_phy_init FAIL\n");
+
+err5:
+	clk_disable(clk_sata_i2c);
+	clk_put(clk_sata_i2c);
+err4:
+	clk_disable(clk_sataphy);
+	clk_put(clk_sataphy);
+err3:
+	clk_disable(clk_sata);
+	clk_put(clk_sata);
+err2:
+	iounmap(phy_ctrl);
+err1:
+	iounmap(phy_i2c_base);
+
+	return false;
+}
+
+static struct ahci_platform_data exynos5_ahci_pdata = {
+	.init = exynos5_ahci_init,
+};
+
+static struct resource exynos5_ahci_resource[] = {
+	[0] = {
+		.start	= EXYNOS5_PA_SATA_BASE,
+		.end	= EXYNOS5_PA_SATA_BASE + SZ_64K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= IRQ_SATA,
+		.end	= IRQ_SATA,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static u64 exynos5_ahci_dmamask = DMA_BIT_MASK(32);
+
+struct platform_device exynos5_device_ahci = {
+	.name		= "ahci",
+	.id		= -1,
+	.resource	= exynos5_ahci_resource,
+	.num_resources	= ARRAY_SIZE(exynos5_ahci_resource),
+	.dev		= {
+		.platform_data		= &exynos5_ahci_pdata,
+		.dma_mask		= &exynos5_ahci_dmamask,
+		.coherent_dma_mask	= DMA_BIT_MASK(32),
+	},
+};
diff --git a/arch/arm/mach-exynos/dev-ahci.c b/arch/arm/mach-exynos/dev-ahci.c
new file mode 100644
index 0000000..21b0f4f
--- /dev/null
+++ b/arch/arm/mach-exynos/dev-ahci.c
@@ -0,0 +1,263 @@
+/* linux/arch/arm/mach-exynos/dev-ahci.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS4 - AHCI support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/ahci_platform.h>
+
+#include <plat/cpu.h>
+
+#include <mach/irqs.h>
+#include <mach/map.h>
+#include <mach/regs-pmu.h>
+
+/* PHY Control Register */
+#define SATA_CTRL0		0x0
+/* PHY Link Control Register */
+#define SATA_CTRL1		0x4
+/* PHY Status Register */
+#define SATA_PHY_STATUS		0x8
+
+#define SATA_CTRL0_RX_DATA_VALID(x)	(x << 27)
+#define SATA_CTRL0_SPEED_MODE		(1 << 26)
+#define SATA_CTRL0_M_PHY_CAL		(1 << 19)
+#define SATA_CTRL0_PHY_CMU_RST_N	(1 << 10)
+#define SATA_CTRL0_M_PHY_LN_RST_N	(1 << 9)
+#define SATA_CTRL0_PHY_POR_N		(1 << 8)
+
+#define SATA_CTRL1_RST_PMALIVE_N	(1 << 8)
+#define SATA_CTRL1_RST_RXOOB_N		(1 << 7)
+#define SATA_CTRL1_RST_RX_N		(1 << 6)
+#define SATA_CTRL1_RST_TX_N		(1 << 5)
+
+#define SATA_PHY_STATUS_CMU_OK		(1 << 18)
+#define SATA_PHY_STATUS_LANE_OK		(1 << 16)
+
+#define LANE0		0x200
+#define COM_LANE	0xA00
+
+#define HOST_PORTS_IMPL	0xC
+#define SCLK_SATA_FREQ	(67 * MHZ)
+
+static void __iomem *phy_base, *phy_ctrl;
+
+struct phy_reg {
+	u8	reg;
+	u8	val;
+};
+
+/* SATA PHY setup */
+static const struct phy_reg exynos4_sataphy_cmu[] = {
+	{ 0x00, 0x06 }, { 0x02, 0x80 }, { 0x22, 0xa0 }, { 0x23, 0x42 },
+	{ 0x2e, 0x04 }, { 0x2f, 0x50 }, { 0x30, 0x70 }, { 0x31, 0x02 },
+	{ 0x32, 0x25 }, { 0x33, 0x40 }, { 0x34, 0x01 }, { 0x35, 0x40 },
+	{ 0x61, 0x2e }, { 0x63, 0x5e }, { 0x65, 0x42 }, { 0x66, 0xd1 },
+	{ 0x67, 0x20 }, { 0x68, 0x28 }, { 0x69, 0x78 }, { 0x6a, 0x04 },
+	{ 0x6b, 0xc8 }, { 0x6c, 0x06 },
+};
+
+static const struct phy_reg exynos4_sataphy_lane[] = {
+	{ 0x00, 0x02 }, { 0x05, 0x10 }, { 0x06, 0x84 }, { 0x07, 0x04 },
+	{ 0x08, 0xe0 }, { 0x10, 0x23 }, { 0x13, 0x05 }, { 0x14, 0x30 },
+	{ 0x15, 0x00 }, { 0x17, 0x70 }, { 0x18, 0xf2 }, { 0x19, 0x1e },
+	{ 0x1a, 0x18 }, { 0x1b, 0x0d }, { 0x1c, 0x08 }, { 0x50, 0x60 },
+	{ 0x51, 0x0f },
+};
+
+static const struct phy_reg exynos4_sataphy_comlane[] = {
+	{ 0x01, 0x20 }, { 0x03, 0x40 }, { 0x04, 0x3c }, { 0x05, 0x7d },
+	{ 0x06, 0x1d }, { 0x07, 0xcf }, { 0x08, 0x05 }, { 0x09, 0x63 },
+	{ 0x0a, 0x29 }, { 0x0b, 0xc4 }, { 0x0c, 0x01 }, { 0x0d, 0x03 },
+	{ 0x0e, 0x28 }, { 0x0f, 0x98 }, { 0x10, 0x19 }, { 0x13, 0x80 },
+	{ 0x14, 0xf0 }, { 0x15, 0xd0 }, { 0x39, 0xa0 }, { 0x3a, 0xa0 },
+	{ 0x3b, 0xa0 }, { 0x3c, 0xa0 }, { 0x3d, 0xa0 }, { 0x3e, 0xa0 },
+	{ 0x3f, 0xa0 }, { 0x40, 0x42 }, { 0x42, 0x80 }, { 0x43, 0x58 },
+	{ 0x45, 0x44 }, { 0x46, 0x5c }, { 0x47, 0x86 }, { 0x48, 0x8d },
+	{ 0x49, 0xd0 }, { 0x4a, 0x09 }, { 0x4b, 0x90 }, { 0x4c, 0x07 },
+	{ 0x4d, 0x40 }, { 0x51, 0x20 }, { 0x52, 0x32 }, { 0x7f, 0xd8 },
+	{ 0x80, 0x1a }, { 0x81, 0xff }, { 0x82, 0x11 }, { 0x83, 0x00 },
+	{ 0x87, 0xf0 }, { 0x87, 0xff }, { 0x87, 0xff }, { 0x87, 0xff },
+	{ 0x87, 0xff }, { 0x8c, 0x1c }, { 0x8d, 0xc2 }, { 0x8e, 0xc3 },
+	{ 0x8f, 0x3f }, { 0x90, 0x0a }, { 0x96, 0xf8 },
+};
+
+static int wait_for_phy_ready(void __iomem *reg, unsigned long bit)
+{
+	unsigned long timeout;
+
+	/* wait for maximum of 3 sec */
+	timeout = jiffies + msecs_to_jiffies(3000);
+	while (!(__raw_readl(reg) & bit)) {
+		if (time_after(jiffies, timeout))
+			return -1;
+		cpu_relax();
+	}
+	return 0;
+}
+
+static int ahci_phy_init(void __iomem *mmio)
+{
+	int i, ctrl0;
+
+	for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_cmu); i++)
+		__raw_writeb(exynos4_sataphy_cmu[i].val,
+		phy_base + (exynos4_sataphy_cmu[i].reg * 4));
+
+	for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_lane); i++)
+		__raw_writeb(exynos4_sataphy_lane[i].val,
+		phy_base + (LANE0 + exynos4_sataphy_lane[i].reg) * 4);
+
+	for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_comlane); i++)
+		__raw_writeb(exynos4_sataphy_comlane[i].val,
+		phy_base + (COM_LANE + exynos4_sataphy_comlane[i].reg) * 4);
+
+	__raw_writeb(0x07, phy_base);
+
+	ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
+	ctrl0 |= SATA_CTRL0_PHY_CMU_RST_N;
+	__raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
+
+	if (wait_for_phy_ready(phy_ctrl + SATA_PHY_STATUS,
+				SATA_PHY_STATUS_CMU_OK) < 0) {
+		printk(KERN_ERR "PHY CMU not ready\n");
+		return -EBUSY;
+	}
+
+	__raw_writeb(0x03, phy_base + (COM_LANE * 4));
+
+	ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
+	ctrl0 |= SATA_CTRL0_M_PHY_LN_RST_N;
+	__raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
+
+	if (wait_for_phy_ready(phy_ctrl + SATA_PHY_STATUS,
+				SATA_PHY_STATUS_LANE_OK) < 0) {
+		printk(KERN_ERR "PHY LANE not ready\n");
+		return -EBUSY;
+	}
+
+	ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
+	ctrl0 |= SATA_CTRL0_M_PHY_CAL;
+	__raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
+
+	return 0;
+}
+
+static int exynos4_ahci_init(struct device *dev, void __iomem *mmio)
+{
+	struct clk *clk_sata, *clk_sataphy, *clk_sclk_sata;
+	int val, ret;
+
+	phy_base = ioremap(EXYNOS4_PA_SATAPHY, SZ_64K);
+	if (!phy_base) {
+		dev_err(dev, "failed to allocate memory for SATA PHY\n");
+		return -ENOMEM;
+	}
+
+	phy_ctrl = ioremap(EXYNOS4_PA_SATAPHY_CTRL, SZ_16);
+	if (!phy_ctrl) {
+		dev_err(dev, "failed to allocate memory for SATA PHY CTRL\n");
+		ret = -ENOMEM;
+		goto err1;
+	}
+
+	clk_sata = clk_get(dev, "sata");
+	if (IS_ERR(clk_sata)) {
+		dev_err(dev, "failed to get sata clock\n");
+		ret = PTR_ERR(clk_sata);
+		clk_sata = NULL;
+		goto err2;
+
+	}
+	clk_enable(clk_sata);
+
+	clk_sataphy = clk_get(dev, "sataphy");
+	if (IS_ERR(clk_sataphy)) {
+		dev_err(dev, "failed to get sataphy clock\n");
+		ret = PTR_ERR(clk_sataphy);
+		clk_sataphy = NULL;
+		goto err3;
+	}
+	clk_enable(clk_sataphy);
+
+	clk_sclk_sata = clk_get(dev, "sclk_sata");
+	if (IS_ERR(clk_sclk_sata)) {
+		dev_err(dev, "failed to get sclk_sata\n");
+		ret = PTR_ERR(clk_sclk_sata);
+		clk_sclk_sata = NULL;
+		goto err4;
+	}
+	clk_enable(clk_sclk_sata);
+	clk_set_rate(clk_sclk_sata, SCLK_SATA_FREQ);
+
+	__raw_writel(S5P_PMU_SATA_PHY_CONTROL_EN, S5P_PMU_SATA_PHY_CONTROL);
+
+	/* Enable PHY link control */
+	val = SATA_CTRL1_RST_PMALIVE_N | SATA_CTRL1_RST_RXOOB_N |
+			SATA_CTRL1_RST_RX_N | SATA_CTRL1_RST_TX_N;
+	__raw_writel(val, phy_ctrl + SATA_CTRL1);
+
+	/* Set communication speed as 3Gbps and enable PHY power */
+	val = SATA_CTRL0_RX_DATA_VALID(3) | SATA_CTRL0_SPEED_MODE |
+			SATA_CTRL0_PHY_POR_N;
+	__raw_writel(val, phy_ctrl + SATA_CTRL0);
+
+	/* Port0 is available */
+	__raw_writel(0x1, mmio + HOST_PORTS_IMPL);
+
+	return ahci_phy_init(mmio);
+
+err4:
+	clk_disable(clk_sataphy);
+	clk_put(clk_sataphy);
+err3:
+	clk_disable(clk_sata);
+	clk_put(clk_sata);
+err2:
+	iounmap(phy_ctrl);
+err1:
+	iounmap(phy_base);
+
+	return ret;
+}
+
+static struct ahci_platform_data exynos4_ahci_pdata = {
+	.init = exynos4_ahci_init,
+};
+
+static struct resource exynos4_ahci_resource[] = {
+	[0] = {
+		.start	= EXYNOS4_PA_SATA,
+		.end	= EXYNOS4_PA_SATA + SZ_64K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= IRQ_SATA,
+		.end	= IRQ_SATA,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static u64 exynos4_ahci_dmamask = DMA_BIT_MASK(32);
+
+struct platform_device exynos4_device_ahci = {
+	.name		= "ahci",
+	.id		= -1,
+	.resource	= exynos4_ahci_resource,
+	.num_resources	= ARRAY_SIZE(exynos4_ahci_resource),
+	.dev		= {
+		.platform_data		= &exynos4_ahci_pdata,
+		.dma_mask		= &exynos4_ahci_dmamask,
+		.coherent_dma_mask	= DMA_BIT_MASK(32),
+	},
+};
diff --git a/arch/arm/mach-exynos/dev-audio.c b/arch/arm/mach-exynos/dev-audio.c
new file mode 100644
index 0000000..054a26d
--- /dev/null
+++ b/arch/arm/mach-exynos/dev-audio.c
@@ -0,0 +1,438 @@
+/* linux/arch/arm/mach-exynos/dev-audio.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Copyright (c) 2010 Samsung Electronics Co. Ltd
+ *	Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/gpio.h>
+
+#include <plat/gpio-cfg.h>
+#include <plat/audio.h>
+#include <plat/cpu.h>
+
+#include <mach/map.h>
+#include <mach/dma.h>
+#include <mach/irqs.h>
+
+static const char *rclksrc[] = {
+	[0] = "busclk",
+	[1] = "i2sclk",
+};
+
+struct exynos_gpio_cfg {
+	unsigned int	addr;
+	unsigned int	num;
+	unsigned int	bit;
+};
+
+static int exynos_cfg_i2s_gpio(struct platform_device *pdev)
+{
+	/* configure GPIO for i2s port */
+	struct exynos_gpio_cfg exynos4_cfg[3] = {
+				{ EXYNOS4_GPZ(0),  7, S3C_GPIO_SFN(2) },
+				{ EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(2) },
+				{ EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(2) }
+	};
+	struct exynos_gpio_cfg exynos5_cfg[3] = {
+				{ EXYNOS5_GPZ(0),  7, S3C_GPIO_SFN(2) },
+				{ EXYNOS5_GPB0(0), 5, S3C_GPIO_SFN(2) },
+				{ EXYNOS5_GPB1(0), 5, S3C_GPIO_SFN(2) }
+	};
+
+	if (pdev->id < 0 || pdev->id > 2) {
+		printk(KERN_ERR "Invalid Device %d\n", pdev->id);
+		return -EINVAL;
+	}
+
+	if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412())
+		s3c_gpio_cfgpin_range(exynos4_cfg[pdev->id].addr,
+			exynos4_cfg[pdev->id].num, exynos4_cfg[pdev->id].bit);
+	else if (soc_is_exynos5210() || soc_is_exynos5250())
+		s3c_gpio_cfgpin_range(exynos5_cfg[pdev->id].addr,
+			exynos5_cfg[pdev->id].num, exynos5_cfg[pdev->id].bit);
+
+	return 0;
+}
+
+static struct s3c_audio_pdata i2sv5_pdata = {
+	.cfg_gpio = exynos_cfg_i2s_gpio,
+	.type = {
+		.i2s = {
+			.quirks = QUIRK_PRI_6CHAN
+#ifdef CONFIG_SND_SOC_SAMSUNG_I2S_SEC
+				| QUIRK_SEC_DAI
+#endif
+#ifdef CONFIG_SND_SAMSUNG_RP
+				| QUIRK_ENABLED_SRP
+#endif
+				| QUIRK_NEED_RSTCLR,
+			.src_clk = rclksrc,
+		},
+	},
+};
+
+static struct resource exynos_i2s0_resource[] = {
+	[0] = {
+		.start	= EXYNOS_PA_I2S0,
+		.end	= EXYNOS_PA_I2S0 + 0x100 - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= DMACH_I2S0_TX,
+		.end	= DMACH_I2S0_TX,
+		.flags	= IORESOURCE_DMA,
+	},
+	[2] = {
+		.start	= DMACH_I2S0_RX,
+		.end	= DMACH_I2S0_RX,
+		.flags	= IORESOURCE_DMA,
+	},
+	[3] = {
+		.start	= DMACH_I2S0S_TX,
+		.end	= DMACH_I2S0S_TX,
+		.flags	= IORESOURCE_DMA,
+	},
+};
+
+struct platform_device exynos_device_i2s0 = {
+	.name = "samsung-i2s",
+	.id = 0,
+	.num_resources = ARRAY_SIZE(exynos_i2s0_resource),
+	.resource = exynos_i2s0_resource,
+	.dev = {
+		.platform_data = &i2sv5_pdata,
+	},
+};
+
+static const char *rclksrc_v3[] = {
+	[0] = "sclk_i2s",
+	[1] = "no_such_clock",
+};
+
+static struct s3c_audio_pdata i2sv3_pdata = {
+	.cfg_gpio = exynos_cfg_i2s_gpio,
+	.type = {
+		.i2s = {
+			.quirks = QUIRK_NO_MUXPSR,
+			.src_clk = rclksrc_v3,
+		},
+	},
+};
+
+static struct resource exynos_i2s1_resource[] = {
+	[0] = {
+		.start	= EXYNOS_PA_I2S1,
+		.end	= EXYNOS_PA_I2S1 + 0x100 - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= DMACH_I2S1_TX,
+		.end	= DMACH_I2S1_TX,
+		.flags	= IORESOURCE_DMA,
+	},
+	[2] = {
+		.start	= DMACH_I2S1_RX,
+		.end	= DMACH_I2S1_RX,
+		.flags	= IORESOURCE_DMA,
+	},
+};
+
+struct platform_device exynos_device_i2s1 = {
+	.name = "samsung-i2s",
+	.id = 1,
+	.num_resources = ARRAY_SIZE(exynos_i2s1_resource),
+	.resource = exynos_i2s1_resource,
+	.dev = {
+		.platform_data = &i2sv3_pdata,
+	},
+};
+
+static struct resource exynos_i2s2_resource[] = {
+	[0] = {
+		.start	= EXYNOS_PA_I2S2,
+		.end	= EXYNOS_PA_I2S2 + 0x100 - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= DMACH_I2S2_TX,
+		.end	= DMACH_I2S2_TX,
+		.flags	= IORESOURCE_DMA,
+	},
+	[2] = {
+		.start	= DMACH_I2S2_RX,
+		.end	= DMACH_I2S2_RX,
+		.flags	= IORESOURCE_DMA,
+	},
+};
+
+struct platform_device exynos_device_i2s2 = {
+	.name = "samsung-i2s",
+	.id = 2,
+	.num_resources = ARRAY_SIZE(exynos_i2s2_resource),
+	.resource = exynos_i2s2_resource,
+	.dev = {
+		.platform_data = &i2sv3_pdata,
+	},
+};
+
+/* PCM Controller platform_devices */
+
+static int exynos_pcm_cfg_gpio(struct platform_device *pdev)
+{
+	/* configure GPIO for pcm port */
+	struct exynos_gpio_cfg exynos4_cfg[3] = {
+				{ EXYNOS4_GPZ(0),  5, S3C_GPIO_SFN(3) },
+				{ EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(3) },
+				{ EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(3) }
+	};
+	struct exynos_gpio_cfg exynos5_cfg[3] = {
+				{ EXYNOS5_GPZ(0),  5, S3C_GPIO_SFN(3) },
+				{ EXYNOS5_GPB0(0), 5, S3C_GPIO_SFN(3) },
+				{ EXYNOS5_GPB1(0), 5, S3C_GPIO_SFN(3) }
+	};
+
+	if (pdev->id < 0 || pdev->id > 2) {
+		printk(KERN_ERR "Invalid Device %d\n", pdev->id);
+		return -EINVAL;
+	}
+
+	if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412())
+		s3c_gpio_cfgpin_range(exynos4_cfg[pdev->id].addr,
+			exynos4_cfg[pdev->id].num, exynos4_cfg[pdev->id].bit);
+	else if (soc_is_exynos5210() || soc_is_exynos5250())
+		s3c_gpio_cfgpin_range(exynos5_cfg[pdev->id].addr,
+			exynos5_cfg[pdev->id].num, exynos5_cfg[pdev->id].bit);
+
+	return 0;
+}
+
+static struct s3c_audio_pdata s3c_pcm_pdata = {
+	.cfg_gpio = exynos_pcm_cfg_gpio,
+};
+
+static struct resource exynos_pcm0_resource[] = {
+	[0] = {
+		.start	= EXYNOS_PA_PCM0,
+		.end	= EXYNOS_PA_PCM0 + 0x100 - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= DMACH_PCM0_TX,
+		.end	= DMACH_PCM0_TX,
+		.flags	= IORESOURCE_DMA,
+	},
+	[2] = {
+		.start	= DMACH_PCM0_RX,
+		.end	= DMACH_PCM0_RX,
+		.flags	= IORESOURCE_DMA,
+	},
+};
+
+struct platform_device exynos_device_pcm0 = {
+	.name = "samsung-pcm",
+	.id = 0,
+	.num_resources = ARRAY_SIZE(exynos_pcm0_resource),
+	.resource = exynos_pcm0_resource,
+	.dev = {
+		.platform_data = &s3c_pcm_pdata,
+	},
+};
+
+static struct resource exynos_pcm1_resource[] = {
+	[0] = {
+		.start	= EXYNOS_PA_PCM1,
+		.end	= EXYNOS_PA_PCM1 + 0x100 - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= DMACH_PCM1_TX,
+		.end	= DMACH_PCM1_TX,
+		.flags	= IORESOURCE_DMA,
+	},
+	[2] = {
+		.start	= DMACH_PCM1_RX,
+		.end	= DMACH_PCM1_RX,
+		.flags	= IORESOURCE_DMA,
+	},
+};
+
+struct platform_device exynos_device_pcm1 = {
+	.name = "samsung-pcm",
+	.id = 1,
+	.num_resources = ARRAY_SIZE(exynos_pcm1_resource),
+	.resource = exynos_pcm1_resource,
+	.dev = {
+		.platform_data = &s3c_pcm_pdata,
+	},
+};
+
+static struct resource exynos_pcm2_resource[] = {
+	[0] = {
+		.start	= EXYNOS_PA_PCM2,
+		.end	= EXYNOS_PA_PCM2 + 0x100 - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= DMACH_PCM2_TX,
+		.end	= DMACH_PCM2_TX,
+		.flags	= IORESOURCE_DMA,
+	},
+	[2] = {
+		.start	= DMACH_PCM2_RX,
+		.end	= DMACH_PCM2_RX,
+		.flags	= IORESOURCE_DMA,
+	},
+};
+
+struct platform_device exynos_device_pcm2 = {
+	.name = "samsung-pcm",
+	.id = 2,
+	.num_resources = ARRAY_SIZE(exynos_pcm2_resource),
+	.resource = exynos_pcm2_resource,
+	.dev = {
+		.platform_data = &s3c_pcm_pdata,
+	},
+};
+
+/* AC97 Controller platform devices */
+
+static int exynos_ac97_cfg_gpio(struct platform_device *pdev)
+{
+	/* configure GPIO for ac97 port */
+	if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412())
+		s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(4));
+	else if (soc_is_exynos5210() || soc_is_exynos5250())
+		s3c_gpio_cfgpin_range(EXYNOS5_GPB0(0), 5, S3C_GPIO_SFN(4));
+
+	return 0;
+}
+
+static struct resource exynos_ac97_resource[] = {
+	[0] = {
+		.start	= EXYNOS_PA_AC97,
+		.end	= EXYNOS_PA_AC97 + 0x100 - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= DMACH_AC97_PCMOUT,
+		.end	= DMACH_AC97_PCMOUT,
+		.flags	= IORESOURCE_DMA,
+	},
+	[2] = {
+		.start	= DMACH_AC97_PCMIN,
+		.end	= DMACH_AC97_PCMIN,
+		.flags	= IORESOURCE_DMA,
+	},
+	[3] = {
+		.start	= DMACH_AC97_MICIN,
+		.end	= DMACH_AC97_MICIN,
+		.flags	= IORESOURCE_DMA,
+	},
+	[4] = {
+		.start	= IRQ_AC97,
+		.end	= IRQ_AC97,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct s3c_audio_pdata s3c_ac97_pdata = {
+	.cfg_gpio = exynos_ac97_cfg_gpio,
+};
+
+static u64 exynos_ac97_dmamask = DMA_BIT_MASK(32);
+
+struct platform_device exynos_device_ac97 = {
+	.name = "samsung-ac97",
+	.id = -1,
+	.num_resources = ARRAY_SIZE(exynos_ac97_resource),
+	.resource = exynos_ac97_resource,
+	.dev = {
+		.platform_data = &s3c_ac97_pdata,
+		.dma_mask = &exynos_ac97_dmamask,
+		.coherent_dma_mask = DMA_BIT_MASK(32),
+	},
+};
+
+/* S/PDIF Controller platform_device */
+
+static int exynos_spdif_cfg_gpio(struct platform_device *pdev)
+{
+	/* configure GPIO for SPDIF port */
+	if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412())
+		s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 2, S3C_GPIO_SFN(4));
+	else if (soc_is_exynos5210() || soc_is_exynos5250())
+		s3c_gpio_cfgpin_range(EXYNOS5_GPB1(0), 2, S3C_GPIO_SFN(4));
+
+	return 0;
+}
+
+static struct resource exynos_spdif_resource[] = {
+	[0] = {
+		.start	= EXYNOS_PA_SPDIF,
+		.end	= EXYNOS_PA_SPDIF + 0x100 - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= DMACH_SPDIF,
+		.end	= DMACH_SPDIF,
+		.flags	= IORESOURCE_DMA,
+	},
+};
+
+static struct s3c_audio_pdata samsung_spdif_pdata = {
+	.cfg_gpio = exynos_spdif_cfg_gpio,
+};
+
+static u64 exynos_spdif_dmamask = DMA_BIT_MASK(32);
+
+struct platform_device exynos_device_spdif = {
+	.name = "samsung-spdif",
+	.id = -1,
+	.num_resources = ARRAY_SIZE(exynos_spdif_resource),
+	.resource = exynos_spdif_resource,
+	.dev = {
+		.platform_data = &samsung_spdif_pdata,
+		.dma_mask = &exynos_spdif_dmamask,
+		.coherent_dma_mask = DMA_BIT_MASK(32),
+	},
+};
+
+#if defined(CONFIG_SND_SAMSUNG_RP) || defined(CONFIG_SND_SAMSUNG_ALP)
+static struct resource exynos_srp_resource[] = {
+};
+
+static u64 exynos_srp_dmamask = DMA_BIT_MASK(32);
+
+struct platform_device exynos_device_srp = {
+	.name             = "samsung-rp",
+	.id               = -1,
+	.num_resources    = ARRAY_SIZE(exynos_srp_resource),
+	.resource         = exynos_srp_resource,
+	.dev = {
+		.dma_mask = &exynos_srp_dmamask,
+		.coherent_dma_mask = DMA_BIT_MASK(32),
+	},
+};
+EXPORT_SYMBOL(exynos_device_srp);
+#endif
+
+#ifdef CONFIG_ARCH_EXYNOS4
+void __init exynos4_i2sv3_setup_resource(void)
+{
+	if (!soc_is_exynos4210()) {
+		exynos_i2s1_resource[0].start = EXYNOS4212_PA_I2S1;
+		exynos_i2s1_resource[0].end   = EXYNOS4212_PA_I2S1 + 0x100 - 1;
+		exynos_i2s2_resource[0].start = EXYNOS4212_PA_I2S2;
+		exynos_i2s2_resource[0].end   = EXYNOS4212_PA_I2S2 + 0x100 - 1;
+	}
+}
+#endif
diff --git a/arch/arm/mach-exynos/dev-c2c.c b/arch/arm/mach-exynos/dev-c2c.c
new file mode 100644
index 0000000..1b77a8e
--- /dev/null
+++ b/arch/arm/mach-exynos/dev-c2c.c
@@ -0,0 +1,85 @@
+/* linux/arch/arm/mach-exynos/dev-c2c.c
+ *
+ * Copyright (c) 2011 Samsung Electronics
+ *
+ * Base EXYNOS C2C resource and device definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/ioport.h>
+#include <linux/dma-mapping.h>
+
+#include <mach/map.h>
+#include <mach/regs-pmu.h>
+#include <mach/regs-pmu5.h>
+#include <mach/c2c.h>
+#include <plat/irqs.h>
+#include <plat/cpu.h>
+
+static struct resource exynos_c2c_resource[] = {
+	[0] = {
+		.start  = EXYNOS_PA_C2C,
+		.end    = EXYNOS_PA_C2C + SZ_64K - 1,
+		.flags  = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start  = EXYNOS_PA_C2C_CP,
+		.end    = EXYNOS_PA_C2C_CP + SZ_64K - 1,
+		.flags  = IORESOURCE_MEM,
+	},
+	[2] = {
+		.start  = IRQ_C2C_SSCM0,
+		.end    = IRQ_C2C_SSCM0,
+		.flags  = IORESOURCE_IRQ,
+	},
+	[3] = {
+		.start  = IRQ_C2C_SSCM1,
+		.end    = IRQ_C2C_SSCM1,
+		.flags  = IORESOURCE_IRQ,
+	},
+};
+
+static u64 exynos_c2c_dma_mask = DMA_BIT_MASK(32);
+
+struct platform_device exynos_device_c2c = {
+	.name		= "samsung-c2c",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(exynos_c2c_resource),
+	.resource	= exynos_c2c_resource,
+	.dev		= {
+		.dma_mask		= &exynos_c2c_dma_mask,
+		.coherent_dma_mask	= DMA_BIT_MASK(32),
+	},
+};
+
+void __init exynos_c2c_set_platdata(struct exynos_c2c_platdata *pd)
+{
+	struct exynos_c2c_platdata *npd = pd;
+
+	if (!npd->setup_gpio)
+		npd->setup_gpio = exynos_c2c_cfg_gpio;
+	if (!npd->set_cprst)
+		npd->set_cprst = exynos_c2c_set_cprst;
+	if (!npd->clear_cprst)
+		npd->clear_cprst = exynos_c2c_clear_cprst;
+
+	if (soc_is_exynos4212() || soc_is_exynos4412()) {
+		/* Set C2C_CTRL Register */
+		writel(0x1, S5P_C2C_CTRL);
+		if (samsung_rev() < EXYNOS4412_REV_1_0)
+			npd->c2c_sysreg = S3C_VA_SYS + 0x010C;
+	} else if (soc_is_exynos5250()) {
+		/* Set C2C_CTRL Register */
+		writel(0x1, EXYNOS5_C2C_CTRL);
+		if (samsung_rev() < EXYNOS5250_REV_1_0)
+			npd->c2c_sysreg = S3C_VA_SYS + 0x0360;
+	}
+
+	exynos_device_c2c.dev.platform_data = npd;
+}
diff --git a/arch/arm/mach-exynos/dev-dwmci.c b/arch/arm/mach-exynos/dev-dwmci.c
new file mode 100644
index 0000000..8db1907
--- /dev/null
+++ b/arch/arm/mach-exynos/dev-dwmci.c
@@ -0,0 +1,239 @@
+/*
+ * linux/arch/arm/mach-exynos/dev-dwmci.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Platform device for Synopsys DesignWare Mobile Storage IP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/mmc/dw_mmc.h>
+#include <linux/mmc/host.h>
+
+#include <plat/devs.h>
+#include <plat/cpu.h>
+
+#include <mach/map.h>
+
+#define DWMCI_CLKSEL	0x09c
+
+static int exynos_dwmci_get_bus_wd(u32 slot_id)
+{
+	return 4;
+}
+
+static int exynos_dwmci_init(u32 slot_id, irq_handler_t handler, void *data)
+{
+	struct dw_mci *host = (struct dw_mci *)data;
+
+	/* Set Phase Shift Register */
+	if (soc_is_exynos4210()) {
+		host->pdata->sdr_timing = 0x00010001;
+		host->pdata->ddr_timing = 0x00020002;
+	} else if (soc_is_exynos4212() || soc_is_exynos4412()) {
+		host->pdata->sdr_timing = 0x00010001;
+		host->pdata->ddr_timing = 0x00010002;
+	} else if (soc_is_exynos5250()) {
+		if (samsung_rev() >= EXYNOS5250_REV_1_0) {
+			switch (host->pdev->id) {
+			case 0:
+				host->pdata->sdr_timing = 0x03020001;
+				host->pdata->ddr_timing = 0x03030002;
+				break;
+			case 1:
+				host->pdata->sdr_timing = 0x03020001;
+				host->pdata->ddr_timing = 0x03030002;
+				break;
+			case 2:
+				host->pdata->sdr_timing = 0x03020001;
+				host->pdata->ddr_timing = 0x03030002;
+				break;
+			case 3:
+				host->pdata->sdr_timing = 0x03020001;
+				host->pdata->ddr_timing = 0x03030002;
+				break;
+			default:
+				host->pdata->sdr_timing = 0x03020001;
+				host->pdata->ddr_timing = 0x03030002;
+				break;
+			}
+		} else {
+			host->pdata->sdr_timing = 0x00010000;
+			host->pdata->ddr_timing = 0x00010000;
+		}
+	}
+#ifdef CONFIG_SLP
+	host->pdata->sdr_timing = 0x00020001;
+	host->pdata->ddr_timing = 0x00020002;
+#endif
+
+	return 0;
+}
+
+static void exynos_dwmci_set_io_timing(void *data, unsigned char timing)
+{
+	struct dw_mci *host = (struct dw_mci *)data;
+
+	if (timing == MMC_TIMING_UHS_DDR50)
+		__raw_writel(host->pdata->ddr_timing,
+			host->regs + DWMCI_CLKSEL);
+	else
+		__raw_writel(host->pdata->sdr_timing,
+			host->regs + DWMCI_CLKSEL);
+}
+
+static struct resource exynos_dwmci_resource[] = {
+	[0] = {
+		.start	= EXYNOS_PA_DWMCI,
+		.end	= EXYNOS_PA_DWMCI + SZ_4K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= IRQ_DWMCI,
+		.end	= IRQ_DWMCI,
+		.flags	= IORESOURCE_IRQ,
+	}
+};
+
+static struct dw_mci_board exynos_dwmci_def_platdata = {
+	.num_slots		= 1,
+	.quirks			= DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
+	.bus_hz			= 80 * 1000 * 1000,
+	.detect_delay_ms	= 200,
+	.init			= exynos_dwmci_init,
+	.get_bus_wd		= exynos_dwmci_get_bus_wd,
+	.set_io_timing		= exynos_dwmci_set_io_timing,
+};
+
+static u64 exynos_dwmci_dmamask = DMA_BIT_MASK(32);
+
+struct platform_device exynos_device_dwmci = {
+	.name		= "dw_mmc",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(exynos_dwmci_resource),
+	.resource	= exynos_dwmci_resource,
+	.dev		= {
+		.dma_mask		= &exynos_dwmci_dmamask,
+		.coherent_dma_mask	= DMA_BIT_MASK(32),
+		.platform_data		= &exynos_dwmci_def_platdata,
+	},
+};
+
+#define EXYNOS5_DWMCI_RESOURCE(_channel) \
+static struct resource exynos5_dwmci##_channel##_resource[] = { \
+	[0] = {							\
+		.start	= S3C_PA_HSMMC##_channel,		\
+		.end	= S3C_PA_HSMMC##_channel + SZ_4K - 1,	\
+		.flags	= IORESOURCE_MEM,			\
+	},							\
+	[1] = {							\
+		.start	= IRQ_HSMMC##_channel,			\
+		.end	= IRQ_HSMMC##_channel,			\
+		.flags	= IORESOURCE_IRQ,			\
+	}							\
+};
+
+EXYNOS5_DWMCI_RESOURCE(0)
+EXYNOS5_DWMCI_RESOURCE(1)
+EXYNOS5_DWMCI_RESOURCE(2)
+EXYNOS5_DWMCI_RESOURCE(3)
+
+#define EXYNOS_DWMCI_DEF_PLATDATA(_channel)			\
+struct dw_mci_board exynos_dwmci##_channel##_def_platdata = {	\
+	.num_slots		= 1,				\
+	.quirks			=				\
+		DW_MCI_QUIRK_BROKEN_CARD_DETECTION,		\
+	.bus_hz			= 200 * 1000 * 1000,		\
+	.detect_delay_ms	= 200,				\
+	.init			= exynos_dwmci_init,		\
+	.get_bus_wd		= exynos_dwmci_get_bus_wd,	\
+	.set_io_timing		= exynos_dwmci_set_io_timing,	\
+	.cd_type 		= DW_MCI_CD_INTERNAL 		\
+};
+
+EXYNOS_DWMCI_DEF_PLATDATA(0)
+EXYNOS_DWMCI_DEF_PLATDATA(1)
+EXYNOS_DWMCI_DEF_PLATDATA(2)
+EXYNOS_DWMCI_DEF_PLATDATA(3)
+
+#define EXYNOS_DWMCI_PLATFORM_DEVICE(_channel)			\
+struct platform_device exynos_device_dwmci##_channel =		\
+{								\
+	.name		= "dw_mmc",				\
+	.id		= _channel,				\
+	.num_resources	=					\
+	ARRAY_SIZE(exynos5_dwmci##_channel##_resource), 	\
+	.resource	= exynos5_dwmci##_channel##_resource,	\
+	.dev		= {					\
+		.dma_mask		= &exynos_dwmci_dmamask,\
+		.coherent_dma_mask	= DMA_BIT_MASK(32),	\
+		.platform_data		=			\
+		&exynos_dwmci##_channel##_def_platdata,	\
+	},							\
+};
+
+EXYNOS_DWMCI_PLATFORM_DEVICE(0)
+EXYNOS_DWMCI_PLATFORM_DEVICE(1)
+EXYNOS_DWMCI_PLATFORM_DEVICE(2)
+EXYNOS_DWMCI_PLATFORM_DEVICE(3)
+
+void __init exynos_dwmci_set_platdata(struct dw_mci_board *pd, u32 slot_id)
+{
+	struct dw_mci_board *npd = NULL;
+
+	if ((soc_is_exynos4210()) ||
+		soc_is_exynos4212() || soc_is_exynos4412()) {
+		npd = s3c_set_platdata(pd, sizeof(struct dw_mci_board),
+			&exynos_device_dwmci);
+	} else if (soc_is_exynos5250()) {
+		if (slot_id == 0) {
+			if (samsung_rev() < EXYNOS5250_REV_1_0) {
+				exynos_device_dwmci0.resource[0].start =
+					EXYNOS_PA_DWMCI;
+				exynos_device_dwmci0.resource[0].end =
+					EXYNOS_PA_DWMCI + SZ_4K - 1;
+				exynos_device_dwmci0.resource[1].start =
+					IRQ_DWMCI;
+				exynos_device_dwmci0.resource[1].end =
+					IRQ_DWMCI;
+			}
+			npd = s3c_set_platdata(pd, sizeof(struct dw_mci_board),
+				&exynos_device_dwmci0);
+		} else if (slot_id == 1) {
+			npd = s3c_set_platdata(pd, sizeof(struct dw_mci_board),
+				&exynos_device_dwmci1);
+		} else if (slot_id == 2) {
+			npd = s3c_set_platdata(pd, sizeof(struct dw_mci_board),
+				&exynos_device_dwmci2);
+		} else if (slot_id == 3) {
+			npd = s3c_set_platdata(pd, sizeof(struct dw_mci_board),
+				&exynos_device_dwmci3);
+		} else {
+			pr_err("This channel %d Cannot support.\n", slot_id);
+		}
+	} else {
+		printk("dwmci platform data support only exynos4/5!\n");
+#ifdef CONFIG_SLP
+		npd = s3c_set_platdata(pd, sizeof(struct dw_mci_board),
+			&exynos_device_dwmci);
+#endif
+	}
+
+	if (npd) {
+		if (!npd->init)
+			npd->init = exynos_dwmci_init;
+		if (!npd->get_bus_wd)
+			npd->get_bus_wd = exynos_dwmci_get_bus_wd;
+		if (!npd->set_io_timing)
+			npd->set_io_timing = exynos_dwmci_set_io_timing;
+	}
+}
diff --git a/arch/arm/mach-exynos/dev-fimc-is.c b/arch/arm/mach-exynos/dev-fimc-is.c
new file mode 100644
index 0000000..bc531e3
--- /dev/null
+++ b/arch/arm/mach-exynos/dev-fimc-is.c
@@ -0,0 +1,136 @@
+/* linux/arch/arm/plat-s5p/dev-fimc_is.c
+ *
+ * Copyright (c) 2011 Samsung Electronics
+ *
+ * Base FIMC-IS resource and device definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <media/exynos_fimc_is.h>
+
+#if defined(CONFIG_ARCH_EXYNOS4)
+static struct resource exynos4_fimc_is_resource[] = {
+	[0] = {
+		.start	= EXYNOS4_PA_FIMC_IS,
+		.end	= EXYNOS4_PA_FIMC_IS + SZ_2M + SZ_256K + SZ_128K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= IRQ_FIMC_IS0,
+		.end	= IRQ_FIMC_IS0,
+		.flags	= IORESOURCE_IRQ,
+	},
+	[2] = {
+		.start	= IRQ_FIMC_IS1,
+		.end	= IRQ_FIMC_IS1,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+struct platform_device exynos4_device_fimc_is = {
+	.name		= "exynos4-fimc-is",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(exynos4_fimc_is_resource),
+	.resource	= exynos4_fimc_is_resource,
+};
+#endif
+
+#if defined(CONFIG_ARCH_EXYNOS5)
+static struct resource exynos5_fimc_is_resource[] = {
+	[0] = {
+		.start	= EXYNOS5_PA_FIMC_IS,
+		.end	= EXYNOS5_PA_FIMC_IS + SZ_2M + SZ_256K + SZ_128K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= IRQ_ARMISP_GIC,
+		.end	= IRQ_ARMISP_GIC,
+		.flags	= IORESOURCE_IRQ,
+	},
+	[2] = {
+		.start	= IRQ_ISP_GIC,
+		.end	= IRQ_ISP_GIC,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+struct platform_device exynos5_device_fimc_is = {
+	.name		= "exynos5-fimc-is",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(exynos5_fimc_is_resource),
+	.resource	= exynos5_fimc_is_resource,
+};
+#endif
+
+struct exynos4_platform_fimc_is exynos4_fimc_is_default_data __initdata = {
+	.hw_ver = 15,
+};
+
+#if defined(CONFIG_ARCH_EXYNOS4)
+void __init exynos4_fimc_is_set_platdata(struct exynos4_platform_fimc_is *pd)
+{
+	struct exynos4_platform_fimc_is *npd;
+
+	if (!pd)
+		pd = &exynos4_fimc_is_default_data;
+
+	npd = kmemdup(pd, sizeof(struct exynos4_platform_fimc_is), GFP_KERNEL);
+
+	if (!npd) {
+		printk(KERN_ERR "%s: no memory for platform data\n", __func__);
+	} else {
+		if (!npd->cfg_gpio)
+			npd->cfg_gpio = exynos_fimc_is_cfg_gpio;
+		if (!npd->clk_cfg)
+			npd->clk_cfg = exynos_fimc_is_cfg_clk;
+		if (!npd->clk_on)
+			npd->clk_on = exynos_fimc_is_clk_on;
+		if (!npd->clk_off)
+			npd->clk_off = exynos_fimc_is_clk_off;
+		if (!npd->clk_get)
+			npd->clk_get = exynos_fimc_is_clk_get;
+		if (!npd->clk_put)
+			npd->clk_put = exynos_fimc_is_clk_put;
+
+		exynos4_device_fimc_is.dev.platform_data = npd;
+	}
+}
+#endif
+
+#if defined(CONFIG_ARCH_EXYNOS5)
+void __init exynos5_fimc_is_set_platdata(struct exynos5_platform_fimc_is *pd)
+{
+	struct exynos5_platform_fimc_is *npd;
+
+	if (!pd)
+		pd = (struct exynos5_platform_fimc_is *)&exynos4_fimc_is_default_data;
+
+	npd = kmemdup(pd, sizeof(struct exynos5_platform_fimc_is), GFP_KERNEL);
+
+	if (!npd) {
+		printk(KERN_ERR "%s: no memory for platform data\n", __func__);
+	} else {
+
+		if (!npd->cfg_gpio)
+			npd->cfg_gpio = exynos5_fimc_is_cfg_gpio;
+		if (!npd->clk_cfg)
+			npd->clk_cfg = exynos5_fimc_is_cfg_clk;
+		if (!npd->clk_on)
+			npd->clk_on = exynos5_fimc_is_clk_on;
+		if (!npd->clk_off)
+			npd->clk_off = exynos5_fimc_is_clk_off;
+
+		exynos5_device_fimc_is.dev.platform_data = npd;
+	}
+}
+#endif
diff --git a/arch/arm/mach-exynos/dev-fimc-lite.c b/arch/arm/mach-exynos/dev-fimc-lite.c
new file mode 100644
index 0000000..9187566
--- /dev/null
+++ b/arch/arm/mach-exynos/dev-fimc-lite.c
@@ -0,0 +1,85 @@
+/* linux/arch/arm/plat-s5p/dev-fimc-lite.c
+ *
+ * Copyright (c) 2011 Samsung Electronics
+ *
+ * Base S5P FIMC-Lite resource and device definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <mach/map.h>
+#include <media/exynos_flite.h>
+
+static struct resource exynos_flite0_resource[] = {
+	[0] = {
+		.start	= EXYNOS_PA_FIMC_LITE0,
+		.end	= EXYNOS_PA_FIMC_LITE0 + SZ_4K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= IRQ_FIMC_LITE0,
+		.end	= IRQ_FIMC_LITE0,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+struct platform_device exynos_device_flite0 = {
+	.name		= "exynos-fimc-lite",
+	.id		= 0,
+	.num_resources	= ARRAY_SIZE(exynos_flite0_resource),
+	.resource	= exynos_flite0_resource,
+};
+
+static struct resource exynos_flite1_resource[] = {
+	[0] = {
+		.start	= EXYNOS_PA_FIMC_LITE1,
+		.end	= EXYNOS_PA_FIMC_LITE1 + SZ_4K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= IRQ_FIMC_LITE1,
+		.end	= IRQ_FIMC_LITE1,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+struct platform_device exynos_device_flite1 = {
+	.name		= "exynos-fimc-lite",
+	.id		= 1,
+	.num_resources	= ARRAY_SIZE(exynos_flite1_resource),
+	.resource	= exynos_flite1_resource,
+};
+
+#ifdef CONFIG_ARCH_EXYNOS5
+static struct resource exynos_flite2_resource[] = {
+	[0] = {
+		.start	= EXYNOS_PA_FIMC_LITE2,
+		.end	= EXYNOS_PA_FIMC_LITE2 + SZ_4K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= IRQ_FIMC_LITE2,
+		.end	= IRQ_FIMC_LITE2,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+struct platform_device exynos_device_flite2 = {
+	.name		= "exynos-fimc-lite",
+	.id		= 2,
+	.num_resources	= ARRAY_SIZE(exynos_flite2_resource),
+	.resource	= exynos_flite2_resource,
+};
+#endif
+
+struct exynos_platform_flite exynos_flite0_default_data __initdata;
+struct exynos_platform_flite exynos_flite1_default_data __initdata;
+#ifdef CONFIG_ARCH_EXYNOS5
+struct exynos_platform_flite exynos_flite2_default_data __initdata;
+#endif
diff --git a/arch/arm/mach-exynos/dev-gsc.c b/arch/arm/mach-exynos/dev-gsc.c
new file mode 100644
index 0000000..bb6403d
--- /dev/null
+++ b/arch/arm/mach-exynos/dev-gsc.c
@@ -0,0 +1,123 @@
+/* linux/arch/arm/mach-exynos/dev-gsc.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Base G-Scaler resource and device definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <media/exynos_gscaler.h>
+#include <plat/devs.h>
+#include <mach/map.h>
+
+static u64 exynos5_gsc_dma_mask = DMA_BIT_MASK(32);
+
+static struct resource exynos5_gsc0_resource[] = {
+	[0] = {
+		.start	= EXYNOS5_PA_GSC0,
+		.end	= EXYNOS5_PA_GSC0 + SZ_4K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= IRQ_GSC0,
+		.end	= IRQ_GSC0,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+struct platform_device exynos5_device_gsc0 = {
+	.name		= "exynos-gsc",
+	.id		= 0,
+	.num_resources	= ARRAY_SIZE(exynos5_gsc0_resource),
+	.resource	= exynos5_gsc0_resource,
+	.dev		= {
+		.dma_mask		= &exynos5_gsc_dma_mask,
+		.coherent_dma_mask	= DMA_BIT_MASK(32),
+	},
+};
+
+static struct resource exynos5_gsc1_resource[] = {
+	[0] = {
+		.start	= EXYNOS5_PA_GSC1,
+		.end	= EXYNOS5_PA_GSC1 + SZ_4K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= IRQ_GSC1,
+		.end	= IRQ_GSC1,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+struct platform_device exynos5_device_gsc1 = {
+	.name		= "exynos-gsc",
+	.id		= 1,
+	.num_resources	= ARRAY_SIZE(exynos5_gsc1_resource),
+	.resource	= exynos5_gsc1_resource,
+	.dev		= {
+		.dma_mask		= &exynos5_gsc_dma_mask,
+		.coherent_dma_mask	= DMA_BIT_MASK(32),
+	},
+};
+
+static struct resource exynos5_gsc2_resource[] = {
+	[0] = {
+		.start	= EXYNOS5_PA_GSC2,
+		.end	= EXYNOS5_PA_GSC2 + SZ_4K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= IRQ_GSC2,
+		.end	= IRQ_GSC2,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+struct platform_device exynos5_device_gsc2 = {
+	.name		= "exynos-gsc",
+	.id		= 2,
+	.num_resources	= ARRAY_SIZE(exynos5_gsc2_resource),
+	.resource	= exynos5_gsc2_resource,
+	.dev		= {
+		.dma_mask		= &exynos5_gsc_dma_mask,
+		.coherent_dma_mask	= DMA_BIT_MASK(32),
+	},
+};
+
+static struct resource exynos5_gsc3_resource[] = {
+	[0] = {
+		.start	= EXYNOS5_PA_GSC3,
+		.end	= EXYNOS5_PA_GSC3 + SZ_4K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= IRQ_GSC3,
+		.end	= IRQ_GSC3,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+struct platform_device exynos5_device_gsc3 = {
+	.name		= "exynos-gsc",
+	.id		= 3,
+	.num_resources	= ARRAY_SIZE(exynos5_gsc3_resource),
+	.resource	= exynos5_gsc3_resource,
+	.dev		= {
+		.dma_mask		= &exynos5_gsc_dma_mask,
+		.coherent_dma_mask	= DMA_BIT_MASK(32),
+	},
+};
+
+struct exynos_platform_gscaler exynos_gsc0_default_data __initdata;
+struct exynos_platform_gscaler exynos_gsc1_default_data __initdata;
+struct exynos_platform_gscaler exynos_gsc2_default_data __initdata;
+struct exynos_platform_gscaler exynos_gsc3_default_data __initdata;
diff --git a/arch/arm/mach-exynos/dev-ion.c b/arch/arm/mach-exynos/dev-ion.c
new file mode 100644
index 0000000..8d84b33
--- /dev/null
+++ b/arch/arm/mach-exynos/dev-ion.c
@@ -0,0 +1,46 @@
+/* linux/arch/arm/mach-exynos/dev-ion.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/ion.h>
+#include <linux/slab.h>
+#include <mach/exynos-ion.h>
+
+struct platform_device exynos_device_ion = {
+	.name		= "ion-exynos",
+	.id		= -1,
+};
+
+void __init exynos_ion_set_platdata(void)
+{
+	struct ion_platform_data *pdata;
+	pdata = kzalloc(sizeof(struct ion_platform_data)
+			+ 5 * sizeof(struct ion_platform_heap), GFP_KERNEL);
+	if (pdata) {
+		pdata->nr = 5;
+		pdata->heaps[0].type = ION_HEAP_TYPE_SYSTEM;
+		pdata->heaps[0].name = "ion_noncontig_heap";
+		pdata->heaps[0].id = ION_HEAP_TYPE_SYSTEM;
+		pdata->heaps[1].type = ION_HEAP_TYPE_SYSTEM_CONTIG;
+		pdata->heaps[1].name = "ion_contig_heap";
+		pdata->heaps[1].id = ION_HEAP_TYPE_SYSTEM_CONTIG;
+		pdata->heaps[2].type = ION_HEAP_TYPE_EXYNOS;
+		pdata->heaps[2].name = "exynos_noncontig_heap";
+		pdata->heaps[2].id = ION_HEAP_TYPE_EXYNOS;
+		pdata->heaps[3].type = ION_HEAP_TYPE_EXYNOS_CONTIG;
+		pdata->heaps[3].name = "exynos_contig_heap";
+		pdata->heaps[3].id = ION_HEAP_TYPE_EXYNOS_CONTIG;
+		pdata->heaps[4].type = ION_HEAP_TYPE_EXYNOS_USER;
+		pdata->heaps[4].name = "exynos_user_heap";
+		pdata->heaps[4].id = ION_HEAP_TYPE_EXYNOS_USER;
+		exynos_device_ion.dev.platform_data = pdata;
+	}
+}
diff --git a/arch/arm/mach-exynos/dev-pd-exynos4.c b/arch/arm/mach-exynos/dev-pd-exynos4.c
new file mode 100644
index 0000000..670d425
--- /dev/null
+++ b/arch/arm/mach-exynos/dev-pd-exynos4.c
@@ -0,0 +1,255 @@
+/* linux/arch/arm/mach-exynos/dev-pd-exynos4.c
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS4 - Power Domain support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+
+#include <mach/regs-pmu.h>
+#include <mach/regs-clock.h>
+
+#include <plat/pd.h>
+
+static u32 exynos_pd_status[8];
+
+static int exynos_pd_save(struct device *dev)
+{
+	struct samsung_pd_info *pdata = dev->platform_data;
+	struct platform_device *pdev = to_platform_device(dev);
+	int ret = 0;
+
+	exynos_pd_status[pdev->id] = __raw_readl(pdata->base + 0x4);
+	exynos_pd_status[pdev->id] &= S5P_INT_LOCAL_PWR_EN;
+
+#if !defined(CONFIG_CPU_EXYNOS4210)
+	pr_debug("%s: %s(%d) exynos4_pd_status = 0x%08x\n",
+		__func__, pdev->name, pdev->id, exynos_pd_status[pdev->id]);
+#endif
+
+	if (exynos_pd_status[pdev->id] == S5P_INT_LOCAL_PWR_EN)
+		ret = exynos_pd_disable(dev);
+
+#if !defined(CONFIG_CPU_EXYNOS4210)
+	pr_debug("%s: %s(%d) exynos4 pd status reg = 0x%08x\n",
+		__func__, pdev->name, pdev->id, __raw_readl(pdata->base + 0x4));
+#endif
+
+	return ret;
+}
+
+static int exynos_pd_restore(struct device *dev)
+{
+	struct samsung_pd_info *pdata = dev->platform_data;
+	struct platform_device *pdev = to_platform_device(dev);
+	int ret = 0;
+
+#if !defined(CONFIG_CPU_EXYNOS4210)
+	pr_debug("%s: %s(%d) exynos4_pd_status = 0x%08x\n",
+		__func__, pdev->name, pdev->id, exynos_pd_status[pdev->id]);
+#endif
+
+	if (exynos_pd_status[pdev->id] == S5P_INT_LOCAL_PWR_EN)
+		ret =  exynos_pd_enable(dev);
+
+	exynos_pd_status[pdev->id] = 0;
+
+#if !defined(CONFIG_CPU_EXYNOS4210)
+	pr_debug("%s: %s(%d) exynos4 pd status reg = 0x%08x\n",
+		__func__, pdev->name, pdev->id, __raw_readl(pdata->base + 0x4));
+#endif
+
+	return ret;
+}
+
+struct platform_device exynos4_device_pd[] = {
+	[PD_MFC] = {
+		.name		= "samsung-pd",
+		.id		= PD_MFC,
+		.dev = {
+			.platform_data = &(struct samsung_pd_info) {
+				.init		= exynos_pd_init,
+				.enable		= exynos_pd_enable,
+				.disable	= exynos_pd_disable,
+				.save		= exynos_pd_save,
+				.restore	= exynos_pd_restore,
+				.base		= S5P_PMU_MFC_CONF,
+				.data		= &(struct exynos_pd_data) {
+					.clk_base	= EXYNOS4_CLKGATE_IP_MFC,
+					.read_phy_addr	= EXYNOS4_PA_MFC,
+				},
+			},
+		},
+	},
+	[PD_G3D] = {
+		.name		= "samsung-pd",
+		.id		= PD_G3D,
+		.dev = {
+			.platform_data = &(struct samsung_pd_info) {
+				.init		= exynos_pd_init,
+				.enable		= exynos_pd_enable,
+				.disable	= exynos_pd_disable,
+				.save		= exynos_pd_save,
+				.restore	= exynos_pd_restore,
+				.base		= S5P_PMU_G3D_CONF,
+				.data		= &(struct exynos_pd_data) {
+					.clk_base	= EXYNOS4_CLKGATE_IP_G3D,
+					.read_phy_addr	= EXYNOS4_PA_G3D,
+				},
+			},
+		},
+	},
+	[PD_LCD0] = {
+		.name		= "samsung-pd",
+		.id		= PD_LCD0,
+		.dev = {
+			.platform_data = &(struct samsung_pd_info) {
+				.init		= exynos_pd_init,
+				.enable		= exynos_pd_enable,
+				.disable	= exynos_pd_disable,
+				.save		= exynos_pd_save,
+				.restore	= exynos_pd_restore,
+				.base		= S5P_PMU_LCD0_CONF,
+				.data		= &(struct exynos_pd_data) {
+					.clk_base	= EXYNOS4_CLKGATE_IP_LCD0,
+					.read_phy_addr	= EXYNOS4_PA_FIMD0,
+				},
+			},
+		},
+	},
+	[PD_LCD1] = {
+		.name		= "samsung-pd",
+		.id		= PD_LCD1,
+		.dev = {
+			.platform_data = &(struct samsung_pd_info) {
+				.init		= exynos_pd_init,
+				.enable		= exynos_pd_enable,
+				.disable	= exynos_pd_disable,
+				.save		= exynos_pd_save,
+				.restore	= exynos_pd_restore,
+				.base		= S5P_PMU_LCD1_CONF,
+				.data		= &(struct exynos_pd_data) {
+					.clk_base	= EXYNOS4_CLKGATE_IP_LCD1,
+					.read_phy_addr	= EXYNOS4_PA_FIMD1,
+				},
+			},
+		},
+	},
+	[PD_TV] = {
+		.name		= "samsung-pd",
+		.id		= PD_TV,
+		.dev = {
+			.platform_data = &(struct samsung_pd_info) {
+				.init		= exynos_pd_init,
+				.enable		= exynos_pd_enable,
+				.disable	= exynos_pd_disable,
+				.save		= exynos_pd_save,
+				.restore	= exynos_pd_restore,
+				.base		= S5P_PMU_TV_CONF,
+				.data		= &(struct exynos_pd_data) {
+					.clk_base	= EXYNOS4_CLKGATE_IP_TV,
+					.read_phy_addr	= EXYNOS4_PA_VP,
+				},
+			},
+		},
+	},
+	[PD_CAM] = {
+		.name		= "samsung-pd",
+		.id		= PD_CAM,
+		.dev = {
+			.platform_data = &(struct samsung_pd_info) {
+				.init		= exynos_pd_init,
+				.enable		= exynos_pd_enable,
+				.disable	= exynos_pd_disable,
+				.save		= exynos_pd_save,
+				.restore	= exynos_pd_restore,
+				.base		= S5P_PMU_CAM_CONF,
+				.data		= &(struct exynos_pd_data) {
+					.clk_base	= EXYNOS4_CLKGATE_IP_CAM,
+					.read_phy_addr	= EXYNOS4_PA_FIMC0,
+				},
+			},
+		},
+	},
+	[PD_GPS] = {
+		.name		= "samsung-pd",
+		.id		= PD_GPS,
+		.dev = {
+			.platform_data = &(struct samsung_pd_info) {
+				.init		= exynos_pd_init,
+				.enable		= exynos_pd_enable,
+				.disable	= exynos_pd_disable,
+				.save		= exynos_pd_save,
+				.restore	= exynos_pd_restore,
+				.base		= S5P_PMU_GPS_CONF,
+				.data		= &(struct exynos_pd_data) {
+					.clk_base	= EXYNOS4_CLKGATE_IP_GPS,
+					.read_phy_addr	= EXYNOS4_PA_GPS,
+				},
+			},
+		},
+	},
+	[PD_GPS_ALIVE] = {
+		.name		= "samsung-pd",
+		.id		= PD_GPS_ALIVE,
+		.dev = {
+			.platform_data = &(struct samsung_pd_info) {
+				.init		= exynos_pd_init,
+				.enable		= exynos_pd_enable,
+				.disable	= exynos_pd_disable,
+				.save		= exynos_pd_save,
+				.restore	= exynos_pd_restore,
+				.base		= S5P_PMU_GPS_ALIVE_CONF,
+				.data		= &(struct exynos_pd_data) {
+					.clk_base	= (void __iomem *)NULL,
+					.read_phy_addr	= (unsigned long)NULL,
+				},
+			},
+		},
+	}, 
+	[PD_ISP] = {
+		.name		= "samsung-pd",
+		.id		= PD_ISP,
+		.dev = {
+			.platform_data = &(struct samsung_pd_info) {
+				.init		= exynos_pd_init,
+				.enable		= exynos_pd_enable,
+				.disable	= exynos_pd_disable,
+				.save		= exynos_pd_save,
+				.restore	= exynos_pd_restore,
+				.base		= S5P_PMU_ISP_CONF,
+				.data		= &(struct exynos_pd_data) {
+					.clk_base	= EXYNOS4_CLKGATE_IP_ISP,
+					.read_phy_addr	= EXYNOS4_PA_FIMC_IS,
+				},
+			},
+		},
+	}, 
+	[PD_MAUDIO] = {
+		.name		= "samsung-pd",
+		.id		= PD_MAUDIO,
+		.dev = {
+			.platform_data = &(struct samsung_pd_info) {
+				.init		= exynos_pd_init,
+				.enable		= exynos_pd_enable,
+				.disable	= exynos_pd_disable,
+				.save		= exynos_pd_save,
+				.restore	= exynos_pd_restore,
+				.base		= S5P_PMU_MAUDIO_CONF,
+				.data		= &(struct exynos_pd_data) {
+					.clk_base	= EXYNOS4_CLKGATE_IP_MAUDIO,
+					.read_phy_addr	= EXYNOS4_PA_AUDSS,
+				},
+			},
+		},
+	}, 
+};
diff --git a/arch/arm/mach-exynos/dev-pd-exynos5.c b/arch/arm/mach-exynos/dev-pd-exynos5.c
new file mode 100644
index 0000000..ee3768c
--- /dev/null
+++ b/arch/arm/mach-exynos/dev-pd-exynos5.c
@@ -0,0 +1,120 @@
+/* linux/arch/arm/mach-exynos/dev-pd-exynos5.c
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS5 - Power Domain support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+
+#include <mach/regs-pmu5.h>
+#include <mach/regs-clock.h>
+
+#include <plat/pd.h>
+
+struct platform_device exynos5_device_pd[] = {
+	[PD_MFC] = {
+		.name		= "samsung-pd",
+		.id		= PD_MFC,
+		.dev = {
+			.platform_data = &(struct samsung_pd_info) {
+				.init		= exynos_pd_init,
+				.enable		= exynos_pd_enable,
+				.disable	= exynos_pd_disable,
+				.base		= EXYNOS5_MFC_CONFIGURATION,
+				.data		= &(struct exynos_pd_data) {
+					.clk_base	= EXYNOS5_CLKGATE_IP_MFC,
+					.clksrc_base	= EXYNOS5_CLKSRC_TOP3,
+				},
+			},
+		},
+	},
+	[PD_G3D] = {
+		.name		= "samsung-pd",
+		.id		= PD_G3D,
+		.dev = {
+			.platform_data = &(struct samsung_pd_info) {
+				.init		= exynos_pd_init,
+				.enable		= exynos_pd_enable,
+				.disable	= exynos_pd_disable,
+				.base		= EXYNOS5_G3D_CONFIGURATION,
+				.data		= &(struct exynos_pd_data) {
+					.clk_base	= EXYNOS5_CLKGATE_IP_G3D,
+					.clksrc_base	= EXYNOS5_CLKSRC_TOP3,
+				},
+			},
+		},
+	},
+	[PD_GPS] = {
+		.name		= "samsung-pd",
+		.id		= PD_GPS,
+		.dev = {
+			.platform_data = &(struct samsung_pd_info) {
+				.init		= exynos_pd_init,
+				.enable		= exynos_pd_enable,
+				.disable	= exynos_pd_disable,
+				.base		= EXYNOS5_GPS_CONFIGURATION,
+				.data		= &(struct exynos_pd_data) {
+					.clk_base	= EXYNOS5_CLKGATE_IP_GPS,
+					.clksrc_base	= EXYNOS5_CLKSRC_TOP3,
+				},
+			},
+		},
+	},
+	[PD_ISP] = {
+		.name		= "samsung-pd",
+		.id		= PD_ISP,
+		.dev = {
+			.platform_data = &(struct samsung_pd_info) {
+				.init		= exynos_pd_init,
+				.enable		= exynos_pd_enable,
+				.disable	= exynos_pd_disable,
+				.base		= EXYNOS5_ISP_CONFIGURATION,
+				.data		= &(struct exynos_pd_data) {
+					.clk_base	= NULL,
+					.clksrc_base	= EXYNOS5_CLKSRC_TOP3,
+				},
+			},
+		},
+	},
+	[PD_GSCL] = {
+		.name		= "samsung-pd",
+		.id		= PD_GSCL,
+		.dev = {
+			.platform_data = &(struct samsung_pd_info) {
+				.init		= exynos_pd_init,
+				.enable		= exynos_pd_enable,
+				.disable	= exynos_pd_disable,
+				.base		= EXYNOS5_GSCL_CONFIGURATION,
+				.data		= &(struct exynos_pd_data) {
+					.clk_base	= EXYNOS5_CLKGATE_IP_GSCL,
+					.clksrc_base	= EXYNOS5_CLKSRC_TOP3,
+				},
+			},
+		},
+	},
+	[PD_DISP1] = {
+		.name		= "samsung-pd",
+		.id		= PD_DISP1,
+		.dev = {
+			.platform_data = &(struct samsung_pd_info) {
+				.init		= exynos_pd_init,
+				.enable		= exynos_pd_enable,
+				.disable	= exynos_pd_disable,
+				.base		= EXYNOS5_DISP1_CONFIGURATION,
+				.data		= &(struct exynos_pd_data) {
+					.clk_base	= EXYNOS5_CLKGATE_IP_DISP1,
+					.clksrc_base	= EXYNOS5_CLKSRC_TOP3,
+				},
+			},
+		},
+	},
+};
diff --git a/arch/arm/mach-exynos/dev-pd.c b/arch/arm/mach-exynos/dev-pd.c
new file mode 100644
index 0000000..2441fe6
--- /dev/null
+++ b/arch/arm/mach-exynos/dev-pd.c
@@ -0,0 +1,167 @@
+/* linux/arch/arm/mach-exynos/dev-pd.c
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS4 - Power Domain support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+
+#include <mach/regs-pmu.h>
+#include <mach/regs-pmu5.h>
+#include <mach/regs-clock.h>
+
+#include <plat/cpu.h>
+#include <plat/pd.h>
+#include <plat/bts.h>
+
+int exynos_pd_init(struct device *dev)
+{
+	struct samsung_pd_info *pdata =  dev->platform_data;
+	struct exynos_pd_data *data = (struct exynos_pd_data *) pdata->data;
+
+	if (soc_is_exynos4210() && data->read_phy_addr) {
+		data->read_base = ioremap(data->read_phy_addr, SZ_4K);
+		if (!data->read_base)
+			return -ENOMEM;
+	}
+
+	return 0;
+}
+
+int exynos_pd_enable(struct device *dev)
+{
+	struct samsung_pd_info *pdata =  dev->platform_data;
+	struct exynos_pd_data *data = (struct exynos_pd_data *) pdata->data;
+	u32 timeout;
+	u32 tmp = 0;
+
+	/*  save IP clock gating register */
+	if (data->clk_base) {
+		tmp = __raw_readl(data->clk_base);
+
+		/*  enable all the clocks of IPs in the power domain */
+		__raw_writel(0xffffffff, data->clk_base);
+	}
+
+	__raw_writel(S5P_INT_LOCAL_PWR_EN, pdata->base);
+
+	/* Wait max 1ms */
+	timeout = 1000;
+	while ((__raw_readl(pdata->base + 0x4) & S5P_INT_LOCAL_PWR_EN)
+	       != S5P_INT_LOCAL_PWR_EN) {
+		if (timeout == 0) {
+			printk(KERN_ERR "Power domain %s enable failed.\n",
+			       dev_name(dev));
+			return -ETIMEDOUT;
+		}
+		timeout--;
+		udelay(1);
+	}
+
+	if (data->read_base)
+		/* dummy read to check the completion of power-on sequence */
+		__raw_readl(data->read_base);
+
+	/* restore IP clock gating register */
+	if (data->clk_base)
+		__raw_writel(tmp, data->clk_base);
+
+	bts_enable(pdata->id);
+	return 0;
+}
+
+int exynos_pd_disable(struct device *dev)
+{
+	struct samsung_pd_info *pdata =  dev->platform_data;
+	struct exynos_pd_data *data = (struct exynos_pd_data *) pdata->data;
+	u32 timeout;
+	u32 tmp = 0;
+
+	static int boot_lcd0 = 1;
+	if (boot_lcd0) {
+		struct platform_device *pdev = to_platform_device(dev);
+		/*
+		 * Currently,in exynos4x12, FIMD parent power domain
+		 * is PD_LCD0,
+		 * but in exynos5x12, it is changed to PD_DISP1.
+		 * so i add PD_DISP1 for exynos5
+		 */
+		if ((pdev->id == PD_LCD0) || (pdev->id == PD_DISP1)) {
+			printk(KERN_INFO "lcd0 disable skip only one time");
+			boot_lcd0--;
+			return 0;
+		}
+	}
+
+	/*  save clock source register */
+	if (data->clksrc_base)
+		tmp = __raw_readl(data->clksrc_base);
+#ifdef CONFIG_EXYNOS5_LOWPWR_IDLE
+	if (soc_is_exynos5250() &&
+		(pdata->base == EXYNOS5_ISP_CONFIGURATION))
+		return 0;
+#endif
+	/* Do not disable MFC power domain for EXYNOS5250 EVT0 */
+	if (soc_is_exynos5250() &&
+		(samsung_rev() < EXYNOS5250_REV_1_0) &&
+		(pdata->base == EXYNOS5_MFC_CONFIGURATION))
+		return 0;
+
+	/*
+	 * To ISP power domain off,
+	 * first, ISP_ARM power domain be off.
+	 */
+	if (soc_is_exynos5250() &&
+		(pdata->base == EXYNOS5_ISP_CONFIGURATION)) {
+		if (!(__raw_readl(EXYNOS5_ISP_ARM_STATUS) & 0x1)) {
+			/* Disable ISP_ARM */
+			timeout = __raw_readl(EXYNOS5_ISP_ARM_OPTION);
+			timeout &= ~EXYNOS5_ISP_ARM_ENABLE;
+			__raw_writel(timeout, EXYNOS5_ISP_ARM_OPTION);
+
+			/* ISP_ARM power off */
+			__raw_writel(0x0, EXYNOS5_ISP_ARM_CONFIGURATION);
+
+			timeout = 1000;
+
+			while (__raw_readl(EXYNOS5_ISP_ARM_STATUS) & 0x1) {
+				if (timeout == 0) {
+					printk(KERN_ERR "ISP_ARM power domain can not off\n");
+					return -ETIMEDOUT;
+				}
+				timeout--;
+				udelay(1);
+			}
+			/* CMU_RESET_ISP_ARM off */
+			__raw_writel(0x0, EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG);
+		}
+	}
+
+	__raw_writel(0, pdata->base);
+
+	/* Wait max 1ms */
+	timeout = 1000;
+	while (__raw_readl(pdata->base + 0x4) & S5P_INT_LOCAL_PWR_EN) {
+		if (timeout == 0) {
+			printk(KERN_ERR "Power domain %s disable failed.\n",
+			       dev_name(dev));
+			return -ETIMEDOUT;
+		}
+		timeout--;
+		udelay(1);
+	}
+
+	/* restore clock source register */
+	if (data->clksrc_base)
+		__raw_writel(tmp, data->clksrc_base);
+	return 0;
+}
diff --git a/arch/arm/mach-exynos/dev-spi.c b/arch/arm/mach-exynos/dev-spi.c
new file mode 100644
index 0000000..0807d3d
--- /dev/null
+++ b/arch/arm/mach-exynos/dev-spi.c
@@ -0,0 +1,308 @@
+/* linux/arch/arm/mach-exynos/dev-spi.c
+ *
+ * Copyright (C) 2010 Samsung Electronics Co. Ltd.
+ *	Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/clk.h>
+
+#include <mach/irqs.h>
+#include <mach/dma.h>
+#include <mach/map.h>
+#include <mach/gpio.h>
+#include <mach/spi-clocks.h>
+#include <mach/regs-clock.h>
+
+#include <plat/s3c64xx-spi.h>
+#include <plat/gpio-cfg.h>
+#include <plat/irqs.h>
+
+static char *spi_src_clks[] = {
+	[EXYNOS_SPI_SRCCLK_SCLK] = "sclk_spi",
+};
+
+/* SPI Controller platform_devices */
+
+/* Since we emulate multi-cs capability, we do not touch the CS.
+ * The emulated CS is toggled by board specific mechanism, as it can
+ * be either some immediate GPIO or some signal out of some other
+ * chip in between ... or some yet another way.
+ * We simply do not assume anything about CS.
+ */
+#if defined(CONFIG_ARCH_EXYNOS5)
+static int exynos_spi_cfg_gpio(struct platform_device *pdev)
+{
+	int gpio;
+
+	switch (pdev->id) {
+	case 0:
+		s3c_gpio_cfgpin(EXYNOS5_GPA2(0), S3C_GPIO_SFN(2));
+		s3c_gpio_cfgpin(EXYNOS5_GPA2(2), S3C_GPIO_SFN(2));
+		s3c_gpio_cfgpin(EXYNOS5_GPA2(3), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(EXYNOS5_GPA2(0), S3C_GPIO_PULL_UP);
+		s3c_gpio_setpull(EXYNOS5_GPA2(2), S3C_GPIO_PULL_UP);
+		s3c_gpio_setpull(EXYNOS5_GPA2(3), S3C_GPIO_PULL_UP);
+
+		for (gpio = EXYNOS5_GPA2(0); gpio < EXYNOS5_GPA2(4); gpio++)
+			s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV3);
+
+		break;
+
+	case 1:
+		s3c_gpio_cfgpin(EXYNOS5_GPA2(4), S3C_GPIO_SFN(2));
+		s3c_gpio_cfgpin(EXYNOS5_GPA2(6), S3C_GPIO_SFN(2));
+		s3c_gpio_cfgpin(EXYNOS5_GPA2(7), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(EXYNOS5_GPA2(4), S3C_GPIO_PULL_UP);
+		s3c_gpio_setpull(EXYNOS5_GPA2(6), S3C_GPIO_PULL_UP);
+		s3c_gpio_setpull(EXYNOS5_GPA2(7), S3C_GPIO_PULL_UP);
+
+		for (gpio = EXYNOS5_GPA2(4); gpio < EXYNOS5_GPA2(8); gpio++)
+			s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV3);
+
+		break;
+
+	case 2:
+		s3c_gpio_cfgpin(EXYNOS5_GPB1(1), S3C_GPIO_SFN(5));
+		s3c_gpio_cfgpin(EXYNOS5_GPB1(3), S3C_GPIO_SFN(5));
+		s3c_gpio_cfgpin(EXYNOS5_GPB1(4), S3C_GPIO_SFN(5));
+		s3c_gpio_setpull(EXYNOS5_GPB1(1), S3C_GPIO_PULL_UP);
+		s3c_gpio_setpull(EXYNOS5_GPB1(3), S3C_GPIO_PULL_UP);
+		s3c_gpio_setpull(EXYNOS5_GPB1(4), S3C_GPIO_PULL_UP);
+
+		for (gpio = EXYNOS5_GPB1(1); gpio < EXYNOS5_GPB1(5); gpio++)
+			s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV3);
+
+		break;
+
+	default:
+		dev_err(&pdev->dev, "Invalid SPI Controller number!");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+#else
+static int exynos_spi_cfg_gpio(struct platform_device *pdev)
+{
+	int gpio;
+
+	switch (pdev->id) {
+	case 0:
+		s3c_gpio_cfgpin(EXYNOS4_GPB(0), S3C_GPIO_SFN(2));
+		s3c_gpio_cfgpin(EXYNOS4_GPB(2), S3C_GPIO_SFN(2));
+		s3c_gpio_cfgpin(EXYNOS4_GPB(3), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(EXYNOS4_GPB(0), S3C_GPIO_PULL_UP);
+		s3c_gpio_setpull(EXYNOS4_GPB(2), S3C_GPIO_PULL_UP);
+		s3c_gpio_setpull(EXYNOS4_GPB(3), S3C_GPIO_PULL_UP);
+
+		for (gpio = EXYNOS4_GPB(0); gpio < EXYNOS4_GPB(4); gpio++)
+			s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV3);
+
+		break;
+
+	case 1:
+		s3c_gpio_cfgpin(EXYNOS4_GPB(4), S3C_GPIO_SFN(2));
+		s3c_gpio_cfgpin(EXYNOS4_GPB(6), S3C_GPIO_SFN(2));
+		s3c_gpio_cfgpin(EXYNOS4_GPB(7), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(EXYNOS4_GPB(4), S3C_GPIO_PULL_UP);
+		s3c_gpio_setpull(EXYNOS4_GPB(6), S3C_GPIO_PULL_UP);
+		s3c_gpio_setpull(EXYNOS4_GPB(7), S3C_GPIO_PULL_UP);
+
+		for (gpio = EXYNOS4_GPB(4); gpio < EXYNOS4_GPB(8); gpio++)
+			s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV3);
+
+		break;
+
+	case 2:
+		s3c_gpio_cfgpin(EXYNOS4_GPC1(1), S3C_GPIO_SFN(5));
+		s3c_gpio_cfgpin(EXYNOS4_GPC1(3), S3C_GPIO_SFN(5));
+		s3c_gpio_cfgpin(EXYNOS4_GPC1(4), S3C_GPIO_SFN(5));
+		s3c_gpio_setpull(EXYNOS4_GPC1(1), S3C_GPIO_PULL_UP);
+		s3c_gpio_setpull(EXYNOS4_GPC1(3), S3C_GPIO_PULL_UP);
+		s3c_gpio_setpull(EXYNOS4_GPC1(4), S3C_GPIO_PULL_UP);
+
+		for (gpio = EXYNOS4_GPC1(1); gpio < EXYNOS4_GPC1(5); gpio++)
+			s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV3);
+
+		break;
+
+	default:
+		dev_err(&pdev->dev, "Invalid SPI Controller number!");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+#endif
+
+static struct resource exynos_spi0_resource[] = {
+	[0] = {
+		.start = EXYNOS_PA_SPI0,
+		.end   = EXYNOS_PA_SPI0 + 0x100 - 1,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = DMACH_SPI0_TX,
+		.end   = DMACH_SPI0_TX,
+		.flags = IORESOURCE_DMA,
+	},
+	[2] = {
+		.start = DMACH_SPI0_RX,
+		.end   = DMACH_SPI0_RX,
+		.flags = IORESOURCE_DMA,
+	},
+	[3] = {
+		.start = IRQ_SPI0,
+		.end   = IRQ_SPI0,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+static struct s3c64xx_spi_info exynos_spi0_pdata = {
+	.cfg_gpio = exynos_spi_cfg_gpio,
+	.fifo_lvl_mask = 0x1ff,
+	.rx_lvl_offset = 15,
+	.high_speed = 1,
+	.clk_from_cmu = true,
+	.tx_st_done = 25,
+};
+
+static u64 spi_dmamask = DMA_BIT_MASK(32);
+
+struct platform_device exynos_device_spi0 = {
+	.name		  = "s3c64xx-spi",
+	.id		  = 0,
+	.num_resources	  = ARRAY_SIZE(exynos_spi0_resource),
+	.resource	  = exynos_spi0_resource,
+	.dev = {
+		.dma_mask		= &spi_dmamask,
+		.coherent_dma_mask	= DMA_BIT_MASK(32),
+		.platform_data = &exynos_spi0_pdata,
+	},
+};
+
+static struct resource exynos_spi1_resource[] = {
+	[0] = {
+		.start = EXYNOS_PA_SPI1,
+		.end   = EXYNOS_PA_SPI1 + 0x100 - 1,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = DMACH_SPI1_TX,
+		.end   = DMACH_SPI1_TX,
+		.flags = IORESOURCE_DMA,
+	},
+	[2] = {
+		.start = DMACH_SPI1_RX,
+		.end   = DMACH_SPI1_RX,
+		.flags = IORESOURCE_DMA,
+	},
+	[3] = {
+		.start = IRQ_SPI1,
+		.end   = IRQ_SPI1,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+static struct s3c64xx_spi_info exynos_spi1_pdata = {
+	.cfg_gpio = exynos_spi_cfg_gpio,
+	.fifo_lvl_mask = 0x7f,
+	.rx_lvl_offset = 15,
+	.high_speed = 1,
+	.clk_from_cmu = true,
+	.tx_st_done = 25,
+};
+
+struct platform_device exynos_device_spi1 = {
+	.name		  = "s3c64xx-spi",
+	.id		  = 1,
+	.num_resources	  = ARRAY_SIZE(exynos_spi1_resource),
+	.resource	  = exynos_spi1_resource,
+	.dev = {
+		.dma_mask		= &spi_dmamask,
+		.coherent_dma_mask	= DMA_BIT_MASK(32),
+		.platform_data = &exynos_spi1_pdata,
+	},
+};
+
+static struct resource exynos_spi2_resource[] = {
+	[0] = {
+		.start = EXYNOS_PA_SPI2,
+		.end   = EXYNOS_PA_SPI2 + 0x100 - 1,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = DMACH_SPI2_TX,
+		.end   = DMACH_SPI2_TX,
+		.flags = IORESOURCE_DMA,
+	},
+	[2] = {
+		.start = DMACH_SPI2_RX,
+		.end   = DMACH_SPI2_RX,
+		.flags = IORESOURCE_DMA,
+	},
+	[3] = {
+		.start = IRQ_SPI2,
+		.end   = IRQ_SPI2,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+static struct s3c64xx_spi_info exynos_spi2_pdata = {
+	.cfg_gpio = exynos_spi_cfg_gpio,
+	.fifo_lvl_mask = 0x7f,
+	.rx_lvl_offset = 15,
+	.high_speed = 1,
+	.clk_from_cmu = true,
+	.tx_st_done = 25,
+};
+
+struct platform_device exynos_device_spi2 = {
+	.name		  = "s3c64xx-spi",
+	.id		  = 2,
+	.num_resources	  = ARRAY_SIZE(exynos_spi2_resource),
+	.resource	  = exynos_spi2_resource,
+	.dev = {
+		.dma_mask		= &spi_dmamask,
+		.coherent_dma_mask	= DMA_BIT_MASK(32),
+		.platform_data = &exynos_spi2_pdata,
+	},
+};
+
+void __init exynos_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
+{
+	struct s3c64xx_spi_info *pd;
+
+	/* Reject invalid configuration */
+	if (!num_cs || src_clk_nr < 0
+			|| src_clk_nr > EXYNOS_SPI_SRCCLK_SCLK) {
+		printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
+		return;
+	}
+
+	switch (cntrlr) {
+	case 0:
+		pd = &exynos_spi0_pdata;
+		break;
+	case 1:
+		pd = &exynos_spi1_pdata;
+		break;
+	case 2:
+		pd = &exynos_spi2_pdata;
+		break;
+	default:
+		printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
+							__func__, cntrlr);
+		return;
+	}
+
+	pd->num_cs = num_cs;
+	pd->src_clk_nr = src_clk_nr;
+	pd->src_clk_name = spi_src_clks[src_clk_nr];
+}
diff --git a/arch/arm/mach-exynos/dev-sysmmu-exynos4.c b/arch/arm/mach-exynos/dev-sysmmu-exynos4.c
new file mode 100644
index 0000000..bb14b74
--- /dev/null
+++ b/arch/arm/mach-exynos/dev-sysmmu-exynos4.c
@@ -0,0 +1,130 @@
+/* linux/arch/arm/mach-exynos/dev-sysmmu.c
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS - System MMU support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+
+#include <mach/map.h>
+#include <mach/irqs.h>
+#include <mach/dev-sysmmu.h>
+#include <plat/s5p-clock.h>
+
+#if defined(CONFIG_ARCH_EXYNOS4)
+#define EXYNOS_PA_SYSMMU(ipbase) EXYNOS4_PA_SYSMMU_##ipbase
+#elif defined(CONFIG_ARCH_EXYNOS5)
+#define EXYNOS_PA_SYSMMU(ipbase) EXYNOS5_PA_SYSMMU_##ipbase
+#endif
+
+#define SYSMMU_RESOURCE(ipname, base, irq) \
+static struct resource sysmmu_resource_##ipname[] =\
+{\
+	{\
+		.start	= EXYNOS_PA_SYSMMU(base),\
+		.end	= EXYNOS_PA_SYSMMU(base) + SZ_4K - 1,\
+		.flags	= IORESOURCE_MEM,\
+	}, {\
+		.start	= IRQ_SYSMMU_##irq##_0,\
+		.end	= IRQ_SYSMMU_##irq##_0,\
+		.flags	= IORESOURCE_IRQ,\
+	},\
+}
+
+#define SYSMMU_PLATFORM_DEVICE(ipname, devid) \
+struct platform_device SYSMMU_PLATDEV(ipname) =\
+{\
+	.name		= SYSMMU_DEVNAME_BASE,\
+	.id		= devid,\
+	.num_resources	= ARRAY_SIZE(sysmmu_resource_##ipname),\
+	.resource	= sysmmu_resource_##ipname,\
+	.dev		= {\
+		.dma_mask		= &exynos_sysmmu_dma_mask,\
+		.coherent_dma_mask	= DMA_BIT_MASK(32),\
+	},\
+}
+
+static u64 exynos_sysmmu_dma_mask = DMA_BIT_MASK(32);
+
+SYSMMU_RESOURCE(sss,	SSS,	SSS);
+SYSMMU_RESOURCE(jpeg,	JPEG,	JPEG);
+SYSMMU_RESOURCE(fimd1,	FIMD1,	FIMD1);
+SYSMMU_RESOURCE(2d,	2D,	2D);
+SYSMMU_RESOURCE(rot,	ROTATOR, ROTATOR);
+SYSMMU_RESOURCE(mdma,	MDMA2,	MDMA1);
+SYSMMU_RESOURCE(tv,	TV,	TV);
+SYSMMU_RESOURCE(mfc_l,	MFC_L,	MFC_L);
+SYSMMU_RESOURCE(mfc_r,	MFC_R,	MFC_R);
+SYSMMU_RESOURCE(is_isp, ISP,	ISP);
+SYSMMU_RESOURCE(is_drc, DRC,	DRC);
+SYSMMU_RESOURCE(is_fd,	FD,	FD);
+SYSMMU_RESOURCE(is_cpu, ISPCPU, MCUISP);
+SYSMMU_RESOURCE(flite0,	LITE0,	LITE0);
+SYSMMU_RESOURCE(flite1,	LITE1,	LITE1);
+
+SYSMMU_PLATFORM_DEVICE(sss,	0);
+SYSMMU_PLATFORM_DEVICE(jpeg,	5);
+SYSMMU_PLATFORM_DEVICE(fimd1,	7);
+SYSMMU_PLATFORM_DEVICE(2d,	9);
+SYSMMU_PLATFORM_DEVICE(rot,	10);
+SYSMMU_PLATFORM_DEVICE(mdma,	11);
+SYSMMU_PLATFORM_DEVICE(tv,	12);
+SYSMMU_PLATFORM_DEVICE(mfc_l,	13);
+SYSMMU_PLATFORM_DEVICE(mfc_r,	14);
+SYSMMU_PLATFORM_DEVICE(is_isp,	16);
+SYSMMU_PLATFORM_DEVICE(is_drc,	17);
+SYSMMU_PLATFORM_DEVICE(is_fd,	18);
+SYSMMU_PLATFORM_DEVICE(is_cpu,	19);
+SYSMMU_PLATFORM_DEVICE(flite0,	30);
+SYSMMU_PLATFORM_DEVICE(flite1,	31);
+
+#ifdef CONFIG_ARCH_EXYNOS4
+SYSMMU_RESOURCE(fimc0,	FIMC0,	FIMC0);
+SYSMMU_RESOURCE(fimc1,	FIMC1,	FIMC1);
+SYSMMU_RESOURCE(fimc2,	FIMC2,	FIMC2);
+SYSMMU_RESOURCE(fimc3,	FIMC3,	FIMC3);
+SYSMMU_RESOURCE(fimd0,	FIMD0,	FIMD0);
+SYSMMU_RESOURCE(pcie,	PCIe,	PCIE);
+SYSMMU_RESOURCE(g2d_acp, G2D_ACP, 2D);
+
+SYSMMU_PLATFORM_DEVICE(fimc0,	1);
+SYSMMU_PLATFORM_DEVICE(fimc1,	2);
+SYSMMU_PLATFORM_DEVICE(fimc2,	3);
+SYSMMU_PLATFORM_DEVICE(fimc3,	4);
+SYSMMU_PLATFORM_DEVICE(fimd0,	6);
+SYSMMU_PLATFORM_DEVICE(pcie,	8);
+SYSMMU_PLATFORM_DEVICE(g2d_acp,	15);
+#endif
+
+#ifdef CONFIG_ARCH_EXYNOS5
+SYSMMU_RESOURCE(gsc0,	GSC0,	GSC0);
+SYSMMU_RESOURCE(gsc1,	GSC1,	GSC1);
+SYSMMU_RESOURCE(gsc2,	GSC2,	GSC2);
+SYSMMU_RESOURCE(gsc3,	GSC3,	GSC3);
+SYSMMU_RESOURCE(is_sclrc, SCALERC, SCALERCISP);
+SYSMMU_RESOURCE(is_sclrp, SCALERP, SCALERPISP);
+SYSMMU_RESOURCE(is_odc,	ODC,	ODC);
+SYSMMU_RESOURCE(is_dis0, DIS0,	DIS0);
+SYSMMU_RESOURCE(is_dis1, DIS1,	DIS1);
+SYSMMU_RESOURCE(is_3dnr, 3DNR,	3DNR);
+SYSMMU_RESOURCE(flite2,	LITE2,	LITE2);
+
+SYSMMU_PLATFORM_DEVICE(gsc0,	20);
+SYSMMU_PLATFORM_DEVICE(gsc1,	21);
+SYSMMU_PLATFORM_DEVICE(gsc2,	22);
+SYSMMU_PLATFORM_DEVICE(gsc3,	23);
+SYSMMU_PLATFORM_DEVICE(is_sclrc, 24);
+SYSMMU_PLATFORM_DEVICE(is_sclrp, 25);
+SYSMMU_PLATFORM_DEVICE(is_odc,	26);
+SYSMMU_PLATFORM_DEVICE(is_dis0,	27);
+SYSMMU_PLATFORM_DEVICE(is_dis1,	28);
+SYSMMU_PLATFORM_DEVICE(is_3dnr,	29);
+SYSMMU_PLATFORM_DEVICE(flite2,	32);
+#endif
diff --git a/arch/arm/mach-exynos/dev-sysmmu.c b/arch/arm/mach-exynos/dev-sysmmu.c
new file mode 100644
index 0000000..0981fba
--- /dev/null
+++ b/arch/arm/mach-exynos/dev-sysmmu.c
@@ -0,0 +1,301 @@
+/* linux/arch/arm/mach-exynos/dev-sysmmu.c
+ *
+ * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS - System MMU support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+
+#include <plat/cpu.h>
+#include <plat/pd.h>
+#include <plat/devs.h>
+
+#include <mach/map.h>
+#include <mach/irqs.h>
+#include <mach/sysmmu.h>
+
+static u64 exynos_sysmmu_dma_mask = DMA_BIT_MASK(32);
+
+/* DEFINE_RES_XXXX is defined in 3.3 kernel */
+#ifndef DEFINE_RES_NAMED
+#define DEFINE_RES_NAMED(_start, _size, _name, _flags)			\
+	{								\
+		.start = (_start),					\
+		.end = (_start) + (_size) - 1,				\
+		.name = (_name),					\
+		.flags = (_flags),					\
+	}
+
+#define DEFINE_RES_MEM_NAMED(_start, _size, _name)			\
+	DEFINE_RES_NAMED((_start), (_size), (_name), IORESOURCE_MEM)
+#define DEFINE_RES_MEM(_start, _size)					\
+	DEFINE_RES_MEM_NAMED((_start), (_size), NULL)
+
+#define DEFINE_RES_IRQ_NAMED(_irq, _name)				\
+	DEFINE_RES_NAMED((_irq), 1, (_name), IORESOURCE_IRQ)
+#define DEFINE_RES_IRQ(_irq)						\
+	DEFINE_RES_IRQ_NAMED((_irq), NULL)
+#endif /* DEFINE_RES_NAMED */
+
+#define SYSMMU_PLATFORM_DEVICE(ipname, devid)				\
+static struct sysmmu_platform_data platdata_##ipname = {		\
+	.dbgname = #ipname,						\
+};									\
+struct platform_device SYSMMU_PLATDEV(ipname) =				\
+{									\
+	.name		= SYSMMU_DEVNAME_BASE,				\
+	.id		= devid,					\
+	.dev		= {						\
+		.dma_mask		= &exynos_sysmmu_dma_mask,	\
+		.coherent_dma_mask	= DMA_BIT_MASK(32),		\
+		.platform_data		= &platdata_##ipname,		\
+	},								\
+}
+
+SYSMMU_PLATFORM_DEVICE(mfc_lr,	0);
+SYSMMU_PLATFORM_DEVICE(tv,	2);
+SYSMMU_PLATFORM_DEVICE(jpeg,	3);
+SYSMMU_PLATFORM_DEVICE(rot,	4);
+SYSMMU_PLATFORM_DEVICE(fimc0,	5); /* fimc* and gsc* exist exclusively */
+SYSMMU_PLATFORM_DEVICE(fimc1,	6);
+SYSMMU_PLATFORM_DEVICE(fimc2,	7);
+SYSMMU_PLATFORM_DEVICE(fimc3,	8);
+SYSMMU_PLATFORM_DEVICE(gsc0,	5);
+SYSMMU_PLATFORM_DEVICE(gsc1,	6);
+SYSMMU_PLATFORM_DEVICE(gsc2,	7);
+SYSMMU_PLATFORM_DEVICE(gsc3,	8);
+SYSMMU_PLATFORM_DEVICE(isp,	9);
+SYSMMU_PLATFORM_DEVICE(fimd0,	10);
+SYSMMU_PLATFORM_DEVICE(fimd1,	11);
+SYSMMU_PLATFORM_DEVICE(camif0,	12);
+SYSMMU_PLATFORM_DEVICE(camif1,	13);
+SYSMMU_PLATFORM_DEVICE(camif2,	14);
+SYSMMU_PLATFORM_DEVICE(2d,	15);
+
+#define SYSMMU_RESOURCE_NAME(core, ipname) sysmmures_##core##_##ipname
+
+#define SYSMMU_RESOURCE(core, ipname)					\
+	static struct resource SYSMMU_RESOURCE_NAME(core, ipname)[] __initdata =
+
+#define DEFINE_SYSMMU_RESOURCE(core, mem, irq)				\
+	DEFINE_RES_MEM_NAMED(core##_PA_SYSMMU_##mem, SZ_4K, #mem),	\
+	DEFINE_RES_IRQ_NAMED(core##_IRQ_SYSMMU_##irq##_0, #mem)
+
+#define SYSMMU_RESOURCE_DEFINE(core, ipname, mem, irq)			\
+	SYSMMU_RESOURCE(core, ipname) {					\
+		DEFINE_SYSMMU_RESOURCE(core, mem, irq)			\
+	}
+
+struct sysmmu_resource_map {
+	struct platform_device *pdev;
+	struct resource *res;
+	u32 rnum;
+	struct device *pdd;
+	char *clocknames;
+};
+
+#define SYSMMU_RESOURCE_MAPPING(core, ipname, resname) {		\
+	.pdev = &SYSMMU_PLATDEV(ipname),				\
+	.res = SYSMMU_RESOURCE_NAME(EXYNOS##core, resname),		\
+	.rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
+	.clocknames = SYSMMU_CLOCK_NAME,				\
+}
+
+#define SYSMMU_RESOURCE_MAPPING_MC(core, ipname, resname, pdata) {	\
+	.pdev = &SYSMMU_PLATDEV(ipname),				\
+	.res = SYSMMU_RESOURCE_NAME(EXYNOS##core, resname),		\
+	.rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
+	.clocknames = SYSMMU_CLOCK_NAME "," SYSMMU_CLOCK_NAME2,		\
+}
+
+#ifdef CONFIG_EXYNOS_DEV_PD
+#define SYSMMU_RESOURCE_MAPPING_PD(core, ipname, resname, pd) {		\
+	.pdev = &SYSMMU_PLATDEV(ipname),				\
+	.res = SYSMMU_RESOURCE_NAME(EXYNOS##core, resname),		\
+	.rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
+	.clocknames = SYSMMU_CLOCK_NAME,				\
+	.pdd = &exynos##core##_device_pd[pd].dev,			\
+}
+
+#define SYSMMU_RESOURCE_MAPPING_MCPD(core, ipname, resname, pd, pdata) {\
+	.pdev = &SYSMMU_PLATDEV(ipname),				\
+	.res = SYSMMU_RESOURCE_NAME(EXYNOS##core, resname),		\
+	.rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
+	.clocknames = SYSMMU_CLOCK_NAME "," SYSMMU_CLOCK_NAME2,		\
+	.pdd = &exynos##core##_device_pd[pd].dev,			\
+}
+#else
+#define SYSMMU_RESOURCE_MAPPING_PD(core, ipname, resname, pd)		\
+		SYSMMU_RESOURCE_MAPPING(core, ipname, resname)
+#define SYSMMU_RESOURCE_MAPPING_MCPD(core, ipname, resname, pd, pdata)	\
+		SYSMMU_RESOURCE_MAPPING_MC(core, ipname, resname, pdata)
+
+#endif /* CONFIG_EXYNOS_DEV_PD */
+
+#ifdef CONFIG_ARCH_EXYNOS4
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc0,	FIMC0,	FIMC0);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc1,	FIMC1,	FIMC1);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc2,	FIMC2,	FIMC2);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc3,	FIMC3,	FIMC3);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, jpeg,	JPEG,	JPEG);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, 2d,	G2D,	2D);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, tv,	TV,	TV_M0);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, 2d_acp,	G2D_ACP, 2D);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, rot,	ROTATOR, ROTATOR);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimd0,	FIMD0,	LCD0_M0);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimd1,	FIMD1,	LCD1_M1);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, flite0,	FIMC_LITE0, FIMC_LITE0);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, flite1,	FIMC_LITE1, FIMC_LITE1);
+SYSMMU_RESOURCE(EXYNOS4, mfc_lr) {
+	DEFINE_SYSMMU_RESOURCE(EXYNOS4, MFC_R, MFC_M0),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS4, MFC_L, MFC_M1),
+};
+SYSMMU_RESOURCE(EXYNOS4, isp) {
+	DEFINE_SYSMMU_RESOURCE(EXYNOS4, ISP, FIMC_ISP),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS4, DRC, FIMC_DRC),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS4, FD, FIMC_FD),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS4, ISPCPU, FIMC_CX),
+};
+
+static struct sysmmu_resource_map sysmmu_resmap4[] __initdata = {
+	SYSMMU_RESOURCE_MAPPING_PD(4, fimc0,	fimc0,	PD_CAM),
+	SYSMMU_RESOURCE_MAPPING_PD(4, fimc1,	fimc1,	PD_CAM),
+	SYSMMU_RESOURCE_MAPPING_PD(4, fimc2,	fimc2,	PD_CAM),
+	SYSMMU_RESOURCE_MAPPING_PD(4, fimc3,	fimc3,	PD_CAM),
+	SYSMMU_RESOURCE_MAPPING_PD(4, tv,	tv,	PD_TV),
+	SYSMMU_RESOURCE_MAPPING_PD(4, mfc_lr,	mfc_lr,	PD_MFC),
+	SYSMMU_RESOURCE_MAPPING_PD(4, rot,	rot,	PD_LCD0),
+	SYSMMU_RESOURCE_MAPPING_PD(4, jpeg,	jpeg,	PD_CAM),
+	SYSMMU_RESOURCE_MAPPING_PD(4, fimd0,	fimd0,	PD_LCD0),
+};
+
+static struct sysmmu_resource_map sysmmu_resmap4210[] __initdata = {
+	SYSMMU_RESOURCE_MAPPING_PD(4, 2d,	2d,	PD_LCD0),
+	SYSMMU_RESOURCE_MAPPING_PD(4, fimd1,	fimd1,	PD_LCD1),
+};
+
+static struct sysmmu_resource_map sysmmu_resmap4212[] __initdata = {
+	SYSMMU_RESOURCE_MAPPING(4,	2d,	2d_acp),
+	SYSMMU_RESOURCE_MAPPING_PD(4,	camif0, flite0,	PD_ISP),
+	SYSMMU_RESOURCE_MAPPING_PD(4,	camif1, flite1,	PD_ISP),
+	SYSMMU_RESOURCE_MAPPING_PD(4,	isp,	isp,	PD_ISP),
+};
+#endif /* CONFIG_ARCH_EXYNOS4 */
+
+#ifdef CONFIG_ARCH_EXYNOS5
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, jpeg,	JPEG,	JPEG);
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, fimd1,	FIMD1,	FIMD1);
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, 2d,	2D,	2D);
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, rot,	ROTATOR, ROTATOR);
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, tv,	TV,	TV);
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, flite0,	LITE0,	LITE0);
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, flite1,	LITE1,	LITE1);
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, flite2,	LITE2,	LITE2);
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc0,	GSC0,	GSC0);
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc1,	GSC1,	GSC1);
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc2,	GSC2,	GSC2);
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc3,	GSC3,	GSC3);
+SYSMMU_RESOURCE(EXYNOS5, mfc_lr) {
+	DEFINE_SYSMMU_RESOURCE(EXYNOS5, MFC_R, MFC_R),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS5, MFC_L, MFC_L),
+};
+SYSMMU_RESOURCE(EXYNOS5, isp) {
+	DEFINE_SYSMMU_RESOURCE(EXYNOS5, ISP, ISP),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS5, DRC, DRC),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS5, FD, FD),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS5, ISPCPU, MCUISP),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS5, SCALERC, SCALERCISP),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS5, SCALERP, SCALERPISP),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS5,	ODC, ODC),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS5, DIS0, DIS0),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS5, DIS1, DIS1),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS5, 3DNR, 3DNR),
+};
+
+static struct sysmmu_resource_map sysmmu_resmap5[] __initdata = {
+	SYSMMU_RESOURCE_MAPPING(5,	jpeg,	jpeg),
+	SYSMMU_RESOURCE_MAPPING(5,	fimd1,	fimd1),
+	SYSMMU_RESOURCE_MAPPING(5,	2d,	2d),
+	SYSMMU_RESOURCE_MAPPING(5,	rot,	rot),
+	SYSMMU_RESOURCE_MAPPING_PD(5,	tv,	tv,	PD_DISP1),
+	SYSMMU_RESOURCE_MAPPING_PD(5,	camif0,	flite0,	PD_GSCL),
+	SYSMMU_RESOURCE_MAPPING_PD(5,	camif1,	flite1,	PD_GSCL),
+	SYSMMU_RESOURCE_MAPPING_PD(5,	camif2,	flite2,	PD_GSCL),
+	SYSMMU_RESOURCE_MAPPING_PD(5,	gsc0,	gsc0,	PD_GSCL),
+	SYSMMU_RESOURCE_MAPPING_PD(5,	gsc1,	gsc1,	PD_GSCL),
+	SYSMMU_RESOURCE_MAPPING_PD(5,	gsc2,	gsc2,	PD_GSCL),
+	SYSMMU_RESOURCE_MAPPING_PD(5,	gsc3,	gsc3,	PD_GSCL),
+	SYSMMU_RESOURCE_MAPPING_PD(5,	mfc_lr,	mfc_lr,	PD_MFC),
+	SYSMMU_RESOURCE_MAPPING_MCPD(5,	isp,	isp,	PD_ISP, mc_platdata),
+};
+#endif /* CONFIG_ARCH_EXYNOS5 */
+
+static int __init init_sysmmu_platform_device(void)
+{
+	int i, j;
+	struct sysmmu_resource_map *resmap[2] = {NULL, NULL};
+	int nmap[2] = {0, 0};
+
+#ifdef CONFIG_ARCH_EXYNOS5
+	if (soc_is_exynos5250()) {
+		resmap[0] = sysmmu_resmap5;
+		nmap[0] = ARRAY_SIZE(sysmmu_resmap5);
+		nmap[1] = 0;
+	}
+#endif
+
+#ifdef CONFIG_ARCH_EXYNOS4
+	if (resmap[0] == NULL) {
+		resmap[0] = sysmmu_resmap4;
+		nmap[0] = ARRAY_SIZE(sysmmu_resmap4);
+	}
+
+	if (soc_is_exynos4210()) {
+		resmap[1] = sysmmu_resmap4210;
+		nmap[1] = ARRAY_SIZE(sysmmu_resmap4210);
+	}
+
+	if (soc_is_exynos4412() || soc_is_exynos4212()) {
+		resmap[1] = sysmmu_resmap4212;
+		nmap[1] = ARRAY_SIZE(sysmmu_resmap4212);
+	}
+#endif
+
+	for (j = 0; j < 2; j++) {
+		for (i = 0; i < nmap[j]; i++) {
+			struct sysmmu_resource_map *map;
+			struct sysmmu_platform_data *platdata;
+
+			map = &resmap[j][i];
+
+			map->pdev->dev.parent = map->pdd;
+
+			platdata = map->pdev->dev.platform_data;
+			platdata->clockname = map->clocknames;
+
+			if (platform_device_add_resources(map->pdev, map->res,
+								map->rnum)) {
+				pr_err("%s: Failed to add device resources for "
+						"%s.%d\n", __func__,
+						map->pdev->name, map->pdev->id);
+				continue;
+			}
+
+			if (platform_device_register(map->pdev)) {
+				pr_err("%s: Failed to register %s.%d\n",
+					__func__, map->pdev->name,
+						map->pdev->id);
+			}
+		}
+	}
+
+	return 0;
+}
+subsys_initcall(init_sysmmu_platform_device);
diff --git a/arch/arm/mach-exynos/dev.c b/arch/arm/mach-exynos/dev.c
new file mode 100644
index 0000000..a866a9a
--- /dev/null
+++ b/arch/arm/mach-exynos/dev.c
@@ -0,0 +1,188 @@
+/* linux/arch/arm/mach-exynos/dev.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * EXYNOS4 Device List support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/device.h>
+#include <linux/list.h>
+#include <linux/mutex.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+
+#include <mach/dev.h>
+#ifdef CONFIG_ARCH_EXYNOS4
+#include <mach/busfreq_exynos4.h>
+#else
+#include <mach/busfreq_exynos5.h>
+#endif
+
+static LIST_HEAD(domains_list);
+static DEFINE_MUTEX(domains_mutex);
+
+static struct device_domain *find_device_domain(struct device *dev)
+{
+	struct device_domain *tmp_domain, *domain = ERR_PTR(-ENODEV);
+
+	mutex_lock(&domains_mutex);
+	list_for_each_entry(tmp_domain, &domains_list, node) {
+		if (tmp_domain->device == dev) {
+			domain = tmp_domain;
+			break;
+		}
+	}
+
+	mutex_unlock(&domains_mutex);
+	return domain;
+}
+
+int dev_add(struct device_domain *dev, struct device *device)
+{
+	if (!dev || !device)
+		return -EINVAL;
+
+	mutex_lock(&domains_mutex);
+	INIT_LIST_HEAD(&dev->domain_list);
+	dev->device = device;
+	list_add(&dev->node, &domains_list);
+	mutex_unlock(&domains_mutex);
+
+	return 0;
+}
+
+struct device *dev_get(const char *name)
+{
+	struct device_domain *domain;
+
+	mutex_lock(&domains_mutex);
+	list_for_each_entry(domain, &domains_list, node)
+		if (strcmp(name, dev_name(domain->device)) == 0)
+			goto found;
+
+	mutex_unlock(&domains_mutex);
+	return ERR_PTR(-ENODEV);
+found:
+	mutex_unlock(&domains_mutex);
+	return domain->device;
+}
+
+void dev_put(const char *name)
+{
+	return;
+}
+
+int dev_lock(struct device *device, struct device *dev,
+		unsigned long freq)
+{
+	struct device_domain *domain;
+	struct domain_lock *lock;
+	int ret = 0;
+
+	domain = find_device_domain(device);
+
+	if (IS_ERR(domain)) {
+		dev_err(dev, "Can't find device domain.\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&domains_mutex);
+	list_for_each_entry(lock, &domain->domain_list, node) {
+		if (lock->device == dev) {
+			/* If the lock already exist, only update the freq */
+			lock->freq = freq;
+			goto out;
+		}
+	}
+
+	lock = kzalloc(sizeof(struct domain_lock), GFP_KERNEL);
+	if (!lock) {
+		dev_err(device, "Unable to create domain_lock");
+		ret = -ENOMEM;
+		goto out;
+	}
+
+	lock->device = dev;
+	lock->freq = freq;
+	list_add(&lock->node, &domain->domain_list);
+
+out:
+	mutex_unlock(&domains_mutex);
+	exynos_request_apply(freq);
+	return ret;
+}
+
+int dev_unlock(struct device *device, struct device *dev)
+{
+	struct device_domain *domain;
+	struct domain_lock *lock;
+
+	domain = find_device_domain(device);
+
+	if (IS_ERR(domain)) {
+		dev_err(dev, "Can't find device domain.\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&domains_mutex);
+	list_for_each_entry(lock, &domain->domain_list, node) {
+		if (lock->device == dev) {
+			list_del(&lock->node);
+			kfree(lock);
+			break;
+		}
+	}
+
+	mutex_unlock(&domains_mutex);
+
+	return 0;
+}
+
+unsigned long dev_max_freq(struct device *device)
+{
+	struct device_domain *domain;
+	struct domain_lock *lock;
+	unsigned long freq = 0;
+
+	domain = find_device_domain(device);
+	if (IS_ERR(domain)) {
+		dev_dbg(device, "Can't find device domain.\n");
+		return freq;
+	}
+
+	mutex_lock(&domains_mutex);
+	list_for_each_entry(lock, &domain->domain_list, node)
+		if (lock->freq > freq)
+			freq = lock->freq;
+
+	mutex_unlock(&domains_mutex);
+
+	return freq;
+}
+
+int dev_lock_list(struct device *device, char *buf)
+{
+	struct device_domain *domain;
+	struct domain_lock *lock;
+	int count = 0;
+
+	domain = find_device_domain(device);
+	if (IS_ERR(domain)) {
+		dev_dbg(device, "Can't find device domain.\n");
+		return 0;
+	}
+
+	mutex_lock(&domains_mutex);
+	count = sprintf(buf, "Lock List\n");
+	list_for_each_entry(lock, &domain->domain_list, node)
+		count += sprintf(buf + count, "%s : %lu\n", dev_name(lock->device), lock->freq);
+
+	mutex_unlock(&domains_mutex);
+
+	return count;
+}
diff --git a/arch/arm/mach-exynos/dma.c b/arch/arm/mach-exynos/dma.c
new file mode 100644
index 0000000..2de356e
--- /dev/null
+++ b/arch/arm/mach-exynos/dma.c
@@ -0,0 +1,404 @@
+/* linux/arch/arm/mach-exynos/dma.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Copyright (C) 2010 Samsung Electronics Co. Ltd.
+ *	Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+
+#include <plat/devs.h>
+#include <plat/irqs.h>
+#ifdef CONFIG_EXYNOS_DEV_PD
+#include <plat/pd.h>
+#endif
+
+#include <mach/map.h>
+#include <mach/irqs.h>
+
+#include <plat/cpu.h>
+#include <plat/s3c-pl330-pdata.h>
+
+static u64 dma_dmamask = DMA_BIT_MASK(32);
+
+static struct resource exynos_mdma_resource[] = {
+	[0] = {
+		.start  = S5P_PA_MDMA1,
+		.end    = S5P_PA_MDMA1 + SZ_4K,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= IRQ_MDMA1,
+		.end	= IRQ_MDMA1,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+struct s3c_pl330_platdata exynos_mdma_pdata = {
+	.peri = {
+		/*
+		 * The DMAC can have max 8 channel so there
+		 * can be MAX 8 M<->M requests served at any time.
+		 *
+		 * Always keep the first 8 M->M channels on the
+		 * DMAC dedicated for M->M transfers.
+		 */
+		[0] = DMACH_MTOM_0,
+		[1] = DMACH_MTOM_1,
+		[2] = DMACH_MTOM_2,
+		[3] = DMACH_MTOM_3,
+		[4] = DMACH_MTOM_4,
+		[5] = DMACH_MTOM_5,
+		[6] = DMACH_MTOM_6,
+		[7] = DMACH_MTOM_7,
+		[8] = DMACH_MAX,
+		[9] = DMACH_MAX,
+		[10] = DMACH_MAX,
+		[11] = DMACH_MAX,
+		[12] = DMACH_MAX,
+		[13] = DMACH_MAX,
+		[14] = DMACH_MAX,
+		[15] = DMACH_MAX,
+		[16] = DMACH_MAX,
+		[17] = DMACH_MAX,
+		[18] = DMACH_MAX,
+		[19] = DMACH_MAX,
+		[20] = DMACH_MAX,
+		[21] = DMACH_MAX,
+		[22] = DMACH_MAX,
+		[23] = DMACH_MAX,
+		[24] = DMACH_MAX,
+		[25] = DMACH_MAX,
+		[26] = DMACH_MAX,
+		[27] = DMACH_MAX,
+		[28] = DMACH_MAX,
+		[29] = DMACH_MAX,
+		[30] = DMACH_MAX,
+		[31] = DMACH_MAX,
+	},
+};
+
+struct platform_device exynos_device_mdma = {
+	.name		= "s3c-pl330",
+	.id		= 0,
+	.num_resources	= ARRAY_SIZE(exynos_mdma_resource),
+	.resource	= exynos_mdma_resource,
+	.dev		= {
+		.dma_mask = &dma_dmamask,
+		.coherent_dma_mask = DMA_BIT_MASK(32),
+		.platform_data = &exynos_mdma_pdata,
+#if 0 /* defined(CONFIG_ARCH_EXYNOS4) && defined(CONFIG_EXYNOS_DEV_PD) */
+		.parent = &exynos4_device_pd[PD_LCD0].dev,
+#endif
+	},
+};
+
+static struct resource exynos_pdma0_resource[] = {
+	[0] = {
+		.start	= S5P_PA_PDMA0,
+		.end	= S5P_PA_PDMA0 + SZ_4K,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= IRQ_PDMA0,
+		.end	= IRQ_PDMA0,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct s3c_pl330_platdata exynos4210_pdma0_pdata = {
+	.peri = {
+		[0] = DMACH_PCM0_RX,
+		[1] = DMACH_PCM0_TX,
+		[2] = DMACH_PCM2_RX,
+		[3] = DMACH_PCM2_TX,
+		[4] = DMACH_MSM_REQ0,
+		[5] = DMACH_MSM_REQ2,
+		[6] = DMACH_SPI0_RX,
+		[7] = DMACH_SPI0_TX,
+		[8] = DMACH_SPI2_RX,
+		[9] = DMACH_SPI2_TX,
+		[10] = DMACH_I2S0S_TX,
+		[11] = DMACH_I2S0_RX,
+		[12] = DMACH_I2S0_TX,
+		[13] = DMACH_I2S2_RX,
+		[14] = DMACH_I2S2_TX,
+		[15] = DMACH_UART0_RX,
+		[16] = DMACH_UART0_TX,
+		[17] = DMACH_UART2_RX,
+		[18] = DMACH_UART2_TX,
+		[19] = DMACH_UART4_RX,
+		[20] = DMACH_UART4_TX,
+		[21] = DMACH_SLIMBUS0_RX,
+		[22] = DMACH_SLIMBUS0_TX,
+		[23] = DMACH_SLIMBUS2_RX,
+		[24] = DMACH_SLIMBUS2_TX,
+		[25] = DMACH_SLIMBUS4_RX,
+		[26] = DMACH_SLIMBUS4_TX,
+		[27] = DMACH_AC97_MICIN,
+		[28] = DMACH_AC97_PCMIN,
+		[29] = DMACH_AC97_PCMOUT,
+		[30] = DMACH_MAX,
+		[31] = DMACH_MAX,
+	},
+};
+
+static struct s3c_pl330_platdata exynos4212_pdma0_pdata = {
+	.peri = {
+		[0] = DMACH_PCM0_RX,
+		[1] = DMACH_PCM0_TX,
+		[2] = DMACH_PCM2_RX,
+		[3] = DMACH_PCM2_TX,
+		[4] = DMACH_MIPI_HSI0,
+		[5] = DMACH_MIPI_HSI1,
+		[6] = DMACH_SPI0_RX,
+		[7] = DMACH_SPI0_TX,
+		[8] = DMACH_SPI2_RX,
+		[9] = DMACH_SPI2_TX,
+		[10] = DMACH_I2S0S_TX,
+		[11] = DMACH_I2S0_RX,
+		[12] = DMACH_I2S0_TX,
+		[13] = DMACH_I2S2_RX,
+		[14] = DMACH_I2S2_TX,
+		[15] = DMACH_UART0_RX,
+		[16] = DMACH_UART0_TX,
+		[17] = DMACH_UART2_RX,
+		[18] = DMACH_UART2_TX,
+		[19] = DMACH_UART4_RX,
+		[20] = DMACH_UART4_TX,
+		[21] = DMACH_SLIMBUS0_RX,
+		[22] = DMACH_SLIMBUS0_TX,
+		[23] = DMACH_SLIMBUS2_RX,
+		[24] = DMACH_SLIMBUS2_TX,
+		[25] = DMACH_SLIMBUS4_RX,
+		[26] = DMACH_SLIMBUS4_TX,
+		[27] = DMACH_AC97_MICIN,
+		[28] = DMACH_AC97_PCMIN,
+		[29] = DMACH_AC97_PCMOUT,
+		[30] = DMACH_MIPI_HSI4,
+		[31] = DMACH_MIPI_HSI5,
+	},
+};
+
+static struct s3c_pl330_platdata exynos5210_pdma0_pdata = {
+	.peri = {
+		[0] = DMACH_PCM0_RX,
+		[1] = DMACH_PCM0_TX,
+		[2] = DMACH_PCM2_RX,
+		[3] = DMACH_PCM2_TX,
+		[4] = DMACH_SPI0_RX,
+		[5] = DMACH_SPI0_TX,
+		[6] = DMACH_SPI2_RX,
+		[7] = DMACH_SPI2_TX,
+		[8] = DMACH_I2S0S_TX,
+		[9] = DMACH_I2S0_RX,
+		[10] = DMACH_I2S0_TX,
+		[11] = DMACH_I2S2_RX,
+		[12] = DMACH_I2S2_TX,
+		[13] = DMACH_UART0_RX,
+		[14] = DMACH_UART0_TX,
+		[15] = DMACH_UART2_RX,
+		[16] = DMACH_UART2_TX,
+		[17] = DMACH_UART4_RX,
+		[18] = DMACH_UART4_TX,
+		[19] = DMACH_SLIMBUS0_RX,
+		[20] = DMACH_SLIMBUS0_TX,
+		[21] = DMACH_SLIMBUS2_RX,
+		[22] = DMACH_SLIMBUS2_TX,
+		[23] = DMACH_SLIMBUS4_RX,
+		[24] = DMACH_SLIMBUS4_TX,
+		[25] = DMACH_AC97_MICIN,
+		[26] = DMACH_AC97_PCMIN,
+		[27] = DMACH_AC97_PCMOUT,
+		[28] = DMACH_MIPI_HSI0,
+		[29] = DMACH_MIPI_HSI2,
+		[30] = DMACH_MIPI_HSI4,
+		[31] = DMACH_MIPI_HSI6,
+	},
+};
+
+struct platform_device exynos_device_pdma0 = {
+	.name		= "s3c-pl330",
+	.id		= 1,
+	.num_resources	= ARRAY_SIZE(exynos_pdma0_resource),
+	.resource	= exynos_pdma0_resource,
+	.dev		= {
+		.dma_mask = &dma_dmamask,
+		.coherent_dma_mask = DMA_BIT_MASK(32),
+	},
+};
+
+static struct resource exynos_pdma1_resource[] = {
+	[0] = {
+		.start	= S5P_PA_PDMA1,
+		.end	= S5P_PA_PDMA1 + SZ_4K,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= IRQ_PDMA1,
+		.end	= IRQ_PDMA1,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct s3c_pl330_platdata exynos4210_pdma1_pdata = {
+	.peri = {
+		[0] = DMACH_PCM0_RX,
+		[1] = DMACH_PCM0_TX,
+		[2] = DMACH_PCM1_RX,
+		[3] = DMACH_PCM1_TX,
+		[4] = DMACH_MSM_REQ1,
+		[5] = DMACH_MSM_REQ3,
+		[6] = DMACH_SPI1_RX,
+		[7] = DMACH_SPI1_TX,
+		[8] = DMACH_I2S0S_TX,
+		[9] = DMACH_I2S0_RX,
+		[10] = DMACH_I2S0_TX,
+		[11] = DMACH_I2S1_RX,
+		[12] = DMACH_I2S1_TX,
+		[13] = DMACH_UART0_RX,
+		[14] = DMACH_UART0_TX,
+		[15] = DMACH_UART1_RX,
+		[16] = DMACH_UART1_TX,
+		[17] = DMACH_UART3_RX,
+		[18] = DMACH_UART3_TX,
+		[19] = DMACH_SLIMBUS1_RX,
+		[20] = DMACH_SLIMBUS1_TX,
+		[21] = DMACH_SLIMBUS3_RX,
+		[22] = DMACH_SLIMBUS3_TX,
+		[23] = DMACH_SLIMBUS5_RX,
+		[24] = DMACH_SLIMBUS5_TX,
+		[25] = DMACH_SLIMBUS0AUX_RX,
+		[26] = DMACH_SLIMBUS0AUX_TX,
+		[27] = DMACH_SPDIF,
+		[28] = DMACH_MAX,
+		[29] = DMACH_MAX,
+		[30] = DMACH_MAX,
+		[31] = DMACH_MAX,
+	},
+};
+
+static struct s3c_pl330_platdata exynos4212_pdma1_pdata = {
+	.peri = {
+		[0] = DMACH_PCM0_RX,
+		[1] = DMACH_PCM0_TX,
+		[2] = DMACH_PCM1_RX,
+		[3] = DMACH_PCM1_TX,
+		[4] = DMACH_MIPI_HSI2,
+		[5] = DMACH_MIPI_HSI3,
+		[6] = DMACH_SPI1_RX,
+		[7] = DMACH_SPI1_TX,
+		[8] = DMACH_I2S0S_TX,
+		[9] = DMACH_I2S0_RX,
+		[10] = DMACH_I2S0_TX,
+		[11] = DMACH_I2S1_RX,
+		[12] = DMACH_I2S1_TX,
+		[13] = DMACH_UART0_RX,
+		[14] = DMACH_UART0_TX,
+		[15] = DMACH_UART1_RX,
+		[16] = DMACH_UART1_TX,
+		[17] = DMACH_UART3_RX,
+		[18] = DMACH_UART3_TX,
+		[19] = DMACH_SLIMBUS1_RX,
+		[20] = DMACH_SLIMBUS1_TX,
+		[21] = DMACH_SLIMBUS3_RX,
+		[22] = DMACH_SLIMBUS3_TX,
+		[23] = DMACH_SLIMBUS5_RX,
+		[24] = DMACH_SLIMBUS5_TX,
+		[25] = DMACH_SLIMBUS0AUX_RX,
+		[26] = DMACH_SLIMBUS0AUX_TX,
+		[27] = DMACH_SPDIF,
+		[28] = DMACH_MIPI_HSI6,
+		[29] = DMACH_MIPI_HSI7,
+		[30] = DMACH_MAX,
+		[31] = DMACH_MAX,
+	},
+};
+
+static struct s3c_pl330_platdata exynos5210_pdma1_pdata = {
+	.peri = {
+		[0] = DMACH_PCM0_RX,
+		[1] = DMACH_PCM0_TX,
+		[2] = DMACH_PCM1_RX,
+		[3] = DMACH_PCM1_TX,
+		[4] = DMACH_SPI1_RX,
+		[5] = DMACH_SPI1_TX,
+		[6] = DMACH_PWM,
+		[7] = DMACH_SPDIF,
+		[8] = DMACH_I2S0S_TX,
+		[9] = DMACH_I2S0_RX,
+		[10] = DMACH_I2S0_TX,
+		[11] = DMACH_I2S1_RX,
+		[12] = DMACH_I2S1_TX,
+		[13] = DMACH_UART0_RX,
+		[14] = DMACH_UART0_TX,
+		[15] = DMACH_UART1_RX,
+		[16] = DMACH_UART1_TX,
+		[17] = DMACH_UART3_RX,
+		[18] = DMACH_UART3_TX,
+		[19] = DMACH_SLIMBUS1_RX,
+		[20] = DMACH_SLIMBUS1_TX,
+		[21] = DMACH_SLIMBUS3_RX,
+		[22] = DMACH_SLIMBUS3_TX,
+		[23] = DMACH_SLIMBUS5_RX,
+		[24] = DMACH_SLIMBUS5_TX,
+		[25] = DMACH_SLIMBUS0AUX_RX,
+		[26] = DMACH_SLIMBUS0AUX_TX,
+		[27] = DMACH_DISP1,
+		[28] = DMACH_MIPI_HSI1,
+		[29] = DMACH_MIPI_HSI3,
+		[30] = DMACH_MIPI_HSI5,
+		[31] = DMACH_MIPI_HSI7,
+	},
+};
+
+struct platform_device exynos_device_pdma1 = {
+	.name		= "s3c-pl330",
+	.id		= 2,
+	.num_resources	= ARRAY_SIZE(exynos_pdma1_resource),
+	.resource	= exynos_pdma1_resource,
+	.dev		= {
+		.dma_mask = &dma_dmamask,
+		.coherent_dma_mask = DMA_BIT_MASK(32),
+	},
+};
+
+static struct platform_device *exynos_dmacs[] __initdata = {
+	&exynos_device_mdma,
+	&exynos_device_pdma0,
+	&exynos_device_pdma1,
+};
+
+static int __init exynos_dma_init(void)
+{
+	if (soc_is_exynos4210()) {
+		exynos_device_pdma0.dev.platform_data = &exynos4210_pdma0_pdata;
+		exynos_device_pdma1.dev.platform_data = &exynos4210_pdma1_pdata;
+	} else if (soc_is_exynos4212() || soc_is_exynos4412()) {
+		exynos_device_pdma0.dev.platform_data = &exynos4212_pdma0_pdata;
+		exynos_device_pdma1.dev.platform_data = &exynos4212_pdma1_pdata;
+	} else if (soc_is_exynos5210() || soc_is_exynos5250()) {
+		exynos_device_pdma0.dev.platform_data = &exynos5210_pdma0_pdata;
+		exynos_device_pdma1.dev.platform_data = &exynos5210_pdma1_pdata;
+	}
+
+	return platform_add_devices(exynos_dmacs, ARRAY_SIZE(exynos_dmacs));
+}
+arch_initcall(exynos_dma_init);
diff --git a/arch/arm/mach-exynos/dvfs-hotplug.c b/arch/arm/mach-exynos/dvfs-hotplug.c
new file mode 100644
index 0000000..519e9f3
--- /dev/null
+++ b/arch/arm/mach-exynos/dvfs-hotplug.c
@@ -0,0 +1,180 @@
+/* linux/arch/arm/mach-exynos/dvfs-hotplug.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * EXYNOS4 - Integrated DVFS CPU hotplug
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/sched.h>
+#include <linux/cpufreq.h>
+#include <linux/cpu.h>
+#include <linux/err.h>
+#include <linux/notifier.h>
+#include <linux/reboot.h>
+#include <linux/suspend.h>
+#include <linux/io.h>
+
+#include <plat/cpu.h>
+
+static unsigned int total_num_target_freq;
+static unsigned int consecutv_highestlevel_cnt;
+static unsigned int consecutv_lowestlevel_cnt;
+
+static unsigned int freq_max;
+static unsigned int freq_in_trg;
+static unsigned int freq_min = -1UL;
+
+static unsigned int can_hotplug;
+
+static void exynos4_integrated_dvfs_hotplug(unsigned int freq_old,
+					unsigned int freq_new)
+{
+	total_num_target_freq++;
+	freq_in_trg = 800000;
+
+	if ((freq_old >= freq_in_trg) && (freq_new >= freq_in_trg)) {
+		if (soc_is_exynos4412()) {
+			if (cpu_online(3) == 0) {
+				if (consecutv_highestlevel_cnt >= 5) {
+					cpu_up(3);
+					consecutv_highestlevel_cnt = 0;
+				}
+			} else if (cpu_online(2) == 0) {
+				if (consecutv_highestlevel_cnt >= 5) {
+					cpu_up(2);
+					consecutv_highestlevel_cnt = 0;
+				}
+			} else if (cpu_online(1) == 0) {
+				if (consecutv_highestlevel_cnt >= 5) {
+					cpu_up(1);
+					consecutv_highestlevel_cnt = 0;
+				}
+			}
+			consecutv_highestlevel_cnt++;
+		} else {
+			if (cpu_online(1) == 0) {
+				if (consecutv_highestlevel_cnt >= 5) {
+					cpu_up(1);
+					consecutv_highestlevel_cnt = 0;
+				}
+			}
+			consecutv_highestlevel_cnt++;
+		}
+	} else if ((freq_old <= freq_min) && (freq_new <= freq_min)) {
+		if (soc_is_exynos4412()) {
+			if (cpu_online(1) == 1) {
+				if (consecutv_lowestlevel_cnt >= 5) {
+					cpu_down(1);
+					consecutv_lowestlevel_cnt = 0;
+				} else
+					consecutv_lowestlevel_cnt++;
+			} else if (cpu_online(2) == 1) {
+				if (consecutv_lowestlevel_cnt >= 5) {
+					cpu_down(2);
+					consecutv_lowestlevel_cnt = 0;
+				} else
+					consecutv_lowestlevel_cnt++;
+			} else if (cpu_online(3) == 1) {
+				if (consecutv_lowestlevel_cnt >= 5) {
+					cpu_down(3);
+					consecutv_lowestlevel_cnt = 0;
+				} else
+					consecutv_lowestlevel_cnt++;
+			}
+		} else {
+			if (cpu_online(1) == 1) {
+				if (consecutv_lowestlevel_cnt >= 5) {
+					cpu_down(1);
+					consecutv_lowestlevel_cnt = 0;
+				} else
+					consecutv_lowestlevel_cnt++;
+			}
+		}
+	} else {
+		consecutv_highestlevel_cnt = 0;
+		consecutv_lowestlevel_cnt = 0;
+	}
+}
+
+static int hotplug_cpufreq_transition(struct notifier_block *nb,
+					unsigned long val, void *data)
+{
+	struct cpufreq_freqs *freqs = (struct cpufreq_freqs *)data;
+
+	if ((val == CPUFREQ_POSTCHANGE) && can_hotplug)
+		exynos4_integrated_dvfs_hotplug(freqs->old, freqs->new);
+
+	return 0;
+}
+
+static struct notifier_block dvfs_hotplug = {
+	.notifier_call = hotplug_cpufreq_transition,
+};
+
+static int hotplug_pm_transition(struct notifier_block *nb,
+					unsigned long val, void *data)
+{
+	switch (val) {
+	case PM_SUSPEND_PREPARE:
+		can_hotplug = 0;
+		consecutv_highestlevel_cnt = 0;
+		consecutv_lowestlevel_cnt = 0;
+		break;
+	case PM_POST_RESTORE:
+	case PM_POST_SUSPEND:
+		can_hotplug = 1;
+		break;
+	}
+
+	return 0;
+}
+
+static struct notifier_block pm_hotplug = {
+	.notifier_call = hotplug_pm_transition,
+};
+
+/*
+ * Note : This function should be called after intialization of CPUFreq
+ * driver for exynos4. The cpufreq_frequency_table for exynos4 should be
+ * established before calling this function.
+ */
+static int __init exynos4_integrated_dvfs_hotplug_init(void)
+{
+	int i;
+	struct cpufreq_frequency_table *table;
+	unsigned int freq;
+
+	total_num_target_freq = 0;
+	consecutv_highestlevel_cnt = 0;
+	consecutv_lowestlevel_cnt = 0;
+	can_hotplug = 1;
+
+	table = cpufreq_frequency_get_table(0);
+	if (IS_ERR(table)) {
+		printk(KERN_ERR "%s: Check loading cpufreq before\n", __func__);
+		return PTR_ERR(table);
+	}
+
+	for (i = 0; table[i].frequency != CPUFREQ_TABLE_END; i++) {
+		freq = table[i].frequency;
+
+		if (freq != CPUFREQ_ENTRY_INVALID && freq > freq_max)
+			freq_max = freq;
+		else if (freq != CPUFREQ_ENTRY_INVALID && freq_min > freq)
+			freq_min = freq;
+	}
+
+	printk(KERN_INFO "%s, max(%d),min(%d)\n", __func__, freq_max, freq_min);
+
+	register_pm_notifier(&pm_hotplug);
+
+	return cpufreq_register_notifier(&dvfs_hotplug,
+					 CPUFREQ_TRANSITION_NOTIFIER);
+}
+
+late_initcall(exynos4_integrated_dvfs_hotplug_init);
diff --git a/arch/arm/mach-exynos/dynamic-dvfs-nr_running-hotplug.c b/arch/arm/mach-exynos/dynamic-dvfs-nr_running-hotplug.c
new file mode 100644
index 0000000..7c380ae
--- /dev/null
+++ b/arch/arm/mach-exynos/dynamic-dvfs-nr_running-hotplug.c
@@ -0,0 +1,322 @@
+/* linux/arch/arm/mach-exynos/dynamic-dvfs-nr_running-hotplug.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * EXYNOS4 - Integrated DVFS CPU hotplug
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/sched.h>
+#include <linux/cpufreq.h>
+#include <linux/cpu.h>
+#include <linux/err.h>
+#include <linux/notifier.h>
+#include <linux/reboot.h>
+#include <linux/suspend.h>
+#include <linux/io.h>
+
+#ifdef CONFIG_SLP
+#include <linux/platform_device.h>
+#endif
+
+#include <plat/cpu.h>
+
+static unsigned int total_num_target_freq;
+static unsigned int ctn_freq_in_trg_cnt;	/* continuous frequency hotplug in trigger count */
+static unsigned int ctn_freq_out_trg_cnt;	/* continuous frequency hotplug out trigger count */
+static unsigned int ctn_nr_running_over2;
+static unsigned int ctn_nr_running_over3;
+static unsigned int ctn_nr_running_over4;
+static unsigned int ctn_nr_running_under2;
+static unsigned int ctn_nr_running_under3;
+static unsigned int ctn_nr_running_under4;
+static unsigned int freq_max;			/* max frequency of the dedicated dvfs table */
+static unsigned int freq_min = -1UL;		/* min frequency of the dedicated dvfs table */
+static unsigned int freq_in_trg;		/* frequency hotplug in trigger */
+static unsigned int freq_out_trg;		/* frequency hotplug out trigger */
+static unsigned int can_hotplug;
+#ifdef CONFIG_SLP
+static unsigned int user_lock;			/* Enable/Disable hotplug */
+#endif
+
+static void exynos4_integrated_dvfs_hotplug(unsigned int freq_old,
+					unsigned int freq_new)
+{
+
+	total_num_target_freq++;
+	freq_in_trg = 800000;			/* tunnable */
+	freq_out_trg = freq_min;		/* tunnable */
+
+	if (nr_running() <= 1) {
+		ctn_nr_running_over2 = 0;
+		ctn_nr_running_over3 = 0;
+		ctn_nr_running_over4 = 0;
+		ctn_nr_running_under2++;
+		ctn_nr_running_under3++;
+		ctn_nr_running_under4++;
+	} else if ((nr_running() > 1) && (nr_running() <= 2)) {
+		ctn_nr_running_over2++;
+		ctn_nr_running_over3 = 0;
+		ctn_nr_running_over4 = 0;
+		ctn_nr_running_under2 = 0;
+		ctn_nr_running_under3++;
+		ctn_nr_running_under4++;
+	} else if ((nr_running() > 2) && (nr_running() <= 3)) {
+		ctn_nr_running_over2++;
+		ctn_nr_running_over3++;
+		ctn_nr_running_over4 = 0;
+		ctn_nr_running_under2 = 0;
+		ctn_nr_running_under3 = 0;
+		ctn_nr_running_under4++;
+	} else if (nr_running() > 3) {
+		ctn_nr_running_over2++;
+		ctn_nr_running_over3++;
+		ctn_nr_running_over4++;
+		ctn_nr_running_under2 = 0;
+		ctn_nr_running_under3 = 0;
+		ctn_nr_running_under4 = 0;
+	}
+
+	if ((freq_old >= freq_in_trg) && (freq_new >= freq_in_trg))
+		ctn_freq_in_trg_cnt++;
+	else
+		ctn_freq_in_trg_cnt = 0;
+	if ((freq_old <= freq_out_trg) && (freq_new <= freq_out_trg))
+		ctn_freq_out_trg_cnt++;
+	else
+		ctn_freq_out_trg_cnt = 0;
+
+	if (soc_is_exynos4412()) {
+		if ((cpu_online(3) == 0) && (nr_running() >= 2) &&
+		   ((freq_old >= freq_in_trg) && (freq_new >= freq_in_trg))) {
+			if ((ctn_nr_running_over2 >= 4) &&
+			   (ctn_freq_in_trg_cnt >= 5)) {
+				/* over 400ms for nr_running(), over 500ms for frequency, tunnable */
+				cpu_up(3);
+				ctn_freq_in_trg_cnt = 0;
+			}
+		} else if ((cpu_online(2) == 0) && (nr_running() >= 3) &&
+			  ((freq_old >= freq_in_trg) && (freq_new >= freq_in_trg))) {
+			if ((ctn_nr_running_over3 >= 4) &&
+			   (ctn_freq_in_trg_cnt >= 5)) {
+				/* over 400ms for nr_running(), over 500ms for frequency, tunnable */
+				cpu_up(2);
+				ctn_freq_in_trg_cnt = 0;
+			}
+		} else if ((cpu_online(1) == 0) && (nr_running() >= 4) &&
+			  ((freq_old >= freq_in_trg) && (freq_new >= freq_in_trg))) {
+			if ((ctn_nr_running_over4 >= 8) &&
+			   (ctn_freq_in_trg_cnt >= 5)) {
+				/* over 800ms for nr_running(), over 500ms for frequency, tunnable */
+				cpu_up(1);
+				ctn_freq_in_trg_cnt = 0;
+			}
+		}
+	} else {
+		if ((cpu_online(1) == 0) && ((freq_old >= freq_in_trg) &&
+		   (freq_new >= freq_in_trg))) {
+			if ((ctn_nr_running_over2 >= 8) &&
+			   (ctn_freq_in_trg_cnt >= 5)) {
+				/* over 800ms  for nr_running(), over 500ms for frequency, tunnable */
+				cpu_up(1);
+				ctn_nr_running_over2 = 0;
+				ctn_freq_in_trg_cnt = 0;
+			}
+		}
+	}
+
+	if (soc_is_exynos4412()) {
+		if ((cpu_online(1) == 1) && (nr_running() < 4) &&
+		   ((freq_old <= freq_out_trg) && (freq_new <= freq_out_trg))) {
+			if ((ctn_nr_running_under4 >= 8) &&
+			   (ctn_freq_out_trg_cnt >= 5)) {
+				/* over 800ms for nr_running(), over 500ms for frequency, tunnable */
+				cpu_down(1);
+				ctn_freq_out_trg_cnt = 0;
+			}
+		} else if ((cpu_online(2) == 1) && (nr_running() < 3) &&
+			  ((freq_old <= freq_out_trg) && (freq_new <= freq_out_trg))) {
+			if ((ctn_nr_running_under3 >= 8) &&
+			   (ctn_freq_out_trg_cnt >= 5)) {
+				/* over 800ms for nr_running(), over 500ms for frequency, tunnable */
+				cpu_down(2);
+				ctn_freq_out_trg_cnt = 0;
+			}
+		} else if ((cpu_online(3) == 1) && (nr_running() < 2) &&
+			  ((freq_old <= freq_out_trg) && (freq_new <= freq_out_trg))) {
+			if ((ctn_nr_running_under2 >= 8) &&
+			   (ctn_freq_out_trg_cnt >= 5)) {
+				/* over 800ms for nr_running(), over 500ms for frequency, tunnable */
+				cpu_down(3);
+				ctn_freq_out_trg_cnt = 0;
+			}
+		}
+	} else {
+		if ((cpu_online(1) == 1) &&
+		   ((freq_old <= freq_out_trg) && (freq_new <= freq_out_trg))) {
+			if ((ctn_nr_running_under2 >= 8) &&
+			   (ctn_freq_out_trg_cnt >= 5)) {
+				/* over 800ms for nr_running(), over 500ms for frequency, tunnable */
+				cpu_down(1);
+				ctn_nr_running_under2 = 0;
+				ctn_freq_out_trg_cnt = 0;
+			}
+		}
+	}
+}
+
+static int hotplug_cpufreq_transition(struct notifier_block *nb,
+					unsigned long val, void *data)
+{
+	struct cpufreq_freqs *freqs = (struct cpufreq_freqs *)data;
+
+	if ((val == CPUFREQ_POSTCHANGE) && can_hotplug)
+		exynos4_integrated_dvfs_hotplug(freqs->old, freqs->new);
+
+	return 0;
+}
+
+static struct notifier_block dvfs_hotplug = {
+	.notifier_call = hotplug_cpufreq_transition,
+};
+
+static int hotplug_pm_transition(struct notifier_block *nb,
+					unsigned long val, void *data)
+{
+	switch (val) {
+	case PM_SUSPEND_PREPARE:
+		can_hotplug = 0;
+		ctn_freq_in_trg_cnt = 0;
+		ctn_freq_out_trg_cnt = 0;
+		break;
+	case PM_POST_RESTORE:
+	case PM_POST_SUSPEND:
+#ifdef CONFIG_SLP
+		if (!user_lock)
+#endif
+			can_hotplug = 1;
+		break;
+	}
+
+	return 0;
+}
+
+static struct notifier_block pm_hotplug = {
+	.notifier_call = hotplug_pm_transition,
+};
+
+#ifdef CONFIG_SLP
+static ssize_t user_lock_show(struct device *dev,
+	 struct device_attribute *attr,	char *buf)
+{
+	return sprintf(buf, "%u\n", user_lock);
+}
+
+static ssize_t user_lock_store(struct device *dev,
+	struct device_attribute *attr, const char *buf, size_t count)
+{
+	int ret;
+
+	ret = sscanf(buf, "%u", &user_lock);
+	if (ret != 1)
+		return -EINVAL;
+
+	if (user_lock)
+		can_hotplug = 0;
+	else
+		can_hotplug = 1;
+
+	return count;
+}
+static DEVICE_ATTR(user_lock, 0644, user_lock_show, user_lock_store);
+
+static int sysfs_pm_hotplug_create(struct device *dev)
+{
+	int ret;
+
+	ret = device_create_file(dev, &dev_attr_user_lock);
+
+	if (ret)
+		device_remove_file(dev, &dev_attr_user_lock);
+
+	return ret;
+}
+
+static void sysfs_pm_hotplug_remove(struct device *dev)
+{
+	device_remove_file(dev, &dev_attr_user_lock);
+}
+
+static struct platform_device exynos_pm_hotplug_device = {
+	.name   = "exynos-dynamic-cpu-hotplug",
+	.id     = -1,
+};
+#endif
+
+/*
+ * Note : This function should be called after intialization of CPUFreq
+ * driver for exynos4. The cpufreq_frequency_table for exynos4 should be
+ * established before calling this function.
+ */
+static int __init exynos4_integrated_dvfs_hotplug_init(void)
+{
+	int i;
+	struct cpufreq_frequency_table *table;
+	unsigned int freq;
+
+#ifdef CONFIG_SLP
+	int ret;
+#endif
+
+	total_num_target_freq = 0;
+	ctn_freq_in_trg_cnt = 0;
+	ctn_freq_out_trg_cnt = 0;
+	ctn_nr_running_over2 = 0;
+	ctn_nr_running_over3 = 0;
+	ctn_nr_running_over4 = 0;
+	ctn_nr_running_under2 = 0;
+	ctn_nr_running_under3 = 0;
+	ctn_nr_running_under4 = 0;
+
+	can_hotplug = 1;
+
+	table = cpufreq_frequency_get_table(0);
+	if (IS_ERR(table)) {
+		printk(KERN_ERR "%s: Check loading cpufreq before\n", __func__);
+		return PTR_ERR(table);
+	}
+
+	for (i = 0; table[i].frequency != CPUFREQ_TABLE_END; i++) {
+		freq = table[i].frequency;
+
+		if (freq != CPUFREQ_ENTRY_INVALID && freq > freq_max)
+			freq_max = freq;
+		else if (freq != CPUFREQ_ENTRY_INVALID && freq_min > freq)
+			freq_min = freq;
+	}
+
+	printk(KERN_INFO "%s, max(%d),min(%d)\n", __func__, freq_max, freq_min);
+
+#ifdef CONFIG_SLP
+	ret = platform_device_register(&exynos_pm_hotplug_device);
+	if (ret) {
+		printk(KERN_ERR "failed register pd\n");
+		return ret;
+	}
+
+	ret = sysfs_pm_hotplug_create(&exynos_pm_hotplug_device.dev);
+	if (ret)
+		printk(KERN_ERR "failed at(%d)\n", __LINE__);
+#endif
+
+	register_pm_notifier(&pm_hotplug);
+
+	return cpufreq_register_notifier(&dvfs_hotplug,
+					 CPUFREQ_TRANSITION_NOTIFIER);
+}
+
+late_initcall(exynos4_integrated_dvfs_hotplug_init);
diff --git a/arch/arm/mach-exynos/dynamic-nr_running-hotplug.c b/arch/arm/mach-exynos/dynamic-nr_running-hotplug.c
new file mode 100644
index 0000000..233a104
--- /dev/null
+++ b/arch/arm/mach-exynos/dynamic-nr_running-hotplug.c
@@ -0,0 +1,199 @@
+/* linux/arch/arm/mach-exynos/dynamic-nr_running-hotplug.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * EXYNOS - nr_running based dynamic CPU hotplug
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/sched.h>
+#include <linux/cpufreq.h>
+#include <linux/cpu.h>
+#include <linux/err.h>
+#include <linux/notifier.h>
+#include <linux/reboot.h>
+#include <linux/suspend.h>
+#include <plat/cpu.h>
+
+static unsigned int total_num_target_freq;
+static unsigned int ctn_highestlevel_cnt;		/* continuous the highest level count */
+static unsigned int ctn_lowestlevel_cnt;
+static unsigned int ctn_nr_running_over2;
+static unsigned int ctn_nr_running_over3;
+static unsigned int ctn_nr_running_over4;
+static unsigned int ctn_nr_running_under2;
+static unsigned int ctn_nr_running_under3;
+static unsigned int ctn_nr_running_under4;
+static unsigned int freq_max;
+static unsigned int freq_in_trg;
+static unsigned int freq_min;
+static unsigned int can_hotplug;
+
+static void exynos4_integrated_dvfs_hotplug(unsigned int freq_old,
+					unsigned int freq_new)
+{
+	total_num_target_freq++;
+	freq_in_trg = 800000;
+
+	if (nr_running() <= 1) {
+		ctn_nr_running_over2 = 0;
+		ctn_nr_running_over3 = 0;
+		ctn_nr_running_over4 = 0;
+		ctn_nr_running_under2++;
+		ctn_nr_running_under3++;
+		ctn_nr_running_under4++;
+	} else if ((nr_running() > 1) && (nr_running() <= 2)) {
+		ctn_nr_running_over2++;
+		ctn_nr_running_over3 = 0;
+		ctn_nr_running_over4 = 0;
+		ctn_nr_running_under2 = 0;
+		ctn_nr_running_under3++;
+		ctn_nr_running_under4++;
+	} else if ((nr_running() > 2) && (nr_running() <= 3)) {
+		ctn_nr_running_over2++;
+		ctn_nr_running_over3++;
+		ctn_nr_running_over4 = 0;
+		ctn_nr_running_under2 = 0;
+		ctn_nr_running_under3 = 0;
+		ctn_nr_running_under4++;
+	} else if (nr_running() > 3) {
+		ctn_nr_running_over2++;
+		ctn_nr_running_over3++;
+		ctn_nr_running_over4++;
+		ctn_nr_running_under2 = 0;
+		ctn_nr_running_under3 = 0;
+		ctn_nr_running_under4 = 0;
+	}
+
+	if (soc_is_exynos4412()) {
+		if ((cpu_online(3) == 0) && (nr_running() >= 2)) {
+			if (ctn_nr_running_over2 >= 4) {		/* over 400ms, tunnable */
+				cpu_up(3);
+			}
+		} else if ((cpu_online(2) == 0) && (nr_running() >= 3)) {
+			if (ctn_nr_running_over3 >= 4) {		/* over 400ms, tunnable */
+				cpu_up(2);
+			}
+		} else if ((cpu_online(1) == 0) && (nr_running() >= 4)) {
+			if (ctn_nr_running_over4 >= 8) {		/* over 800ms, tunnable */
+				cpu_up(1);
+			}
+		}
+	} else {
+		if (cpu_online(1) == 0) {
+			if (ctn_nr_running_over2 >= 8) {		/* over 800ms, tunnable */
+				cpu_up(1);
+				ctn_nr_running_over2 = 0;
+			}
+		}
+	} /* end of else */
+	if (soc_is_exynos4412()) {
+		if ((cpu_online(1) == 1) && (nr_running() < 4)) {
+			if (ctn_nr_running_under4 >= 8) {		/* over 800ms, tunnable */
+				cpu_down(1);
+			}
+		} else if ((cpu_online(2) == 1) && (nr_running() < 3)) {
+			if (ctn_nr_running_under3 >= 8) {		/* over 800ms, tunnable */
+				cpu_down(2);
+			}
+		} else if ((cpu_online(3) == 1) && (nr_running() < 2)) {
+			if (ctn_nr_running_under2 >= 8) {		/* over 800ms, tunnable */
+				cpu_down(3);
+			}
+		}
+	} else {
+		if (cpu_online(1) == 1) {
+			if (ctn_nr_running_under2 >= 8) {		/* over 800ms, tunnable */
+				cpu_down(1);
+				ctn_nr_running_under2 = 0;
+			}
+		}
+	} /* end of else */
+}
+
+static int hotplug_cpufreq_transition(struct notifier_block *nb,
+					unsigned long val, void *data)
+{
+	struct cpufreq_freqs *freqs = (struct cpufreq_freqs *)data;
+
+	if ((val == CPUFREQ_POSTCHANGE) && can_hotplug)
+		exynos4_integrated_dvfs_hotplug(freqs->old, freqs->new);
+
+	return 0;
+}
+
+static struct notifier_block dvfs_hotplug = {
+	.notifier_call = hotplug_cpufreq_transition,
+};
+
+static int hotplug_pm_transition(struct notifier_block *nb,
+					unsigned long val, void *data)
+{
+	switch (val) {
+	case PM_SUSPEND_PREPARE:
+		can_hotplug = 0;
+		ctn_highestlevel_cnt = 0;
+		ctn_lowestlevel_cnt = 0;
+		break;
+	case PM_POST_RESTORE:
+	case PM_POST_SUSPEND:
+		can_hotplug = 1;
+		break;
+	}
+
+	return 0;
+}
+
+static struct notifier_block pm_hotplug = {
+	.notifier_call = hotplug_pm_transition,
+};
+
+/*
+ * Note : This function should be called after intialization of CPUFreq
+ * driver for exynos4. The cpufreq_frequency_table for exynos4 should be
+ * established before calling this function.
+ */
+static int __init exynos4_integrated_dvfs_hotplug_init(void)
+{
+	int i;
+	struct cpufreq_frequency_table *table;
+	unsigned int freq;
+
+	total_num_target_freq = 0;
+	ctn_highestlevel_cnt = 0;
+	ctn_lowestlevel_cnt = 0;
+	ctn_nr_running_over2 = 0;
+	ctn_nr_running_over3 = 0;
+	ctn_nr_running_over4 = 0;
+	ctn_nr_running_under2 = 0;
+	ctn_nr_running_under3 = 0;
+	ctn_nr_running_under4 = 0;
+
+	can_hotplug = 1;
+
+	table = cpufreq_frequency_get_table(0);
+	if (IS_ERR(table)) {
+		printk(KERN_ERR "%s: Check loading cpufreq before\n", __func__);
+		return PTR_ERR(table);
+	}
+
+	for (i = 0; table[i].frequency != CPUFREQ_TABLE_END; i++) {
+		freq = table[i].frequency;
+
+		if (freq != CPUFREQ_ENTRY_INVALID && freq > freq_max)
+			freq_max = freq;
+		else if (freq != CPUFREQ_ENTRY_INVALID && freq_min > freq)
+			freq_min = freq;
+	}
+
+	register_pm_notifier(&pm_hotplug);
+
+	return cpufreq_register_notifier(&dvfs_hotplug,
+					 CPUFREQ_TRANSITION_NOTIFIER);
+}
+
+late_initcall(exynos4_integrated_dvfs_hotplug_init);
diff --git a/arch/arm/mach-exynos/exynos4-smc.c b/arch/arm/mach-exynos/exynos4-smc.c
new file mode 100644
index 0000000..08795fa
--- /dev/null
+++ b/arch/arm/mach-exynos/exynos4-smc.c
@@ -0,0 +1,52 @@
+#include <linux/types.h>
+#include <mach/smc.h>
+
+#ifndef __ASSEMBLY__
+u32 exynos_smc(u32 cmd, u32 arg1, u32 arg2, u32 arg3)
+{
+	register u32 reg0 __asm__("r0") = cmd;
+	register u32 reg1 __asm__("r1") = arg1;
+	register u32 reg2 __asm__("r2") = arg2;
+	register u32 reg3 __asm__("r3") = arg3;
+
+	__asm__ volatile (
+#ifdef REQUIRES_SEC
+		".arch_extension sec\n"
+#endif
+		"smc	0\n"
+		: "+r"(reg0), "+r"(reg1), "+r"(reg2), "+r"(reg3)
+	);
+
+	return reg0;
+}
+
+u32 exynos_smc_readsfr(u32 addr, u32 *val)
+{
+	register u32 reg0 __asm__("r0") = SMC_CMD_REG;
+	register u32 reg1 __asm__("r1") = SMC_REG_ID_SFR_R(addr);
+	register u32 reg2 __asm__("r2") = 0;
+	register u32 reg3 __asm__("r3") = 0;
+
+	__asm__ volatile (
+#ifdef REQUIRES_SEC
+		".arch_extension sec\n"
+#endif
+		"smc	0\n"
+		: "+r"(reg0), "+r"(reg1), "+r"(reg2), "+r"(reg3)
+	);
+
+	if (reg0 == SMC_CMD_REG) {
+		if (!reg1)
+			*val = reg2;
+		return reg1;
+	}
+
+	if (!reg0)
+		*val = reg2;
+
+	return reg0;
+}
+
+#endif
+
+
diff --git a/arch/arm/mach-exynos/gc1-gpio.c b/arch/arm/mach-exynos/gc1-gpio.c
new file mode 100644
index 0000000..674d293
--- /dev/null
+++ b/arch/arm/mach-exynos/gc1-gpio.c
@@ -0,0 +1,528 @@
+/*
+ *  linux/arch/arm/mach-exynos/midas-gpio.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * EXYNOS - GPIO setting in set board
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/gpio.h>
+#include <linux/serial_core.h>
+#include <plat/devs.h>
+#include <plat/gpio-cfg.h>
+#include <plat/regs-serial.h>
+#include <mach/gpio-midas.h>
+#include <plat/cpu.h>
+#include <mach/pmu.h>
+
+struct gpio_init_data {
+	uint num;
+	uint cfg;
+	uint val;
+	uint pud;
+	uint drv;
+};
+
+/*
+ * GC1 GPIO Init Table
+ */
+static struct gpio_init_data m0_init_gpios[] = {
+
+	{EXYNOS4_GPD0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPD0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1},
+
+	{EXYNOS4_GPD1(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* GSENSE_SDA_1.8V */
+	{EXYNOS4_GPD1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* GSENSE_SCL_1.8V */
+
+	{EXYNOS4_GPX0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* PS_ALS_INT */
+	{EXYNOS4_GPX0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPX0(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPX0(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4_GPX0(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4_GPX0(7), S3C_GPIO_SFN(0xF), S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* AP_PMIC_IRQ */
+
+	{EXYNOS4_GPX1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4_GPX1(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* TELE_KEY_F */
+
+	{EXYNOS4_GPX2(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* KEY_S1 */
+	{EXYNOS4_GPX2(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* KEY_S2 */
+	{EXYNOS4_GPX2(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* TELE_KEY */
+	{EXYNOS4_GPX2(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* FUEL_ALERT */
+	{EXYNOS4_GPX2(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* BT_HOST_WAKEUP */
+
+	{EXYNOS4_GPX3(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* BT_WAKE */
+	{EXYNOS4_GPX3(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WIDE_KEY */
+	{EXYNOS4_GPX3(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* T_FLASH_DETECT */
+
+	{EXYNOS4_GPK3(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_CMD */
+	{EXYNOS4_GPK3(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(0) */
+	{EXYNOS4_GPK3(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(1) */
+	{EXYNOS4_GPK3(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(2) */
+	{EXYNOS4_GPK3(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(3) */
+
+	{EXYNOS4_GPY0(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4_GPY0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4_GPY0(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4_GPY0(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+
+	{EXYNOS4_GPY1(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4_GPY1(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4_GPY1(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4_GPY1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+
+	{EXYNOS4_GPY2(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+
+	{EXYNOS4212_GPJ0(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_ZERO,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV4}, /* WLAN_EN */
+
+	{EXYNOS4212_GPJ1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV3}, /* CAM_MCLK */
+
+	{EXYNOS4212_GPM2(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV3}, /* VTCAM_MCLK */
+};
+
+/*
+ * GC1 GPIO Sleep Table
+ */
+static unsigned int m0_sleep_gpio_table[][3] = {
+	{EXYNOS4_GPA0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+	{EXYNOS4_GPA0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+
+	{EXYNOS4_GPA1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+#if defined(CONFIG_SEC_MODEM)
+	{EXYNOS4_GPA1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC(IPC_RXD) */
+	{EXYNOS4_GPA1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC(IPC_TXD) */
+#else
+	{EXYNOS4_GPA1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* AP_FLM_RXD */
+	/*
+	 * UART3-TXD : It should be pulled up during sleep, if this uart is
+	 * used for PC connection like a factory command program.
+	 * Otherwise, a PC might get null characters like noise.
+	 * In addition, LPA mode is also applied to this comment, because
+	 * LPA mode invokes this GPIO sleep configuration.
+	 */
+	{EXYNOS4_GPA1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, /* AP_FLM_TXD */
+#endif
+
+	{EXYNOS4_GPB(0),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(1),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(2),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(3),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(4),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPB(5),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+	{EXYNOS4_GPB(6),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(7),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPC0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPC0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPC0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPC0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPC0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPC1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPC1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPC1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPC1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPC1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPD0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPD0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPD0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPD0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPD1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPD1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPD1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPD1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPF0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPF0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPF0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPF0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPF0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPF1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPF1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPF1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF1(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF1(7),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPF2(0),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPF2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPF2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF2(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPF2(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+
+	{EXYNOS4_GPF3(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF3(1),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF3(2),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF3(3),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF3(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF3(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPK0(0),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK0(1),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK0(2),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK0(3),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK0(4),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK0(5),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK0(6),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPK1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPK1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPK1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPK1(3),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK1(4),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK1(5),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK1(6),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPK2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPK2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPK3(0),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPK3(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPL0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPL0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPL0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPL0(3),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL0(4),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+/*	{EXYNOS4_GPL0(5),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE}, */
+	{EXYNOS4_GPL0(6),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+/*	{EXYNOS4_GPL0(7),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE}, */
+
+	{EXYNOS4_GPL1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPL1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+/*	{EXYNOS4_GPL1(2),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE}, */
+
+	{EXYNOS4_GPL2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPL2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPL2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPL2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPL2(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPL2(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPY0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPY1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPY2(0),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPY3(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY3(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY3(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY3(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY3(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY3(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY3(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY3(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPY4(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY4(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY4(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY4(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY4(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY4(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY4(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY4(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPY5(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY5(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY5(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY5(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY5(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY5(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY5(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY5(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPY6(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY6(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY6(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY6(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY6(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY6(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY6(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY6(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPZ(0),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPZ(1),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPZ(2),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPZ(3),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPZ(4),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPZ(5),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPZ(6),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	/* Exynos4212 specific gpio */
+	{EXYNOS4212_GPJ0(0),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4212_GPJ0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPJ0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPJ0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPJ0(4),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4212_GPJ0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPJ0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPJ0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPJ1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPJ1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPJ1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPJ1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPJ1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPM0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPM0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPM1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /*HWREV*/
+	{EXYNOS4212_GPM1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /*HWREV*/
+	{EXYNOS4212_GPM1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /*HWREV*/
+	{EXYNOS4212_GPM1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /*HWREV*/
+	{EXYNOS4212_GPM1(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPM2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4212_GPM2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4212_GPM2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPM2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPM3(0),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	{EXYNOS4212_GPM3(1),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	{EXYNOS4212_GPM3(2),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	{EXYNOS4212_GPM3(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM3(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM3(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM3(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM3(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPM4(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM4(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM4(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM4(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM4(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM4(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM4(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM4(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPV0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPV1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV1(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV1(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPV2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV2(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV2(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPV3(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV3(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV3(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV3(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV3(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV3(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV3(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV3(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPV4(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV4(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+}; /* GC1_sleep_gpio_table */
+
+/*
+ * GC1 Rev0.1 (HW EMUL REV0.4) GPIO Sleep Table
+ */
+static unsigned int m0_sleep_gpio_table_rev01[][3] = {
+	{EXYNOS4_GPF0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /*GYRO_INT*/
+	{EXYNOS4_GPL0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /*POWER_LED*/
+	{EXYNOS4_GPL2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /*GYRO_DE*/
+	{EXYNOS4212_GPM0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /*MOT_EN*/
+	{EXYNOS4212_GPM0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /*SAMBAZ*/
+};
+
+/*
+ * GC1 Rev0.2 (HW MAIN REV0.0) GPIO Sleep Table
+ */
+static unsigned int m0_sleep_gpio_table_rev02[][3] = {
+	{EXYNOS4_GPF0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /*NC*/
+	{EXYNOS4_GPL0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /*NC*/
+	{EXYNOS4_GPL0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /*NC*/
+	{EXYNOS4_GPL2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /*NC*/
+	{EXYNOS4_GPL2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /*NC*/
+};
+
+struct m0_sleep_table {
+	unsigned int (*ptr)[3];
+	int size;
+};
+
+#define GPIO_TABLE(_ptr) \
+	{.ptr = _ptr, \
+	.size = ARRAY_SIZE(_ptr)} \
+
+#define GPIO_TABLE_NULL \
+	{.ptr = NULL, \
+	.size = 0} \
+
+/* in order to distinguish SLEEP GPIO of HW version */
+static struct m0_sleep_table m0_sleep_table[] = {
+	GPIO_TABLE(m0_sleep_gpio_table),	/* HWID(0x0) - GC1 HWREV0.3 */
+	GPIO_TABLE(m0_sleep_gpio_table_rev01),	/* HWID(0x1) - GC1 HWREV0.4 */
+	GPIO_TABLE(m0_sleep_gpio_table_rev02),	/* HWID(0x2) - GC1 MAIN 0.0 */
+};
+
+static void config_sleep_gpio_table(int array_size,
+				    unsigned int (*gpio_table)[3])
+{
+	u32 i, gpio;
+
+	for (i = 0; i < array_size; i++) {
+		gpio = gpio_table[i][0];
+		s3c_gpio_slp_cfgpin(gpio, gpio_table[i][1]);
+		s3c_gpio_slp_setpull_updown(gpio, gpio_table[i][2]);
+	}
+}
+
+void m0_config_sleep_gpio_table(void)
+{
+	int i;
+	int index = min(ARRAY_SIZE(m0_sleep_table), system_rev + 1);
+
+	for (i = 0; i < index; i++) {
+		if (m0_sleep_table[i].ptr == NULL)
+			continue;
+
+		config_sleep_gpio_table(m0_sleep_table[i].size,
+				m0_sleep_table[i].ptr);
+	}
+}
+
+/* To save power consumption, gpio pin set before enterling sleep */
+void midas_config_sleep_gpio_table(void)
+{
+	m0_config_sleep_gpio_table();
+}
+
+/* Intialize gpio set in midas board */
+void midas_config_gpio_table(void)
+{
+	u32 i, gpio;
+
+	printk(KERN_DEBUG "%s\n", __func__);
+
+	for (i = 0; i < ARRAY_SIZE(m0_init_gpios); i++) {
+		gpio = m0_init_gpios[i].num;
+		if (gpio <= EXYNOS4212_GPV4(1)) {
+			s3c_gpio_cfgpin(gpio, m0_init_gpios[i].cfg);
+			s3c_gpio_setpull(gpio, m0_init_gpios[i].pud);
+
+			if (m0_init_gpios[i].val != S3C_GPIO_SETPIN_NONE)
+				gpio_set_value(gpio, m0_init_gpios[i].val);
+
+			s5p_gpio_set_drvstr(gpio, m0_init_gpios[i].drv);
+		}
+	}
+}
diff --git a/arch/arm/mach-exynos/gc1-power.c b/arch/arm/mach-exynos/gc1-power.c
new file mode 100644
index 0000000..175a579
--- /dev/null
+++ b/arch/arm/mach-exynos/gc1-power.c
@@ -0,0 +1,791 @@
+/*
+ * midas-power.c - Power Management of MIDAS Project
+ *
+ *  Copyright (C) 2011 Samsung Electrnoics
+ *  Chiwoong Byun <woong.byun@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/i2c.h>
+#include <linux/regulator/machine.h>
+#include <plat/gpio-cfg.h>
+#include <mach/gpio-midas.h>
+#include <mach/irqs.h>
+
+#include <linux/mfd/max8997.h>
+#include <linux/mfd/max77686.h>
+#include <linux/mfd/max77693.h>
+
+#if defined(CONFIG_REGULATOR_S5M8767)
+#include <linux/mfd/s5m87xx/s5m-pmic.h>
+#include <linux/mfd/s5m87xx/s5m-core.h>
+#endif
+
+
+#ifdef CONFIG_REGULATOR_MAX77686
+/* max77686 */
+
+#ifdef CONFIG_SND_SOC_WM8994
+static struct regulator_consumer_supply ldo3_supply[] = {
+	REGULATOR_SUPPLY("AVDD2", NULL),
+	REGULATOR_SUPPLY("CPVDD", NULL),
+	REGULATOR_SUPPLY("DBVDD1", NULL),
+	REGULATOR_SUPPLY("DBVDD2", NULL),
+	REGULATOR_SUPPLY("DBVDD3", NULL),
+};
+#else
+static struct regulator_consumer_supply ldo3_supply[] = {};
+#endif
+
+static struct regulator_consumer_supply ldo5_supply[] = {
+	REGULATOR_SUPPLY("vcc_1.8v", NULL),
+	REGULATOR_SUPPLY("touchkey", NULL),
+};
+
+static struct regulator_consumer_supply ldo8_supply[] = {
+	REGULATOR_SUPPLY("vmipi_1.0v", NULL),
+	REGULATOR_SUPPLY("VDD10", "s5p-mipi-dsim.0"),
+	REGULATOR_SUPPLY("vdd", "exynos4-hdmi"),
+	REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"),
+};
+
+static struct regulator_consumer_supply ldo10_supply[] = {
+	REGULATOR_SUPPLY("vmipi_1.8v", NULL),
+	REGULATOR_SUPPLY("VDD18", "s5p-mipi-dsim.0"),
+	REGULATOR_SUPPLY("vdd_osc", "exynos4-hdmi"),
+};
+
+static struct regulator_consumer_supply ldo11_supply[] = {
+	REGULATOR_SUPPLY("vabb1_1.95v", NULL),
+};
+
+static struct regulator_consumer_supply ldo12_supply[] = {
+	REGULATOR_SUPPLY("votg_3.0v", NULL),
+};
+
+static struct regulator_consumer_supply ldo13_supply[] = {
+	REGULATOR_SUPPLY("ois_1.5v", NULL),
+};
+
+static struct regulator_consumer_supply ldo14_supply[] = {
+	REGULATOR_SUPPLY("vabb2_1.95v", NULL),
+};
+
+static struct regulator_consumer_supply ldo17_supply[] = {
+	REGULATOR_SUPPLY("cam_sensor_core_1.2v", NULL),
+};
+
+static struct regulator_consumer_supply ldo18_supply[] = {
+	REGULATOR_SUPPLY("touch_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo19_supply[] = {
+	REGULATOR_SUPPLY("cam_sensor_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo21_supply[] = {
+	REGULATOR_SUPPLY("vtf_2.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo23_supply[] = {
+	REGULATOR_SUPPLY("cam_isp_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo24_supply[] = {
+	REGULATOR_SUPPLY("touch", NULL),
+};
+
+static struct regulator_consumer_supply ldo25_supply[] = {
+	REGULATOR_SUPPLY("cam_sensor_2.8v", NULL),
+	REGULATOR_SUPPLY("VCI", "s6e8aa0"),
+};
+
+static struct regulator_consumer_supply ldo26_supply[] = {
+	REGULATOR_SUPPLY("mot_3.3v", NULL),
+};
+
+static struct regulator_consumer_supply max77686_buck1[] = {
+	REGULATOR_SUPPLY("vdd_mif", NULL),
+	REGULATOR_SUPPLY("vdd_mif", "exynos4412-busfreq"),
+};
+
+static struct regulator_consumer_supply max77686_buck2 =
+	REGULATOR_SUPPLY("vdd_arm", NULL);
+
+static struct regulator_consumer_supply max77686_buck3[] = {
+	REGULATOR_SUPPLY("vdd_int", NULL),
+	REGULATOR_SUPPLY("vdd_int", "exynoss4412-busfreq"),
+};
+
+static struct regulator_consumer_supply max77686_buck4[] = {
+	REGULATOR_SUPPLY("vdd_g3d", NULL),
+	REGULATOR_SUPPLY("vdd_g3d", "mali_dev.0"),
+};
+
+static struct regulator_consumer_supply max77686_buck9 =
+	REGULATOR_SUPPLY("cam_isp_1.2v", NULL);
+
+static struct regulator_consumer_supply max77686_enp32khz[] = {
+	REGULATOR_SUPPLY("lpo_in", "bcm47511"),
+	REGULATOR_SUPPLY("lpo", "bcm4334_bluetooth"),
+};
+
+#define REGULATOR_INIT(_ldo, _name, _min_uV, _max_uV, _always_on, _ops_mask, \
+		       _disabled)					\
+	static struct regulator_init_data _ldo##_init_data = {		\
+		.constraints = {					\
+			.name = _name,					\
+			.min_uV = _min_uV,				\
+			.max_uV = _max_uV,				\
+			.always_on	= _always_on,			\
+			.boot_on	= _always_on,			\
+			.apply_uV	= 1,				\
+			.valid_ops_mask = _ops_mask,			\
+			.state_mem = {					\
+				.disabled	= _disabled,		\
+				.enabled	= !(_disabled),		\
+			}						\
+		},							\
+		.num_consumer_supplies = ARRAY_SIZE(_ldo##_supply),	\
+		.consumer_supplies = &_ldo##_supply[0],			\
+	};
+
+REGULATOR_INIT(ldo3, "VCC_1.8V_AP", 1800000, 1800000, 1, 0, 0);
+REGULATOR_INIT(ldo5, "VCC_1.8V_IO", 1800000, 1800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo8, "VMIPI_1.0V", 1000000, 1000000, 1,
+	       REGULATOR_CHANGE_STATUS, 0);
+REGULATOR_INIT(ldo10, "VMIPI_1.8V", 1800000, 1800000, 1,
+	       REGULATOR_CHANGE_STATUS, 0);
+REGULATOR_INIT(ldo11, "VABB1_1.95V", 1950000, 1950000, 1,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo12, "VUOTG_3.0V", 3000000, 3000000, 1,
+	       REGULATOR_CHANGE_STATUS, 0);
+REGULATOR_INIT(ldo13, "OIS_1.5V", 1500000, 1500000, 0,
+	       REGULATOR_CHANGE_STATUS, 0);
+REGULATOR_INIT(ldo14, "VABB2_1.95V", 1950000, 1950000, 1,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo17, "CAM_SENSOR_CORE_1.2V", 1200000, 1200000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo18, "TSP_VDD_1.8V", 1800000, 1800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo19, "CAM_SENSOR_1.8V", 1800000, 1800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo21, "VTF_2.8V", 2800000, 2800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo23, "CAM_ISP_1.8V", 1800000, 1800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo24, "TSP_AVDD_3.3V", 3300000, 3300000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo25, "CAM_SENSOR_2.8V", 2800000, 2800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo26, "MOT_3.3V", 3300000, 3300000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+
+static struct regulator_init_data max77686_buck1_data = {
+	.constraints = {
+		.name = "vdd_mif range",
+		.min_uV = 850000,
+		.max_uV = 1050000,
+		.always_on = 1,
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_buck1),
+	.consumer_supplies = max77686_buck1,
+};
+
+static struct regulator_init_data max77686_buck2_data = {
+	.constraints = {
+		.name = "vdd_arm range",
+		.min_uV = 850000,
+		.max_uV = 1500000,
+		.apply_uV = 1,
+		.always_on = 1,
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &max77686_buck2,
+};
+
+static struct regulator_init_data max77686_buck3_data = {
+	.constraints = {
+		.name = "vdd_int range",
+		.min_uV = 850000,
+		.max_uV = 1100000,
+		.always_on = 1,
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_buck3),
+	.consumer_supplies = max77686_buck3,
+};
+
+static struct regulator_init_data max77686_buck4_data = {
+	.constraints = {
+		.name = "vdd_g3d range",
+		.min_uV = 850000,
+		.max_uV = 1075000,
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+		REGULATOR_CHANGE_STATUS,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_buck4),
+	.consumer_supplies = max77686_buck4,
+};
+
+static struct regulator_init_data max77686_buck9_data = {
+	.constraints = {
+		.name = "CAM_ISP_1.2V",
+		.min_uV = 1000000,
+		.max_uV = 1200000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+		REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.disabled = 1,
+		},
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &max77686_buck9,
+};
+
+static struct regulator_init_data max77686_enp32khz_data = {
+	.constraints = {
+		.name = "32KHZ_PMIC",
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.enabled	= 1,
+			.disabled	= 0,
+		},
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_enp32khz),
+	.consumer_supplies = max77686_enp32khz,
+};
+
+static struct max77686_regulator_data max77686_regulators[] = {
+	{MAX77686_BUCK1, &max77686_buck1_data,},
+	{MAX77686_BUCK2, &max77686_buck2_data,},
+	{MAX77686_BUCK3, &max77686_buck3_data,},
+	{MAX77686_BUCK4, &max77686_buck4_data,},
+	{MAX77686_BUCK9, &max77686_buck9_data,},
+	{MAX77686_LDO3, &ldo3_init_data,},
+	{MAX77686_LDO5, &ldo5_init_data,},
+	{MAX77686_LDO8, &ldo8_init_data,},
+	{MAX77686_LDO10, &ldo10_init_data,},
+	{MAX77686_LDO11, &ldo11_init_data,},
+	{MAX77686_LDO12, &ldo12_init_data,},
+	{MAX77686_LDO13, &ldo13_init_data,},
+	{MAX77686_LDO14, &ldo14_init_data,},
+	{MAX77686_LDO17, &ldo17_init_data,},
+	{MAX77686_LDO18, &ldo18_init_data,},
+	{MAX77686_LDO19, &ldo19_init_data,},
+	{MAX77686_LDO21, &ldo21_init_data,},
+	{MAX77686_LDO23, &ldo23_init_data,},
+	{MAX77686_LDO24, &ldo24_init_data,},
+	{MAX77686_LDO25, &ldo25_init_data,},
+	{MAX77686_LDO26, &ldo26_init_data,},
+	{MAX77686_P32KH, &max77686_enp32khz_data,},
+};
+
+struct max77686_opmode_data max77686_opmode_data[MAX77686_REG_MAX] = {
+	[MAX77686_LDO3] = {MAX77686_LDO3, MAX77686_OPMODE_NORMAL},
+	[MAX77686_LDO8] = {MAX77686_LDO8, MAX77686_OPMODE_STANDBY},
+	[MAX77686_LDO10] = {MAX77686_LDO10, MAX77686_OPMODE_STANDBY},
+	[MAX77686_LDO11] = {MAX77686_LDO11, MAX77686_OPMODE_STANDBY},
+	[MAX77686_LDO12] = {MAX77686_LDO12, MAX77686_OPMODE_STANDBY},
+	[MAX77686_LDO14] = {MAX77686_LDO14, MAX77686_OPMODE_STANDBY},
+	[MAX77686_BUCK1] = {MAX77686_BUCK1, MAX77686_OPMODE_STANDBY},
+	[MAX77686_BUCK2] = {MAX77686_BUCK2, MAX77686_OPMODE_STANDBY},
+	[MAX77686_BUCK3] = {MAX77686_BUCK3, MAX77686_OPMODE_STANDBY},
+	[MAX77686_BUCK4] = {MAX77686_BUCK4, MAX77686_OPMODE_STANDBY},
+};
+
+struct max77686_platform_data exynos4_max77686_info = {
+	.num_regulators = ARRAY_SIZE(max77686_regulators),
+	.regulators = max77686_regulators,
+	.irq_gpio	= GPIO_PMIC_IRQ,
+	.irq_base	= IRQ_BOARD_PMIC_START,
+	.wakeup		= 1,
+
+	.opmode_data = max77686_opmode_data,
+	.ramp_rate = MAX77686_RAMP_RATE_27MV,
+	.wtsr_smpl = MAX77686_WTSR_ENABLE | MAX77686_SMPL_ENABLE,
+
+	.buck234_gpio_dvs = {
+		/* Use DVS2 register of each bucks to supply stable power
+		 * after sudden reset */
+		{GPIO_PMIC_DVS1, 1},
+		{GPIO_PMIC_DVS2, 0},
+		{GPIO_PMIC_DVS3, 0},
+	},
+	.buck234_gpio_selb = {
+		GPIO_BUCK2_SEL,
+		GPIO_BUCK3_SEL,
+		GPIO_BUCK4_SEL,
+	},
+	.buck2_voltage[0] = 1100000,	/* 1.1V */
+	.buck2_voltage[1] = 1100000,	/* 1.1V */
+	.buck2_voltage[2] = 1100000,	/* 1.1V */
+	.buck2_voltage[3] = 1100000,	/* 1.1V */
+	.buck2_voltage[4] = 1100000,	/* 1.1V */
+	.buck2_voltage[5] = 1100000,	/* 1.1V */
+	.buck2_voltage[6] = 1100000,	/* 1.1V */
+	.buck2_voltage[7] = 1100000,	/* 1.1V */
+
+	.buck3_voltage[0] = 1100000,	/* 1.1V */
+	.buck3_voltage[1] = 1000000,	/* 1.0V */
+	.buck3_voltage[2] = 1100000,	/* 1.1V */
+	.buck3_voltage[3] = 1100000,	/* 1.1V */
+	.buck3_voltage[4] = 1100000,	/* 1.1V */
+	.buck3_voltage[5] = 1100000,	/* 1.1V */
+	.buck3_voltage[6] = 1100000,	/* 1.1V */
+	.buck3_voltage[7] = 1100000,	/* 1.1V */
+
+	.buck4_voltage[0] = 1100000,	/* 1.1V */
+	.buck4_voltage[1] = 1000000,	/* 1.0V */
+	.buck4_voltage[2] = 1100000,	/* 1.1V */
+	.buck4_voltage[3] = 1100000,	/* 1.1V */
+	.buck4_voltage[4] = 1100000,	/* 1.1V */
+	.buck4_voltage[5] = 1100000,	/* 1.1V */
+	.buck4_voltage[6] = 1100000,	/* 1.1V */
+	.buck4_voltage[7] = 1100000,	/* 1.1V */
+};
+
+#endif /* CONFIG_REGULATOR_MAX77686 */
+
+void midas_power_set_muic_pdata(void *pdata, int gpio)
+{
+	gpio_request(gpio, "AP_PMIC_IRQ");
+	s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
+	s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+}
+
+void midas_power_gpio_init(void)
+{
+}
+
+#ifdef CONFIG_MFD_MAX77693
+static struct regulator_consumer_supply safeout1_supply[] = {
+	REGULATOR_SUPPLY("safeout1", NULL),
+};
+
+static struct regulator_consumer_supply safeout2_supply[] = {
+	REGULATOR_SUPPLY("safeout2", NULL),
+};
+
+static struct regulator_consumer_supply charger_supply[] = {
+	REGULATOR_SUPPLY("vinchg1", "charger-manager.0"),
+	REGULATOR_SUPPLY("vinchg1", NULL),
+};
+
+static struct regulator_init_data safeout1_init_data = {
+	.constraints	= {
+		.name		= "safeout1 range",
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.always_on	= 0,
+		.boot_on	= 1,
+		.state_mem	= {
+			.enabled = 1,
+		},
+	},
+	.num_consumer_supplies	= ARRAY_SIZE(safeout1_supply),
+	.consumer_supplies	= safeout1_supply,
+};
+
+static struct regulator_init_data safeout2_init_data = {
+	.constraints	= {
+		.name		= "safeout2 range",
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.always_on	= 0,
+		.boot_on	= 0,
+		.state_mem	= {
+			.disabled = 1,
+		},
+	},
+	.num_consumer_supplies	= ARRAY_SIZE(safeout2_supply),
+	.consumer_supplies	= safeout2_supply,
+};
+
+static struct regulator_init_data charger_init_data = {
+	.constraints	= {
+		.name		= "CHARGER",
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS |
+		REGULATOR_CHANGE_CURRENT,
+		.boot_on	= 1,
+		.min_uA		= 60000,
+		.max_uA		= 2580000,
+	},
+	.num_consumer_supplies	= ARRAY_SIZE(charger_supply),
+	.consumer_supplies	= charger_supply,
+};
+
+struct max77693_regulator_data max77693_regulators[] = {
+	{MAX77693_ESAFEOUT1, &safeout1_init_data,},
+	{MAX77693_ESAFEOUT2, &safeout2_init_data,},
+	{MAX77693_CHARGER, &charger_init_data,},
+};
+
+#endif /* CONFIG_MFD_MAX77693 */
+
+#if defined(CONFIG_REGULATOR_S5M8767)
+/* S5M8767 Regulator */
+
+#ifdef CONFIG_SND_SOC_WM8994
+static struct regulator_consumer_supply s5m_ldo3_supply[] = {
+	REGULATOR_SUPPLY("AVDD2", NULL),
+	REGULATOR_SUPPLY("CPVDD", NULL),
+	REGULATOR_SUPPLY("DBVDD1", NULL),
+	REGULATOR_SUPPLY("DBVDD2", NULL),
+	REGULATOR_SUPPLY("DBVDD3", NULL),
+};
+#else
+static struct regulator_consumer_supply s5m_ldo3_supply[] = {};
+#endif
+
+static struct regulator_consumer_supply s5m_ldo4_supply[] = {
+	REGULATOR_SUPPLY("vddq_pre_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply s5m_ldo8_supply[] = {
+	REGULATOR_SUPPLY("vmipi_1.0v", NULL),
+	REGULATOR_SUPPLY("VDD10", "s5p-mipi-dsim.0"),
+	REGULATOR_SUPPLY("vdd", "exynos4-hdmi"),
+	REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"),
+};
+
+static struct regulator_consumer_supply s5m_ldo9_supply[] = {
+	REGULATOR_SUPPLY("cam_isp_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply s5m_ldo10_supply[] = {
+	REGULATOR_SUPPLY("vmipi_1.8v", NULL),
+	REGULATOR_SUPPLY("VDD18", "s5p-mipi-dsim.0"),
+	REGULATOR_SUPPLY("vdd_osc", "exynos4-hdmi"),
+};
+
+static struct regulator_consumer_supply s5m_ldo11_supply[] = {
+	REGULATOR_SUPPLY("vabb1_1.95v", NULL),
+};
+
+static struct regulator_consumer_supply s5m_ldo12_supply[] = {
+	REGULATOR_SUPPLY("votg_3.0v", NULL),
+};
+
+static struct regulator_consumer_supply s5m_ldo14_supply[] = {
+	REGULATOR_SUPPLY("vabb2_1.95v", NULL),
+};
+
+static struct regulator_consumer_supply s5m_ldo20_supply[] = {
+	REGULATOR_SUPPLY("touch", NULL),
+};
+
+static struct regulator_consumer_supply s5m_ldo21_supply[] = {
+	REGULATOR_SUPPLY("mot_3.3v", NULL),
+};
+
+static struct regulator_consumer_supply s5m_ldo22_supply[] = {
+	REGULATOR_SUPPLY("cam_sensor_2.8v", NULL),
+	REGULATOR_SUPPLY("VCI", "s6e8aa0"),
+};
+
+static struct regulator_consumer_supply s5m_ldo23_supply[] = {
+	REGULATOR_SUPPLY("vtf_2.8v", NULL),
+};
+
+static struct regulator_consumer_supply s5m_ldo24_supply[] = {
+	REGULATOR_SUPPLY("led_3.3v", NULL),
+};
+
+static struct regulator_consumer_supply s5m_ldo25_supply[] = {
+	REGULATOR_SUPPLY("cam_sensor_core_1.2v", NULL),
+};
+
+static struct regulator_consumer_supply s5m_ldo26_supply[] = {
+	REGULATOR_SUPPLY("cam_sensor_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply s5m_ldo27_supply[] = {
+	REGULATOR_SUPPLY("ois_1.5v", NULL),
+};
+
+static struct regulator_consumer_supply s5m_ldo28_supply[] = {
+	REGULATOR_SUPPLY("touch_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply s5m8767_buck1[] = {
+	REGULATOR_SUPPLY("vdd_mif", NULL),
+	REGULATOR_SUPPLY("vdd_mif", "exynos4212-busfreq"),
+};
+
+static struct regulator_consumer_supply s5m8767_buck2 =
+	REGULATOR_SUPPLY("vdd_arm", NULL);
+
+static struct regulator_consumer_supply s5m8767_buck3[] = {
+	REGULATOR_SUPPLY("vdd_int", NULL),
+	REGULATOR_SUPPLY("vdd_int", "exynos4212-busfreq"),
+};
+
+static struct regulator_consumer_supply s5m8767_buck4[] = {
+	REGULATOR_SUPPLY("vdd_g3d", NULL),
+	REGULATOR_SUPPLY("vdd_g3d", "mali_dev.0"),
+};
+
+static struct regulator_consumer_supply s5m8767_buck6 =
+	REGULATOR_SUPPLY("cam_isp_1.2v", NULL);
+
+static struct regulator_consumer_supply s5m8767_enp32khz[] = {
+	REGULATOR_SUPPLY("lpo_in", "bcm47511"),
+	REGULATOR_SUPPLY("lpo", "bcm4334_bluetooth"),
+};
+
+#define S5M_REGULATOR_INIT(_ldo, _name, _min_uV, _max_uV, _always_on, \
+			_ops_mask, _disabled)				\
+	static struct regulator_init_data _ldo##_init_data = {		\
+		.constraints = {					\
+			.name = _name,					\
+			.min_uV = _min_uV,				\
+			.max_uV = _max_uV,				\
+			.always_on	= _always_on,			\
+			.boot_on	= _always_on,			\
+			.apply_uV	= 1,				\
+			.valid_ops_mask = _ops_mask,			\
+			.state_mem = {					\
+				.disabled	= _disabled,		\
+				.enabled	= !(_disabled),		\
+			}						\
+		},							\
+		.num_consumer_supplies = ARRAY_SIZE(_ldo##_supply),	\
+		.consumer_supplies = &_ldo##_supply[0],			\
+	};
+
+S5M_REGULATOR_INIT(s5m_ldo3, "VCC_1.8V_AP", 1800000, 1800000, 1, 0, 0);
+S5M_REGULATOR_INIT(s5m_ldo8, "VMIPI_1.0V", 1000000, 1000000, 1,
+	       REGULATOR_CHANGE_STATUS, 0);
+S5M_REGULATOR_INIT(s5m_ldo9, "CAM_ISP_1.8V", 1800000, 1800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+S5M_REGULATOR_INIT(s5m_ldo10, "VMIPI_1.8V", 1800000, 1800000, 1,
+	       REGULATOR_CHANGE_STATUS, 0);
+S5M_REGULATOR_INIT(s5m_ldo11, "VABB1_1.95V", 1950000, 1950000, 1,
+	       REGULATOR_CHANGE_STATUS, 1);
+S5M_REGULATOR_INIT(s5m_ldo12, "VUOTG_3.0V", 3000000, 3000000, 1,
+	       REGULATOR_CHANGE_STATUS, 0);
+S5M_REGULATOR_INIT(s5m_ldo14, "VABB2_1.95V", 1950000, 1950000, 1,
+	       REGULATOR_CHANGE_STATUS, 1);
+S5M_REGULATOR_INIT(s5m_ldo20, "TSP_AVDD_3.3V", 3300000, 3300000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+S5M_REGULATOR_INIT(s5m_ldo21, "MOT_3.3V", 3300000, 3300000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+S5M_REGULATOR_INIT(s5m_ldo22, "CAM_SENSOR_2.8V", 2800000, 2800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+S5M_REGULATOR_INIT(s5m_ldo23, "VTF_2.8V", 2800000, 2800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+S5M_REGULATOR_INIT(s5m_ldo24, "LED_3.3V", 3300000, 3300000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+S5M_REGULATOR_INIT(s5m_ldo25, "CAM_SENSOR_CORE_1.2V", 1200000, 1200000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+S5M_REGULATOR_INIT(s5m_ldo26, "CAM_SENSOR_1.8V", 1800000, 1800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+S5M_REGULATOR_INIT(s5m_ldo27, "OIS_1.5V", 1500000, 1500000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+S5M_REGULATOR_INIT(s5m_ldo28, "TSP_VDD_1.8V", 1800000, 1800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+
+
+static struct regulator_init_data s5m8767_buck1_data = {
+	.constraints = {
+		.name = "vdd_mif range",
+		.min_uV = 850000,
+		.max_uV = 1100000,
+		.always_on = 1,
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(s5m8767_buck1),
+	.consumer_supplies = s5m8767_buck1,
+};
+
+static struct regulator_init_data s5m8767_buck2_data = {
+	.constraints = {
+		.name = "vdd_arm range",
+		.min_uV = 850000,
+		.max_uV = 1500000,
+		.always_on = 1,
+		.apply_uV = 1,
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &s5m8767_buck2,
+};
+
+static struct regulator_init_data s5m8767_buck3_data = {
+	.constraints = {
+		.name = "vdd_int range",
+		.min_uV = 850000,
+		.max_uV = 1100000,
+		.always_on = 1,
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(s5m8767_buck3),
+	.consumer_supplies = s5m8767_buck3,
+};
+
+static struct regulator_init_data s5m8767_buck4_data = {
+	.constraints = {
+		.name = "vdd_g3d range",
+		.min_uV = 850000,
+		.max_uV = 1075000,
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+		REGULATOR_CHANGE_STATUS,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(s5m8767_buck4),
+	.consumer_supplies = s5m8767_buck4,
+};
+
+static struct regulator_init_data s5m8767_buck6_data = {
+	.constraints = {
+		.name = "CAM_ISP_1.2V",
+		.min_uV = 1000000,
+		.max_uV = 1200000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+		REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.disabled = 1,
+		},
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &s5m8767_buck6,
+};
+
+static struct regulator_init_data s5m8767_enp32khz_data = {
+	.constraints = {
+		.name = "32KHZ_PMIC",
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.enabled	= 1,
+			.disabled	= 0,
+		},
+	},
+	.num_consumer_supplies = ARRAY_SIZE(s5m8767_enp32khz),
+	.consumer_supplies = s5m8767_enp32khz,
+};
+
+static struct s5m_regulator_data s5m8767_regulators[] = {
+	{S5M8767_BUCK1, &s5m8767_buck1_data,},
+	{S5M8767_BUCK2, &s5m8767_buck2_data,},
+	{S5M8767_BUCK3, &s5m8767_buck3_data,},
+	{S5M8767_BUCK4, &s5m8767_buck4_data,},
+	{S5M8767_BUCK6, &s5m8767_buck6_data,},
+	{S5M8767_LDO3, &s5m_ldo3_init_data,},
+	{S5M8767_LDO8, &s5m_ldo8_init_data,},
+	{S5M8767_LDO9, &s5m_ldo9_init_data,},
+	{S5M8767_LDO10, &s5m_ldo10_init_data,},
+	{S5M8767_LDO11, &s5m_ldo11_init_data,},
+	{S5M8767_LDO12, &s5m_ldo12_init_data,},
+	{S5M8767_LDO14, &s5m_ldo14_init_data,},
+	{S5M8767_LDO20, &s5m_ldo20_init_data,},
+	{S5M8767_LDO21, &s5m_ldo21_init_data,},
+	{S5M8767_LDO22, &s5m_ldo22_init_data,},
+	{S5M8767_LDO23, &s5m_ldo23_init_data,},
+	{S5M8767_LDO24, &s5m_ldo24_init_data,},
+	{S5M8767_LDO25, &s5m_ldo25_init_data,},
+	{S5M8767_LDO26, &s5m_ldo26_init_data,},
+	{S5M8767_LDO27, &s5m_ldo27_init_data,},
+	{S5M8767_LDO28, &s5m_ldo28_init_data,},
+};
+
+struct s5m_opmode_data s5m8767_opmode_data[S5M8767_REG_MAX] = {
+	[S5M8767_BUCK1] = {S5M8767_BUCK1, S5M_OPMODE_STANDBY},
+	[S5M8767_BUCK2] = {S5M8767_BUCK2, S5M_OPMODE_STANDBY},
+	[S5M8767_BUCK3] = {S5M8767_BUCK3, S5M_OPMODE_STANDBY},
+	[S5M8767_BUCK4] = {S5M8767_BUCK4, S5M_OPMODE_STANDBY},
+	[S5M8767_LDO3] = {S5M8767_LDO3, S5M_OPMODE_NORMAL},
+	[S5M8767_LDO8] = {S5M8767_LDO8, S5M_OPMODE_STANDBY},
+	[S5M8767_LDO10] = {S5M8767_LDO10, S5M_OPMODE_STANDBY},
+	[S5M8767_LDO11] = {S5M8767_LDO11, S5M_OPMODE_STANDBY},
+	[S5M8767_LDO12] = {S5M8767_LDO12, S5M_OPMODE_STANDBY},
+	[S5M8767_LDO14] = {S5M8767_LDO14, S5M_OPMODE_STANDBY},
+};
+
+struct s5m_platform_data exynos4_s5m8767_info = {
+	.device_type	= S5M8767X,
+	.num_regulators = ARRAY_SIZE(s5m8767_regulators),
+	.regulators = s5m8767_regulators,
+	.buck2_ramp_enable	= true,
+	.buck3_ramp_enable	= true,
+	.buck4_ramp_enable	= true,
+	.irq_gpio	= GPIO_PMIC_IRQ,
+	.irq_base	= IRQ_BOARD_PMIC_START,
+	.wakeup		= 1,
+
+	.opmode_data = s5m8767_opmode_data,
+	.wtsr_smpl		= 1,
+
+	.buck2_voltage[0] = 1100000,	/* 1.1V */
+	.buck2_voltage[1] = 1100000,	/* 1.1V */
+	.buck2_voltage[2] = 1100000,	/* 1.1V */
+	.buck2_voltage[3] = 1100000,	/* 1.1V */
+	.buck2_voltage[4] = 1100000,	/* 1.1V */
+	.buck2_voltage[5] = 1100000,	/* 1.1V */
+	.buck2_voltage[6] = 1100000,	/* 1.1V */
+	.buck2_voltage[7] = 1100000,	/* 1.1V */
+
+	.buck3_voltage[0] = 1100000,	/* 1.1V */
+	.buck3_voltage[1] = 1100000,	/* 1.1V */
+	.buck3_voltage[2] = 1100000,	/* 1.1V */
+	.buck3_voltage[3] = 1100000,	/* 1.1V */
+	.buck3_voltage[4] = 1100000,	/* 1.1V */
+	.buck3_voltage[5] = 1100000,	/* 1.1V */
+	.buck3_voltage[6] = 1100000,	/* 1.1V */
+	.buck3_voltage[7] = 1100000,	/* 1.1V */
+
+	.buck4_voltage[0] = 1100000,	/* 1.1V */
+	.buck4_voltage[1] = 1100000,	/* 1.1V */
+	.buck4_voltage[2] = 1100000,	/* 1.1V */
+	.buck4_voltage[3] = 1100000,	/* 1.1V */
+	.buck4_voltage[4] = 1100000,	/* 1.1V */
+	.buck4_voltage[5] = 1100000,	/* 1.1V */
+	.buck4_voltage[6] = 1100000,	/* 1.1V */
+	.buck4_voltage[7] = 1100000,	/* 1.1V */
+
+	.buck_ramp_delay = 25,
+	.buck_default_idx = 1,
+
+	.buck_gpios[0]		= EXYNOS4212_GPM3(0),
+	.buck_gpios[1]		= EXYNOS4212_GPM3(1),
+	.buck_gpios[2]		= EXYNOS4212_GPM3(2),
+
+	.buck_ds[0]		= EXYNOS4_GPF3(1),
+	.buck_ds[1]		= EXYNOS4_GPF3(2),
+	.buck_ds[2]		= EXYNOS4_GPF3(3),
+
+	.buck2_init		= 1100000,
+	.buck3_init		= 1000000,
+	.buck4_init		= 1000000,
+};
+
+/* End of S5M8767 */
+#endif
+
+void midas_power_init(void)
+{
+	printk(KERN_INFO "%s\n", __func__);
+}
diff --git a/arch/arm/mach-exynos/headsmp.S b/arch/arm/mach-exynos/headsmp.S
new file mode 100644
index 0000000..617509e
--- /dev/null
+++ b/arch/arm/mach-exynos/headsmp.S
@@ -0,0 +1,41 @@
+/*
+ *  linux/arch/arm/mach-exynos/headsmp.S
+ *
+ *  Cloned from linux/arch/arm/mach-realview/headsmp.S
+ *
+ *  Copyright (c) 2003 ARM Limited
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+	__CPUINIT
+
+/*
+ * exynos4 specific entry point for secondary CPUs.  This provides
+ * a "holding pen" into which all secondary cores are held until we're
+ * ready for them to initialise.
+ */
+ENTRY(exynos_secondary_startup)
+	mrc	p15, 0, r0, c0, c0, 5
+	and	r0, r0, #15
+	adr	r4, 1f
+	ldmia	r4, {r5, r6}
+	sub	r4, r4, r5
+	add	r6, r6, r4
+pen:	ldr	r7, [r6]
+	cmp	r7, r0
+	bne	pen
+
+	/*
+	 * we've been released from the holding pen: secondary_stack
+	 * should now contain the SVC stack for this core
+	 */
+	b	secondary_startup
+
+1:	.long	.
+	.long	pen_release
diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
new file mode 100644
index 0000000..d16df01
--- /dev/null
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -0,0 +1,166 @@
+/* linux arch/arm/mach-exynos/hotplug.c
+ *
+ *  Cloned from linux/arch/arm/mach-realview/hotplug.c
+ *
+ *  Copyright (C) 2002 ARM Ltd.
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/smp.h>
+#include <linux/completion.h>
+#include <linux/io.h>
+
+#include <asm/cacheflush.h>
+
+#include <plat/cpu.h>
+#include <mach/regs-pmu.h>
+
+extern volatile int pen_release;
+
+static inline void cpu_enter_lowpower_a9(void)
+{
+	unsigned int v;
+
+	flush_cache_all();
+	asm volatile(
+	"	mcr	p15, 0, %1, c7, c5, 0\n"
+	"	mcr	p15, 0, %1, c7, c10, 4\n"
+	/*
+	 * Turn off coherency
+	 */
+	"	mrc	p15, 0, %0, c1, c0, 1\n"
+	"	bic	%0, %0, %3\n"
+	"	mcr	p15, 0, %0, c1, c0, 1\n"
+	"	mrc	p15, 0, %0, c1, c0, 0\n"
+	"	bic	%0, %0, %2\n"
+	"	mcr	p15, 0, %0, c1, c0, 0\n"
+	  : "=&r" (v)
+	  : "r" (0), "Ir" (CR_C), "Ir" (0x40)
+	  : "cc");
+}
+
+static inline void cpu_enter_lowpower_a15(void)
+{
+	unsigned int v;
+
+	asm volatile(
+	"       mrc     p15, 0, %0, c1, c0, 0\n"
+	"       bic     %0, %0, %1\n"
+	"       mcr     p15, 0, %0, c1, c0, 0\n"
+	  : "=&r" (v)
+	  : "Ir" (CR_C)
+	  : "cc");
+
+	flush_cache_all();
+
+	asm volatile(
+	/*
+	* Turn off coherency
+	*/
+	"       mrc     p15, 0, %0, c1, c0, 1\n"
+	"       bic     %0, %0, %1\n"
+	"       mcr     p15, 0, %0, c1, c0, 1\n"
+	: "=&r" (v)
+	: "Ir" (0x40)
+	: "cc");
+
+	isb();
+	dsb();
+}
+
+static inline void cpu_leave_lowpower(void)
+{
+	unsigned int v;
+
+	asm volatile(
+	"mrc	p15, 0, %0, c1, c0, 0\n"
+	"	orr	%0, %0, %1\n"
+	"	mcr	p15, 0, %0, c1, c0, 0\n"
+	"	mrc	p15, 0, %0, c1, c0, 1\n"
+	"	orr	%0, %0, %2\n"
+	"	mcr	p15, 0, %0, c1, c0, 1\n"
+	  : "=&r" (v)
+	  : "Ir" (CR_C), "Ir" (0x40)
+	  : "cc");
+}
+
+static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
+{
+	for (;;) {
+		/* make cpu1 to be turned off at next WFI command */
+		if ((cpu >= 1) && (cpu < NR_CPUS))
+			__raw_writel(0, S5P_ARM_CORE_CONFIGURATION(cpu));
+
+		/*
+		 * here's the WFI
+		 */
+		asm(".word	0xe320f003\n"
+		    :
+		    :
+		    : "memory", "cc");
+
+		if (pen_release == cpu) {
+			/*
+			 * OK, proper wakeup, we're done
+			 */
+			break;
+		}
+
+		/*
+		 * Getting here, means that we have come out of WFI without
+		 * having been woken up - this shouldn't happen
+		 *
+		 * Just note it happening - when we're woken, we can report
+		 * its occurrence.
+		 */
+		(*spurious)++;
+	}
+}
+
+int platform_cpu_kill(unsigned int cpu)
+{
+	return 1;
+}
+
+/*
+ * platform-specific code to shutdown a CPU
+ *
+ * Called with IRQs disabled
+ */
+void platform_cpu_die(unsigned int cpu)
+{
+	int spurious = 0;
+
+	/*
+	 * we're ready for shutdown now, so do it
+	 */
+	if (soc_is_exynos5250())
+		cpu_enter_lowpower_a15();
+	else
+		cpu_enter_lowpower_a9();
+	platform_do_lowpower(cpu, &spurious);
+
+	/*
+	 * bring this CPU back into the world of cache
+	 * coherency, and then restore interrupts
+	 */
+	cpu_leave_lowpower();
+
+	if (spurious)
+		pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
+}
+
+int platform_cpu_disable(unsigned int cpu)
+{
+	/*
+	 * we don't allow CPU 0 to be shutdown (it is still too special
+	 * e.g. clock tick interrupts)
+	 */
+	return cpu == 0 ? -EPERM : 0;
+}
diff --git a/arch/arm/mach-exynos/idle-exynos4.S b/arch/arm/mach-exynos/idle-exynos4.S
new file mode 100644
index 0000000..a8038e3
--- /dev/null
+++ b/arch/arm/mach-exynos/idle-exynos4.S
@@ -0,0 +1,241 @@
+/* linux/arch/arm/mach-exynos/idle-exynos4.S
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS4210 AFTR/LPA idle support
+ * Based on S3C2410 sleep code by:
+ *	Ben Dooks, (c) 2004 Simtec Electronics
+ *
+ * Based on PXA/SA1100 sleep code by:
+ *	Nicolas Pitre, (c) 2002 Monta Vista Software Inc
+ *	Cliff Brake, (c) 2001
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/memory.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <plat/map-base.h>
+#include <plat/map-s5p.h>
+#include <mach/smc.h>
+#include <mach/map-exynos4.h>
+
+	.text
+
+	/*
+	 * exynos4_enter_lp
+	 *
+	 * entry:
+	 *	r1 = v:p offset
+	 */
+
+ENTRY(exynos4_enter_lp)
+	stmfd	sp!, { r3 - r12, lr }
+
+	adr	r0, sleep_save_misc
+
+	mrc	p15, 0, r2, c15, c0, 0	@ read power control register
+	str	r2, [r0], #4
+
+	mrc	p15, 0, r2, c15, c0, 1	@ read diagnostic register
+	str	r2, [r0], #4
+
+	ldr	r3, =resume_with_mmu
+	bl	cpu_suspend
+
+	mov	r0, sp
+
+	mrc	p15, 0, r1, c2, c0, 0	@ TTB 0
+	mov	r2, r1, lsr #14		@ get TTB0 base
+	mov	r1, r2, lsl #14
+	bl	exynos4_flush_cache
+
+	adr	r0, sys_pwr_conf_addr
+	ldr	r1, [r0]
+	ldr	r2, [r1]
+	bic	r2, r2, #(1<<16)
+	str	r2, [r1]
+
+#ifdef CONFIG_ARM_TRUSTZONE
+	ldr	r0, =SMC_CMD_CPU0AFTR
+	mov	r1, #0
+	mov	r2, #0
+	mov	r3, #0
+#ifdef REQUIRES_SEC
+	.arch_extension sec
+#endif
+	smc	0
+#else
+	dsb
+	wfi
+#endif
+
+	/* Restore original sp */
+	mov	r0, sp
+	add	r0, r0, #4
+	ldr	sp, [r0]
+
+	mov	r0, #0
+	b	early_wakeup
+
+resume_with_mmu:
+#ifdef CONFIG_CACHE_L2X0
+	/* Enable L2 cache */
+#ifdef CONFIG_ARM_TRUSTZONE
+	ldr	r0, =SMC_CMD_L2X0CTRL
+	mov	r1, #1
+	mov	r2, #0
+	mov	r3, #0
+#ifdef REQUIRES_SEC
+	.arch_extension sec
+#endif
+	smc	0
+#else
+	mov	r0, #1
+	ldr	r1, =S5P_VA_L2CC
+	str	r0, [r1, #0x100]
+#endif
+#endif
+	adr	r0, sleep_save_misc
+
+#ifdef CONFIG_ARM_TRUSTZONE
+	ldr	r1, [r0], #4
+	ldr	r2, [r0], #4
+	ldr	r0, =SMC_CMD_C15RESUME
+	mov	r3, #0
+#ifdef REQUIRES_SEC
+	.arch_extension sec
+#endif
+	smc	0
+#else
+	ldr	r1, [r0], #4
+	mcr	p15, 0, r1, c15, c0, 0	@ write power control register
+
+	ldr	r1, [r0], #4
+	mcr	p15, 0, r1, c15, c0, 1	@ write diagnostic register
+#endif
+
+	mov	r0, #1
+early_wakeup:
+
+	ldmfd	sp!, { r3 - r12, pc }
+
+	.ltorg
+
+	/*
+	 * sleep magic, to allow the bootloader to check for an valid
+	 * image to resume to. Must be the first word before the
+	 * s3c_cpu_resume entry.
+	 */
+
+	.word	0x2bedf00d
+
+sleep_save_misc:
+	.long	0
+	.long	0
+
+	.global sys_pwr_conf_addr
+sys_pwr_conf_addr:
+	.long	0
+
+	.global l2x0_save
+l2x0_save:
+	.word	0
+	.word	0
+	.word	0
+
+	.global scu_save
+scu_save:
+	.word	0
+	.word	0
+
+	/*
+	 * exynos4_idle_resume
+	 *
+	 * resume code entry for IROM to call
+	 *
+	 * we must put this code here in the data segment as we have no
+	 * other way of restoring the stack pointer after sleep, and we
+	 * must not write to the code segment (code is read-only)
+	 */
+
+ENTRY(exynos4_idle_resume)
+	/* SCU enable */
+	ldr	r1, =0x10500000
+	adr	r0, scu_save
+
+	ldr	r5, [r0]
+	ldr	r6, [r0, #4]
+
+	str	r5, [r1, #0x30]
+	str	r6, [r1]
+
+#ifdef CONFIG_CACHE_L2X0
+	/* Restore register value for L2X0 */
+	adr	r0, l2x0_save
+
+	ldr	r5, [r0], #4	@ Data latency
+	ldr	r6, [r0], #4	@ Tag latency
+	ldr	r7, [r0], #4	@ prepatch
+
+#ifdef CONFIG_ARM_TRUSTZONE
+	mov	r1, r5
+	mov	r2, r6
+	mov	r3, r7
+
+	ldr	r0, =SMC_CMD_L2X0SETUP1
+
+#ifdef REQUIRES_SEC
+	.arch_extension sec
+#endif
+	smc	0
+
+	ldr	r0, =SMC_CMD_L2X0SETUP2
+	ldr	r1, =0x3
+	ldr	r2, =0x7C470001
+	ldr	r3, =0xC200FFFF
+
+#ifdef REQUIRES_SEC
+	.arch_extension sec
+#endif
+	smc	0
+#else
+	ldr	r0, =EXYNOS4_PA_L2CC
+
+	str	r5, [r0, #L2X0_TAG_LATENCY_CTRL]
+	str	r6, [r0, #L2X0_DATA_LATENCY_CTRL]
+	str	r7, [r0, #L2X0_PREFETCH_CTRL]
+
+	/*
+	 * Set Power ctrl register for L2X0
+	 */
+	mov	r1, #0x3
+	str	r1, [r0, #L2X0_POWER_CTRL]
+
+	ldr	r1, [r0, #L2X0_AUX_CTRL]
+	ldr	r2, =0x7C470001
+	ldr	r3, =0xC200FFFF
+
+	and	r1, r1, r3
+	orr	r1, r1, r2
+
+	str	r1, [r0, #L2X0_AUX_CTRL]
+
+#endif
+#endif
+	b	cpu_resume
diff --git a/arch/arm/mach-exynos/idle-exynos5.S b/arch/arm/mach-exynos/idle-exynos5.S
new file mode 100644
index 0000000..a3575ca
--- /dev/null
+++ b/arch/arm/mach-exynos/idle-exynos5.S
@@ -0,0 +1,210 @@
+/* linux/arch/arm/mach-exynos/idle-exynos5.S
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS5 AFTR/LPA idle support
+ * Based on S3C2410 sleep code by:
+ *	Ben Dooks, (c) 2004 Simtec Electronics
+ *
+ * Based on PXA/SA1100 sleep code by:
+ *	Nicolas Pitre, (c) 2002 Monta Vista Software Inc
+ *	Cliff Brake, (c) 2001
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/memory.h>
+#include <plat/map-base.h>
+#include <plat/map-s5p.h>
+#include <mach/smc.h>
+
+	.text
+
+	/*
+	 * exynos5_enter_lp
+	 *
+	 * entry:
+	 *	r1 = v:p offset
+	 */
+
+ENTRY(exynos5_enter_lp)
+	stmfd	sp!, { r3 - r12, lr }
+
+	adr	r0, sleep_save_misc
+
+#ifdef CONFIG_ARM_TRUSTZONE
+	mrc	p15, 0, r2, c1, c0, 1	@ read aux control register
+	str	r2, [r0], #4
+#endif
+	mrc	p15, 1, r2, c9, c0, 2	@ read l2 control register
+	str	r2, [r0], #4
+	mrc	p15, 1, r2, c15, c0, 3	@ read l2 prefetch register
+	str	r2, [r0], #4
+
+	ldr	r3, =resume_with_mmu
+	bl	cpu_suspend
+
+	bl	exynos5_L1_dcache_flush
+
+	adr	r0, sys_pwr_conf_addr
+	ldr	r1, [r0]
+	ldr	r2, [r1]
+	bic	r2, r2, #(1<<16)
+	str	r2, [r1]
+
+#ifdef CONFIG_ARM_TRUSTZONE
+        ldr     r0, =SMC_CMD_CPU0AFTR
+        mov     r1, #0
+        mov     r2, #0
+        mov     r3, #0
+        smc     0
+#else
+	dsb
+	wfi
+#endif
+
+	/* Restore original sp */
+	mov	r0, sp
+	add	r0, r0, #4
+	ldr	sp, [r0]
+
+	mov	r0, #0
+	b	early_wakeup
+
+resume_with_mmu:
+	adr	r4, sleep_save_misc
+
+#ifdef CONFIG_ARM_TRUSTZONE
+        mov	r3, #0
+
+        ldr	r0, =SMC_CMD_REG
+	ldr	r1, =SMC_REG_ID_CP15(1, 0, 0, 1)	@ aux control register
+	ldr	r2, [r4], #4
+	smc	0
+        ldr	r0, =SMC_CMD_REG
+	ldr	r1, =SMC_REG_ID_CP15(9, 1, 0, 2)	@ L2 control register
+	ldr	r2, [r4], #4
+	smc	0
+        ldr	r0, =SMC_CMD_REG
+	ldr	r1, =SMC_REG_ID_CP15(15, 1, 0, 3)	@ L2 prefetch register
+	ldr	r2, [r4], #4
+	smc	0
+#else
+	ldr	r2, [r4], #4
+	mcr	p15, 1, r2, c9, c0, 2			@ L2 control register
+	ldr	r2, [r4], #4
+	mcr	p15, 1, r2, c15, c0, 3			@ L2 prefetch register
+#endif
+	mov	r0, #1
+early_wakeup:
+
+	ldmfd	sp!, { r3 - r12, pc }
+
+	.ltorg
+
+	/*
+	 * sleep magic, to allow the bootloader to check for an valid
+	 * image to resume to. Must be the first word before the
+	 * s3c_cpu_resume entry.
+	 */
+
+	.word	0x2bedf00d
+
+sleep_save_misc:
+	.long	0
+	.long	0
+	.long	0
+
+	.global sys_pwr_conf_addr
+sys_pwr_conf_addr:
+	.long	0
+
+	/*
+	 * exynos5_L1_dcache_flush
+	 *
+	 * L1 only dcache flush function
+	 *
+	 * When enter lowpower cpuidle mode, It is need to L1 only flush function.
+	 */
+ENTRY(exynos5_L1_dcache_flush)
+	dmb					@ ensure ordering with previous memory accesses
+	mrc	p15, 1, r0, c0, c0, 1		@ read clidr
+	ands	r3, r0, #0x7000000		@ extract loc from clidr
+	mov	r3, r3, lsr #23			@ left align loc bit field
+	beq	skip				@ if loc is 0, then no need to clean
+	mov	r10, #0				@ start clean at cache level 0
+loop1:
+	add	r2, r10, r10, lsr #1		@ work out 3x current cache level
+	mov	r1, r0, lsr r2			@ extract cache type bits from clidr
+	and	r1, r1, #7			@ mask of the bits for current cache only
+	cmp	r1, #2				@ see what cache we have at this level
+	blt	skip				@ skip if no cache, or just i-cache
+	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
+	isb					@ isb to sych the new cssr&csidr
+	mrc	p15, 1, r1, c0, c0, 0		@ read the new csidr
+	and	r2, r1, #7			@ extract the length of the cache lines
+	add	r2, r2, #4			@ add 4 (line length offset)
+	ldr	r4, =0x3ff
+	ands	r4, r4, r1, lsr #3		@ find maximum number on the way size
+	clz	r5, r4				@ find bit position of way size increment
+	ldr	r7, =0x7fff
+	ands	r7, r7, r1, lsr #13		@ extract max number of the index size
+loop2:
+	mov	r9, r4				@ create working copy of max way size
+loop3:
+ ARM(	orr	r11, r10, r9, lsl r5	)	@ factor way and cache number into r11
+ THUMB(	lsl	r6, r9, r5		)
+ THUMB(	orr	r11, r10, r6		)	@ factor way and cache number into r11
+ ARM(	orr	r11, r11, r7, lsl r2	)	@ factor index number into r11
+ THUMB(	lsl	r6, r7, r2		)
+ THUMB(	orr	r11, r11, r6		)	@ factor index number into r11
+	mcr	p15, 0, r11, c7, c14, 2		@ clean & invalidate by set/way
+	subs	r9, r9, #1			@ decrement the way
+	bge	loop3
+	subs	r7, r7, #1			@ decrement the index
+	bge	loop2
+skip:
+	mov	r10, #0				@ swith back to cache level 0
+	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
+	dsb
+	isb
+	mov	pc, lr
+ENDPROC(exynos5_L1_dcache_flush)
+
+	/*
+	 * exynos5_idle_resume
+	 *
+	 * resume code entry for IROM to call
+	 *
+	 * we must put this code here in the data segment as we have no
+	 * other way of restoring the stack pointer after sleep, and we
+	 * must not write to the code segment (code is read-only)
+	 */
+
+ENTRY(exynos5_idle_resume)
+	/*
+	 * To use JTEG after wakeup from power mode
+	 * Set DBGEN, NIDEN, SPIDEN, SPNIDEN on TZPC1
+	 */
+	ldr	r0, =0x10110810
+	mov	r1, #0xf
+	str	r1, [r0]
+	dsb
+	isb
+
+	b	cpu_resume
diff --git a/arch/arm/mach-exynos/include/mach/asv.h b/arch/arm/mach-exynos/include/mach/asv.h
new file mode 100644
index 0000000..6fda670
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/asv.h
@@ -0,0 +1,124 @@
+/* linux/arch/arm/mach-exynos/include/mach/asv.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * EXYNOS4 - Adoptive Support Voltage Header file
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_ASV_H
+#define __ASM_ARCH_ASV_H __FILE__
+
+#ifdef CONFIG_EXYNOS4_CPUFREQ
+
+#include <mach/regs-pmu.h>
+#include <mach/regs-pmu5.h>
+
+#include <plat/cpu.h>
+
+#define JUDGE_TABLE_END			NULL
+
+#define LOOP_CNT			10
+
+extern unsigned int exynos_result_of_asv;
+
+enum exynos4x12_abb_member {
+	ABB_INT,
+	ABB_MIF,
+	ABB_G3D,
+	ABB_ARM,
+};
+
+static inline void exynos4x12_set_abb_member(enum exynos4x12_abb_member abb_target,
+					     unsigned int abb_mode_value)
+{
+	unsigned int tmp;
+
+	if (abb_mode_value != ABB_MODE_BYPASS)
+		tmp = S5P_ABB_INIT;
+	else
+		tmp = S5P_ABB_INIT_BYPASS;
+
+	tmp |= abb_mode_value;
+
+	if (!soc_is_exynos5250())
+		__raw_writel(tmp, S5P_ABB_MEMBER(abb_target));
+	else if (abb_target == ABB_INT)
+		__raw_writel(tmp, EXYNOS5_ABB_MEMBER(ABB_INT));
+	else if (abb_target == ABB_MIF)
+		__raw_writel(tmp, EXYNOS5_ABB_MEMBER(ABB_MIF));
+	else if (abb_target == ABB_G3D)
+		__raw_writel(tmp, EXYNOS5_ABB_MEMBER(ABB_G3D));
+	else if (abb_target == ABB_ARM)
+		__raw_writel(tmp, EXYNOS5_ABB_MEMBER(ABB_ARM));
+}
+
+static inline void exynos4x12_set_abb(unsigned int abb_mode_value)
+{
+	unsigned int tmp;
+
+	pr_debug("EXYNOS4X12 ABB MODE : %d(mV)\n", 600 + (abb_mode_value * 50));
+
+	if (abb_mode_value != ABB_MODE_BYPASS)
+		tmp = S5P_ABB_INIT;
+	else
+		tmp = S5P_ABB_INIT_BYPASS;
+
+	tmp |= abb_mode_value;
+
+	if (!soc_is_exynos5250()) {
+		__raw_writel(tmp, S5P_ABB_INT);
+		__raw_writel(tmp, S5P_ABB_MIF);
+		__raw_writel(tmp, S5P_ABB_G3D);
+		__raw_writel(tmp, S5P_ABB_ARM);
+	} else {
+		__raw_writel(tmp, EXYNOS5_ABB_MEMBER(ABB_INT));
+		__raw_writel(tmp, EXYNOS5_ABB_MEMBER(ABB_MIF));
+		__raw_writel(tmp, EXYNOS5_ABB_MEMBER(ABB_G3D));
+		__raw_writel(tmp, EXYNOS5_ABB_MEMBER(ABB_ARM));
+	}
+}
+
+static inline int exynos4x12_get_abb_member(enum exynos4x12_abb_member abb_target)
+{
+	return (__raw_readl(S5P_ABB_MEMBER(abb_target)) & 0x1f);
+}
+
+struct asv_judge_table {
+	unsigned int hpm_limit; /* HPM value to decide group of target */
+	unsigned int ids_limit; /* IDS value to decide group of target */
+};
+
+struct samsung_asv {
+	unsigned int pkg_id;			/* fused value for pakage */
+	unsigned int ids_offset;		/* ids_offset of chip */
+	unsigned int ids_mask;			/* ids_mask of chip */
+	unsigned int hpm_result;		/* hpm value of chip */
+	unsigned int ids_result;		/* ids value of chip */
+	int (*check_vdd_arm)(void);		/* check vdd_arm value, this function is selectable */
+	int (*pre_clock_init)(void);		/* clock init function to get hpm */
+	int (*pre_clock_setup)(void);		/* clock setup function to get hpm */
+	/* specific get ids function */
+	int (*get_ids)(struct samsung_asv *asv_info);
+	/* specific get hpm function */
+	int (*get_hpm)(struct samsung_asv *asv_info);
+	/* store into some repository to send result of asv */
+	int (*store_result)(struct samsung_asv *asv_info);
+};
+
+extern int exynos4210_asv_init(struct samsung_asv *asv_info);
+extern int exynos4x12_asv_init(struct samsung_asv *asv_info);
+extern int exynos5250_asv_init(struct samsung_asv *asv_info);
+void exynos4x12_set_abb_member(enum exynos4x12_abb_member abb_target, unsigned int abb_mode_value);
+
+#else
+
+/* left empty to invoke build errors */
+
+#endif
+
+#endif /* __ASM_ARCH_ASV_H */
diff --git a/arch/arm/mach-exynos/include/mach/bcm47511.h b/arch/arm/mach-exynos/include/mach/bcm47511.h
new file mode 100644
index 0000000..b2648eb
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/bcm47511.h
@@ -0,0 +1,27 @@
+/* linux/arm/arch/mach-exynos/include/mach/bcm47511.h
+ *
+ * Platform data  Header for BCM47511(GPS) driver.
+ *
+ * Copyright (c) 2011 Samsung Electronics
+ * Minho Ban <mhban@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef _BCM47511_H
+#define _BCM47511_H
+
+struct bcm47511_platform_data {
+	unsigned int regpu;		/* Power */
+	unsigned int nrst;		/* Reset */
+	unsigned int uart_rxd;		/* Start gpio number of uart */
+	/* Below are machine dependant */
+	unsigned int gps_cntl;		/* Request 26MHz CP clock */
+	const char *reg32khz;		/* regulator id for 32KHz clk */
+};
+
+#endif /* _BCM47511_H */
+
+
diff --git a/arch/arm/mach-exynos/include/mach/board-bluetooth-bcm.h b/arch/arm/mach-exynos/include/mach/board-bluetooth-bcm.h
new file mode 100644
index 0000000..125d7f2
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/board-bluetooth-bcm.h
@@ -0,0 +1,30 @@
+/*
+ * Bluetooth Broadcom GPIO and Low Power Mode control
+ *
+ *  Copyright (C) 2011 Samsung, Inc.
+ *  Copyright (C) 2011 Google, Inc.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __BOARD_BLUETOOTH_BCM4334_H__
+#define __BOARD_BLUETOOTH_BCM4334_H__
+
+#include <linux/serial_core.h>
+
+extern void bcm_bt_lpm_exit_lpm_locked(struct uart_port *uport);
+
+#endif /*  __BOARD_BLUETOOTH_BCM4334_H__  */
diff --git a/arch/arm/mach-exynos/include/mach/board-bluetooth-csr.h b/arch/arm/mach-exynos/include/mach/board-bluetooth-csr.h
new file mode 100644
index 0000000..11514b1
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/board-bluetooth-csr.h
@@ -0,0 +1,30 @@
+/*
+ * Bluetooth CSR GPIO and Low Power Mode control
+ *
+ *  Copyright (C) 2011 Samsung, Inc.
+ *  Copyright (C) 2011 Google, Inc.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __BOARD_BLUETOOTH_CSR8811_H__
+#define __BOARD_BLUETOOTH_CSR8811_H__
+
+#include <linux/serial_core.h>
+
+extern void csr_bt_lpm_exit_lpm_locked(struct uart_port *uport);
+
+#endif /*  __BOARD_BLUETOOTH_BCM4334_H__  */
diff --git a/arch/arm/mach-exynos/include/mach/board-gps.h b/arch/arm/mach-exynos/include/mach/board-gps.h
new file mode 100644
index 0000000..6b7e42a
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/board-gps.h
@@ -0,0 +1,29 @@
+/*
+ * GPS GPIO control
+ *
+ *  Copyright (C) 2012 Samsung, Inc.
+ *  Copyright (C) 2012 Google, Inc.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+
+#ifndef __BOARD_GPS_H__
+#define __BOARD_GPS_H__
+
+extern struct class *sec_class;
+
+#endif /*  __BOARD_GPS_H__  */
diff --git a/arch/arm/mach-exynos/include/mach/board_rev.h b/arch/arm/mach-exynos/include/mach/board_rev.h
new file mode 100644
index 0000000..a5e37a1
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/board_rev.h
@@ -0,0 +1,26 @@
+/* linux/arch/arm/mach-exynos/include/mach/board_rev.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS - board revision support header
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_BOARD_REV_H
+#define __ASM_ARCH_BOARD_REV_H __FILE__
+
+enum {
+	SAMSUNG_BOARD_REV_0_0 = 0x0000,
+	SAMSUNG_BOARD_REV_0_1 = 0x0001
+};
+
+extern int samsung_board_rev;
+
+#define samsung_board_rev_is_0_0() (samsung_board_rev == SAMSUNG_BOARD_REV_0_0)
+#define samsung_board_rev_is_0_1() (samsung_board_rev == SAMSUNG_BOARD_REV_0_1)
+
+#endif /* __ASM_ARCH_BOARD_REV_H */
diff --git a/arch/arm/mach-exynos/include/mach/busfreq.h b/arch/arm/mach-exynos/include/mach/busfreq.h
new file mode 100644
index 0000000..1be7145
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/busfreq.h
@@ -0,0 +1,120 @@
+/* linux/arch/arm/mach-exynos/include/mach/busfreq.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS4 - BUSFreq support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_BUSFREQ_H
+#define __ASM_ARCH_BUSFREQ_H __FILE__
+
+#include <linux/notifier.h>
+#include <linux/earlysuspend.h>
+
+#include <mach/ppmu.h>
+
+#define MAX_LOAD		100
+#define LOAD_HISTORY_SIZE	5
+#define DIVIDING_FACTOR		10000
+
+#define TIMINGROW_OFFSET	0x34
+
+struct opp;
+struct device;
+struct busfreq_table;
+
+struct busfreq_data {
+	bool use;
+	struct device *dev;
+	struct delayed_work worker;
+	struct opp *curr_opp;
+	struct opp *max_opp;
+	struct opp *min_opp;
+	struct regulator *vdd_int;
+	struct regulator *vdd_mif;
+	unsigned int sampling_rate;
+	struct kobject *busfreq_kobject;
+	int table_size;
+	struct busfreq_table *table;
+	unsigned long long *time_in_state;
+	unsigned long long last_time;
+	unsigned int load_history[PPMU_END][LOAD_HISTORY_SIZE];
+	int index;
+
+	struct notifier_block exynos_buspm_notifier;
+	struct notifier_block exynos_reboot_notifier;
+	struct notifier_block exynos_request_notifier;
+	struct early_suspend busfreq_early_suspend_handler;
+	struct attribute_group busfreq_attr_group;
+	int (*init)	(struct device *dev, struct busfreq_data *data);
+	struct opp *(*monitor)(struct busfreq_data *data);
+	void (*target)	(int mif_index, int int_index);
+	unsigned int (*get_int_volt) (unsigned long freq);
+	unsigned int (*get_table_index) (struct opp *opp);
+	void (*busfreq_prepare) (unsigned int index);
+	void (*busfreq_post) (unsigned int index);
+	void (*set_qos) (unsigned int index);
+	void (*busfreq_suspend) (void);
+	void (*busfreq_resume) (void);
+};
+
+struct busfreq_table {
+	unsigned int idx;
+	unsigned int mem_clk;
+	unsigned int volt;
+	unsigned int clk_topdiv;
+	unsigned int clk_dmc0div;
+	unsigned int clk_dmc1div;
+};
+
+void exynos_request_apply(unsigned long freq, struct device *dev);
+struct opp *step_down(struct busfreq_data *data, int step);
+
+#if defined(CONFIG_ARCH_EXYNOS5)
+int exynos5250_init(struct device *dev, struct busfreq_data *data);
+void exynos5250_target(int mif_index, int int_index);
+unsigned int exynos5250_get_int_volt(unsigned long freq);
+unsigned int exynos5250_get_table_index(struct opp *opp);
+struct opp *exynos5250_monitor(struct busfreq_data *data);
+void exynos5250_prepare(unsigned int index);
+void exynos5250_post(unsigned int index);
+void exynos5250_suspend(void);
+void exynos5250_resume(void);
+
+#define exynos4x12_init NULL
+#define exynos4x12_target NULL
+#define exynos4x12_get_int_volt NULL
+#define exynos4x12_get_table_index NULL
+#define exynos4x12_monitor NULL
+#define exynos4x12_prepare NULL
+#define exynos4x12_post NULL
+#define exynos4x12_suspend NULL
+#define exynos4x12_resume NULL
+#elif defined(CONFIG_ARCH_EXYNOS4)
+#define exynos5250_init NULL
+#define exynos5250_target NULL
+#define exynos5250_get_int_volt NULL
+#define exynos5250_get_table_index NULL
+#define exynos5250_monitor NULL
+#define exynos5250_prepare NULL
+#define exynos5250_post NULL
+#define exynos5250_suspend NULL
+#define exynos5250_resume NULL
+
+int exynos4x12_init(struct device *dev, struct busfreq_data *data);
+void exynos4x12_target(int mif_index, int int_index);
+unsigned int exynos4x12_get_int_volt(unsigned long freq);
+unsigned int exynos4x12_get_table_index(struct opp *opp);
+struct opp *exynos4x12_monitor(struct busfreq_data *data);
+void exynos4x12_prepare(unsigned int index);
+void exynos4x12_post(unsigned int index);
+void exynos4x12_set_qos(unsigned int index);
+void exynos4x12_suspend(void);
+void exynos4x12_resume(void);
+#endif
+#endif /* __ASM_ARCH_BUSFREQ_H */
diff --git a/arch/arm/mach-exynos/include/mach/busfreq_exynos4.h b/arch/arm/mach-exynos/include/mach/busfreq_exynos4.h
new file mode 100644
index 0000000..fabd1e8
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/busfreq_exynos4.h
@@ -0,0 +1,103 @@
+/* linux/arch/arm/mach-exynos/include/mach/busfreq_exynos4.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS4 - BUSFreq support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_BUSFREQ_H
+#define __ASM_ARCH_BUSFREQ_H __FILE__
+
+#include <linux/notifier.h>
+#include <linux/earlysuspend.h>
+
+#include <mach/ppmu.h>
+
+#define MAX_LOAD		100
+#define LOAD_HISTORY_SIZE	5
+#define DIVIDING_FACTOR		10000
+
+#define TIMINGROW_OFFSET	0x34
+
+#define EXYNOS4412_DMC_MAX_THRESHOLD	30
+#define EXYNOS4212_DMC_MAX_THRESHOLD	30
+
+extern unsigned int up_threshold;
+extern unsigned int ppmu_threshold;
+extern unsigned int idle_threshold;
+extern unsigned int up_cpu_threshold;
+extern unsigned int max_cpu_threshold;
+extern unsigned int cpu_slope_size;
+extern unsigned int dmc_max_threshold;
+extern unsigned int load_history_size;
+
+struct opp;
+struct device;
+struct busfreq_table;
+
+struct busfreq_data {
+	bool use;
+	struct device *dev;
+	struct delayed_work worker;
+	struct opp *curr_opp;
+	struct opp *max_opp;
+	struct opp *min_opp;
+	struct regulator *vdd_int;
+	struct regulator *vdd_mif;
+	unsigned int sampling_rate;
+	struct kobject *busfreq_kobject;
+	int table_size;
+	struct busfreq_table *table;
+	unsigned long long *time_in_state;
+	unsigned long long last_time;
+	unsigned int load_history[PPMU_END][LOAD_HISTORY_SIZE];
+	int index;
+
+	struct notifier_block exynos_buspm_notifier;
+	struct notifier_block exynos_reboot_notifier;
+	struct notifier_block exynos_request_notifier;
+	struct notifier_block exynos_cpufreq_notifier;
+	struct notifier_block exynos_busqos_notifier;
+	struct early_suspend busfreq_early_suspend_handler;
+	struct attribute_group busfreq_attr_group;
+	int (*init)	(struct device *dev, struct busfreq_data *data);
+	struct opp *(*monitor)(struct busfreq_data *data);
+	void (*target)	(int index);
+	unsigned int (*get_int_volt) (unsigned long index);
+	unsigned int (*get_table_index) (struct opp *opp);
+	void (*busfreq_prepare) (unsigned int index);
+	void (*busfreq_post) (unsigned int index);
+	void (*set_qos) (unsigned int index);
+	void (*busfreq_suspend) (void);
+	void (*busfreq_resume) (void);
+};
+
+struct busfreq_table {
+	unsigned int idx;
+	unsigned int mem_clk;
+	unsigned int volt;
+	unsigned int clk_topdiv;
+	unsigned int clk_dmc0div;
+	unsigned int clk_dmc1div;
+};
+
+void exynos_request_apply(unsigned long freq);
+struct opp *step_down(struct busfreq_data *data, int step);
+
+int exynos4x12_init(struct device *dev, struct busfreq_data *data);
+void exynos4x12_target(int index);
+unsigned int exynos4x12_get_int_volt(unsigned long freq);
+unsigned int exynos4x12_get_table_index(struct opp *opp);
+struct opp *exynos4x12_monitor(struct busfreq_data *data);
+void exynos4x12_prepare(unsigned int index);
+void exynos4x12_post(unsigned int index);
+void exynos4x12_set_qos(unsigned int index);
+void exynos4x12_suspend(void);
+void exynos4x12_resume(void);
+int exynos4x12_find_busfreq_by_volt(unsigned int req_volt, unsigned int *freq);
+#endif /* __ASM_ARCH_BUSFREQ_H */
diff --git a/arch/arm/mach-exynos/include/mach/busfreq_exynos5.h b/arch/arm/mach-exynos/include/mach/busfreq_exynos5.h
new file mode 100644
index 0000000..fe00bd1
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/busfreq_exynos5.h
@@ -0,0 +1,93 @@
+/* linux/arch/arm/mach-exynos/include/mach/busfreq_exynos5.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS4 - BUSFreq support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_BUSFREQ_H
+#define __ASM_ARCH_BUSFREQ_H __FILE__
+
+#include <linux/notifier.h>
+#include <linux/earlysuspend.h>
+
+#include <mach/ppmu.h>
+
+#define MAX_LOAD		100
+#define LOAD_HISTORY_SIZE	5
+#define DIVIDING_FACTOR		10000
+
+#define TIMINGROW_OFFSET	0x34
+
+enum busfreq_level_idx {
+	LV_0,
+	LV_1,
+	LV_2,
+	LV_3,
+	LV_INT_END,
+	LV_MIF_END = LV_3,
+};
+
+struct opp;
+struct device;
+struct busfreq_table;
+
+struct busfreq_data {
+	bool use;
+	struct device *dev[PPMU_TYPE_END];
+	struct delayed_work worker;
+	unsigned long curr_freq[PPMU_TYPE_END];
+	unsigned long max_freq[PPMU_TYPE_END];
+	unsigned long min_freq[PPMU_TYPE_END];
+	struct regulator *vdd_reg[PPMU_TYPE_END];
+	unsigned int sampling_rate;
+	struct kobject *busfreq_kobject;
+	struct busfreq_table *table[PPMU_TYPE_END];
+	unsigned long long time_in_state[PPMU_TYPE_END][LV_INT_END];
+	unsigned long long last_time[PPMU_TYPE_END];
+	unsigned int load_history[PPMU_END][LOAD_HISTORY_SIZE];
+	int index;
+
+	struct notifier_block exynos_buspm_notifier;
+	struct notifier_block exynos_reboot_notifier;
+	struct notifier_block exynos_request_notifier;
+	struct early_suspend busfreq_early_suspend_handler;
+	struct attribute_group busfreq_attr_group;
+	int (*init)	(struct device *dev, struct busfreq_data *data);
+	void (*monitor) (struct busfreq_data *data, struct opp **mif_opp,
+			struct opp **int_opp);
+	void (*target)	(struct busfreq_data *data, enum ppmu_type type, int index);
+	unsigned int (*get_int_volt) (unsigned long freq);
+	int (*get_table_index) (unsigned long freq, enum ppmu_type type);
+	void (*busfreq_prepare) (int index);
+	void (*busfreq_post) (int index);
+	void (*busfreq_suspend) (void);
+	void (*busfreq_resume) (void);
+
+	/* Dividers calculated at boot/probe-time */
+	unsigned int lex_divtable[LV_INT_END];
+	unsigned int r0x_divtable[LV_INT_END];
+	unsigned int r1x_divtable[LV_INT_END];
+	unsigned int cdrex_divtable[LV_MIF_END];
+	unsigned int cdrex2_divtable[LV_MIF_END];
+};
+
+struct busfreq_table {
+	unsigned int idx;
+	unsigned int mem_clk;
+	unsigned int volt;
+	unsigned int clk_topdiv;
+	unsigned int clk_dmc0div;
+	unsigned int clk_dmc1div;
+};
+
+void exynos_request_apply(unsigned long freq);
+unsigned long step_down(struct busfreq_data *data, enum ppmu_type type, int step);
+
+int exynos5250_init(struct device *dev, struct busfreq_data *data);
+#endif /* __ASM_ARCH_BUSFREQ_H */
diff --git a/arch/arm/mach-exynos/include/mach/c2c.h b/arch/arm/mach-exynos/include/mach/c2c.h
new file mode 100644
index 0000000..a422bde
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/c2c.h
@@ -0,0 +1,68 @@
+/* linux/arch/arm/mach-exynos/include/mach/c2c.h
+ *
+ * Copyright 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Platform header file for Samsung C2C Interface driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#ifndef __ASM_PLAT_C2C_H
+#define __ASM_PLAT_C2C_H __FILE__
+
+#define C2C_SHAREDMEM_BASE 0x60000000
+
+enum c2c_opp_mode {
+	C2C_OPP0 = 0,
+	C2C_OPP25 = 1,
+	C2C_OPP50 = 2,
+	C2C_OPP100 = 3,
+};
+
+enum c2c_buswidth {
+	C2C_BUSWIDTH_8 = 0,
+	C2C_BUSWIDTH_10 = 1,
+	C2C_BUSWIDTH_16 = 2,
+};
+
+enum c2c_shrdmem_size {
+	C2C_MEMSIZE_4 = 0,
+	C2C_MEMSIZE_8 = 1,
+	C2C_MEMSIZE_16 = 2,
+	C2C_MEMSIZE_32 = 3,
+	C2C_MEMSIZE_64 = 4,
+	C2C_MEMSIZE_128 = 5,
+	C2C_MEMSIZE_256 = 6,
+	C2C_MEMSIZE_512 = 7,
+};
+
+struct exynos_c2c_platdata {
+	void (*setup_gpio)(enum c2c_buswidth rx_width, enum c2c_buswidth tx_width);
+	void (*set_cprst)(void);
+	void (*clear_cprst)(void);
+	u32 (*get_c2c_state)(void);
+
+	u32 shdmem_addr;
+	enum c2c_shrdmem_size shdmem_size;
+
+	void __iomem *ap_sscm_addr;
+	void __iomem *cp_sscm_addr;
+
+	enum c2c_buswidth rx_width;
+	enum c2c_buswidth tx_width;
+	u32 clk_opp100;	/* clock of OPP100 mode */
+	u32 clk_opp50;	/* clock of OPP50 mode */
+	u32 clk_opp25;	/* clock of OPP25 */
+	enum c2c_opp_mode default_opp_mode;
+
+	void __iomem *c2c_sysreg;	/* System Register address for C2C */
+	char *c2c_clk;
+};
+
+void exynos_c2c_set_platdata(struct exynos_c2c_platdata *pd);
+extern void exynos_c2c_cfg_gpio(enum c2c_buswidth rx_width, enum c2c_buswidth tx_width);
+extern void exynos_c2c_set_cprst(void);
+extern void exynos_c2c_clear_cprst(void);
+#endif /*__ASM_PLAT_C2C_H */
diff --git a/arch/arm/mach-exynos/include/mach/clkdev.h b/arch/arm/mach-exynos/include/mach/clkdev.h
new file mode 100644
index 0000000..7dffa83
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __MACH_CLKDEV_H__
+#define __MACH_CLKDEV_H__
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do {} while (0)
+
+#endif
diff --git a/arch/arm/mach-exynos/include/mach/clock-domain.h b/arch/arm/mach-exynos/include/mach/clock-domain.h
new file mode 100644
index 0000000..91013d1
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/clock-domain.h
@@ -0,0 +1,33 @@
+/* linux/arch/arm/mach-exynos/include/mach/clock-domain.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * EXYNOS - Clock Domain support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_CLOCK_DOMAIN_H
+#define __ASM_ARCH_CLOCK_DOMAIN_H __FILE__
+
+#define LPA_DOMAIN	0x00000001
+
+struct clock {
+	struct list_head node;
+
+	struct clk *clk;
+};
+
+struct clock_domain {
+	struct list_head node;
+
+	unsigned int flag;
+	struct list_head domain_list;
+};
+
+int clock_add_domain(unsigned int flag, struct clk *clk);
+int clock_domain_enabled(unsigned int flag);
+#endif /* __ASM_ARCH_CLOCK_DOMAIN_H */
diff --git a/arch/arm/mach-exynos/include/mach/cpufreq.h b/arch/arm/mach-exynos/include/mach/cpufreq.h
new file mode 100644
index 0000000..9ef27df
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/cpufreq.h
@@ -0,0 +1,152 @@
+/* linux/arch/arm/mach-exynos/include/mach/cpufreq.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS4 - CPUFreq support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* CPU frequency level index for using cpufreq lock API
+ * This should be same with cpufreq_frequency_table
+*/
+
+enum cpufreq_level_index {
+	L0, L1, L2, L3, L4,
+	L5, L6, L7, L8, L9,
+	L10, L11, L12, L13, L14,
+	L15, L16, L17, L18, L19,
+	L20,
+};
+
+enum busfreq_level_request {
+	BUS_L0,		/* MEM 400MHz BUS 200MHz */
+	BUS_L1,		/* MEM 267MHz BUS 160MHz */
+	BUS_L2,		/* MEM 133MHz BUS 133MHz */
+	BUS_LEVEL_END,
+};
+
+enum cpufreq_lock_ID {
+	DVFS_LOCK_ID_G2D,	/* G2D */
+	DVFS_LOCK_ID_TV,	/* TV */
+	DVFS_LOCK_ID_MFC,	/* MFC */
+	DVFS_LOCK_ID_USB,	/* USB */
+	DVFS_LOCK_ID_USB_IF,	/* USB_IF */
+	DVFS_LOCK_ID_CAM,	/* CAM */
+	DVFS_LOCK_ID_PM,	/* PM */
+	DVFS_LOCK_ID_USER,	/* USER */
+	DVFS_LOCK_ID_TMU,	/* TMU */
+	DVFS_LOCK_ID_LPA,	/* LPA */
+	DVFS_LOCK_ID_TSP,	/* TSP */
+	DVFS_LOCK_ID_PEN,	/* E-PEN */
+	DVFS_LOCK_ID_G3D,	/* G3D */
+	DVFS_LOCK_ID_IR_LED,	/* IR_LED */
+	DVFS_LOCK_ID_LCD,	/* LCD */
+	DVFS_LOCK_ID_DRM,	/* DRM */
+	DVFS_LOCK_ID_ROTATION_BOOSTER,	/* ROTATION_BOOSTER */
+
+	/*
+	 * QoS Request on DMA Latency.
+	 *
+	 * dvfs_lock is a non standard implementation that can be
+	 * replaced with PM QoS framework.
+	 * However, in this implementation, in order to provide
+	 * a prototype and test of PM QoS on CPU (DMA Latency),
+	 * PM QoS uses dvfs_lock on CPU until we have a full
+	 * implementation in CPUFREQ framework of QoS.
+	 */
+	DVFS_LOCK_ID_QOS_DMA_LATENCY,
+	DVFS_LOCK_ID_END,
+};
+
+int exynos_cpufreq_get_level(unsigned int freq,
+			unsigned int *level);
+int exynos_find_cpufreq_level_by_volt(unsigned int arm_volt,
+			unsigned int *level);
+int exynos_cpufreq_lock(unsigned int nId,
+			enum cpufreq_level_index cpufreq_level);
+void exynos_cpufreq_lock_free(unsigned int nId);
+
+int exynos4_busfreq_lock(unsigned int nId,
+			enum busfreq_level_request busfreq_level);
+void exynos4_busfreq_lock_free(unsigned int nId);
+
+int exynos_cpufreq_upper_limit(unsigned int nId,
+			enum cpufreq_level_index cpufreq_level);
+void exynos_cpufreq_upper_limit_free(unsigned int nId);
+
+/*
+ * This level fix API set highset priority level lock.
+ * Please use this carefully, with other lock API
+ */
+int exynos_cpufreq_level_fix(unsigned int freq);
+void exynos_cpufreq_level_unfix(void);
+int exynos_cpufreq_is_fixed(void);
+
+#define MAX_INDEX	10
+
+#ifdef CONFIG_SLP
+struct dvfs_qos_info {
+	unsigned int qos_value;
+	unsigned int min_freq;
+	enum cpufreq_level_index level;
+};
+#endif
+
+struct exynos_dvfs_info {
+	unsigned long	mpll_freq_khz;
+	unsigned int	pll_safe_idx;
+	unsigned int	pm_lock_idx;
+	unsigned int	max_support_idx;
+	unsigned int	min_support_idx;
+	unsigned int	gov_support_freq;
+	struct clk	*cpu_clk;
+	unsigned int	*volt_table;
+	struct cpufreq_frequency_table	*freq_table;
+	void (*set_freq)(unsigned int, unsigned int);
+	bool (*need_apll_change)(unsigned int, unsigned int);
+
+#ifdef CONFIG_SLP
+	struct dvfs_qos_info *cpu_dma_latency;
+#endif
+};
+
+extern struct exynos_dvfs_info *exynos_info;
+
+#define SUPPORT_1400MHZ	(1<<31)
+#define SUPPORT_1200MHZ	(1<<30)
+#define SUPPORT_1000MHZ	(1<<29)
+#define SUPPORT_FREQ_SHIFT	29
+#define SUPPORT_FREQ_MASK	7
+
+#if defined(CONFIG_ARCH_EXYNOS4)
+extern int exynos4210_cpufreq_init(struct exynos_dvfs_info *);
+extern int exynos4x12_cpufreq_init(struct exynos_dvfs_info *);
+static inline int exynos5250_cpufreq_init(struct exynos_dvfs_info *info)
+{
+	return 0;
+}
+
+#elif defined(CONFIG_ARCH_EXYNOS5)
+static inline int exynos4210_cpufreq_init(struct exynos_dvfs_info *info)
+{
+	return 0;
+}
+
+static inline int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
+{
+	return 0;
+}
+
+extern int exynos5250_cpufreq_init(struct exynos_dvfs_info *);
+#else
+	#warning "Should define CONFIG_ARCH_EXYNOS4(5)\n"
+#endif
+
+#if defined(CONFIG_EXYNOS5250_ABB_WA)
+/* These function and variables should be removed in EVT1 */
+void exynos5250_set_arm_abbg(unsigned int arm_volt, unsigned int int_volt);
+#endif
diff --git a/arch/arm/mach-exynos/include/mach/debug-macro.S b/arch/arm/mach-exynos/include/mach/debug-macro.S
new file mode 100644
index 0000000..26ee8b5
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/debug-macro.S
@@ -0,0 +1,35 @@
+/* linux/arch/arm/mach-exynos/include/mach/debug-macro.S
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Based on arch/arm/mach-s3c6400/include/mach/debug-macro.S
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* pull in the relevant register and map files. */
+
+#include <mach/map.h>
+
+	/* note, for the boot process to work we have to keep the UART
+	 * virtual address aligned to an 1MiB boundary for the L1
+	 * mapping the head code makes. We keep the UART virtual address
+	 * aligned and add in the offset when we load the value here.
+	 */
+
+	.macro addruart, rp, rv
+		ldr	\rp, = S3C_PA_UART
+		ldr	\rv, = S3C_VA_UART
+#if CONFIG_DEBUG_S3C_UART != 0
+		add	\rp, \rp, #(0x10000 * CONFIG_DEBUG_S3C_UART)
+		add	\rv, \rv, #(0x10000 * CONFIG_DEBUG_S3C_UART)
+#endif
+	.endm
+
+#define fifo_full fifo_full_s5pv210
+#define fifo_level fifo_level_s5pv210
+
+#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-exynos/include/mach/dev-sysmmu.h b/arch/arm/mach-exynos/include/mach/dev-sysmmu.h
new file mode 100644
index 0000000..ed5fc92
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/dev-sysmmu.h
@@ -0,0 +1,87 @@
+/* linux/arch/arm/mach-exynos/include/mach/dev-sysmmu.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS - System MMU support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _ARM_MACH_EXYNOS_SYSMMU_H_
+#define _ARM_MACH_EXYNOS_SYSMMU_H_
+
+#define SYSMMU_DEVNAME_BASE "s5p-sysmmu"
+
+#ifdef CONFIG_S5P_SYSTEM_MMU
+#include <linux/device.h>
+
+#define SYSMMU_PLATDEV(ipname) exynos_device_sysmmu_##ipname
+
+#ifdef CONFIG_EXYNOS_DEV_PD
+#define ASSIGN_SYSMMU_POWERDOMAIN(ipname, powerdomain) \
+		SYSMMU_PLATDEV(ipname).dev.parent = powerdomain
+#else
+#define ASSIGN_SYSMMU_POWERDOMAIN(ipname, powerdomain) do { } while (0)
+#endif
+
+extern struct platform_device SYSMMU_PLATDEV(sss);
+extern struct platform_device SYSMMU_PLATDEV(jpeg);
+extern struct platform_device SYSMMU_PLATDEV(fimd1);
+extern struct platform_device SYSMMU_PLATDEV(pcie);
+extern struct platform_device SYSMMU_PLATDEV(2d);
+extern struct platform_device SYSMMU_PLATDEV(rot);
+extern struct platform_device SYSMMU_PLATDEV(mdma);
+extern struct platform_device SYSMMU_PLATDEV(tv);
+extern struct platform_device SYSMMU_PLATDEV(mfc_l);
+extern struct platform_device SYSMMU_PLATDEV(mfc_r);
+extern struct platform_device SYSMMU_PLATDEV(is_isp);
+extern struct platform_device SYSMMU_PLATDEV(is_drc);
+extern struct platform_device SYSMMU_PLATDEV(is_fd);
+extern struct platform_device SYSMMU_PLATDEV(is_cpu);
+extern struct platform_device SYSMMU_PLATDEV(flite0);
+extern struct platform_device SYSMMU_PLATDEV(flite1);
+extern struct platform_device SYSMMU_PLATDEV(flite2);
+
+#ifdef CONFIG_ARCH_EXYNOS4
+extern struct platform_device SYSMMU_PLATDEV(fimc0);
+extern struct platform_device SYSMMU_PLATDEV(fimc1);
+extern struct platform_device SYSMMU_PLATDEV(fimc2);
+extern struct platform_device SYSMMU_PLATDEV(fimc3);
+extern struct platform_device SYSMMU_PLATDEV(g2d_acp);
+extern struct platform_device SYSMMU_PLATDEV(gps);
+extern struct platform_device SYSMMU_PLATDEV(lite0);
+extern struct platform_device SYSMMU_PLATDEV(lite1);
+extern struct platform_device SYSMMU_PLATDEV(ispcx);
+extern struct platform_device SYSMMU_PLATDEV(fimd0);
+#endif
+
+#ifdef CONFIG_ARCH_EXYNOS5
+extern struct platform_device SYSMMU_PLATDEV(gsc0);
+extern struct platform_device SYSMMU_PLATDEV(gsc1);
+extern struct platform_device SYSMMU_PLATDEV(gsc2);
+extern struct platform_device SYSMMU_PLATDEV(gsc3);
+
+extern struct platform_device SYSMMU_PLATDEV(is_sclrc);
+extern struct platform_device SYSMMU_PLATDEV(is_sclrp);
+extern struct platform_device SYSMMU_PLATDEV(is_odc);
+extern struct platform_device SYSMMU_PLATDEV(is_dis0);
+extern struct platform_device SYSMMU_PLATDEV(is_dis1);
+extern struct platform_device SYSMMU_PLATDEV(is_3dnr);
+#endif
+
+static inline void sysmmu_set_owner(struct device *sysmmu, struct device *owner)
+{
+	sysmmu->platform_data = owner;
+}
+
+#else /* !CONFIG_S5P_SYSTEM_MMU */
+#define sysmmu_set_owner(sysmmu, owner) do { } while (0)
+#define ASSIGN_SYSMMU_POWERDOMAIN(ipname, powerdomain) do { } while (0)
+#endif
+
+#define SYSMMU_CLOCK_NAME(ipname, id) SYSMMU_DEVNAME_BASE "." #id
+
+#endif /* _ARM_MACH_EXYNOS_SYSMMU_H_ */
diff --git a/arch/arm/mach-exynos/include/mach/dev.h b/arch/arm/mach-exynos/include/mach/dev.h
new file mode 100644
index 0000000..c3dcb71
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/dev.h
@@ -0,0 +1,43 @@
+/* linux/arch/arm/mach-exynos/include/mach/dev.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * EXYNOS4 - Device List support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_DEV_H
+#define __ASM_ARCH_DEV_H __FILE__
+
+struct device;
+
+struct domain_lock {
+	struct list_head node;
+
+	struct device_domain *domain;
+	struct device *device;
+	unsigned long freq;
+};
+
+struct device_domain {
+	struct list_head node;
+
+	struct device *device;
+	struct list_head domain_list;
+};
+
+int dev_add(struct device_domain *domain, struct device *device);
+struct device *dev_get(const char *name);
+void dev_put(const char *name);
+int dev_lock(struct device *device, struct device *dev, unsigned long freq);
+int dev_lock_fix(struct device *device, struct device *dev, unsigned long freq);
+int dev_unlock(struct device *device, struct device *dev);
+void dev_unlock_fix(struct device *device, struct device *dev);
+unsigned long dev_max_freq(struct device *device);
+int dev_lock_list(struct device *dev, char *buf);
+
+#endif /* __ASM_ARCH_DEV_H */
diff --git a/arch/arm/mach-exynos/include/mach/diag_bridge.h b/arch/arm/mach-exynos/include/mach/diag_bridge.h
new file mode 100644
index 0000000..b06f020
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/diag_bridge.h
@@ -0,0 +1,55 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __LINUX_USB_DIAG_BRIDGE_H__
+#define __LINUX_USB_DIAG_BRIDGE_H__
+
+struct diag_bridge_ops {
+	void *ctxt;
+	void (*read_complete_cb)(void *ctxt, char *buf,
+			int buf_size, int actual);
+	void (*write_complete_cb)(void *ctxt, char *buf,
+			int buf_size, int actual);
+	int (*suspend)(void *ctxt);
+	void (*resume)(void *ctxt);
+};
+
+#if defined(CONFIG_USB_QCOM_DIAG_BRIDGE) \
+	|| defined(CONFIG_USB_QCOM_DIAG_BRIDGE_MODULE)
+
+extern int diag_bridge_read(char *data, int size);
+extern int diag_bridge_write(char *data, int size);
+extern int diag_bridge_open(struct diag_bridge_ops *ops);
+extern void diag_bridge_close(void);
+
+#else
+
+static int __maybe_unused diag_bridge_read(char *data, int size)
+{
+	return -ENODEV;
+}
+
+static int __maybe_unused diag_bridge_write(char *data, int size)
+{
+	return -ENODEV;
+}
+
+static int __maybe_unused diag_bridge_open(struct diag_bridge_ops *ops)
+{
+	return -ENODEV;
+}
+
+static void __maybe_unused diag_bridge_close(void) { }
+
+#endif
+
+#endif
diff --git a/arch/arm/mach-exynos/include/mach/dma.h b/arch/arm/mach-exynos/include/mach/dma.h
new file mode 100644
index 0000000..81209eb
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/dma.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics Co. Ltd.
+ *	Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __MACH_DMA_H
+#define __MACH_DMA_H
+
+/* This platform uses the common S3C DMA API driver for PL330 */
+#include <plat/s3c-dma-pl330.h>
+
+#endif /* __MACH_DMA_H */
diff --git a/arch/arm/mach-exynos/include/mach/dsim.h b/arch/arm/mach-exynos/include/mach/dsim.h
new file mode 100644
index 0000000..de60369
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/dsim.h
@@ -0,0 +1,259 @@
+/* linux/arm/arch/mach-exynos/include/mach/dsim.h
+ *
+ * Platform data header for Samsung MIPI-DSIM.
+ *
+ * Copyright (c) 2009 Samsung Electronics
+ * InKi Dae <inki.dae@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef _DSIM_H
+#define _DSIM_H
+
+/* h/w configuration */
+#define MIPI_FIN		24000000
+#define DSIM_HEADER_FIFO_SZ	16
+#define DSIM_TIMEOUT_MS		5000
+#define DSIM_NO_OF_INTERRUPT	26
+#define DSIM_PM_STABLE_TIME	10
+
+#define DSIM_TRUE		1
+#define DSIM_FALSE		0
+
+#define CMD_LENGTH		0xf
+
+enum dsim_interface_type {
+	DSIM_COMMAND 		= 0,
+	DSIM_VIDEO 		= 1,
+};
+
+enum dsim_state {
+	DSIM_STATE_RESET 	= 0,
+	DSIM_STATE_INIT 	= 1,
+	DSIM_STATE_STOP 	= 2,
+	DSIM_STATE_HSCLKEN 	= 3,
+	DSIM_STATE_ULPS 	= 4,
+};
+
+enum {
+	DSIM_NONE_STATE 	= 0,
+	DSIM_RESUME_COMPLETE 	= 1,
+	DSIM_FRAME_DONE 	= 2,
+};
+
+enum dsim_virtual_ch_no {
+	DSIM_VIRTUAL_CH_0 	= 0,
+	DSIM_VIRTUAL_CH_1 	= 1,
+	DSIM_VIRTUAL_CH_2 	= 2,
+	DSIM_VIRTUAL_CH_3 	= 3,
+};
+
+enum dsim_video_mode_type {
+	DSIM_NON_BURST_SYNC_EVENT 	= 0,
+	DSIM_BURST_SYNC_EVENT 		= 1,
+	DSIM_NON_BURST_SYNC_PULSE 	= 2,
+	DSIM_BURST 			= 3,
+	DSIM_NON_VIDEO_MODE 		= 4,
+};
+
+enum dsim_fifo_state {
+	DSIM_RX_DATA_FULL 	= (1 << 25),
+	DSIM_RX_DATA_EMPTY 	= (1 << 24),
+	SFR_HEADER_FULL 	= (1 << 23),
+	SFR_HEADER_EMPTY 	= (1 << 22),
+	SFR_PAYLOAD_FULL 	= (1 << 21),
+	SFR_PAYLOAD_EMPTY 	= (1 << 20),
+	I80_HEADER_FULL 	= (1 << 19),
+	I80_HEADER_EMPTY 	= (1 << 18),
+	I80_PALOAD_FULL 	= (1 << 17),
+	I80_PALOAD_EMPTY 	= (1 << 16),
+	SUB_DISP_HEADER_FULL 	= (1 << 15),
+	SUB_DISP_HEADER_EMPTY 	= (1 << 14),
+	SUB_DISP_PAYLOAD_FULL 	= (1 << 13),
+	SUB_DISP_PAYLOAD_EMPTY 	= (1 << 12),
+	MAIN_DISP_HEADER_FULL 	= (1 << 11),
+	MAIN_DISP_HEADER_EMPTY 	= (1 << 10),
+	MAIN_DISP_PAYLOAD_FULL 	= (1 << 9),
+	MAIN_DISP_PAYLOAD_EMPTY = (1 << 8),
+};
+
+enum dsim_no_of_data_lane {
+	DSIM_DATA_LANE_1 	= 0,
+	DSIM_DATA_LANE_2 	= 1,
+	DSIM_DATA_LANE_3 	= 2,
+	DSIM_DATA_LANE_4 	= 3,
+};
+
+enum dsim_byte_clk_src {
+	DSIM_PLL_OUT_DIV8 	= 0,
+	DSIM_EXT_CLK_DIV8 	= 1,
+	DSIM_EXT_CLK_BYPASS 	= 2,
+};
+
+enum dsim_lane {
+	DSIM_LANE_DATA0 	= (1 << 0),
+	DSIM_LANE_DATA1 	= (1 << 1),
+	DSIM_LANE_DATA2 	= (1 << 2),
+	DSIM_LANE_DATA3 	= (1 << 3),
+	DSIM_LANE_DATA_ALL 	= 0xf,
+	DSIM_LANE_CLOCK 	= (1 << 4),
+	DSIM_LANE_ALL 		= DSIM_LANE_CLOCK | DSIM_LANE_DATA_ALL,
+};
+
+enum dsim_pixel_format {
+	DSIM_CMD_3BPP 			= 0,
+	DSIM_CMD_8BPP 			= 1,
+	DSIM_CMD_12BPP 			= 2,
+	DSIM_CMD_16BPP 			= 3,
+	DSIM_VID_16BPP_565 		= 4,
+	DSIM_VID_18BPP_666PACKED 	= 5,
+	DSIM_18BPP_666LOOSELYPACKED 	= 6,
+	DSIM_24BPP_888 			= 7,
+};
+
+enum dsim_lane_state {
+	DSIM_LANE_STATE_HS_READY,
+	DSIM_LANE_STATE_ULPS,
+	DSIM_LANE_STATE_STOP,
+	DSIM_LANE_STATE_LPDT,
+};
+
+enum dsim_transfer {
+	DSIM_TRANSFER_NEITHER	= 0,
+	DSIM_TRANSFER_BYCPU	= (1 << 7),
+	DSIM_TRANSFER_BYLCDC	= (1 << 6),
+	DSIM_TRANSFER_BOTH	= (0x3 << 6)
+};
+
+enum dsim_lane_change {
+	DSIM_NO_CHANGE 		= 0,
+	DSIM_DATA_LANE_CHANGE 	= 1,
+	DSIM_CLOCK_NALE_CHANGE 	= 2,
+	DSIM_ALL_LANE_CHANGE 	= 3,
+};
+
+enum dsim_int_src {
+	DSIM_ALL_OF_INTR 	= 0xffffffff,
+	DSIM_PLL_STABLE 	= (1 << 31),
+        DSIM_REL_SWRST		= (1 << 30),
+        DSIM_FIFO_EMPTY		= (1 << 29),
+};
+
+enum dsim_data_id {
+	/* short packet types of packet types for command */
+	GEN_SHORT_WR_NO_PARA	= 0x03,
+	GEN_SHORT_WR_1_PARA	= 0x13,
+	GEN_SHORT_WR_2_PARA	= 0x23,
+	GEN_RD_NO_PARA		= 0x04,
+	GEN_RD_1_PARA		= 0x14,
+	GEN_RD_2_PARA		= 0x24,
+	DCS_WR_NO_PARA		= 0x05,
+	DCS_WR_1_PARA		= 0x15,
+	DCS_RD_NO_PARA		= 0x06,
+	SET_MAX_RTN_PKT_SIZE	= 0x37,
+
+	/* long packet types of packet types for command */
+	NULL_PKT		= 0x09,
+	BLANKING_PKT		= 0x19,
+	GEN_LONG_WR		= 0x29,
+	DCS_LONG_WR		= 0x39,
+
+	/* short packet types of generic command */
+	CMD_OFF			= 0x02,
+	CMD_ON			= 0x12,
+	SHUT_DOWN		= 0x22,
+	TURN_ON			= 0x32,
+
+	/* short packet types for video data */
+	VSYNC_START		= 0x01,
+	VSYNC_END		= 0x11,
+	HSYNC_START		= 0x21,
+	HSYNC_END		= 0x31,
+	EOT_PKT			= 0x08,
+
+	/* long packet types for video data */
+	RGB565_PACKED		= 0x0e,
+	RGB666_PACKED		= 0x1e,
+	RGB666_LOOSLY		= 0x2e,
+	RGB888_PACKED		= 0x3e,
+};
+
+struct dsim_config {
+	/* only DSIM_1_03 */
+	unsigned char auto_flush;
+
+	/* only DSIM_1.02 or DSIM_1_03 */
+	unsigned char eot_disable;
+
+	/* porch option */
+	unsigned char auto_vertical_cnt;	/* auto vertical cnt mode */
+	unsigned char hse;			/* horizontal sync event mode */
+	unsigned char hfp;			/* discard horizontal front porch time */
+	unsigned char hbp;			/* discard horizontal back porch time */
+	unsigned char hsa;			/* discard horizontal sync area timing */
+
+	/* data lane */
+	enum dsim_no_of_data_lane e_no_data_lane;	/* number of data lane using DSI Master */
+
+	/* byte clock and escape clock */
+	enum dsim_byte_clk_src e_byte_clk;
+
+	/* pll pms value */
+	unsigned char p;
+	unsigned short m;
+	unsigned char s;
+
+	/* pll stable time */
+	unsigned int pll_stable_time;
+
+	unsigned long esc_clk;
+
+	/* BTA sequence */
+	unsigned short stop_holding_cnt;
+	unsigned char bta_timeout;
+	unsigned short rx_timeout;
+	enum dsim_video_mode_type e_lane_swap;
+
+	unsigned long hs_toggle;
+};
+
+struct dsim_lcd_config {
+	enum dsim_interface_type e_interface;
+	unsigned int parameter[3];
+
+	/* lcd panel info */
+	void *lcd_panel_info;
+
+	/* platform data for lcd panel based on MIPI-DSI. */
+	void *mipi_ddi_pd;
+
+	unsigned int lcd_enabled;
+};
+
+struct s5p_platform_dsim {
+	char	*clk_name;
+	char	lcd_panel_name[64];
+	unsigned int te_irq;
+	unsigned int platform_rev;
+
+	struct dsim_config *dsim_info;
+	struct dsim_lcd_config *dsim_lcd_info;
+
+	void (*mipi_power) (int enable);
+	void (*enable_clk) (void *d_clk, unsigned char enable);
+	void (*part_reset) (void);
+	void (*init_d_phy) (unsigned int dsim_base);
+	void (*exit_d_phy) (unsigned int dsim_base);
+	void (*cfg_gpio) (void);
+};
+
+extern void s5p_dsim_enable_clk(void *d_clk, unsigned char enable);
+extern void s5p_dsim_part_reset(void);
+extern void s5p_dsim_init_d_phy(unsigned int dsim_base);
+extern void s5p_dsim_exit_d_phy(unsigned int dsim_base);
+extern void exynos4_dsim_gpio_setup_24bpp(void);
+
+#endif /* _DSIM_H */
diff --git a/arch/arm/mach-exynos/include/mach/dwmci.h b/arch/arm/mach-exynos/include/mach/dwmci.h
new file mode 100644
index 0000000..fc14dc0
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/dwmci.h
@@ -0,0 +1,20 @@
+/* linux/arch/arm/mach-exynos/include/mach/dwmci.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Synopsys DesignWare Mobile Storage for EXYNOS4210
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARM_ARCH_DWMCI_H
+#define __ASM_ARM_ARCH_DWMCI_H __FILE__
+
+#include <linux/mmc/dw_mmc.h>
+
+extern void exynos_dwmci_set_platdata(struct dw_mci_board *pd, u32 slot_id);
+
+#endif /* __ASM_ARM_ARCH_DWMCI_H */
diff --git a/arch/arm/mach-exynos/include/mach/entry-macro.S b/arch/arm/mach-exynos/include/mach/entry-macro.S
new file mode 100644
index 0000000..c6b2b7c
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/entry-macro.S
@@ -0,0 +1,126 @@
+/* arch/arm/mach-exynos/include/mach/entry-macro.S
+ *
+ * Cloned from arch/arm/mach-realview/include/mach/entry-macro.S
+ *
+ * Low-level IRQ helper macros for EXYNOS4 platforms
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+*/
+
+#include <mach/hardware.h>
+#include <asm/hardware/gic.h>
+#include <mach/map.h>
+
+		.macro	disable_fiq
+		.endm
+
+		.macro  get_irqnr_preamble, base, tmp
+#ifdef CONFIG_ARCH_EXYNOS4
+		mov	\tmp, #0
+		mrc	p15, 0, \base, c0, c0, 5
+		and	\base, \base, #3
+		cmp	\base, #0
+		beq	1f
+		ldr	\tmp, =gic_bank_offset
+		ldr	\tmp, [\tmp]
+		cmp	\base, #1
+		beq	1f
+		cmp	\base, #2
+		addeq	\tmp, \tmp, \tmp
+		addne	\tmp, \tmp, \tmp, LSL #1
+#endif
+1:		ldr	\base, =gic_cpu_base_addr
+		ldr	\base, [\base]
+
+#ifdef CONFIG_ARCH_EXYNOS4
+		add	\base, \base, \tmp
+#endif
+		.endm
+
+		.macro  arch_ret_to_user, tmp1, tmp2
+		.endm
+
+		/*
+		 * The interrupt numbering scheme is defined in the
+		 * interrupt controller spec.  To wit:
+		 *
+		 * Interrupts 0-15 are IPI
+		 * 16-28 are reserved
+		 * 29-31 are local.  We allow 30 to be used for the watchdog.
+		 * 32-1020 are global
+		 * 1021-1022 are reserved
+		 * 1023 is "spurious" (no interrupt)
+		 *
+		 * For now, we ignore all local interrupts so only return an interrupt if it's
+		 * between 30 and 1020.  The test_for_ipi routine below will pick up on IPIs.
+		 *
+		 * A simple read from the controller will tell us the number of the highest
+                 * priority enabled interrupt.  We then just need to check whether it is in the
+		 * valid range for an IRQ (30-1020 inclusive).
+		 */
+
+		.macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+
+		ldr     \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
+
+#if defined (CONFIG_ARCH_EXYNOS4)
+		/* workaround for gic lockup */
+		add   \base, \base, #0x10000
+		ldr   \tmp, [\base, #GIC_DIST_PRI]
+		str   \tmp, [\base, #GIC_DIST_PRI]
+		sub   \base, \base, #0x10000
+#endif
+		ldr	\tmp, =1021
+
+		bic     \irqnr, \irqstat, #0x1c00
+
+		cmp     \irqnr, #29
+		cmpcc	\irqnr, \irqnr
+		cmpne	\irqnr, \tmp
+		cmpcs	\irqnr, \irqnr
+		addne	\irqnr, \irqnr, #32
+#if defined(CONFIG_ARM_TRUSTZONE)
+		bne	101f
+
+		mrc	p15, 0, \tmp, c0, c0, 5
+		and	\tmp, \tmp, #0x3
+		cmp	\tmp, #1
+		cmpcs	\tmp, \tmp
+		beq	101f
+
+		cmp	\irqnr, #7
+		cmpcc	\irqnr, \irqnr
+		cmpne	\irqnr, #16
+		cmpcs	\irqnr, \irqnr
+		addne	\irqnr, \irqnr, #32
+101:
+#endif
+
+		.endm
+
+		/* We assume that irqstat (the raw value of the IRQ acknowledge
+		 * register) is preserved from the macro above.
+		 * If there is an IPI, we immediately signal end of interrupt on the
+		 * controller, since this requires the original irqstat value which
+		 * we won't easily be able to recreate later.
+		 */
+
+		.macro test_for_ipi, irqnr, irqstat, base, tmp
+		bic	\irqnr, \irqstat, #0x1c00
+		cmp	\irqnr, #16
+		strcc	\irqstat, [\base, #GIC_CPU_EOI]
+		cmpcs	\irqnr, \irqnr
+		.endm
+
+		/* As above, this assumes that irqstat and base are preserved.. */
+
+		.macro test_for_ltirq, irqnr, irqstat, base, tmp
+		bic     \irqnr, \irqstat, #0x1c00
+		mov     \tmp, #0
+		cmp     \irqnr, #28
+		moveq   \tmp, #1
+		streq   \irqstat, [\base, #GIC_CPU_EOI]
+		cmp     \tmp, #0
+		.endm
diff --git a/arch/arm/mach-exynos/include/mach/exynos-clock.h b/arch/arm/mach-exynos/include/mach/exynos-clock.h
new file mode 100644
index 0000000..823d548
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/exynos-clock.h
@@ -0,0 +1,80 @@
+/*
+ * linux/arch/arm/mach-exynos/include/mach/exynos-clock.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Header file for exynos4 clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H __FILE__
+
+#include <linux/clk.h>
+
+extern struct clk exynos4_clk_sclk_hdmi27m;
+extern struct clk exynos4_clk_sclk_usbphy0;
+extern struct clk exynos4_clk_sclk_usbphy1;
+extern struct clk exynos4_clk_sclk_hdmiphy;
+extern struct clk exynos4_clk_fimg2d;
+
+extern struct clksrc_clk exynos4_clk_sclk_apll;
+extern struct clksrc_clk exynos4_clk_mout_mpll;
+extern struct clksrc_clk exynos4_clk_aclk_160;
+extern struct clksrc_clk exynos4_clk_aclk_133;
+extern struct clksrc_clk exynos4_clk_aclk_200;
+#ifdef CONFIG_CPU_EXYNOS4212
+extern struct clksrc_clk exynos4212_clk_aclk_266;
+extern struct clksrc_clk exynos4212_clk_aclk_400_mcuisp;
+#endif
+extern struct clksrc_clk exynos4_clk_mout_epll;
+extern struct clksrc_clk exynos4_clk_sclk_vpll;
+extern struct clksrc_clk exynos4_clk_mout_g2d0;
+extern struct clksrc_clk exynos4_clk_mout_g2d1;
+extern struct clksrc_clk exynos4_clk_sclk_fimg2d;
+
+extern struct clk *exynos4_clkset_corebus_list[];
+extern struct clksrc_sources exynos4_clkset_mout_corebus;
+
+extern struct clk *exynos4_clkset_aclk_top_list[];
+extern struct clksrc_sources exynos4_clkset_aclk;
+
+extern struct clk *exynos4_clkset_group_list[];
+extern struct clksrc_sources exynos4_clkset_group;
+
+extern struct clk *exynos4_clkset_mout_mfc0_list[];
+
+extern struct clk exynos4_init_dmaclocks[];
+
+/* For vpll  */
+struct vpll_div_data {
+	u32 rate;
+	u32 pdiv;
+	u32 mdiv;
+	u32 sdiv;
+	u32 k;
+	u32 mfr;
+	u32 mrr;
+	u32 vsel;
+};
+
+extern struct clk_ops exynos4_vpll_ops;
+extern struct clk_ops exynos4_epll_ops;
+
+extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
+extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
+extern int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable);
+extern int exynos4_clk_ip_leftbus_ctrl(struct clk *clk, int enable);
+extern int exynos4_clk_ip_rightbus_ctrl(struct clk *clk, int enable);
+extern int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable);
+extern int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable);
+extern int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable);
+extern int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable);
+extern int exynos4_clk_ip_gps_ctrl(struct clk *clk, int enable);
+extern int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable);
+
+#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/mach-exynos/include/mach/exynos-ion.h b/arch/arm/mach-exynos/include/mach/exynos-ion.h
new file mode 100644
index 0000000..cca859a
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/exynos-ion.h
@@ -0,0 +1,20 @@
+/* linux/arch/arm/mach-exynos/include/mach/exynos-ion.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __MACH_EXYNOS_ION_H_
+
+struct platform_device;
+
+#ifdef CONFIG_ION_EXYNOS
+extern struct platform_device exynos_device_ion;
+void exynos_ion_set_platdata(void);
+#endif
+
+#endif /* __MACH_S5PV310_ION_H_ */
diff --git a/arch/arm/mach-exynos/include/mach/gc1-power.h b/arch/arm/mach-exynos/include/mach/gc1-power.h
new file mode 100644
index 0000000..ffebeae
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/gc1-power.h
@@ -0,0 +1,37 @@
+/*
+ * midas-power.h - Power Management of MIDAS Project
+ *
+ *  Copyright (C) 2011 Samsung Electrnoics
+ *  Chiwoong Byun <woong.byun@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __MIDAS_POWER_H
+#define __MIDAS_POWER_H __FILE__
+
+#if defined(CONFIG_MFD_S5M_CORE) && defined(CONFIG_MFD_MAX77686)
+extern struct s5m_platform_data exynos4_s5m8767_info;
+extern struct max77686_platform_data exynos4_max77686_info;
+#elif defined(CONFIG_MFD_S5M_CORE)
+extern struct s5m_platform_data exynos4_s5m8767_info;
+#else
+extern struct max77686_platform_data exynos4_max77686_info;
+#endif
+
+void midas_power_init(void);
+void midas_power_set_muic_pdata(void *, int);
+void midas_power_gpio_init(void);
+#endif /* __MIDAS_POWER_H */
diff --git a/arch/arm/mach-exynos/include/mach/gpio-exynos4.h b/arch/arm/mach-exynos/include/mach/gpio-exynos4.h
new file mode 100644
index 0000000..93b5b7b
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/gpio-exynos4.h
@@ -0,0 +1,241 @@
+/* linux/arch/arm/mach-exynos/include/mach/gpio-exynos4.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS4 - GPIO common lib support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_GPIO_EXYNOS4_H
+#define __ASM_ARCH_GPIO_EXYNOS4_H __FILE__
+
+#define gpio_get_value	__gpio_get_value
+#define gpio_set_value	__gpio_set_value
+#define gpio_cansleep	__gpio_cansleep
+#define gpio_to_irq	__gpio_to_irq
+
+/* Practically, GPIO banks up to GPZ are the configurable gpio banks */
+
+/* Common GPIO bank sizes */
+#define EXYNOS4_GPIO_A0_NR	(8)
+#define EXYNOS4_GPIO_A1_NR	(6)
+#define EXYNOS4_GPIO_B_NR	(8)
+#define EXYNOS4_GPIO_C0_NR	(5)
+#define EXYNOS4_GPIO_C1_NR	(5)
+#define EXYNOS4_GPIO_D0_NR	(4)
+#define EXYNOS4_GPIO_D1_NR	(4)
+#define EXYNOS4_GPIO_F0_NR	(8)
+#define EXYNOS4_GPIO_F1_NR	(8)
+#define EXYNOS4_GPIO_F2_NR	(8)
+#define EXYNOS4_GPIO_F3_NR	(6)
+#define EXYNOS4_GPIO_K0_NR	(7)
+#define EXYNOS4_GPIO_K1_NR	(7)
+#define EXYNOS4_GPIO_K2_NR	(7)
+#define EXYNOS4_GPIO_K3_NR	(7)
+#define EXYNOS4_GPIO_L0_NR	(8)
+#define EXYNOS4_GPIO_L1_NR	(3)
+#define EXYNOS4_GPIO_L2_NR	(8)
+#define EXYNOS4_GPIO_Y0_NR	(6)
+#define EXYNOS4_GPIO_Y1_NR	(4)
+#define EXYNOS4_GPIO_Y2_NR	(6)
+#define EXYNOS4_GPIO_Y3_NR	(8)
+#define EXYNOS4_GPIO_Y4_NR	(8)
+#define EXYNOS4_GPIO_Y5_NR	(8)
+#define EXYNOS4_GPIO_Y6_NR	(8)
+#define EXYNOS4_GPIO_X0_NR	(8)
+#define EXYNOS4_GPIO_X1_NR	(8)
+#define EXYNOS4_GPIO_X2_NR	(8)
+#define EXYNOS4_GPIO_X3_NR	(8)
+#define EXYNOS4_GPIO_Z_NR	(7)
+
+/* Only EXYNOS4210 GPIO bank sizes */
+#define EXYNOS4210_GPIO_E0_NR	(5)
+#define EXYNOS4210_GPIO_E1_NR	(8)
+#define EXYNOS4210_GPIO_E2_NR	(6)
+#define EXYNOS4210_GPIO_E3_NR	(8)
+#define EXYNOS4210_GPIO_E4_NR	(8)
+#define EXYNOS4210_GPIO_J0_NR	(8)
+#define EXYNOS4210_GPIO_J1_NR	(5)
+
+/* Only EXYNOS4212 GPIO bank sizes */
+#define EXYNOS4212_GPIO_J0_NR	(8)
+#define EXYNOS4212_GPIO_J1_NR	(5)
+#define EXYNOS4212_GPIO_M0_NR	(8)
+#define EXYNOS4212_GPIO_M1_NR	(7)
+#define EXYNOS4212_GPIO_M2_NR	(5)
+#define EXYNOS4212_GPIO_M3_NR	(8)
+#define EXYNOS4212_GPIO_M4_NR	(8)
+#define EXYNOS4212_GPIO_V0_NR	(8)
+#define EXYNOS4212_GPIO_V1_NR	(8)
+#define EXYNOS4212_GPIO_V2_NR	(8)
+#define EXYNOS4212_GPIO_V3_NR	(8)
+#define EXYNOS4212_GPIO_V4_NR	(2)
+
+/* GPIO bank numbers */
+
+#define EXYNOS4_GPIO_NEXT(__gpio) \
+	((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
+
+enum exynos4_gpio_number {
+	EXYNOS4_GPIO_A0_START		= 0,
+	EXYNOS4_GPIO_A1_START		= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_A0),
+	EXYNOS4_GPIO_B_START		= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_A1),
+	EXYNOS4_GPIO_C0_START		= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_B),
+	EXYNOS4_GPIO_C1_START		= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_C0),
+	EXYNOS4_GPIO_D0_START		= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_C1),
+	EXYNOS4_GPIO_D1_START		= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_D0),
+	EXYNOS4_GPIO_F0_START		= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_D1),
+	EXYNOS4_GPIO_F1_START		= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F0),
+	EXYNOS4_GPIO_F2_START		= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F1),
+	EXYNOS4_GPIO_F3_START		= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F2),
+	EXYNOS4_GPIO_K0_START		= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F3),
+	EXYNOS4_GPIO_K1_START		= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K0),
+	EXYNOS4_GPIO_K2_START		= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K1),
+	EXYNOS4_GPIO_K3_START		= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K2),
+	EXYNOS4_GPIO_L0_START		= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K3),
+	EXYNOS4_GPIO_L1_START		= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L0),
+	EXYNOS4_GPIO_L2_START		= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L1),
+	EXYNOS4_GPIO_Y0_START		= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L2),
+	EXYNOS4_GPIO_Y1_START		= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y0),
+	EXYNOS4_GPIO_Y2_START		= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y1),
+	EXYNOS4_GPIO_Y3_START		= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y2),
+	EXYNOS4_GPIO_Y4_START		= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y3),
+	EXYNOS4_GPIO_Y5_START		= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y4),
+	EXYNOS4_GPIO_Y6_START		= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y5),
+	EXYNOS4_GPIO_X0_START		= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y6),
+	EXYNOS4_GPIO_X1_START		= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X0),
+	EXYNOS4_GPIO_X2_START		= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X1),
+	EXYNOS4_GPIO_X3_START		= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X2),
+	EXYNOS4_GPIO_Z_START		= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X3),
+};
+
+enum exynos4210_gpio_number {
+	EXYNOS4210_GPIO_E0_START	= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Z),
+	EXYNOS4210_GPIO_E1_START	= EXYNOS4_GPIO_NEXT(EXYNOS4210_GPIO_E0),
+	EXYNOS4210_GPIO_E2_START	= EXYNOS4_GPIO_NEXT(EXYNOS4210_GPIO_E1),
+	EXYNOS4210_GPIO_E3_START	= EXYNOS4_GPIO_NEXT(EXYNOS4210_GPIO_E2),
+	EXYNOS4210_GPIO_E4_START	= EXYNOS4_GPIO_NEXT(EXYNOS4210_GPIO_E3),
+	EXYNOS4210_GPIO_J0_START	= EXYNOS4_GPIO_NEXT(EXYNOS4210_GPIO_E4),
+	EXYNOS4210_GPIO_J1_START	= EXYNOS4_GPIO_NEXT(EXYNOS4210_GPIO_J0),
+};
+
+enum exynos4212_gpio_number {
+	EXYNOS4212_GPIO_J0_START	= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Z),
+	EXYNOS4212_GPIO_J1_START	= EXYNOS4_GPIO_NEXT(EXYNOS4212_GPIO_J0),
+	EXYNOS4212_GPIO_M0_START	= EXYNOS4_GPIO_NEXT(EXYNOS4212_GPIO_J1),
+	EXYNOS4212_GPIO_M1_START	= EXYNOS4_GPIO_NEXT(EXYNOS4212_GPIO_M0),
+	EXYNOS4212_GPIO_M2_START	= EXYNOS4_GPIO_NEXT(EXYNOS4212_GPIO_M1),
+	EXYNOS4212_GPIO_M3_START	= EXYNOS4_GPIO_NEXT(EXYNOS4212_GPIO_M2),
+	EXYNOS4212_GPIO_M4_START	= EXYNOS4_GPIO_NEXT(EXYNOS4212_GPIO_M3),
+	EXYNOS4212_GPIO_V0_START	= EXYNOS4_GPIO_NEXT(EXYNOS4212_GPIO_M4),
+	EXYNOS4212_GPIO_V1_START	= EXYNOS4_GPIO_NEXT(EXYNOS4212_GPIO_V0),
+	EXYNOS4212_GPIO_V2_START	= EXYNOS4_GPIO_NEXT(EXYNOS4212_GPIO_V1),
+	EXYNOS4212_GPIO_V3_START	= EXYNOS4_GPIO_NEXT(EXYNOS4212_GPIO_V2),
+	EXYNOS4212_GPIO_V4_START	= EXYNOS4_GPIO_NEXT(EXYNOS4212_GPIO_V3),
+};
+
+/* EXYNOS4 GPIO number definitions */
+#define EXYNOS4_GPA0(_nr)	(EXYNOS4_GPIO_A0_START + (_nr))
+#define EXYNOS4_GPA1(_nr)	(EXYNOS4_GPIO_A1_START + (_nr))
+#define EXYNOS4_GPB(_nr)	(EXYNOS4_GPIO_B_START + (_nr))
+#define EXYNOS4_GPC0(_nr)	(EXYNOS4_GPIO_C0_START + (_nr))
+#define EXYNOS4_GPC1(_nr)	(EXYNOS4_GPIO_C1_START + (_nr))
+#define EXYNOS4_GPD0(_nr)	(EXYNOS4_GPIO_D0_START + (_nr))
+#define EXYNOS4_GPD1(_nr)	(EXYNOS4_GPIO_D1_START + (_nr))
+#define EXYNOS4_GPF0(_nr)	(EXYNOS4_GPIO_F0_START + (_nr))
+#define EXYNOS4_GPF1(_nr)	(EXYNOS4_GPIO_F1_START + (_nr))
+#define EXYNOS4_GPF2(_nr)	(EXYNOS4_GPIO_F2_START + (_nr))
+#define EXYNOS4_GPF3(_nr)	(EXYNOS4_GPIO_F3_START + (_nr))
+#define EXYNOS4_GPK0(_nr)	(EXYNOS4_GPIO_K0_START + (_nr))
+#define EXYNOS4_GPK1(_nr)	(EXYNOS4_GPIO_K1_START + (_nr))
+#define EXYNOS4_GPK2(_nr)	(EXYNOS4_GPIO_K2_START + (_nr))
+#define EXYNOS4_GPK3(_nr)	(EXYNOS4_GPIO_K3_START + (_nr))
+#define EXYNOS4_GPL0(_nr)	(EXYNOS4_GPIO_L0_START + (_nr))
+#define EXYNOS4_GPL1(_nr)	(EXYNOS4_GPIO_L1_START + (_nr))
+#define EXYNOS4_GPL2(_nr)	(EXYNOS4_GPIO_L2_START + (_nr))
+#define EXYNOS4_GPY0(_nr)	(EXYNOS4_GPIO_Y0_START + (_nr))
+#define EXYNOS4_GPY1(_nr)	(EXYNOS4_GPIO_Y1_START + (_nr))
+#define EXYNOS4_GPY2(_nr)	(EXYNOS4_GPIO_Y2_START + (_nr))
+#define EXYNOS4_GPY3(_nr)	(EXYNOS4_GPIO_Y3_START + (_nr))
+#define EXYNOS4_GPY4(_nr)	(EXYNOS4_GPIO_Y4_START + (_nr))
+#define EXYNOS4_GPY5(_nr)	(EXYNOS4_GPIO_Y5_START + (_nr))
+#define EXYNOS4_GPY6(_nr)	(EXYNOS4_GPIO_Y6_START + (_nr))
+#define EXYNOS4_GPX0(_nr)	(EXYNOS4_GPIO_X0_START + (_nr))
+#define EXYNOS4_GPX1(_nr)	(EXYNOS4_GPIO_X1_START + (_nr))
+#define EXYNOS4_GPX2(_nr)	(EXYNOS4_GPIO_X2_START + (_nr))
+#define EXYNOS4_GPX3(_nr)	(EXYNOS4_GPIO_X3_START + (_nr))
+#define EXYNOS4_GPZ(_nr)	(EXYNOS4_GPIO_Z_START + (_nr))
+
+#define EXYNOS4210_GPE0(_nr)	(EXYNOS4210_GPIO_E0_START + (_nr))
+#define EXYNOS4210_GPE1(_nr)	(EXYNOS4210_GPIO_E1_START + (_nr))
+#define EXYNOS4210_GPE2(_nr)	(EXYNOS4210_GPIO_E2_START + (_nr))
+#define EXYNOS4210_GPE3(_nr)	(EXYNOS4210_GPIO_E3_START + (_nr))
+#define EXYNOS4210_GPE4(_nr)	(EXYNOS4210_GPIO_E4_START + (_nr))
+#define EXYNOS4210_GPJ0(_nr)	(EXYNOS4210_GPIO_J0_START + (_nr))
+#define EXYNOS4210_GPJ1(_nr)	(EXYNOS4210_GPIO_J1_START + (_nr))
+
+#define EXYNOS4212_GPJ0(_nr)	(EXYNOS4212_GPIO_J0_START + (_nr))
+#define EXYNOS4212_GPJ1(_nr)	(EXYNOS4212_GPIO_J1_START + (_nr))
+#define EXYNOS4212_GPM0(_nr)	(EXYNOS4212_GPIO_M0_START + (_nr))
+#define EXYNOS4212_GPM1(_nr)	(EXYNOS4212_GPIO_M1_START + (_nr))
+#define EXYNOS4212_GPM2(_nr)	(EXYNOS4212_GPIO_M2_START + (_nr))
+#define EXYNOS4212_GPM3(_nr)	(EXYNOS4212_GPIO_M3_START + (_nr))
+#define EXYNOS4212_GPM4(_nr)	(EXYNOS4212_GPIO_M4_START + (_nr))
+#define EXYNOS4212_GPV0(_nr)	(EXYNOS4212_GPIO_V0_START + (_nr))
+#define EXYNOS4212_GPV1(_nr)	(EXYNOS4212_GPIO_V1_START + (_nr))
+#define EXYNOS4212_GPV2(_nr)	(EXYNOS4212_GPIO_V2_START + (_nr))
+#define EXYNOS4212_GPV3(_nr)	(EXYNOS4212_GPIO_V3_START + (_nr))
+#define EXYNOS4212_GPV4(_nr)	(EXYNOS4212_GPIO_V4_START + (_nr))
+
+/* the end of the EXYNOS4 specific gpios */
+#define EXYNOS4210_GPIO_END	(EXYNOS4212_GPV4(EXYNOS4212_GPIO_V4_NR) + 1)
+#define EXYNOS4212_GPIO_END	(EXYNOS4210_GPJ1(EXYNOS4210_GPIO_J1_NR) + 1)
+
+#define EXYNOS4XXX_GPIO_END	(EXYNOS4212_GPIO_END > EXYNOS4210_GPIO_END ? \
+				 EXYNOS4212_GPIO_END : EXYNOS4210_GPIO_END)
+#define EXYNOS4_GPIO_END	EXYNOS4XXX_GPIO_END
+
+/* define the number of gpios we need to the one after the GPZ() range */
+#define ARCH_NR_GPIOS		(EXYNOS4XXX_GPIO_END +			\
+				CONFIG_SAMSUNG_GPIO_EXTRA)
+
+#include <asm-generic/gpio.h>
+#if defined(CONFIG_MACH_MIDAS) || defined(CONFIG_MACH_SLP_MIDAS) \
+			       || defined(CONFIG_MACH_SLP_PQ) \
+			       || defined(CONFIG_MACH_SLP_PQ_LTE)
+#include "gpio-midas.h"
+#endif
+
+#if defined(CONFIG_MACH_SLP_NAPLES)
+#include "gpio-naples.h"
+#endif
+
+#if defined(CONFIG_MACH_U1)
+#include "gpio-u1.h"
+#endif
+
+#if defined(CONFIG_MACH_U1CAMERA_BD)
+#include "gpio-u1camera.h"
+#endif
+
+#if defined(CONFIG_MACH_Q1_BD)
+#include "gpio-q1.h"
+#endif
+
+#if defined(CONFIG_MACH_P2)
+#include "gpio-p2.h"
+#endif
+
+#if defined(CONFIG_MACH_P4)
+#include "gpio-p4.h"
+#endif
+
+#if defined(CONFIG_MACH_P8)
+#include "gpio-p8.h"
+#endif
+
+#endif /* __ASM_ARCH_GPIO_EXYNOS4_H */
diff --git a/arch/arm/mach-exynos/include/mach/gpio-exynos5.h b/arch/arm/mach-exynos/include/mach/gpio-exynos5.h
new file mode 100644
index 0000000..65aff87
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/gpio-exynos5.h
@@ -0,0 +1,201 @@
+/* linux/arch/arm/mach-exynos/include/mach/gpio-exynos5.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS5 - GPIO common lib support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_GPIO_EXYNOS5_H
+#define __ASM_ARCH_GPIO_EXYNOS5_H __FILE__
+
+#define gpio_get_value	__gpio_get_value
+#define gpio_set_value	__gpio_set_value
+#define gpio_cansleep	__gpio_cansleep
+#define gpio_to_irq	__gpio_to_irq
+
+/* Practically, GPIO banks up to GPZ are the configurable gpio banks */
+
+/* Common GPIO bank sizes */
+#define EXYNOS5_GPIO_A0_NR	(8)
+#define EXYNOS5_GPIO_A1_NR	(6)
+#define EXYNOS5_GPIO_A2_NR	(8)
+#define EXYNOS5_GPIO_B0_NR	(5)
+#define EXYNOS5_GPIO_B1_NR	(5)
+#define EXYNOS5_GPIO_B2_NR	(4)
+#define EXYNOS5_GPIO_B3_NR	(4)
+#define EXYNOS5_GPIO_C0_NR	(7)
+#define EXYNOS5_GPIO_C1_NR	(7)
+#define EXYNOS5_GPIO_C2_NR	(7)
+#define EXYNOS5_GPIO_C3_NR	(7)
+#define EXYNOS5_GPIO_C4_NR	(8)
+#define EXYNOS5_GPIO_D0_NR	(8)
+#define EXYNOS5_GPIO_D1_NR	(8)
+#define EXYNOS5_GPIO_Y0_NR	(6)
+#define EXYNOS5_GPIO_Y1_NR	(4)
+#define EXYNOS5_GPIO_Y2_NR	(6)
+#define EXYNOS5_GPIO_Y3_NR	(8)
+#define EXYNOS5_GPIO_Y4_NR	(8)
+#define EXYNOS5_GPIO_Y5_NR	(8)
+#define EXYNOS5_GPIO_Y6_NR	(8)
+#define EXYNOS5_GPIO_X0_NR	(8)
+#define EXYNOS5_GPIO_X1_NR	(8)
+#define EXYNOS5_GPIO_X2_NR	(8)
+#define EXYNOS5_GPIO_X3_NR	(8)
+#define EXYNOS5_GPIO_E0_NR	(8)
+#define EXYNOS5_GPIO_E1_NR	(2)
+#define EXYNOS5_GPIO_F0_NR	(4)
+#define EXYNOS5_GPIO_F1_NR	(4)
+#define EXYNOS5_GPIO_G0_NR	(8)
+#define EXYNOS5_GPIO_G1_NR	(8)
+#define EXYNOS5_GPIO_G2_NR	(2)
+#define EXYNOS5_GPIO_H0_NR	(4)
+#define EXYNOS5_GPIO_H1_NR	(8)
+#define EXYNOS5_GPIO_V0_NR	(8)
+#define EXYNOS5_GPIO_V1_NR	(8)
+#define EXYNOS5_GPIO_V2_NR	(8)
+#define EXYNOS5_GPIO_V3_NR	(8)
+#define EXYNOS5_GPIO_V4_NR	(2)
+#define EXYNOS5_GPIO_Z_NR	(7)
+
+/* Only EXYNOS5210 GPIO bank sizes */
+#define EXYNOS5210_GPIO_J0_NR	(5)
+#define EXYNOS5210_GPIO_J1_NR	(8)
+#define EXYNOS5210_GPIO_J2_NR	(8)
+#define EXYNOS5210_GPIO_J3_NR	(8)
+#define EXYNOS5210_GPIO_J4_NR	(2)
+#define EXYNOS5210_GPIO_K0_NR	(8)
+#define EXYNOS5210_GPIO_K1_NR	(8)
+#define EXYNOS5210_GPIO_K2_NR	(8)
+#define EXYNOS5210_GPIO_K3_NR	(7)
+
+/* GPIO bank numbers */
+
+#define EXYNOS5_GPIO_NEXT(__gpio) \
+	((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
+
+enum exynos5_gpio_number {
+	EXYNOS5_GPIO_A0_START		= 0,
+	EXYNOS5_GPIO_A1_START		= EXYNOS5_GPIO_NEXT(EXYNOS5_GPIO_A0),
+	EXYNOS5_GPIO_A2_START		= EXYNOS5_GPIO_NEXT(EXYNOS5_GPIO_A1),
+	EXYNOS5_GPIO_B0_START		= EXYNOS5_GPIO_NEXT(EXYNOS5_GPIO_A2),
+	EXYNOS5_GPIO_B1_START		= EXYNOS5_GPIO_NEXT(EXYNOS5_GPIO_B0),
+	EXYNOS5_GPIO_B2_START		= EXYNOS5_GPIO_NEXT(EXYNOS5_GPIO_B1),
+	EXYNOS5_GPIO_B3_START		= EXYNOS5_GPIO_NEXT(EXYNOS5_GPIO_B2),
+	EXYNOS5_GPIO_C0_START		= EXYNOS5_GPIO_NEXT(EXYNOS5_GPIO_B3),
+	EXYNOS5_GPIO_C1_START		= EXYNOS5_GPIO_NEXT(EXYNOS5_GPIO_C0),
+	EXYNOS5_GPIO_C2_START		= EXYNOS5_GPIO_NEXT(EXYNOS5_GPIO_C1),
+	EXYNOS5_GPIO_C3_START		= EXYNOS5_GPIO_NEXT(EXYNOS5_GPIO_C2),
+	EXYNOS5_GPIO_C4_START		= EXYNOS5_GPIO_NEXT(EXYNOS5_GPIO_C3),
+	EXYNOS5_GPIO_D0_START		= EXYNOS5_GPIO_NEXT(EXYNOS5_GPIO_C4),
+	EXYNOS5_GPIO_D1_START		= EXYNOS5_GPIO_NEXT(EXYNOS5_GPIO_D0),
+	EXYNOS5_GPIO_Y0_START		= EXYNOS5_GPIO_NEXT(EXYNOS5_GPIO_D1),
+	EXYNOS5_GPIO_Y1_START		= EXYNOS5_GPIO_NEXT(EXYNOS5_GPIO_Y0),
+	EXYNOS5_GPIO_Y2_START		= EXYNOS5_GPIO_NEXT(EXYNOS5_GPIO_Y1),
+	EXYNOS5_GPIO_Y3_START		= EXYNOS5_GPIO_NEXT(EXYNOS5_GPIO_Y2),
+	EXYNOS5_GPIO_Y4_START		= EXYNOS5_GPIO_NEXT(EXYNOS5_GPIO_Y3),
+	EXYNOS5_GPIO_Y5_START		= EXYNOS5_GPIO_NEXT(EXYNOS5_GPIO_Y4),
+	EXYNOS5_GPIO_Y6_START		= EXYNOS5_GPIO_NEXT(EXYNOS5_GPIO_Y5),
+	EXYNOS5_GPIO_X0_START		= EXYNOS5_GPIO_NEXT(EXYNOS5_GPIO_Y6),
+	EXYNOS5_GPIO_X1_START		= EXYNOS5_GPIO_NEXT(EXYNOS5_GPIO_X0),
+	EXYNOS5_GPIO_X2_START		= EXYNOS5_GPIO_NEXT(EXYNOS5_GPIO_X1),
+	EXYNOS5_GPIO_X3_START		= EXYNOS5_GPIO_NEXT(EXYNOS5_GPIO_X2),
+	EXYNOS5_GPIO_E0_START		= EXYNOS5_GPIO_NEXT(EXYNOS5_GPIO_X3),
+	EXYNOS5_GPIO_E1_START		= EXYNOS5_GPIO_NEXT(EXYNOS5_GPIO_E0),
+	EXYNOS5_GPIO_F0_START		= EXYNOS5_GPIO_NEXT(EXYNOS5_GPIO_E1),
+	EXYNOS5_GPIO_F1_START		= EXYNOS5_GPIO_NEXT(EXYNOS5_GPIO_F0),
+	EXYNOS5_GPIO_G0_START		= EXYNOS5_GPIO_NEXT(EXYNOS5_GPIO_F1),
+	EXYNOS5_GPIO_G1_START		= EXYNOS5_GPIO_NEXT(EXYNOS5_GPIO_G0),
+	EXYNOS5_GPIO_G2_START		= EXYNOS5_GPIO_NEXT(EXYNOS5_GPIO_G1),
+	EXYNOS5_GPIO_H0_START		= EXYNOS5_GPIO_NEXT(EXYNOS5_GPIO_G2),
+	EXYNOS5_GPIO_H1_START		= EXYNOS5_GPIO_NEXT(EXYNOS5_GPIO_H0),
+	EXYNOS5_GPIO_V0_START		= EXYNOS5_GPIO_NEXT(EXYNOS5_GPIO_H1),
+	EXYNOS5_GPIO_V1_START		= EXYNOS5_GPIO_NEXT(EXYNOS5_GPIO_V0),
+	EXYNOS5_GPIO_V2_START		= EXYNOS5_GPIO_NEXT(EXYNOS5_GPIO_V1),
+	EXYNOS5_GPIO_V3_START		= EXYNOS5_GPIO_NEXT(EXYNOS5_GPIO_V2),
+	EXYNOS5_GPIO_V4_START		= EXYNOS5_GPIO_NEXT(EXYNOS5_GPIO_V3),
+	EXYNOS5_GPIO_Z_START		= EXYNOS5_GPIO_NEXT(EXYNOS5_GPIO_V4),
+};
+
+enum exynos5210_gpio_number {
+	EXYNOS5210_GPIO_J0_START	= EXYNOS5_GPIO_NEXT(EXYNOS5_GPIO_Z),
+	EXYNOS5210_GPIO_J1_START	= EXYNOS5_GPIO_NEXT(EXYNOS5210_GPIO_J0),
+	EXYNOS5210_GPIO_J2_START	= EXYNOS5_GPIO_NEXT(EXYNOS5210_GPIO_J1),
+	EXYNOS5210_GPIO_J3_START	= EXYNOS5_GPIO_NEXT(EXYNOS5210_GPIO_J2),
+	EXYNOS5210_GPIO_J4_START	= EXYNOS5_GPIO_NEXT(EXYNOS5210_GPIO_J3),
+	EXYNOS5210_GPIO_K0_START	= EXYNOS5_GPIO_NEXT(EXYNOS5210_GPIO_J4),
+	EXYNOS5210_GPIO_K1_START	= EXYNOS5_GPIO_NEXT(EXYNOS5210_GPIO_K0),
+	EXYNOS5210_GPIO_K2_START	= EXYNOS5_GPIO_NEXT(EXYNOS5210_GPIO_K1),
+	EXYNOS5210_GPIO_K3_START	= EXYNOS5_GPIO_NEXT(EXYNOS5210_GPIO_K2),
+};
+
+/* EXYNOS5 GPIO number definitions */
+#define EXYNOS5_GPA0(_nr)	(EXYNOS5_GPIO_A0_START + (_nr))
+#define EXYNOS5_GPA1(_nr)	(EXYNOS5_GPIO_A1_START + (_nr))
+#define EXYNOS5_GPA2(_nr)	(EXYNOS5_GPIO_A2_START + (_nr))
+#define EXYNOS5_GPB0(_nr)	(EXYNOS5_GPIO_B0_START + (_nr))
+#define EXYNOS5_GPB1(_nr)	(EXYNOS5_GPIO_B1_START + (_nr))
+#define EXYNOS5_GPB2(_nr)	(EXYNOS5_GPIO_B2_START + (_nr))
+#define EXYNOS5_GPB3(_nr)	(EXYNOS5_GPIO_B3_START + (_nr))
+#define EXYNOS5_GPC0(_nr)	(EXYNOS5_GPIO_C0_START + (_nr))
+#define EXYNOS5_GPC1(_nr)	(EXYNOS5_GPIO_C1_START + (_nr))
+#define EXYNOS5_GPC2(_nr)	(EXYNOS5_GPIO_C2_START + (_nr))
+#define EXYNOS5_GPC3(_nr)	(EXYNOS5_GPIO_C3_START + (_nr))
+#define EXYNOS5_GPC4(_nr)	(EXYNOS5_GPIO_C4_START + (_nr))
+#define EXYNOS5_GPD0(_nr)	(EXYNOS5_GPIO_D0_START + (_nr))
+#define EXYNOS5_GPD1(_nr)	(EXYNOS5_GPIO_D1_START + (_nr))
+#define EXYNOS5_GPY0(_nr)	(EXYNOS5_GPIO_Y0_START + (_nr))
+#define EXYNOS5_GPY1(_nr)	(EXYNOS5_GPIO_Y1_START + (_nr))
+#define EXYNOS5_GPY2(_nr)	(EXYNOS5_GPIO_Y2_START + (_nr))
+#define EXYNOS5_GPY3(_nr)	(EXYNOS5_GPIO_Y3_START + (_nr))
+#define EXYNOS5_GPY4(_nr)	(EXYNOS5_GPIO_Y4_START + (_nr))
+#define EXYNOS5_GPY5(_nr)	(EXYNOS5_GPIO_Y5_START + (_nr))
+#define EXYNOS5_GPY6(_nr)	(EXYNOS5_GPIO_Y6_START + (_nr))
+#define EXYNOS5_GPX0(_nr)	(EXYNOS5_GPIO_X0_START + (_nr))
+#define EXYNOS5_GPX1(_nr)	(EXYNOS5_GPIO_X1_START + (_nr))
+#define EXYNOS5_GPX2(_nr)	(EXYNOS5_GPIO_X2_START + (_nr))
+#define EXYNOS5_GPX3(_nr)	(EXYNOS5_GPIO_X3_START + (_nr))
+#define EXYNOS5_GPE0(_nr)	(EXYNOS5_GPIO_E0_START + (_nr))
+#define EXYNOS5_GPE1(_nr)	(EXYNOS5_GPIO_E1_START + (_nr))
+#define EXYNOS5_GPF0(_nr)	(EXYNOS5_GPIO_F0_START + (_nr))
+#define EXYNOS5_GPF1(_nr)	(EXYNOS5_GPIO_F1_START + (_nr))
+#define EXYNOS5_GPG0(_nr)	(EXYNOS5_GPIO_G0_START + (_nr))
+#define EXYNOS5_GPG1(_nr)	(EXYNOS5_GPIO_G1_START + (_nr))
+#define EXYNOS5_GPG2(_nr)	(EXYNOS5_GPIO_G2_START + (_nr))
+#define EXYNOS5_GPH0(_nr)	(EXYNOS5_GPIO_H0_START + (_nr))
+#define EXYNOS5_GPH1(_nr)	(EXYNOS5_GPIO_H1_START + (_nr))
+#define EXYNOS5_GPV0(_nr)	(EXYNOS5_GPIO_V0_START + (_nr))
+#define EXYNOS5_GPV1(_nr)	(EXYNOS5_GPIO_V1_START + (_nr))
+#define EXYNOS5_GPV2(_nr)	(EXYNOS5_GPIO_V2_START + (_nr))
+#define EXYNOS5_GPV3(_nr)	(EXYNOS5_GPIO_V3_START + (_nr))
+#define EXYNOS5_GPV4(_nr)	(EXYNOS5_GPIO_V4_START + (_nr))
+#define EXYNOS5_GPZ(_nr)	(EXYNOS5_GPIO_Z_START + (_nr))
+
+/* EXYNOS5210 GPIO number definitions */
+#define EXYNOS5210_GPJ0(_nr)	(EXYNOS5210_GPIO_J0_START + (_nr))
+#define EXYNOS5210_GPJ1(_nr)	(EXYNOS5210_GPIO_J1_START + (_nr))
+#define EXYNOS5210_GPJ2(_nr)	(EXYNOS5210_GPIO_J2_START + (_nr))
+#define EXYNOS5210_GPJ3(_nr)	(EXYNOS5210_GPIO_J3_START + (_nr))
+#define EXYNOS5210_GPJ4(_nr)	(EXYNOS5210_GPIO_J4_START + (_nr))
+#define EXYNOS5210_GPK0(_nr)	(EXYNOS5210_GPIO_K0_START + (_nr))
+#define EXYNOS5210_GPK1(_nr)	(EXYNOS5210_GPIO_K1_START + (_nr))
+#define EXYNOS5210_GPK2(_nr)	(EXYNOS5210_GPIO_K2_START + (_nr))
+#define EXYNOS5210_GPK3(_nr)	(EXYNOS5210_GPIO_K3_START + (_nr))
+
+/* the end of the EXYNOS5 specific gpios */
+#define EXYNOS5210_GPIO_END	(EXYNOS5210_GPK3(EXYNOS5210_GPIO_K3_NR) + 1)
+#define EXYNOS5250_GPIO_END	(EXYNOS5_GPZ(EXYNOS5_GPIO_Z_NR) + 1)
+
+#define EXYNOS5XXX_GPIO_END	(EXYNOS5210_GPIO_END > EXYNOS5250_GPIO_END ? \
+				EXYNOS5210_GPIO_END : EXYNOS5250_GPIO_END)
+#define EXYNOS5_GPIO_END	EXYNOS5XXX_GPIO_END
+
+#if defined(CONFIG_MACH_P10)
+#include "gpio-p10.h"
+#endif
+
+#endif /* __ASM_ARCH_GPIO_EXYNOS5_H */
diff --git a/arch/arm/mach-exynos/include/mach/gpio-midas.h b/arch/arm/mach-exynos/include/mach/gpio-midas.h
new file mode 100644
index 0000000..894c1cf
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/gpio-midas.h
@@ -0,0 +1,52 @@
+/* linux/arch/arm/mach-exynos/include/mach/gpio-midas.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS4 - MIDAS GPIO lib
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_GPIO_MIDAS_H
+#define __ASM_ARCH_GPIO_MIDAS_H __FILE__
+
+#if defined(CONFIG_MACH_MIDAS_01_BD) || defined(CONFIG_GPIO_MIDAS_01_BD)
+#include "gpio-rev01-midas.h"
+#elif defined(CONFIG_MACH_MIDAS_02_BD) || defined(CONFIG_GPIO_MIDAS_02_BD)
+#include "gpio-rev02-midas.h"
+#elif defined(CONFIG_MACH_M0_GRANDECTC)
+#include "gpio-rev00-m0grandectc.h"
+#elif defined(CONFIG_MACH_M0_CTC)
+#include "gpio-rev00-m0ctc.h"
+#elif defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_SLP_PQ)
+#include "gpio-rev00-m0.h"
+#elif defined(CONFIG_MACH_M3)
+#include "gpio-rev00-m3.h"
+#elif defined(CONFIG_MACH_C1) && !defined(CONFIG_TARGET_LOCALE_KOR)
+#include "gpio-rev00-c1.h"
+#elif defined(CONFIG_MACH_C1CTC)
+#include "gpio-rev00-c1ctc.h"
+#elif (defined(CONFIG_MACH_C1VZW) || defined(CONFIG_MACH_SLP_PQ_LTE)) && \
+	!defined(CONFIG_TARGET_LOCALE_KOR)
+#include "gpio-rev00-c1vzw.h"
+#elif defined(CONFIG_MACH_JENGA)
+#include "gpio-rev00-jenga.h"
+#elif defined(CONFIG_MACH_S2PLUS)
+#include "gpio-rev00-s2plus.h"
+#elif defined(CONFIG_GPIO_NAPLES_00_BD)
+#include "gpio-rev00-naples.h"
+#elif (defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW)) && \
+	defined(CONFIG_TARGET_LOCALE_KOR)
+#include "gpio-rev03-c1kor.h"
+#elif defined(CONFIG_MACH_P4NOTE)
+#include "gpio-rev00-p4notepq.h"
+#elif defined(CONFIG_MACH_GC1)
+#include "gpio-rev00-gc1.h"
+#elif defined(CONFIG_MACH_T0)
+#include "gpio-rev00-t0.h"
+#endif
+
+#endif /* __ASM_ARCH_GPIO_MIDAS_H */
diff --git a/arch/arm/mach-exynos/include/mach/gpio-naples.h b/arch/arm/mach-exynos/include/mach/gpio-naples.h
new file mode 100644
index 0000000..bed9ee9
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/gpio-naples.h
@@ -0,0 +1,23 @@
+/* linux/arch/arm/mach-exynos/include/mach/gpio-naples.h
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS4 - MIDAS GPIO lib
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_GPIO_NAPLES_H
+#define __ASM_ARCH_GPIO_NAPLES_H __FILE__
+
+#if defined(CONFIG_GPIO_NAPLES_00_BD)
+#include "gpio-rev00-naples.h"
+#endif
+
+extern int s3c_gpio_slp_cfgpin(unsigned int pin, unsigned int config);
+extern int s3c_gpio_slp_setpull_updown(unsigned int pin, unsigned int config);
+
+#endif /* __ASM_ARCH_GPIO_NAPLES_H */
diff --git a/arch/arm/mach-exynos/include/mach/gpio-p10.h b/arch/arm/mach-exynos/include/mach/gpio-p10.h
new file mode 100644
index 0000000..3674faa
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/gpio-p10.h
@@ -0,0 +1,28 @@
+/* linux/arch/arm/mach-exynos/include/mach/gpio-midas.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS4 - MIDAS GPIO lib
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_GPIO_P10_H
+#define __ASM_ARCH_GPIO_P10_H __FILE__
+
+#if defined(CONFIG_MACH_P10_00_BD)
+#include "gpio-rev00-p10.h"
+#elif defined(CONFIG_MACH_P10_LTE_00_BD)
+#include "gpio-rev00-p10-lte.h"
+#elif defined(CONFIG_MACH_P10_WIFI_00_BD)
+#include "gpio-rev00-p10-wifi.h"
+#elif defined(CONFIG_MACH_P10_LUNGO_01_BD)
+#include "gpio-rev01-p10-lungo.h"
+#elif defined(CONFIG_MACH_P10_LUNGO_WIFI_01_BD)
+#include "gpio-rev01-p10-lungo-wifi.h"
+#endif
+
+#endif /* __ASM_ARCH_GPIO_P10_H */
diff --git a/arch/arm/mach-exynos/include/mach/gpio-p2.h b/arch/arm/mach-exynos/include/mach/gpio-p2.h
new file mode 100644
index 0000000..986bed3
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/gpio-p2.h
@@ -0,0 +1,242 @@
+#ifndef __MACH_GPIO_P2_H
+#define __MACH_GPIO_P2_H __FILE__
+
+#define GPIO_XMMC0_CDn		EXYNOS4_GPK0(2)
+
+#define GPIO_PS_ALS_SDA		EXYNOS4_GPK2(2)
+#define GPIO_PS_ALS_SCL		EXYNOS4_GPK3(2)
+
+#define GPIO_GYRO_INT		EXYNOS4_GPX0(0)
+#define GPIO_PS_VOUT		EXYNOS4_GPL0(6)
+#define GPIO_PS_VOUT_WAKE	EXYNOS4_GPX0(1)
+
+#define GPIO_BUCK1_EN_A		EXYNOS4_GPX0(5)
+#define GPIO_BUCK1_EN_B		EXYNOS4_GPX0(6)
+#define GPIO_BUCK2_EN		EXYNOS4_GPL0(0)
+#define GPIO_PMIC_IRQ		EXYNOS4_GPX0(7)
+
+#define GPIO_VOL_UP		EXYNOS4_GPX2(0)
+#define GPIO_VOL_DOWN		EXYNOS4_GPX2(1)
+
+#define GPIO_nPOWER		EXYNOS4_GPX2(7)
+
+#define VT_CAM_SDA_18V		EXYNOS4_GPC1(0)
+#define VT_CAM_SCL_18V		EXYNOS4_GPC1(2)
+
+#define CODEC_VT_SDA_18V	EXYNOS4_GPC1(3)
+#define CODEC_VT_SCL_18V	EXYNOS4_GPC1(4)
+
+#define GPIO_FUEL_SDA		EXYNOS4_GPY4(0)
+#define GPIO_FUEL_SCL		EXYNOS4_GPY4(1)
+#define GPIO_FUEL_ALERT	EXYNOS4_GPX2(3)
+
+#define GPIO_MASSMEM_EN_LEVEL	0
+
+#define GPIO_CAM_MOVIE_EN	EXYNOS4_GPL0(1)
+#define GPIO_CAM_FLASH_EN	EXYNOS4_GPL0(2)
+#define GPIO_CAM_FLASH_SET	EXYNOS4_GPE0(2)
+
+#define GPIO_TSP_LDO_ON		EXYNOS4_GPL0(3)
+#define GPIO_TSP_RST		EXYNOS4_GPL0(5)
+#define GPIO_TSP_INT		EXYNOS4_GPX0(4)
+#define GPIO_TSP_SDA		EXYNOS4_GPA1(2)
+#define GPIO_TSP_SCL		EXYNOS4_GPA1(3)
+#define GPIO_TSP_VENDOR1    EXYNOS4_GPY5(6)
+#define GPIO_TSP_VENDOR2    EXYNOS4_GPY5(7)
+
+
+
+#define GPIO_LCD_EN		EXYNOS4_GPL0(7)
+#define GPIO_LCD_LDO_EN	EXYNOS4_GPK1(1)
+#define GPIO_UART_SEL		EXYNOS4_GPY4(7)
+
+#define GPIO_CAM_PCLK		EXYNOS4_GPJ0(0)
+#define GPIO_CAM_VSYNC		EXYNOS4_GPJ0(1)
+#define GPIO_CAM_HSYNC		EXYNOS4_GPJ0(2)
+
+#define GPIO_CAM_MCLK		EXYNOS4210_GPJ1(3)
+
+#define GPIO_2M_nSTBY		EXYNOS4_GPL2(0)
+#define GPIO_2M_nRST		EXYNOS4_GPL2(1)
+#define GPIO_3M_nSTBY		EXYNOS4_GPL2(2)
+#define GPIO_3M_nRST		EXYNOS4_GPL2(7)
+
+#define GPIO_DET_35		EXYNOS4_GPX3(2)
+#define GPIO_DET_35_AF		0xF
+
+#define GPIO_EAR_SEND_END	EXYNOS4_GPX3(6)
+#define GPIO_EAR_SEND_END_AF	0xF
+
+#define GPIO_GPS_nRST		EXYNOS4_GPY5(4)
+#define GPIO_GPS_nRST_28V	EXYNOS4_GPL0(3)
+#define GPIO_GPS_PWR_EN		EXYNOS4_GPY5(5)
+
+#define GPIO_BT_RXD		EXYNOS4_GPA0(0)
+#define GPIO_BT_RXD_AF		2
+
+#define GPIO_BT_TXD		EXYNOS4_GPA0(1)
+#define GPIO_BT_TXD_AF		2
+
+#define GPIO_BT_CTS		EXYNOS4_GPA0(2)
+#define GPIO_BT_CTS_AF		2
+
+#define GPIO_BT_RTS		EXYNOS4_GPA0(3)
+#define GPIO_BT_RTS_AF		2
+
+#define GPIO_GPS_RXD		EXYNOS4_GPA0(4)
+#define GPIO_GPS_RXD_AF		2
+
+#define GPIO_GPS_TXD		EXYNOS4_GPA0(5)
+#define GPIO_GPS_TXD_AF		2
+
+#define GPIO_GPS_CTS		EXYNOS4_GPA0(6)
+#define GPIO_GPS_CTS_AF		2
+
+#define GPIO_GPS_RTS		EXYNOS4_GPA0(7)
+#define GPIO_GPS_RTS_AF		2
+
+#define GPIO_ALC_nRST		EXYNOS4_GPX1(7)
+
+#define GPIO_DOUBLE_RR		EXYNOS4_GPL2(3)
+/*#define GPIO_2MIC_EN		EXYNOS4_GPL2(5)*/
+
+#define GPIO_CURR_ADJ		EXYNOS4_GPE2(1)
+#define GPIO_TA_EN			EXYNOS4_GPY6(6)
+#define GPIO_TA_nCHG		EXYNOS4_GPL2(4)
+#define GPIO_TA_nCONNECTED	EXYNOS4_GPX3(5)
+#define GPIO_CHG_SDA	EXYNOS4_GPB(2)
+#define GPIO_CHG_SCL	EXYNOS4_GPB(3)
+
+#define GPIO_IPC_RXD		EXYNOS4_GPA1(4)
+#define GPIO_IPC_RXD_AF		2
+
+#define GPIO_IPC_TXD		EXYNOS4_GPA1(5)
+#define GPIO_IPC_TXD_AF		2
+
+#define GPIO_PHONE_ON		EXYNOS4_GPC1(1)
+#define GPIO_PHONE_ACTIVE	EXYNOS4_GPX1(6)
+#define GPIO_PDA_ACTIVE		EXYNOS4_GPY4(2)
+#define GPIO_CP_DUMP_INT	EXYNOS4_GPX1(2)
+#define GPIO_CP_RST		EXYNOS4_GPX1(4)
+#define GPIO_CP_REQ_RESET	EXYNOS4_GPY4(6)
+#define GPIO_IPC_SLAVE_WAKEUP	EXYNOS4_GPX1(0)
+#define GPIO_IPC_HOST_WAKEUP	EXYNOS4_GPX1(1)
+#define GPIO_SUSPEND_REQUEST	EXYNOS4_GPX1(3)
+#define GPIO_LVDS_NSHDN		EXYNOS4_GPX1(5)
+#define GPIO_ACTIVE_STATE	EXYNOS4_GPY3(5)
+
+#define IRQ_PHONE_ACTIVE	IRQ_EINT14
+#define IRQ_SUSPEND_REQUEST	IRQ_EINT11
+#define IRQ_IPC_HOST_WAKEUP	IRQ_EINT9
+
+#define EXYNOS4_GPD_0_0_TOUT_0	(0x2 << 0)
+#if defined(CONFIG_FB_MDNIE_PWM)
+#define EXYNOS4_GPD_0_1_TOUT_1	(0x3 << 4)
+#else
+#define EXYNOS4_GPD_0_1_TOUT_1	(0x2 << 4)
+#endif
+#define EXYNOS4_GPD_0_2_TOUT_2	(0x2 << 8)
+#define EXYNOS4_GPD_0_3_TOUT_3	(0x2 << 12)
+
+#define GPIO_WLAN_EN		EXYNOS4_GPL1(2)
+#define GPIO_WLAN_EN2		EXYNOS4_GPL0(6)
+#define GPIO_WLAN_EN_AF		1
+#define GPIO_WLAN_nRST		EXYNOS4_GPL0(4)
+
+/* CSR8811 Project(Alan.Ko) 2011.07.02 */
+/*#define GPIO_BT_EN		EXYNOS4_GPL0(4)*/
+/* CSR8811 Project(Alan.Ko) end */
+
+#define GPIO_BT_nRST		EXYNOS4_GPL1(0)
+
+#define GPIO_WLAN_HOST_WAKE	EXYNOS4_GPX2(5)
+#define GPIO_WLAN_HOST_WAKE_AF	0xF
+
+#define GPIO_BT_HOST_WAKE	EXYNOS4_GPX2(6)
+#define GPIO_BT_HOST_WAKE_AF	0xF
+
+/* CSR8811 Project(Alan.Ko) 2011.07.02 */
+/*#define GPIO_BT_WAKE		EXYNOS4_GPX3(1)*/
+/* CSR8811 Project(Alan.Ko) end */
+
+#define GPIO_WLAN_SDIO_CLK	EXYNOS4_GPK3(0)
+#define GPIO_WLAN_SDIO_CLK_AF	2
+
+#define GPIO_WLAN_SDIO_CMD	EXYNOS4_GPK3(1)
+#define GPIO_WLAN_SDIO_CMD_AF	2
+
+#define GPIO_WLAN_SDIO_D0	EXYNOS4_GPK3(3)
+#define GPIO_WLAN_SDIO_D0_AF	2
+
+#define GPIO_WLAN_SDIO_D1	EXYNOS4_GPK3(4)
+#define GPIO_WLAN_SDIO_D1_AF	2
+
+#define GPIO_WLAN_SDIO_D2	EXYNOS4_GPK3(5)
+#define GPIO_WLAN_SDIO_D2_AF	2
+
+#define GPIO_WLAN_SDIO_D3	EXYNOS4_GPK3(6)
+#define GPIO_WLAN_SDIO_D3_AF	2
+
+#define GPIO_HW_REV0		EXYNOS4_GPE1(0)
+#define GPIO_HW_REV1		EXYNOS4_GPE1(1)
+#define GPIO_HW_REV2		EXYNOS4_GPE1(2)
+#define GPIO_HW_REV3		EXYNOS4_GPE1(3)
+
+#define GPIO_HDMI_EN1		EXYNOS4_GPL1(1)
+#define GPIO_MHL_RST		EXYNOS4_GPF3(4)
+#define GPIO_MHL_INT		EXYNOS4_GPF3(5)
+#define GPIO_MHL_INT_AF		S3C_GPIO_SFN(0xF)
+#define	GPIO_MHL_WAKE_UP_AF	S3C_GPIO_SFN(0xF)
+#define GPIO_HDMI_HPD		EXYNOS4_GPX3(7)
+
+#define GPIO_SIM_DETECT		EXYNOS4_GPX0(3)
+
+#define GPIO_MSENSE_INT		EXYNOS4_GPX2(2)
+#define GPIO_DOCK_INT		EXYNOS4_GPX2(4)
+
+#define GPIO_IRDA_CONTROL	EXYNOS4_GPX3(0)
+#define GPIO_USB_OTG_EN		EXYNOS4_GPX3(3)
+#define GPIO_USB_SEL1		EXYNOS4_GPY3(4)
+#define GPIO_USB_SEL2		EXYNOS4_GPY3(7)
+#define GPIO_USB_SEL3		EXYNOS4_GPY4(5)
+#define GPIO_IF_CON_SENSE	EXYNOS4_GPY4(3)
+
+#define GPIO_MSENSOR_MHL_SDA_28V	EXYNOS4_GPD0(2)
+#define	GPIO_MSENSOR_MHL_SDA_AF			0x3
+#define GPIO_MSENSOR_MHL_SCL_28V	EXYNOS4_GPD0(3)
+#define	GPIO_MSENSOR_MHL_SCL_AF			0x3
+#define GPIO_MHL_SDA_18V		EXYNOS4_GPY3(0)
+#define GPIO_MHL_SCL_18V		EXYNOS4_GPY3(2)
+
+#define GPIO_AP_HDMI_SDA	GPIO_MSENSOR_MHL_SDA_28V
+#define	GPIO_AP_HDMI_SDA_AF	GPIO_MSENSOR_MHL_SDA_AF
+#define GPIO_AP_HDMI_SCL	GPIO_MSENSOR_MHL_SCL_28V
+#define	GPIO_AP_HDMI_SCL_AF	GPIO_MSENSOR_MHL_SCL_AF
+#define GPIO_AP_SDA_18V		GPIO_MHL_SDA_18V
+#define GPIO_AP_SCL_18V		GPIO_MHL_SCL_18V
+
+#define MHL_INT_IRQ		gpio_to_irq(GPIO_MHL_INT)
+#define MHL_WAKEUP_IRQ		gpio_to_irq(GPIO_MHL_WAKE_UP)
+
+#define GPIO_MIC_BIAS_EN	EXYNOS4_GPY6(7)
+#define GPIO_EAR_MIC_BIAS_EN	EXYNOS4_GPL2(6)
+
+#define GPIO_TDMB_EN		EXYNOS4_GPC0(1)
+#define GPIO_TDMB_RST_N		EXYNOS4_GPB(5)
+#define GPIO_TDMB_INT		EXYNOS4_GPB(4)
+#define GPIO_TDMB_INT_AF	0xf
+
+#define GPIO_PEN_SDA_28V	EXYNOS4_GPB(2)
+#define GPIO_PEN_SCL_28V	EXYNOS4_GPB(3)
+#define GPIO_PEN_LDO_EN		EXYNOS4_GPE0(1)
+#define GPIO_PEN_PDCT_18V	EXYNOS4_GPE1(6)
+#define GPIO_PEN_SLP_18V	EXYNOS4_GPE1(7)
+#define GPIO_PEN_IRQ_18V	EXYNOS4_GPE2(0)
+
+#define GPIO_REMOTE_SENSE_IRQ	EXYNOS4_GPE1(5)
+
+#define GPIO_ACCESSORY_EN	EXYNOS4_GPY6(1)
+#define GPIO_ACCESSORY_INT	EXYNOS4_GPX1(7)
+#define GPIO_ACCESSORY_OUT_5V EXYNOS4_GPY4(4)
+
+#endif /* __MACH_GPIO_P2_H */
diff --git a/arch/arm/mach-exynos/include/mach/gpio-p4.h b/arch/arm/mach-exynos/include/mach/gpio-p4.h
new file mode 100644
index 0000000..654f742
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/gpio-p4.h
@@ -0,0 +1,233 @@
+#ifndef __MACH_GPIO_P4_H
+#define __MACH_GPIO_P4_H __FILE__
+
+#define GPIO_XMMC0_CDn		EXYNOS4_GPK0(2)
+
+#define GPIO_PS_ALS_SDA		EXYNOS4_GPK2(2)
+#define GPIO_PS_ALS_SCL		EXYNOS4_GPK3(2)
+
+#define GPIO_GYRO_INT		EXYNOS4_GPX0(0)
+#define GPIO_PS_VOUT		EXYNOS4_GPL0(6)
+#define GPIO_PS_VOUT_WAKE	EXYNOS4_GPX0(1)
+
+#define GPIO_BUCK1_EN_A		EXYNOS4_GPX0(5)
+#define GPIO_BUCK1_EN_B		EXYNOS4_GPX0(6)
+#define GPIO_BUCK2_EN		EXYNOS4_GPL0(0)
+#define GPIO_PMIC_IRQ		EXYNOS4_GPX0(7)
+
+#define GPIO_VOL_UP		EXYNOS4_GPX2(1)
+#define GPIO_VOL_DOWN		EXYNOS4_GPX2(0)
+
+#define GPIO_nPOWER		EXYNOS4_GPX2(7)
+
+#define VT_CAM_SDA_18V		EXYNOS4_GPC1(0)
+#define VT_CAM_SCL_18V		EXYNOS4_GPC1(2)
+
+#define CODEC_VT_SDA_18V	EXYNOS4_GPC1(3)
+#define CODEC_VT_SCL_18V	EXYNOS4_GPC1(4)
+
+#define GPIO_FUEL_SDA		EXYNOS4_GPY4(0)
+#define GPIO_FUEL_SCL		EXYNOS4_GPY4(1)
+#define GPIO_FUEL_ALERT	EXYNOS4_GPX2(3)
+
+#define GPIO_MASSMEM_EN_LEVEL	0
+
+#define GPIO_CAM_MOVIE_EN	EXYNOS4_GPL0(1)
+#define GPIO_CAM_FLASH_EN	EXYNOS4_GPL0(2)
+#define GPIO_CAM_FLASH_SET	EXYNOS4210210_GPE0(2)
+
+#define GPIO_TSP_LDO_ON		EXYNOS4_GPL0(3)
+#define GPIO_TSP_RST		EXYNOS4_GPL0(5)
+#define GPIO_TSP_INT		EXYNOS4_GPX0(4)
+
+#define GPIO_LCD_EN		EXYNOS4_GPL0(7)
+#define GPIO_UART_SEL		EXYNOS4_GPY4(7)
+
+#define GPIO_LED_BACKLIGHT_RESET	EXYNOS4_GPK1(1)
+
+#define GPIO_CAM_PCLK		EXYNOS4210_GPJ0(0)
+#define GPIO_CAM_VSYNC		EXYNOS4210_GPJ0(1)
+#define GPIO_CAM_HSYNC		EXYNOS4210_GPJ0(2)
+
+#define GPIO_CAM_MCLK		EXYNOS4210_GPJ1(3)
+
+#define GPIO_2M_nSTBY		EXYNOS4_GPL2(0)
+#define GPIO_2M_nRST		EXYNOS4_GPL2(1)
+#define GPIO_3M_nSTBY		EXYNOS4_GPL2(2)
+#define GPIO_3M_nRST		EXYNOS4_GPL2(7)
+
+#define GPIO_DET_35		EXYNOS4_GPX3(2)
+#define GPIO_DET_35_AF		0xF
+
+#define GPIO_EAR_SEND_END	EXYNOS4_GPX3(6)
+#define GPIO_EAR_SEND_END_AF	0xF
+
+#define GPIO_GPS_nRST		EXYNOS4_GPY5(4)
+#define GPIO_GPS_PWR_EN		EXYNOS4_GPY5(5)
+
+#define GPIO_BT_RXD		EXYNOS4_GPA0(0)
+#define GPIO_BT_RXD_AF		2
+
+#define GPIO_BT_TXD		EXYNOS4_GPA0(1)
+#define GPIO_BT_TXD_AF		2
+
+#define GPIO_BT_CTS		EXYNOS4_GPA0(2)
+#define GPIO_BT_CTS_AF		2
+
+#define GPIO_BT_RTS		EXYNOS4_GPA0(3)
+#define GPIO_BT_RTS_AF		2
+
+#define GPIO_GPS_RXD		EXYNOS4_GPA0(4)
+#define GPIO_GPS_RXD_AF		2
+
+#define GPIO_GPS_TXD		EXYNOS4_GPA0(5)
+#define GPIO_GPS_TXD_AF		2
+
+#define GPIO_GPS_CTS		EXYNOS4_GPA0(6)
+#define GPIO_GPS_CTS_AF		2
+
+#define GPIO_GPS_RTS		EXYNOS4_GPA0(7)
+#define GPIO_GPS_RTS_AF		2
+
+#define GPIO_ALC_nRST		EXYNOS4_GPX1(7)
+
+#define GPIO_DOUBLE_RR		EXYNOS4_GPL2(3)
+/* #define GPIO_2MIC_EN		EXYNOS4_GPL2(5) */
+
+#define GPIO_CURR_ADJ		EXYNOS4_GPY5(7)
+#define GPIO_TA_EN		EXYNOS4_GPY6(6)
+#define GPIO_TA_nCHG		EXYNOS4_GPL2(4)
+#define GPIO_TA_nCONNECTED	EXYNOS4_GPX3(5)
+
+/* Charger I2C for H/W rev02 */
+#define GPIO_CHG_SDA		EXYNOS4_GPC1(2)
+#define GPIO_CHG_SCL		EXYNOS4_GPC1(0)
+
+#define GPIO_IPC_RXD		EXYNOS4_GPA1(4)
+#define GPIO_IPC_RXD_AF		2
+
+#define GPIO_IPC_TXD		EXYNOS4_GPA1(5)
+#define GPIO_IPC_TXD_AF		2
+
+#define GPIO_PHONE_ON		EXYNOS4_GPC1(1)
+#define GPIO_PHONE_ACTIVE	EXYNOS4_GPX1(6)
+#define GPIO_PDA_ACTIVE		EXYNOS4_GPY4(2)
+#define GPIO_CP_DUMP_INT	EXYNOS4_GPX1(2)
+#define GPIO_CP_RST		EXYNOS4_GPX1(4)
+#define GPIO_CP_PMU_RST		EXYNOS4_GPX1(4)
+#define GPIO_CP_REQ_RESET	EXYNOS4_GPY4(6)
+#define GPIO_IPC_SLAVE_WAKEUP	EXYNOS4_GPX1(0)
+#define GPIO_IPC_HOST_WAKEUP	EXYNOS4_GPX1(1)
+#define GPIO_SUSPEND_REQUEST	EXYNOS4_GPX1(3)
+#define GPIO_LVDS_NSHDN		EXYNOS4_GPX1(5)
+#define GPIO_ACTIVE_STATE	EXYNOS4_GPY3(5)
+
+#define IRQ_PHONE_ACTIVE	IRQ_EINT14
+#define IRQ_SUSPEND_REQUEST	IRQ_EINT11
+#define IRQ_IPC_HOST_WAKEUP	IRQ_EINT9
+
+#define EXYNOS4_GPD_0_0_TOUT_0	(0x2 << 0)
+#if defined(CONFIG_FB_MDNIE_PWM)
+#define EXYNOS4_GPD_0_1_TOUT_1	(0x3 << 4)
+#else
+#define EXYNOS4_GPD_0_1_TOUT_1	(0x2 << 4)
+#endif
+#define EXYNOS4_GPD_0_2_TOUT_2	(0x2 << 8)
+#define EXYNOS4_GPD_0_3_TOUT_3	(0x2 << 12)
+
+#define GPIO_WLAN_EN		EXYNOS4_GPL1(2)
+#define GPIO_WLAN_EN2		EXYNOS4_GPL0(6)
+#define GPIO_WLAN_EN_AF		1
+#define GPIO_WLAN_nRST		EXYNOS4_GPL0(4)
+
+//#define GPIO_BT_EN		EXYNOS4_GPL0(4)
+#define GPIO_BT_nRST		EXYNOS4_GPL1(0)
+
+#define GPIO_WLAN_HOST_WAKE	EXYNOS4_GPX2(5)
+#define GPIO_WLAN_HOST_WAKE_AF	0xF
+
+#define GPIO_BT_HOST_WAKE	EXYNOS4_GPX2(6)
+#define GPIO_BT_HOST_WAKE_AF	0xF
+
+//#define GPIO_BT_WAKE		EXYNOS4_GPX3(1)
+
+#define GPIO_WLAN_SDIO_CLK	EXYNOS4_GPK3(0)
+#define GPIO_WLAN_SDIO_CLK_AF	2
+
+#define GPIO_WLAN_SDIO_CMD	EXYNOS4_GPK3(1)
+#define GPIO_WLAN_SDIO_CMD_AF	2
+
+#define GPIO_WLAN_SDIO_D0	EXYNOS4_GPK3(3)
+#define GPIO_WLAN_SDIO_D0_AF	2
+
+#define GPIO_WLAN_SDIO_D1	EXYNOS4_GPK3(4)
+#define GPIO_WLAN_SDIO_D1_AF	2
+
+#define GPIO_WLAN_SDIO_D2	EXYNOS4_GPK3(5)
+#define GPIO_WLAN_SDIO_D2_AF	2
+
+#define GPIO_WLAN_SDIO_D3	EXYNOS4_GPK3(6)
+#define GPIO_WLAN_SDIO_D3_AF	2
+
+#define GPIO_HW_REV0		EXYNOS4210_GPE1(0)
+#define GPIO_HW_REV1		EXYNOS4210_GPE1(1)
+#define GPIO_HW_REV2		EXYNOS4210_GPE1(2)
+#define GPIO_HW_REV3		EXYNOS4210_GPE1(3)
+
+#define GPIO_HDMI_EN1		EXYNOS4_GPL1(1)
+#define GPIO_MHL_RST		EXYNOS4_GPF3(4)
+#define GPIO_MHL_INT		EXYNOS4_GPF3(5)
+#define GPIO_MHL_INT_AF		S3C_GPIO_SFN(0xF)
+#define	GPIO_MHL_WAKE_UP_AF	S3C_GPIO_SFN(0xF)
+#define GPIO_HDMI_HPD		EXYNOS4_GPX3(7)
+
+#define GPIO_MSENSE_INT		EXYNOS4_GPX2(2)
+#define GPIO_DOCK_INT		EXYNOS4_GPX2(4)
+
+#define GPIO_IRDA_CONTROL	EXYNOS4_GPX3(0)
+#define GPIO_USB_OTG_EN		EXYNOS4_GPX3(3)
+#define GPIO_USB_SEL1		EXYNOS4_GPY3(4)
+#define GPIO_USB_SEL2		EXYNOS4_GPY3(7)
+#define GPIO_USB_SEL3		EXYNOS4_GPY4(5)
+#define GPIO_IF_CON_SENSE	EXYNOS4_GPY4(3)
+
+#define GPIO_MSENSOR_MHL_SDA_28V	EXYNOS4_GPD0(2)
+#define	GPIO_MSENSOR_MHL_SDA_AF			0x3
+#define GPIO_MSENSOR_MHL_SCL_28V	EXYNOS4_GPD0(3)
+#define	GPIO_MSENSOR_MHL_SCL_AF			0x3
+#define GPIO_MHL_SDA_18V		EXYNOS4_GPY3(0)
+#define GPIO_MHL_SCL_18V		EXYNOS4_GPY3(2)
+
+#define GPIO_AP_HDMI_SDA	GPIO_MSENSOR_MHL_SDA_28V
+#define	GPIO_AP_HDMI_SDA_AF	GPIO_MSENSOR_MHL_SDA_AF
+#define GPIO_AP_HDMI_SCL	GPIO_MSENSOR_MHL_SCL_28V
+#define	GPIO_AP_HDMI_SCL_AF	GPIO_MSENSOR_MHL_SCL_AF
+#define GPIO_AP_SDA_18V		GPIO_MHL_SDA_18V
+#define GPIO_AP_SCL_18V		GPIO_MHL_SCL_18V
+
+#define MHL_INT_IRQ		gpio_to_irq(GPIO_MHL_INT)
+#define MHL_WAKEUP_IRQ		gpio_to_irq(GPIO_MHL_WAKE_UP)
+
+#define GPIO_MIC_BIAS_EN	EXYNOS4_GPY6(7)
+#define GPIO_EAR_MIC_BIAS_EN	EXYNOS4_GPL2(6)
+
+#define GPIO_TDMB_EN		EXYNOS4_GPC0(1)
+#define GPIO_TDMB_RST_N		EXYNOS4_GPB(5)
+#define GPIO_TDMB_INT		EXYNOS4_GPB(4)
+#define GPIO_TDMB_INT_AF	0xf
+
+#define GPIO_PEN_SDA_28V	EXYNOS4_GPB(2)
+#define GPIO_PEN_SCL_28V	EXYNOS4_GPB(3)
+#define GPIO_PEN_LDO_EN		EXYNOS4_GPY6(0)
+#define GPIO_PEN_PDCT_18V	EXYNOS4_GPY6(4)
+#define GPIO_PEN_SLP_18V	EXYNOS4_GPY6(5)
+#define GPIO_PEN_IRQ_18V	EXYNOS4_GPL2(5)
+
+#define GPIO_REMOTE_SENSE_IRQ	EXYNOS4_GPX0(2)
+
+#define GPIO_ACCESSORY_EN	EXYNOS4_GPY6(1)
+#define GPIO_ACCESSORY_INT	EXYNOS4_GPX1(7)
+#define GPIO_ACCESSORY_OUT_5V	EXYNOS4_GPY4(4)
+
+#define GPIO_SIM_DETECT	EXYNOS4_GPX0(3)
+#endif /* __MACH_GPIO_P4_H */
diff --git a/arch/arm/mach-exynos/include/mach/gpio-p8.h b/arch/arm/mach-exynos/include/mach/gpio-p8.h
new file mode 100644
index 0000000..b6e67b4
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/gpio-p8.h
@@ -0,0 +1,233 @@
+#ifndef __MACH_GPIO_P8_H
+#define __MACH_GPIO_P8_H __FILE__
+
+#define GPIO_XMMC0_CDn		EXYNOS4_GPK0(2)
+
+#define GPIO_PS_ALS_SDA		EXYNOS4_GPK2(2)
+#define GPIO_PS_ALS_SCL		EXYNOS4_GPK3(2)
+
+#define GPIO_GYRO_INT		EXYNOS4_GPX0(0)
+#define GPIO_PS_VOUT		EXYNOS4_GPL0(6)
+#define GPIO_PS_VOUT_WAKE	EXYNOS4_GPX0(1)
+
+#define GPIO_BUCK1_EN_A		EXYNOS4_GPX0(5)
+#define GPIO_BUCK1_EN_B		EXYNOS4_GPX0(6)
+#define GPIO_BUCK2_EN		EXYNOS4_GPL0(0)
+#define GPIO_PMIC_IRQ		EXYNOS4_GPX0(7)
+
+#define GPIO_VOL_UP		EXYNOS4_GPX2(0)
+#define GPIO_VOL_DOWN		EXYNOS4_GPX2(1)
+
+#define GPIO_nPOWER		EXYNOS4_GPX2(7)
+
+/* #define VT_CAM_SDA_18V		EXYNOS4_GPC1(0) */
+/* #define VT_CAM_SCL_18V		EXYNOS4_GPC1(2) */
+
+#define CODEC_VT_SDA_18V	EXYNOS4_GPC1(3)
+#define CODEC_VT_SCL_18V	EXYNOS4_GPC1(4)
+
+#define GPIO_FUEL_SDA		EXYNOS4_GPY4(0)
+#define GPIO_FUEL_SCL		EXYNOS4_GPY4(1)
+#define GPIO_FUEL_ALERT	EXYNOS4_GPX2(3)
+
+#define GPIO_MASSMEM_EN_LEVEL	0
+
+#define GPIO_CAM_MOVIE_EN	EXYNOS4_GPL0(1)
+#define GPIO_CAM_FLASH_EN	EXYNOS4_GPL0(2)
+/* #define GPIO_CAM_FLASH_SET	EXYNOS4_GPE0(2) */
+
+#define GPIO_TSP_LDO_ON		EXYNOS4_GPL0(3)
+/* #define GPIO_TSP_RST		EXYNOS4_GPL0(5) */
+/* #define GPIO_TSP_INT		EXYNOS4_GPX0(4) */
+#define GPIO_TSP_SDA		EXYNOS4_GPA1(2)
+#define GPIO_TSP_SCL		EXYNOS4_GPA1(3)
+#define GPIO_TSP_VENDOR		EXYNOS4_GPY5(6)
+#define GPIO_TSP_INT_18V	EXYNOS4_GPX1(5)
+
+#define GPIO_LCD_RST		EXYNOS4_GPF0(1)
+#define GPIO_LCD_EN		EXYNOS4_GPL0(7)
+#define GPIO_LCD_LDO_EN	EXYNOS4_GPK1(1)
+#define GPIO_UART_SEL		EXYNOS4_GPY4(7)
+
+/* #define GPIO_CAM_PCLK		EXYNOS4_GPJ0(0) */
+/* #define GPIO_CAM_VSYNC		EXYNOS4_GPJ0(1) */
+/* #define GPIO_CAM_HSYNC		EXYNOS4_GPJ0(2) */
+
+#define GPIO_CAM_MCLK		EXYNOS4210_GPJ1(3)
+#define GPIO_CAM_AVDD_EN	EXYNOS4210_GPJ1(4)
+
+#define GPIO_2M_nSTBY		EXYNOS4_GPL2(0)
+#define GPIO_2M_nRST		EXYNOS4_GPL2(1)
+#define GPIO_3M_nSTBY		EXYNOS4_GPL2(2)
+#define GPIO_3M_nRST		EXYNOS4_GPL2(7)
+
+#define GPIO_DET_35		EXYNOS4_GPX3(2)
+#define GPIO_DET_35_AF		0xF
+
+#define GPIO_EAR_SEND_END	EXYNOS4_GPX3(6)
+#define GPIO_EAR_SEND_END_AF	0xF
+
+#define GPIO_GPS_nRST		EXYNOS4_GPY5(4)
+#define GPIO_GPS_PWR_EN		EXYNOS4_GPY5(5)
+
+#define GPIO_BT_RXD		EXYNOS4_GPA0(0)
+#define GPIO_BT_RXD_AF		2
+
+#define GPIO_BT_TXD		EXYNOS4_GPA0(1)
+#define GPIO_BT_TXD_AF		2
+
+#define GPIO_BT_CTS		EXYNOS4_GPA0(2)
+#define GPIO_BT_CTS_AF		2
+
+#define GPIO_BT_RTS		EXYNOS4_GPA0(3)
+#define GPIO_BT_RTS_AF		2
+
+#define GPIO_GPS_RXD		EXYNOS4_GPA0(4)
+#define GPIO_GPS_RXD_AF		2
+
+#define GPIO_GPS_TXD		EXYNOS4_GPA0(5)
+#define GPIO_GPS_TXD_AF		2
+
+#define GPIO_GPS_CTS		EXYNOS4_GPA0(6)
+#define GPIO_GPS_CTS_AF		2
+
+#define GPIO_GPS_RTS		EXYNOS4_GPA0(7)
+#define GPIO_GPS_RTS_AF		2
+
+/* #define GPIO_ALC_nRST		EXYNOS4_GPX1(7) */
+
+#define GPIO_DOUBLE_RR		EXYNOS4_GPL2(3)
+/* #define GPIO_2MIC_EN		 EXYNOS4_GPL2(5) */
+
+#define GPIO_CURR_ADJ	     EXYNOS4_GPY5(7)
+#define GPIO_TA_EN	     EXYNOS4_GPY6(6)
+#define GPIO_TA_nCHG	     EXYNOS4_GPX0(4)
+#define GPIO_TA_nCONNECTED   EXYNOS4_GPX3(5)
+
+/* #define GPIO_CHG_SDA_28V	EXYNOS4_GPB(2) */
+/* #define GPIO_CHG_SCL_28V	EXYNOS4_GPB(3) */
+
+#define GPIO_IPC_RXD		EXYNOS4_GPA1(4)
+#define GPIO_IPC_RXD_AF		2
+
+#define GPIO_IPC_TXD		EXYNOS4_GPA1(5)
+#define GPIO_IPC_TXD_AF		2
+
+#define GPIO_PHONE_ON		EXYNOS4_GPC1(1)
+#define GPIO_PHONE_ACTIVE	EXYNOS4_GPX1(6)
+#define GPIO_PDA_ACTIVE		EXYNOS4_GPY4(2)
+#define GPIO_CP_DUMP_INT	EXYNOS4_GPX1(2)
+#define GPIO_CP_RST		EXYNOS4_GPX1(4)
+#define GPIO_CP_REQ_RESET	EXYNOS4_GPY4(6)
+#define GPIO_IPC_SLAVE_WAKEUP	EXYNOS4_GPX1(0)
+#define GPIO_IPC_HOST_WAKEUP	EXYNOS4_GPX1(1)
+#define GPIO_SUSPEND_REQUEST	EXYNOS4_GPX1(3)
+/* #define GPIO_LVDS_NSHDN		EXYNOS4_GPX1(5) */
+#define GPIO_ACTIVE_STATE	EXYNOS4_GPY3(5)
+
+#define IRQ_PHONE_ACTIVE	IRQ_EINT14
+#define IRQ_SUSPEND_REQUEST	IRQ_EINT11
+#define IRQ_IPC_HOST_WAKEUP	IRQ_EINT9
+
+#define EXYNOS4_GPD_0_0_TOUT_0	(0x2 << 0)
+#define EXYNOS4_GPD_0_1_TOUT_1	(0x2 << 4)
+#define EXYNOS4_GPD_0_2_TOUT_2	(0x2 << 8)
+#define EXYNOS4_GPD_0_3_TOUT_3	(0x2 << 12)
+
+#define GPIO_WLAN_EN		EXYNOS4_GPL1(2)
+#define GPIO_WLAN_EN2		EXYNOS4_GPL0(6)
+#define GPIO_WLAN_EN_AF		1
+#define GPIO_WLAN_nRST		EXYNOS4_GPL0(4)
+
+/* CSR8811 Project(Alan.Ko) 2011.07.02 */
+/* #define GPIO_BT_EN		 EXYNOS4_GPL0(4) */
+/* CSR8811 Project(Alan.Ko) end */
+
+#define GPIO_BT_nRST		EXYNOS4_GPL1(0)
+
+#define GPIO_WLAN_HOST_WAKE	EXYNOS4_GPX2(5)
+#define GPIO_WLAN_HOST_WAKE_AF	0xF
+
+#define GPIO_BT_HOST_WAKE	EXYNOS4_GPX2(6)
+#define GPIO_BT_HOST_WAKE_AF	0xF
+
+/* CSR8811 Project(Alan.Ko) 2011.07.02 */
+/* #define GPIO_BT_WAKE		 EXYNOS4_GPX3(1) */
+/* CSR8811 Project(Alan.Ko) end */
+
+#define GPIO_WLAN_SDIO_CLK	EXYNOS4_GPK3(0)
+#define GPIO_WLAN_SDIO_CLK_AF	2
+
+#define GPIO_WLAN_SDIO_CMD	EXYNOS4_GPK3(1)
+#define GPIO_WLAN_SDIO_CMD_AF	2
+
+#define GPIO_WLAN_SDIO_D0	EXYNOS4_GPK3(3)
+#define GPIO_WLAN_SDIO_D0_AF	2
+
+#define GPIO_WLAN_SDIO_D1	EXYNOS4_GPK3(4)
+#define GPIO_WLAN_SDIO_D1_AF	2
+
+#define GPIO_WLAN_SDIO_D2	EXYNOS4_GPK3(5)
+#define GPIO_WLAN_SDIO_D2_AF	2
+
+#define GPIO_WLAN_SDIO_D3	EXYNOS4_GPK3(6)
+#define GPIO_WLAN_SDIO_D3_AF	2
+
+#define GPIO_HW_REV0		EXYNOS4_GPY5(0)
+#define GPIO_HW_REV1		EXYNOS4_GPY5(1)
+#define GPIO_HW_REV2		EXYNOS4_GPY5(2)
+#define GPIO_HW_REV3		EXYNOS4_GPY5(3)
+
+#define GPIO_HDMI_EN1		EXYNOS4_GPL1(1)
+#define GPIO_MHL_RST		EXYNOS4_GPF3(4)
+#define GPIO_MHL_INT		EXYNOS4_GPF3(5)
+#define GPIO_MHL_INT_AF		S3C_GPIO_SFN(0xF)
+#define	GPIO_MHL_WAKE_UP_AF	S3C_GPIO_SFN(0xF)
+#define GPIO_HDMI_HPD		EXYNOS4_GPX3(7)
+
+#define GPIO_SIM_DETECT		EXYNOS4_GPX0(3)
+
+#define GPIO_MSENSE_INT		EXYNOS4_GPX2(2)
+#define GPIO_DOCK_INT		EXYNOS4_GPX2(4)
+
+/* IRDA */
+#define GPIO_IRDA_EN		EXYNOS4_GPX3(0)
+#define GPIO_IRDA_nINT	    EXYNOS4_GPB(4)
+#define GPIO_IRDA_nRST	    EXYNOS4_GPB(5)
+#define GPIO_IRDA_SCL_28V   EXYNOS4_GPK1(0)
+#define GPIO_IRDA_SDA_28V   EXYNOS4_GPK1(2)
+
+#define GPIO_USB_OTG_EN		EXYNOS4_GPX3(3)
+#define GPIO_USB_SEL1		EXYNOS4_GPY3(4)
+#define GPIO_USB_SEL2		EXYNOS4_GPY3(7)
+#define GPIO_USB_SEL3		EXYNOS4_GPY4(5)
+#define GPIO_IF_CON_SENSE	EXYNOS4_GPY4(3)
+
+#define GPIO_MSENSOR_MHL_SDA_28V	EXYNOS4_GPD0(2)
+#define	GPIO_MSENSOR_MHL_SDA_AF			0x3
+#define GPIO_MSENSOR_MHL_SCL_28V	EXYNOS4_GPD0(3)
+#define	GPIO_MSENSOR_MHL_SCL_AF			0x3
+#define GPIO_MHL_SDA_18V		EXYNOS4_GPY3(0)
+#define GPIO_MHL_SCL_18V		EXYNOS4_GPY3(2)
+
+#define GPIO_AP_HDMI_SDA	GPIO_MSENSOR_MHL_SDA_28V
+#define	GPIO_AP_HDMI_SDA_AF	GPIO_MSENSOR_MHL_SDA_AF
+#define GPIO_AP_HDMI_SCL	GPIO_MSENSOR_MHL_SCL_28V
+#define	GPIO_AP_HDMI_SCL_AF	GPIO_MSENSOR_MHL_SCL_AF
+#define GPIO_AP_SDA_18V		GPIO_MHL_SDA_18V
+#define GPIO_AP_SCL_18V		GPIO_MHL_SCL_18V
+
+#define MHL_INT_IRQ		gpio_to_irq(GPIO_MHL_INT)
+/* #define MHL_WAKEUP_IRQ		gpio_to_irq(GPIO_MHL_WAKE_UP) */
+
+#define GPIO_SUB_MIC_BIAS_EN	EXYNOS4_GPY6(7)
+#define GPIO_MAIN_MIC_BIAS_EN EXYNOS4_GPC0(1)
+#define GPIO_EAR_MIC_BIAS_EN	EXYNOS4_GPL2(6)
+
+#define GPIO_REMOTE_SENSE_IRQ	EXYNOS4_GPX0(2)
+
+#define GPIO_ACCESSORY_EN	EXYNOS4_GPY6(1)
+#define GPIO_ACCESSORY_INT	EXYNOS4_GPX1(7)
+#define GPIO_ACCESSORY_OUT_5V EXYNOS4_GPY4(4)
+
+#endif				/* __MACH_GPIO_P8_REV01_H */
diff --git a/arch/arm/mach-exynos/include/mach/gpio-q1.h b/arch/arm/mach-exynos/include/mach/gpio-q1.h
new file mode 100644
index 0000000..1119d0b
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/gpio-q1.h
@@ -0,0 +1,296 @@
+#ifndef __MACH_GPIO_Q1_H
+#define __MACH_GPIO_Q1_H __FILE__
+
+#if defined(CONFIG_MACH_Q1_BD)
+
+#define GPIO_OLED_DET		EXYNOS4_GPL0(7)
+
+#define GPIO_XMMC0_CDn		EXYNOS4_GPK0(2)
+
+#define GPIO_PS_ALS_SDA		EXYNOS4_GPK2(2)
+#define GPIO_PS_ALS_SCL		EXYNOS4_GPK3(2)
+
+#define GPIO_GYRO_INT		EXYNOS4_GPX0(0)
+#define GPIO_GYRO_FIFOP_INT	EXYNOS4_GPX0(1)
+#define GPIO_PS_ALS_INT		EXYNOS4_GPX0(2)
+
+#define GPIO_BUCK1_EN_A		EXYNOS4_GPX0(5)
+#define GPIO_BUCK1_EN_B		EXYNOS4_GPX0(6)
+#define GPIO_BUCK2_EN		EXYNOS4_GPL0(0)
+#define GPIO_PMIC_IRQ		EXYNOS4_GPX0(7)
+
+#define GPIO_VOL_UP		EXYNOS4_GPX2(0)
+#define GPIO_VOL_DOWN		EXYNOS4_GPX2(1)
+#define GPIO_nPOWER		EXYNOS4_GPX2(7)
+
+#define GPIO_OK_KEY		EXYNOS4_GPX3(5)
+
+#define VT_CAM_SDA_18V		EXYNOS4_GPC1(0)
+#define VT_CAM_SCL_18V		EXYNOS4_GPC1(2)
+
+#define CODEC_VT_SDA_18V	EXYNOS4_GPC1(3)
+#define CODEC_VT_SCL_18V	EXYNOS4_GPC1(4)
+
+#define GPIO_ISP_RESET		EXYNOS4_GPY3(7)
+#define GPIO_FUEL_SDA		EXYNOS4_GPY4(0)
+#define GPIO_FUEL_SCL		EXYNOS4_GPY4(1)
+#define GPIO_FUEL_ALERT		EXYNOS4_GPX2(3)
+
+#define GPIO_USB_SDA		EXYNOS4210_GPE1(0)
+#define GPIO_USB_SCL		EXYNOS4210_GPE1(1)
+#define GPIO_MASSMEM_EN		EXYNOS4_GPL1(1)
+#define GPIO_MASSMEM_EN_LEVEL	0
+#define GPIO_TSP_INT		EXYNOS4_GPX0(4)
+#define GPIO_TSP_SDA		EXYNOS4_GPA1(2)
+#define GPIO_TSP_SCL		EXYNOS4_GPA1(3)
+
+#define GPIO_CAM_IO_EN		EXYNOS4210_GPE2(1)
+#define GPIO_CAM_SENSOR_CORE	EXYNOS4210_GPE2(5)
+#define GPIO_TSP_LDO_ON		EXYNOS4_GPL0(3)
+
+#define GPIO_LCD_EN		EXYNOS4_GPY3(1)
+#define GPIO_MLCD_RST		EXYNOS4_GPY4(5)
+
+#define GPIO_USB_SEL		EXYNOS4_GPL0(6)
+#define GPIO_UART_SEL		EXYNOS4_GPY4(7)
+
+#define GPIO_3_TOUCH_SCL	EXYNOS4_GPK1(0)
+#define GPIO_8M_AF_EN		EXYNOS4_GPK1(1)
+#define GPIO_3_TOUCH_SDA	EXYNOS4_GPK1(2)
+#define GPIO_3_TOUCH_INT	EXYNOS4_GPL0(5)
+
+#define GPIO_VT_CAM_15V	EXYNOS4210_GPE2(2)
+
+#define GPIO_CAM_MCLK		EXYNOS4210_GPJ1(3)
+
+#define GPIO_CAM_VGA_nSTBY	EXYNOS4_GPL2(0)
+#define GPIO_CAM_VGA_nRST	EXYNOS4_GPL2(1)
+
+#define GPIO_DET_35		EXYNOS4_GPX3(2)
+#define GPIO_DET_35_AF		0xF
+
+#define GPIO_EAR_SEND_END	EXYNOS4_GPX3(6)
+#define GPIO_EAR_SEND_END_AF	0xF
+
+#define GPIO_GPS_PWR_EN		EXYNOS4210_GPE0(3)
+#define GPIO_GPS_nRST		EXYNOS4210_GPE0(4)
+
+#define GPIO_BT_RXD		EXYNOS4_GPA0(0)
+#define GPIO_BT_RXD_AF		2
+
+#define GPIO_BT_TXD		EXYNOS4_GPA0(1)
+#define GPIO_BT_TXD_AF		2
+
+#define GPIO_BT_CTS		EXYNOS4_GPA0(2)
+#define GPIO_BT_CTS_AF		2
+
+#define GPIO_BT_RTS		EXYNOS4_GPA0(3)
+#define GPIO_BT_RTS_AF		2
+
+#define GPIO_GPS_RXD		EXYNOS4_GPA0(4)
+#define GPIO_GPS_RXD_AF		2
+
+#define GPIO_GPS_TXD		EXYNOS4_GPA0(5)
+#define GPIO_GPS_TXD_AF		2
+
+#define GPIO_GPS_CTS		EXYNOS4_GPA0(6)
+#define GPIO_GPS_CTS_AF		2
+
+#define GPIO_GPS_RTS		EXYNOS4_GPA0(7)
+#define GPIO_GPS_RTS_AF		2
+
+#define GPIO_NFC_SCL		EXYNOS4_GPY0(0)
+#define GPIO_NFC_SDA		EXYNOS4_GPY0(1)
+#define GPIO_NFC_EN		EXYNOS4_GPL2(6)
+#define GPIO_NFC_FIRM		EXYNOS4_GPL2(7)
+#define GPIO_NFC_IRQ		EXYNOS4_GPX1(7)
+
+#define GPIO_2MIC_PWDN		EXYNOS4_GPL2(3)
+#define GPIO_2MIC_RST		EXYNOS4_GPL2(4)
+#define GPIO_2MIC_EN		EXYNOS4_GPL2(5)
+
+#ifdef	CONFIG_CHARGER_MAX8922_U1	/* sub-charger */
+#define GPIO_CHG_EN		EXYNOS4_GPL2(2)
+#define GPIO_CHG_ING_N		EXYNOS4_GPL2(4)
+#define GPIO_TA_nCONNECTED	EXYNOS4_GPL2(5)
+#endif
+
+#ifdef	CONFIG_SMB136_CHARGER_Q1	/* sub-charger */
+#define GPIO_CHG_SDA		EXYNOS4_GPY0(4)
+#define GPIO_CHG_SCL		EXYNOS4_GPY0(5)
+#define GPIO_CHG_EN		EXYNOS4_GPL2(2)
+#define GPIO_OTG_EN		EXYNOS4_GPX3(3)
+#define GPIO_CHG_ING_N		EXYNOS4_GPL2(5)
+#endif
+
+#ifdef	CONFIG_CHARGER_SMB328_Q1	/* sub-charger */
+#define GPIO_CHG_SDA		EXYNOS4_GPY0(4)
+#define GPIO_CHG_SCL		EXYNOS4_GPY0(5)
+#define GPIO_CHG_EN		EXYNOS4_GPL2(2)
+#define GPIO_TA_nCONNECTED	EXYNOS4_GPL2(5)
+#endif
+
+#define GPIO_2MIC_SDA		EXYNOS4_GPC1(2)
+#define GPIO_2MIC_SCL		EXYNOS4_GPC1(0)
+
+#define GPIO_FLM_RXD		EXYNOS4_GPA1(4)
+#define GPIO_FLM_RXD_AF		2
+
+#define GPIO_FLM_TXD		EXYNOS4_GPA1(5)
+#define GPIO_FLM_TXD_AF		2
+
+/* Modem Interface GPIOs - Q1 HSIC */
+#if !defined(CONFIG_SEC_MODEM_M0_TD)
+#define GPIO_PHONE_ON		EXYNOS4_GPC1(1)
+#define GPIO_PHONE_ACTIVE	EXYNOS4_GPX1(6)
+#define GPIO_PDA_ACTIVE		EXYNOS4_GPY4(2)
+#define GPIO_CP_DUMP_INT	EXYNOS4_GPX1(2)
+#define GPIO_CP_RST		EXYNOS4_GPX1(4)
+#define GPIO_CP_REQ_RESET	EXYNOS4_GPY4(6)
+#define GPIO_IPC_SLAVE_WAKEUP	EXYNOS4_GPX1(0)
+#define GPIO_IPC_HOST_WAKEUP	EXYNOS4_GPX1(1)
+#define GPIO_SUSPEND_REQUEST	EXYNOS4_GPX1(3)
+#define GPIO_ISP_INT		EXYNOS4_GPX1(5)
+#define GPIO_ACTIVE_STATE	EXYNOS4_GPY3(5)
+
+#define IRQ_PHONE_ACTIVE	IRQ_EINT14
+#define IRQ_SUSPEND_REQUEST	IRQ_EINT11
+#define IRQ_IPC_HOST_WAKEUP	IRQ_EINT9
+#else
+#define GPIO_PHONE_ON		EXYNOS4_GPC1(1)
+#define GPIO_PHONE_ACTIVE	EXYNOS4_GPX1(6)
+#define GPIO_PDA_ACTIVE		EXYNOS4_GPY4(2)
+#define GPIO_CP_DUMP_INT	EXYNOS4_GPX1(2)
+#define GPIO_IPC_MRDY		EXYNOS4_GPY4(3)
+#define GPIO_IPC_SUB_MRDY	EXYNOS4_GPY3(3)
+#define GPIO_IPC_SRDY		EXYNOS4_GPX1(0)
+#define GPIO_IPC_SUB_SRDY	EXYNOS4_GPX1(4)
+#define GPIO_AP_CP_INT1		EXYNOS4_GPY3(5)
+#define GPIO_AP_CP_INT2		EXYNOS4_GPY4(4)
+/* not use (S5PV310_GPX1(1) => NC pin) */
+#define GPIO_CP_RST		EXYNOS4_GPX1(1)
+#define GPIO_CP_REQ_RESET	EXYNOS4_GPX1(1)
+#define GPIO_IPC_SLAVE_WAKEUP	EXYNOS4_GPX1(1)
+#define GPIO_IPC_HOST_WAKEUP	EXYNOS4_GPX1(1)
+#define GPIO_SUSPEND_REQUEST	EXYNOS4_GPX1(1)
+#define GPIO_ISP_INT			EXYNOS4_GPX1(1)
+#define GPIO_ACTIVE_STATE	EXYNOS4_GPX1(1)
+
+#define IRQ_PHONE_ACTIVE	IRQ_EINT14
+#define IRQ_IPC_SRDY		IRQ_EINT8
+#define IRQ_IPC_SUB_SRDY	IRQ_EINT12
+#define IRQ_CP_DUMP_INT		IRQ_EINT10
+#endif
+
+#define GPIO_WLAN_EN		EXYNOS4_GPL1(2)
+#define GPIO_WLAN_EN_AF		1
+
+#define GPIO_BT_EN		EXYNOS4_GPL0(4)
+#define GPIO_BT_nRST		EXYNOS4_GPL1(0)
+
+#define GPIO_WLAN_HOST_WAKE	EXYNOS4_GPX2(5)
+#define GPIO_WLAN_HOST_WAKE_AF	0xF
+
+#define GPIO_BT_HOST_WAKE	EXYNOS4_GPX2(6)
+#define GPIO_BT_HOST_WAKE_AF	0xF
+#define IRQ_BT_HOST_WAKE	IRQ_EINT(22)
+
+#define GPIO_BT_WAKE		EXYNOS4_GPX3(1)
+
+#define GPIO_WLAN_SDIO_CLK	EXYNOS4_GPK3(0)
+#define GPIO_WLAN_SDIO_CLK_AF	2
+
+#define GPIO_WLAN_SDIO_CMD	EXYNOS4_GPK3(1)
+#define GPIO_WLAN_SDIO_CMD_AF	2
+
+#define GPIO_WLAN_SDIO_D0	EXYNOS4_GPK3(3)
+#define GPIO_WLAN_SDIO_D0_AF	2
+
+#define GPIO_WLAN_SDIO_D1	EXYNOS4_GPK3(4)
+#define GPIO_WLAN_SDIO_D1_AF	2
+
+#define GPIO_WLAN_SDIO_D2	EXYNOS4_GPK3(5)
+#define GPIO_WLAN_SDIO_D2_AF	2
+
+#define GPIO_WLAN_SDIO_D3	EXYNOS4_GPK3(6)
+#define GPIO_WLAN_SDIO_D3_AF	2
+
+#define GPIO_HW_REV0		EXYNOS4210_GPE1(0)
+#define GPIO_HW_REV1		EXYNOS4210_GPE1(1)
+#define GPIO_HW_REV2		EXYNOS4210_GPE1(2)
+#define GPIO_HW_REV3		EXYNOS4210_GPE1(3)
+
+#define GPIO_MHL_RST		EXYNOS4_GPF3(4)
+#define GPIO_MHL_INT		EXYNOS4_GPF3(5)
+#define GPIO_MHL_INT_AF		S3C_GPIO_SFN(0xF)
+#define GPIO_MHL_WAKE_UP	EXYNOS4210_GPJ1(4)
+#define	GPIO_MHL_WAKE_UP_AF	S3C_GPIO_SFN(0xF)
+#define GPIO_MHL_SEL		EXYNOS4_GPL0(1)
+
+#define GPIO_BOOT_MODE		EXYNOS4_GPX0(3)
+
+#define GPIO_MSENSE_INT		EXYNOS4_GPX2(2)
+#define GPIO_HDMI_EN		EXYNOS4_GPL1(1)
+#define GPIO_HDMI_EN_REV07	EXYNOS4_GPL1(1)
+#define GPIO_HDMI_CEC		EXYNOS4_GPX3(6)
+#define GPIO_HDMI_HPD		EXYNOS4_GPX3(7)
+
+#define GPIO_ACC_INT		EXYNOS4_GPX3(0)
+#define GPIO_USB_OTG_EN		EXYNOS4_GPX3(3)
+
+#define GPIO_MSENSOR_MHL_SDA_28V	EXYNOS4_GPD0(2)
+#define	GPIO_MSENSOR_MHL_SDA_AF		0x3
+#define GPIO_MSENSOR_MHL_SCL_28V	EXYNOS4_GPD0(3)
+#define	GPIO_MSENSOR_MHL_SCL_AF		0x3
+#define GPIO_MHL_SDA_18V		EXYNOS4_GPY3(0)
+#define GPIO_MHL_SCL_18V		EXYNOS4_GPY3(2)
+
+#define GPIO_AP_HDMI_SDA	GPIO_MSENSOR_MHL_SDA_28V
+#define	GPIO_AP_HDMI_SDA_AF	GPIO_MSENSOR_MHL_SDA_AF
+#define GPIO_AP_HDMI_SCL	GPIO_MSENSOR_MHL_SCL_28V
+#define	GPIO_AP_HDMI_SCL_AF	GPIO_MSENSOR_MHL_SCL_AF
+#define GPIO_AP_SDA_18V		GPIO_MHL_SDA_18V
+#define GPIO_AP_SCL_18V		GPIO_MHL_SCL_18V
+
+#define MHL_INT_IRQ		gpio_to_irq(GPIO_MHL_INT)
+#define MHL_WAKEUP_IRQ		gpio_to_irq(GPIO_MHL_WAKE_UP)
+
+#define GPIO_MIC_BIAS_EN	EXYNOS4210_GPE1(4)
+#define GPIO_SUB_MIC_BIAS_EN	EXYNOS4210_GPE2(0)
+#define GPIO_EAR_MIC_BIAS_EN	EXYNOS4210_GPE2(4)
+
+#define GPIO_TDMB_EN		EXYNOS4_GPC0(1)
+#define GPIO_TDMB_RST_N		EXYNOS4_GPB(5)
+#define GPIO_TDMB_INT		EXYNOS4_GPB(4)
+#define GPIO_TDMB_INT_AF	0xf
+
+#if defined(CONFIG_SEC_MODEM_M0_TD)
+#define GPIO_FM_RST			EXYNOS4_GPX1(3)
+#define GPIO_FM_INT				EXYNOS4_GPX2(4)
+#define GPIO_FM_INT_REV07		EXYNOS4_GPX2(4)
+#define GPIO_FM_SDA_28V		EXYNOS4210_GPE2(3)
+#define GPIO_FM_SCL_28V		EXYNOS4210_GPE1(5)
+#else
+#define GPIO_FM_RST			EXYNOS4_GPB(0)
+#define GPIO_FM_INT				EXYNOS4_GPX2(4)
+#define GPIO_FM_INT_REV07		EXYNOS4_GPX2(4)
+#define GPIO_FM_SDA_28V		EXYNOS4_GPB(2)
+#define GPIO_FM_SCL_28V		EXYNOS4_GPB(3)
+#endif
+
+#ifdef CONFIG_EPEN_WACOM_G5SP
+#define GPIO_PEN_PDCT		EXYNOS4210_GPE1(6)
+#define GPIO_PEN_SLP		EXYNOS4210_GPE1(7)
+#define GPIO_PEN_IRQ		EXYNOS4210_GPE0(0)
+#define GPIO_PEN_RESET		EXYNOS4210_GPE0(2)
+#define GPIO_PEN_SDA_18V	EXYNOS4_GPC1(3)
+#define GPIO_PEN_SCL_18V	EXYNOS4_GPC1(4)
+#endif /* CONFIG_EPEN_WACOM_G5SP */
+
+#define GPIO_MOTOR_EN		EXYNOS4_GPL2(4)
+
+#define GPIO_BARO_INT1		EXYNOS4_GPE1(5)
+#define GPIO_BARO_INT2		EXYNOS4_GPE2(3)
+
+#endif
+#endif /* __MACH_GPIO_Q1_H */
diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev00-c1.h b/arch/arm/mach-exynos/include/mach/gpio-rev00-c1.h
new file mode 100644
index 0000000..827f1f9
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/gpio-rev00-c1.h
@@ -0,0 +1,293 @@
+#ifndef __MACH_GPIO_C1_H
+#define __MACH_GPIO_C1_H __FILE__
+
+#include <mach/gpio.h>
+
+extern void midas_config_gpio_table(void);
+extern void midas_config_sleep_gpio_table(void);
+
+#define GPIO_eMMC_EN		EXYNOS4_GPK0(2)
+
+#define GPIO_BOOT_MODE		EXYNOS4_GPX0(3)
+
+#define GPIO_FM_I2S_CLK		EXYNOS4_GPC0(0)
+#define GPIO_FM_I2S_SYNC	EXYNOS4_GPC0(2)
+#define GPIO_FM_I2S_DI		EXYNOS4_GPC0(3)
+#define GPIO_FM_I2S_DO		EXYNOS4_GPC0(4)
+
+#define GPIO_IF_PMIC_SDA	EXYNOS4212_GPM2(0)
+#define GPIO_IF_PMIC_SCL	EXYNOS4212_GPM2(1)
+#define GPIO_PMIC_SDA		EXYNOS4_GPB(2)
+#define GPIO_PMIC_SCL		EXYNOS4_GPB(3)
+
+#define GPIO_ADC_SCL		EXYNOS4_GPY0(2)
+#define GPIO_ADC_SDA		EXYNOS4_GPY0(3)
+#define GPIO_ADC_INT		EXYNOS4_GPX2(4)
+
+#define GPIO_CAM_SPI_SCLK	EXYNOS4_GPB(4)
+#define GPIO_CAM_SPI_SSN	EXYNOS4_GPB(5)
+#define GPIO_CAM_SPI_MISO	EXYNOS4_GPB(6)
+#define GPIO_CAM_SPI_MOSI	EXYNOS4_GPB(7)
+
+#define GPIO_CAM_MCLK		EXYNOS4212_GPJ1(3)
+#define GPIO_VTCAM_MCLK		EXYNOS4212_GPM2(2)
+
+#define GPIO_ISP_STANDBY	EXYNOS4212_GPM0(1)
+#define GPIO_CAM_IO_EN		EXYNOS4212_GPM0(2)
+#define GPIO_ISP_CORE_EN	EXYNOS4212_GPM0(3)
+#define GPIO_CAM_AF_EN		EXYNOS4212_GPM0(4)
+#define GPIO_CAM_VT_nRST	EXYNOS4212_GPM1(6)
+
+#if 1
+#define GPIO_8M_CAM_SCL_18V	EXYNOS4_GPD1(0)
+#define GPIO_8M_CAM_SDA_18V	EXYNOS4_GPD1(1)
+#else
+#define GPIO_8M_CAM_SCL_18V	EXYNOS4212_GPM4(0)
+#define GPIO_8M_CAM_SDA_18V	EXYNOS4212_GPM4(1)
+#define GPIO_8M_CAM_SCL_18V_00	EXYNOS4_GPD1(0)
+#define GPIO_8M_CAM_SDA_18V_00	EXYNOS4_GPD1(1)
+#endif
+
+#define GPIO_VT_CAM_SCL_18V	EXYNOS4212_GPM4(2)
+#define GPIO_VT_CAM_SDA_18V	EXYNOS4212_GPM4(3)
+#define GPIO_VT_CAM_ID		EXYNOS4_GPF1(2)
+
+/* Sensors & NFC*/
+#define GPIO_PS_ALS_EN		EXYNOS4212_GPJ0(5)
+#define GPIO_PS_ALS_SDA_28V	EXYNOS4_GPK1(1)
+#define GPIO_PS_ALS_SCL_28V	EXYNOS4_GPK2(2)
+#define GPIO_PS_ALS_INT		EXYNOS4_GPX0(2)
+
+#define GPIO_ACC_INT		EXYNOS4_GPX0(0)
+
+#define GPIO_GYRO_DE		EXYNOS4_GPL2(0)
+#define GPIO_GPS_nRST		EXYNOS4_GPL2(1)
+#define GPIO_GPS_PWR_EN		EXYNOS4_GPL2(2)
+
+#define GPIO_GYRO_INT		EXYNOS4_GPF0(3)
+#define GPIO_GSENSE_SDA_18V	EXYNOS4_GPD1(2)
+#define GPIO_GSENSE_SCL_18V	EXYNOS4_GPD1(3)
+
+#define GPIO_MSENSOR_INT	EXYNOS4212_GPJ0(7)
+#define GPIO_MSENSOR_SDA_18V	EXYNOS4_GPY2(4)
+#define GPIO_MSENSOR_SCL_18V	EXYNOS4_GPY2(5)
+
+#define GPIO_BENSE_SCL_18V	EXYNOS4_GPY2(3)
+#define GPIO_BSENSE_SDA_18V	EXYNOS4_GPY2(2)
+#define GPIO_BARO_INT		EXYNOS4_GPF0(5)
+
+#define GPIO_TF_EN		EXYNOS4_GPY0(1)
+
+#define GPIO_NFC_SCL_18V	EXYNOS4_GPD1(1)
+#define GPIO_NFC_SDA_18V	EXYNOS4_GPD1(0)
+#define GPIO_NFC_SCL_18V_00	EXYNOS4_GPB(3)
+#define GPIO_NFC_SDA_18V_00	EXYNOS4_GPB(2)
+#define GPIO_NFC_IRQ		EXYNOS4_GPX1(7)
+#define GPIO_NFC_EN		EXYNOS4_GPL2(6)
+#define GPIO_NFC_FIRMWARE	EXYNOS4_GPL2(7)
+#define GPIO_NFC_CLK_REQ	EXYNOS4212_GPM0(0)
+/* Sensors & NFC*/
+
+
+#define GPIO_MIC_BIAS_EN	EXYNOS4_GPF1(7)
+#define GPIO_SUB_MIC_BIAS_EN	EXYNOS4_GPF2(0)
+#define GPIO_THIRD_MIC_BIAS_EN	EXYNOS4212_GPJ0(2)
+
+#define GPIO_PMIC_IRQ		EXYNOS4_GPX0(7)
+#define GPIO_IF_PMIC_IRQ	EXYNOS4_GPX1(5)
+
+#define GPIO_TSP_INT		EXYNOS4212_GPM2(3)
+#define GPIO_TSP_SDA_18V	EXYNOS4_GPA1(2)
+#define GPIO_TSP_SCL_18V	EXYNOS4_GPA1(3)
+
+#define GPIO_BT_EN		EXYNOS4_GPL0(6)
+#define GPIO_BT_WAKE		EXYNOS4_GPX3(1)
+#define GPIO_BT_HOST_WAKE	EXYNOS4_GPX2(6)
+#define IRQ_BT_HOST_WAKE	IRQ_EINT(22)
+
+#define GPIO_BT_RXD		EXYNOS4_GPA0(0)
+#define GPIO_BT_RXD_AF		2
+
+#define GPIO_BT_TXD		EXYNOS4_GPA0(1)
+#define GPIO_BT_TXD_AF		2
+
+#define GPIO_BT_CTS		EXYNOS4_GPA0(2)
+#define GPIO_BT_CTS_AF		2
+
+#define GPIO_BT_RTS		EXYNOS4_GPA0(3)
+#define GPIO_BT_RTS_AF		2
+
+#define GPIO_GPS_RXD		EXYNOS4_GPA0(4)
+#define GPIO_GPS_RXD_AF		2
+
+#define GPIO_GPS_TXD		EXYNOS4_GPA0(5)
+#define GPIO_GPS_TXD_AF		2
+
+#define GPIO_GPS_CTS		EXYNOS4_GPA0(6)
+#define GPIO_GPS_CTS_AF		2
+
+#define GPIO_GPS_RTS		EXYNOS4_GPA0(7)
+#define GPIO_GPS_RTS_AF		2
+
+#define GPIO_FLM_RXD		EXYNOS4_GPA1(4)
+#define GPIO_FLM_RXD_AF		2
+
+#define GPIO_FLM_TXD		EXYNOS4_GPA1(5)
+#define GPIO_FLM_TXD_AF		2
+
+#define GPIO_OK_KEY_ANDROID	EXYNOS4_GPX0(1)
+
+#define GPIO_3_TOUCH_SCL	EXYNOS4_GPL0(1)
+#define GPIO_3_TOUCH_SDA	EXYNOS4_GPL0(2)
+#define GPIO_HDMI_EN		EXYNOS4_GPL0(4)
+#define GPIO_3_TOUCH_INT	EXYNOS4212_GPJ0(3)
+#define GPIO_3_TOUCH_EN		EXYNOS4212_GPM0(0)
+
+#define GPIO_PWM0		EXYNOS4_GPD0(0)
+#define GPIO_PWM1		EXYNOS4_GPD0(1)
+#define GPIO_PWM2		EXYNOS4_GPD0(2)
+#define GPIO_PWM3		EXYNOS4_GPD0(3)
+
+#define GPIO_VIBTONE_EN		EXYNOS4212_GPJ0(6)
+
+#define GPIO_WLAN_EN		EXYNOS4212_GPJ0(0)
+#define GPIO_WLAN_EN_AF		1
+#define GPIO_WLAN_HOST_WAKE	EXYNOS4_GPX2(5)
+#define GPIO_WLAN_HOST_WAKE_AF	0xF
+#define GPIO_WLAN_SDIO_CLK	EXYNOS4_GPK3(0)
+#define GPIO_WLAN_SDIO_CLK_AF	2
+#define GPIO_WLAN_SDIO_CMD	EXYNOS4_GPK3(1)
+#define GPIO_WLAN_SDIO_CMD_AF	2
+#define GPIO_WLAN_SDIO_D0	EXYNOS4_GPK3(3)
+#define GPIO_WLAN_SDIO_D0_AF	2
+#define GPIO_WLAN_SDIO_D1	EXYNOS4_GPK3(4)
+#define GPIO_WLAN_SDIO_D1_AF	2
+#define GPIO_WLAN_SDIO_D2	EXYNOS4_GPK3(5)
+#define GPIO_WLAN_SDIO_D2_AF	2
+#define GPIO_WLAN_SDIO_D3	EXYNOS4_GPK3(6)
+#define GPIO_WLAN_SDIO_D3_AF	2
+
+#define GPIO_USB_SEL		EXYNOS4212_GPJ0(1)
+
+#define GPIO_LCD_22V_EN		EXYNOS4212_GPM4(4)
+#define GPIO_LCD_22V_EN_00	EXYNOS4_GPC0(1)
+
+#define GPIO_ISP_TXD		EXYNOS4212_GPM4(5)
+#define GPIO_ISP_RXD		EXYNOS4212_GPM4(6)
+
+#define GPIO_TA_EN		EXYNOS4_GPL2(2)
+
+#define GPIO_MHL_SEL		EXYNOS4_GPL0(3)
+
+#define GPIO_MHL_SDA_1_8V	EXYNOS4_GPF0(4)
+#define GPIO_MHL_SCL_1_8V	EXYNOS4_GPF0(6)
+#define GPIO_MHL_SDA_1_8V_00	EXYNOS4_GPB(2)
+#define GPIO_MHL_SCL_1_8V_00	EXYNOS4_GPB(3)
+
+#define GPIO_OTG_EN		EXYNOS4_GPF0(7)
+
+#define GPIO_OLED_ID		EXYNOS4_GPF1(0)
+#define GPIO_ISP_RESET		EXYNOS4_GPF1(3)
+#define GPIO_FUEL_SCL		EXYNOS4_GPF1(4)
+#define GPIO_FUEL_SDA		EXYNOS4_GPF1(5)
+
+#define GPIO_MLCD_RST		EXYNOS4_GPF2(1)
+#define GPIO_UART_SEL		EXYNOS4_GPF2(3)
+#define GPIO_S_LED_I2C_SCL	EXYNOS4_GPF2(6)
+#define GPIO_S_LED_I2C_SDA	EXYNOS4_GPF2(7)
+#define GPIO_OLED_DET		EXYNOS4_GPF3(0)
+
+#define GPIO_PMIC_DVS1		EXYNOS4212_GPM3(0)
+#define GPIO_PMIC_DVS2		EXYNOS4212_GPM3(1)
+
+/* Definitions for Sii 9244B0 */
+#define GPIO_PMIC_DVS3		EXYNOS4212_GPM3(2)
+#define GPIO_BUCK2_SEL		EXYNOS4_GPF3(1)
+#define GPIO_BUCK3_SEL		EXYNOS4_GPF3(2)
+#define GPIO_BUCK4_SEL		EXYNOS4_GPF3(3)
+#define GPIO_MHL_RST		EXYNOS4_GPF3(4)
+#define GPIO_MHL_INT		EXYNOS4_GPF3(5)
+#define GPIO_MHL_INT_AF		S3C_GPIO_SFN(0xF)
+#define GPIO_MHL_WAKE_UP	EXYNOS4212_GPJ1(4)
+
+#define GPIO_RGB_SDA_1_8V	EXYNOS4_GPF0(0)
+#define GPIO_RGB_SCL_1_8V	EXYNOS4_GPF0(1)
+#define GPIO_RGB_INT		EXYNOS4_GPX2(2)
+#define GPIO_VOL_UP		EXYNOS4212_GPJ1(1)
+#define GPIO_VOL_DOWN		EXYNOS4212_GPJ1(2)
+#define GPIO_VOL_UP_00		EXYNOS4_GPX2(2)
+#define GPIO_VOL_DOWN_00	EXYNOS4_GPX3(3)
+
+#define GPIO_CAM_SW_EN		EXYNOS4212_GPJ1(0)
+#define GPIO_TORCH_EN		EXYNOS4212_GPJ1(1)
+#define GPIO_TORCH_SET		EXYNOS4212_GPJ1(2)
+
+#define GPIO_MHL_DSCL_2_8V	EXYNOS4_GPK1(0)
+#define GPIO_MHL_DSDA_2_8V	EXYNOS4_GPK1(2)
+
+#define MHL_INT_IRQ		gpio_to_irq(GPIO_MHL_INT)
+#define MHL_WAKEUP_IRQ		gpio_to_irq(GPIO_MHL_WAKE_UP)
+
+#define GPIO_HDMI_CEC		EXYNOS4_GPX3(6)
+#define GPIO_HDMI_HPD		EXYNOS4_GPX3(7)
+
+#define GPIO_nPOWER		EXYNOS4_GPX2(7)
+#define GPIO_OK_KEY		EXYNOS4_GPX3(5)
+
+#define GPIO_FUEL_ALERT		EXYNOS4_GPX2(3)
+
+#define GPIO_V_BUS_INT		EXYNOS4_GPX2(4)	/* rev0.4 ~ */
+#define GPIO_WPC_INT		EXYNOS4_GPX3(0)
+
+#define GPIO_VIBTONE_PWM	EXYNOS4_GPD0(1)
+
+#define GPIO_CODEC_SDA_18V	EXYNOS4_GPD0(2)
+#define GPIO_CODEC_SCL_18V	EXYNOS4_GPD0(3)
+#define GPIO_CODEC_SDA_18V_00	EXYNOS4_GPB(0)
+#define GPIO_CODEC_SCL_18V_00	EXYNOS4_GPB(1)
+
+#define GPIO_CODEC_LDO_EN	EXYNOS4212_GPJ0(4)
+
+#define GPIO_WM8994_LDO		EXYNOS4212_GPJ0(4)
+
+/* Definitions for DPRAM */
+#define GPIO_DPRAM_CSN		EXYNOS4_GPY0(0)
+#define GPIO_DPRAM_CSN0		EXYNOS4_GPY0(0)
+#define GPIO_DPRAM_CSN1		EXYNOS4_GPY0(1)
+#define GPIO_DPRAM_CSN2		EXYNOS4_GPY0(2)
+#define GPIO_DPRAM_CSN3		EXYNOS4_GPY0(3)
+#define GPIO_DPRAM_REN		EXYNOS4_GPY0(4)
+#define GPIO_DPRAM_WEN		EXYNOS4_GPY0(5)
+#define GPIO_DPRAM_LBN		EXYNOS4_GPY1(0)
+#define GPIO_DPRAM_UBN		EXYNOS4_GPY1(1)
+#define GPIO_SROM_ADDR_BUS_LOW	EXYNOS4_GPY3(0)
+#define GPIO_SROM_ADDR_BUS_HIGH	EXYNOS4_GPY4(0)
+#define GPIO_SROM_DATA_BUS_LOW	EXYNOS4_GPY5(0)
+#define GPIO_SROM_DATA_BUS_HIGH	EXYNOS4_GPY6(0)
+
+/* Definitions for CMC221 */
+#define CP_CMC221_PMIC_PWRON	EXYNOS4_GPL2(5)
+#define CP_CMC221_CPU_RST	EXYNOS4_GPL2(4)
+
+#define GPIO_LTE_ACTIVE		EXYNOS4_GPX1(6)
+#define LTE_ACTIVE_IRQ		IRQ_EINT(14)	/* IRQ of GPX1[6] */
+
+#define GPIO_CMC_IDPRAM_INT_00	EXYNOS4_GPX2(0)
+#define CMC_IDPRAM_INT_IRQ_00	IRQ_EINT(16)	/* IRQ of GPX2[0] */
+
+#define GPIO_CMC_IDPRAM_STATUS	EXYNOS4_GPX0(5)
+#define GPIO_CMC_IDPRAM_WAKEUP	EXYNOS4_GPX3(2)
+
+#define GPIO_ACTIVE_STATE	EXYNOS4_GPF1(1)
+#define GPIO_IPC_SLAVE_WAKEUP	EXYNOS4_GPX1(0)
+#define GPIO_IPC_HOST_WAKEUP	EXYNOS4_GPX1(1)
+
+#define GPIO_AP2CMC_INT2	EXYNOS4_GPX1(2)
+
+/* Definitions for an USB HUB for CMC221 */
+#define GPIO_USB_HUB_RST	EXYNOS4_GPL0(0)
+#define GPIO_USB_HUB_SCL	EXYNOS4_GPL1(0)
+#define GPIO_USB_HUB_SDA	EXYNOS4_GPL1(1)
+#define GPIO_USB_HUB_INT	EXYNOS4_GPX2(1)
+
+#endif /* __MACH_GPIO_C1_H */
diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev00-c1ctc.h b/arch/arm/mach-exynos/include/mach/gpio-rev00-c1ctc.h
new file mode 100644
index 0000000..e7c17d0
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/gpio-rev00-c1ctc.h
@@ -0,0 +1,287 @@
+#ifndef __MACH_GPIO_C1_H
+#define __MACH_GPIO_C1_H __FILE__
+
+#include <mach/gpio.h>
+
+extern void midas_config_gpio_table(void);
+extern void midas_config_sleep_gpio_table(void);
+
+#define GPIO_eMMC_EN		EXYNOS4_GPK0(2)
+
+#define GPIO_BOOT_MODE		EXYNOS4_GPX0(3)
+
+
+#define GPIO_IF_PMIC_SDA	EXYNOS4212_GPM2(0)
+#define GPIO_IF_PMIC_SCL	EXYNOS4212_GPM2(1)
+#define GPIO_PMIC_SDA		EXYNOS4_GPB(2)
+#define GPIO_PMIC_SCL		EXYNOS4_GPB(3)
+
+#define GPIO_ADC_SCL		EXYNOS4_GPY0(2)
+#define GPIO_ADC_SDA		EXYNOS4_GPY0(3)
+#define GPIO_ADC_INT		EXYNOS4_GPX2(4)
+
+#define GPIO_CAM_SPI_SCLK	EXYNOS4_GPB(4)
+#define GPIO_CAM_SPI_SSN	EXYNOS4_GPB(5)
+#define GPIO_CAM_SPI_MISO	EXYNOS4_GPB(6)
+#define GPIO_CAM_SPI_MOSI	EXYNOS4_GPB(7)
+
+#define GPIO_CAM_MCLK		EXYNOS4212_GPJ1(3)
+#define GPIO_VTCAM_MCLK		EXYNOS4212_GPM2(2)
+
+#define GPIO_ISP_STANDBY	EXYNOS4212_GPM0(1)
+#define GPIO_CAM_IO_EN		EXYNOS4212_GPM0(2)
+#define GPIO_ISP_CORE_EN	EXYNOS4212_GPM0(3)
+#define GPIO_CAM_AF_EN		EXYNOS4212_GPM0(4)
+#define GPIO_CAM_VT_nRST	EXYNOS4212_GPM1(6)
+
+#define GPIO_8M_CAM_SCL_18V	EXYNOS4212_GPM4(0)
+#define GPIO_8M_CAM_SDA_18V	EXYNOS4212_GPM4(1)
+#define GPIO_8M_CAM_SCL_18V_00	EXYNOS4_GPD1(0)
+#define GPIO_8M_CAM_SDA_18V_00	EXYNOS4_GPD1(1)
+
+#define GPIO_VT_CAM_SCL_18V	EXYNOS4212_GPM4(2)
+#define GPIO_VT_CAM_SDA_18V	EXYNOS4212_GPM4(3)
+#define GPIO_VT_CAM_ID		EXYNOS4_GPF1(2)
+
+/* Sensors & NFC*/
+#define GPIO_PS_ALS_EN		EXYNOS4212_GPJ0(5)
+#define GPIO_PS_ALS_SDA_28V	EXYNOS4_GPK1(1)
+#define GPIO_PS_ALS_SCL_28V	EXYNOS4_GPK2(2)
+#define GPIO_PS_ALS_INT		EXYNOS4_GPX0(2)
+
+#define GPIO_ACC_INT		EXYNOS4_GPX0(0)
+
+#define GPIO_GYRO_DE		EXYNOS4_GPL2(0)
+#define GPIO_GPS_nRST		EXYNOS4_GPL2(1)
+#define GPIO_GPS_PWR_EN		EXYNOS4_GPL2(2)
+
+#define GPIO_GYRO_INT		EXYNOS4_GPF0(3)
+#define GPIO_GSENSE_SDA_18V	EXYNOS4_GPD1(2)
+#define GPIO_GSENSE_SCL_18V	EXYNOS4_GPD1(3)
+
+#define GPIO_MSENSOR_INT	EXYNOS4212_GPJ0(7)
+#define GPIO_MSENSOR_SDA_18V	EXYNOS4_GPY2(4)
+#define GPIO_MSENSOR_SCL_18V	EXYNOS4_GPY2(5)
+
+#define GPIO_BENSE_SCL_18V	EXYNOS4_GPY2(3)
+#define GPIO_BSENSE_SDA_18V	EXYNOS4_GPY2(2)
+#define GPIO_BARO_INT		EXYNOS4_GPF0(5)
+
+#define GPIO_TF_EN		EXYNOS4_GPY0(1)
+#define GPIO_NFC_SCL_18V	EXYNOS4_GPD1(1)
+#define GPIO_NFC_SDA_18V	EXYNOS4_GPD1(0)
+#define GPIO_NFC_SCL_18V_00	EXYNOS4_GPB(3)
+#define GPIO_NFC_SDA_18V_00	EXYNOS4_GPB(2)
+#define GPIO_NFC_IRQ		EXYNOS4_GPX1(7)
+#define GPIO_NFC_EN		EXYNOS4_GPL2(6)
+#define GPIO_NFC_FIRMWARE	EXYNOS4_GPL2(7)
+#define GPIO_NFC_CLK_REQ	EXYNOS4212_GPM0(0)
+/* Sensors & NFC*/
+
+#define GPIO_DET_35		EXYNOS4_GPX0(1)
+
+#define GPIO_MIC_BIAS_EN	EXYNOS4_GPF1(7)
+#define GPIO_SUB_MIC_BIAS_EN	EXYNOS4_GPF2(0)
+
+#define GPIO_PMU_RST		EXYNOS4_GPX3(2)
+
+#define GPIO_PMIC_IRQ		EXYNOS4_GPX0(7)
+#define GPIO_IF_PMIC_IRQ	EXYNOS4_GPX1(5)
+
+#define GPIO_TSP_INT		EXYNOS4212_GPM2(3)
+#define GPIO_TSP_SDA_18V	EXYNOS4_GPA1(2)
+#define GPIO_TSP_SCL_18V	EXYNOS4_GPA1(3)
+
+#define GPIO_BT_EN		EXYNOS4_GPL0(6)
+#define GPIO_BT_WAKE		EXYNOS4_GPX3(1)
+#define GPIO_BT_HOST_WAKE	EXYNOS4_GPX2(6)
+#define IRQ_BT_HOST_WAKE	IRQ_EINT(22)
+
+#define GPIO_BT_RXD		EXYNOS4_GPA0(0)
+#define GPIO_BT_RXD_AF		2
+
+#define GPIO_BT_TXD		EXYNOS4_GPA0(1)
+#define GPIO_BT_TXD_AF		2
+
+#define GPIO_BT_CTS		EXYNOS4_GPA0(2)
+#define GPIO_BT_CTS_AF		2
+
+#define GPIO_BT_RTS		EXYNOS4_GPA0(3)
+#define GPIO_BT_RTS_AF		2
+
+#define GPIO_GPS_RXD		EXYNOS4_GPA0(4)
+#define GPIO_GPS_RXD_AF		2
+
+#define GPIO_GPS_TXD		EXYNOS4_GPA0(5)
+#define GPIO_GPS_TXD_AF		2
+
+#define GPIO_GPS_CTS		EXYNOS4_GPA0(6)
+#define GPIO_GPS_CTS_AF		2
+
+#define GPIO_GPS_RTS		EXYNOS4_GPA0(7)
+#define GPIO_GPS_RTS_AF		2
+
+#define GPIO_FLM_RXD		EXYNOS4_GPA1(4)
+#define GPIO_FLM_RXD_AF		2
+
+#define GPIO_FLM_TXD		EXYNOS4_GPA1(5)
+#define GPIO_FLM_TXD_AF		2
+
+#define GPIO_3_TOUCH_SCL	EXYNOS4_GPL0(1)
+#define GPIO_3_TOUCH_SDA	EXYNOS4_GPL0(2)
+#define GPIO_HDMI_EN		EXYNOS4_GPL0(4)
+#define GPIO_3_TOUCH_INT	EXYNOS4212_GPJ1(0)
+#define GPIO_TOUCH_EN		EXYNOS4212_GPJ0(3)
+
+#define GPIO_PWM0		EXYNOS4_GPD0(0)
+#define GPIO_PWM1		EXYNOS4_GPD0(1)
+#define GPIO_PWM2		EXYNOS4_GPD0(2)
+#define GPIO_PWM3		EXYNOS4_GPD0(3)
+
+#define GPIO_VIBTONE_EN		EXYNOS4212_GPJ0(6)
+
+#define GPIO_WLAN_EN		EXYNOS4212_GPJ0(0)
+#define GPIO_WLAN_EN_AF		1
+#define GPIO_WLAN_HOST_WAKE	EXYNOS4_GPX2(5)
+#define GPIO_WLAN_HOST_WAKE_AF	0xF
+#define GPIO_WLAN_SDIO_CLK	EXYNOS4_GPK3(0)
+#define GPIO_WLAN_SDIO_CLK_AF	2
+#define GPIO_WLAN_SDIO_CMD	EXYNOS4_GPK3(1)
+#define GPIO_WLAN_SDIO_CMD_AF	2
+#define GPIO_WLAN_SDIO_D0	EXYNOS4_GPK3(3)
+#define GPIO_WLAN_SDIO_D0_AF	2
+#define GPIO_WLAN_SDIO_D1	EXYNOS4_GPK3(4)
+#define GPIO_WLAN_SDIO_D1_AF	2
+#define GPIO_WLAN_SDIO_D2	EXYNOS4_GPK3(5)
+#define GPIO_WLAN_SDIO_D2_AF	2
+#define GPIO_WLAN_SDIO_D3	EXYNOS4_GPK3(6)
+#define GPIO_WLAN_SDIO_D3_AF	2
+
+#define GPIO_USB_SEL		EXYNOS4212_GPJ0(1)
+
+#define GPIO_LCD_22V_EN		EXYNOS4212_GPM4(4)
+#define GPIO_LCD_22V_EN_00	EXYNOS4_GPC0(1)
+
+#define GPIO_ISP_TXD		EXYNOS4212_GPM4(5)
+#define GPIO_ISP_RXD		EXYNOS4212_GPM4(6)
+
+#define GPIO_TA_EN		EXYNOS4_GPL2(2)
+
+#define GPIO_MHL_SEL		EXYNOS4_GPL0(3)
+
+#define GPIO_MHL_SDA_1_8V	EXYNOS4_GPF0(4)
+#define GPIO_MHL_SCL_1_8V	EXYNOS4_GPF0(6)
+#define GPIO_MHL_SDA_1_8V_00	EXYNOS4_GPB(2)
+#define GPIO_MHL_SCL_1_8V_00	EXYNOS4_GPB(3)
+
+#define GPIO_OTG_EN		EXYNOS4_GPF0(7)
+
+#define GPIO_OLED_ID		EXYNOS4_GPF1(0)
+#define GPIO_ISP_RESET		EXYNOS4_GPF1(3)
+#define GPIO_FUEL_SCL		EXYNOS4_GPF1(4)
+#define GPIO_FUEL_SDA		EXYNOS4_GPF1(5)
+
+#define GPIO_MLCD_RST		EXYNOS4_GPF2(1)
+#define GPIO_UART_SEL		EXYNOS4_GPF2(3)
+#define GPIO_S_LED_I2C_SCL	EXYNOS4_GPF2(6)
+#define GPIO_S_LED_I2C_SDA	EXYNOS4_GPF2(7)
+#define GPIO_OLED_DET		EXYNOS4_GPF3(0)
+
+#define GPIO_PMIC_DVS1		EXYNOS4212_GPM3(0)
+#define GPIO_PMIC_DVS2		EXYNOS4212_GPM3(1)
+
+/* Definitions for Sii 9244B0 */
+#define GPIO_PMIC_DVS3		EXYNOS4212_GPM3(2)
+#define GPIO_BUCK2_SEL		EXYNOS4_GPF3(1)
+#define GPIO_BUCK3_SEL		EXYNOS4_GPF3(2)
+#define GPIO_BUCK4_SEL		EXYNOS4_GPF3(3)
+#define GPIO_MHL_RST		EXYNOS4_GPF3(4)
+#define GPIO_MHL_INT		EXYNOS4_GPF3(5)
+#define GPIO_MHL_INT_AF		S3C_GPIO_SFN(0xF)
+#define GPIO_MHL_WAKE_UP	EXYNOS4212_GPJ1(4)
+
+#define GPIO_RGB_SDA_1_8V	EXYNOS4_GPF0(0)
+#define GPIO_RGB_SCL_1_8V	EXYNOS4_GPF0(1)
+#define GPIO_RGB_INT		EXYNOS4_GPX2(2)
+#define GPIO_VOL_UP		EXYNOS4212_GPJ1(1)
+#define GPIO_VOL_DOWN		EXYNOS4212_GPJ1(2)
+#define GPIO_VOL_UP_00		EXYNOS4_GPX2(2)
+#define GPIO_VOL_DOWN_00	EXYNOS4_GPX3(3)
+
+#define GPIO_CAM_SW_EN		EXYNOS4212_GPJ1(0)
+#define GPIO_TORCH_EN		EXYNOS4212_GPJ1(1)
+#define GPIO_TORCH_SET		EXYNOS4212_GPJ1(2)
+
+#define GPIO_MHL_DSCL_2_8V	EXYNOS4_GPK1(0)
+#define GPIO_MHL_DSDA_2_8V	EXYNOS4_GPK1(2)
+
+#define MHL_INT_IRQ		gpio_to_irq(GPIO_MHL_INT)
+#define MHL_WAKEUP_IRQ		gpio_to_irq(GPIO_MHL_WAKE_UP)
+
+#define GPIO_HDMI_CEC		EXYNOS4_GPX3(6)
+#define GPIO_HDMI_HPD		EXYNOS4_GPX3(7)
+
+#define GPIO_nPOWER		EXYNOS4_GPX2(7)
+#define GPIO_OK_KEY		EXYNOS4_GPX3(5)
+
+#define GPIO_FUEL_ALERT		EXYNOS4_GPX2(3)
+
+#define GPIO_WPC_INT		EXYNOS4_GPX3(0)
+
+#define GPIO_VIBTONE_PWM	EXYNOS4_GPD0(1)
+
+#define GPIO_CODEC_SDA_18V	EXYNOS4_GPD0(2)
+#define GPIO_CODEC_SCL_18V	EXYNOS4_GPD0(3)
+#define GPIO_CODEC_SDA_18V_00	EXYNOS4_GPB(0)
+#define GPIO_CODEC_SCL_18V_00	EXYNOS4_GPB(1)
+
+#define GPIO_CODEC_LDO_EN	EXYNOS4212_GPJ0(4)
+
+#define GPIO_WM8994_LDO		EXYNOS4212_GPJ0(4)
+
+#define GPIO_FM_RST	EXYNOS4_GPC1(1)
+#define GPIO_FM_INT_REV07	EXYNOS4_GPX1(3)
+#define GPIO_FM_INT	EXYNOS4_GPX1(3)
+
+/* Definitions for DPRAM */
+#define GPIO_DPRAM_CSN		EXYNOS4_GPY0(0)
+#define GPIO_DPRAM_CSN0		EXYNOS4_GPY0(0)
+#define GPIO_DPRAM_CSN1		EXYNOS4_GPY0(1)
+#define GPIO_DPRAM_CSN2		EXYNOS4_GPY0(2)
+#define GPIO_DPRAM_CSN3		EXYNOS4_GPY0(3)
+#define GPIO_DPRAM_REN		EXYNOS4_GPY0(4)
+#define GPIO_DPRAM_WEN		EXYNOS4_GPY0(5)
+#define GPIO_DPRAM_LBN		EXYNOS4_GPY1(0)
+#define GPIO_DPRAM_UBN		EXYNOS4_GPY1(1)
+#define GPIO_DPRAM_BUSY		EXYNOS4_GPY1(2)
+
+/* Definitions for CMC221 */
+#define GPIO_ACTIVE_STATE	EXYNOS4_GPF1(1)
+#define GPIO_PDA_ACTIVE		EXYNOS4_GPF1(6)
+#define GPIO_AP_CP_INT		EXYNOS4_GPF2(2)
+
+#define GPIO_USB_HUB_RST	EXYNOS4_GPL0(0)
+#define GPIO_USB_HUB_SCL	EXYNOS4_GPL1(0)
+#define GPIO_USB_HUB_SDA	EXYNOS4_GPL1(1)
+#define GPIO_USB_HUB_INT	EXYNOS4_GPX2(1)
+#define GPIO_USB_HUB_CONNECT	EXYNOS4212_GPV3(5)
+#define GPIO_USB_BOOT_EN		EXYNOS4212_GPV3(7)
+
+#define GPIO_BOOT_SW_SEL		EXYNOS4212_GPV3(6)
+
+#define GPIO_IPC_SLAVE_WAKEUP	EXYNOS4_GPX1(0)
+#define GPIO_IPC_HOST_WAKEUP	EXYNOS4_GPX1(1)
+
+#define GPIO_CP_MSM_PWRON	EXYNOS4_GPL2(5)
+ #define GPIO_CP_MSM_RST	EXYNOS4_GPL2(4)
+#define GPIO_CP_MSM_PMU_RST	EXYNOS4_GPX3(2)
+#define GPIO_CP_MSM_DUMP	EXYNOS4_GPX1(2)
+
+#define GPIO_MSM_PHONE_ACTIVE		EXYNOS4_GPX1(6)
+#define MSM_PHONE_ACTIVE_IRQ		IRQ_EINT(14)	/* IRQ of GPX1[6] */
+
+#define GPIO_MSM_DPRAM_INT	EXYNOS4_GPX2(0)
+#define MSM_DPRAM_INT_IRQ	IRQ_EINT(16)	/* IRQ of GPX2[0] */
+
+
+#endif /* __MACH_GPIO_C1_H */
diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev00-c1vzw.h b/arch/arm/mach-exynos/include/mach/gpio-rev00-c1vzw.h
new file mode 100644
index 0000000..605b70c
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/gpio-rev00-c1vzw.h
@@ -0,0 +1,316 @@
+#ifndef __MACH_GPIO_C1VZW_H
+#define __MACH_GPIO_C1VZW_H __FILE__
+
+#include <mach/gpio.h>
+
+extern void midas_config_gpio_table(void);
+extern void midas_config_sleep_gpio_table(void);
+
+#define GPIO_eMMC_EN		EXYNOS4_GPK0(2)
+
+#define GPIO_BOOT_MODE		EXYNOS4_GPX0(3)
+
+#define GPIO_FM_I2S_CLK		EXYNOS4_GPC0(0)
+#define GPIO_FM_I2S_SYNC	EXYNOS4_GPC0(2)
+#define GPIO_FM_I2S_DI		EXYNOS4_GPC0(3)
+#define GPIO_FM_I2S_DO		EXYNOS4_GPC0(4)
+
+#ifdef CONFIG_AUDIENCE_ES305
+#define	GPIO_ES305_WAKEUP	EXYNOS4_GPC0(4)
+#define	GPIO_ES305_RESET	EXYNOS4_GPF2(5)
+#endif
+
+#define	GPIO_FM34_PWDN		EXYNOS4_GPL0(3)
+#define	GPIO_FM34_RESET		EXYNOS4_GPY1(3)
+#define	GPIO_FM34_BYPASS	EXYNOS4_GPY1(2)
+#define GPIO_FM34_SCL		EXYNOS4212_GPM4(0)
+#define GPIO_FM34_SDA		EXYNOS4212_GPM4(1)
+
+#define GPIO_IF_PMIC_SDA	EXYNOS4212_GPM2(0)
+#define GPIO_IF_PMIC_SCL	EXYNOS4212_GPM2(1)
+#define GPIO_PMIC_SDA		EXYNOS4_GPB(2)
+#define GPIO_PMIC_SCL		EXYNOS4_GPB(3)
+
+#define GPIO_ADC_SCL		EXYNOS4_GPY0(2)
+#define GPIO_ADC_SDA		EXYNOS4_GPY0(3)
+#define GPIO_ADC_INT		EXYNOS4_GPX2(4)
+
+#define GPIO_CAM_SPI_SCLK	EXYNOS4_GPB(4)
+#define GPIO_CAM_SPI_SSN	EXYNOS4_GPB(5)
+#define GPIO_CAM_SPI_MISO	EXYNOS4_GPB(6)
+#define GPIO_CAM_SPI_MOSI	EXYNOS4_GPB(7)
+
+#define GPIO_CAM_MCLK		EXYNOS4212_GPJ1(3)
+#define GPIO_VTCAM_MCLK		EXYNOS4212_GPM2(2)
+
+#define GPIO_ISP_STANDBY	EXYNOS4212_GPM0(1)
+#define GPIO_CAM_IO_EN		EXYNOS4212_GPM0(2)
+#define GPIO_ISP_CORE_EN	EXYNOS4212_GPM0(3)
+#define GPIO_CAM_AF_EN		EXYNOS4212_GPM0(4)
+#define GPIO_CAM_VT_nRST	EXYNOS4212_GPM1(6)
+
+#define GPIO_8M_CAM_SCL_18V	EXYNOS4212_GPM4(0)
+#define GPIO_8M_CAM_SDA_18V	EXYNOS4212_GPM4(1)
+#define GPIO_8M_CAM_SCL_18V_00	EXYNOS4_GPD1(0)
+#define GPIO_8M_CAM_SDA_18V_00	EXYNOS4_GPD1(1)
+
+#define GPIO_VT_CAM_SCL_18V	EXYNOS4212_GPM4(2)
+#define GPIO_VT_CAM_SDA_18V	EXYNOS4212_GPM4(3)
+#define GPIO_VT_CAM_ID		EXYNOS4_GPF1(2)
+
+/* Sensors & NFC*/
+#define GPIO_PS_ALS_EN		EXYNOS4212_GPJ0(5)
+#define GPIO_PS_ALS_SDA_28V	EXYNOS4_GPK1(1)
+#define GPIO_PS_ALS_SCL_28V	EXYNOS4_GPK2(2)
+#define GPIO_PS_ALS_INT		EXYNOS4_GPX0(2)
+
+#define GPIO_ACC_INT		EXYNOS4_GPX0(0)
+
+#define GPIO_GYRO_DE		EXYNOS4_GPL2(0)
+#define GPIO_GPS_nRST		EXYNOS4_GPL2(1)
+#define GPIO_GPS_PWR_EN		EXYNOS4_GPL2(2)
+
+#define GPIO_GYRO_INT		EXYNOS4_GPF0(3)
+#define GPIO_GSENSE_SDA_18V	EXYNOS4_GPD1(2)
+#define GPIO_GSENSE_SCL_18V	EXYNOS4_GPD1(3)
+
+#define GPIO_MSENSOR_INT	EXYNOS4212_GPJ0(7)
+#define GPIO_MSENSOR_SDA_18V	EXYNOS4_GPY2(4)
+#define GPIO_MSENSOR_SCL_18V	EXYNOS4_GPY2(5)
+
+#define GPIO_BENSE_SCL_18V	EXYNOS4_GPY2(3)
+#define GPIO_BSENSE_SDA_18V	EXYNOS4_GPY2(2)
+#define GPIO_BARO_INT		EXYNOS4_GPF0(5)
+
+#define GPIO_TF_EN		EXYNOS4_GPY0(1)
+#define GPIO_NFC_SCL_18V	EXYNOS4_GPD1(1)
+#define GPIO_NFC_SDA_18V	EXYNOS4_GPD1(0)
+#define GPIO_NFC_SCL_18V_00	EXYNOS4_GPB(3)
+#define GPIO_NFC_SDA_18V_00	EXYNOS4_GPB(2)
+#define GPIO_NFC_IRQ		EXYNOS4_GPX1(7)
+#define GPIO_NFC_EN		EXYNOS4_GPL2(6)
+#define GPIO_NFC_FIRMWARE	EXYNOS4_GPL2(7)
+#define GPIO_NFC_CLK_REQ	EXYNOS4212_GPM0(0)
+/* Sensors & NFC*/
+
+#define GPIO_DET_35		EXYNOS4_GPX0(1)
+
+#define GPIO_MIC_BIAS_EN	EXYNOS4_GPF1(7)
+#define GPIO_SUB_MIC_BIAS_EN	EXYNOS4_GPC0(3)
+#define GPIO_THIRD_MIC_BIAS_EN	EXYNOS4_GPF2(0)
+
+#define GPIO_PMU_RST		EXYNOS4_GPX3(2)
+
+#define GPIO_PMIC_IRQ		EXYNOS4_GPX0(7)
+#define GPIO_IF_PMIC_IRQ	EXYNOS4_GPX1(5)
+
+#define GPIO_TSP_INT		EXYNOS4212_GPM2(3)
+#define GPIO_TSP_SDA_18V	EXYNOS4_GPA1(2)
+#define GPIO_TSP_SCL_18V	EXYNOS4_GPA1(3)
+
+#define GPIO_BT_EN		EXYNOS4_GPL0(6)
+#define GPIO_BT_WAKE		EXYNOS4_GPX3(1)
+#define GPIO_BT_HOST_WAKE	EXYNOS4_GPX2(6)
+#define IRQ_BT_HOST_WAKE	IRQ_EINT(22)
+
+#define GPIO_BT_RXD		EXYNOS4_GPA0(0)
+#define GPIO_BT_RXD_AF		2
+
+#define GPIO_BT_TXD		EXYNOS4_GPA0(1)
+#define GPIO_BT_TXD_AF		2
+
+#define GPIO_BT_CTS		EXYNOS4_GPA0(2)
+#define GPIO_BT_CTS_AF		2
+
+#define GPIO_BT_RTS		EXYNOS4_GPA0(3)
+#define GPIO_BT_RTS_AF		2
+
+#define GPIO_GPS_RXD		EXYNOS4_GPA0(4)
+#define GPIO_GPS_RXD_AF		2
+
+#define GPIO_GPS_TXD		EXYNOS4_GPA0(5)
+#define GPIO_GPS_TXD_AF		2
+
+#define GPIO_GPS_CTS		EXYNOS4_GPA0(6)
+#define GPIO_GPS_CTS_AF		2
+
+#define GPIO_GPS_RTS		EXYNOS4_GPA0(7)
+#define GPIO_GPS_RTS_AF		2
+
+#define GPIO_FLM_RXD		EXYNOS4_GPA1(4)
+#define GPIO_FLM_RXD_AF		2
+
+#define GPIO_FLM_TXD		EXYNOS4_GPA1(5)
+#define GPIO_FLM_TXD_AF		2
+
+#define GPIO_3_TOUCH_SCL	EXYNOS4_GPL0(1)
+#define GPIO_3_TOUCH_SDA	EXYNOS4_GPL0(2)
+#define GPIO_HDMI_EN		EXYNOS4_GPL0(4)
+#define GPIO_3_TOUCH_INT	EXYNOS4212_GPJ0(3)
+#define GPIO_3_TOUCH_EN		EXYNOS4212_GPM0(0)
+
+#define GPIO_PWM0		EXYNOS4_GPD0(0)
+#define GPIO_PWM1		EXYNOS4_GPD0(1)
+#define GPIO_PWM2		EXYNOS4_GPD0(2)
+#define GPIO_PWM3		EXYNOS4_GPD0(3)
+
+#define GPIO_VIBTONE_EN		EXYNOS4212_GPJ0(6)
+
+#define GPIO_WLAN_EN		EXYNOS4212_GPJ0(0)
+#define GPIO_WLAN_EN_AF		1
+#define GPIO_WLAN_HOST_WAKE	EXYNOS4_GPX2(5)
+#define GPIO_WLAN_HOST_WAKE_AF	0xF
+#define GPIO_WLAN_SDIO_CLK	EXYNOS4_GPK3(0)
+#define GPIO_WLAN_SDIO_CLK_AF	2
+#define GPIO_WLAN_SDIO_CMD	EXYNOS4_GPK3(1)
+#define GPIO_WLAN_SDIO_CMD_AF	2
+#define GPIO_WLAN_SDIO_D0	EXYNOS4_GPK3(3)
+#define GPIO_WLAN_SDIO_D0_AF	2
+#define GPIO_WLAN_SDIO_D1	EXYNOS4_GPK3(4)
+#define GPIO_WLAN_SDIO_D1_AF	2
+#define GPIO_WLAN_SDIO_D2	EXYNOS4_GPK3(5)
+#define GPIO_WLAN_SDIO_D2_AF	2
+#define GPIO_WLAN_SDIO_D3	EXYNOS4_GPK3(6)
+#define GPIO_WLAN_SDIO_D3_AF	2
+
+#define GPIO_USB_SEL		EXYNOS4212_GPJ0(1)
+
+#define GPIO_LCD_22V_EN		EXYNOS4212_GPM4(4)
+#define GPIO_LCD_22V_EN_00	EXYNOS4_GPC0(1)
+
+#define GPIO_ISP_TXD		EXYNOS4212_GPM4(5)
+#define GPIO_ISP_RXD		EXYNOS4212_GPM4(6)
+
+#define GPIO_TA_EN		EXYNOS4_GPL2(2)
+
+#define GPIO_MHL_SEL		EXYNOS4_GPL0(3)
+
+#define GPIO_MHL_SDA_1_8V	EXYNOS4_GPF0(4)
+#define GPIO_MHL_SCL_1_8V	EXYNOS4_GPF0(6)
+#define GPIO_MHL_SDA_1_8V_00	EXYNOS4_GPB(2)
+#define GPIO_MHL_SCL_1_8V_00	EXYNOS4_GPB(3)
+
+#define GPIO_OTG_EN		EXYNOS4_GPF0(7)
+
+#define GPIO_OLED_ID		EXYNOS4_GPF1(0)
+#define GPIO_ISP_RESET		EXYNOS4_GPF1(3)
+#define GPIO_FUEL_SCL		EXYNOS4_GPF1(4)
+#define GPIO_FUEL_SDA		EXYNOS4_GPF1(5)
+
+#define GPIO_MLCD_RST		EXYNOS4_GPF2(1)
+#define GPIO_UART_SEL		EXYNOS4_GPF2(3)
+#define GPIO_LTE_VIA_UART_SEL	EXYNOS4212_GPJ0(6)
+#define GPIO_S_LED_I2C_SCL	EXYNOS4_GPF2(6)
+#define GPIO_S_LED_I2C_SDA	EXYNOS4_GPF2(7)
+#define GPIO_OLED_DET		EXYNOS4_GPF3(0)
+
+#define GPIO_PMIC_DVS1		EXYNOS4212_GPM3(0)
+#define GPIO_PMIC_DVS2		EXYNOS4212_GPM3(1)
+
+/* Definitions for Sii 9244B0 */
+#define GPIO_PMIC_DVS3		EXYNOS4212_GPM3(2)
+#define GPIO_BUCK2_SEL		EXYNOS4_GPF3(1)
+#define GPIO_BUCK3_SEL		EXYNOS4_GPF3(2)
+#define GPIO_BUCK4_SEL		EXYNOS4_GPF3(3)
+#define GPIO_MHL_RST		EXYNOS4_GPF3(4)
+#define GPIO_MHL_INT		EXYNOS4_GPF3(5)
+#define GPIO_MHL_INT_AF		S3C_GPIO_SFN(0xF)
+#define GPIO_MHL_WAKE_UP	EXYNOS4212_GPJ1(4)
+
+#define GPIO_RGB_SDA_1_8V	EXYNOS4_GPF0(0)
+#define GPIO_RGB_SCL_1_8V	EXYNOS4_GPF0(1)
+#define GPIO_RGB_INT		EXYNOS4_GPX2(2)
+#define GPIO_VOL_UP		EXYNOS4212_GPJ1(1)
+#define GPIO_VOL_DOWN		EXYNOS4212_GPJ1(2)
+#define GPIO_VOL_UP_00		EXYNOS4_GPX2(2)
+#define GPIO_VOL_DOWN_00	EXYNOS4_GPX3(3)
+
+#define GPIO_CAM_SW_EN		EXYNOS4212_GPJ1(0)
+#define GPIO_TORCH_EN		EXYNOS4212_GPJ1(1)
+#define GPIO_TORCH_SET		EXYNOS4212_GPJ1(2)
+
+#define GPIO_MHL_DSCL_2_8V	EXYNOS4_GPK1(0)
+#define GPIO_MHL_DSDA_2_8V	EXYNOS4_GPK1(2)
+
+#define MHL_INT_IRQ		gpio_to_irq(GPIO_MHL_INT)
+#define MHL_WAKEUP_IRQ		gpio_to_irq(GPIO_MHL_WAKE_UP)
+
+#define GPIO_HDMI_HPD		EXYNOS4_GPX3(7)
+
+#define GPIO_nPOWER		EXYNOS4_GPX2(7)
+#define GPIO_OK_KEY		EXYNOS4_GPX3(5)
+#define GPIO_OK_KEY_ANDROID	EXYNOS4_GPX0(1)
+
+#define GPIO_FUEL_ALERT		EXYNOS4_GPX2(3)
+
+#define GPIO_V_BUS_INT		EXYNOS4_GPX2(4)	/* rev0.9 ~ */
+#define GPIO_WPC_INT		EXYNOS4_GPX3(0)
+
+#define GPIO_VIBTONE_PWM	EXYNOS4_GPD0(1)
+
+#define GPIO_CODEC_SDA_18V	EXYNOS4_GPD0(2)
+#define GPIO_CODEC_SCL_18V	EXYNOS4_GPD0(3)
+#define GPIO_CODEC_SDA_18V_00	EXYNOS4_GPB(0)
+#define GPIO_CODEC_SCL_18V_00	EXYNOS4_GPB(1)
+
+#define GPIO_CODEC_LDO_EN	EXYNOS4212_GPJ0(4)
+
+#define GPIO_WM8994_LDO		EXYNOS4212_GPJ0(4)
+
+/* Definitions for DPRAM */
+#define GPIO_DPRAM_CSN		EXYNOS4_GPY0(0)
+#define GPIO_DPRAM_CSN0		EXYNOS4_GPY0(0)
+#define GPIO_DPRAM_CSN1		EXYNOS4_GPY0(1)
+#define GPIO_DPRAM_CSN2		EXYNOS4_GPY0(2)
+#define GPIO_DPRAM_CSN3		EXYNOS4_GPY0(3)
+#define GPIO_DPRAM_REN		EXYNOS4_GPY0(4)
+#define GPIO_DPRAM_WEN		EXYNOS4_GPY0(5)
+#define GPIO_DPRAM_LBN		EXYNOS4_GPY1(0)
+#define GPIO_DPRAM_UBN		EXYNOS4_GPY1(1)
+#define GPIO_SROM_ADDR_BUS_LOW	EXYNOS4_GPY3(0)
+#define GPIO_SROM_ADDR_BUS_HIGH	EXYNOS4_GPY4(0)
+#define GPIO_SROM_DATA_BUS_LOW	EXYNOS4_GPY5(0)
+#define GPIO_SROM_DATA_BUS_HIGH	EXYNOS4_GPY6(0)
+
+/* Definitions for CMC221 */
+#define CP_CMC221_PMIC_PWRON	EXYNOS4_GPL2(5)
+#define CP_CMC221_CPU_RST	EXYNOS4_GPL2(4)
+
+#define GPIO_LTE_ACTIVE		EXYNOS4_GPX1(6)
+#define LTE_ACTIVE_IRQ		IRQ_EINT(14)	/* IRQ of GPX1[6] */
+
+#define GPIO_CMC_IDPRAM_INT_00	EXYNOS4_GPX3(3)
+#define CMC_IDPRAM_INT_IRQ_00	IRQ_EINT(27)	/* IRQ of GPX3[3] */
+#define GPIO_CMC_IDPRAM_INT_01	EXYNOS4_GPX2(0)
+#define CMC_IDPRAM_INT_IRQ_01	IRQ_EINT(16)	/* IRQ of GPX2[0] */
+
+#define GPIO_CMC_IDPRAM_STATUS	EXYNOS4_GPX0(5)
+#define GPIO_CMC_IDPRAM_WAKEUP	EXYNOS4_GPX3(2)
+
+#define GPIO_ACTIVE_STATE	EXYNOS4_GPF1(1)
+#define GPIO_IPC_SLAVE_WAKEUP	EXYNOS4_GPX1(0)
+#define GPIO_IPC_HOST_WAKEUP	EXYNOS4_GPX1(1)
+
+/* Definitions for an USB HUB for CMC221 */
+#define GPIO_USB_HUB_RST	EXYNOS4_GPL0(0)
+#define GPIO_USB_HUB_SCL	EXYNOS4_GPL1(0)
+#define GPIO_USB_HUB_SDA	EXYNOS4_GPL1(1)
+#define GPIO_USB_HUB_INT	EXYNOS4_GPX2(1)
+
+/* Definitions for CBP7.2 */
+#define GPIO_CBP_PMIC_PWRON	EXYNOS4212_GPM0(6)
+#define GPIO_CBP_PS_HOLD_OFF	EXYNOS4212_GPM1(0)
+#define GPIO_CBP_CP_RST		EXYNOS4_GPF2(4)
+#define GPIO_PDA_ACTIVE		EXYNOS4_GPF1(6)
+
+#define GPIO_CBP_PHONE_ACTIVE	EXYNOS4_GPX1(3)
+#define CBP_PHONE_ACTIVE_IRQ	IRQ_EINT(11)
+
+#define GPIO_CBP_DPRAM_INT_00	EXYNOS4_GPX2(0)
+#define CBP_DPRAM_INT_IRQ_00	IRQ_EINT(16)	/* IRQ of GPX2[0] */
+#define GPIO_CBP_DPRAM_INT_01	EXYNOS4_GPX3(5)
+#define CBP_DPRAM_INT_IRQ_01	IRQ_EINT(29)	/* IRQ of GPX3[5] */
+
+#define GPIO_CBP_BOOT_SEL	EXYNOS4212_GPM0(5)
+
+#endif /* __MACH_GPIO_C1VZW_H */
diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev00-gc1.h b/arch/arm/mach-exynos/include/mach/gpio-rev00-gc1.h
new file mode 100644
index 0000000..04e3fb8
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/gpio-rev00-gc1.h
@@ -0,0 +1,321 @@
+#ifndef __MACH_GPIO_MIDAS_H
+#define __MACH_GPIO_MIDAS_H __FILE__
+
+#include <mach/gpio.h>
+
+extern void midas_config_gpio_table(void);
+extern void midas_config_sleep_gpio_table(void);
+
+extern int s3c_gpio_slp_cfgpin(unsigned int pin, unsigned int config);
+extern int s3c_gpio_slp_setpull_updown(unsigned int pin, unsigned int config);
+
+#define GPIO_eMMC_EN		EXYNOS4_GPK0(2)
+
+#define GPIO_BOOT_MODE		EXYNOS4_GPX0(3)
+
+#define GPIO_FM_I2S_CLK		EXYSNO4_GPC0(0)
+#define GPIO_FM_I2S_SYNC	EXYSNO4_GPC0(2)
+#define GPIO_FM_I2S_DI		EXYSNO4_GPC0(3)
+#define GPIO_FM_I2S_DO		EXYSNO4_GPC0(4)
+
+#define GPIO_IF_PMIC_SDA	EXYNOS4212_GPM2(0)
+#define GPIO_IF_PMIC_SCL	EXYNOS4212_GPM2(1)
+#define GPIO_PMIC_SDA		EXYNOS4_GPB(2)
+#define GPIO_PMIC_SCL		EXYNOS4_GPB(3)
+
+#define GPIO_ADC_SCL		EXYNOS4_GPY0(2)
+#define GPIO_ADC_SDA		EXYNOS4_GPY0(3)
+#define GPIO_ADC_INT		EXYNOS4_GPX2(4)	/* rev0.0, 0.1 */
+
+#define GPIO_CAM_SPI_SCLK	EXYNOS4_GPB(4)
+#define GPIO_CAM_SPI_SSN	EXYNOS4_GPB(5)
+#define GPIO_CAM_SPI_MISO	EXYNOS4_GPB(6)
+#define GPIO_CAM_SPI_MOSI	EXYNOS4_GPB(7)
+
+#define GPIO_CAM_MCLK		EXYNOS4212_GPJ1(3)
+#define GPIO_VTCAM_MCLK		EXYNOS4212_GPM2(2)
+
+#define GPIO_ISP_STANDBY	EXYNOS4212_GPM0(1)
+#define GPIO_CAM_IO_EN		EXYNOS4212_GPM0(2)
+#define GPIO_ISP_CORE_EN	EXYNOS4212_GPM0(3)
+#define GPIO_CAM_AF_EN		EXYNOS4212_GPM0(4)
+
+#define GPIO_MOT_EN		EXYNOS4212_GPM0(5)
+#define GPIO_SAMBAZ_RESET	EXYNOS4212_GPM0(6)
+
+#define GPIO_CAM_VT_nRST	EXYNOS4212_GPM1(6)
+
+#if 1
+#define GPIO_8M_CAM_SCL_18V	EXYNOS4_GPD1(0)
+#define GPIO_8M_CAM_SDA_18V	EXYNOS4_GPD1(1)
+#else
+#define GPIO_8M_CAM_SCL_18V	EXYNOS4212_GPM4(0)
+#define GPIO_8M_CAM_SDA_18V	EXYNOS4212_GPM4(1)
+#define GPIO_8M_CAM_SCL_18V_00	EXYNOS4_GPD1(0)
+#define GPIO_8M_CAM_SDA_18V_00	EXYNOS4_GPD1(1)
+#endif
+
+#define GPIO_VT_CAM_SCL_18V	EXYNOS4212_GPM4(2)
+#define GPIO_VT_CAM_SDA_18V	EXYNOS4212_GPM4(3)
+#define GPIO_VT_CAM_ID		EXYNOS4_GPF1(2)
+
+#define GPIO_GPS_nRST		EXYNOS4_GPL2(1)
+#define GPIO_GPS_PWR_EN		EXYNOS4_GPL2(2)
+
+#define GPIO_TOP_PCB_PWREN	EXYNOS4_GPL2(4)
+
+/* Sensors */
+#define GPIO_ACC_INT		EXYNOS4_GPX0(0)
+#define GPIO_GSENSE_SDA_18V	EXYNOS4_GPD1(2)
+#define GPIO_GSENSE_SCL_18V	EXYNOS4_GPD1(3)
+
+#define GPIO_MSENSOR_INT	EXYNOS4212_GPJ0(7)
+#define GPIO_MSENSOR_SDA_18V	EXYNOS4_GPY2(4)
+#define GPIO_MSENSOR_SCL_18V	EXYNOS4_GPY2(5)
+/* Sensors */
+
+#define GPIO_TF_EN		EXYNOS4_GPY2(0)
+
+#define GPIO_DET_35		EXYNOS4_GPX0(1)
+
+#define GPIO_MIC_BIAS_EN	EXYNOS4_GPF1(7)
+#define GPIO_SUB_MIC_BIAS_EN	EXYNOS4_GPF2(0)
+#define GPIO_THIRD_MIC_BIAS_EN	EXYNOS4212_GPJ0(2)
+
+#define GPIO_PMU_RST		EXYNOS4_GPX3(2)
+
+#define GPIO_PMIC_IRQ		EXYNOS4_GPX0(7)
+#define GPIO_IF_PMIC_IRQ	EXYNOS4_GPX1(5)
+
+#define GPIO_TSP_INT		EXYNOS4212_GPM2(3)
+#define GPIO_TSP_SDA_18V	EXYNOS4_GPA1(2)
+#define GPIO_TSP_SCL_18V	EXYNOS4_GPA1(3)
+
+#define GPIO_BT_EN		EXYNOS4_GPL0(6)
+#define GPIO_BT_WAKE		EXYNOS4_GPX3(1)
+#define GPIO_BT_HOST_WAKE	EXYNOS4_GPX2(6)
+#define IRQ_BT_HOST_WAKE	IRQ_EINT(22)
+
+#define GPIO_BT_RXD		EXYNOS4_GPA0(0)
+#define GPIO_BT_RXD_AF		2
+
+#define GPIO_BT_TXD		EXYNOS4_GPA0(1)
+#define GPIO_BT_TXD_AF		2
+
+#define GPIO_BT_CTS		EXYNOS4_GPA0(2)
+#define GPIO_BT_CTS_AF		2
+
+#define GPIO_BT_RTS		EXYNOS4_GPA0(3)
+#define GPIO_BT_RTS_AF		2
+
+#define GPIO_GPS_RXD		EXYNOS4_GPA0(4)
+#define GPIO_GPS_RXD_AF		2
+
+#define GPIO_GPS_TXD		EXYNOS4_GPA0(5)
+#define GPIO_GPS_TXD_AF		2
+
+#define GPIO_GPS_CTS		EXYNOS4_GPA0(6)
+#define GPIO_GPS_CTS_AF		2
+
+#define GPIO_GPS_RTS		EXYNOS4_GPA0(7)
+#define GPIO_GPS_RTS_AF		2
+
+#define GPIO_FLM_RXD		EXYNOS4_GPA1(4)
+#define GPIO_FLM_RXD_AF		2
+
+#define GPIO_FLM_TXD		EXYNOS4_GPA1(5)
+#define GPIO_FLM_TXD_AF		2
+
+#define GPIO_3_TOUCH_SCL	EXYNOS4_GPL0(1)
+#define GPIO_3_TOUCH_SDA	EXYNOS4_GPL0(2)
+#define GPIO_HDMI_EN		EXYNOS4_GPL0(4)
+#define GPIO_3_TOUCH_INT	EXYNOS4212_GPJ0(3)
+#define GPIO_3_TOUCH_EN		EXYNOS4212_GPM0(0)
+
+#define GPIO_PWM0		EXYNOS4_GPD0(0)
+#define GPIO_PWM1		EXYNOS4_GPD0(1)
+#define GPIO_PWM2		EXYNOS4_GPD0(2)
+#define GPIO_PWM3		EXYNOS4_GPD0(3)
+
+#define GPIO_VIBTONE_EN		EXYNOS4212_GPJ0(6)
+
+#define GPIO_WLAN_EN		EXYNOS4212_GPJ0(0)
+#define GPIO_WLAN_EN_AF		1
+#define GPIO_WLAN_HOST_WAKE	EXYNOS4_GPX2(5)
+#define GPIO_WLAN_HOST_WAKE_AF	0xF
+#define GPIO_WLAN_SDIO_CLK	EXYNOS4_GPK3(0)
+#define GPIO_WLAN_SDIO_CLK_AF	2
+#define GPIO_WLAN_SDIO_CMD	EXYNOS4_GPK3(1)
+#define GPIO_WLAN_SDIO_CMD_AF	2
+#define GPIO_WLAN_SDIO_D0	EXYNOS4_GPK3(3)
+#define GPIO_WLAN_SDIO_D0_AF	2
+#define GPIO_WLAN_SDIO_D1	EXYNOS4_GPK3(4)
+#define GPIO_WLAN_SDIO_D1_AF	2
+#define GPIO_WLAN_SDIO_D2	EXYNOS4_GPK3(5)
+#define GPIO_WLAN_SDIO_D2_AF	2
+#define GPIO_WLAN_SDIO_D3	EXYNOS4_GPK3(6)
+#define GPIO_WLAN_SDIO_D3_AF	2
+
+#define GPIO_USB_SEL		EXYNOS4212_GPJ0(1)
+
+#define GPIO_LCD_22V_EN		EXYNOS4212_GPM4(4)
+#define GPIO_LCD_22V_EN_00		EXYNOS4_GPC0(1)
+
+#define GPIO_ISP_TXD		EXYNOS4212_GPM4(5)
+#define GPIO_ISP_RXD		EXYNOS4212_GPM4(6)
+
+#define GPIO_TA_EN		EXYNOS4_GPL2(2)
+
+#define GPIO_MHL_SEL		EXYNOS4_GPL0(3)
+
+#define GPIO_MHL_SDA_1_8V	EXYNOS4_GPF0(4)
+#define GPIO_MHL_SCL_1_8V	EXYNOS4_GPF0(6)
+#define GPIO_MHL_SDA_1_8V_00	EXYNOS4_GPB(2)
+#define GPIO_MHL_SCL_1_8V_00	EXYNOS4_GPB(3)
+
+#define GPIO_OTG_EN		EXYNOS4_GPF0(7)
+
+#define GPIO_OLED_ID		EXYNOS4_GPF1(0)
+#define GPIO_ISP_RESET		EXYNOS4_GPF1(3)
+#define GPIO_FUEL_SCL		EXYNOS4_GPF1(4)
+#define GPIO_FUEL_SDA		EXYNOS4_GPF1(5)
+
+#define GPIO_MLCD_RST		EXYNOS4_GPF2(1)
+#define GPIO_UART_SEL		EXYNOS4_GPF2(3)
+#define GPIO_S_LED_I2C_SCL	EXYNOS4_GPF2(6)
+#define GPIO_S_LED_I2C_SDA	EXYNOS4_GPF2(7)
+#define GPIO_OLED_DET		EXYNOS4_GPF3(0)
+
+#define GPIO_PMIC_DVS1		EXYNOS4212_GPM3(0)
+#define GPIO_PMIC_DVS2		EXYNOS4212_GPM3(1)
+
+/* Definitions for Sii 9244B0 */
+#define GPIO_PMIC_DVS3		EXYNOS4212_GPM3(2)
+#define GPIO_BUCK2_SEL		EXYNOS4_GPF3(1)
+#define GPIO_BUCK3_SEL		EXYNOS4_GPF3(2)
+#define GPIO_BUCK4_SEL		EXYNOS4_GPF3(3)
+#define GPIO_MHL_RST		EXYNOS4_GPF3(4)
+#define GPIO_MHL_INT		EXYNOS4_GPF3(5)
+#define GPIO_MHL_INT_AF		S3C_GPIO_SFN(0xF)
+#define GPIO_MHL_WAKE_UP	EXYNOS4212_GPJ1(4)
+
+#define GPIO_RGB_SDA_1_8V	EXYNOS4_GPF0(0)
+#define GPIO_RGB_SCL_1_8V	EXYNOS4_GPF0(1)
+#define GPIO_RGB_INT		EXYNOS4_GPX2(2)
+#define GPIO_VOL_UP		EXYNOS4212_GPJ1(1)
+#define GPIO_VOL_DOWN		EXYNOS4212_GPJ1(2)
+#define GPIO_VOL_UP_00		EXYNOS4_GPX2(2)
+#define GPIO_VOL_DOWN_00	EXYNOS4_GPX3(3)
+
+#define GPIO_CAM_SW_EN		EXYNOS4212_GPJ1(0)
+#define GPIO_TORCH_EN		EXYNOS4212_GPJ1(1)
+#define GPIO_TORCH_SET		EXYNOS4212_GPJ1(2)
+
+#define GPIO_MHL_DSCL_2_8V	EXYNOS4_GPK1(0)
+#define GPIO_MHL_DSDA_2_8V	EXYNOS4_GPK1(2)
+
+#define MHL_INT_IRQ		gpio_to_irq(GPIO_MHL_INT)
+#define MHL_WAKEUP_IRQ		gpio_to_irq(GPIO_MHL_WAKE_UP)
+
+#define GPIO_HDMI_CEC		EXYNOS4_GPX3(6)
+#define GPIO_HDMI_HPD		EXYNOS4_GPX3(7)
+
+#define GPIO_nPOWER		EXYNOS4_GPX2(7)
+#define GPIO_OK_KEY		EXYNOS4_GPX3(5)
+
+#define GPIO_FUEL_ALERT		EXYNOS4_GPX2(3)
+
+#define GPIO_V_BUS_INT		EXYNOS4_GPX2(4)	/* rev0.9 ~ */
+#define GPIO_WPC_INT		EXYNOS4_GPX3(0)
+
+#define GPIO_VIBTONE_PWM	EXYNOS4_GPD0(1)
+
+#define GPIO_VIBTONE_PWM	EXYNOS4_GPD0(1)
+
+#define GPIO_CODEC_SDA_18V	EXYNOS4_GPD0(2)
+#define GPIO_CODEC_SCL_18V	EXYNOS4_GPD0(3)
+#define GPIO_CODEC_SDA_18V_00		EXYNOS4_GPB(0)
+#define GPIO_CODEC_SCL_18V_00		EXYNOS4_GPB(1)
+
+
+#define GPIO_CODEC_LDO_EN	EXYNOS4212_GPJ0(4)
+
+#define GPIO_WM8994_LDO		EXYNOS4212_GPJ0(4)
+
+#define GPIO_ISP_INT		EXYNOS4_GPX0(2)
+
+/* Modem Interface GPIOs - M0 HSIC */
+#if !defined(CONFIG_SEC_MODEM_M0_TD)
+#define GPIO_ACTIVE_STATE	EXYNOS4_GPF1(1)
+#define GPIO_PDA_ACTIVE		EXYNOS4_GPF1(6)
+#define GPIO_PHONE_ON		EXYNOS4_GPL2(5)
+#define GPIO_SUSPEND_REQUEST	EXYNOS4212_GPM2(4)
+#define GPIO_CP_REQ_RESET	EXYNOS4212_GPM3(3)
+#define GPIO_GPS_CNTL		EXYNOS4212_GPM3(4)
+#define GPIO_IPC_SLAVE_WAKEUP	EXYNOS4_GPX1(0)
+#define GPIO_IPC_HOST_WAKEUP	EXYNOS4_GPX1(1)
+#define GPIO_CP_DUMP_INT	EXYNOS4_GPX1(2)
+#define GPIO_PHONE_ACTIVE	EXYNOS4_GPX1(6)
+#define GPIO_CP_RST		EXYNOS4_GPX3(2)
+
+#define GPIO_FM_RST EXYNOS4_GPC1(1)
+#else
+
+/* Modem Interface GPIOs - M0 SPI */
+#define GPIO_PDA_ACTIVE	EXYNOS4_GPF1(6)
+#define GPIO_PHONE_ON	EXYNOS4_GPL2(5)
+#define GPIO_PHONE_ACTIVE	EXYNOS4_GPX1(6)
+#define GPIO_AP_CP_INT1	EXYNOS4_GPX0(5)
+#define GPIO_AP_CP_INT2	EXYNOS4_GPX3(5)
+#define GPIO_CP_DUMP_INT	EXYNOS4_GPX1(2)
+#define GPIO_IPC_MRDY	EXYNOS4_GPX0(4)
+#define GPIO_IPC_SRDY	EXYNOS4_GPX1(0)
+#define GPIO_IPC_SUB_MRDY	EXYNOS4_GPX3(2)
+#define GPIO_IPC_SUB_SRDY	EXYNOS4_GPX1(1)
+
+#define GPIO_CP_RST	EXYNOS4_GPF1(1)
+#define GPIO_CP_REQ_RESET	EXYNOS4_GPF1(1)
+#define GPIO_IPC_SLAVE_WAKEUP	EXYNOS4_GPX2(0)
+#define GPIO_IPC_HOST_WAKEUP	EXYNOS4_GPX2(0)
+#define GPIO_SUSPEND_REQUEST	EXYNOS4_GPF1(1)
+#define GPIO_ISP_INT		EXYNOS4_GPF1(1)
+#define GPIO_ACTIVE_STATE	EXYNOS4_GPF1(1)
+
+#define GPIO_FM_RST	EXYNOS4_GPC1(0)
+
+#define IRQ_IPC_SRDY		IRQ_EINT8
+#define IRQ_PHONE_ACTIVE	IRQ_EINT14
+#define IRQ_IPC_SRDY		IRQ_EINT8
+#define IRQ_IPC_SUB_SRDY	IRQ_EINT9
+#define IRQ_CP_DUMP_INT	IRQ_EINT10
+#endif
+
+#define GPIO_OK_KEY_ANDROID	EXYNOS4_GPX0(1)		/*system_rev == 11*/
+#define GPIO_OK_KEY_ANDROID_F EXYNOS4_GPX1(3)	/*system_rev >= 15*/
+
+#define GPIO_RECORD_KEY		EXYNOS4_GPX0(4)
+#define GPIO_MENU_KEY		EXYNOS4_GPX0(5)
+#define GPIO_BACK_KEY		EXYNOS4_GPX1(3)
+#define GPIO_PLAY_KEY		EXYNOS4_GPX1(4)
+#define GPIO_S1_KEY			EXYNOS4_GPX2(0)
+#define GPIO_S2_KEY			EXYNOS4_GPX2(1)
+#define GPIO_WIDE_KEY		EXYNOS4_GPX2(2)
+#define GPIO_TELE_KEY		EXYNOS4_GPX3(3)
+
+#define GPIO_FM_INT_REV15	EXYNOS4_GPX1(4)
+#define GPIO_FM_INT_REV07	EXYNOS4_GPX1(3)
+#define GPIO_FM_INT		EXYNOS4_GPX1(3)
+#define GPIO_FM_MIC_SW		EXYNOS4_GPL0(3)
+
+#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE)
+#define GPIO_TDMB_EN		EXYNOS4_GPL0(0)
+#define GPIO_TDMB_INT		EXYNOS4_GPF0(2)
+#define GPIO_TDMB_IRQ		gpio_to_irq(GPIO_TDMB_INT)
+#define GPIO_TDMB_INT_AF	0xf
+#define GPIO_TDMB_SPI_CLK	EXYNOS4_GPC1(1)
+#define GPIO_TDMB_SPI_CS	EXYNOS4_GPC1(2)
+#define GPIO_TDMB_SPI_MISO	EXYNOS4_GPC1(3)
+#define GPIO_TDMB_SPI_MOSI	EXYNOS4_GPC1(4)
+#endif
+
+#endif /* __MACH_GPIO_MIDAS_H */
diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev00-jenga.h b/arch/arm/mach-exynos/include/mach/gpio-rev00-jenga.h
new file mode 100644
index 0000000..42d1f08
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/gpio-rev00-jenga.h
@@ -0,0 +1,265 @@
+#ifndef __MACH_GPIO_MIDAS_H
+#define __MACH_GPIO_MIDAS_H __FILE__
+
+#include <mach/gpio.h>
+
+extern void midas_config_gpio_table(void);
+extern void midas_config_sleep_gpio_table(void);
+
+#define GPIO_eMMC_EN		EXYNOS4_GPK0(2)
+
+#define GPIO_BOOT_MODE		EXYNOS4_GPX0(3)
+
+#define GPIO_FM_I2S_CLK		EXYSNO4_GPC0(0)
+#define GPIO_FM_I2S_SYNC	EXYSNO4_GPC0(2)
+#define GPIO_FM_I2S_DI		EXYSNO4_GPC0(3)
+#define GPIO_FM_I2S_DO		EXYSNO4_GPC0(4)
+
+#define GPIO_IF_PMIC_SDA	EXYNOS4212_GPM2(0)
+#define GPIO_IF_PMIC_SCL	EXYNOS4212_GPM2(1)
+#define GPIO_PMIC_SDA		EXYNOS4_GPB(2)
+#define GPIO_PMIC_SCL		EXYNOS4_GPB(3)
+
+#define GPIO_ADC_SCL		EXYNOS4_GPY0(2)
+#define GPIO_ADC_SDA		EXYNOS4_GPY0(3)
+#define GPIO_ADC_INT		EXYNOS4_GPX2(4)
+
+#define GPIO_CAM_SPI_SCLK	EXYNOS4_GPB(4)
+#define GPIO_CAM_SPI_SSN	EXYNOS4_GPB(5)
+#define GPIO_CAM_SPI_MISO	EXYNOS4_GPB(6)
+#define GPIO_CAM_SPI_MOSI	EXYNOS4_GPB(7)
+
+#define GPIO_CAM_MCLK		EXYNOS4212_GPJ1(3)
+#define GPIO_VTCAM_MCLK		EXYNOS4212_GPM2(2)
+
+#define GPIO_ISP_STANDBY	EXYNOS4212_GPM0(1)
+#define GPIO_CAM_IO_EN		EXYNOS4212_GPM0(2)
+#define GPIO_ISP_CORE_EN	EXYNOS4212_GPM0(3)
+#define GPIO_CAM_AF_EN		EXYNOS4212_GPM0(4)
+#define GPIO_CAM_VT_nRST	EXYNOS4212_GPM1(6)
+
+#define GPIO_8M_CAM_SCL_18V	EXYNOS4212_GPM4(0)
+#define GPIO_8M_CAM_SDA_18V	EXYNOS4212_GPM4(1)
+#define GPIO_8M_CAM_SCL_18V_00	EXYNOS4_GPD1(0)
+#define GPIO_8M_CAM_SDA_18V_00	EXYNOS4_GPD1(1)
+
+#define GPIO_VT_CAM_SCL_18V	EXYNOS4212_GPM4(2)
+#define GPIO_VT_CAM_SDA_18V	EXYNOS4212_GPM4(3)
+#define GPIO_VT_CAM_ID			EXYNOS4_GPF1(2)
+
+/* Sensors & NFC*/
+#define GPIO_PS_ALS_EN		EXYNOS4212_GPJ0(5)
+#define GPIO_PS_ALS_SDA_28V	EXYNOS4_GPK1(1)
+#define GPIO_PS_ALS_SCL_28V	EXYNOS4_GPK2(2)
+#define GPIO_PS_ALS_INT		EXYNOS4_GPX0(2)
+
+#define GPIO_ACC_INT		EXYNOS4_GPX0(0)
+
+#define GPIO_GYRO_DE		EXYNOS4_GPL2(0)
+#define GPIO_GPS_nRST		EXYNOS4_GPL2(1)
+#define GPIO_GPS_PWR_EN		EXYNOS4_GPL2(2)
+
+#define GPIO_GYRO_INT		EXYNOS4_GPF0(3)
+#define GPIO_GSENSE_SDA_18V	EXYNOS4_GPD1(2)
+#define GPIO_GSENSE_SCL_18V	EXYNOS4_GPD1(3)
+
+#define GPIO_MSENSOR_INT	EXYNOS4212_GPJ0(7)
+#define GPIO_MSENSOR_SDA_18V	EXYNOS4_GPY2(4)
+#define GPIO_MSENSOR_SCL_18V	EXYNOS4_GPY2(5)
+
+#define GPIO_BENSE_SCL_18V	EXYNOS4_GPY2(3)
+#define GPIO_BSENSE_SDA_18V	EXYNOS4_GPY2(2)
+#define GPIO_BARO_INT		EXYNOS4_GPF0(5)
+
+#define GPIO_TF_EN		EXYNOS4_GPY0(1)
+#define GPIO_NFC_SCL_18V	EXYNOS4_GPZ(6)
+#define GPIO_NFC_SDA_18V	EXYNOS4_GPZ(5)
+#define GPIO_NFC_SCL_18V_00	EXYNOS4_GPB(3)
+#define GPIO_NFC_SDA_18V_00	EXYNOS4_GPB(2)
+#define GPIO_NFC_IRQ		EXYNOS4_GPX1(7)
+#define GPIO_NFC_EN		EXYNOS4_GPL2(6)
+#define GPIO_NFC_FIRMWARE	EXYNOS4_GPL2(7)
+#define GPIO_NFC_CLK_REQ	EXYNOS4212_GPM0(0)
+/* Sensors & NFC*/
+
+#define GPIO_DET_35		EXYNOS4_GPX0(1)
+
+#define GPIO_MIC_BIAS_EN	EXYNOS4212_GPM4(5)
+#define GPIO_MIC_BIAS_EN_00		EXYNOS4_GPF1(7)
+#define GPIO_SUB_MIC_BIAS_EN	EXYNOS4212_GPM4(6)
+#define GPIO_SUB_MIC_BIAS_EN_00	EXYNOS4_GPF2(0)
+#define GPIO_EAR_MIC_BIAS_EN	EXYNOS4212_GPM4(7)
+#define GPIO_EAR_MIC_BIAS_EN_00	EXYNOS4212_GPJ0(2)
+
+
+#define GPIO_PMU_RST		EXYNOS4_GPX3(2)
+
+#define GPIO_PMIC_IRQ		EXYNOS4_GPX0(7)
+#define GPIO_IF_PMIC_IRQ	EXYNOS4_GPX1(5)
+
+#define GPIO_TSP_INT		EXYNOS4212_GPM2(3)
+#define GPIO_TSP_SDA_18V	EXYNOS4_GPA1(2)
+#define GPIO_TSP_SCL_18V	EXYNOS4_GPA1(3)
+
+#define GPIO_BT_EN		EXYNOS4_GPL0(6)
+#define GPIO_BT_WAKE		EXYNOS4_GPX3(1)
+#define GPIO_BT_HOST_WAKE	EXYNOS4_GPX2(6)
+#define IRQ_BT_HOST_WAKE	IRQ_EINT(22)
+
+#define GPIO_BT_RXD		EXYNOS4_GPA0(0)
+#define GPIO_BT_RXD_AF		2
+
+#define GPIO_BT_TXD		EXYNOS4_GPA0(1)
+#define GPIO_BT_TXD_AF		2
+
+#define GPIO_BT_CTS		EXYNOS4_GPA0(2)
+#define GPIO_BT_CTS_AF		2
+
+#define GPIO_BT_RTS		EXYNOS4_GPA0(3)
+#define GPIO_BT_RTS_AF		2
+
+#define GPIO_GPS_RXD		EXYNOS4_GPA0(4)
+#define GPIO_GPS_RXD_AF		2
+
+#define GPIO_GPS_TXD		EXYNOS4_GPA0(5)
+#define GPIO_GPS_TXD_AF		2
+
+#define GPIO_GPS_CTS		EXYNOS4_GPA0(6)
+#define GPIO_GPS_CTS_AF		2
+
+#define GPIO_GPS_RTS		EXYNOS4_GPA0(7)
+#define GPIO_GPS_RTS_AF		2
+
+#define GPIO_FLM_RXD		EXYNOS4_GPA1(4)
+#define GPIO_FLM_RXD_AF		2
+
+#define GPIO_FLM_TXD		EXYNOS4_GPA1(5)
+#define GPIO_FLM_TXD_AF		2
+
+#define GPIO_3_TOUCH_SCL	EXYNOS4_GPL0(1)
+#define GPIO_3_TOUCH_SDA	EXYNOS4_GPL0(2)
+#define GPIO_HDMI_EN		EXYNOS4_GPL0(4)
+#define GPIO_3_TOUCH_INT	EXYNOS4212_GPJ1(0)
+#define GPIO_TOUCH_EN		EXYNOS4212_GPJ0(3)
+
+#define GPIO_PWM0		EXYNOS4_GPD0(0)
+#define GPIO_PWM1		EXYNOS4_GPD0(1)
+#define GPIO_PWM2		EXYNOS4_GPD0(2)
+#define GPIO_PWM3		EXYNOS4_GPD0(3)
+
+#define GPIO_VIBTONE_EN		EXYNOS4212_GPJ0(6)
+
+#define GPIO_WLAN_EN		EXYNOS4212_GPJ0(0)
+#define GPIO_WLAN_EN_AF		1
+#define GPIO_WLAN_HOST_WAKE	EXYNOS4_GPX2(5)
+#define GPIO_WLAN_HOST_WAKE_AF	0xF
+#define GPIO_WLAN_SDIO_CLK	EXYNOS4_GPK3(0)
+#define GPIO_WLAN_SDIO_CLK_AF	2
+#define GPIO_WLAN_SDIO_CMD	EXYNOS4_GPK3(1)
+#define GPIO_WLAN_SDIO_CMD_AF	2
+#define GPIO_WLAN_SDIO_D0	EXYNOS4_GPK3(3)
+#define GPIO_WLAN_SDIO_D0_AF	2
+#define GPIO_WLAN_SDIO_D1	EXYNOS4_GPK3(4)
+#define GPIO_WLAN_SDIO_D1_AF	2
+#define GPIO_WLAN_SDIO_D2	EXYNOS4_GPK3(5)
+#define GPIO_WLAN_SDIO_D2_AF	2
+#define GPIO_WLAN_SDIO_D3	EXYNOS4_GPK3(6)
+#define GPIO_WLAN_SDIO_D3_AF	2
+
+#define GPIO_USB_SEL		EXYNOS4212_GPJ0(1)
+
+#define GPIO_LCD_22V_EN		EXYNOS4212_GPM4(4)
+#define GPIO_LCD_22V_EN_00		EXYNOS4_GPC0(1)
+
+#define GPIO_ISP_TXD		EXYNOS4212_GPM4(5)
+#define GPIO_ISP_RXD		EXYNOS4212_GPM4(6)
+
+#define GPIO_TA_EN		EXYNOS4_GPL2(2)
+
+#define GPIO_MHL_SEL		EXYNOS4_GPL0(3)
+
+#define GPIO_MHL_SDA_1_8V	EXYNOS4_GPF0(4)
+#define GPIO_MHL_SCL_1_8V	EXYNOS4_GPF0(6)
+#define GPIO_MHL_SDA_1_8V_00	EXYNOS4_GPB(2)
+#define GPIO_MHL_SCL_1_8V_00	EXYNOS4_GPB(3)
+
+#define GPIO_OTG_EN		EXYNOS4_GPF0(7)
+
+#define GPIO_OLED_ID		EXYNOS4_GPF1(0)
+#define GPIO_ISP_RESET		EXYNOS4_GPF1(3)
+#define GPIO_FUEL_SCL		EXYNOS4_GPF1(4)
+#define GPIO_FUEL_SDA		EXYNOS4_GPF1(5)
+
+#define GPIO_MLCD_RST		EXYNOS4_GPF2(1)
+#define GPIO_UART_SEL		EXYNOS4_GPF2(3)
+#define GPIO_PMIC_DVS1		EXYNOS4212_GPM3(0)
+#define GPIO_PMIC_DVS2		EXYNOS4212_GPM3(1)
+
+/* Definitions for Sii 9244B0 */
+#define GPIO_PMIC_DVS3		EXYNOS4212_GPM3(2)
+#define GPIO_BUCK2_SEL		EXYNOS4_GPF3(1)
+#define GPIO_BUCK3_SEL		EXYNOS4_GPF3(2)
+#define GPIO_BUCK4_SEL		EXYNOS4_GPF3(3)
+#define GPIO_MHL_RST		EXYNOS4_GPF3(4)
+#define GPIO_MHL_INT		EXYNOS4_GPF3(5)
+#define GPIO_MHL_INT_AF		S3C_GPIO_SFN(0xF)
+#define GPIO_MHL_WAKE_UP	EXYNOS4212_GPJ1(4)
+
+#define GPIO_RGB_SDA_1_8V	EXYNOS4_GPF0(0)
+#define GPIO_RGB_SCL_1_8V	EXYNOS4_GPF0(1)
+#define GPIO_RGB_INT		EXYNOS4_GPX2(2)
+#define GPIO_VOL_UP		EXYNOS4212_GPJ1(1)
+#define GPIO_VOL_DOWN		EXYNOS4212_GPJ1(2)
+#define GPIO_VOL_UP_00		EXYNOS4_GPX2(2)
+#define GPIO_VOL_DOWN_00	EXYNOS4_GPX3(3)
+
+#define GPIO_CAM_SW_EN		EXYNOS4212_GPJ1(0)
+#define GPIO_TORCH_EN		EXYNOS4212_GPJ1(1)
+#define GPIO_TORCH_SET		EXYNOS4212_GPJ1(2)
+
+#define GPIO_MHL_DSCL_2_8V	EXYNOS4_GPK1(0)
+#define GPIO_MHL_DSDA_2_8V	EXYNOS4_GPK1(2)
+
+#define MHL_INT_IRQ		gpio_to_irq(GPIO_MHL_INT)
+#define MHL_WAKEUP_IRQ		gpio_to_irq(GPIO_MHL_WAKE_UP)
+
+#define GPIO_HDMI_CEC		EXYNOS4_GPX3(6)
+#define GPIO_HDMI_HPD		EXYNOS4_GPX3(7)
+
+#define GPIO_nPOWER		EXYNOS4_GPX2(7)
+#define GPIO_OK_KEY		EXYNOS4_GPX3(5)
+
+#define GPIO_FUEL_ALERT		EXYNOS4_GPX2(3)
+
+#define GPIO_VIBTONE_PWM	EXYNOS4_GPD0(1)
+
+#define GPIO_VIBTONE_PWM	EXYNOS4_GPD0(1)
+
+#define GPIO_CODEC_SDA_18V	EXYNOS4_GPD0(2)
+#define GPIO_CODEC_SCL_18V	EXYNOS4_GPD0(3)
+#define GPIO_CODEC_SDA_18V_00		EXYNOS4_GPB(0)
+#define GPIO_CODEC_SCL_18V_00		EXYNOS4_GPB(1)
+
+
+#define GPIO_CODEC_LDO_EN	EXYNOS4212_GPJ0(4)
+
+#define GPIO_WM8994_LDO		EXYNOS4212_GPJ0(4)
+
+/* Modem Interface GPIOs - M0 HSIC */
+#define GPIO_ACTIVE_STATE	EXYNOS4_GPF1(1)
+#define GPIO_PDA_ACTIVE		EXYNOS4_GPF1(6)
+#define GPIO_PHONE_ON		EXYNOS4_GPL2(5)
+#define GPIO_SUSPEND_REQUEST	EXYNOS4212_GPM2(4)
+#define GPIO_CP_REQ_RESET	EXYNOS4212_GPM3(3)
+#define GPIO_GPS_CNTL		EXYNOS4212_GPM3(4)
+#define GPIO_IPC_SLAVE_WAKEUP	EXYNOS4_GPX1(0)
+#define GPIO_IPC_HOST_WAKEUP	EXYNOS4_GPX1(1)
+#define GPIO_CP_DUMP_INT	EXYNOS4_GPX1(2)
+#define GPIO_PHONE_ACTIVE	EXYNOS4_GPX1(6)
+#define GPIO_CP_RST		EXYNOS4_GPX3(2)
+
+#define GPIO_FM_INT_REV07	EXYNOS4_GPX1(3)
+#define GPIO_FM_RST	EXYNOS4_GPC1(1)
+#define GPIO_FM_INT	EXYNOS4_GPX1(3)
+
+#endif /* __MACH_GPIO_MIDAS_H */
diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev00-m0.h b/arch/arm/mach-exynos/include/mach/gpio-rev00-m0.h
new file mode 100644
index 0000000..13fdb3d
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/gpio-rev00-m0.h
@@ -0,0 +1,322 @@
+#ifndef __MACH_GPIO_MIDAS_H
+#define __MACH_GPIO_MIDAS_H __FILE__
+
+#include <mach/gpio.h>
+
+extern void midas_config_gpio_table(void);
+extern void midas_config_sleep_gpio_table(void);
+
+#define GPIO_eMMC_EN		EXYNOS4_GPK0(2)
+
+#define GPIO_BOOT_MODE		EXYNOS4_GPX0(3)
+
+#define GPIO_FM_I2S_CLK		EXYSNO4_GPC0(0)
+#define GPIO_FM_I2S_SYNC	EXYSNO4_GPC0(2)
+#define GPIO_FM_I2S_DI		EXYSNO4_GPC0(3)
+#define GPIO_FM_I2S_DO		EXYSNO4_GPC0(4)
+
+#define GPIO_IF_PMIC_SDA	EXYNOS4212_GPM2(0)
+#define GPIO_IF_PMIC_SCL	EXYNOS4212_GPM2(1)
+#define GPIO_PMIC_SDA		EXYNOS4_GPB(2)
+#define GPIO_PMIC_SCL		EXYNOS4_GPB(3)
+
+#define GPIO_ADC_SCL		EXYNOS4_GPY0(2)
+#define GPIO_ADC_SDA		EXYNOS4_GPY0(3)
+#define GPIO_ADC_INT		EXYNOS4_GPX2(4)	/* rev0.0, 0.1 */
+
+#define GPIO_CAM_SPI_SCLK	EXYNOS4_GPB(4)
+#define GPIO_CAM_SPI_SSN	EXYNOS4_GPB(5)
+#define GPIO_CAM_SPI_MISO	EXYNOS4_GPB(6)
+#define GPIO_CAM_SPI_MOSI	EXYNOS4_GPB(7)
+
+#define GPIO_CAM_MCLK		EXYNOS4212_GPJ1(3)
+#define GPIO_VTCAM_MCLK		EXYNOS4212_GPM2(2)
+
+#define GPIO_ISP_STANDBY	EXYNOS4212_GPM0(1)
+#define GPIO_CAM_IO_EN		EXYNOS4212_GPM0(2)
+#define GPIO_ISP_CORE_EN	EXYNOS4212_GPM0(3)
+#define GPIO_CAM_AF_EN		EXYNOS4212_GPM0(4)
+#define GPIO_CAM_VT_nRST	EXYNOS4212_GPM1(6)
+
+#if 1
+#define GPIO_8M_CAM_SCL_18V	EXYNOS4_GPD1(0)
+#define GPIO_8M_CAM_SDA_18V	EXYNOS4_GPD1(1)
+#else
+#define GPIO_8M_CAM_SCL_18V	EXYNOS4212_GPM4(0)
+#define GPIO_8M_CAM_SDA_18V	EXYNOS4212_GPM4(1)
+#define GPIO_8M_CAM_SCL_18V_00	EXYNOS4_GPD1(0)
+#define GPIO_8M_CAM_SDA_18V_00	EXYNOS4_GPD1(1)
+#endif
+
+#define GPIO_VT_CAM_SCL_18V	EXYNOS4212_GPM4(2)
+#define GPIO_VT_CAM_SDA_18V	EXYNOS4212_GPM4(3)
+#define GPIO_VT_CAM_ID		EXYNOS4_GPF1(2)
+
+/* Sensors & NFC*/
+#define GPIO_PS_ALS_EN		EXYNOS4212_GPJ0(5)
+#define GPIO_PS_ALS_SDA_28V	EXYNOS4_GPK1(1)
+#define GPIO_PS_ALS_SCL_28V	EXYNOS4_GPK2(2)
+#define GPIO_PS_ALS_INT		EXYNOS4_GPX0(2)
+
+#define GPIO_ACC_INT		EXYNOS4_GPX0(0)
+
+#define GPIO_GYRO_DE		EXYNOS4_GPL2(0)
+#define GPIO_GPS_nRST		EXYNOS4_GPL2(1)
+#define GPIO_GPS_PWR_EN		EXYNOS4_GPL2(2)
+
+#define GPIO_GYRO_INT		EXYNOS4_GPF0(3)
+#define GPIO_GSENSE_SDA_18V	EXYNOS4_GPD1(2)
+#define GPIO_GSENSE_SCL_18V	EXYNOS4_GPD1(3)
+
+#define GPIO_MSENSOR_INT	EXYNOS4212_GPJ0(7)
+#define GPIO_MSENSOR_SDA_18V	EXYNOS4_GPY2(4)
+#define GPIO_MSENSOR_SCL_18V	EXYNOS4_GPY2(5)
+
+#define GPIO_BENSE_SCL_18V	EXYNOS4_GPY2(3)
+#define GPIO_BSENSE_SDA_18V	EXYNOS4_GPY2(2)
+#define GPIO_BARO_INT		EXYNOS4_GPF0(5)
+
+#define GPIO_TF_EN		EXYNOS4_GPY2(0)
+#define GPIO_NFC_SCL_18V	EXYNOS4_GPZ(6)
+#define GPIO_NFC_SDA_18V	EXYNOS4_GPZ(5)
+#define GPIO_NFC_SCL_18V_00	EXYNOS4_GPB(3)
+#define GPIO_NFC_SDA_18V_00	EXYNOS4_GPB(2)
+#define GPIO_NFC_IRQ		EXYNOS4_GPX1(7)
+#define GPIO_NFC_EN		EXYNOS4_GPL2(6)
+#define GPIO_NFC_FIRMWARE	EXYNOS4_GPL2(7)
+#define GPIO_NFC_CLK_REQ	EXYNOS4212_GPM0(0)
+/* Sensors & NFC*/
+
+#define GPIO_DET_35		EXYNOS4_GPX0(1)
+
+#define GPIO_MIC_BIAS_EN	EXYNOS4_GPF1(7)
+#define GPIO_SUB_MIC_BIAS_EN	EXYNOS4_GPF2(0)
+#define GPIO_THIRD_MIC_BIAS_EN	EXYNOS4212_GPJ0(2)
+
+#define GPIO_PMU_RST		EXYNOS4_GPX3(2)
+
+#define GPIO_PMIC_IRQ		EXYNOS4_GPX0(7)
+#define GPIO_IF_PMIC_IRQ	EXYNOS4_GPX1(5)
+
+#define GPIO_TSP_INT		EXYNOS4212_GPM2(3)
+#define GPIO_TSP_SDA_18V	EXYNOS4_GPA1(2)
+#define GPIO_TSP_SCL_18V	EXYNOS4_GPA1(3)
+
+#define GPIO_BT_EN		EXYNOS4_GPL0(6)
+#define GPIO_BT_WAKE		EXYNOS4_GPX3(1)
+#define GPIO_BT_HOST_WAKE	EXYNOS4_GPX2(6)
+#define IRQ_BT_HOST_WAKE	IRQ_EINT(22)
+
+#define GPIO_BT_RXD		EXYNOS4_GPA0(0)
+#define GPIO_BT_RXD_AF		2
+
+#define GPIO_BT_TXD		EXYNOS4_GPA0(1)
+#define GPIO_BT_TXD_AF		2
+
+#define GPIO_BT_CTS		EXYNOS4_GPA0(2)
+#define GPIO_BT_CTS_AF		2
+
+#define GPIO_BT_RTS		EXYNOS4_GPA0(3)
+#define GPIO_BT_RTS_AF		2
+
+#define GPIO_GPS_RXD		EXYNOS4_GPA0(4)
+#define GPIO_GPS_RXD_AF		2
+
+#define GPIO_GPS_TXD		EXYNOS4_GPA0(5)
+#define GPIO_GPS_TXD_AF		2
+
+#define GPIO_GPS_CTS		EXYNOS4_GPA0(6)
+#define GPIO_GPS_CTS_AF		2
+
+#define GPIO_GPS_RTS		EXYNOS4_GPA0(7)
+#define GPIO_GPS_RTS_AF		2
+
+#define GPIO_FLM_RXD		EXYNOS4_GPA1(4)
+#define GPIO_FLM_RXD_AF		2
+
+#define GPIO_FLM_TXD		EXYNOS4_GPA1(5)
+#define GPIO_FLM_TXD_AF		2
+
+#define GPIO_3_TOUCH_SCL	EXYNOS4_GPL0(1)
+#define GPIO_3_TOUCH_SDA	EXYNOS4_GPL0(2)
+#define GPIO_HDMI_EN		EXYNOS4_GPL0(4)
+#define GPIO_3_TOUCH_INT	EXYNOS4212_GPJ0(3)
+#define GPIO_3_TOUCH_EN		EXYNOS4212_GPM0(0)
+
+#define GPIO_PWM0		EXYNOS4_GPD0(0)
+#define GPIO_PWM1		EXYNOS4_GPD0(1)
+#define GPIO_PWM2		EXYNOS4_GPD0(2)
+#define GPIO_PWM3		EXYNOS4_GPD0(3)
+
+#define GPIO_VIBTONE_EN		EXYNOS4212_GPJ0(6)
+
+#define GPIO_WLAN_EN		EXYNOS4212_GPJ0(0)
+#define GPIO_WLAN_EN_AF		1
+#define GPIO_WLAN_HOST_WAKE	EXYNOS4_GPX2(5)
+#define GPIO_WLAN_HOST_WAKE_AF	0xF
+#define GPIO_WLAN_SDIO_CLK	EXYNOS4_GPK3(0)
+#define GPIO_WLAN_SDIO_CLK_AF	2
+#define GPIO_WLAN_SDIO_CMD	EXYNOS4_GPK3(1)
+#define GPIO_WLAN_SDIO_CMD_AF	2
+#define GPIO_WLAN_SDIO_D0	EXYNOS4_GPK3(3)
+#define GPIO_WLAN_SDIO_D0_AF	2
+#define GPIO_WLAN_SDIO_D1	EXYNOS4_GPK3(4)
+#define GPIO_WLAN_SDIO_D1_AF	2
+#define GPIO_WLAN_SDIO_D2	EXYNOS4_GPK3(5)
+#define GPIO_WLAN_SDIO_D2_AF	2
+#define GPIO_WLAN_SDIO_D3	EXYNOS4_GPK3(6)
+#define GPIO_WLAN_SDIO_D3_AF	2
+
+#define GPIO_USB_SEL		EXYNOS4212_GPJ0(1)
+
+#define GPIO_LCD_22V_EN		EXYNOS4212_GPM4(4)
+#define GPIO_LCD_22V_EN_00		EXYNOS4_GPC0(1)
+
+#define GPIO_ISP_TXD		EXYNOS4212_GPM4(5)
+#define GPIO_ISP_RXD		EXYNOS4212_GPM4(6)
+
+#define GPIO_TA_EN		EXYNOS4_GPL2(2)
+
+#define GPIO_MHL_SEL		EXYNOS4_GPL0(3)
+
+#define GPIO_MHL_SDA_1_8V	EXYNOS4_GPF0(4)
+#define GPIO_MHL_SCL_1_8V	EXYNOS4_GPF0(6)
+#define GPIO_MHL_SDA_1_8V_00	EXYNOS4_GPB(2)
+#define GPIO_MHL_SCL_1_8V_00	EXYNOS4_GPB(3)
+
+#define GPIO_OTG_EN		EXYNOS4_GPF0(7)
+
+#define GPIO_OLED_ID		EXYNOS4_GPF1(0)
+#define GPIO_ISP_RESET		EXYNOS4_GPF1(3)
+#define GPIO_FUEL_SCL		EXYNOS4_GPF1(4)
+#define GPIO_FUEL_SDA		EXYNOS4_GPF1(5)
+
+#define GPIO_MLCD_RST		EXYNOS4_GPF2(1)
+#define GPIO_UART_SEL		EXYNOS4_GPF2(3)
+#define GPIO_S_LED_I2C_SCL	EXYNOS4_GPF2(6)
+#define GPIO_S_LED_I2C_SDA	EXYNOS4_GPF2(7)
+#define GPIO_OLED_DET		EXYNOS4_GPF3(0)
+
+#define GPIO_PMIC_DVS1		EXYNOS4212_GPM3(0)
+#define GPIO_PMIC_DVS2		EXYNOS4212_GPM3(1)
+
+/* Definitions for Sii 9244B0 */
+#define GPIO_PMIC_DVS3		EXYNOS4212_GPM3(2)
+#define GPIO_BUCK2_SEL		EXYNOS4_GPF3(1)
+#define GPIO_BUCK3_SEL		EXYNOS4_GPF3(2)
+#define GPIO_BUCK4_SEL		EXYNOS4_GPF3(3)
+#define GPIO_MHL_RST		EXYNOS4_GPF3(4)
+#define GPIO_MHL_INT		EXYNOS4_GPF3(5)
+#define GPIO_MHL_INT_AF		S3C_GPIO_SFN(0xF)
+#define GPIO_MHL_WAKE_UP	EXYNOS4212_GPJ1(4)
+
+#define GPIO_RGB_SDA_1_8V	EXYNOS4_GPF0(0)
+#define GPIO_RGB_SCL_1_8V	EXYNOS4_GPF0(1)
+#define GPIO_RGB_INT		EXYNOS4_GPX2(2)
+#define GPIO_VOL_UP		EXYNOS4212_GPJ1(1)
+#define GPIO_VOL_DOWN		EXYNOS4212_GPJ1(2)
+#define GPIO_VOL_UP_00		EXYNOS4_GPX2(2)
+#define GPIO_VOL_DOWN_00	EXYNOS4_GPX3(3)
+
+#define GPIO_CAM_SW_EN		EXYNOS4212_GPJ1(0)
+#define GPIO_TORCH_EN		EXYNOS4212_GPJ1(1)
+#define GPIO_TORCH_SET		EXYNOS4212_GPJ1(2)
+
+#define GPIO_MHL_DSCL_2_8V	EXYNOS4_GPK1(0)
+#define GPIO_MHL_DSDA_2_8V	EXYNOS4_GPK1(2)
+
+#define MHL_INT_IRQ		gpio_to_irq(GPIO_MHL_INT)
+#define MHL_WAKEUP_IRQ		gpio_to_irq(GPIO_MHL_WAKE_UP)
+
+#define GPIO_HDMI_CEC		EXYNOS4_GPX3(6)
+#define GPIO_HDMI_HPD		EXYNOS4_GPX3(7)
+
+#define GPIO_nPOWER		EXYNOS4_GPX2(7)
+#define GPIO_OK_KEY		EXYNOS4_GPX3(5)
+
+#define GPIO_FUEL_ALERT		EXYNOS4_GPX2(3)
+
+#define GPIO_V_BUS_INT		EXYNOS4_GPX2(4)	/* rev0.9 ~ */
+#define GPIO_WPC_INT		EXYNOS4_GPX3(0)
+
+#define GPIO_VIBTONE_PWM	EXYNOS4_GPD0(1)
+
+#define GPIO_VIBTONE_PWM	EXYNOS4_GPD0(1)
+
+#define GPIO_CODEC_SDA_18V	EXYNOS4_GPD0(2)
+#define GPIO_CODEC_SCL_18V	EXYNOS4_GPD0(3)
+#define GPIO_CODEC_SDA_18V_00		EXYNOS4_GPB(0)
+#define GPIO_CODEC_SCL_18V_00		EXYNOS4_GPB(1)
+
+
+#define GPIO_CODEC_LDO_EN	EXYNOS4212_GPJ0(4)
+
+#define GPIO_WM8994_LDO		EXYNOS4212_GPJ0(4)
+
+/* Modem Interface GPIOs - M0 HSIC */
+#if !defined(CONFIG_SEC_MODEM_M0_TD)
+#define GPIO_ACTIVE_STATE	EXYNOS4_GPF1(1)
+#define GPIO_PDA_ACTIVE		EXYNOS4_GPF1(6)
+#define GPIO_PHONE_ON		EXYNOS4_GPL2(5)
+#define GPIO_SUSPEND_REQUEST	EXYNOS4212_GPM2(4)
+#define GPIO_CP_REQ_RESET	EXYNOS4212_GPM3(3)
+#define GPIO_GPS_CNTL		EXYNOS4212_GPM3(4)
+#define GPIO_IPC_SLAVE_WAKEUP	EXYNOS4_GPX1(0)
+#define GPIO_IPC_HOST_WAKEUP	EXYNOS4_GPX1(1)
+#define GPIO_CP_DUMP_INT	EXYNOS4_GPX1(2)
+#define GPIO_PHONE_ACTIVE	EXYNOS4_GPX1(6)
+#define GPIO_CP_RST		EXYNOS4_GPX3(2)
+#define GPIO_AP_DUMP_INT	EXYNOS4212_GPJ0(1)
+
+#define GPIO_FM_RST EXYNOS4_GPC1(1)
+#else
+
+/* Modem Interface GPIOs - M0 SPI */
+#define GPIO_PDA_ACTIVE	EXYNOS4_GPF1(6)
+#define GPIO_PHONE_ON	EXYNOS4_GPL2(5)
+#define GPIO_PHONE_ACTIVE	EXYNOS4_GPX1(6)
+#define GPIO_AP_CP_INT1	EXYNOS4_GPX0(5)
+#define GPIO_AP_CP_INT2	EXYNOS4_GPX3(5)
+#define GPIO_CP_DUMP_INT	EXYNOS4_GPX1(2)
+#define GPIO_IPC_MRDY	EXYNOS4_GPX0(4)
+#define GPIO_IPC_SRDY	EXYNOS4_GPX1(0)
+#define GPIO_IPC_SUB_MRDY	EXYNOS4_GPX3(2)
+#define GPIO_IPC_SUB_SRDY	EXYNOS4_GPX1(1)
+
+#define GPIO_CP_RST	EXYNOS4_GPF1(1)
+#define GPIO_CP_REQ_RESET	EXYNOS4_GPF1(1)
+#define GPIO_IPC_SLAVE_WAKEUP	EXYNOS4_GPX2(0)
+#define GPIO_IPC_HOST_WAKEUP	EXYNOS4_GPX2(0)
+#define GPIO_SUSPEND_REQUEST	EXYNOS4_GPF1(1)
+#define GPIO_ISP_INT		EXYNOS4_GPF1(1)
+#define GPIO_ACTIVE_STATE	EXYNOS4_GPF1(1)
+
+#define GPIO_FM_RST	EXYNOS4_GPC1(0)
+
+#define IRQ_IPC_SRDY		IRQ_EINT8
+#define IRQ_PHONE_ACTIVE	IRQ_EINT14
+#define IRQ_IPC_SRDY		IRQ_EINT8
+#define IRQ_IPC_SUB_SRDY	IRQ_EINT9
+#define IRQ_CP_DUMP_INT	IRQ_EINT10
+#endif
+
+#define GPIO_OK_KEY_ANDROID	EXYNOS4_GPX0(1)		/*system_rev == 11*/
+#define GPIO_OK_KEY_ANDROID_F EXYNOS4_GPX1(3)	/*system_rev >= 15*/
+
+#define GPIO_FM_INT_REV15	EXYNOS4_GPX1(4)
+#define GPIO_FM_INT_REV07	EXYNOS4_GPX1(3)
+#define GPIO_FM_INT		EXYNOS4_GPX1(3)
+#define GPIO_FM_MIC_SW		EXYNOS4_GPL0(3)
+
+#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE)
+#define GPIO_TDMB_EN		EXYNOS4_GPL0(0)
+#define GPIO_TDMB_INT		EXYNOS4_GPF0(2)
+#define GPIO_TDMB_IRQ		gpio_to_irq(GPIO_TDMB_INT)
+#define GPIO_TDMB_INT_AF	0xf
+#define GPIO_TDMB_SPI_CLK	EXYNOS4_GPC1(1)
+#define GPIO_TDMB_SPI_CS	EXYNOS4_GPC1(2)
+#define GPIO_TDMB_SPI_MISO	EXYNOS4_GPC1(3)
+#define GPIO_TDMB_SPI_MOSI	EXYNOS4_GPC1(4)
+#endif
+
+#endif /* __MACH_GPIO_MIDAS_H */
diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev00-m0ctc.h b/arch/arm/mach-exynos/include/mach/gpio-rev00-m0ctc.h
new file mode 100644
index 0000000..2b36a60
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/gpio-rev00-m0ctc.h
@@ -0,0 +1,296 @@
+#ifndef __MACH_GPIO_C1_H
+#define __MACH_GPIO_C1_H __FILE__
+
+#include <mach/gpio.h>
+
+extern void midas_config_gpio_table(void);
+extern void midas_config_sleep_gpio_table(void);
+
+#define GPIO_eMMC_EN		EXYNOS4_GPK0(2)
+
+#define GPIO_BOOT_MODE		EXYNOS4_GPX0(3)
+
+
+#define GPIO_IF_PMIC_SDA	EXYNOS4212_GPM2(0)
+#define GPIO_IF_PMIC_SCL	EXYNOS4212_GPM2(1)
+#define GPIO_PMIC_SDA		EXYNOS4_GPB(2)
+#define GPIO_PMIC_SCL		EXYNOS4_GPB(3)
+
+#define GPIO_ADC_SCL		EXYNOS4_GPY0(2)
+#define GPIO_ADC_SDA		EXYNOS4_GPY0(3)
+#define GPIO_ADC_INT		EXYNOS4_GPX2(4)
+
+#define GPIO_CAM_SPI_SCLK	EXYNOS4_GPB(4)
+#define GPIO_CAM_SPI_SSN	EXYNOS4_GPB(5)
+#define GPIO_CAM_SPI_MISO	EXYNOS4_GPB(6)
+#define GPIO_CAM_SPI_MOSI	EXYNOS4_GPB(7)
+
+#define GPIO_CAM_MCLK		EXYNOS4212_GPJ1(3)
+#define GPIO_VTCAM_MCLK		EXYNOS4212_GPM2(2)
+
+#define GPIO_ISP_STANDBY	EXYNOS4212_GPM0(1)
+#define GPIO_CAM_IO_EN		EXYNOS4212_GPM0(2)
+#define GPIO_ISP_CORE_EN	EXYNOS4212_GPM0(3)
+#define GPIO_CAM_AF_EN		EXYNOS4212_GPM0(4)
+#define GPIO_CAM_VT_nRST	EXYNOS4212_GPM1(6)
+
+#define GPIO_8M_CAM_SCL_18V	EXYNOS4212_GPM4(0)
+#define GPIO_8M_CAM_SDA_18V	EXYNOS4212_GPM4(1)
+#define GPIO_8M_CAM_SCL_18V_00	EXYNOS4_GPD1(0)
+#define GPIO_8M_CAM_SDA_18V_00	EXYNOS4_GPD1(1)
+
+#define GPIO_VT_CAM_SCL_18V	EXYNOS4212_GPM4(2)
+#define GPIO_VT_CAM_SDA_18V	EXYNOS4212_GPM4(3)
+#define GPIO_VT_CAM_ID		EXYNOS4_GPF1(2)
+
+/* Sensors & NFC*/
+#define GPIO_PS_ALS_EN		EXYNOS4212_GPJ0(5)
+#define GPIO_PS_ALS_SDA_28V	EXYNOS4_GPK1(1)
+#define GPIO_PS_ALS_SCL_28V	EXYNOS4_GPK2(2)
+#define GPIO_PS_ALS_INT		EXYNOS4_GPX0(2)
+
+#define GPIO_ACC_INT		EXYNOS4_GPX0(0)
+
+#define GPIO_GYRO_DE		EXYNOS4_GPL2(0)
+#define GPIO_GPS_nRST		EXYNOS4_GPL2(1)
+#define GPIO_GPS_PWR_EN		EXYNOS4_GPL2(2)
+
+#define GPIO_GYRO_INT		EXYNOS4_GPF0(3)
+#define GPIO_GSENSE_SDA_18V	EXYNOS4_GPD1(2)
+#define GPIO_GSENSE_SCL_18V	EXYNOS4_GPD1(3)
+
+#define GPIO_MSENSOR_INT	EXYNOS4212_GPJ0(7)
+#define GPIO_MSENSOR_SDA_18V	EXYNOS4_GPY2(4)
+#define GPIO_MSENSOR_SCL_18V	EXYNOS4_GPY2(5)
+
+#define GPIO_BENSE_SCL_18V	EXYNOS4_GPY2(3)
+#define GPIO_BSENSE_SDA_18V	EXYNOS4_GPY2(2)
+#define GPIO_BARO_INT		EXYNOS4_GPF0(5)
+
+#define GPIO_TF_EN		EXYNOS4_GPY2(0)
+#define GPIO_NFC_SCL_18V	EXYNOS4_GPD1(1)
+#define GPIO_NFC_SDA_18V	EXYNOS4_GPD1(0)
+#define GPIO_NFC_SCL_18V_00	EXYNOS4_GPB(3)
+#define GPIO_NFC_SDA_18V_00	EXYNOS4_GPB(2)
+#define GPIO_NFC_IRQ		EXYNOS4_GPX1(7)
+#define GPIO_NFC_EN		EXYNOS4_GPL2(6)
+#define GPIO_NFC_FIRMWARE	EXYNOS4_GPL2(7)
+#define GPIO_NFC_CLK_REQ	EXYNOS4212_GPM0(0)
+/* Sensors & NFC*/
+
+#define GPIO_DET_35		EXYNOS4_GPX0(1)
+
+#define GPIO_MIC_BIAS_EN	EXYNOS4_GPF1(7)
+#define GPIO_SUB_MIC_BIAS_EN	EXYNOS4_GPF2(0)
+#define GPIO_THIRD_MIC_BIAS_EN	EXYNOS4212_GPJ0(2)
+
+#define GPIO_PMU_RST		EXYNOS4_GPX3(2)
+
+#define GPIO_PMIC_IRQ		EXYNOS4_GPX0(7)
+#define GPIO_IF_PMIC_IRQ	EXYNOS4_GPX1(5)
+
+#define GPIO_TSP_INT		EXYNOS4212_GPM2(3)
+#define GPIO_TSP_SDA_18V	EXYNOS4_GPA1(2)
+#define GPIO_TSP_SCL_18V	EXYNOS4_GPA1(3)
+
+#define GPIO_BT_EN		EXYNOS4_GPL0(6)
+#define GPIO_BT_WAKE		EXYNOS4_GPX3(1)
+#define GPIO_BT_HOST_WAKE	EXYNOS4_GPX2(6)
+#define IRQ_BT_HOST_WAKE	IRQ_EINT(22)
+
+#define GPIO_BT_RXD		EXYNOS4_GPA0(0)
+#define GPIO_BT_RXD_AF		2
+
+#define GPIO_BT_TXD		EXYNOS4_GPA0(1)
+#define GPIO_BT_TXD_AF		2
+
+#define GPIO_BT_CTS		EXYNOS4_GPA0(2)
+#define GPIO_BT_CTS_AF		2
+
+#define GPIO_BT_RTS		EXYNOS4_GPA0(3)
+#define GPIO_BT_RTS_AF		2
+
+#define GPIO_GPS_RXD		EXYNOS4_GPA0(4)
+#define GPIO_GPS_RXD_AF		2
+
+#define GPIO_GPS_TXD		EXYNOS4_GPA0(5)
+#define GPIO_GPS_TXD_AF		2
+
+#define GPIO_GPS_CTS		EXYNOS4_GPA0(6)
+#define GPIO_GPS_CTS_AF		2
+
+#define GPIO_GPS_RTS		EXYNOS4_GPA0(7)
+#define GPIO_GPS_RTS_AF		2
+
+#define GPIO_FLM_RXD		EXYNOS4_GPA1(4)
+#define GPIO_FLM_RXD_AF		2
+
+#define GPIO_FLM_TXD		EXYNOS4_GPA1(5)
+#define GPIO_FLM_TXD_AF		2
+
+#define GPIO_3_TOUCH_SCL	EXYNOS4_GPL0(1)
+#define GPIO_3_TOUCH_SDA	EXYNOS4_GPL0(2)
+#define GPIO_HDMI_EN		EXYNOS4_GPL0(4)
+#define GPIO_3_TOUCH_INT	EXYNOS4212_GPJ0(3)
+#define GPIO_3_TOUCH_EN		EXYNOS4212_GPM0(0)
+
+#define GPIO_PWM0		EXYNOS4_GPD0(0)
+#define GPIO_PWM1		EXYNOS4_GPD0(1)
+#define GPIO_PWM2		EXYNOS4_GPD0(2)
+#define GPIO_PWM3		EXYNOS4_GPD0(3)
+
+#define GPIO_VIBTONE_EN		EXYNOS4212_GPJ0(6)
+
+#define GPIO_WLAN_EN		EXYNOS4212_GPJ0(0)
+#define GPIO_WLAN_EN_AF		1
+#define GPIO_WLAN_HOST_WAKE	EXYNOS4_GPX2(5)
+#define GPIO_WLAN_HOST_WAKE_AF	0xF
+#define GPIO_WLAN_SDIO_CLK	EXYNOS4_GPK3(0)
+#define GPIO_WLAN_SDIO_CLK_AF	2
+#define GPIO_WLAN_SDIO_CMD	EXYNOS4_GPK3(1)
+#define GPIO_WLAN_SDIO_CMD_AF	2
+#define GPIO_WLAN_SDIO_D0	EXYNOS4_GPK3(3)
+#define GPIO_WLAN_SDIO_D0_AF	2
+#define GPIO_WLAN_SDIO_D1	EXYNOS4_GPK3(4)
+#define GPIO_WLAN_SDIO_D1_AF	2
+#define GPIO_WLAN_SDIO_D2	EXYNOS4_GPK3(5)
+#define GPIO_WLAN_SDIO_D2_AF	2
+#define GPIO_WLAN_SDIO_D3	EXYNOS4_GPK3(6)
+#define GPIO_WLAN_SDIO_D3_AF	2
+
+#define GPIO_USB_SEL		EXYNOS4212_GPJ0(1)
+
+#define GPIO_LCD_22V_EN		EXYNOS4212_GPM4(4)
+#define GPIO_LCD_22V_EN_00	EXYNOS4_GPC0(1)
+
+#define GPIO_ISP_TXD		EXYNOS4212_GPM4(5)
+#define GPIO_ISP_RXD		EXYNOS4212_GPM4(6)
+
+#define GPIO_TA_EN		EXYNOS4_GPL2(2)
+
+#define GPIO_MHL_SEL		EXYNOS4_GPL0(3)
+
+#define GPIO_MHL_SDA_1_8V	EXYNOS4_GPF0(4)
+#define GPIO_MHL_SCL_1_8V	EXYNOS4_GPF0(6)
+#define GPIO_MHL_SDA_1_8V_00	EXYNOS4_GPB(2)
+#define GPIO_MHL_SCL_1_8V_00	EXYNOS4_GPB(3)
+
+#define GPIO_OTG_EN		EXYNOS4_GPF0(7)
+
+#define GPIO_OLED_ID		EXYNOS4_GPF1(0)
+#define GPIO_ISP_RESET		EXYNOS4_GPF1(3)
+#define GPIO_FUEL_SCL		EXYNOS4_GPF1(4)
+#define GPIO_FUEL_SDA		EXYNOS4_GPF1(5)
+
+#define GPIO_MLCD_RST		EXYNOS4_GPF2(1)
+#define GPIO_UART_SEL		EXYNOS4_GPF2(3)
+#define GPIO_S_LED_I2C_SCL	EXYNOS4_GPF2(6)
+#define GPIO_S_LED_I2C_SDA	EXYNOS4_GPF2(7)
+#define GPIO_OLED_DET		EXYNOS4_GPF3(0)
+
+#define GPIO_PMIC_DVS1		EXYNOS4212_GPM3(0)
+#define GPIO_PMIC_DVS2		EXYNOS4212_GPM3(1)
+
+/* Definitions for Sii 9244B0 */
+#define GPIO_PMIC_DVS3		EXYNOS4212_GPM3(2)
+#define GPIO_BUCK2_SEL		EXYNOS4_GPF3(1)
+#define GPIO_BUCK3_SEL		EXYNOS4_GPF3(2)
+#define GPIO_BUCK4_SEL		EXYNOS4_GPF3(3)
+#define GPIO_MHL_RST		EXYNOS4_GPF3(4)
+#define GPIO_MHL_INT		EXYNOS4_GPF3(5)
+#define GPIO_MHL_INT_AF		S3C_GPIO_SFN(0xF)
+#define GPIO_MHL_WAKE_UP	EXYNOS4212_GPJ1(4)
+
+#define GPIO_RGB_SDA_1_8V	EXYNOS4_GPF0(0)
+#define GPIO_RGB_SCL_1_8V	EXYNOS4_GPF0(1)
+#define GPIO_RGB_INT		EXYNOS4_GPX2(2)
+#define GPIO_VOL_UP		EXYNOS4212_GPJ1(1)
+#define GPIO_VOL_DOWN		EXYNOS4212_GPJ1(2)
+#define GPIO_VOL_UP_00		EXYNOS4_GPX2(2)
+#define GPIO_VOL_DOWN_00	EXYNOS4_GPX3(3)
+
+#define GPIO_CAM_SW_EN		EXYNOS4212_GPJ1(0)
+#define GPIO_TORCH_EN		EXYNOS4212_GPJ1(1)
+#define GPIO_TORCH_SET		EXYNOS4212_GPJ1(2)
+
+#define GPIO_MHL_DSCL_2_8V	EXYNOS4_GPK1(0)
+#define GPIO_MHL_DSDA_2_8V	EXYNOS4_GPK1(2)
+
+#define MHL_INT_IRQ		gpio_to_irq(GPIO_MHL_INT)
+#define MHL_WAKEUP_IRQ		gpio_to_irq(GPIO_MHL_WAKE_UP)
+
+#define GPIO_HDMI_CEC		EXYNOS4_GPX3(6)
+#define GPIO_HDMI_HPD		EXYNOS4_GPX3(7)
+
+#define GPIO_nPOWER		EXYNOS4_GPX2(7)
+#define GPIO_OK_KEY		EXYNOS4_GPX3(5)
+#define GPIO_OK_KEY_ANDROID	EXYNOS4_GPX0(1)		/*system_rev == 11*/
+#define GPIO_OK_KEY_ANDROID_F EXYNOS4_GPX1(3)	/*system_rev >= 15*/
+#define GPIO_FUEL_ALERT		EXYNOS4_GPX2(3)
+
+#define GPIO_V_BUS_INT		EXYNOS4_GPX2(4)	/* rev0.9 ~ */
+#define GPIO_WPC_INT		EXYNOS4_GPX3(0)
+
+#define GPIO_VIBTONE_PWM	EXYNOS4_GPD0(1)
+
+#define GPIO_CODEC_SDA_18V	EXYNOS4_GPD0(2)
+#define GPIO_CODEC_SCL_18V	EXYNOS4_GPD0(3)
+#define GPIO_CODEC_SDA_18V_00	EXYNOS4_GPB(0)
+#define GPIO_CODEC_SCL_18V_00	EXYNOS4_GPB(1)
+
+#define GPIO_CODEC_LDO_EN	EXYNOS4212_GPJ0(4)
+
+#define GPIO_WM8994_LDO		EXYNOS4212_GPJ0(4)
+
+#define GPIO_FM_RST	EXYNOS4_GPC1(1)
+#define GPIO_FM_INT_REV15	EXYNOS4_GPX1(3)
+#define GPIO_FM_INT_REV07	EXYNOS4_GPX1(3)
+#define GPIO_FM_INT	EXYNOS4_GPX1(3)
+#define GPIO_FM_MIC_SW		EXYNOS4_GPL0(3)
+
+/* Definitions for DPRAM */
+#define GPIO_DPRAM_CSN		EXYNOS4_GPY0(0)
+#define GPIO_DPRAM_CSN0		EXYNOS4_GPY0(0)
+#define GPIO_DPRAM_CSN1		EXYNOS4_GPY0(1)
+#define GPIO_DPRAM_CSN2		EXYNOS4_GPY0(2)
+#define GPIO_DPRAM_CSN3		EXYNOS4_GPY0(3)
+#define GPIO_DPRAM_REN		EXYNOS4_GPY0(4)
+#define GPIO_DPRAM_WEN		EXYNOS4_GPY0(5)
+#define GPIO_DPRAM_LBN		EXYNOS4_GPY1(0)
+#define GPIO_DPRAM_UBN		EXYNOS4_GPY1(1)
+#define GPIO_DPRAM_BUSY		EXYNOS4_GPY1(2)
+
+/* Definitions for CMC221 */
+#define GPIO_ACTIVE_STATE	EXYNOS4_GPF1(1)
+#define GPIO_PDA_ACTIVE		EXYNOS4_GPF1(6)
+#define GPIO_AP_CP_INT		EXYNOS4_GPF2(2)
+
+#define GPIO_USB_HUB_RST	EXYNOS4_GPL0(0)
+#define GPIO_USB_HUB_SCL	EXYNOS4_GPL1(0)
+#define GPIO_USB_HUB_SDA	EXYNOS4_GPL1(1)
+#define GPIO_USB_HUB_INT	EXYNOS4_GPX2(1)
+#define GPIO_USB_HUB_CONNECT	EXYNOS4212_GPV3(5)
+#define GPIO_USB_BOOT_EN		EXYNOS4212_GPV3(7)
+
+#define GPIO_BOOT_SW_SEL		EXYNOS4212_GPV3(6)
+
+/* for revesion 06 higher */
+#define GPIO_USB_BOOT_EN_REV06		EXYNOS4_GPF2(2)
+#define GPIO_BOOT_SW_SEL_REV06		EXYNOS4_GPF1(1)
+
+#define GPIO_IPC_SLAVE_WAKEUP	EXYNOS4_GPX1(0)
+#define GPIO_IPC_HOST_WAKEUP	EXYNOS4_GPX1(1)
+
+#define GPIO_CP_MSM_PWRON	EXYNOS4_GPL2(5)
+ #define GPIO_CP_MSM_RST	EXYNOS4_GPL2(4)
+#define GPIO_CP_MSM_PMU_RST	EXYNOS4_GPX3(2)
+#define GPIO_CP_MSM_DUMP	EXYNOS4_GPX1(2)
+
+#define GPIO_MSM_PHONE_ACTIVE		EXYNOS4_GPX1(6)
+#define MSM_PHONE_ACTIVE_IRQ		IRQ_EINT(14)	/* IRQ of GPX1[6] */
+
+#define GPIO_MSM_DPRAM_INT	EXYNOS4_GPX2(0)
+#define MSM_DPRAM_INT_IRQ	IRQ_EINT(16)	/* IRQ of GPX2[0] */
+
+
+#endif /* __MACH_GPIO_C1_H */
diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev00-m0grandectc.h b/arch/arm/mach-exynos/include/mach/gpio-rev00-m0grandectc.h
new file mode 100644
index 0000000..e5c96b4
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/gpio-rev00-m0grandectc.h
@@ -0,0 +1,227 @@
+#ifndef __MACH_GPIO_C1_H
+#define __MACH_GPIO_C1_H __FILE__
+
+#include <mach/gpio.h>
+
+extern void midas_config_gpio_table(void);
+extern void midas_config_sleep_gpio_table(void);
+
+#define GPIO_eMMC_EN		EXYNOS4_GPK0(2)
+
+#define GPIO_BOOT_MODE		EXYNOS4_GPX0(3)
+
+
+#define GPIO_IF_PMIC_SDA	EXYNOS4212_GPM2(0)
+#define GPIO_IF_PMIC_SCL	EXYNOS4212_GPM2(1)
+
+#define GPIO_CAM_MCLK		EXYNOS4212_GPJ1(3)
+#define GPIO_VTCAM_MCLK		EXYNOS4212_GPM2(2)
+
+#define GPIO_ISP_STANDBY	EXYNOS4212_GPM0(1)
+#define GPIO_CAM_IO_EN		EXYNOS4212_GPM0(2)
+#define GPIO_ISP_CORE_EN	EXYNOS4212_GPM0(3)
+#define GPIO_CAM_AF_EN		EXYNOS4212_GPM0(4)
+#define GPIO_CAM_VT_nRST	EXYNOS4212_GPM1(6)
+
+#define GPIO_8M_CAM_SCL_18V	EXYNOS4_GPD1(0)
+#define GPIO_8M_CAM_SDA_18V	EXYNOS4_GPD1(1)
+
+#define GPIO_VT_CAM_SCL_18V	EXYNOS4212_GPM4(2)
+#define GPIO_VT_CAM_SDA_18V	EXYNOS4212_GPM4(3)
+
+#define GPIO_ACC_INT		EXYNOS4_GPX0(0)
+
+#define GPIO_GYRO_DE		EXYNOS4_GPL2(0)
+
+#define GPIO_GYRO_INT		EXYNOS4_GPF0(3)
+#define GPIO_GSENSE_SDA_18V	EXYNOS4_GPD1(2)
+#define GPIO_GSENSE_SCL_18V	EXYNOS4_GPD1(3)
+
+#define GPIO_MSENSOR_INT	EXYNOS4212_GPJ0(7)
+#define GPIO_MSENSOR_SDA_18V	EXYNOS4_GPY2(4)
+#define GPIO_MSENSOR_SCL_18V	EXYNOS4_GPY2(5)
+
+#define GPIO_BENSE_SCL_18V	EXYNOS4_GPY2(3)
+#define GPIO_BSENSE_SDA_18V	EXYNOS4_GPY2(2)
+
+#define GPIO_TF_EN		EXYNOS4_GPY2(0)
+
+#define GPIO_MIC_BIAS_EN	EXYNOS4_GPF1(7)
+#define GPIO_SUB_MIC_BIAS_EN	EXYNOS4_GPF2(0)
+
+#define GPIO_PMU_RST		EXYNOS4_GPX3(2)
+
+#define GPIO_PMIC_IRQ		EXYNOS4_GPX0(7)
+#define GPIO_IF_PMIC_IRQ	EXYNOS4_GPX1(5)
+
+#define GPIO_TSP_INT		EXYNOS4212_GPM2(3)
+#define GPIO_TSP_SDA_18V	EXYNOS4_GPA1(2)
+#define GPIO_TSP_SCL_18V	EXYNOS4_GPA1(3)
+
+#define GPIO_BT_EN		EXYNOS4_GPL0(6)
+#define GPIO_BT_WAKE		EXYNOS4_GPX3(1)
+#define GPIO_BT_HOST_WAKE	EXYNOS4_GPX2(6)
+#define IRQ_BT_HOST_WAKE	IRQ_EINT(22)
+
+#define GPIO_BT_RXD		EXYNOS4_GPA0(0)
+#define GPIO_BT_RXD_AF		2
+
+#define GPIO_BT_TXD		EXYNOS4_GPA0(1)
+#define GPIO_BT_TXD_AF		2
+
+#define GPIO_BT_CTS		EXYNOS4_GPA0(2)
+#define GPIO_BT_CTS_AF		2
+
+#define GPIO_BT_RTS		EXYNOS4_GPA0(3)
+#define GPIO_BT_RTS_AF		2
+
+#define GPIO_GPS_RXD		EXYNOS4_GPA0(4)
+#define GPIO_GPS_RXD_AF		2
+
+#define GPIO_GPS_TXD		EXYNOS4_GPA0(5)
+#define GPIO_GPS_TXD_AF		2
+
+#define GPIO_GPS_CTS		EXYNOS4_GPA0(6)
+#define GPIO_GPS_CTS_AF		2
+
+#define GPIO_GPS_RTS		EXYNOS4_GPA0(7)
+#define GPIO_GPS_RTS_AF		2
+
+#define GPIO_FLM_RXD		EXYNOS4_GPA1(4)
+#define GPIO_FLM_RXD_AF		2
+
+#define GPIO_FLM_TXD		EXYNOS4_GPA1(5)
+#define GPIO_FLM_TXD_AF		2
+
+#define GPIO_PWM0		EXYNOS4_GPD0(0)
+#define GPIO_PWM1		EXYNOS4_GPD0(1)
+#define GPIO_PWM2		EXYNOS4_GPD0(2)
+#define GPIO_PWM3		EXYNOS4_GPD0(3)
+
+#define GPIO_WLAN_EN		EXYNOS4212_GPJ0(0)
+#define GPIO_WLAN_EN_AF		1
+#define GPIO_WLAN_HOST_WAKE	EXYNOS4_GPX2(5)
+#define GPIO_WLAN_HOST_WAKE_AF	0xF
+#define GPIO_WLAN_SDIO_CLK	EXYNOS4_GPK3(0)
+#define GPIO_WLAN_SDIO_CLK_AF	2
+#define GPIO_WLAN_SDIO_CMD	EXYNOS4_GPK3(1)
+#define GPIO_WLAN_SDIO_CMD_AF	2
+#define GPIO_WLAN_SDIO_D0	EXYNOS4_GPK3(3)
+#define GPIO_WLAN_SDIO_D0_AF	2
+#define GPIO_WLAN_SDIO_D1	EXYNOS4_GPK3(4)
+#define GPIO_WLAN_SDIO_D1_AF	2
+#define GPIO_WLAN_SDIO_D2	EXYNOS4_GPK3(5)
+#define GPIO_WLAN_SDIO_D2_AF	2
+#define GPIO_WLAN_SDIO_D3	EXYNOS4_GPK3(6)
+#define GPIO_WLAN_SDIO_D3_AF	2
+
+#define GPIO_USB_SEL		EXYNOS4212_GPJ1(4)
+
+#define GPIO_LCD_22V_EN_00	EXYNOS4_GPC0(1)
+
+#define GPIO_OTG_EN		EXYNOS4_GPF0(7)
+
+#define GPIO_ISP_RESET		EXYNOS4_GPF1(3)
+#define GPIO_FUEL_SCL		EXYNOS4_GPF1(4)
+#define GPIO_FUEL_SDA		EXYNOS4_GPF1(5)
+
+#define GPIO_MLCD_RST		EXYNOS4_GPF2(1)
+#define GPIO_UART_SEL		EXYNOS4212_GPJ0(2)
+#define GPIO_S_LED_I2C_SCL
+#define GPIO_S_LED_I2C_SDA
+#define GPIO_OLED_DET		EXYNOS4_GPF3(0)
+
+#define GPIO_LCD_SEL		EXYNOS4_GPF2(6)
+#define GPIO_LCD_OE			EXYNOS4_GPF2(7)
+
+#define GPIO_PMIC_DVS1		EXYNOS4212_GPM3(0)
+#define GPIO_PMIC_DVS2		EXYNOS4212_GPM3(1)
+
+/* Definitions for Sii 9244B0 */
+#define GPIO_PMIC_DVS3		EXYNOS4212_GPM3(2)
+#define GPIO_BUCK2_SEL		EXYNOS4_GPF3(1)
+#define GPIO_BUCK3_SEL		EXYNOS4_GPF3(2)
+#define GPIO_BUCK4_SEL		EXYNOS4_GPF3(3)
+
+#define GPIO_VOL_UP			EXYNOS4_GPX2(2)
+#define GPIO_VOL_DOWN		EXYNOS4_GPX3(3)
+#define GPIO_VOL_UP_00		EXYNOS4_GPX2(2)
+#define GPIO_VOL_DOWN_00	EXYNOS4_GPX3(3)
+
+#define GPIO_CAM_SW_EN		EXYNOS4212_GPJ1(0)
+#define GPIO_TORCH_EN		EXYNOS4212_GPJ1(1)
+#define GPIO_TORCH_SET		EXYNOS4212_GPJ1(2)
+
+#define MHL_INT_IRQ		gpio_to_irq(GPIO_MHL_INT)
+#define MHL_WAKEUP_IRQ		gpio_to_irq(GPIO_MHL_WAKE_UP)
+
+#define GPIO_nPOWER		EXYNOS4_GPX2(7)
+#define GPIO_OK_KEY		EXYNOS4_GPX3(5)
+#define GPIO_OK_KEY_ANDROID	EXYNOS4_GPX0(1)		/*system_rev == 11*/
+#define GPIO_OK_KEY_ANDROID_F EXYNOS4_GPX1(3)	/*system_rev >= 15*/
+#define GPIO_FUEL_ALERT		EXYNOS4_GPX2(3)
+
+#define GPIO_WPC_INT		EXYNOS4_GPX3(0)
+
+#define GPIO_VIBTONE_PWM	EXYNOS4_GPD0(1)
+
+#define GPIO_CODEC_SDA_18V_00	EXYNOS4_GPB(0)
+#define GPIO_CODEC_SCL_18V_00	EXYNOS4_GPB(1)
+
+#define GPIO_CODEC_LDO_EN	EXYNOS4212_GPJ0(4)
+
+#define GPIO_WM8994_LDO		EXYNOS4212_GPJ0(4)
+
+/* Definitions for DPRAM */
+#define GPIO_DPRAM_CSN		EXYNOS4_GPY0(0)
+#define GPIO_DPRAM_CSN0		EXYNOS4_GPY0(0)
+#define GPIO_DPRAM_CSN1		EXYNOS4_GPY0(1)
+#define GPIO_DPRAM_CSN2		EXYNOS4_GPY0(2)
+#define GPIO_DPRAM_CSN3		EXYNOS4_GPY0(3)
+#define GPIO_DPRAM_REN		EXYNOS4_GPY0(4)
+#define GPIO_DPRAM_WEN		EXYNOS4_GPY0(5)
+#define GPIO_DPRAM_LBN		EXYNOS4_GPY1(0)
+#define GPIO_DPRAM_UBN		EXYNOS4_GPY1(1)
+#define GPIO_DPRAM_BUSY		EXYNOS4_GPY1(2)
+
+/* Definitions for CMC221 */
+#define GPIO_ACTIVE_STATE	EXYNOS4_GPF1(1)
+#define GPIO_PDA_ACTIVE		EXYNOS4_GPF1(6)
+#define GPIO_AP_CP_INT		EXYNOS4_GPF2(2)
+
+#define GPIO_USB_HUB_RST	EXYNOS4_GPL0(0)
+#define GPIO_USB_HUB_SCL	EXYNOS4_GPL1(0)
+#define GPIO_USB_HUB_SDA	EXYNOS4_GPL1(1)
+#define GPIO_USB_HUB_INT	EXYNOS4_GPX2(1)
+#define GPIO_USB_HUB_CONNECT	EXYNOS4212_GPV3(5)
+#define GPIO_USB_BOOT_EN		EXYNOS4212_GPV3(7)
+
+#define GPIO_BOOT_SW_SEL		EXYNOS4212_GPV3(6)
+
+/* for revesion 06 higher */
+#define GPIO_USB_BOOT_EN_REV06		EXYNOS4212_GPV3(7)
+#define GPIO_BOOT_SW_SEL_REV06		EXYNOS4212_GPV3(6)
+
+#define GPIO_IPC_SLAVE_WAKEUP	EXYNOS4_GPX1(0)
+#define GPIO_IPC_HOST_WAKEUP	EXYNOS4_GPX1(1)
+
+#define GPIO_CP_MSM_PWRON	EXYNOS4_GPL2(5)
+#define GPIO_CP_MSM_RST		EXYNOS4_GPL2(4)
+#define GPIO_CP_MSM_PMU_RST	EXYNOS4_GPX3(2)
+#define GPIO_CP_MSM_DUMP	EXYNOS4_GPX1(2)
+
+#define GPIO_MSM_PHONE_ACTIVE		EXYNOS4_GPX1(6)
+#define MSM_PHONE_ACTIVE_IRQ		IRQ_EINT(14)	/* IRQ of GPX1[6] */
+
+#define GPIO_MSM_DPRAM_INT	EXYNOS4_GPX2(0)
+#define MSM_DPRAM_INT_IRQ	IRQ_EINT(16)	/* IRQ of GPX2[0] */
+
+#define GPIO_CP2_MSM_PWRON		EXYNOS4_GPL2(1)
+#define GPIO_CP2_MSM_RST		EXYNOS4_GPL2(2)
+
+/* DUMP GPIOS */
+#define GPIO_HDMI_HPD		EXYNOS4_GPA1(4)
+#define GPIO_HDMI_EN		EXYNOS4_GPA1(4)
+#define GPIO_V_BUS_INT		EXYNOS4_GPA1(4)
+
+#endif /* __MACH_GPIO_C1_H */
diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev00-m3.h b/arch/arm/mach-exynos/include/mach/gpio-rev00-m3.h
new file mode 100644
index 0000000..cd3bc9c
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/gpio-rev00-m3.h
@@ -0,0 +1,291 @@
+#ifndef __MACH_GPIO_M3_H
+#define __MACH_GPIO_M3_H __FILE__
+
+#include <mach/gpio.h>
+
+extern void midas_config_gpio_table(void);
+extern void midas_config_sleep_gpio_table(void);
+
+#define GPIO_eMMC_EN		EXYNOS4_GPK0(2)
+
+#define GPIO_BOOT_MODE		EXYNOS4_GPX0(3)
+
+#define GPIO_FM_I2S_CLK		EXYNOS4_GPC0(0)
+#define GPIO_FM_I2S_SYNC	EXYNOS4_GPC0(2)
+#define GPIO_FM_I2S_DI		EXYNOS4_GPC0(3)
+#define GPIO_FM_I2S_DO		EXYNOS4_GPC0(4)
+
+#define GPIO_IF_PMIC_SDA	EXYNOS4212_GPM2(0)
+#define GPIO_IF_PMIC_SCL	EXYNOS4212_GPM2(1)
+#define GPIO_PMIC_SDA		EXYNOS4_GPB(2)
+#define GPIO_PMIC_SCL		EXYNOS4_GPB(3)
+
+#define GPIO_ADC_SCL		EXYNOS4_GPY0(2)
+#define GPIO_ADC_SDA		EXYNOS4_GPY0(3)
+#define GPIO_ADC_INT		EXYNOS4_GPX2(4)
+
+#define GPIO_CAM_SPI_SCLK	EXYNOS4_GPB(4)
+#define GPIO_CAM_SPI_SSN	EXYNOS4_GPB(5)
+#define GPIO_CAM_SPI_MISO	EXYNOS4_GPB(6)
+#define GPIO_CAM_SPI_MOSI	EXYNOS4_GPB(7)
+
+#define GPIO_CAM_MCLK		EXYNOS4212_GPJ1(3)
+#define GPIO_VTCAM_MCLK		EXYNOS4212_GPM2(2)
+
+#define GPIO_ISP_STANDBY	EXYNOS4212_GPM0(1)
+#define GPIO_CAM_IO_EN		EXYNOS4212_GPM0(2)
+#define GPIO_ISP_CORE_EN	EXYNOS4212_GPM0(3)
+#define GPIO_CAM_AF_EN		EXYNOS4212_GPM0(4)
+#define GPIO_CAM_VT_nRST	EXYNOS4212_GPM1(6)
+
+#define GPIO_8M_CAM_SCL_18V	EXYNOS4212_GPM4(0)
+#define GPIO_8M_CAM_SDA_18V	EXYNOS4212_GPM4(1)
+#define GPIO_8M_CAM_SCL_18V_00	EXYNOS4_GPD1(0)
+#define GPIO_8M_CAM_SDA_18V_00	EXYNOS4_GPD1(1)
+
+#define GPIO_VT_CAM_SCL_18V	EXYNOS4212_GPM4(2)
+#define GPIO_VT_CAM_SDA_18V	EXYNOS4212_GPM4(3)
+#define GPIO_VT_CAM_ID		EXYNOS4_GPF1(2)
+
+/* Sensors & NFC*/
+#define GPIO_PS_ALS_EN		EXYNOS4212_GPJ0(5)
+#define GPIO_PS_ALS_SDA_28V	EXYNOS4_GPK1(1)
+#define GPIO_PS_ALS_SCL_28V	EXYNOS4_GPK2(2)
+#define GPIO_PS_ALS_INT		EXYNOS4_GPX0(2)
+
+#define GPIO_ACC_INT		EXYNOS4_GPX0(0)
+
+#define GPIO_GYRO_DE		EXYNOS4_GPL2(0)
+#define GPIO_GPS_nRST		EXYNOS4_GPL2(1)
+#define GPIO_GPS_PWR_EN		EXYNOS4_GPL2(2)
+
+#define GPIO_GYRO_INT		EXYNOS4_GPF0(3)
+#define GPIO_GSENSE_SDA_18V	EXYNOS4_GPD1(2)
+#define GPIO_GSENSE_SCL_18V	EXYNOS4_GPD1(3)
+
+#define GPIO_MSENSOR_INT	EXYNOS4212_GPJ0(7)
+#define GPIO_MSENSOR_SDA_18V	EXYNOS4_GPY2(4)
+#define GPIO_MSENSOR_SCL_18V	EXYNOS4_GPY2(5)
+
+#define GPIO_BENSE_SCL_18V	EXYNOS4_GPY2(3)
+#define GPIO_BSENSE_SDA_18V	EXYNOS4_GPY2(2)
+#define GPIO_BARO_INT		EXYNOS4_GPF0(5)
+
+#define GPIO_TF_EN		EXYNOS4_GPY0(1)
+#define GPIO_NFC_SCL_18V	EXYNOS4_GPD1(1)
+#define GPIO_NFC_SDA_18V	EXYNOS4_GPD1(0)
+#define GPIO_NFC_SCL_18V_00	EXYNOS4_GPB(3)
+#define GPIO_NFC_SDA_18V_00	EXYNOS4_GPB(2)
+#define GPIO_NFC_IRQ		EXYNOS4_GPX1(7)
+#define GPIO_NFC_EN		EXYNOS4_GPL2(6)
+#define GPIO_NFC_FIRMWARE	EXYNOS4_GPL2(7)
+#define GPIO_NFC_CLK_REQ	EXYNOS4212_GPM0(0)
+/* Sensors & NFC*/
+
+#define GPIO_DET_35		EXYNOS4_GPX0(1)
+
+#define GPIO_MIC_BIAS_EN	EXYNOS4_GPF1(7)
+#define GPIO_SUB_MIC_BIAS_EN	EXYNOS4_GPF2(0)
+
+#define GPIO_PMU_RST		EXYNOS4_GPX3(2)
+
+#define GPIO_PMIC_IRQ		EXYNOS4_GPX0(7)
+#define GPIO_IF_PMIC_IRQ	EXYNOS4_GPX1(5)
+
+#define GPIO_TSP_INT		EXYNOS4212_GPM2(3)
+#define GPIO_TSP_SDA_18V	EXYNOS4_GPA1(2)
+#define GPIO_TSP_SCL_18V	EXYNOS4_GPA1(3)
+
+#define GPIO_BT_EN		EXYNOS4_GPL0(6)
+#define GPIO_BT_WAKE		EXYNOS4_GPX3(1)
+#define GPIO_BT_HOST_WAKE	EXYNOS4_GPX2(6)
+#define IRQ_BT_HOST_WAKE	IRQ_EINT(22)
+
+#define GPIO_BT_RXD		EXYNOS4_GPA0(0)
+#define GPIO_BT_RXD_AF		2
+
+#define GPIO_BT_TXD		EXYNOS4_GPA0(1)
+#define GPIO_BT_TXD_AF		2
+
+#define GPIO_BT_CTS		EXYNOS4_GPA0(2)
+#define GPIO_BT_CTS_AF		2
+
+#define GPIO_BT_RTS		EXYNOS4_GPA0(3)
+#define GPIO_BT_RTS_AF		2
+
+#define GPIO_GPS_RXD		EXYNOS4_GPA0(4)
+#define GPIO_GPS_RXD_AF		2
+
+#define GPIO_GPS_TXD		EXYNOS4_GPA0(5)
+#define GPIO_GPS_TXD_AF		2
+
+#define GPIO_GPS_CTS		EXYNOS4_GPA0(6)
+#define GPIO_GPS_CTS_AF		2
+
+#define GPIO_GPS_RTS		EXYNOS4_GPA0(7)
+#define GPIO_GPS_RTS_AF		2
+
+#define GPIO_FLM_RXD		EXYNOS4_GPA1(4)
+#define GPIO_FLM_RXD_AF		2
+
+#define GPIO_FLM_TXD		EXYNOS4_GPA1(5)
+#define GPIO_FLM_TXD_AF		2
+
+#define GPIO_3_TOUCH_SCL	EXYNOS4_GPL0(1)
+#define GPIO_3_TOUCH_SDA	EXYNOS4_GPL0(2)
+#define GPIO_HDMI_EN		EXYNOS4_GPL0(4)
+#define GPIO_3_TOUCH_INT	EXYNOS4212_GPJ1(0)
+#define GPIO_TOUCH_EN		EXYNOS4212_GPJ0(3)
+
+#define GPIO_PWM0		EXYNOS4_GPD0(0)
+#define GPIO_PWM1		EXYNOS4_GPD0(1)
+#define GPIO_PWM2		EXYNOS4_GPD0(2)
+#define GPIO_PWM3		EXYNOS4_GPD0(3)
+
+#define GPIO_VIBTONE_EN		EXYNOS4212_GPJ0(6)
+
+#define GPIO_WLAN_EN		EXYNOS4212_GPJ0(0)
+#define GPIO_WLAN_EN_AF		1
+#define GPIO_WLAN_HOST_WAKE	EXYNOS4_GPX2(5)
+#define GPIO_WLAN_HOST_WAKE_AF	0xF
+#define GPIO_WLAN_SDIO_CLK	EXYNOS4_GPK3(0)
+#define GPIO_WLAN_SDIO_CLK_AF	2
+#define GPIO_WLAN_SDIO_CMD	EXYNOS4_GPK3(1)
+#define GPIO_WLAN_SDIO_CMD_AF	2
+#define GPIO_WLAN_SDIO_D0	EXYNOS4_GPK3(3)
+#define GPIO_WLAN_SDIO_D0_AF	2
+#define GPIO_WLAN_SDIO_D1	EXYNOS4_GPK3(4)
+#define GPIO_WLAN_SDIO_D1_AF	2
+#define GPIO_WLAN_SDIO_D2	EXYNOS4_GPK3(5)
+#define GPIO_WLAN_SDIO_D2_AF	2
+#define GPIO_WLAN_SDIO_D3	EXYNOS4_GPK3(6)
+#define GPIO_WLAN_SDIO_D3_AF	2
+
+#define GPIO_USB_SEL		EXYNOS4212_GPJ0(1)
+
+#define GPIO_LCD_22V_EN		EXYNOS4212_GPM4(4)
+#define GPIO_LCD_22V_EN_00	EXYNOS4_GPC0(1)
+
+#define GPIO_ISP_TXD		EXYNOS4212_GPM4(5)
+#define GPIO_ISP_RXD		EXYNOS4212_GPM4(6)
+
+#define GPIO_TA_EN		EXYNOS4_GPL2(2)
+
+#define GPIO_MHL_SEL		EXYNOS4_GPL0(3)
+
+#define GPIO_MHL_SDA_1_8V	EXYNOS4_GPF0(4)
+#define GPIO_MHL_SCL_1_8V	EXYNOS4_GPF0(6)
+#define GPIO_MHL_SDA_1_8V_00	EXYNOS4_GPB(2)
+#define GPIO_MHL_SCL_1_8V_00	EXYNOS4_GPB(3)
+
+#define GPIO_OTG_EN		EXYNOS4_GPF0(7)
+
+#define GPIO_OLED_ID		EXYNOS4_GPF1(0)
+#define GPIO_ISP_RESET		EXYNOS4_GPF1(3)
+#define GPIO_FUEL_SCL		EXYNOS4_GPF1(4)
+#define GPIO_FUEL_SDA		EXYNOS4_GPF1(5)
+
+#define GPIO_MLCD_RST		EXYNOS4_GPF2(1)
+#define GPIO_UART_SEL		EXYNOS4_GPF2(3)
+#define GPIO_S_LED_I2C_SCL	EXYNOS4_GPF2(6)
+#define GPIO_S_LED_I2C_SDA	EXYNOS4_GPF2(7)
+#define GPIO_OLED_DET		EXYNOS4_GPF3(0)
+
+#define GPIO_PMIC_DVS1		EXYNOS4212_GPM3(0)
+#define GPIO_PMIC_DVS2		EXYNOS4212_GPM3(1)
+
+/* Definitions for Sii 9244B0 */
+#define GPIO_PMIC_DVS3		EXYNOS4212_GPM3(2)
+#define GPIO_BUCK2_SEL		EXYNOS4_GPF3(1)
+#define GPIO_BUCK3_SEL		EXYNOS4_GPF3(2)
+#define GPIO_BUCK4_SEL		EXYNOS4_GPF3(3)
+#define GPIO_MHL_RST		EXYNOS4_GPF3(4)
+#define GPIO_MHL_INT		EXYNOS4_GPF3(5)
+#define GPIO_MHL_INT_AF		S3C_GPIO_SFN(0xF)
+#define GPIO_MHL_WAKE_UP	EXYNOS4212_GPJ1(4)
+
+#define GPIO_RGB_SDA_1_8V	EXYNOS4_GPF0(0)
+#define GPIO_RGB_SCL_1_8V	EXYNOS4_GPF0(1)
+#define GPIO_RGB_INT		EXYNOS4_GPX2(2)
+#define GPIO_VOL_UP		EXYNOS4212_GPJ1(1)
+#define GPIO_VOL_DOWN		EXYNOS4212_GPJ1(2)
+#define GPIO_VOL_UP_00		EXYNOS4_GPX2(2)
+#define GPIO_VOL_DOWN_00	EXYNOS4_GPX3(3)
+
+#define GPIO_CAM_SW_EN		EXYNOS4212_GPJ1(0)
+#define GPIO_TORCH_EN		EXYNOS4212_GPJ1(1)
+#define GPIO_TORCH_SET		EXYNOS4212_GPJ1(2)
+
+#define GPIO_MHL_DSCL_2_8V	EXYNOS4_GPK1(0)
+#define GPIO_MHL_DSDA_2_8V	EXYNOS4_GPK1(2)
+
+#define MHL_INT_IRQ		gpio_to_irq(GPIO_MHL_INT)
+#define MHL_WAKEUP_IRQ		gpio_to_irq(GPIO_MHL_WAKE_UP)
+
+#define GPIO_HDMI_HPD		EXYNOS4_GPX3(7)
+
+#define GPIO_nPOWER		EXYNOS4_GPX2(7)
+#define GPIO_OK_KEY		EXYNOS4_GPX3(5)
+
+#define GPIO_FUEL_ALERT		EXYNOS4_GPX2(3)
+
+#define GPIO_WPC_INT		EXYNOS4_GPX3(0)
+
+#define GPIO_VIBTONE_PWM	EXYNOS4_GPD0(1)
+
+#define GPIO_CODEC_SDA_18V	EXYNOS4_GPD0(2)
+#define GPIO_CODEC_SCL_18V	EXYNOS4_GPD0(3)
+#define GPIO_CODEC_SDA_18V_00	EXYNOS4_GPB(0)
+#define GPIO_CODEC_SCL_18V_00	EXYNOS4_GPB(1)
+
+#define GPIO_CODEC_LDO_EN	EXYNOS4212_GPJ0(4)
+
+#define GPIO_WM8994_LDO		EXYNOS4212_GPJ0(4)
+
+/* Definitions for DPRAM */
+#define GPIO_DPRAM_CSN		EXYNOS4_GPY0(0)
+#define GPIO_DPRAM_CSN0		EXYNOS4_GPY0(0)
+#define GPIO_DPRAM_CSN1		EXYNOS4_GPY0(1)
+#define GPIO_DPRAM_CSN2		EXYNOS4_GPY0(2)
+#define GPIO_DPRAM_CSN3		EXYNOS4_GPY0(3)
+#define GPIO_DPRAM_REN		EXYNOS4_GPY0(4)
+#define GPIO_DPRAM_WEN		EXYNOS4_GPY0(5)
+
+/* Definitions for CMC221 */
+#define GPIO_ACTIVE_STATE	EXYNOS4_GPF1(1)
+#define GPIO_PDA_ACTIVE		EXYNOS4_GPF1(6)
+#define GPIO_AP_CP_INT		EXYNOS4_GPF2(2)
+#define GPIO_USB_HUB_RST	EXYNOS4_GPL0(0)
+#define GPIO_USB_HUB_SCL	EXYNOS4_GPL1(0)
+#define GPIO_USB_HUB_SDA	EXYNOS4_GPL1(1)
+#define CP_CMC221_CPU_RST	EXYNOS4_GPL2(4)
+#define CP_CMC221_PMIC_PWRON	EXYNOS4_GPL2(5)
+#define GPIO_CMC2AP_INT1_18V	EXYNOS4_GPX0(5)
+#define GPIO_AP2CMC_DP_INT3_18V	EXYNOS4_GPX3(2)
+#define GPIO_IPC_SLAVE_WAKEUP	EXYNOS4_GPX1(0)
+#define GPIO_IPC_HOST_WAKEUP	EXYNOS4_GPX1(1)
+
+#define GPIO_LTE_ACTIVE		EXYNOS4_GPX1(6)
+#define LTE_ACTIVE_IRQ		IRQ_EINT(14)	/* IRQ of GPX1[6] */
+
+#define GPIO_CMC_IDPRAM_INT	EXYNOS4_GPX2(0)
+#define CMC_IDPRAM_INT_IRQ	IRQ_EINT(16)	/* IRQ of GPX2[0] */
+
+#define GPIO_USB_HUB_INT	EXYNOS4_GPX2(1)
+
+#define GPIO_CMC2AP_STATUS	EXYNOS4_GPX0(5)
+#define GPIO_AP2CMC_WAKEUP	EXYNOS4_GPX1(2)
+
+#define ACTIVE_STATE_HSIC	EXYNOS4_GPF1(1)
+#define MDM_LTE_ACTIVE		EXYNOS4_GPF2(0)
+#define PDA_ACTIVE		EXYNOS4_GPF1(6)
+#define AP2MDM_PMIC_RESET_N	EXYNOS4_GPL2(4)
+#define MDM2AP_STATUS		EXYNOS4212_GPM1(1)
+#define AP2MDM_STATUS		EXYNOS4212_GPM2(4)
+#define MDM2AP_HSIC_READY	EXYNOS4_GPX0(4)
+#define AP2MDM_HSIC_READY	EXYNOS4_GPX0(5)
+#define AP2MDM_ERRFATAL		EXYNOS4_GPX1(0)
+#define MDM2AP_ERRFATAL		EXYNOS4_GPX1(1)
+#define MDM_DUMP_INT		EXYNOS4_GPX1(2)
+
+#endif /* __MACH_GPIO_M3_H */
diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev00-naples.h b/arch/arm/mach-exynos/include/mach/gpio-rev00-naples.h
new file mode 100644
index 0000000..be3efc7
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/gpio-rev00-naples.h
@@ -0,0 +1,295 @@
+#ifndef __MACH_GPIO_NAPLES_H
+#define __MACH_GPIO_NAPLES_H __FILE__
+#include <mach/gpio.h>
+
+extern void midas_config_gpio_table(void);
+extern void midas_config_sleep_gpio_table(void);
+
+#define GPIO_eMMC_EN		EXYNOS4_GPK0(2)
+
+#define GPIO_BOOT_MODE		EXYNOS4_GPX0(3)
+
+#define GPIO_FM_I2S_CLK		EXYSNO4_GPC0(0)
+#define GPIO_FM_I2S_SYNC	EXYSNO4_GPC0(2)
+#define GPIO_FM_I2S_DI		EXYSNO4_GPC0(3)
+#define GPIO_FM_I2S_DO		EXYSNO4_GPC0(4)
+
+#define GPIO_IF_PMIC_SDA	EXYNOS4212_GPM2(0)
+#define GPIO_IF_PMIC_SCL	EXYNOS4212_GPM2(1)
+#define GPIO_PMIC_SDA		EXYNOS4_GPB(2)
+#define GPIO_PMIC_SCL		EXYNOS4_GPB(3)
+
+#define GPIO_ADC_SCL		EXYNOS4_GPY0(2)
+#define GPIO_ADC_SDA		EXYNOS4_GPY0(3)
+#define GPIO_ADC_INT		EXYNOS4_GPX2(4)
+
+#define GPIO_CAM_MCLK		EXYNOS4212_GPJ1(3)
+
+#define GPIO_5M_CAM_nSTBY	EXYNOS4212_GPM0(1)
+#define GPIO_5M_CAM_RESET	EXYNOS4_GPF1(3)
+#define GPIO_CAM_IO_EN		EXYNOS4212_GPM0(2)
+#define GPIO_ISP_CORE_EN	EXYNOS4212_GPM0(3)
+#define GPIO_CAM_AF_EN		EXYNOS4212_GPM0(4)
+#define GPIO_VT_CAM_nSTBY	EXYNOS4212_GPM0(5)
+#define GPIO_CAM_VT_nRST	EXYNOS4212_GPM1(6)
+
+#define GPIO_CAM_SDA_18V	EXYNOS4_GPD1(0)
+#define GPIO_CAM_SCL_18V	EXYNOS4_GPD1(1)
+
+#define GPIO_VT_CAM_SCL_18V	EXYNOS4212_GPM4(2)
+#define GPIO_VT_CAM_SDA_18V	EXYNOS4212_GPM4(3)
+#define GPIO_VT_CAM_ID			EXYNOS4_GPF1(2)
+
+/* Sensors & NFC*/
+#define GPIO_PS_ALS_EN		EXYNOS4212_GPJ0(5)
+#define GPIO_PS_ALS_SDA_28V	EXYNOS4_GPK1(1)
+#define GPIO_PS_ALS_SCL_28V	EXYNOS4_GPK2(2)
+#define GPIO_PS_ALS_INT		EXYNOS4_GPX0(2)
+
+#define GPIO_ACC_INT		EXYNOS4_GPX0(0)
+
+#define GPIO_GYRO_DE		EXYNOS4_GPL2(0)
+#define GPIO_GPS_nRST		EXYNOS4_GPL2(1)
+#define GPIO_GPS_PWR_EN		EXYNOS4_GPL2(2)
+
+#define GPIO_GYRO_INT		EXYNOS4_GPF0(3)
+#define GPIO_GSENSE_SDA_18V	EXYNOS4_GPD1(2)
+#define GPIO_GSENSE_SCL_18V	EXYNOS4_GPD1(3)
+
+#define GPIO_MSENSOR_INT	EXYNOS4212_GPJ0(7)
+#define GPIO_MSENSOR_SDA_18V	EXYNOS4_GPY2(4)
+#define GPIO_MSENSOR_SCL_18V	EXYNOS4_GPY2(5)
+
+#define GPIO_BENSE_SCL_18V	EXYNOS4_GPY2(3)
+#define GPIO_BSENSE_SDA_18V	EXYNOS4_GPY2(2)
+#define GPIO_BARO_INT		EXYNOS4_GPF0(5)
+
+#define GPIO_TF_EN		EXYNOS4_GPY2(0)
+#define GPIO_NFC_SCL_18V	EXYNOS4_GPB(5)
+#define GPIO_NFC_SDA_18V	EXYNOS4_GPB(4)
+#define GPIO_NFC_SCL_18V_00	EXYNOS4_GPB(3)
+#define GPIO_NFC_SDA_18V_00	EXYNOS4_GPB(2)
+#define GPIO_NFC_IRQ		EXYNOS4_GPX1(7)
+#define GPIO_NFC_EN		EXYNOS4_GPL2(6)
+#define GPIO_NFC_FIRMWARE	EXYNOS4_GPL2(7)
+#define GPIO_NFC_CLK_REQ	EXYNOS4212_GPM0(0)
+/* Sensors & NFC*/
+
+#define GPIO_DET_35		EXYNOS4_GPX0(1)
+
+#define GPIO_MIC_BIAS_EN	EXYNOS4_GPF1(7)
+#define GPIO_MIC_BIAS_EN_00		EXYNOS4_GPF1(7)
+#define GPIO_SUB_MIC_BIAS_EN	EXYNOS4_GPF2(0)
+#define GPIO_SUB_MIC_BIAS_EN_00	EXYNOS4_GPF2(0)
+#define GPIO_EAR_MIC_BIAS_EN_00	EXYNOS4212_GPJ0(2)
+
+#define GPIO_PMU_RST		EXYNOS4_GPX3(2)
+
+#define GPIO_PMIC_IRQ		EXYNOS4_GPX0(7)
+#define GPIO_IF_PMIC_IRQ	EXYNOS4_GPX1(5)
+
+#define GPIO_TSP_INT		EXYNOS4212_GPM2(3)
+#define GPIO_TSP_SDA_18V	EXYNOS4_GPA1(2)
+#define GPIO_TSP_SCL_18V	EXYNOS4_GPA1(3)
+
+#define GPIO_BT_EN		EXYNOS4_GPL0(6)
+#define GPIO_BT_WAKE		EXYNOS4_GPX3(1)
+#define GPIO_BT_HOST_WAKE	EXYNOS4_GPX2(6)
+#define IRQ_BT_HOST_WAKE	IRQ_EINT(22)
+
+#define GPIO_BT_RXD		EXYNOS4_GPA0(0)
+#define GPIO_BT_RXD_AF		2
+
+#define GPIO_BT_TXD		EXYNOS4_GPA0(1)
+#define GPIO_BT_TXD_AF		2
+
+#define GPIO_BT_CTS		EXYNOS4_GPA0(2)
+#define GPIO_BT_CTS_AF		2
+
+#define GPIO_BT_RTS		EXYNOS4_GPA0(3)
+#define GPIO_BT_RTS_AF		2
+
+#define GPIO_GPS_RXD		EXYNOS4_GPA0(4)
+#define GPIO_GPS_RXD_AF		2
+
+#define GPIO_GPS_TXD		EXYNOS4_GPA0(5)
+#define GPIO_GPS_TXD_AF		2
+
+#define GPIO_GPS_CTS		EXYNOS4_GPA0(6)
+#define GPIO_GPS_CTS_AF		2
+
+#define GPIO_GPS_RTS		EXYNOS4_GPA0(7)
+#define GPIO_GPS_RTS_AF		2
+
+#define GPIO_FLM_RXD		EXYNOS4_GPA1(4)
+#define GPIO_FLM_RXD_AF		2
+
+#define GPIO_FLM_TXD		EXYNOS4_GPA1(5)
+#define GPIO_FLM_TXD_AF		2
+
+#define GPIO_3_TOUCH_SCL	EXYNOS4_GPL0(1)
+#define GPIO_3_TOUCH_SDA	EXYNOS4_GPL0(2)
+#define GPIO_HDMI_EN		EXYNOS4_GPL0(4)
+#define GPIO_3_TOUCH_INT	EXYNOS4212_GPJ1(0)
+#define GPIO_TOUCH_EN		EXYNOS4212_GPJ0(3)
+
+#define GPIO_PWM0		EXYNOS4_GPD0(0)
+#define GPIO_PWM1		EXYNOS4_GPD0(1)
+#define GPIO_PWM2		EXYNOS4_GPD0(2)
+#define GPIO_PWM3		EXYNOS4_GPD0(3)
+
+#define GPIO_VIBTONE_EN		EXYNOS4212_GPJ0(6)
+
+#define GPIO_WLAN_EN		EXYNOS4212_GPJ0(0)
+#define GPIO_WLAN_EN_AF		1
+#define GPIO_WLAN_HOST_WAKE	EXYNOS4_GPX2(5)
+#define GPIO_WLAN_HOST_WAKE_AF	0xF
+#define GPIO_WLAN_SDIO_CLK	EXYNOS4_GPK3(0)
+#define GPIO_WLAN_SDIO_CLK_AF	2
+#define GPIO_WLAN_SDIO_CMD	EXYNOS4_GPK3(1)
+#define GPIO_WLAN_SDIO_CMD_AF	2
+#define GPIO_WLAN_SDIO_D0	EXYNOS4_GPK3(3)
+#define GPIO_WLAN_SDIO_D0_AF	2
+#define GPIO_WLAN_SDIO_D1	EXYNOS4_GPK3(4)
+#define GPIO_WLAN_SDIO_D1_AF	2
+#define GPIO_WLAN_SDIO_D2	EXYNOS4_GPK3(5)
+#define GPIO_WLAN_SDIO_D2_AF	2
+#define GPIO_WLAN_SDIO_D3	EXYNOS4_GPK3(6)
+#define GPIO_WLAN_SDIO_D3_AF	2
+
+#define GPIO_USB_SEL		EXYNOS4212_GPJ0(1)
+
+#define GPIO_LCD_22V_EN		EXYNOS4212_GPM4(4)
+#define GPIO_LCD_22V_EN_00		EXYNOS4_GPC0(1)
+
+#define GPIO_ISP_TXD		EXYNOS4212_GPM4(5)
+#define GPIO_ISP_RXD		EXYNOS4212_GPM4(6)
+
+#define GPIO_TA_EN		EXYNOS4_GPL2(2)
+
+#define GPIO_MHL_SEL		EXYNOS4_GPL0(3)
+
+#define GPIO_MHL_SDA_1_8V	EXYNOS4_GPF0(4)
+#define GPIO_MHL_SCL_1_8V	EXYNOS4_GPF0(6)
+#define GPIO_MHL_SDA_1_8V_00	EXYNOS4_GPB(2)
+#define GPIO_MHL_SCL_1_8V_00	EXYNOS4_GPB(3)
+
+#define GPIO_OTG_EN		EXYNOS4_GPF0(7)
+
+#define GPIO_OLED_ID		EXYNOS4_GPF1(0)
+#define GPIO_ISP_RESET		EXYNOS4_GPF1(3)
+#define GPIO_FUEL_SCL		EXYNOS4_GPF1(4)
+#define GPIO_FUEL_SDA		EXYNOS4_GPF1(5)
+
+#define GPIO_MLCD_RST		EXYNOS4_GPF2(1)
+#define GPIO_UART_SEL		EXYNOS4_GPF2(3)
+#define GPIO_S_LED_I2C_SCL	EXYNOS4_GPF2(6)
+#define GPIO_S_LED_I2C_SDA	EXYNOS4_GPF2(7)
+#define GPIO_OLED_DET		EXYNOS4_GPF3(0)
+
+#define GPIO_PMIC_DVS1		EXYNOS4212_GPM3(0)
+#define GPIO_PMIC_DVS2		EXYNOS4212_GPM3(1)
+
+/* Definitions for Sii 9244B0 */
+#define GPIO_PMIC_DVS3		EXYNOS4212_GPM3(2)
+#define GPIO_BUCK2_SEL		EXYNOS4_GPF3(1)
+#define GPIO_BUCK3_SEL		EXYNOS4_GPF3(2)
+#define GPIO_BUCK4_SEL		EXYNOS4_GPF3(3)
+#define GPIO_MHL_RST		EXYNOS4_GPF3(4)
+#define GPIO_MHL_INT		EXYNOS4_GPF3(5)
+#define GPIO_MHL_INT_AF		S3C_GPIO_SFN(0xF)
+#define GPIO_MHL_WAKE_UP	EXYNOS4212_GPJ1(4)
+
+#define GPIO_RGB_SDA_1_8V	EXYNOS4_GPF0(0)
+#define GPIO_RGB_SCL_1_8V	EXYNOS4_GPF0(1)
+#define GPIO_RGB_INT		EXYNOS4_GPX2(2)
+#define GPIO_VOL_UP		EXYNOS4_GPX2(2)
+#define GPIO_VOL_DOWN		EXYNOS4_GPX3(3)
+#define GPIO_VOL_UP_00		EXYNOS4_GPX2(2)
+#define GPIO_VOL_DOWN_00	EXYNOS4_GPX3(3)
+
+#define GPIO_CAM_SW_EN		EXYNOS4212_GPJ1(0)
+#define GPIO_TORCH_EN		EXYNOS4212_GPJ1(1)
+#define GPIO_TORCH_SET		EXYNOS4212_GPJ1(2)
+
+#define GPIO_MHL_DSCL_2_8V	EXYNOS4_GPK1(0)
+#define GPIO_MHL_DSDA_2_8V	EXYNOS4_GPK1(2)
+
+#define MHL_INT_IRQ		gpio_to_irq(GPIO_MHL_INT)
+#define MHL_WAKEUP_IRQ		gpio_to_irq(GPIO_MHL_WAKE_UP)
+
+#define GPIO_HDMI_CEC		EXYNOS4_GPX3(6)
+#define GPIO_HDMI_HPD		EXYNOS4_GPX3(7)
+
+#define GPIO_nPOWER		EXYNOS4_GPX2(7)
+#define GPIO_OK_KEY		EXYNOS4_GPX2(0)
+
+#define GPIO_FUEL_ALERT		EXYNOS4_GPX2(3)
+
+#define GPIO_WPC_INT		EXYNOS4_GPX3(0)
+
+#define GPIO_VIBTONE_PWM	EXYNOS4_GPD0(1)
+
+#define GPIO_VIBTONE_PWM	EXYNOS4_GPD0(1)
+
+#define GPIO_CODEC_SDA_18V	EXYNOS4_GPD0(2)
+#define GPIO_CODEC_SCL_18V	EXYNOS4_GPD0(3)
+#define GPIO_CODEC_SDA_18V_00		EXYNOS4_GPB(0)
+#define GPIO_CODEC_SCL_18V_00		EXYNOS4_GPB(1)
+
+
+#define GPIO_CODEC_LDO_EN	EXYNOS4212_GPJ0(4)
+
+#define GPIO_WM8994_LDO		EXYNOS4212_GPJ0(4)
+
+/* Modem Interface GPIOs - M0 HSIC */
+#if !defined(CONFIG_SEC_MODEM_M0_TD)
+#define GPIO_ACTIVE_STATE	EXYNOS4_GPF1(1)
+#define GPIO_PDA_ACTIVE		EXYNOS4_GPF1(6)
+#define GPIO_PHONE_ON		EXYNOS4_GPL2(5)
+#define GPIO_SUSPEND_REQUEST	EXYNOS4212_GPM2(4)
+#define GPIO_CP_REQ_RESET	EXYNOS4212_GPM3(3)
+#define GPIO_GPS_CNTL		EXYNOS4212_GPM3(4)
+#define GPIO_IPC_SLAVE_WAKEUP	EXYNOS4_GPX1(0)
+#define GPIO_IPC_HOST_WAKEUP	EXYNOS4_GPX1(1)
+#define GPIO_CP_DUMP_INT	EXYNOS4_GPX1(2)
+#define GPIO_PHONE_ACTIVE	EXYNOS4_GPX1(6)
+#define GPIO_CP_RST		EXYNOS4_GPX3(2)
+
+#define GPIO_FM_RST EXYNOS4_GPC1(1)
+#else
+
+/* Modem Interface GPIOs - M0 SPI */
+#define GPIO_PDA_ACTIVE	EXYNOS4_GPF1(6)
+#define GPIO_PHONE_ON	EXYNOS4_GPL2(5)
+#define GPIO_PHONE_ACTIVE	EXYNOS4_GPX1(6)
+#define GPIO_AP_CP_INT1	EXYNOS4_GPX0(5)
+#define GPIO_AP_CP_INT2	EXYNOS4_GPX3(5)
+#define GPIO_CP_DUMP_INT	EXYNOS4_GPX1(2)
+#define GPIO_IPC_MRDY	EXYNOS4_GPX0(4)
+#define GPIO_IPC_SRDY	EXYNOS4_GPX1(0)
+#define GPIO_IPC_SUB_MRDY	EXYNOS4_GPX3(2)
+#define GPIO_IPC_SUB_SRDY	EXYNOS4_GPX1(1)
+
+#define GPIO_CP_RST	EXYNOS4_GPF1(1)
+#define GPIO_CP_REQ_RESET	EXYNOS4_GPF1(1)
+#define GPIO_IPC_SLAVE_WAKEUP	EXYNOS4_GPX2(0)
+#define GPIO_IPC_HOST_WAKEUP	EXYNOS4_GPX2(0)
+#define GPIO_SUSPEND_REQUEST	EXYNOS4_GPF1(1)
+#define GPIO_ISP_INT		EXYNOS4_GPF1(1)
+#define GPIO_ACTIVE_STATE	EXYNOS4_GPF1(1)
+
+#define GPIO_FM_RST	EXYNOS4_GPC1(0)
+
+#define IRQ_IPC_SRDY		IRQ_EINT8
+#define IRQ_PHONE_ACTIVE	IRQ_EINT14
+#define IRQ_IPC_SRDY		IRQ_EINT8
+#define IRQ_IPC_SUB_SRDY	IRQ_EINT9
+#define IRQ_CP_DUMP_INT	IRQ_EINT10
+#endif
+
+#define GPIO_FM_INT_REV07	EXYNOS4_GPX1(3)
+#define GPIO_FM_RST	EXYNOS4_GPC1(1)
+#define GPIO_FM_INT	EXYNOS4_GPX1(3)
+
+#endif /* __MACH_GPIO_NAPLES_H */
diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev00-p10-lte.h b/arch/arm/mach-exynos/include/mach/gpio-rev00-p10-lte.h
new file mode 100644
index 0000000..9ceb31c
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/gpio-rev00-p10-lte.h
@@ -0,0 +1,376 @@
+#ifndef __MACH_GPIO_P10_H
+#define __MACH_GPIO_P10 __FILE__
+
+#include <mach/gpio.h>
+
+extern void p10_config_gpio_table(void);
+extern void p10_config_sleep_gpio_table(void);
+
+/**
+ * Main GPIO function mapping.
+ */
+#define	GPIO_5M_CAM_SCL_18V	EXYNOS5_GPF0(1)
+#define	GPIO_5M_CAM_SDA_18V	EXYNOS5_GPF0(0)
+#define	GPIO_5M_CORE_EN		EXYNOS5_GPV0(2)
+#define	GPIO_5M_SPI_CLK		EXYNOS5_GPA2(4)
+#define	GPIO_5M_SPI_CS		EXYNOS5_GPA2(5)
+#define	GPIO_5M_SPI_DI		EXYNOS5_GPA2(6)
+#define	GPIO_5M_SPI_DO		EXYNOS5_GPA2(7)
+
+#define	GPIO_ACC_INT		EXYNOS5_GPX1(4)
+
+#define	GPIO_ACCESSORY_CHECK	EXYNOS5_GPE0(4)
+#define	GPIO_ACCESSORY_EN	EXYNOS5_GPH1(5)
+#define	GPIO_ACCESSORY_INT	EXYNOS5_GPX3(2)
+
+#define	GPIO_ADC_INT		EXYNOS5_GPX2(4)
+#define	GPIO_ADC_SCL_18V	EXYNOS5_GPV3(0)
+#define	GPIO_ADC_SDA_18V	EXYNOS5_GPV3(1)
+
+#define	GPIO_ALS_nRST		EXYNOS5_GPH1(2)
+#define	GPIO_ALS_SCL_18V	EXYNOS5_GPG0(1)
+#define	GPIO_ALS_SDA_18V	EXYNOS5_GPG0(0)
+
+#define	GPIO_AP_CP_INT		EXYNOS5_GPB0(0)
+#define	GPIO_AP_CPU_PWR_DN	EXYNOS5_GPX1(5)
+#define	GPIO_AP_PMIC_IRQ	EXYNOS5_GPX0(2)
+#define	GPIO_AP_PMIC_SCL	EXYNOS5_GPA2(3)
+#define	GPIO_AP_PMIC_SDA	EXYNOS5_GPA2(2)
+#define	GPIO_AP_RXD		EXYNOS5_GPA1(0)
+#define	GPIO_AP_TXD		EXYNOS5_GPA1(1)
+
+#define	GPIO_AP2CMC_INT1_18V	EXYNOS5_GPX0(6)
+#define	GPIO_AP2CMC_INT2_18V	EXYNOS5_GPX1(1)
+#define	GPIO_AP2CMC_INT3_18V	EXYNOS5_GPX1(2)
+
+#define	GPIO_AUTO_DFS		EXYNOS5_GPZ(1)
+
+#define	GPIO_BARO_INT		EXYNOS5_GPB1(0)
+
+#define	GPIO_BSENSE_SCL_18V	EXYNOS5_GPD0(3)
+#define	GPIO_BSENSE_SDA_18V	EXYNOS5_GPD0(2)
+
+#define	GPIO_BT_HOST_WAKE	EXYNOS5_GPX2(6)
+#define	GPIO_BT_UART_CTS	EXYNOS5_GPA0(2)
+#define	GPIO_BT_UART_RTS	EXYNOS5_GPA0(3)
+#define	GPIO_BT_UART_RXD	EXYNOS5_GPA0(0)
+#define	GPIO_BT_UART_TXD	EXYNOS5_GPA0(1)
+#define	GPIO_BT_WAKE		EXYNOS5_GPH1(3)
+
+#define	GPIO_BTREG_ON		EXYNOS5_GPH0(0)
+#define   IRQ_BT_HOST_WAKE	IRQ_EINT(22)
+
+#define	GPIO_BUCK2_SEL		EXYNOS5_GPV0(4)
+
+#define	GPIO_BUCK3_SEL		EXYNOS5_GPV0(1)
+
+#define	GPIO_BUCK4_SEL		EXYNOS5_GPV0(0)
+
+#define	GPIO_CAM_FLASH_EN_T	EXYNOS5_GPG1(0)
+#define	GPIO_CAM_FLASH_SET_T	EXYNOS5_GPG1(1)
+#define	GPIO_CAM_IO_EN		EXYNOS5_GPV0(3)
+#define	GPIO_CAM_MCLK		EXYNOS5_GPH0(3)
+#define	GPIO_CAM_VT_nRST	EXYNOS5_GPG1(6)
+
+#define	GPIO_CHG_SCL_18V	EXYNOS5_GPE0(2)
+#define	GPIO_CHG_SDA_18V	EXYNOS5_GPE0(1)
+
+#define	GPIO_CIS_nRST		EXYNOS5_GPE0(0)
+
+#define	GPIO_CMC_PMIC_PWRON	EXYNOS5_GPD1(5)
+#define	GPIO_CMC_SPI_CLK_ACK	EXYNOS5_GPX1(3)
+#define	GPIO_CMC_SPI_CLK_REQ	EXYNOS5_GPB0(2)
+#define	GPIO_CMC_USB_DETECT	EXYNOS5_GPH1(0)
+
+#define	GPIO_CMC221_CPU_RST	EXYNOS5_GPB0(1)
+
+#define	GPIO_CMC2AP_INT1_18V	EXYNOS5_GPX0(3)
+#define	GPIO_CMC2AP_INT2_18V	EXYNOS5_GPX1(0)
+
+#define	GPIO_WM8994_LDO		EXYNOS5_GPH1(1)
+#define	GPIO_CODEC_SCL_18V	EXYNOS5_GPB2(3)
+#define	GPIO_CODEC_SDA_18V	EXYNOS5_GPB2(2)
+
+#define	GPIO_DET_35		EXYNOS5_GPX0(1)
+
+#define	GPIO_DOCK_INT		EXYNOS5_GPX3(0)
+
+#define	GPIO_DP_HPD		EXYNOS5_GPX0(7)
+
+#define	GPIO_DPRAM_A0		EXYNOS5_GPY3(0)
+#define	GPIO_DPRAM_A1		EXYNOS5_GPY3(1)
+#define	GPIO_DPRAM_A2		EXYNOS5_GPY3(2)
+#define	GPIO_DPRAM_A3		EXYNOS5_GPY3(3)
+#define	GPIO_DPRAM_A4		EXYNOS5_GPY3(4)
+#define	GPIO_DPRAM_A5		EXYNOS5_GPY3(5)
+#define	GPIO_DPRAM_A6		EXYNOS5_GPY3(6)
+#define	GPIO_DPRAM_A7		EXYNOS5_GPY3(7)
+#define	GPIO_DPRAM_A8		EXYNOS5_GPY4(0)
+#define	GPIO_DPRAM_A9		EXYNOS5_GPY4(1)
+#define	GPIO_DPRAM_A10		EXYNOS5_GPY4(2)
+#define	GPIO_DPRAM_A11		EXYNOS5_GPY4(3)
+#define	GPIO_DPRAM_A12		EXYNOS5_GPY4(4)
+#define	GPIO_DPRAM_A13		EXYNOS5_GPY4(5)
+#define	GPIO_DPRAM_CSN		EXYNOS5_GPY0(0)
+#define	GPIO_DPRAM_D0		EXYNOS5_GPY5(0)
+#define	GPIO_DPRAM_D1		EXYNOS5_GPY5(1)
+#define	GPIO_DPRAM_D2		EXYNOS5_GPY5(2)
+#define	GPIO_DPRAM_D3		EXYNOS5_GPY5(3)
+#define	GPIO_DPRAM_D4		EXYNOS5_GPY5(4)
+#define	GPIO_DPRAM_D5		EXYNOS5_GPY5(5)
+#define	GPIO_DPRAM_D6		EXYNOS5_GPY5(6)
+#define	GPIO_DPRAM_D7		EXYNOS5_GPY5(7)
+#define	GPIO_DPRAM_D8		EXYNOS5_GPY6(0)
+#define	GPIO_DPRAM_D9		EXYNOS5_GPY6(1)
+#define	GPIO_DPRAM_D10		EXYNOS5_GPY6(2)
+#define	GPIO_DPRAM_D11		EXYNOS5_GPY6(3)
+#define	GPIO_DPRAM_D12		EXYNOS5_GPY6(4)
+#define	GPIO_DPRAM_D13		EXYNOS5_GPY6(5)
+#define	GPIO_DPRAM_D14		EXYNOS5_GPY6(6)
+#define	GPIO_DPRAM_D15		EXYNOS5_GPY6(7)
+#define	GPIO_DPRAM_INT		EXYNOS5_GPX0(5)
+#define	GPIO_DPRAM_REN		EXYNOS5_GPY0(4)
+#define	GPIO_DPRAM_WEN		EXYNOS5_GPY0(5)
+
+#define	GPIO_EAR_SEND_END	EXYNOS5_GPX3(6)
+
+#define	GPIO_eMMC_EN		EXYNOS5_GPC0(2)
+
+#define	GPIO_FM34_BYPASS	EXYNOS5_GPH1(4)
+#define	GPIO_FM34_PWDN		EXYNOS5_GPG0(3)
+#define	GPIO_FM34_RESET		EXYNOS5_GPG0(4)
+#define	GPIO_FM34_SCL_18V	EXYNOS5_GPA2(1)
+#define	GPIO_FM34_SDA_18V	EXYNOS5_GPA2(0)
+
+#define	GPIO_ES305_WAKEUP	EXYNOS5_GPG0(3)
+#define	GPIO_ES305_RESET	EXYNOS5_GPG0(4)
+
+#define	GPIO_FUEL_ALERT		EXYNOS5_GPX2(3)
+#define	GPIO_FUEL_SCL_18V	EXYNOS5_GPD0(1)
+#define	GPIO_FUEL_SDA_18V	EXYNOS5_GPD0(0)
+
+#define	GPIO_GPS_PWR_EN		EXYNOS5_GPE1(0)
+#define	GPIO_GPS_nRST		EXYNOS5_GPE0(6)
+#define	GPIO_GPS_CTS		EXYNOS5_GPA0(6)
+#define	GPIO_GPS_RTS		EXYNOS5_GPA0(7)
+#define	GPIO_GPS_RXD		EXYNOS5_GPA0(4)
+#define	GPIO_GPS_TXD		EXYNOS5_GPA0(5)
+
+#define	GPIO_GPS_CTS_AF		2
+#define	GPIO_GPS_RTS_AF		2
+#define	GPIO_GPS_RXD_AF		2
+#define	GPIO_GPS_TXD_AF		2
+
+#define	GPIO_GSENSE_SCL_18V	EXYNOS5_GPB3(3)
+#define	GPIO_GSENSE_SDA_18V	EXYNOS5_GPB3(2)
+
+#define	GPIO_HDMI_EN		EXYNOS5_GPC1(2)
+#define	GPIO_HDMI_HPD		EXYNOS5_GPX3(7)
+
+#define	GPIO_HUM_SCL_18V	EXYNOS5_GPV2(4)
+#define	GPIO_HUM_SDA_18V	EXYNOS5_GPV2(5)
+
+#define	GPIO_HW_REV0		EXYNOS5_GPV1(4)
+#define	GPIO_HW_REV1		EXYNOS5_GPV1(3)
+#define	GPIO_HW_REV2		EXYNOS5_GPV1(2)
+#define	GPIO_HW_REV3		EXYNOS5_GPV1(1)
+
+#define	GPIO_IPC_RXD		EXYNOS5_GPA1(4)
+#define	GPIO_IPC_TXD		EXYNOS5_GPA1(5)
+
+#define	GPIO_ISP_RXD		EXYNOS5_GPE1(1)
+#define	GPIO_ISP_STANDBY	EXYNOS5_GPG1(7)
+#define	GPIO_ISP_TXD		EXYNOS5_GPE0(7)
+
+#define	GPIO_LCD_EN		EXYNOS5_GPH1(7)
+#define	GPIO_LCD_ID		EXYNOS5_GPD1(4)
+#define	GPIO_LCD_PWM_IN_18V	EXYNOS5_GPB2(0)
+
+#define	GPIO_LCDP_SCL__18V	EXYNOS5_GPD0(6)
+#define	GPIO_LCDP_SDA__18V	EXYNOS5_GPD0(7)
+
+#define	GPIO_LED_BACKLIGHT_RESET	EXYNOS5_GPG0(5)
+
+#define	GPIO_LTE_ACTIVE		EXYNOS5_GPX1(6)
+
+#define	GPIO_MHL_DSCL_18V	EXYNOS5_GPB3(1)
+#define	GPIO_MHL_DSDA_18V	EXYNOS5_GPB3(0)
+#define	GPIO_MHL_INT		EXYNOS5_GPG0(6)
+#define	GPIO_MHL_RST		EXYNOS5_GPG0(7)
+#define	GPIO_MHL_SCL_18V	EXYNOS5_GPD0(5)
+#define	GPIO_MHL_SDA_18V	EXYNOS5_GPD0(4)
+
+#define	GPIO_MM_I2S_CLK		EXYNOS5_GPZ(0)
+#define	GPIO_MM_I2S_DI		EXYNOS5_GPZ(3)
+#define	GPIO_MM_I2S_DO		EXYNOS5_GPZ(4)
+#define	GPIO_MM_I2S_SYNC	EXYNOS5_GPZ(2)
+
+#define	GPIO_MOTOR_EN		EXYNOS5_GPD1(6)
+#define	GPIO_MOTOR_PWM		EXYNOS5_GPB2(1)
+#define	GPIO_MOTOR_SCL_18V	EXYNOS5_GPD1(3)
+#define	GPIO_MOTOR_SDA_18V	EXYNOS5_GPD1(2)
+
+#define	GPIO_MSENSE_RDY		EXYNOS5_GPX2(2)
+#define	GPIO_MSENSE_RST		EXYNOS5_GPG2(0)
+#define	GPIO_MSENSE_SDA		EXYNOS5_GPV2(7)
+#define	GPIO_MSENSE_SCL		EXYNOS5_GPV2(6)
+
+#define	GPIO_PS_ALS_SDA		EXYNOS5_GPG0(0)
+#define	GPIO_PS_ALS_SCL		EXYNOS5_GPG0(1)
+#define	GPIO_PS_VOUT		EXYNOS5_GPH1(2)
+#define	GPIO_HUM_SDA		EXYNOS5_GPV2(5)
+#define	GPIO_HUM_SCL		EXYNOS5_GPV2(4)
+
+
+#define	GPIO_M_SDA		EXYNOS5_GPB1(3)
+
+#define	GPIO_NAND_CLK		EXYNOS5_GPC0(0)
+#define	GPIO_NAND_CMD		EXYNOS5_GPC0(1)
+#define	GPIO_NAND_D0		EXYNOS5_GPC0(3)
+#define	GPIO_NAND_D1		EXYNOS5_GPC0(4)
+#define	GPIO_NAND_D2		EXYNOS5_GPC0(5)
+#define	GPIO_NAND_D3		EXYNOS5_GPC0(6)
+#define	GPIO_NAND_D4		EXYNOS5_GPC1(3)
+#define	GPIO_NAND_D5		EXYNOS5_GPC1(4)
+#define	GPIO_NAND_D6		EXYNOS5_GPC1(5)
+#define	GPIO_NAND_D7		EXYNOS5_GPC1(6)
+
+#define	GPIO_nPOWER		EXYNOS5_GPX2(7)
+
+#define	GPIO_OTG_EN		EXYNOS5_GPC3(2)
+
+#define	GPIO_PDA_ACTIVE		EXYNOS5_GPE0(3)
+
+#define	GPIO_PMIC_DVS1		EXYNOS5_GPV0(7)
+#define	GPIO_PMIC_DVS2		EXYNOS5_GPV0(6)
+#define	GPIO_PMIC_DVS3		EXYNOS5_GPV0(5)
+
+#define	GPIO_REMOTE_SENSE_IRQ	EXYNOS5_GPX3(1)
+
+#define	GPIO_SIM_DETECT		EXYNOS5_GPX3(3)
+
+#define	GPIO_T_FLASH_CLK	EXYNOS5_GPC2(0)
+#define	GPIO_T_FLASH_CMD	EXYNOS5_GPC2(1)
+#define	GPIO_T_FLASH_D0		EXYNOS5_GPC2(3)
+#define	GPIO_T_FLASH_D1		EXYNOS5_GPC2(4)
+#define	GPIO_T_FLASH_D2		EXYNOS5_GPC2(5)
+#define	GPIO_T_FLASH_D3		EXYNOS5_GPC2(6)
+#define	GPIO_T_FLASH_DETECT	EXYNOS5_GPX3(4)
+
+#define	GPIO_TA_EN		EXYNOS5_GPG1(5)
+#define	GPIO_TA_nCONNECTED	EXYNOS5_GPX0(0)
+#define	GPIO_TA_nCHG		EXYNOS5_GPG1(4)
+
+#define	GPIO_TF_EN		EXYNOS5_GPY2(0)
+
+#define	GPIO_TOUCH_CHG		EXYNOS5_GPG1(2)
+#define	GPIO_TOUCH_RESET	EXYNOS5_GPG1(3)
+
+#define	GPIO_TP400		EXYNOS5_GPH0(2)
+
+#define	GPIO_TP405		EXYNOS5_GPX0(4)
+
+#define	GPIO_TP406		EXYNOS5_GPX3(5)
+
+#define	GPIO_TP411		EXYNOS5_GPG0(2)
+
+#define	GPIO_TSP_SCL_18V	EXYNOS5_GPA1(3)
+#define	GPIO_TSP_SDA_18V	EXYNOS5_GPA1(2)
+
+#define	GPIO_UART_SEL		EXYNOS5_GPE0(5)
+
+#define	GPIO_USB_SEL1		EXYNOS5_GPH0(1)
+
+#define	GPIO_USB30_EN		EXYNOS5_GPC2(2)
+
+#define	GPIO_VOL_DOWN		EXYNOS5_GPX2(1)
+#define	GPIO_VOL_UP		EXYNOS5_GPX2(0)
+
+#define	GPIO_VT_CAM_SCL_18V	EXYNOS5_GPF0(3)
+#define	GPIO_VT_CAM_SDA_18V	EXYNOS5_GPF0(2)
+
+#define	GPIO_VTCAM_MCLK		EXYNOS5_GPG2(1)
+
+#define GPIO_WLAN_EN            EXYNOS5_GPV1(0)
+#define GPIO_WLAN_EN_AF         1
+#define GPIO_WLAN_HOST_WAKE     EXYNOS5_GPX2(5)
+#define GPIO_WLAN_HOST_WAKE_AF  0xF
+#define GPIO_WLAN_SDIO_CLK      EXYNOS5_GPC3(0)
+#define GPIO_WLAN_SDIO_CLK_AF   2
+#define GPIO_WLAN_SDIO_CMD      EXYNOS5_GPC3(1)
+#define GPIO_WLAN_SDIO_CMD_AF   2
+#define GPIO_WLAN_SDIO_D0       EXYNOS5_GPC3(3)
+#define GPIO_WLAN_SDIO_D0_AF    2
+#define GPIO_WLAN_SDIO_D1       EXYNOS5_GPC3(4)
+#define GPIO_WLAN_SDIO_D1_AF    2
+#define GPIO_WLAN_SDIO_D2       EXYNOS5_GPC3(5)
+#define GPIO_WLAN_SDIO_D2_AF    2
+#define GPIO_WLAN_SDIO_D3       EXYNOS5_GPC3(6)
+#define GPIO_WLAN_SDIO_D3_AF    2
+
+/**
+ *  Mapping for Func0.
+ */
+#define	GPIO_I2C_0_SDA		EXYNOS5_GPB3(0)
+#define	GPIO_I2C_1_SDA		EXYNOS5_GPB3(2)
+
+/**
+ *  Mapping for Func1.
+ */
+#define	GPIO_I2C_2_SDA		EXYNOS5_GPA0(6)
+#define	GPIO_I2C_3_SDA		EXYNOS5_GPA1(2)
+#define	GPIO_I2C_4_SDA		EXYNOS5_GPA2(0)
+#define	GPIO_I2C_5_SDA		EXYNOS5_GPA2(2)
+#define	GPIO_I2C_7_SDA		EXYNOS5_GPB2(2)
+
+#define	GPIO_PCM_0_SCLK		EXYNOS5_GPZ(0)
+#define	GPIO_PCM_1_SCLK		EXYNOS5_GPB0(0)
+#define	GPIO_PCM_2_SCLK		EXYNOS5_GPB1(0)
+
+/**
+ *  Mapping for Func2.
+ */
+#define	GPIO_I2C_6_SDA		EXYNOS5_GPB1(3)
+
+/**
+ *  Remappig for downward compatibility.
+ */
+#define	GPIO_PMIC_IRQ		GPIO_AP_PMIC_IRQ
+#define	GPIO_HDMI_CEC		GPIO_EAR_SEND_END
+
+/* Definitions for DPRAM */
+#define GPIO_DPRAM_CSN		EXYNOS5_GPY0(0)
+#define GPIO_DPRAM_CSN0		EXYNOS5_GPY0(0)
+#define GPIO_DPRAM_CSN1		EXYNOS5_GPY0(1)
+#define GPIO_DPRAM_CSN2		EXYNOS5_GPY0(2)
+#define GPIO_DPRAM_CSN3		EXYNOS5_GPY0(3)
+#define GPIO_DPRAM_REN		EXYNOS5_GPY0(4)
+#define GPIO_DPRAM_WEN		EXYNOS5_GPY0(5)
+/* #define GPIO_DPRAM_LBN		EXYNOS4_GPY1(0) // for via modem */
+/* #define GPIO_DPRAM_UBN		EXYNOS4_GPY1(1) // for via modem */
+#define GPIO_SROM_ADDR_BUS_LOW	EXYNOS5_GPY3(0)
+#define GPIO_SROM_ADDR_BUS_HIGH	EXYNOS5_GPY4(0)
+#define GPIO_SROM_DATA_BUS_LOW	EXYNOS5_GPY5(0)
+#define GPIO_SROM_DATA_BUS_HIGH	EXYNOS5_GPY6(0)
+
+/* Definitions for CMC221 */
+#define CP_CMC221_PMIC_PWRON	EXYNOS5_GPD1(5)
+#define CP_CMC221_CPU_RST	EXYNOS5_GPB0(1)
+#define GPIO_LTE_ACTIVE		EXYNOS5_GPX1(6)
+#define LTE_ACTIVE_IRQ		IRQ_EINT(14)	/* IRQ of GPX1[6] */
+
+#define GPIO_CMC_IDPRAM_INT_00	EXYNOS5_GPX0(5)
+#define CMC_IDPRAM_INT_IRQ_00	IRQ_EINT(5)	/* IRQ of GPX0[5] */
+
+#define GPIO_CMC_IDPRAM_STATUS	EXYNOS5_GPX0(3) /* CMC2AP_INT_1 */
+#define GPIO_CMC_IDPRAM_WAKEUP	EXYNOS5_GPX1(2) /* AP2CMC_INT_3 */
+/* #define GPIO_ACTIVE_STATE	EXYNOS4_GPF1(1) // for USB */
+#define GPIO_IPC_SLAVE_WAKEUP	EXYNOS5_GPX0(6) /* AP2CMC_INT_1 */
+#define GPIO_IPC_HOST_WAKEUP	EXYNOS5_GPX1(0) /* CMC2AP_INT_2 */
+
+#define	GPIO_CMC_CLK_18V	EXYNOS5_GPF1(0)
+#define	GPIO_CMC_CS_18V		EXYNOS5_GPF1(1)
+
+#define	GPIO_5M_nRST		EXYNOS5_GPE0(0)
+
+#endif /* __MACH_GPIO_P10_H */
diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev00-p10-wifi.h b/arch/arm/mach-exynos/include/mach/gpio-rev00-p10-wifi.h
new file mode 100644
index 0000000..9ceb31c
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/gpio-rev00-p10-wifi.h
@@ -0,0 +1,376 @@
+#ifndef __MACH_GPIO_P10_H
+#define __MACH_GPIO_P10 __FILE__
+
+#include <mach/gpio.h>
+
+extern void p10_config_gpio_table(void);
+extern void p10_config_sleep_gpio_table(void);
+
+/**
+ * Main GPIO function mapping.
+ */
+#define	GPIO_5M_CAM_SCL_18V	EXYNOS5_GPF0(1)
+#define	GPIO_5M_CAM_SDA_18V	EXYNOS5_GPF0(0)
+#define	GPIO_5M_CORE_EN		EXYNOS5_GPV0(2)
+#define	GPIO_5M_SPI_CLK		EXYNOS5_GPA2(4)
+#define	GPIO_5M_SPI_CS		EXYNOS5_GPA2(5)
+#define	GPIO_5M_SPI_DI		EXYNOS5_GPA2(6)
+#define	GPIO_5M_SPI_DO		EXYNOS5_GPA2(7)
+
+#define	GPIO_ACC_INT		EXYNOS5_GPX1(4)
+
+#define	GPIO_ACCESSORY_CHECK	EXYNOS5_GPE0(4)
+#define	GPIO_ACCESSORY_EN	EXYNOS5_GPH1(5)
+#define	GPIO_ACCESSORY_INT	EXYNOS5_GPX3(2)
+
+#define	GPIO_ADC_INT		EXYNOS5_GPX2(4)
+#define	GPIO_ADC_SCL_18V	EXYNOS5_GPV3(0)
+#define	GPIO_ADC_SDA_18V	EXYNOS5_GPV3(1)
+
+#define	GPIO_ALS_nRST		EXYNOS5_GPH1(2)
+#define	GPIO_ALS_SCL_18V	EXYNOS5_GPG0(1)
+#define	GPIO_ALS_SDA_18V	EXYNOS5_GPG0(0)
+
+#define	GPIO_AP_CP_INT		EXYNOS5_GPB0(0)
+#define	GPIO_AP_CPU_PWR_DN	EXYNOS5_GPX1(5)
+#define	GPIO_AP_PMIC_IRQ	EXYNOS5_GPX0(2)
+#define	GPIO_AP_PMIC_SCL	EXYNOS5_GPA2(3)
+#define	GPIO_AP_PMIC_SDA	EXYNOS5_GPA2(2)
+#define	GPIO_AP_RXD		EXYNOS5_GPA1(0)
+#define	GPIO_AP_TXD		EXYNOS5_GPA1(1)
+
+#define	GPIO_AP2CMC_INT1_18V	EXYNOS5_GPX0(6)
+#define	GPIO_AP2CMC_INT2_18V	EXYNOS5_GPX1(1)
+#define	GPIO_AP2CMC_INT3_18V	EXYNOS5_GPX1(2)
+
+#define	GPIO_AUTO_DFS		EXYNOS5_GPZ(1)
+
+#define	GPIO_BARO_INT		EXYNOS5_GPB1(0)
+
+#define	GPIO_BSENSE_SCL_18V	EXYNOS5_GPD0(3)
+#define	GPIO_BSENSE_SDA_18V	EXYNOS5_GPD0(2)
+
+#define	GPIO_BT_HOST_WAKE	EXYNOS5_GPX2(6)
+#define	GPIO_BT_UART_CTS	EXYNOS5_GPA0(2)
+#define	GPIO_BT_UART_RTS	EXYNOS5_GPA0(3)
+#define	GPIO_BT_UART_RXD	EXYNOS5_GPA0(0)
+#define	GPIO_BT_UART_TXD	EXYNOS5_GPA0(1)
+#define	GPIO_BT_WAKE		EXYNOS5_GPH1(3)
+
+#define	GPIO_BTREG_ON		EXYNOS5_GPH0(0)
+#define   IRQ_BT_HOST_WAKE	IRQ_EINT(22)
+
+#define	GPIO_BUCK2_SEL		EXYNOS5_GPV0(4)
+
+#define	GPIO_BUCK3_SEL		EXYNOS5_GPV0(1)
+
+#define	GPIO_BUCK4_SEL		EXYNOS5_GPV0(0)
+
+#define	GPIO_CAM_FLASH_EN_T	EXYNOS5_GPG1(0)
+#define	GPIO_CAM_FLASH_SET_T	EXYNOS5_GPG1(1)
+#define	GPIO_CAM_IO_EN		EXYNOS5_GPV0(3)
+#define	GPIO_CAM_MCLK		EXYNOS5_GPH0(3)
+#define	GPIO_CAM_VT_nRST	EXYNOS5_GPG1(6)
+
+#define	GPIO_CHG_SCL_18V	EXYNOS5_GPE0(2)
+#define	GPIO_CHG_SDA_18V	EXYNOS5_GPE0(1)
+
+#define	GPIO_CIS_nRST		EXYNOS5_GPE0(0)
+
+#define	GPIO_CMC_PMIC_PWRON	EXYNOS5_GPD1(5)
+#define	GPIO_CMC_SPI_CLK_ACK	EXYNOS5_GPX1(3)
+#define	GPIO_CMC_SPI_CLK_REQ	EXYNOS5_GPB0(2)
+#define	GPIO_CMC_USB_DETECT	EXYNOS5_GPH1(0)
+
+#define	GPIO_CMC221_CPU_RST	EXYNOS5_GPB0(1)
+
+#define	GPIO_CMC2AP_INT1_18V	EXYNOS5_GPX0(3)
+#define	GPIO_CMC2AP_INT2_18V	EXYNOS5_GPX1(0)
+
+#define	GPIO_WM8994_LDO		EXYNOS5_GPH1(1)
+#define	GPIO_CODEC_SCL_18V	EXYNOS5_GPB2(3)
+#define	GPIO_CODEC_SDA_18V	EXYNOS5_GPB2(2)
+
+#define	GPIO_DET_35		EXYNOS5_GPX0(1)
+
+#define	GPIO_DOCK_INT		EXYNOS5_GPX3(0)
+
+#define	GPIO_DP_HPD		EXYNOS5_GPX0(7)
+
+#define	GPIO_DPRAM_A0		EXYNOS5_GPY3(0)
+#define	GPIO_DPRAM_A1		EXYNOS5_GPY3(1)
+#define	GPIO_DPRAM_A2		EXYNOS5_GPY3(2)
+#define	GPIO_DPRAM_A3		EXYNOS5_GPY3(3)
+#define	GPIO_DPRAM_A4		EXYNOS5_GPY3(4)
+#define	GPIO_DPRAM_A5		EXYNOS5_GPY3(5)
+#define	GPIO_DPRAM_A6		EXYNOS5_GPY3(6)
+#define	GPIO_DPRAM_A7		EXYNOS5_GPY3(7)
+#define	GPIO_DPRAM_A8		EXYNOS5_GPY4(0)
+#define	GPIO_DPRAM_A9		EXYNOS5_GPY4(1)
+#define	GPIO_DPRAM_A10		EXYNOS5_GPY4(2)
+#define	GPIO_DPRAM_A11		EXYNOS5_GPY4(3)
+#define	GPIO_DPRAM_A12		EXYNOS5_GPY4(4)
+#define	GPIO_DPRAM_A13		EXYNOS5_GPY4(5)
+#define	GPIO_DPRAM_CSN		EXYNOS5_GPY0(0)
+#define	GPIO_DPRAM_D0		EXYNOS5_GPY5(0)
+#define	GPIO_DPRAM_D1		EXYNOS5_GPY5(1)
+#define	GPIO_DPRAM_D2		EXYNOS5_GPY5(2)
+#define	GPIO_DPRAM_D3		EXYNOS5_GPY5(3)
+#define	GPIO_DPRAM_D4		EXYNOS5_GPY5(4)
+#define	GPIO_DPRAM_D5		EXYNOS5_GPY5(5)
+#define	GPIO_DPRAM_D6		EXYNOS5_GPY5(6)
+#define	GPIO_DPRAM_D7		EXYNOS5_GPY5(7)
+#define	GPIO_DPRAM_D8		EXYNOS5_GPY6(0)
+#define	GPIO_DPRAM_D9		EXYNOS5_GPY6(1)
+#define	GPIO_DPRAM_D10		EXYNOS5_GPY6(2)
+#define	GPIO_DPRAM_D11		EXYNOS5_GPY6(3)
+#define	GPIO_DPRAM_D12		EXYNOS5_GPY6(4)
+#define	GPIO_DPRAM_D13		EXYNOS5_GPY6(5)
+#define	GPIO_DPRAM_D14		EXYNOS5_GPY6(6)
+#define	GPIO_DPRAM_D15		EXYNOS5_GPY6(7)
+#define	GPIO_DPRAM_INT		EXYNOS5_GPX0(5)
+#define	GPIO_DPRAM_REN		EXYNOS5_GPY0(4)
+#define	GPIO_DPRAM_WEN		EXYNOS5_GPY0(5)
+
+#define	GPIO_EAR_SEND_END	EXYNOS5_GPX3(6)
+
+#define	GPIO_eMMC_EN		EXYNOS5_GPC0(2)
+
+#define	GPIO_FM34_BYPASS	EXYNOS5_GPH1(4)
+#define	GPIO_FM34_PWDN		EXYNOS5_GPG0(3)
+#define	GPIO_FM34_RESET		EXYNOS5_GPG0(4)
+#define	GPIO_FM34_SCL_18V	EXYNOS5_GPA2(1)
+#define	GPIO_FM34_SDA_18V	EXYNOS5_GPA2(0)
+
+#define	GPIO_ES305_WAKEUP	EXYNOS5_GPG0(3)
+#define	GPIO_ES305_RESET	EXYNOS5_GPG0(4)
+
+#define	GPIO_FUEL_ALERT		EXYNOS5_GPX2(3)
+#define	GPIO_FUEL_SCL_18V	EXYNOS5_GPD0(1)
+#define	GPIO_FUEL_SDA_18V	EXYNOS5_GPD0(0)
+
+#define	GPIO_GPS_PWR_EN		EXYNOS5_GPE1(0)
+#define	GPIO_GPS_nRST		EXYNOS5_GPE0(6)
+#define	GPIO_GPS_CTS		EXYNOS5_GPA0(6)
+#define	GPIO_GPS_RTS		EXYNOS5_GPA0(7)
+#define	GPIO_GPS_RXD		EXYNOS5_GPA0(4)
+#define	GPIO_GPS_TXD		EXYNOS5_GPA0(5)
+
+#define	GPIO_GPS_CTS_AF		2
+#define	GPIO_GPS_RTS_AF		2
+#define	GPIO_GPS_RXD_AF		2
+#define	GPIO_GPS_TXD_AF		2
+
+#define	GPIO_GSENSE_SCL_18V	EXYNOS5_GPB3(3)
+#define	GPIO_GSENSE_SDA_18V	EXYNOS5_GPB3(2)
+
+#define	GPIO_HDMI_EN		EXYNOS5_GPC1(2)
+#define	GPIO_HDMI_HPD		EXYNOS5_GPX3(7)
+
+#define	GPIO_HUM_SCL_18V	EXYNOS5_GPV2(4)
+#define	GPIO_HUM_SDA_18V	EXYNOS5_GPV2(5)
+
+#define	GPIO_HW_REV0		EXYNOS5_GPV1(4)
+#define	GPIO_HW_REV1		EXYNOS5_GPV1(3)
+#define	GPIO_HW_REV2		EXYNOS5_GPV1(2)
+#define	GPIO_HW_REV3		EXYNOS5_GPV1(1)
+
+#define	GPIO_IPC_RXD		EXYNOS5_GPA1(4)
+#define	GPIO_IPC_TXD		EXYNOS5_GPA1(5)
+
+#define	GPIO_ISP_RXD		EXYNOS5_GPE1(1)
+#define	GPIO_ISP_STANDBY	EXYNOS5_GPG1(7)
+#define	GPIO_ISP_TXD		EXYNOS5_GPE0(7)
+
+#define	GPIO_LCD_EN		EXYNOS5_GPH1(7)
+#define	GPIO_LCD_ID		EXYNOS5_GPD1(4)
+#define	GPIO_LCD_PWM_IN_18V	EXYNOS5_GPB2(0)
+
+#define	GPIO_LCDP_SCL__18V	EXYNOS5_GPD0(6)
+#define	GPIO_LCDP_SDA__18V	EXYNOS5_GPD0(7)
+
+#define	GPIO_LED_BACKLIGHT_RESET	EXYNOS5_GPG0(5)
+
+#define	GPIO_LTE_ACTIVE		EXYNOS5_GPX1(6)
+
+#define	GPIO_MHL_DSCL_18V	EXYNOS5_GPB3(1)
+#define	GPIO_MHL_DSDA_18V	EXYNOS5_GPB3(0)
+#define	GPIO_MHL_INT		EXYNOS5_GPG0(6)
+#define	GPIO_MHL_RST		EXYNOS5_GPG0(7)
+#define	GPIO_MHL_SCL_18V	EXYNOS5_GPD0(5)
+#define	GPIO_MHL_SDA_18V	EXYNOS5_GPD0(4)
+
+#define	GPIO_MM_I2S_CLK		EXYNOS5_GPZ(0)
+#define	GPIO_MM_I2S_DI		EXYNOS5_GPZ(3)
+#define	GPIO_MM_I2S_DO		EXYNOS5_GPZ(4)
+#define	GPIO_MM_I2S_SYNC	EXYNOS5_GPZ(2)
+
+#define	GPIO_MOTOR_EN		EXYNOS5_GPD1(6)
+#define	GPIO_MOTOR_PWM		EXYNOS5_GPB2(1)
+#define	GPIO_MOTOR_SCL_18V	EXYNOS5_GPD1(3)
+#define	GPIO_MOTOR_SDA_18V	EXYNOS5_GPD1(2)
+
+#define	GPIO_MSENSE_RDY		EXYNOS5_GPX2(2)
+#define	GPIO_MSENSE_RST		EXYNOS5_GPG2(0)
+#define	GPIO_MSENSE_SDA		EXYNOS5_GPV2(7)
+#define	GPIO_MSENSE_SCL		EXYNOS5_GPV2(6)
+
+#define	GPIO_PS_ALS_SDA		EXYNOS5_GPG0(0)
+#define	GPIO_PS_ALS_SCL		EXYNOS5_GPG0(1)
+#define	GPIO_PS_VOUT		EXYNOS5_GPH1(2)
+#define	GPIO_HUM_SDA		EXYNOS5_GPV2(5)
+#define	GPIO_HUM_SCL		EXYNOS5_GPV2(4)
+
+
+#define	GPIO_M_SDA		EXYNOS5_GPB1(3)
+
+#define	GPIO_NAND_CLK		EXYNOS5_GPC0(0)
+#define	GPIO_NAND_CMD		EXYNOS5_GPC0(1)
+#define	GPIO_NAND_D0		EXYNOS5_GPC0(3)
+#define	GPIO_NAND_D1		EXYNOS5_GPC0(4)
+#define	GPIO_NAND_D2		EXYNOS5_GPC0(5)
+#define	GPIO_NAND_D3		EXYNOS5_GPC0(6)
+#define	GPIO_NAND_D4		EXYNOS5_GPC1(3)
+#define	GPIO_NAND_D5		EXYNOS5_GPC1(4)
+#define	GPIO_NAND_D6		EXYNOS5_GPC1(5)
+#define	GPIO_NAND_D7		EXYNOS5_GPC1(6)
+
+#define	GPIO_nPOWER		EXYNOS5_GPX2(7)
+
+#define	GPIO_OTG_EN		EXYNOS5_GPC3(2)
+
+#define	GPIO_PDA_ACTIVE		EXYNOS5_GPE0(3)
+
+#define	GPIO_PMIC_DVS1		EXYNOS5_GPV0(7)
+#define	GPIO_PMIC_DVS2		EXYNOS5_GPV0(6)
+#define	GPIO_PMIC_DVS3		EXYNOS5_GPV0(5)
+
+#define	GPIO_REMOTE_SENSE_IRQ	EXYNOS5_GPX3(1)
+
+#define	GPIO_SIM_DETECT		EXYNOS5_GPX3(3)
+
+#define	GPIO_T_FLASH_CLK	EXYNOS5_GPC2(0)
+#define	GPIO_T_FLASH_CMD	EXYNOS5_GPC2(1)
+#define	GPIO_T_FLASH_D0		EXYNOS5_GPC2(3)
+#define	GPIO_T_FLASH_D1		EXYNOS5_GPC2(4)
+#define	GPIO_T_FLASH_D2		EXYNOS5_GPC2(5)
+#define	GPIO_T_FLASH_D3		EXYNOS5_GPC2(6)
+#define	GPIO_T_FLASH_DETECT	EXYNOS5_GPX3(4)
+
+#define	GPIO_TA_EN		EXYNOS5_GPG1(5)
+#define	GPIO_TA_nCONNECTED	EXYNOS5_GPX0(0)
+#define	GPIO_TA_nCHG		EXYNOS5_GPG1(4)
+
+#define	GPIO_TF_EN		EXYNOS5_GPY2(0)
+
+#define	GPIO_TOUCH_CHG		EXYNOS5_GPG1(2)
+#define	GPIO_TOUCH_RESET	EXYNOS5_GPG1(3)
+
+#define	GPIO_TP400		EXYNOS5_GPH0(2)
+
+#define	GPIO_TP405		EXYNOS5_GPX0(4)
+
+#define	GPIO_TP406		EXYNOS5_GPX3(5)
+
+#define	GPIO_TP411		EXYNOS5_GPG0(2)
+
+#define	GPIO_TSP_SCL_18V	EXYNOS5_GPA1(3)
+#define	GPIO_TSP_SDA_18V	EXYNOS5_GPA1(2)
+
+#define	GPIO_UART_SEL		EXYNOS5_GPE0(5)
+
+#define	GPIO_USB_SEL1		EXYNOS5_GPH0(1)
+
+#define	GPIO_USB30_EN		EXYNOS5_GPC2(2)
+
+#define	GPIO_VOL_DOWN		EXYNOS5_GPX2(1)
+#define	GPIO_VOL_UP		EXYNOS5_GPX2(0)
+
+#define	GPIO_VT_CAM_SCL_18V	EXYNOS5_GPF0(3)
+#define	GPIO_VT_CAM_SDA_18V	EXYNOS5_GPF0(2)
+
+#define	GPIO_VTCAM_MCLK		EXYNOS5_GPG2(1)
+
+#define GPIO_WLAN_EN            EXYNOS5_GPV1(0)
+#define GPIO_WLAN_EN_AF         1
+#define GPIO_WLAN_HOST_WAKE     EXYNOS5_GPX2(5)
+#define GPIO_WLAN_HOST_WAKE_AF  0xF
+#define GPIO_WLAN_SDIO_CLK      EXYNOS5_GPC3(0)
+#define GPIO_WLAN_SDIO_CLK_AF   2
+#define GPIO_WLAN_SDIO_CMD      EXYNOS5_GPC3(1)
+#define GPIO_WLAN_SDIO_CMD_AF   2
+#define GPIO_WLAN_SDIO_D0       EXYNOS5_GPC3(3)
+#define GPIO_WLAN_SDIO_D0_AF    2
+#define GPIO_WLAN_SDIO_D1       EXYNOS5_GPC3(4)
+#define GPIO_WLAN_SDIO_D1_AF    2
+#define GPIO_WLAN_SDIO_D2       EXYNOS5_GPC3(5)
+#define GPIO_WLAN_SDIO_D2_AF    2
+#define GPIO_WLAN_SDIO_D3       EXYNOS5_GPC3(6)
+#define GPIO_WLAN_SDIO_D3_AF    2
+
+/**
+ *  Mapping for Func0.
+ */
+#define	GPIO_I2C_0_SDA		EXYNOS5_GPB3(0)
+#define	GPIO_I2C_1_SDA		EXYNOS5_GPB3(2)
+
+/**
+ *  Mapping for Func1.
+ */
+#define	GPIO_I2C_2_SDA		EXYNOS5_GPA0(6)
+#define	GPIO_I2C_3_SDA		EXYNOS5_GPA1(2)
+#define	GPIO_I2C_4_SDA		EXYNOS5_GPA2(0)
+#define	GPIO_I2C_5_SDA		EXYNOS5_GPA2(2)
+#define	GPIO_I2C_7_SDA		EXYNOS5_GPB2(2)
+
+#define	GPIO_PCM_0_SCLK		EXYNOS5_GPZ(0)
+#define	GPIO_PCM_1_SCLK		EXYNOS5_GPB0(0)
+#define	GPIO_PCM_2_SCLK		EXYNOS5_GPB1(0)
+
+/**
+ *  Mapping for Func2.
+ */
+#define	GPIO_I2C_6_SDA		EXYNOS5_GPB1(3)
+
+/**
+ *  Remappig for downward compatibility.
+ */
+#define	GPIO_PMIC_IRQ		GPIO_AP_PMIC_IRQ
+#define	GPIO_HDMI_CEC		GPIO_EAR_SEND_END
+
+/* Definitions for DPRAM */
+#define GPIO_DPRAM_CSN		EXYNOS5_GPY0(0)
+#define GPIO_DPRAM_CSN0		EXYNOS5_GPY0(0)
+#define GPIO_DPRAM_CSN1		EXYNOS5_GPY0(1)
+#define GPIO_DPRAM_CSN2		EXYNOS5_GPY0(2)
+#define GPIO_DPRAM_CSN3		EXYNOS5_GPY0(3)
+#define GPIO_DPRAM_REN		EXYNOS5_GPY0(4)
+#define GPIO_DPRAM_WEN		EXYNOS5_GPY0(5)
+/* #define GPIO_DPRAM_LBN		EXYNOS4_GPY1(0) // for via modem */
+/* #define GPIO_DPRAM_UBN		EXYNOS4_GPY1(1) // for via modem */
+#define GPIO_SROM_ADDR_BUS_LOW	EXYNOS5_GPY3(0)
+#define GPIO_SROM_ADDR_BUS_HIGH	EXYNOS5_GPY4(0)
+#define GPIO_SROM_DATA_BUS_LOW	EXYNOS5_GPY5(0)
+#define GPIO_SROM_DATA_BUS_HIGH	EXYNOS5_GPY6(0)
+
+/* Definitions for CMC221 */
+#define CP_CMC221_PMIC_PWRON	EXYNOS5_GPD1(5)
+#define CP_CMC221_CPU_RST	EXYNOS5_GPB0(1)
+#define GPIO_LTE_ACTIVE		EXYNOS5_GPX1(6)
+#define LTE_ACTIVE_IRQ		IRQ_EINT(14)	/* IRQ of GPX1[6] */
+
+#define GPIO_CMC_IDPRAM_INT_00	EXYNOS5_GPX0(5)
+#define CMC_IDPRAM_INT_IRQ_00	IRQ_EINT(5)	/* IRQ of GPX0[5] */
+
+#define GPIO_CMC_IDPRAM_STATUS	EXYNOS5_GPX0(3) /* CMC2AP_INT_1 */
+#define GPIO_CMC_IDPRAM_WAKEUP	EXYNOS5_GPX1(2) /* AP2CMC_INT_3 */
+/* #define GPIO_ACTIVE_STATE	EXYNOS4_GPF1(1) // for USB */
+#define GPIO_IPC_SLAVE_WAKEUP	EXYNOS5_GPX0(6) /* AP2CMC_INT_1 */
+#define GPIO_IPC_HOST_WAKEUP	EXYNOS5_GPX1(0) /* CMC2AP_INT_2 */
+
+#define	GPIO_CMC_CLK_18V	EXYNOS5_GPF1(0)
+#define	GPIO_CMC_CS_18V		EXYNOS5_GPF1(1)
+
+#define	GPIO_5M_nRST		EXYNOS5_GPE0(0)
+
+#endif /* __MACH_GPIO_P10_H */
diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev00-p10.h b/arch/arm/mach-exynos/include/mach/gpio-rev00-p10.h
new file mode 100644
index 0000000..2e8a85c
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/gpio-rev00-p10.h
@@ -0,0 +1,311 @@
+#ifndef __MACH_GPIO_P10_H
+#define __MACH_GPIO_P10 __FILE__
+
+#include <mach/gpio.h>
+
+extern void p10_config_gpio_table(void);
+extern void p10_config_sleep_gpio_table(void);
+
+#define	GPIO_5M_CAM_SCL_18V	EXYNOS5_GPF0(1)
+#define	GPIO_5M_CAM_SDA_18V	EXYNOS5_GPF0(0)
+#define	GPIO_5M_CORE_EN		EXYNOS5_GPV0(2)
+#define	GPIO_5M_nRST		EXYNOS5_GPE0(0)
+#define	GPIO_5M_SPI_CLK		EXYNOS5_GPA2(4)
+#define	GPIO_5M_SPI_CS		EXYNOS5_GPA2(5)
+#define	GPIO_5M_SPI_DI		EXYNOS5_GPA2(6)
+#define	GPIO_5M_SPI_DO		EXYNOS5_GPA2(7)
+
+#define	GPIO_ACC_INT		EXYNOS5_GPX1(4)
+
+#define	GPIO_ACCESSORY_CHECK	EXYNOS5_GPE0(4)
+#define	GPIO_ACCESSORY_EN	EXYNOS5_GPH1(5)
+#define	GPIO_ACCESSORY_INT	EXYNOS5_GPX3(2)
+
+#define	GPIO_ADC_INT		EXYNOS5_GPX2(4)
+#define	GPIO_ADC_SCL_18V	EXYNOS5_GPV3(0)
+#define	GPIO_ADC_SDA_18V	EXYNOS5_GPV3(1)
+
+#define	GPIO_AMP_L_INT		EXYNOS5_GPB0(1)
+#define	GPIO_AMP_L_SCL_18V	EXYNOS5_GPC1(1)
+#define	GPIO_AMP_L_SDA_18V	EXYNOS5_GPC1(0)
+#define	GPIO_AMP_R_INT		EXYNOS5_GPB1(0)
+#define	GPIO_AMP_R_SCL_18V	EXYNOS5_GPB1(2)
+#define	GPIO_AMP_R_SDA_18V	EXYNOS5_GPB1(1)
+
+#define	GPIO_AP_CP_INT		EXYNOS5_GPB0(4)
+#define	GPIO_AP_CPU_PWR_DN	EXYNOS5_GPX1(5)
+#define	GPIO_AP_PMIC_IRQ	EXYNOS5_GPX0(2)
+#define	GPIO_AP_PMIC_SCL	EXYNOS5_GPA2(3)
+#define	GPIO_AP_PMIC_SDA	EXYNOS5_GPA2(2)
+#define	GPIO_AP_RXD		EXYNOS5_GPA1(0)
+#define	GPIO_AP_TXD		EXYNOS5_GPA1(1)
+
+#define	GPIO_AP2CMC_INT1_18V	EXYNOS5_GPX0(6)
+#define	GPIO_AP2CMC_INT2_18V	EXYNOS5_GPX1(1)
+#define	GPIO_AP2CMC_INT3_18V	EXYNOS5_GPX1(2)
+
+#define	GPIO_BARO_INT		EXYNOS5_GPB0(2)
+
+#define	GPIO_BSENSE_SCL_18V	EXYNOS5_GPD0(3)
+#define	GPIO_BSENSE_SDA_18V	EXYNOS5_GPD0(2)
+
+#define	GPIO_BT_EN		EXYNOS5_GPE0(2)
+#define	GPIO_BT_HOST_WAKE	EXYNOS5_GPX2(6)
+#define	GPIO_BT_nRST		EXYNOS5_GPE0(1)
+#define	GPIO_BT_UART_CTS	EXYNOS5_GPA0(2)
+#define	GPIO_BT_UART_RTS	EXYNOS5_GPA0(3)
+#define	GPIO_BT_UART_RXD	EXYNOS5_GPA0(0)
+#define	GPIO_BT_UART_TXD	EXYNOS5_GPA0(1)
+#define	GPIO_BT_WAKE		EXYNOS5_GPH1(3)
+#define   IRQ_BT_HOST_WAKE	IRQ_EINT(22)
+
+#define	GPIO_BUCK2_SEL		EXYNOS5_GPV0(4)
+#define	GPIO_BUCK3_SEL		EXYNOS5_GPV0(1)
+#define	GPIO_BUCK4_SEL		EXYNOS5_GPV0(0)
+
+#define	GPIO_CAM_FLASH_EN	EXYNOS5_GPG1(0)
+#define	GPIO_CAM_FLASH_SET	EXYNOS5_GPG1(1)
+#define	GPIO_CAM_IO_EN		EXYNOS5_GPV0(3)
+#define	GPIO_CAM_MCLK		EXYNOS5_GPH0(3)
+#define	GPIO_CAM_VT_nRST	EXYNOS5_GPG1(6)
+
+#define	GPIO_CHG_SDA_18V	EXYNOS5_GPE0(1)
+#define	GPIO_CHG_SCL_18V	EXYNOS5_GPE0(2)
+
+#define	GPIO_CMC_CLK_18V	EXYNOS5_GPF1(0)
+#define	GPIO_CMC_CS_18V		EXYNOS5_GPF1(1)
+#define	GPIO_CMC_DI_18V		EXYNOS5_GPF1(3)
+#define	GPIO_CMC_DO_18V		EXYNOS5_GPF1(2)
+#define	GPIO_CMC_PMIC_PWRON	EXYNOS5_GPD1(5)
+#define	GPIO_CMC_SPI_CLK_ACK	EXYNOS5_GPX1(3)
+#define	GPIO_CMC_SPI_CLK_REQ	EXYNOS5_GPB0(3)
+
+#define	GPIO_CMC221_CPU_RST	EXYNOS5_GPB0(0)
+
+#define	GPIO_CMC2AP_INT1_18V	EXYNOS5_GPX0(3)
+#define	GPIO_CMC2AP_INT2_18V	EXYNOS5_GPX1(0)
+
+#define	GPIO_WM8994_LDO		EXYNOS5_GPH1(1)
+#define	GPIO_CODEC_SCL_18V	EXYNOS5_GPB2(3)
+#define	GPIO_CODEC_SDA_18V	EXYNOS5_GPB2(2)
+
+#define	GPIO_DET_35		EXYNOS5_GPX0(1)
+
+#define	GPIO_DOCK_INT		EXYNOS5_GPX3(0)
+
+#define	GPIO_DP_HPD		EXYNOS5_GPX0(7)
+
+#define	GPIO_DPRAM_A0		EXYNOS5_GPY3(0)
+#define	GPIO_DPRAM_A1		EXYNOS5_GPY3(1)
+#define	GPIO_DPRAM_A2		EXYNOS5_GPY3(2)
+#define	GPIO_DPRAM_A3		EXYNOS5_GPY3(3)
+#define	GPIO_DPRAM_A4		EXYNOS5_GPY3(4)
+#define	GPIO_DPRAM_A5		EXYNOS5_GPY3(5)
+#define	GPIO_DPRAM_A6		EXYNOS5_GPY3(6)
+#define	GPIO_DPRAM_A7		EXYNOS5_GPY3(7)
+#define	GPIO_DPRAM_A8		EXYNOS5_GPY4(0)
+#define	GPIO_DPRAM_A9		EXYNOS5_GPY4(1)
+#define	GPIO_DPRAM_A10		EXYNOS5_GPY4(2)
+#define	GPIO_DPRAM_A11		EXYNOS5_GPY4(3)
+#define	GPIO_DPRAM_A12		EXYNOS5_GPY4(4)
+#define	GPIO_DPRAM_A13		EXYNOS5_GPY4(5)
+
+#define	GPIO_DPRAM_D0		EXYNOS5_GPY5(0)
+#define	GPIO_DPRAM_D1		EXYNOS5_GPY5(1)
+#define	GPIO_DPRAM_D2		EXYNOS5_GPY5(2)
+#define	GPIO_DPRAM_D3		EXYNOS5_GPY5(3)
+#define	GPIO_DPRAM_D4		EXYNOS5_GPY5(4)
+#define	GPIO_DPRAM_D5		EXYNOS5_GPY5(5)
+#define	GPIO_DPRAM_D6		EXYNOS5_GPY5(6)
+#define	GPIO_DPRAM_D7		EXYNOS5_GPY5(7)
+#define	GPIO_DPRAM_D8		EXYNOS5_GPY6(0)
+#define	GPIO_DPRAM_D9		EXYNOS5_GPY6(1)
+#define	GPIO_DPRAM_D10		EXYNOS5_GPY6(2)
+#define	GPIO_DPRAM_D11		EXYNOS5_GPY6(3)
+#define	GPIO_DPRAM_D12		EXYNOS5_GPY6(4)
+#define	GPIO_DPRAM_D13		EXYNOS5_GPY6(5)
+#define	GPIO_DPRAM_D14		EXYNOS5_GPY6(6)
+#define	GPIO_DPRAM_D15		EXYNOS5_GPY6(7)
+
+#define	GPIO_DPRAM_CSN		EXYNOS5_GPY0(0)
+#define	GPIO_DPRAM_INT		EXYNOS5_GPX0(5)
+#define	GPIO_DPRAM_REN		EXYNOS5_GPY0(4)
+#define	GPIO_DPRAM_WEN		EXYNOS5_GPY0(5)
+
+#define	GPIO_EAR_SEND_END	EXYNOS5_GPX3(6)
+
+#define	GPIO_eMMC_EN		EXYNOS5_GPC0(2)
+
+#define	GPIO_FM34_PWDN		EXYNOS5_GPG0(3)
+#define	GPIO_FM34_RESET		EXYNOS5_GPG0(4)
+#define	GPIO_FM34_BYPASS	EXYNOS5_GPH1(4)
+
+#define	GPIO_ES305_WAKEUP	EXYNOS5_GPG0(3)
+#define	GPIO_ES305_RESET	EXYNOS5_GPG0(4)
+
+#define	GPIO_FUEL_ALERT		EXYNOS5_GPX2(3)
+#define	GPIO_FUEL_SCL_18V	EXYNOS5_GPD0(1)
+#define	GPIO_FUEL_SDA_18V	EXYNOS5_GPD0(0)
+
+#define	GPIO_GPS_PWR_EN		EXYNOS5_GPE1(0)
+#define	GPIO_GPS_nRST		EXYNOS5_GPE0(6)
+#define	GPIO_GPS_CTS		EXYNOS5_GPA0(6)
+#define	GPIO_GPS_RTS		EXYNOS5_GPA0(7)
+#define	GPIO_GPS_RXD		EXYNOS5_GPA0(4)
+#define	GPIO_GPS_TXD		EXYNOS5_GPA0(5)
+
+#define	GPIO_GPS_CTS_AF		2
+#define	GPIO_GPS_RTS_AF		2
+#define	GPIO_GPS_RXD_AF		2
+#define	GPIO_GPS_TXD_AF		2
+
+#define	GPIO_GSENSE_SCL_18V	EXYNOS5_GPB3(3)
+#define	GPIO_GSENSE_SDA_18V	EXYNOS5_GPB3(2)
+
+#define	GPIO_HDMI_EN		EXYNOS5_GPC1(2)
+#define	GPIO_HDMI_HPD		EXYNOS5_GPX3(7)
+
+#define	GPIO_HUM_SCL_18V	EXYNOS5_GPV2(4)
+#define	GPIO_HUM_SDA_18V	EXYNOS5_GPV2(5)
+
+#define	GPIO_HW_REV0		EXYNOS5_GPV1(4)
+#define	GPIO_HW_REV1		EXYNOS5_GPV1(3)
+#define	GPIO_HW_REV2		EXYNOS5_GPV1(2)
+#define	GPIO_HW_REV3		EXYNOS5_GPV1(1)
+
+#define	GPIO_IPC_RXD		EXYNOS5_GPA1(4)
+#define	GPIO_IPC_TXD		EXYNOS5_GPA1(5)
+
+#define	GPIO_IRDA_DOUT_AP	EXYNOS5_GPG0(1)
+
+#define	GPIO_ISP_RXD		EXYNOS5_GPE1(1)
+#define	GPIO_ISP_TXD		EXYNOS5_GPE0(7)
+
+#define	GPIO_LCD_APS_EN_18V	EXYNOS5_GPG0(3)
+#define	GPIO_LCD_EN		EXYNOS5_GPH1(7)
+#define	GPIO_LCD_ID		EXYNOS5_GPD1(4)
+#define	GPIO_LCD_PWM_IN_18V	EXYNOS5_GPB2(0)
+
+#define	GPIO_LCDP_SCL__18V	EXYNOS5_GPD0(6)
+#define	GPIO_LCDP_SDA__18V	EXYNOS5_GPD0(7)
+
+#define	GPIO_LED_BACKLIGHT_RESET	EXYNOS5_GPG0(5)
+
+#define	GPIO_LIGHT_I2C_SCL	EXYNOS5_GPB1(4)
+#define	GPIO_LIGHT_I2C_SDA	EXYNOS5_GPB1(3)
+#define	GPIO_LIGHT_nINT		EXYNOS5_GPH1(2)
+
+#define	GPIO_LTE_ACTIVE		EXYNOS5_GPX1(6)
+
+#define	GPIO_MHL_DSCL_18V	EXYNOS5_GPB3(1)
+#define	GPIO_MHL_DSDA_18V	EXYNOS5_GPB3(0)
+#define	GPIO_MHL_INT		EXYNOS5_GPG0(6)
+#define	GPIO_MHL_RST		EXYNOS5_GPG0(7)
+#define	GPIO_MHL_SCL_18V	EXYNOS5_GPD0(5)
+#define	GPIO_MHL_SDA_18V	EXYNOS5_GPD0(4)
+
+#define	GPIO_MM_I2S_CLK		EXYNOS5_GPZ(0)
+#define	GPIO_MM_I2S_DI		EXYNOS5_GPZ(3)
+#define	GPIO_MM_I2S_DO		EXYNOS5_GPZ(4)
+#define	GPIO_MM_I2S_SYNC	EXYNOS5_GPZ(2)
+
+#define	GPIO_MOTOR_SCL_18V	EXYNOS5_GPD1(3)
+#define	GPIO_MOTOR_SDA_18V	EXYNOS5_GPD1(2)
+
+#define	GPIO_MSENSE_INT		EXYNOS5_GPX2(2)
+#define	GPIO_MSENSE_SCL_18V	EXYNOS5_GPV2(6)
+#define	GPIO_MSENSE_SDA_18V	EXYNOS5_GPV2(7)
+
+#define	GPIO_NAND_CLK		EXYNOS5_GPC0(0)
+#define	GPIO_NAND_CMD		EXYNOS5_GPC0(1)
+#define	GPIO_NAND_D0		EXYNOS5_GPC0(3)
+#define	GPIO_NAND_D1		EXYNOS5_GPC0(4)
+#define	GPIO_NAND_D2		EXYNOS5_GPC0(5)
+#define	GPIO_NAND_D3		EXYNOS5_GPC0(6)
+#define	GPIO_NAND_D4		EXYNOS5_GPC1(3)
+#define	GPIO_NAND_D5		EXYNOS5_GPC1(4)
+#define	GPIO_NAND_D6		EXYNOS5_GPC1(5)
+#define	GPIO_NAND_D7		EXYNOS5_GPC1(6)
+
+#define	GPIO_NFC_EN		EXYNOS5_GPD1(6)
+#define	GPIO_NFC_FIRMWARE	EXYNOS5_GPD1(7)
+#define	GPIO_NFC_IRQ		EXYNOS5_GPX1(7)
+#define	GPIO_NFC_SCL_18V	EXYNOS5_GPV2(1)
+#define	GPIO_NFC_SDA_18V	EXYNOS5_GPV2(0)
+
+#define	GPIO_nPOWER		EXYNOS5_GPX2(7)
+
+#define	GPIO_OTG_EN		EXYNOS5_GPC3(2)
+
+#define	GPIO_PDA_ACTIVE		EXYNOS5_GPE0(3)
+
+#define	GPIO_PMIC_DVS1		EXYNOS5_GPV0(7)
+#define	GPIO_PMIC_DVS2		EXYNOS5_GPV0(6)
+#define	GPIO_PMIC_DVS3		EXYNOS5_GPV0(5)
+
+#define	GPIO_REMOTE_SENSE_IRQ	EXYNOS5_GPX3(1)
+
+#define	GPIO_RGB_SCL_18V	EXYNOS5_GPD1(1)
+#define	GPIO_RGB_SDA_18V	EXYNOS5_GPD1(0)
+
+#define	GPIO_SIM_DETECT		EXYNOS5_GPX3(3)
+
+#define	GPIO_T_FLASH_CLK	EXYNOS5_GPC2(0)
+#define	GPIO_T_FLASH_CMD	EXYNOS5_GPC2(1)
+#define	GPIO_T_FLASH_D0		EXYNOS5_GPC2(3)
+#define	GPIO_T_FLASH_D1		EXYNOS5_GPC2(4)
+#define	GPIO_T_FLASH_D2		EXYNOS5_GPC2(5)
+#define	GPIO_T_FLASH_D3		EXYNOS5_GPC2(6)
+#define	GPIO_T_FLASH_DETECT	EXYNOS5_GPX3(4)
+
+#define	GPIO_TA_EN		EXYNOS5_GPG1(5)
+#define	GPIO_TA_nCHG		EXYNOS5_GPG1(4)
+#define	GPIO_TA_nCONNECTED	EXYNOS5_GPX0(0)
+
+#define	GPIO_TF_EN		EXYNOS5_GPY2(0)
+
+#define	GPIO_TOUCH_CHG		EXYNOS5_GPG1(2)
+#define	GPIO_TOUCH_RESET	EXYNOS5_GPG1(3)
+
+#define	GPIO_TSP_SCL_18V	EXYNOS5_GPA1(3)
+#define	GPIO_TSP_SDA_18V	EXYNOS5_GPA1(2)
+
+#define	GPIO_UART_SEL		EXYNOS5_GPE0(5)
+
+#define	GPIO_USB_SEL1		EXYNOS5_GPH0(1)
+
+#define	GPIO_USB30_EN		EXYNOS5_GPG0(2)
+
+#define	GPIO_VOL_DOWN		EXYNOS5_GPX2(1)
+#define	GPIO_VOL_UP		EXYNOS5_GPX2(0)
+
+#define	GPIO_VT_CAM_SCL_18V	EXYNOS5_GPF0(3)
+#define	GPIO_VT_CAM_SDA_18V	EXYNOS5_GPF0(2)
+
+#define	GPIO_VTCAM_MCLK		EXYNOS5_GPG2(1)
+
+#define	GPIO_WLAN_EN		EXYNOS5_GPH0(0)
+#define GPIO_WLAN_EN_AF         1
+#define	GPIO_WLAN_HOST_WAKE	EXYNOS5_GPX2(5)
+#define GPIO_WLAN_HOST_WAKE_AF  0xF
+#define	GPIO_WLAN_SDIO_CLK	EXYNOS5_GPC3(0)
+#define GPIO_WLAN_SDIO_CLK_AF   2
+#define	GPIO_WLAN_SDIO_CMD	EXYNOS5_GPC3(1)
+#define GPIO_WLAN_SDIO_CMD_AF   2
+#define	GPIO_WLAN_SDIO_D0	EXYNOS5_GPC3(3)
+#define GPIO_WLAN_SDIO_D0_AF    2
+#define	GPIO_WLAN_SDIO_D1	EXYNOS5_GPC3(4)
+#define GPIO_WLAN_SDIO_D1_AF    2
+#define	GPIO_WLAN_SDIO_D2	EXYNOS5_GPC3(5)
+#define GPIO_WLAN_SDIO_D2_AF    2
+#define	GPIO_WLAN_SDIO_D3	EXYNOS5_GPC3(6)
+#define GPIO_WLAN_SDIO_D3_AF    2
+#define	GPIO_WLAN_WAKE		EXYNOS5_GPV1(0)
+
+/**
+ *  Remappig for downward compatibility.
+ */
+#define	GPIO_PMIC_IRQ		GPIO_AP_PMIC_IRQ
+#define	GPIO_HDMI_CEC		GPIO_EAR_SEND_END
+
+#endif /* __MACH_GPIO_P10_H */
diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev00-p4note.h b/arch/arm/mach-exynos/include/mach/gpio-rev00-p4note.h
new file mode 100644
index 0000000..b5dc8a7
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/gpio-rev00-p4note.h
@@ -0,0 +1,346 @@
+#ifndef __MACH_GPIO_MIDAS_H
+#define __MACH_GPIO_MIDAS_H __FILE__
+
+#include <mach/gpio.h>
+
+extern void midas_config_gpio_table(void);
+extern void midas_config_sleep_gpio_table(void);
+
+#define GPIO_eMMC_EN		EXYNOS4_GPK0(2)
+
+#define GPIO_BOOT_MODE		EXYNOS4_GPX0(3)
+
+#define GPIO_FM_I2S_CLK		EXYSNO4_GPC0(0)
+#define GPIO_FM_I2S_SYNC	EXYSNO4_GPC0(2)
+#define GPIO_FM_I2S_DI		EXYSNO4_GPC0(3)
+#define GPIO_FM_I2S_DO		EXYSNO4_GPC0(4)
+
+#define GPIO_IF_PMIC_SDA	EXYNOS4212_GPM2(0)
+#define GPIO_IF_PMIC_SCL	EXYNOS4212_GPM2(1)
+#define GPIO_PMIC_SDA		EXYNOS4_GPB(2)
+#define GPIO_PMIC_SCL		EXYNOS4_GPB(3)
+
+#define GPIO_CAM_SPI_SCLK	EXYNOS4_GPB(4)
+#define GPIO_CAM_SPI_SSN	EXYNOS4_GPB(5)
+#define GPIO_CAM_SPI_MISO	EXYNOS4_GPB(6)
+#define GPIO_CAM_SPI_MOSI	EXYNOS4_GPB(7)
+
+#define GPIO_CAM_MCLK		EXYNOS4212_GPJ1(3)
+#define GPIO_VTCAM_MCLK		EXYNOS4212_GPM2(2)
+
+#define GPIO_3M_nRST		EXYNOS4_GPL1(1)
+#define GPIO_ISP_STANDBY	EXYNOS4212_GPM0(1)
+#define GPIO_CAM_IO_EN		EXYNOS4212_GPM0(2)
+#define GPIO_ISP_CORE_EN	EXYNOS4212_GPM0(3)
+#define GPIO_CAM_AF_EN		EXYNOS4212_GPM0(4)
+#define GPIO_3M_nSTBY		EXYNOS4212_GPM0(6)
+#define GPIO_2M_nRST		EXYNOS4212_GPM1(6)
+
+#define GPIO_8M_CAM_SCL_18V	EXYNOS4212_GPM4(0)
+#define GPIO_8M_CAM_SDA_18V	EXYNOS4212_GPM4(1)
+#define GPIO_8M_CAM_SCL_18V_00	EXYNOS4_GPD1(0)
+#define GPIO_8M_CAM_SDA_18V_00	EXYNOS4_GPD1(1)
+
+#define GPIO_VT_CAM_SCL_18V	EXYNOS4212_GPM4(2)
+#define GPIO_2M_nSTBY		EXYNOS4212_GPM4(3)
+#define GPIO_VT_CAM_ID			EXYNOS4_GPF1(2)
+
+/* 30pin Accessory */
+/*
+#define	GPIO_ACCESSORY_CHECK	EXYNOS4_GPE0(4)
+#define	GPIO_ACCESSORY_EN	EXYNOS4_GPL2(6)
+#define GPIO_ACCESSORY_OUT_5V	EXYNOS4_GPY4(4)
+*/
+#define	GPIO_ACCESSORY_INT		EXYNOS4_GPX1(3)
+#define	GPIO_DOCK_INT			EXYNOS4_GPX0(4)
+
+/* Sensors & NFC*/
+#define GPIO_PS_ALS_SDA_28V	EXYNOS4_GPL0(2)
+#define GPIO_PS_ALS_SCL_28V	EXYNOS4_GPL0(1)
+#define GPIO_PS_ALS_INT		EXYNOS4_GPX0(2)
+
+#define GPIO_ACC_INT		EXYNOS4_GPX0(0)
+
+#define GPIO_GYRO_DE		EXYNOS4_GPL2(0)
+#define GPIO_GPS_nRST		EXYNOS4_GPL2(1)
+#define GPIO_GPS_PWR_EN		EXYNOS4_GPL2(2)
+
+#define GPIO_GYRO_INT		EXYNOS4_GPX0(6)
+#define GPIO_GSENSE_SDA_18V	EXYNOS4_GPD1(2)
+#define GPIO_GSENSE_SCL_18V	EXYNOS4_GPD1(3)
+
+#define GPIO_MSENSOR_INT	EXYNOS4212_GPM4(7)
+#define GPIO_MSENSOR_SDA_18V	EXYNOS4_GPY2(4)
+#define GPIO_MSENSOR_SCL_18V	EXYNOS4_GPY2(5)
+
+#define GPIO_BENSE_SCL_18V	EXYNOS4_GPY2(3)
+#define GPIO_BSENSE_SDA_18V	EXYNOS4_GPY2(2)
+#define GPIO_BARO_INT		EXYNOS4_GPF0(5)
+
+#define GPIO_TF_EN		EXYNOS4_GPY2(0)
+#define GPIO_NFC_SCL_18V	EXYNOS4_GPZ(6)
+#define GPIO_NFC_SDA_18V	EXYNOS4_GPZ(5)
+#define GPIO_NFC_SCL_18V_00	EXYNOS4_GPB(3)
+#define GPIO_NFC_SDA_18V_00	EXYNOS4_GPB(2)
+#define GPIO_NFC_IRQ		EXYNOS4_GPX1(7)
+#define GPIO_NFC_EN		EXYNOS4_GPL2(6)
+#define GPIO_NFC_FIRMWARE	EXYNOS4_GPL2(6) /*tmp*/
+#define GPIO_NFC_CLK_REQ	EXYNOS4212_GPM0(0)
+/* Sensors & NFC*/
+
+#define GPIO_DET_35		EXYNOS4_GPX0(1)
+
+#define GPIO_MIC_BIAS_EN	EXYNOS4212_GPM0(0)
+#define GPIO_SUB_MIC_BIAS_EN	EXYNOS4_GPF2(0)
+#define GPIO_THIRD_MIC_BIAS_EN	EXYNOS4212_GPJ0(2)
+
+#define GPIO_PMU_RST		EXYNOS4_GPX3(2)
+
+#define GPIO_PMIC_IRQ		EXYNOS4_GPX0(7)
+#define GPIO_IF_PMIC_IRQ	EXYNOS4_GPX1(5)
+
+#define GPIO_TSP_INT		EXYNOS4212_GPM2(3)
+#define GPIO_TSP_SDA_18V	EXYNOS4_GPA1(2)
+#define GPIO_TSP_SCL_18V	EXYNOS4_GPA1(3)
+#define GPIO_TSP_LDO_ON		EXYNOS4_GPL0(3)
+#define GPIO_TSP_RST		EXYNOS4_GPL0(5)
+
+#define GPIO_PEN_PDCT_18V	EXYNOS4_GPC1(0)
+#define GPIO_PEN_LDO_EN	EXYNOS4_GPC1(1)
+#define GPIO_PEN_IRQ_18V	EXYNOS4_GPC1(2)
+#define GPIO_PEN_SDA_28V	EXYNOS4_GPC1(3)
+#define GPIO_PEN_SCL_28V	EXYNOS4_GPC1(4
+
+#define GPIO_BT_EN		EXYNOS4_GPL0(6)
+#define GPIO_BT_WAKE		EXYNOS4_GPX3(1)
+#define GPIO_BT_HOST_WAKE	EXYNOS4_GPX2(6)
+#define IRQ_BT_HOST_WAKE	IRQ_EINT(22)
+
+#define GPIO_BT_RXD		EXYNOS4_GPA0(0)
+#define GPIO_BT_RXD_AF		2
+
+#define GPIO_BT_TXD		EXYNOS4_GPA0(1)
+#define GPIO_BT_TXD_AF		2
+
+#define GPIO_BT_CTS		EXYNOS4_GPA0(2)
+#define GPIO_BT_CTS_AF		2
+
+#define GPIO_BT_RTS		EXYNOS4_GPA0(3)
+#define GPIO_BT_RTS_AF		2
+
+#define GPIO_GPS_RXD		EXYNOS4_GPA0(4)
+#define GPIO_GPS_RXD_AF		2
+
+#define GPIO_GPS_TXD		EXYNOS4_GPA0(5)
+#define GPIO_GPS_TXD_AF		2
+
+#define GPIO_GPS_CTS		EXYNOS4_GPA0(6)
+#define GPIO_GPS_CTS_AF		2
+
+#define GPIO_GPS_RTS		EXYNOS4_GPA0(7)
+#define GPIO_GPS_RTS_AF		2
+
+#define GPIO_FLM_RXD		EXYNOS4_GPA1(4)
+#define GPIO_FLM_RXD_AF		2
+
+#define GPIO_FLM_TXD		EXYNOS4_GPA1(5)
+#define GPIO_FLM_TXD_AF		2
+
+#define GPIO_3_TOUCH_SCL	EXYNOS4212_GPM0(0)
+#define GPIO_3_TOUCH_SDA	EXYNOS4_GPL2(3)
+#define GPIO_HDMI_EN		EXYNOS4_GPL0(4)
+#define GPIO_3_TOUCH_INT	EXYNOS4_GPC1(3)
+#define GPIO_TOUCH_EN		EXYNOS4212_GPJ0(3)
+
+#define GPIO_PWM0		EXYNOS4_GPD0(0)
+#define GPIO_PWM1		EXYNOS4_GPD0(1)
+#define GPIO_PWM2		EXYNOS4_GPD0(2)
+#define GPIO_PWM3		EXYNOS4_GPD0(3)
+
+#define GPIO_VIBTONE_EN		EXYNOS4212_GPJ0(6)
+
+#define GPIO_WLAN_EN		EXYNOS4212_GPM3(5)
+#define GPIO_WLAN_EN_AF		1
+#define GPIO_WLAN_HOST_WAKE	EXYNOS4_GPX2(5)
+#define GPIO_WLAN_HOST_WAKE_AF	0xF
+#define GPIO_WLAN_SDIO_CLK	EXYNOS4_GPK3(0)
+#define GPIO_WLAN_SDIO_CLK_AF	2
+#define GPIO_WLAN_SDIO_CMD	EXYNOS4_GPK3(1)
+#define GPIO_WLAN_SDIO_CMD_AF	2
+#define GPIO_WLAN_SDIO_D0	EXYNOS4_GPK3(3)
+#define GPIO_WLAN_SDIO_D0_AF	2
+#define GPIO_WLAN_SDIO_D1	EXYNOS4_GPK3(4)
+#define GPIO_WLAN_SDIO_D1_AF	2
+#define GPIO_WLAN_SDIO_D2	EXYNOS4_GPK3(5)
+#define GPIO_WLAN_SDIO_D2_AF	2
+#define GPIO_WLAN_SDIO_D3	EXYNOS4_GPK3(6)
+#define GPIO_WLAN_SDIO_D3_AF	2
+
+#define GPIO_USB_SEL0		EXYNOS4_GPY0(4)
+#define GPIO_USB_SEL1		EXYNOS4_GPY0(5)
+
+#define GPIO_LCD_22V_EN		EXYNOS4212_GPM4(4)
+#define GPIO_LCD_22V_EN_00		EXYNOS4_GPC0(1)
+
+#define GPIO_ISP_TXD		EXYNOS4212_GPM4(5)
+#define GPIO_ISP_RXD		EXYNOS4212_GPM4(6)
+
+#define GPIO_MHL_SEL		EXYNOS4_GPL0(3)
+
+#define GPIO_MHL_SDA_1_8V	EXYNOS4_GPF0(4)
+#define GPIO_MHL_SCL_1_8V	EXYNOS4_GPF0(6)
+#define GPIO_MHL_SDA_1_8V_00	EXYNOS4_GPB(2)
+#define GPIO_MHL_SCL_1_8V_00	EXYNOS4_GPB(3)
+
+#define GPIO_OTG_EN		EXYNOS4_GPF0(7)
+
+/* charger */
+#define GPIO_CHG_SDA		EXYNOS4212_GPM2(0)
+#define GPIO_CHG_SCL		EXYNOS4212_GPM2(1)
+#define GPIO_TA_EN		EXYNOS4_GPY1(3)
+#define GPIO_TA_nCHG		EXYNOS4_GPL2(1)
+#define GPIO_TA_nCONNECTED	EXYNOS4_GPX1(4)
+
+/* adc */
+#define GPIO_ADC_SCL		EXYNOS4212_GPM4(0)
+#define GPIO_ADC_SDA		EXYNOS4212_GPM4(1)
+#define GPIO_ADC_INT		EXYNOS4_GPX0(1)
+
+/* fuelgauge */
+#define GPIO_FUEL_SCL		EXYNOS4_GPY0(3)
+#define GPIO_FUEL_SDA		EXYNOS4_GPY0(2)
+#define GPIO_FUEL_ALERT		EXYNOS4_GPX2(3)
+#define GPIO_IF_CON_SENSE	EXYNOS4_GPY4(3)
+
+#define GPIO_OLED_ID		EXYNOS4_GPF1(0)
+#define GPIO_ISP_RESET		EXYNOS4_GPF1(3)
+
+#define GPIO_MLCD_RST		EXYNOS4_GPF2(1)
+#define GPIO_UART_SEL		EXYNOS4_GPL2(7)
+#define GPIO_S_LED_I2C_SCL	EXYNOS4_GPF2(6)
+#define GPIO_S_LED_I2C_SDA	EXYNOS4_GPF2(7)
+#define GPIO_OLED_DET		EXYNOS4_GPF3(0)
+
+#define GPIO_PMIC_DVS1		EXYNOS4212_GPM3(0)
+#define GPIO_PMIC_DVS2		EXYNOS4212_GPM3(1)
+
+/* Definitions for Sii 9244B0 */
+#define GPIO_PMIC_DVS3		EXYNOS4212_GPM3(2)
+#define GPIO_BUCK2_SEL		EXYNOS4_GPX2(4)
+#define GPIO_BUCK3_SEL		EXYNOS4_GPX2(0)
+#define GPIO_BUCK4_SEL		EXYNOS4_GPX2(1)
+#define GPIO_MHL_RST		EXYNOS4_GPF3(4)
+#define GPIO_MHL_INT		EXYNOS4_GPF3(5)
+#define GPIO_MHL_INT_AF		S3C_GPIO_SFN(0xF)
+#define GPIO_MHL_WAKE_UP	EXYNOS4212_GPJ1(4)
+
+#define GPIO_RGB_SDA_1_8V	EXYNOS4_GPF0(0)
+#define GPIO_RGB_SCL_1_8V	EXYNOS4_GPF0(1)
+#define GPIO_RGB_INT		EXYNOS4_GPX2(2)
+#define GPIO_VOL_DOWN		EXYNOS4_GPX2(2)
+#define GPIO_VOL_UP		EXYNOS4_GPX3(3)
+
+#define GPIO_CAM_SW_EN		EXYNOS4212_GPJ1(0)
+#define GPIO_TORCH_EN		EXYNOS4212_GPJ1(1)
+#define GPIO_TORCH_SET		EXYNOS4212_GPJ1(2)
+
+#define GPIO_MHL_DSCL_2_8V	EXYNOS4_GPK1(0)
+#define GPIO_MHL_DSDA_2_8V	EXYNOS4_GPK1(2)
+
+#define MHL_INT_IRQ		gpio_to_irq(GPIO_MHL_INT)
+#define MHL_WAKEUP_IRQ		gpio_to_irq(GPIO_MHL_WAKE_UP)
+
+#define GPIO_HDMI_CEC		EXYNOS4_GPX3(6)
+#define GPIO_HDMI_HPD		EXYNOS4_GPX3(7)
+
+#define GPIO_nPOWER		EXYNOS4_GPX2(7)
+#define GPIO_OK_KEY		EXYNOS4_GPX3(5)
+
+#define GPIO_V_BUS_INT		EXYNOS4_GPX2(4)	/* rev0.9 ~ */
+#define GPIO_WPC_INT		EXYNOS4_GPX3(0)
+
+#define GPIO_VIBTONE_PWM	EXYNOS4_GPD0(1)
+
+#define GPIO_VIBTONE_PWM	EXYNOS4_GPD0(1)
+
+#define GPIO_CODEC_SDA_18V	EXYNOS4_GPD0(2)
+#define GPIO_CODEC_SCL_18V	EXYNOS4_GPD0(3)
+#define GPIO_CODEC_SDA_18V_00		EXYNOS4_GPB(0)
+#define GPIO_CODEC_SCL_18V_00		EXYNOS4_GPB(1)
+
+
+#define GPIO_CODEC_LDO_EN	EXYNOS4212_GPM4(4)
+#define GPIO_WM8994_LDO		EXYNOS4212_GPM4(4)
+
+/* Modem Interface GPIOs - M0 HSIC */
+#if !defined(CONFIG_SEC_MODEM_M0_TD)
+#define GPIO_ACTIVE_STATE	EXYNOS4_GPL0(0)
+#define GPIO_PDA_ACTIVE		EXYNOS4_GPL1(0)
+#define GPIO_PHONE_ON		EXYNOS4_GPL2(5)
+#define GPIO_SUSPEND_REQUEST	EXYNOS4212_GPM2(4)
+#define GPIO_CP_REQ_RESET	EXYNOS4212_GPM3(3)
+#define GPIO_GPS_CNTL		EXYNOS4212_GPM3(4)
+#define GPIO_IPC_SLAVE_WAKEUP	EXYNOS4_GPX1(0)
+#define GPIO_IPC_HOST_WAKEUP	EXYNOS4_GPX1(1)
+#define GPIO_CP_DUMP_INT	EXYNOS4_GPX1(2)
+#define GPIO_PHONE_ACTIVE	EXYNOS4_GPX1(6)
+#define GPIO_CP_RST		EXYNOS4_GPX3(2)
+
+#define GPIO_FM_RST EXYNOS4_GPC1(1)
+#else
+
+/* Modem Interface GPIOs - M0 SPI */
+#define GPIO_PDA_ACTIVE	EXYNOS4_GPF1(6)
+#define GPIO_PHONE_ON	EXYNOS4_GPL2(5)
+#define GPIO_PHONE_ACTIVE	EXYNOS4_GPX1(6)
+#define GPIO_AP_CP_INT1	EXYNOS4_GPX0(5)
+#define GPIO_AP_CP_INT2	EXYNOS4_GPX3(5)
+#define GPIO_CP_DUMP_INT	EXYNOS4_GPX1(2)
+#define GPIO_IPC_MRDY	EXYNOS4_GPX0(4)
+#define GPIO_IPC_SRDY	EXYNOS4_GPX1(0)
+#define GPIO_IPC_SUB_MRDY	EXYNOS4_GPX3(2)
+#define GPIO_IPC_SUB_SRDY	EXYNOS4_GPX1(1)
+
+#define GPIO_CP_RST	EXYNOS4_GPF1(1)
+#define GPIO_CP_REQ_RESET	EXYNOS4_GPF1(1)
+#define GPIO_IPC_SLAVE_WAKEUP	EXYNOS4_GPX2(0)
+#define GPIO_IPC_HOST_WAKEUP	EXYNOS4_GPX2(0)
+#define GPIO_SUSPEND_REQUEST	EXYNOS4_GPF1(1)
+#define GPIO_ISP_INT		EXYNOS4_GPF1(1)
+#define GPIO_ACTIVE_STATE	EXYNOS4_GPF1(1)
+
+#define GPIO_FM_RST	EXYNOS4_GPC1(0)
+
+#define IRQ_IPC_SRDY		IRQ_EINT8
+#define IRQ_PHONE_ACTIVE	IRQ_EINT14
+#define IRQ_IPC_SRDY		IRQ_EINT8
+#define IRQ_IPC_SUB_SRDY	IRQ_EINT9
+#define IRQ_CP_DUMP_INT	IRQ_EINT10
+#endif
+
+#define GPIO_OK_KEY_ANDROID	EXYNOS4_GPX1(3)
+
+#define GPIO_FM_INT_REV15	EXYNOS4_GPX1(4)
+#define GPIO_FM_INT_REV07	EXYNOS4_GPX1(3)
+#define GPIO_FM_INT		EXYNOS4_GPX1(3)
+#define GPIO_FM_MIC_SW		EXYNOS4_GPL0(3)
+
+#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE)
+#define GPIO_TDMB_EN		EXYNOS4_GPL0(0)
+#define GPIO_TDMB_INT		EXYNOS4_GPF0(2)
+#define GPIO_TDMB_IRQ		gpio_to_irq(GPIO_TDMB_INT)
+#define GPIO_TDMB_INT_AF	0xf
+#define GPIO_TDMB_SPI_CLK	EXYNOS4_GPC1(1)
+#define GPIO_TDMB_SPI_CS	EXYNOS4_GPC1(2)
+#define GPIO_TDMB_SPI_MISO	EXYNOS4_GPC1(3)
+#define GPIO_TDMB_SPI_MOSI	EXYNOS4_GPC1(4)
+#endif
+
+#if defined(CONFIG_FB_S5P_S6C1372)
+#define GPIO_LCD_EN		EXYNOS4_GPC0(1)
+#define GPIO_LED_BACKLIGHT_PWM	EXYNOS4_GPD0(1)
+#define GPIO_LED_BACKLIGHT_RESET	EXYNOS4212_GPM0(1)
+#define GPIO_LVDS_NSHDN		EXYNOS4212_GPM0(5)
+#endif
+
+#endif /* __MACH_GPIO_MIDAS_H */
diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev00-p4notepq.h b/arch/arm/mach-exynos/include/mach/gpio-rev00-p4notepq.h
new file mode 100644
index 0000000..3c62331
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/gpio-rev00-p4notepq.h
@@ -0,0 +1,336 @@
+#ifndef __MACH_GPIO_MIDAS_H
+#define __MACH_GPIO_MIDAS_H __FILE__
+
+#include <mach/gpio.h>
+
+extern void midas_config_gpio_table(void);
+extern void midas_config_sleep_gpio_table(void);
+
+#define GPIO_eMMC_EN		EXYNOS4_GPK0(2)
+
+#define GPIO_BOOT_MODE		EXYNOS4_GPX0(3)
+
+#define GPIO_FM_I2S_CLK		EXYSNO4_GPC0(0)
+#define GPIO_FM_I2S_SYNC	EXYSNO4_GPC0(2)
+#define GPIO_FM_I2S_DI		EXYSNO4_GPC0(3)
+#define GPIO_FM_I2S_DO		EXYSNO4_GPC0(4)
+
+#define GPIO_IF_PMIC_SDA	EXYNOS4212_GPM2(0)
+#define GPIO_IF_PMIC_SCL	EXYNOS4212_GPM2(1)
+#define GPIO_PMIC_SDA		EXYNOS4_GPB(2)
+#define GPIO_PMIC_SCL		EXYNOS4_GPB(3)
+
+/* Camera */
+#define GPIO_CAM_SPI_SCLK	EXYNOS4_GPB(4)
+#define GPIO_CAM_SPI_SSN	EXYNOS4_GPB(5)
+#define GPIO_CAM_SPI_MISO	EXYNOS4_GPB(6)
+#define GPIO_CAM_SPI_MOSI	EXYNOS4_GPB(7)
+
+#define GPIO_CAM_MCLK		EXYNOS4212_GPJ1(3)
+#define GPIO_VTCAM_MCLK		EXYNOS4212_GPM2(2)
+
+#ifdef CONFIG_VIDEO_ISX012
+#define GPIO_5M_nRST		EXYNOS4_GPL1(1)
+#else
+#define GPIO_3M_nRST		EXYNOS4_GPL1(1)
+#endif
+#define GPIO_ISP_STANDBY	EXYNOS4212_GPM0(1)
+#define GPIO_CAM_IO_EN		EXYNOS4212_GPM0(2)
+#define GPIO_ISP_CORE_EN	EXYNOS4212_GPM0(3)
+#define GPIO_CAM_AF_EN		EXYNOS4212_GPM0(4)
+#ifdef CONFIG_VIDEO_ISX012
+#define GPIO_CAM_EN2		EXYNOS4212_GPJ0(5)
+#define GPIO_CAM_EN1		EXYNOS4212_GPJ0(6)
+#define GPIO_5M_nSTBY		EXYNOS4212_GPJ0(7)
+#else
+#define GPIO_3M_nSTBY		EXYNOS4212_GPM0(6)
+#endif
+#ifdef CONFIG_VIDEO_S5K5CCGX_COMMON
+#define GPIO_2M_nRST		EXYNOS4212_GPM1(6)
+#else
+#define GPIO_VT_CAM_nRST	EXYNOS4212_GPJ1(0)
+#endif
+#define GPIO_CAM_MOVIE_EN	EXYNOS4212_GPM3(6)
+#define GPIO_CAM_FLASH_EN	EXYNOS4212_GPM3(7)
+
+/*
+#define GPIO_8M_CAM_SCL_18V	EXYNOS4212_GPM4(0)
+#define GPIO_8M_CAM_SDA_18V	EXYNOS4212_GPM4(1)
+#define GPIO_8M_CAM_SCL_18V_00	EXYNOS4_GPD1(0)
+#define GPIO_8M_CAM_SDA_18V_00	EXYNOS4_GPD1(1)
+*/
+#define GPIO_VT_CAM_SCL_18V	EXYNOS4212_GPM4(2)
+#define GPIO_2M_nSTBY		EXYNOS4212_GPM4(3)
+#define GPIO_VT_CAM_ID			EXYNOS4_GPF1(2)
+
+/* 30pin Accessory */
+#define GPIO_ACCESSORY_EN		EXYNOS4_GPL2(6)
+#define GPIO_ACCESSORY_OUT_5V	EXYNOS4_GPX3(5)
+#define GPIO_ACCESSORY_INT		EXYNOS4_GPX1(3)
+#define GPIO_DOCK_INT			EXYNOS4_GPX0(4)
+
+/* Sensors*/
+#define GPIO_PS_ALS_SDA_28V	EXYNOS4_GPL0(2)
+#define GPIO_PS_ALS_SCL_28V	EXYNOS4_GPL0(1)
+
+#define GPIO_GYRO_DE		EXYNOS4_GPL2(0)
+#define GPIO_GPS_nRST		EXYNOS4_GPL2(1)
+#define GPIO_GPS_PWR_EN		EXYNOS4_GPL2(2)
+#define GPIO_GYRO_INT		EXYNOS4_GPX0(6)
+
+#define GPIO_GSENSE_SDA_18V	EXYNOS4_GPD1(2)
+#define GPIO_GSENSE_SCL_18V	EXYNOS4_GPD1(3)
+#define GPIO_ACC_INT		EXYNOS4_GPX0(0)
+
+#define GPIO_MSENSOR_INT	EXYNOS4212_GPM4(7)
+#define GPIO_MSENSOR_SDA_18V	EXYNOS4_GPY2(4)
+#define GPIO_MSENSOR_SCL_18V	EXYNOS4_GPY2(5)
+/* Sensors*/
+
+#define GPIO_TF_EN		EXYNOS4_GPY2(0)
+#define GPIO_DET_35		EXYNOS4_GPX0(3)
+
+#define GPIO_MIC_BIAS_EN	EXYNOS4212_GPM0(0)
+#define GPIO_SUB_MIC_BIAS_EN	EXYNOS4_GPF2(0)
+#define GPIO_EAR_MIC_BIAS_EN	EXYNOS4212_GPJ0(3)
+#define GPIO_EAR_SEND_END	EXYNOS4_GPX3(6)
+#define GPIO_LINEOUT_EN		EXYNOS4212_GPJ1(2)
+
+#define GPIO_PMU_RST		EXYNOS4_GPX3(2)
+
+#define GPIO_PMIC_IRQ		EXYNOS4_GPX0(7)
+#define GPIO_IF_PMIC_IRQ	EXYNOS4_GPX1(5)
+
+#define GPIO_BT_EN		EXYNOS4_GPL0(6)
+#define GPIO_BT_WAKE		EXYNOS4_GPX3(1)
+#define GPIO_BT_HOST_WAKE	EXYNOS4_GPX2(6)
+#define IRQ_BT_HOST_WAKE	IRQ_EINT(22)
+
+#define GPIO_BT_RXD		EXYNOS4_GPA0(0)
+#define GPIO_BT_RXD_AF		2
+
+#define GPIO_BT_TXD		EXYNOS4_GPA0(1)
+#define GPIO_BT_TXD_AF		2
+
+#define GPIO_BT_CTS		EXYNOS4_GPA0(2)
+#define GPIO_BT_CTS_AF		2
+
+#define GPIO_BT_RTS		EXYNOS4_GPA0(3)
+#define GPIO_BT_RTS_AF		2
+
+#define GPIO_GPS_RXD		EXYNOS4_GPA0(4)
+#define GPIO_GPS_RXD_AF		2
+
+#define GPIO_GPS_TXD		EXYNOS4_GPA0(5)
+#define GPIO_GPS_TXD_AF		2
+
+#define GPIO_GPS_CTS		EXYNOS4_GPA0(6)
+#define GPIO_GPS_CTS_AF		2
+
+#define GPIO_GPS_RTS		EXYNOS4_GPA0(7)
+#define GPIO_GPS_RTS_AF		2
+
+#define GPIO_FLM_RXD		EXYNOS4_GPA1(4)
+#define GPIO_FLM_RXD_AF		2
+
+#define GPIO_FLM_TXD		EXYNOS4_GPA1(5)
+#define GPIO_FLM_TXD_AF		2
+
+#define GPIO_HDMI_EN		EXYNOS4_GPL0(4)
+
+#define GPIO_PWM0		EXYNOS4_GPD0(0)
+#define GPIO_PWM1		EXYNOS4_GPD0(1)
+#define GPIO_PWM2		EXYNOS4_GPD0(2)
+#define GPIO_PWM3		EXYNOS4_GPD0(3)
+
+#define GPIO_TSP_INT		EXYNOS4212_GPM2(3)
+#define GPIO_TSP_SDA_18V	EXYNOS4_GPA1(2)
+#define GPIO_TSP_SCL_18V	EXYNOS4_GPA1(3)
+#define GPIO_TSP_LDO_ON	EXYNOS4212_GPM4(5)
+#define GPIO_TSP_RST		EXYNOS4_GPL0(5)
+
+#define GPIO_PEN_PDCT_18V	EXYNOS4_GPC1(0)
+#define GPIO_PEN_LDO_EN	EXYNOS4_GPC1(1)
+#define GPIO_PEN_IRQ_18V	EXYNOS4_GPC1(2)
+#define GPIO_PEN_SDA_28V	EXYNOS4_GPC1(3)
+#define GPIO_PEN_SCL_28V	EXYNOS4_GPC1(4)
+
+#define GPIO_nPOWER		EXYNOS4_GPX2(7)
+#define GPIO_VOL_DOWN		EXYNOS4_GPX2(2)
+#define GPIO_VOL_UP		EXYNOS4_GPX3(3)
+
+#define GPIO_VIBTONE_PWM	GPIO_PWM0
+#define GPIO_MOTOR_EN		EXYNOS4_GPL2(4)
+#define GPIO_MOTOR_SDA	EXYNOS4212_GPM1(0)
+#define GPIO_MOTOR_SCL	EXYNOS4212_GPM1(1)
+
+#define GPIO_WLAN_EN		EXYNOS4212_GPM3(5)
+#define GPIO_WLAN_EN_AF		1
+#define GPIO_WLAN_HOST_WAKE	EXYNOS4_GPX2(5)
+#define GPIO_WLAN_HOST_WAKE_AF	0xF
+#define GPIO_WLAN_SDIO_CLK	EXYNOS4_GPK3(0)
+#define GPIO_WLAN_SDIO_CLK_AF	2
+#define GPIO_WLAN_SDIO_CMD	EXYNOS4_GPK3(1)
+#define GPIO_WLAN_SDIO_CMD_AF	2
+#define GPIO_WLAN_SDIO_D0	EXYNOS4_GPK3(3)
+#define GPIO_WLAN_SDIO_D0_AF	2
+#define GPIO_WLAN_SDIO_D1	EXYNOS4_GPK3(4)
+#define GPIO_WLAN_SDIO_D1_AF	2
+#define GPIO_WLAN_SDIO_D2	EXYNOS4_GPK3(5)
+#define GPIO_WLAN_SDIO_D2_AF	2
+#define GPIO_WLAN_SDIO_D3	EXYNOS4_GPK3(6)
+#define GPIO_WLAN_SDIO_D3_AF	2
+
+#define GPIO_LCD_22V_EN		EXYNOS4212_GPM4(4)
+#define GPIO_LCD_22V_EN_00		EXYNOS4_GPC0(1)
+
+#define GPIO_ISP_TXD		EXYNOS4212_GPM4(5)
+#define GPIO_ISP_RXD		EXYNOS4212_GPM4(6)
+
+#define GPIO_IRDA_CONTROL	EXYNOS4_GPL0(3)
+
+#define GPIO_MHL_SDA_1_8V	EXYNOS4_GPY2(2)
+#define GPIO_MHL_SCL_1_8V	EXYNOS4_GPY2(3)
+#define GPIO_MHL_SDA_1_8V_00	EXYNOS4_GPB(2)
+#define GPIO_MHL_SCL_1_8V_00	EXYNOS4_GPB(3)
+
+#define GPIO_OTG_EN		EXYNOS4_GPF0(7)
+
+/* USB/UART switch */
+#define GPIO_USB_SEL0		EXYNOS4_GPY0(4)
+#define GPIO_USB_SEL1		EXYNOS4_GPY0(5)
+#define GPIO_USB_SEL_CP		EXYNOS4212_GPM0(7)
+#define GPIO_UART_SEL		EXYNOS4_GPL2(7)
+
+/* charger */
+#define GPIO_CHG_SDA		EXYNOS4212_GPM2(0)
+#define GPIO_CHG_SCL		EXYNOS4212_GPM2(1)
+#define GPIO_TA_EN		EXYNOS4212_GPM4(2)
+#define GPIO_TA_nCHG		EXYNOS4212_GPM0(3)
+#define GPIO_TA_nCONNECTED	EXYNOS4_GPX1(4)
+
+/* adc */
+#define GPIO_ADC_SCL		EXYNOS4212_GPM4(0)
+#define GPIO_ADC_SDA		EXYNOS4212_GPM4(1)
+#define GPIO_ADC_INT		EXYNOS4_GPX0(1)
+
+/* fuelgauge */
+#define GPIO_FUEL_SCL		EXYNOS4_GPY0(3)
+#define GPIO_FUEL_SDA		EXYNOS4_GPY0(2)
+#define GPIO_FUEL_ALERT		EXYNOS4_GPX2(3)
+#define GPIO_IF_CON_SENSE	EXYNOS4_GPX3(0)
+
+#define GPIO_OLED_ID		EXYNOS4_GPF1(0)
+#define GPIO_ISP_RESET		EXYNOS4_GPF1(3)
+
+#define GPIO_S_LED_I2C_SCL	EXYNOS4_GPF2(6)
+#define GPIO_S_LED_I2C_SDA	EXYNOS4_GPF2(7)
+
+#define GPIO_PMIC_DVS1		EXYNOS4212_GPM3(0)
+#define GPIO_PMIC_DVS2		EXYNOS4212_GPM3(1)
+
+/* Definitions for Sii 9244B0 */
+#define GPIO_PMIC_DVS3		EXYNOS4212_GPM3(2)
+#define GPIO_BUCK2_SEL		EXYNOS4_GPX2(4)
+#define GPIO_BUCK3_SEL		EXYNOS4_GPX2(0)
+#define GPIO_BUCK4_SEL		EXYNOS4_GPX2(1)
+#define GPIO_MHL_RST		EXYNOS4_GPF3(4)
+#define GPIO_MHL_INT		EXYNOS4_GPF3(5)
+#define GPIO_MHL_INT_AF		S3C_GPIO_SFN(0xF)
+#define GPIO_MHL_WAKE_UP	EXYNOS4212_GPJ1(4)
+
+#define GPIO_CAM_SW_EN		EXYNOS4212_GPJ1(0)
+#define GPIO_TORCH_EN		EXYNOS4212_GPJ1(1)
+#define GPIO_TORCH_SET		EXYNOS4212_GPJ1(2)
+
+#define GPIO_MHL_DSCL_2_8V	EXYNOS4_GPK1(0)
+#define GPIO_MHL_DSDA_2_8V	EXYNOS4_GPK1(2)
+
+#define MHL_INT_IRQ		gpio_to_irq(GPIO_MHL_INT)
+#define MHL_WAKEUP_IRQ		gpio_to_irq(GPIO_MHL_WAKE_UP)
+
+#define GPIO_HDMI_CEC		EXYNOS4_GPX3(6)
+#define GPIO_HDMI_HPD		EXYNOS4_GPX3(7)
+
+#define GPIO_CODEC_SDA_18V	EXYNOS4_GPD0(2)
+#define GPIO_CODEC_SCL_18V	EXYNOS4_GPD0(3)
+#define GPIO_CODEC_SDA_18V_00		EXYNOS4_GPB(0)
+#define GPIO_CODEC_SCL_18V_00		EXYNOS4_GPB(1)
+
+
+#define GPIO_CODEC_LDO_EN	EXYNOS4212_GPM4(4)
+#define GPIO_WM8994_LDO		EXYNOS4212_GPM4(4)
+
+/* Modem Interface GPIOs - M0 HSIC */
+#if !defined(CONFIG_SEC_MODEM_M0_TD)
+#define GPIO_ACTIVE_STATE	EXYNOS4_GPL0(0)
+#define GPIO_PDA_ACTIVE		EXYNOS4_GPL1(0)
+#define GPIO_PHONE_ON		EXYNOS4_GPL2(5)
+#define GPIO_SUSPEND_REQUEST	EXYNOS4212_GPM2(4)
+#define GPIO_CP_REQ_RESET	EXYNOS4212_GPM3(3)
+#define GPIO_GPS_CNTL		EXYNOS4212_GPM3(4)
+#define GPIO_IPC_SLAVE_WAKEUP	EXYNOS4_GPX1(0)
+#define GPIO_IPC_HOST_WAKEUP	EXYNOS4_GPX1(1)
+#define GPIO_CP_DUMP_INT	EXYNOS4_GPX1(2)
+#define GPIO_PHONE_ACTIVE	EXYNOS4_GPX1(6)
+#define GPIO_CP_RST		EXYNOS4_GPX3(2)
+#define GPIO_SIM_DETECT		EXYNOS4_GPX1(7)
+#define GPIO_FM_RST EXYNOS4_GPC1(1)
+#define GPIO_AP_DUMP_INT	EXYNOS4212_GPM3(4)
+#else
+
+/* Modem Interface GPIOs - M0 SPI */
+#define GPIO_PDA_ACTIVE	EXYNOS4_GPF1(6)
+#define GPIO_PHONE_ON	EXYNOS4_GPL2(5)
+#define GPIO_PHONE_ACTIVE	EXYNOS4_GPX1(6)
+#define GPIO_AP_CP_INT1	EXYNOS4_GPX0(5)
+#define GPIO_AP_CP_INT2	EXYNOS4_GPX3(5)
+#define GPIO_CP_DUMP_INT	EXYNOS4_GPX1(2)
+#define GPIO_IPC_MRDY	EXYNOS4_GPX0(4)
+#define GPIO_IPC_SRDY	EXYNOS4_GPX1(0)
+#define GPIO_IPC_SUB_MRDY	EXYNOS4_GPX3(2)
+#define GPIO_IPC_SUB_SRDY	EXYNOS4_GPX1(1)
+
+#define GPIO_CP_RST	EXYNOS4_GPF1(1)
+#define GPIO_CP_REQ_RESET	EXYNOS4_GPF1(1)
+#define GPIO_IPC_SLAVE_WAKEUP	EXYNOS4_GPX2(0)
+#define GPIO_IPC_HOST_WAKEUP	EXYNOS4_GPX2(0)
+#define GPIO_SUSPEND_REQUEST	EXYNOS4_GPF1(1)
+#define GPIO_ISP_INT		EXYNOS4_GPF1(1)
+#define GPIO_ACTIVE_STATE	EXYNOS4_GPF1(1)
+
+#define GPIO_FM_RST	EXYNOS4_GPC1(0)
+
+#define IRQ_IPC_SRDY		IRQ_EINT8
+#define IRQ_PHONE_ACTIVE	IRQ_EINT14
+#define IRQ_IPC_SRDY		IRQ_EINT8
+#define IRQ_IPC_SUB_SRDY	IRQ_EINT9
+#define IRQ_CP_DUMP_INT	IRQ_EINT10
+#endif
+
+#define GPIO_OK_KEY_ANDROID	EXYNOS4_GPX1(3)
+
+#define GPIO_FM_INT_REV15	EXYNOS4_GPX1(4)
+#define GPIO_FM_INT_REV07	EXYNOS4_GPX1(3)
+#define GPIO_FM_INT		EXYNOS4_GPX1(3)
+
+#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE)
+#define GPIO_TDMB_EN		EXYNOS4_GPL0(0)
+#define GPIO_TDMB_INT		EXYNOS4_GPF0(2)
+#define GPIO_TDMB_IRQ		gpio_to_irq(GPIO_TDMB_INT)
+#define GPIO_TDMB_INT_AF	0xf
+#define GPIO_TDMB_SPI_CLK	EXYNOS4_GPC1(1)
+#define GPIO_TDMB_SPI_CS	EXYNOS4_GPC1(2)
+#define GPIO_TDMB_SPI_MISO	EXYNOS4_GPC1(3)
+#define GPIO_TDMB_SPI_MOSI	EXYNOS4_GPC1(4)
+#endif
+
+#if defined(CONFIG_FB_S5P_S6C1372)
+#define GPIO_LCD_PCLK	EXYNOS4_GPF0(3)
+#define GPIO_LCD_EN		EXYNOS4_GPC0(1)
+#define GPIO_LED_BACKLIGHT_PWM	EXYNOS4_GPD0(1)
+#define GPIO_LED_BACKLIGHT_RESET	EXYNOS4212_GPM0(1)
+#define GPIO_LVDS_NSHDN		EXYNOS4212_GPM0(5)
+#endif
+
+#endif /* __MACH_GPIO_MIDAS_H */
diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev00-s2plus.h b/arch/arm/mach-exynos/include/mach/gpio-rev00-s2plus.h
new file mode 100644
index 0000000..3423451
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/gpio-rev00-s2plus.h
@@ -0,0 +1,715 @@
+#if 1
+/*
+ * Gpio-rev00-s2plus.h
+ *
+ * 2011. 12.21 Sexykyu
+ *
+ * S2Plus H/W REV00 Board Gpio Setup
+ *
+ */
+#ifndef __MACH_GPIO_MIDAS_H
+#define __MACH_GPIO_MIDAS_H __FILE__
+
+#include <mach/gpio.h>
+
+extern void midas_config_gpio_table(void);
+extern void midas_config_sleep_gpio_table(void);
+
+#define GPIO_DUMMP		EXYNOS4212_GPM3(4)
+
+/*********************** GPA0 Block *********/
+
+#define GPIO_BT_RXD		EXYNOS4_GPA0(0)
+#define GPIO_BT_RXD_AF		2
+
+#define GPIO_BT_TXD		EXYNOS4_GPA0(1)
+#define GPIO_BT_TXD_AF		2
+
+#define GPIO_BT_CTS		EXYNOS4_GPA0(2)
+#define GPIO_BT_CTS_AF		2
+
+#define GPIO_BT_RTS		EXYNOS4_GPA0(3)
+#define GPIO_BT_RTS_AF		2
+
+#define GPIO_GPS_RXD		EXYNOS4_GPA0(4)
+#define GPIO_GPS_RXD_AF		2
+
+#define GPIO_GPS_TXD		EXYNOS4_GPA0(5)
+#define GPIO_GPS_TXD_AF		2
+
+#define GPIO_GPS_CTS		EXYNOS4_GPA0(6)
+#define GPIO_GPS_CTS_AF		2
+
+#define GPIO_GPS_RTS		EXYNOS4_GPA0(7)
+#define GPIO_GPS_RTS_AF		2
+
+
+/*********************** GPA1 Block *********/
+#define GPIO_AP_RXD		EXYNOS4_GPA1(0)
+#define GPIO_AP_TXD		EXYNOS4_GPA1(1)
+
+#define GPIO_TSP_SDA_18V	EXYNOS4_GPA1(2)
+#define GPIO_TSP_SCL_18V	EXYNOS4_GPA1(3)
+
+
+/*********************** GPB Block *********/
+
+#define GPIO_CODEC_SDA_18V	EXYNOS4_GPB(0)
+#define GPIO_CODEC_SCL_18V	EXYNOS4_GPB(1)
+
+#define GPIO_NFC_SDA_18V	EXYNOS4_GPB(2)
+#define GPIO_NFC_SCL_18V	EXYNOS4_GPB(3)
+
+#define GPIO_CAM_SPI_SCLK	EXYNOS4_GPB(4)
+#define GPIO_CAM_SPI_SSN	EXYNOS4_GPB(5)
+#define GPIO_CAM_SPI_MISO	EXYNOS4_GPB(6)
+#define GPIO_CAM_SPI_MOSI	EXYNOS4_GPB(7)
+
+/*********************** GPC0 Block *********/
+
+#define GPIO_REC_PCM_CLK	EXYNOS4_GPC0(0)
+#define GPIO_REC_PCM_SYNC	EXYNOS4_GPC0(2)
+#define GPIO_REC_PCM_IN		EXYNOS4_GPC0(3)
+#define GPIO_REC_PCM_OUT	EXYNOS4_GPC0(4)
+
+
+/*********************** GPC1 Block *********/
+
+#define GPIO_FM_I2S_CLK		EXYNOS4_GPC1(0)
+#define GPIO_FM_RST		EXYNOS4_GPC1(1)
+#define GPIO_FM_I2S_SYNC	EXYNOS4_GPC1(2)
+#define GPIO_FM_I2S_DI		EXYNOS4_GPC1(3)
+#define GPIO_FM_I2S_DO		EXYNOS4_GPC1(4)
+
+
+/*********************** GPD0 Block *********/
+
+#define GPIO_VIBTONE_PWM	EXYNOS4_GPD0(0)
+#define GPIO_PMIC_SDA		EXYNOS4_GPD0(2)
+#define GPIO_PMIC_SCL		EXYNOS4_GPD0(3)
+
+
+/*********************** GPD1 Block *********/
+
+#define GPIO_8M_CAM_SCL_18V	EXYNOS4_GPD1(0)
+#define GPIO_8M_CAM_SDA_18V	EXYNOS4_GPD1(1)
+#define GPIO_GSENSE_SDA_18V	EXYNOS4_GPD1(2)
+#define GPIO_GSENSE_SCL_18V	EXYNOS4_GPD1(3)
+
+
+/*********************** GPF0 Block *********/
+#define GPIO_LCD_HYNC		EXYNOS4_GPF0(0)
+#define GPIO_LCD_VSYNC		EXYNOS4_GPF0(1)
+#define GPIO_LCD_DE		EXYNOS4_GPF0(2)
+#define GPIO_LCD_PCLK		EXYNOS4_GPF0(3)
+#define GPIO_LCD_D_0		EXYNOS4_GPF0(4)
+#define GPIO_LCD_D_1		EXYNOS4_GPF0(5)
+#define GPIO_LCD_D_2		EXYNOS4_GPF0(6)
+#define GPIO_LCD_D_3		EXYNOS4_GPF0(7)
+
+
+/*********************** GPF1 Block *********/
+#define GPIO_LCD_D_4		EXYNOS4_GPF1(0)
+#define GPIO_LCD_D_5		EXYNOS4_GPF1(1)
+#define GPIO_LCD_D_6		EXYNOS4_GPF1(2)
+#define GPIO_LCD_D_7		EXYNOS4_GPF1(3)
+#define GPIO_LCD_D_8		EXYNOS4_GPF1(4)
+#define GPIO_LCD_D_9		EXYNOS4_GPF1(5)
+#define GPIO_LCD_D_10		EXYNOS4_GPF1(6)
+#define GPIO_LCD_D_11		EXYNOS4_GPF1(7)
+
+/*********************** GPF2 Block *********/
+#define GPIO_LCD_D_12		EXYNOS4_GPF2(0)
+#define GPIO_LCD_D_13		EXYNOS4_GPF2(1)
+#define GPIO_LCD_D_14		EXYNOS4_GPF2(2)
+#define GPIO_LCD_D_15		EXYNOS4_GPF2(3)
+#define GPIO_LCD_D_16		EXYNOS4_GPF2(4)
+#define GPIO_LCD_D_17		EXYNOS4_GPF2(5)
+#define GPIO_LCD_D_18		EXYNOS4_GPF2(6)
+#define GPIO_LCD_D_19		EXYNOS4_GPF2(7)
+
+
+/*********************** GPF3 Block *********/
+#define GPIO_LCD_D_20		EXYNOS4_GPF3(0)
+#define GPIO_LCD_D_21		EXYNOS4_GPF3(1)
+#define GPIO_LCD_D_22		EXYNOS4_GPF3(2)
+#define GPIO_LCD_D_23		EXYNOS4_GPF3(3)
+#define GPIO_MHL_RST		EXYNOS4_GPF3(4)
+#define GPIO_MHL_INT		EXYNOS4_GPF3(5)
+#define GPIO_MHL_INT_AF		S3C_GPIO_SFN(0xF)
+
+
+/*********************** GPJ0 Block *********/
+#define GPIO_WLAN_EN		EXYNOS4212_GPJ0(0)
+#define GPIO_WLAN_EN_AF		1
+#define GPIO_USB_SEL		EXYNOS4212_GPJ0(1)
+#define GPIO_EAR_MIC_BIAS_EN	EXYNOS4212_GPJ0(2)
+#define GPIO_CODEC_LDO_EN	EXYNOS4212_GPJ0(4)
+#define GPIO_WM8994_LDO		EXYNOS4212_GPJ0(4) /*old name*/
+#define GPIO_PS_ALS_EN		EXYNOS4212_GPJ0(5)
+#define GPIO_MSENSOR_INT	EXYNOS4212_GPJ0(7)
+
+/*********************** GPJ1 Block *********/
+#define GPIO_3_TOUCH_INT	EXYNOS4212_GPJ1(0)
+#define GPIO_CAM_MCLK		EXYNOS4212_GPJ1(3)
+#define GPIO_MHL_WAKE_UP	EXYNOS4212_GPJ1(4)
+
+
+/*********************** GPK0 Block *********/
+#define GPIO_NAND_CLK		EXYNOS4_GPK0(0)
+#define GPIO_NAND_CMD		EXYNOS4_GPK0(1)
+#define GPIO_eMMC_EN		EXYNOS4_GPK0(2)
+#define GPIO_NAND_D_0		EXYNOS4_GPK0(3)
+#define GPIO_NAND_D_1		EXYNOS4_GPK0(4)
+#define GPIO_NAND_D_2		EXYNOS4_GPK0(5)
+#define GPIO_NAND_D_3		EXYNOS4_GPK0(6)
+
+
+/*********************** GPK1 Block *********/
+#define GPIO_NAND_D_4		EXYNOS4_GPK1(3)
+#define GPIO_NAND_D_5		EXYNOS4_GPK1(4)
+#define GPIO_NAND_D_6		EXYNOS4_GPK1(5)
+#define GPIO_NAND_D_7		EXYNOS4_GPK1(6)
+
+
+/*********************** GPK2 Block *********/
+#define GPIO_T_FLASH_CLK	EXYNOS4_GPK2(0)
+#define GPIO_T_FLASH_CMD	EXYNOS4_GPK2(1)
+
+#define GPIO_T_FLASH_D_0	EXYNOS4_GPK2(3)
+#define GPIO_T_FLASH_D_1	EXYNOS4_GPK2(4)
+#define GPIO_T_FLASH_D_2	EXYNOS4_GPK2(5)
+#define GPIO_T_FLASH_D_3	EXYNOS4_GPK2(6)
+
+/*********************** GPK3 Block *********/
+#define GPIO_WLAN_SDIO_CLK	EXYNOS4_GPK3(0)
+#define GPIO_WLAN_SDIO_CLK_AF	2
+#define GPIO_WLAN_SDIO_CMD	EXYNOS4_GPK3(1)
+#define GPIO_WLAN_SDIO_CMD_AF	2
+#define GPIO_WLAN_SDIO_D0	EXYNOS4_GPK3(3)
+#define GPIO_WLAN_SDIO_D0_AF	2
+#define GPIO_WLAN_SDIO_D1	EXYNOS4_GPK3(4)
+#define GPIO_WLAN_SDIO_D1_AF	2
+#define GPIO_WLAN_SDIO_D2	EXYNOS4_GPK3(5)
+#define GPIO_WLAN_SDIO_D2_AF	2
+#define GPIO_WLAN_SDIO_D3	EXYNOS4_GPK3(6)
+#define GPIO_WLAN_SDIO_D3_AF	2
+
+/*********************** GPL0 Block *********/
+#define GPIO_BUCK2_SEL		EXYNOS4_GPL0(1)
+#define GPIO_BUCK3_SEL		EXYNOS4_GPL0(2)
+#define GPIO_BUCK4_SEL		EXYNOS4_GPL0(3)
+#define GPIO_HDMI_EN		EXYNOS4_GPL0(4)
+#define GPIO_BT_EN		EXYNOS4_GPL0(6)
+
+/*********************** GPL1 Block *********/
+#define GPIO_PS_ALS_SCL_18V	EXYNOS4_GPL1(0)
+#define GPIO_PS_ALS_SDA_18V	EXYNOS4_GPL1(1)
+#define GPIO_RGB_SCL_1_8V	EXYNOS4_GPL1(0)
+#define GPIO_RGB_SDA_1_8V	EXYNOS4_GPL1(1)
+
+/*********************** GPL2 Block *********/
+#define GPIO_GYRO_DE		EXYNOS4_GPL2(0)
+#define GPIO_GPS_nRST		EXYNOS4_GPL2(1)
+#define GPIO_GPS_PWR_EN		EXYNOS4_GPL2(2)
+#define GPIO_WLAN_WAKE		EXYNOS4_GPL2(3)
+#define GPIO_CHG_EN		EXYNOS4_GPL2(4)
+#define GPIO_PHONE_ON		EXYNOS4_GPL2(5)
+#define GPIO_NFC_EN		EXYNOS4_GPL2(6)
+#define GPIO_NFC_FIRMWARE	EXYNOS4_GPL2(7)
+
+
+/*********************** GPM0 Block *********/
+#define GPIO_NFC_CLK_REQ	EXYNOS4212_GPM0(0)
+#define GPIO_ISP_STANDBY	EXYNOS4212_GPM0(1)
+#define GPIO_ISP_CORE_EN	EXYNOS4212_GPM0(3)
+#define GPIO_CAM_VT_nSTBY	EXYNOS4212_GPM0(5)
+#define GPIO_TA_nCONNECTED	EXYNOS4212_GPM0(6)
+#define GPIO_CHG_ING_N		EXYNOS4212_GPM0(7)
+
+
+/*********************** GPM1 Block *********/
+#define GPIO_HW_REV0		EXYNOS4212_GPM1(2)
+#define GPIO_HW_REV1		EXYNOS4212_GPM1(3)
+#define GPIO_HW_REV2		EXYNOS4212_GPM1(4)
+#define GPIO_HW_REV3		EXYNOS4212_GPM1(5)
+#define GPIO_CAM_VT_nRST	EXYNOS4212_GPM1(6)
+
+
+/*********************** GPM2 Block *********/
+
+#define GPIO_IF_PMIC_SDA	EXYNOS4212_GPM2(0)
+#define GPIO_IF_PMIC_SCL	EXYNOS4212_GPM2(1)
+#define GPIO_TP_VT_CAM_MCLK	EXYNOS4212_GPM2(2)
+#define GPIO_TSP_INT		EXYNOS4212_GPM2(3)
+#define GPIO_SUSPEND_REQUEST	EXYNOS4212_GPM2(4)
+
+
+/*********************** GPM3 Block *********/
+#define GPIO_PMIC_DVS1		EXYNOS4212_GPM3(0)
+#define GPIO_PMIC_DVS2		EXYNOS4212_GPM3(1)
+#define GPIO_PMIC_DVS3		EXYNOS4212_GPM3(2)
+#define GPIO_CP_REQ_RESET	EXYNOS4212_GPM3(3)
+
+
+/*********************** GPM4 Block *********/
+#define GPIO_3_TOUCH_SCL	EXYNOS4212_GPM4(0)
+#define GPIO_3_TOUCH_SDA	EXYNOS4212_GPM4(1)
+#define GPIO_VT_CAM_SCL_18V	EXYNOS4212_GPM4(2)
+#define GPIO_VT_CAM_SDA_18V	EXYNOS4212_GPM4(3)
+
+#define GPIO_MIC_BIAS_EN	EXYNOS4212_GPM4(5)
+#define GPIO_MIC_BIAS_EN_00	EXYNOS4212_GPM4(5)
+#define GPIO_SUB_MIC_BIAS_EN	EXYNOS4212_GPM4(6)
+#define GPIO_SUB_MIC_BIAS_EN_00	EXYNOS4212_GPM4(6)
+
+
+/*********************** GPX0 Block *********/
+#define GPIO_ACC_INT		EXYNOS4_GPX0(0)
+#define GPIO_DET_35		EXYNOS4_GPX0(1)
+#define GPIO_PS_ALS_INT		EXYNOS4_GPX0(2)
+#define GPIO_BOOT_MODE		EXYNOS4_GPX0(3)
+#define GPIO_GYRO_INT		EXYNOS4_GPX0(4)
+#define GPIO_OLED_DET		EXYNOS4_GPX0(5)
+#define GPIO_PMIC_IRQ		EXYNOS4_GPX0(7)
+
+
+/*********************** GPX1 Block *********/
+#define GPIO_IPC_SLAVE_WAKEUP	EXYNOS4_GPX1(0)
+#define GPIO_IPC_HOST_WAKEUP	EXYNOS4_GPX1(1)
+#define GPIO_CP_DUMP_INT	EXYNOS4_GPX1(2)
+#define GPIO_FM_INT		EXYNOS4_GPX1(3)
+#define GPIO_FM_INT_REV07	EXYNOS4_GPX1(3) /*old name*/
+#define GPIO_BARO_INT		EXYNOS4_GPX1(4)
+#define GPIO_IF_PMIC_IRQ	EXYNOS4_GPX1(5)
+#define GPIO_PHONE_ACTIVE	EXYNOS4_GPX1(6)
+#define GPIO_NFC_IRQ		EXYNOS4_GPX1(7)
+
+
+/*********************** GPX2 Block *********/
+#define GPIO_VOL_UP		GPIO_DUMMP
+#define GPIO_VOL_UP_00		EXYNOS4_GPX2(2)
+#define GPIO_FUEL_ALERT		EXYNOS4_GPX2(3)
+#define GPIO_ADC_INT		EXYNOS4_GPX2(4)
+#define GPIO_WLAN_HOST_WAKE	EXYNOS4_GPX2(5)
+#define GPIO_WLAN_HOST_WAKE_AF	0xF
+#define GPIO_BT_HOST_WAKE	EXYNOS4_GPX2(6)
+#define GPIO_nPOWER		EXYNOS4_GPX2(7)
+
+
+
+/*********************** GPX3 Block *********/
+#define GPIO_ISP_INT		EXYNOS4_GPX3(0)
+#define GPIO_BT_WAKE		EXYNOS4_GPX3(1)
+#define GPIO_CP_RST		EXYNOS4_GPX3(2)
+#define GPIO_VOL_DOWN		GPIO_DUMMP
+#define GPIO_VOL_DOWN_00	EXYNOS4_GPX3(3)
+#define GPIO_T_FLASH_DETECT	EXYNOS4_GPX3(4)
+#define GPIO_OK_KEY		EXYNOS4_GPX3(5)
+#define GPIO_EAR_SEND_END	EXYNOS4_GPX3(6)
+
+#define GPIO_HDMI_CEC		EXYNOS4_GPX3(6)
+#define GPIO_HDMI_HPD		EXYNOS4_GPX3(7)
+
+/*********************** GPY0 Block *********/
+#define GPIO_ADC_SCL		EXYNOS4_GPY0(2)
+#define GPIO_ADC_SDA		EXYNOS4_GPY0(3)
+
+/*********************** GPY2 Block *********/
+#define GPIO_TF_EN		EXYNOS4_GPY2(0)
+#define GPIO_BSENSE_SDA_18V	EXYNOS4_GPY2(2)
+#define GPIO_BSENSE_SCL_18V	EXYNOS4_GPY2(3)
+#define GPIO_MSENSOR_SDA_18V	EXYNOS4_GPY2(4)
+#define GPIO_MSENSOR_SCL_18V	EXYNOS4_GPY2(5)
+
+
+/*********************** GPY3 Block *********/
+
+#define GPIO_MHL_SDA_1_8V	EXYNOS4_GPY3(0)
+#define GPIO_MHL_SDA_1_8V_00	EXYNOS4_GPB(2)
+#define GPIO_LCD_SCLK		EXYNOS4_GPY3(1)
+#define GPIO_MHL_SCL_1_8V	EXYNOS4_GPY3(2)
+#define GPIO_MHL_SCL_1_8V_00	EXYNOS4_GPB(3)
+#define GPIO_LCD_SDI		EXYNOS4_GPY3(3)
+#define GPIO_OLED_ID		EXYNOS4_GPY3(4)
+#define GPIO_ACTIVE_STATE	EXYNOS4_GPY3(5)
+#define GPIO_ISP_RESET		EXYNOS4_GPY3(7)
+
+
+/*********************** GPY4 Block *********/
+#define GPIO_FUEL_SDA		EXYNOS4_GPY4(0)
+#define GPIO_FUEL_SCL		EXYNOS4_GPY4(1)
+#define GPIO_PDA_ACTIVE	EXYNOS4_GPY4(2)
+#define GPIO_LCD_nCS		EXYNOS4_GPY4(3)
+#define GPIO_3_TOUCH_EN	EXYNOS4_GPY4(4)
+#define GPIO_MLCD_RST		EXYNOS4_GPY4(5)
+#define GPIO_MHL_SEL		EXYNOS4_GPY4(6)
+#define GPIO_UART_SEL		EXYNOS4_GPY4(7)
+
+
+/****************** DUMMP ********************/
+#define GPIO_MHL_DSDA_2_8V	GPIO_DUMMP
+#define GPIO_MHL_DSCL_2_8V	GPIO_DUMMP
+#define GPIO_WPC_INT		GPIO_DUMMP
+#define GPIO_OTG_EN		GPIO_DUMMP /*don't used pin*/
+#define GPIO_CAM_IO_EN		GPIO_DUMMP
+#define GPIO_VTCAM_MCLK		GPIO_DUMMP
+#define GPIO_CAM_AF_EN		GPIO_DUMMP
+#define GPIO_FLM_RXD		GPIO_DUMMP
+#define GPIO_FLM_RXD_AF		2
+#define GPIO_FLM_TXD		GPIO_DUMMP
+#define GPIO_FLM_TXD_AF		2
+#define GPIO_GPS_CNTL		GPIO_DUMMP
+#define GPIO_PS_ALS_SDA_28V	GPIO_DUMMP
+#define GPIO_PS_ALS_SCL_28V	GPIO_DUMMP
+#define MHL_INT_IRQ		gpio_to_irq(GPIO_MHL_INT)
+#define MHL_WAKEUP_IRQ		gpio_to_irq(GPIO_MHL_WAKE_UP)
+#define IRQ_BT_HOST_WAKE	IRQ_EINT(22)
+
+
+
+#endif /* __MACH_GPIO_MIDAS_H */
+
+#else
+
+/* linux/arch/arm/mach-exynos/include/mach/gpio-exynos4.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * S2Plus GPIO common lib support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *  
+ */
+#ifndef __MACH_GPIO_MIDAS_H
+#define __MACH_GPIO_MIDAS_H __FILE__
+
+#include <mach/gpio.h>
+
+extern void midas_config_gpio_table(void);
+extern void midas_config_sleep_gpio_table(void);
+
+#define GPIO_DUMMP		EXYNOS4212_GPM3(4)
+
+
+#define GPIO_BT_RXD		EXYNOS4_GPA0(0)
+#define GPIO_BT_RXD_AF		2
+
+#define GPIO_BT_TXD		EXYNOS4_GPA0(1)
+#define GPIO_BT_TXD_AF		2
+
+#define GPIO_BT_CTS		EXYNOS4_GPA0(2)
+#define GPIO_BT_CTS_AF		2
+
+#define GPIO_BT_RTS		EXYNOS4_GPA0(3)
+#define GPIO_BT_RTS_AF		2
+
+#define GPIO_GPS_RXD		EXYNOS4_GPA0(4)
+#define GPIO_GPS_RXD_AF		2
+
+#define GPIO_GPS_TXD		EXYNOS4_GPA0(5)
+#define GPIO_GPS_TXD_AF		2
+
+#define GPIO_GPS_CTS		EXYNOS4_GPA0(6)
+#define GPIO_GPS_CTS_AF		2
+
+#define GPIO_GPS_RTS		EXYNOS4_GPA0(7)
+#define GPIO_GPS_RTS_AF		2
+
+
+#define GPIO_AP_RXD		EXYNOS4_GPA1(0)
+#define GPIO_AP_TXD		EXYNOS4_GPA1(1)
+
+#define GPIO_TSP_SDA_18V	EXYNOS4_GPA1(2)
+#define GPIO_TSP_SCL_18V	EXYNOS4_GPA1(3)
+
+
+
+#define GPIO_CODEC_SDA_18V	EXYNOS4_GPB(0)
+#define GPIO_CODEC_SCL_18V	EXYNOS4_GPB(1)
+
+#define GPIO_NFC_SDA_18V	EXYNOS4_GPB(2)
+#define GPIO_NFC_SCL_18V	EXYNOS4_GPB(3)
+
+#define GPIO_CAM_SPI_SCLK	EXYNOS4_GPB(4)
+#define GPIO_CAM_SPI_SSN	EXYNOS4_GPB(5)
+#define GPIO_CAM_SPI_MISO	EXYNOS4_GPB(6)
+#define GPIO_CAM_SPI_MOSI	EXYNOS4_GPB(7)
+
+
+#define GPIO_REC_PCM_CLK	EXYNOS4_GPC0(0)
+#define GPIO_REC_PCM_SYNC	EXYNOS4_GPC0(2)
+#define GPIO_REC_PCM_IN		EXYNOS4_GPC0(3)
+#define GPIO_REC_PCM_OUT	EXYNOS4_GPC0(4)
+
+
+
+#define GPIO_FM_I2S_CLK		EXYNOS4_GPC1(0)
+#define GPIO_FM_RST		EXYNOS4_GPC1(1)
+#define GPIO_FM_I2S_SYNC	EXYNOS4_GPC1(2)
+#define GPIO_FM_I2S_DI		EXYNOS4_GPC1(3)
+#define GPIO_FM_I2S_DO		EXYNOS4_GPC1(4)
+
+
+
+#define GPIO_VIBTONE_PWM	EXYNOS4_GPD0(0)
+#define GPIO_PMIC_SDA		EXYNOS4_GPD0(2)
+#define GPIO_PMIC_SCL		EXYNOS4_GPD0(3)
+
+
+
+#define GPIO_8M_CAM_SCL_18V	EXYNOS4_GPD1(0)
+#define GPIO_8M_CAM_SDA_18V	EXYNOS4_GPD1(1)
+#define GPIO_GSENSE_SDA_18V	EXYNOS4_GPD1(2)
+#define GPIO_GSENSE_SCL_18V	EXYNOS4_GPD1(3)
+
+
+#define GPIO_LCD_HYNC		EXYNOS4_GPF0(0)
+#define GPIO_LCD_VSYNC		EXYNOS4_GPF0(1)
+#define GPIO_LCD_DE		EXYNOS4_GPF0(2)
+#define GPIO_LCD_PCLK		EXYNOS4_GPF0(3)
+#define GPIO_LCD_D_0		EXYNOS4_GPF0(4)
+#define GPIO_LCD_D_1		EXYNOS4_GPF0(5)
+#define GPIO_LCD_D_2		EXYNOS4_GPF0(6)
+#define GPIO_LCD_D_3		EXYNOS4_GPF0(7)
+
+
+#define GPIO_LCD_D_4		EXYNOS4_GPF1(0)
+#define GPIO_LCD_D_5		EXYNOS4_GPF1(1)
+#define GPIO_LCD_D_6		EXYNOS4_GPF1(2)
+#define GPIO_LCD_D_7		EXYNOS4_GPF1(3)
+#define GPIO_LCD_D_8		EXYNOS4_GPF1(4)
+#define GPIO_LCD_D_9		EXYNOS4_GPF1(5)
+#define GPIO_LCD_D_10		EXYNOS4_GPF1(6)
+#define GPIO_LCD_D_11		EXYNOS4_GPF1(7)
+
+#define GPIO_LCD_D_12		EXYNOS4_GPF2(0)
+#define GPIO_LCD_D_13		EXYNOS4_GPF2(1)
+#define GPIO_LCD_D_14		EXYNOS4_GPF2(2)
+#define GPIO_LCD_D_15		EXYNOS4_GPF2(3)
+#define GPIO_LCD_D_16		EXYNOS4_GPF2(4)
+#define GPIO_LCD_D_17		EXYNOS4_GPF2(5)
+#define GPIO_LCD_D_18		EXYNOS4_GPF2(6)
+#define GPIO_LCD_D_19		EXYNOS4_GPF2(7)
+
+
+#define GPIO_LCD_D_20		EXYNOS4_GPF3(0)
+#define GPIO_LCD_D_21		EXYNOS4_GPF3(1)
+#define GPIO_LCD_D_22		EXYNOS4_GPF3(2)
+#define GPIO_LCD_D_23		EXYNOS4_GPF3(3)
+#define GPIO_MHL_RST		EXYNOS4_GPF3(4)
+#define GPIO_MHL_INT		EXYNOS4_GPF3(5)
+#define GPIO_MHL_INT_AF		S3C_GPIO_SFN(0xF)
+
+
+#define GPIO_WLAN_EN		EXYNOS4212_GPJ0(0)
+#define GPIO_WLAN_EN_AF		1
+#define GPIO_USB_SEL		EXYNOS4212_GPJ0(1)
+#define GPIO_EAR_MIC_BIAS_EN	EXYNOS4212_GPJ0(2)
+#define GPIO_CODEC_LDO_EN	EXYNOS4212_GPJ0(4)
+#define GPIO_WM8994_LDO		EXYNOS4212_GPJ0(4) 
+#define GPIO_PS_ALS_EN		EXYNOS4212_GPJ0(5)
+#define GPIO_MSENSOR_INT	EXYNOS4212_GPJ0(7)
+
+#define GPIO_3_TOUCH_INT	EXYNOS4212_GPJ1(0)
+#define GPIO_CAM_MCLK		EXYNOS4212_GPJ1(3)
+#define GPIO_MHL_WAKE_UP	EXYNOS4212_GPJ1(4)
+
+
+#define GPIO_NAND_CLK		EXYNOS4_GPK0(0)
+#define GPIO_NAND_CMD		EXYNOS4_GPK0(1)
+#define GPIO_eMMC_EN		EXYNOS4_GPK0(2)
+#define GPIO_NAND_D_0		EXYNOS4_GPK0(3)
+#define GPIO_NAND_D_1		EXYNOS4_GPK0(4)
+#define GPIO_NAND_D_2		EXYNOS4_GPK0(5)
+#define GPIO_NAND_D_3		EXYNOS4_GPK0(6)
+
+
+#define GPIO_NAND_D_4		EXYNOS4_GPK1(3)
+#define GPIO_NAND_D_5		EXYNOS4_GPK1(4)
+#define GPIO_NAND_D_6		EXYNOS4_GPK1(5)
+#define GPIO_NAND_D_7		EXYNOS4_GPK1(6)
+
+
+#define GPIO_T_FLASH_CLK	EXYNOS4_GPK2(0)
+#define GPIO_T_FLASH_CMD	EXYNOS4_GPK2(1)
+
+#define GPIO_T_FLASH_D_0	EXYNOS4_GPK2(3)
+#define GPIO_T_FLASH_D_1	EXYNOS4_GPK2(4)
+#define GPIO_T_FLASH_D_2	EXYNOS4_GPK2(5)
+#define GPIO_T_FLASH_D_3	EXYNOS4_GPK2(6)
+
+#define GPIO_WLAN_SDIO_CLK	EXYNOS4_GPK3(0)
+#define GPIO_WLAN_SDIO_CLK_AF	2
+#define GPIO_WLAN_SDIO_CMD	EXYNOS4_GPK3(1)
+#define GPIO_WLAN_SDIO_CMD_AF	2
+#define GPIO_WLAN_SDIO_D0	EXYNOS4_GPK3(3)
+#define GPIO_WLAN_SDIO_D0_AF	2
+#define GPIO_WLAN_SDIO_D1	EXYNOS4_GPK3(4)
+#define GPIO_WLAN_SDIO_D1_AF	2
+#define GPIO_WLAN_SDIO_D2	EXYNOS4_GPK3(5)
+#define GPIO_WLAN_SDIO_D2_AF	2
+#define GPIO_WLAN_SDIO_D3	EXYNOS4_GPK3(6)
+#define GPIO_WLAN_SDIO_D3_AF	2
+
+#define GPIO_BUCK2_SEL		EXYNOS4_GPL0(1)
+#define GPIO_BUCK3_SEL		EXYNOS4_GPL0(2)
+#define GPIO_BUCK4_SEL		EXYNOS4_GPL0(3)
+#define GPIO_HDMI_EN		EXYNOS4_GPL0(4)
+#define GPIO_BT_EN		EXYNOS4_GPL0(6)
+
+#define GPIO_PS_ALS_SCL_18V	EXYNOS4_GPL1(0)
+#define GPIO_PS_ALS_SDA_18V	EXYNOS4_GPL1(1)
+#define GPIO_RGB_SCL_1_8V	EXYNOS4_GPL1(0)
+#define GPIO_RGB_SDA_1_8V	EXYNOS4_GPL1(1)
+
+#define GPIO_GYRO_DE		EXYNOS4_GPL2(0)
+#define GPIO_GPS_nRST		EXYNOS4_GPL2(1)
+#define GPIO_GPS_PWR_EN		EXYNOS4_GPL2(2)
+#define GPIO_WLAN_WAKE		EXYNOS4_GPL2(3)
+#define GPIO_PHONE_ON		EXYNOS4_GPL2(5)
+#define GPIO_NFC_EN		EXYNOS4_GPL2(6)
+#define GPIO_NFC_FIRMWARE	EXYNOS4_GPL2(7)
+
+
+#define GPIO_NFC_CLK_REQ	EXYNOS4212_GPM0(0)
+#define GPIO_ISP_STANDBY	EXYNOS4212_GPM0(1)
+#define GPIO_ISP_CORE_EN	EXYNOS4212_GPM0(3)
+#define GPIO_CAM_VT_nSTBY	EXYNOS4212_GPM0(5)
+
+
+#define GPIO_HW_REV0		EXYNOS4212_GPM1(2)
+#define GPIO_HW_REV1		EXYNOS4212_GPM1(3)
+#define GPIO_HW_REV2		EXYNOS4212_GPM1(4)
+#define GPIO_HW_REV3		EXYNOS4212_GPM1(5)
+#define GPIO_CAM_VT_nRST	EXYNOS4212_GPM1(6)
+
+
+
+#define GPIO_IF_PMIC_SDA	EXYNOS4212_GPM2(0)
+#define GPIO_IF_PMIC_SCL	EXYNOS4212_GPM2(1)
+#define GPIO_TP_VT_CAM_MCLK	EXYNOS4212_GPM2(2)
+#define GPIO_TSP_INT		EXYNOS4212_GPM2(3)
+#define GPIO_SUSPEND_REQUEST	EXYNOS4212_GPM2(4)
+
+
+#define GPIO_PMIC_DVS1		EXYNOS4212_GPM3(0)
+#define GPIO_PMIC_DVS2		EXYNOS4212_GPM3(1)
+#define GPIO_PMIC_DVS3		EXYNOS4212_GPM3(2)
+#define GPIO_CP_REQ_RESET	EXYNOS4212_GPM3(3)
+
+
+#define GPIO_3_TOUCH_SCL	EXYNOS4212_GPM4(0)
+#define GPIO_3_TOUCH_SDA	EXYNOS4212_GPM4(1)
+#define GPIO_VT_CAM_SCL_18V	EXYNOS4212_GPM4(2)
+#define GPIO_VT_CAM_SDA_18V	EXYNOS4212_GPM4(3)
+
+#define GPIO_MIC_BIAS_EN	EXYNOS4212_GPM4(5)
+#define GPIO_MIC_BIAS_EN_00	EXYNOS4212_GPM4(5)
+#define GPIO_SUB_MIC_BIAS_EN	EXYNOS4212_GPM4(6)
+#define GPIO_SUB_MIC_BIAS_EN_00	EXYNOS4212_GPM4(6)
+
+
+#define GPIO_ACC_INT		EXYNOS4_GPX0(0)
+#define GPIO_DET_35		EXYNOS4_GPX0(1)
+#define GPIO_PS_ALS_INT		EXYNOS4_GPX0(2)
+#define GPIO_BOOT_MODE		EXYNOS4_GPX0(3)
+#define GPIO_GYRO_INT		EXYNOS4_GPX0(4)
+#define GPIO_OLED_DET		EXYNOS4_GPX0(5)
+#define GPIO_PMIC_IRQ		EXYNOS4_GPX0(7)
+
+
+#define GPIO_IPC_SLAVE_WAKEUP	EXYNOS4_GPX1(0)
+#define GPIO_IPC_HOST_WAKEUP	EXYNOS4_GPX1(1)
+#define GPIO_CP_DUMP_INT	EXYNOS4_GPX1(2)
+#define GPIO_FM_INT		EXYNOS4_GPX1(3)
+#define GPIO_FM_INT_REV07	EXYNOS4_GPX1(3) 
+#define GPIO_BARO_INT		EXYNOS4_GPX1(4)
+#define GPIO_IF_PMIC_IRQ	EXYNOS4_GPX1(5)
+#define GPIO_PHONE_ACTIVE	EXYNOS4_GPX1(6)
+#define GPIO_NFC_IRQ		EXYNOS4_GPX1(7)
+
+
+#define GPIO_VOL_UP		GPIO_DUMMP
+#define GPIO_VOL_UP_00		EXYNOS4_GPX2(2)
+#define GPIO_FUEL_ALERT		EXYNOS4_GPX2(3)
+#define GPIO_ADC_INT		EXYNOS4_GPX2(4)
+#define GPIO_WLAN_HOST_WAKE	EXYNOS4_GPX2(5)
+#define GPIO_WLAN_HOST_WAKE_AF	0xF
+#define GPIO_BT_HOST_WAKE	EXYNOS4_GPX2(6)
+#define GPIO_nPOWER		EXYNOS4_GPX2(7)
+
+
+
+#define GPIO_WPC_INT		EXYNOS4_GPX3(0)
+#define GPIO_BT_WAKE		EXYNOS4_GPX3(1)
+#define GPIO_CP_RST		EXYNOS4_GPX3(2)
+#define GPIO_VOL_DOWN		GPIO_DUMMP
+#define GPIO_VOL_DOWN_00	EXYNOS4_GPX3(3)
+#define GPIO_T_FLASH_DETECT	EXYNOS4_GPX3(4)
+#define GPIO_OK_KEY		EXYNOS4_GPX3(5)
+#define GPIO_EAR_SEND_END	EXYNOS4_GPX3(6)
+
+#define GPIO_HDMI_CEC		EXYNOS4_GPX3(6)
+#define GPIO_HDMI_HPD		EXYNOS4_GPX3(7)
+
+
+#define GPIO_ADC_SCL		EXYNOS4_GPY0(2)
+#define GPIO_ADC_SDA		EXYNOS4_GPY0(3)
+
+
+#define GPIO_TF_EN		EXYNOS4_GPY2(0)
+#define GPIO_BSENSE_SDA_18V	EXYNOS4_GPY2(2)
+#define GPIO_BENSE_SCL_18V	EXYNOS4_GPY2(3)
+#define GPIO_MSENSOR_SDA_18V	EXYNOS4_GPY2(4)
+#define GPIO_MSENSOR_SCL_18V	EXYNOS4_GPY2(5)
+
+
+
+#define GPIO_MHL_SDA_1_8V	GPIO_DUMMP
+#define GPIO_MHL_SDA_1_8V_00	EXYNOS4_GPY3(0)
+#define GPIO_LCD_SCLK		EXYNOS4_GPY3(1)
+#define GPIO_MHL_SCL_1_8V	GPIO_DUMMP
+#define GPIO_MHL_SCL_1_8V_00	EXYNOS4_GPY3(2)
+#define GPIO_LCD_SDI		EXYNOS4_GPY3(3)
+#define GPIO_OLED_ID		EXYNOS4_GPY3(4)
+#define GPIO_ACTIVE_STATE	EXYNOS4_GPY3(5)
+#define GPIO_ISP_RESET		EXYNOS4_GPY3(7)
+
+
+#define GPIO_FUEL_SDA		EXYNOS4_GPY4(0)
+#define GPIO_FUEL_SCL		EXYNOS4_GPY4(1)
+#define GPIO_PDA_ACTIVE	EXYNOS4_GPY4(2)
+#define GPIO_LCD_nCS		EXYNOS4_GPY4(3)
+#define GPIO_3_TOUCH_EN	EXYNOS4_GPY4(4)
+#define GPIO_MLCD_RST		EXYNOS4_GPY4(5)
+#define GPIO_MHL_SEL		EXYNOS4_GPY4(6)
+#define GPIO_UART_SEL		EXYNOS4_GPY4(7)
+
+
+
+#define GPIO_MHL_DSCL_2_8V	GPIO_DUMMP
+#define GPIO_MHL_DSDA_2_8V	GPIO_DUMMP
+#define GPIO_OTG_EN		GPIO_DUMMP 
+#define GPIO_CAM_IO_EN		GPIO_DUMMP
+#define GPIO_VTCAM_MCLK		GPIO_DUMMP
+#define GPIO_CAM_AF_EN		GPIO_DUMMP
+#define GPIO_FLM_RXD		GPIO_DUMMP
+#define GPIO_FLM_RXD_AF		2
+#define GPIO_FLM_TXD		GPIO_DUMMP
+#define GPIO_FLM_TXD_AF		2
+#define GPIO_GPS_CNTL		GPIO_DUMMP
+#define GPIO_PS_ALS_SDA_28V	GPIO_DUMMP
+#define GPIO_PS_ALS_SCL_28V	GPIO_DUMMP
+#define MHL_INT_IRQ		gpio_to_irq(GPIO_MHL_INT)
+#define MHL_WAKEUP_IRQ		gpio_to_irq(GPIO_MHL_WAKE_UP)
+#define IRQ_BT_HOST_WAKE	IRQ_EINT(22)
+
+
+
+#endif /* __MACH_GPIO_MIDAS_H */
+
+#endif
diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev00-t0.h b/arch/arm/mach-exynos/include/mach/gpio-rev00-t0.h
new file mode 100644
index 0000000..13fdb3d
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/gpio-rev00-t0.h
@@ -0,0 +1,322 @@
+#ifndef __MACH_GPIO_MIDAS_H
+#define __MACH_GPIO_MIDAS_H __FILE__
+
+#include <mach/gpio.h>
+
+extern void midas_config_gpio_table(void);
+extern void midas_config_sleep_gpio_table(void);
+
+#define GPIO_eMMC_EN		EXYNOS4_GPK0(2)
+
+#define GPIO_BOOT_MODE		EXYNOS4_GPX0(3)
+
+#define GPIO_FM_I2S_CLK		EXYSNO4_GPC0(0)
+#define GPIO_FM_I2S_SYNC	EXYSNO4_GPC0(2)
+#define GPIO_FM_I2S_DI		EXYSNO4_GPC0(3)
+#define GPIO_FM_I2S_DO		EXYSNO4_GPC0(4)
+
+#define GPIO_IF_PMIC_SDA	EXYNOS4212_GPM2(0)
+#define GPIO_IF_PMIC_SCL	EXYNOS4212_GPM2(1)
+#define GPIO_PMIC_SDA		EXYNOS4_GPB(2)
+#define GPIO_PMIC_SCL		EXYNOS4_GPB(3)
+
+#define GPIO_ADC_SCL		EXYNOS4_GPY0(2)
+#define GPIO_ADC_SDA		EXYNOS4_GPY0(3)
+#define GPIO_ADC_INT		EXYNOS4_GPX2(4)	/* rev0.0, 0.1 */
+
+#define GPIO_CAM_SPI_SCLK	EXYNOS4_GPB(4)
+#define GPIO_CAM_SPI_SSN	EXYNOS4_GPB(5)
+#define GPIO_CAM_SPI_MISO	EXYNOS4_GPB(6)
+#define GPIO_CAM_SPI_MOSI	EXYNOS4_GPB(7)
+
+#define GPIO_CAM_MCLK		EXYNOS4212_GPJ1(3)
+#define GPIO_VTCAM_MCLK		EXYNOS4212_GPM2(2)
+
+#define GPIO_ISP_STANDBY	EXYNOS4212_GPM0(1)
+#define GPIO_CAM_IO_EN		EXYNOS4212_GPM0(2)
+#define GPIO_ISP_CORE_EN	EXYNOS4212_GPM0(3)
+#define GPIO_CAM_AF_EN		EXYNOS4212_GPM0(4)
+#define GPIO_CAM_VT_nRST	EXYNOS4212_GPM1(6)
+
+#if 1
+#define GPIO_8M_CAM_SCL_18V	EXYNOS4_GPD1(0)
+#define GPIO_8M_CAM_SDA_18V	EXYNOS4_GPD1(1)
+#else
+#define GPIO_8M_CAM_SCL_18V	EXYNOS4212_GPM4(0)
+#define GPIO_8M_CAM_SDA_18V	EXYNOS4212_GPM4(1)
+#define GPIO_8M_CAM_SCL_18V_00	EXYNOS4_GPD1(0)
+#define GPIO_8M_CAM_SDA_18V_00	EXYNOS4_GPD1(1)
+#endif
+
+#define GPIO_VT_CAM_SCL_18V	EXYNOS4212_GPM4(2)
+#define GPIO_VT_CAM_SDA_18V	EXYNOS4212_GPM4(3)
+#define GPIO_VT_CAM_ID		EXYNOS4_GPF1(2)
+
+/* Sensors & NFC*/
+#define GPIO_PS_ALS_EN		EXYNOS4212_GPJ0(5)
+#define GPIO_PS_ALS_SDA_28V	EXYNOS4_GPK1(1)
+#define GPIO_PS_ALS_SCL_28V	EXYNOS4_GPK2(2)
+#define GPIO_PS_ALS_INT		EXYNOS4_GPX0(2)
+
+#define GPIO_ACC_INT		EXYNOS4_GPX0(0)
+
+#define GPIO_GYRO_DE		EXYNOS4_GPL2(0)
+#define GPIO_GPS_nRST		EXYNOS4_GPL2(1)
+#define GPIO_GPS_PWR_EN		EXYNOS4_GPL2(2)
+
+#define GPIO_GYRO_INT		EXYNOS4_GPF0(3)
+#define GPIO_GSENSE_SDA_18V	EXYNOS4_GPD1(2)
+#define GPIO_GSENSE_SCL_18V	EXYNOS4_GPD1(3)
+
+#define GPIO_MSENSOR_INT	EXYNOS4212_GPJ0(7)
+#define GPIO_MSENSOR_SDA_18V	EXYNOS4_GPY2(4)
+#define GPIO_MSENSOR_SCL_18V	EXYNOS4_GPY2(5)
+
+#define GPIO_BENSE_SCL_18V	EXYNOS4_GPY2(3)
+#define GPIO_BSENSE_SDA_18V	EXYNOS4_GPY2(2)
+#define GPIO_BARO_INT		EXYNOS4_GPF0(5)
+
+#define GPIO_TF_EN		EXYNOS4_GPY2(0)
+#define GPIO_NFC_SCL_18V	EXYNOS4_GPZ(6)
+#define GPIO_NFC_SDA_18V	EXYNOS4_GPZ(5)
+#define GPIO_NFC_SCL_18V_00	EXYNOS4_GPB(3)
+#define GPIO_NFC_SDA_18V_00	EXYNOS4_GPB(2)
+#define GPIO_NFC_IRQ		EXYNOS4_GPX1(7)
+#define GPIO_NFC_EN		EXYNOS4_GPL2(6)
+#define GPIO_NFC_FIRMWARE	EXYNOS4_GPL2(7)
+#define GPIO_NFC_CLK_REQ	EXYNOS4212_GPM0(0)
+/* Sensors & NFC*/
+
+#define GPIO_DET_35		EXYNOS4_GPX0(1)
+
+#define GPIO_MIC_BIAS_EN	EXYNOS4_GPF1(7)
+#define GPIO_SUB_MIC_BIAS_EN	EXYNOS4_GPF2(0)
+#define GPIO_THIRD_MIC_BIAS_EN	EXYNOS4212_GPJ0(2)
+
+#define GPIO_PMU_RST		EXYNOS4_GPX3(2)
+
+#define GPIO_PMIC_IRQ		EXYNOS4_GPX0(7)
+#define GPIO_IF_PMIC_IRQ	EXYNOS4_GPX1(5)
+
+#define GPIO_TSP_INT		EXYNOS4212_GPM2(3)
+#define GPIO_TSP_SDA_18V	EXYNOS4_GPA1(2)
+#define GPIO_TSP_SCL_18V	EXYNOS4_GPA1(3)
+
+#define GPIO_BT_EN		EXYNOS4_GPL0(6)
+#define GPIO_BT_WAKE		EXYNOS4_GPX3(1)
+#define GPIO_BT_HOST_WAKE	EXYNOS4_GPX2(6)
+#define IRQ_BT_HOST_WAKE	IRQ_EINT(22)
+
+#define GPIO_BT_RXD		EXYNOS4_GPA0(0)
+#define GPIO_BT_RXD_AF		2
+
+#define GPIO_BT_TXD		EXYNOS4_GPA0(1)
+#define GPIO_BT_TXD_AF		2
+
+#define GPIO_BT_CTS		EXYNOS4_GPA0(2)
+#define GPIO_BT_CTS_AF		2
+
+#define GPIO_BT_RTS		EXYNOS4_GPA0(3)
+#define GPIO_BT_RTS_AF		2
+
+#define GPIO_GPS_RXD		EXYNOS4_GPA0(4)
+#define GPIO_GPS_RXD_AF		2
+
+#define GPIO_GPS_TXD		EXYNOS4_GPA0(5)
+#define GPIO_GPS_TXD_AF		2
+
+#define GPIO_GPS_CTS		EXYNOS4_GPA0(6)
+#define GPIO_GPS_CTS_AF		2
+
+#define GPIO_GPS_RTS		EXYNOS4_GPA0(7)
+#define GPIO_GPS_RTS_AF		2
+
+#define GPIO_FLM_RXD		EXYNOS4_GPA1(4)
+#define GPIO_FLM_RXD_AF		2
+
+#define GPIO_FLM_TXD		EXYNOS4_GPA1(5)
+#define GPIO_FLM_TXD_AF		2
+
+#define GPIO_3_TOUCH_SCL	EXYNOS4_GPL0(1)
+#define GPIO_3_TOUCH_SDA	EXYNOS4_GPL0(2)
+#define GPIO_HDMI_EN		EXYNOS4_GPL0(4)
+#define GPIO_3_TOUCH_INT	EXYNOS4212_GPJ0(3)
+#define GPIO_3_TOUCH_EN		EXYNOS4212_GPM0(0)
+
+#define GPIO_PWM0		EXYNOS4_GPD0(0)
+#define GPIO_PWM1		EXYNOS4_GPD0(1)
+#define GPIO_PWM2		EXYNOS4_GPD0(2)
+#define GPIO_PWM3		EXYNOS4_GPD0(3)
+
+#define GPIO_VIBTONE_EN		EXYNOS4212_GPJ0(6)
+
+#define GPIO_WLAN_EN		EXYNOS4212_GPJ0(0)
+#define GPIO_WLAN_EN_AF		1
+#define GPIO_WLAN_HOST_WAKE	EXYNOS4_GPX2(5)
+#define GPIO_WLAN_HOST_WAKE_AF	0xF
+#define GPIO_WLAN_SDIO_CLK	EXYNOS4_GPK3(0)
+#define GPIO_WLAN_SDIO_CLK_AF	2
+#define GPIO_WLAN_SDIO_CMD	EXYNOS4_GPK3(1)
+#define GPIO_WLAN_SDIO_CMD_AF	2
+#define GPIO_WLAN_SDIO_D0	EXYNOS4_GPK3(3)
+#define GPIO_WLAN_SDIO_D0_AF	2
+#define GPIO_WLAN_SDIO_D1	EXYNOS4_GPK3(4)
+#define GPIO_WLAN_SDIO_D1_AF	2
+#define GPIO_WLAN_SDIO_D2	EXYNOS4_GPK3(5)
+#define GPIO_WLAN_SDIO_D2_AF	2
+#define GPIO_WLAN_SDIO_D3	EXYNOS4_GPK3(6)
+#define GPIO_WLAN_SDIO_D3_AF	2
+
+#define GPIO_USB_SEL		EXYNOS4212_GPJ0(1)
+
+#define GPIO_LCD_22V_EN		EXYNOS4212_GPM4(4)
+#define GPIO_LCD_22V_EN_00		EXYNOS4_GPC0(1)
+
+#define GPIO_ISP_TXD		EXYNOS4212_GPM4(5)
+#define GPIO_ISP_RXD		EXYNOS4212_GPM4(6)
+
+#define GPIO_TA_EN		EXYNOS4_GPL2(2)
+
+#define GPIO_MHL_SEL		EXYNOS4_GPL0(3)
+
+#define GPIO_MHL_SDA_1_8V	EXYNOS4_GPF0(4)
+#define GPIO_MHL_SCL_1_8V	EXYNOS4_GPF0(6)
+#define GPIO_MHL_SDA_1_8V_00	EXYNOS4_GPB(2)
+#define GPIO_MHL_SCL_1_8V_00	EXYNOS4_GPB(3)
+
+#define GPIO_OTG_EN		EXYNOS4_GPF0(7)
+
+#define GPIO_OLED_ID		EXYNOS4_GPF1(0)
+#define GPIO_ISP_RESET		EXYNOS4_GPF1(3)
+#define GPIO_FUEL_SCL		EXYNOS4_GPF1(4)
+#define GPIO_FUEL_SDA		EXYNOS4_GPF1(5)
+
+#define GPIO_MLCD_RST		EXYNOS4_GPF2(1)
+#define GPIO_UART_SEL		EXYNOS4_GPF2(3)
+#define GPIO_S_LED_I2C_SCL	EXYNOS4_GPF2(6)
+#define GPIO_S_LED_I2C_SDA	EXYNOS4_GPF2(7)
+#define GPIO_OLED_DET		EXYNOS4_GPF3(0)
+
+#define GPIO_PMIC_DVS1		EXYNOS4212_GPM3(0)
+#define GPIO_PMIC_DVS2		EXYNOS4212_GPM3(1)
+
+/* Definitions for Sii 9244B0 */
+#define GPIO_PMIC_DVS3		EXYNOS4212_GPM3(2)
+#define GPIO_BUCK2_SEL		EXYNOS4_GPF3(1)
+#define GPIO_BUCK3_SEL		EXYNOS4_GPF3(2)
+#define GPIO_BUCK4_SEL		EXYNOS4_GPF3(3)
+#define GPIO_MHL_RST		EXYNOS4_GPF3(4)
+#define GPIO_MHL_INT		EXYNOS4_GPF3(5)
+#define GPIO_MHL_INT_AF		S3C_GPIO_SFN(0xF)
+#define GPIO_MHL_WAKE_UP	EXYNOS4212_GPJ1(4)
+
+#define GPIO_RGB_SDA_1_8V	EXYNOS4_GPF0(0)
+#define GPIO_RGB_SCL_1_8V	EXYNOS4_GPF0(1)
+#define GPIO_RGB_INT		EXYNOS4_GPX2(2)
+#define GPIO_VOL_UP		EXYNOS4212_GPJ1(1)
+#define GPIO_VOL_DOWN		EXYNOS4212_GPJ1(2)
+#define GPIO_VOL_UP_00		EXYNOS4_GPX2(2)
+#define GPIO_VOL_DOWN_00	EXYNOS4_GPX3(3)
+
+#define GPIO_CAM_SW_EN		EXYNOS4212_GPJ1(0)
+#define GPIO_TORCH_EN		EXYNOS4212_GPJ1(1)
+#define GPIO_TORCH_SET		EXYNOS4212_GPJ1(2)
+
+#define GPIO_MHL_DSCL_2_8V	EXYNOS4_GPK1(0)
+#define GPIO_MHL_DSDA_2_8V	EXYNOS4_GPK1(2)
+
+#define MHL_INT_IRQ		gpio_to_irq(GPIO_MHL_INT)
+#define MHL_WAKEUP_IRQ		gpio_to_irq(GPIO_MHL_WAKE_UP)
+
+#define GPIO_HDMI_CEC		EXYNOS4_GPX3(6)
+#define GPIO_HDMI_HPD		EXYNOS4_GPX3(7)
+
+#define GPIO_nPOWER		EXYNOS4_GPX2(7)
+#define GPIO_OK_KEY		EXYNOS4_GPX3(5)
+
+#define GPIO_FUEL_ALERT		EXYNOS4_GPX2(3)
+
+#define GPIO_V_BUS_INT		EXYNOS4_GPX2(4)	/* rev0.9 ~ */
+#define GPIO_WPC_INT		EXYNOS4_GPX3(0)
+
+#define GPIO_VIBTONE_PWM	EXYNOS4_GPD0(1)
+
+#define GPIO_VIBTONE_PWM	EXYNOS4_GPD0(1)
+
+#define GPIO_CODEC_SDA_18V	EXYNOS4_GPD0(2)
+#define GPIO_CODEC_SCL_18V	EXYNOS4_GPD0(3)
+#define GPIO_CODEC_SDA_18V_00		EXYNOS4_GPB(0)
+#define GPIO_CODEC_SCL_18V_00		EXYNOS4_GPB(1)
+
+
+#define GPIO_CODEC_LDO_EN	EXYNOS4212_GPJ0(4)
+
+#define GPIO_WM8994_LDO		EXYNOS4212_GPJ0(4)
+
+/* Modem Interface GPIOs - M0 HSIC */
+#if !defined(CONFIG_SEC_MODEM_M0_TD)
+#define GPIO_ACTIVE_STATE	EXYNOS4_GPF1(1)
+#define GPIO_PDA_ACTIVE		EXYNOS4_GPF1(6)
+#define GPIO_PHONE_ON		EXYNOS4_GPL2(5)
+#define GPIO_SUSPEND_REQUEST	EXYNOS4212_GPM2(4)
+#define GPIO_CP_REQ_RESET	EXYNOS4212_GPM3(3)
+#define GPIO_GPS_CNTL		EXYNOS4212_GPM3(4)
+#define GPIO_IPC_SLAVE_WAKEUP	EXYNOS4_GPX1(0)
+#define GPIO_IPC_HOST_WAKEUP	EXYNOS4_GPX1(1)
+#define GPIO_CP_DUMP_INT	EXYNOS4_GPX1(2)
+#define GPIO_PHONE_ACTIVE	EXYNOS4_GPX1(6)
+#define GPIO_CP_RST		EXYNOS4_GPX3(2)
+#define GPIO_AP_DUMP_INT	EXYNOS4212_GPJ0(1)
+
+#define GPIO_FM_RST EXYNOS4_GPC1(1)
+#else
+
+/* Modem Interface GPIOs - M0 SPI */
+#define GPIO_PDA_ACTIVE	EXYNOS4_GPF1(6)
+#define GPIO_PHONE_ON	EXYNOS4_GPL2(5)
+#define GPIO_PHONE_ACTIVE	EXYNOS4_GPX1(6)
+#define GPIO_AP_CP_INT1	EXYNOS4_GPX0(5)
+#define GPIO_AP_CP_INT2	EXYNOS4_GPX3(5)
+#define GPIO_CP_DUMP_INT	EXYNOS4_GPX1(2)
+#define GPIO_IPC_MRDY	EXYNOS4_GPX0(4)
+#define GPIO_IPC_SRDY	EXYNOS4_GPX1(0)
+#define GPIO_IPC_SUB_MRDY	EXYNOS4_GPX3(2)
+#define GPIO_IPC_SUB_SRDY	EXYNOS4_GPX1(1)
+
+#define GPIO_CP_RST	EXYNOS4_GPF1(1)
+#define GPIO_CP_REQ_RESET	EXYNOS4_GPF1(1)
+#define GPIO_IPC_SLAVE_WAKEUP	EXYNOS4_GPX2(0)
+#define GPIO_IPC_HOST_WAKEUP	EXYNOS4_GPX2(0)
+#define GPIO_SUSPEND_REQUEST	EXYNOS4_GPF1(1)
+#define GPIO_ISP_INT		EXYNOS4_GPF1(1)
+#define GPIO_ACTIVE_STATE	EXYNOS4_GPF1(1)
+
+#define GPIO_FM_RST	EXYNOS4_GPC1(0)
+
+#define IRQ_IPC_SRDY		IRQ_EINT8
+#define IRQ_PHONE_ACTIVE	IRQ_EINT14
+#define IRQ_IPC_SRDY		IRQ_EINT8
+#define IRQ_IPC_SUB_SRDY	IRQ_EINT9
+#define IRQ_CP_DUMP_INT	IRQ_EINT10
+#endif
+
+#define GPIO_OK_KEY_ANDROID	EXYNOS4_GPX0(1)		/*system_rev == 11*/
+#define GPIO_OK_KEY_ANDROID_F EXYNOS4_GPX1(3)	/*system_rev >= 15*/
+
+#define GPIO_FM_INT_REV15	EXYNOS4_GPX1(4)
+#define GPIO_FM_INT_REV07	EXYNOS4_GPX1(3)
+#define GPIO_FM_INT		EXYNOS4_GPX1(3)
+#define GPIO_FM_MIC_SW		EXYNOS4_GPL0(3)
+
+#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE)
+#define GPIO_TDMB_EN		EXYNOS4_GPL0(0)
+#define GPIO_TDMB_INT		EXYNOS4_GPF0(2)
+#define GPIO_TDMB_IRQ		gpio_to_irq(GPIO_TDMB_INT)
+#define GPIO_TDMB_INT_AF	0xf
+#define GPIO_TDMB_SPI_CLK	EXYNOS4_GPC1(1)
+#define GPIO_TDMB_SPI_CS	EXYNOS4_GPC1(2)
+#define GPIO_TDMB_SPI_MISO	EXYNOS4_GPC1(3)
+#define GPIO_TDMB_SPI_MOSI	EXYNOS4_GPC1(4)
+#endif
+
+#endif /* __MACH_GPIO_MIDAS_H */
diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev01-midas.h b/arch/arm/mach-exynos/include/mach/gpio-rev01-midas.h
new file mode 100644
index 0000000..421bb3b
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/gpio-rev01-midas.h
@@ -0,0 +1,215 @@
+#ifndef __MACH_GPIO_MIDAS_H
+#define __MACH_GPIO_MIDAS_H __FILE__
+
+#include <mach/gpio.h>
+
+extern void midas_config_gpio_table(void);
+extern void midas_config_sleep_gpio_table(void);
+
+#define GPIO_eMMC_EN		EXYNOS4_GPK0(2)
+
+#define GPIO_BOOT_MODE		EXYNOS4_GPX0(3)
+
+#define GPIO_PMIC_SDA		EXYNOS4_GPB(2)
+#define GPIO_PMIC_SCL		EXYNOS4_GPB(3)
+
+#define GPIO_CHARGER_SDA_18V	EXYNOS4_GPB(0)
+#define GPIO_CHARGER_SCL_18V	EXYNOS4_GPB(1)
+#define GPIO_CAM_VT_nRST	EXYNOS4_GPL2(1)
+#define GPIO_VTCAM_MCLK		EXYNOS4212_GPM2(2)
+
+#define GPIO_8M_CAM_SDA_18V	EXYNOS4_GPD1(0)
+#define GPIO_8M_CAM_SCL_18V	EXYNOS4_GPD1(1)
+#define GPIO_CAM_MCLK		EXYNOS4212_GPJ1(3)
+
+/* Sensors & NFC*/
+#define GPIO_PS_ALS_EN		EXYNOS4212_GPJ0(5)
+#define GPIO_PS_ALS_SDA_28V	EXYNOS4_GPK1(1)
+#define GPIO_PS_ALS_SCL_28V	EXYNOS4_GPK2(2)
+#define GPIO_PS_ALS_INT		EXYNOS4_GPX0(2)
+
+#define GPIO_GYRO_DE		EXYNOS4_GPL2(0)
+#define GPIO_GYRO_INT		EXYNOS4_GPX0(0)
+#define GPIO_GSENSE_SDA_18V	EXYNOS4_GPD1(2)
+#define GPIO_GSENSE_SCL_18V	EXYNOS4_GPD1(3)
+
+#define GPIO_MSENSOR_INT	EXYNOS4_GPX2(2)
+#define GPIO_MSENSOR_SDA_18V	EXYNOS4_GPY2(4)
+#define GPIO_MSENSOR_SCL_18V	EXYNOS4_GPY2(5)
+
+#define GPIO_BSENSE_SDA_18V	EXYNOS4_GPY4(3)
+#define GPIO_BENSE_SCL_18V	EXYNOS4_GPY4(4)
+#define GPIO_BARO_INT		EXYNOS4_GPX0(1)
+
+#define GPIO_NFC_SCL_18V	EXYNOS4_GPY0(0)
+#define GPIO_NFC_SDA_18V	EXYNOS4_GPY0(1)
+#define GPIO_NFC_IRQ		EXYNOS4_GPX1(7)
+#define GPIO_NFC_EN			EXYNOS4_GPL2(6)
+#define GPIO_NFC_FIRMWARE	EXYNOS4_GPL2(7)
+/* Sensors & NFC*/
+
+#define GPIO_PMU_RST		EXYNOS4_GPX3(2)
+
+/* #define GPIO_BUCK1_EN_A		EXYNOS4212_GPJ1(1) */
+/* #define GPIO_BUCK1_EN_B		EXYNOS4212_GPJ1(2) */
+/* #define GPIO_BUCK2_EN		EXYNOS4_GPL0(0) */
+#define GPIO_PMIC_IRQ		EXYNOS4_GPX0(7)
+#define GPIO_IF_PMIC_IRQ	EXYNOS4_GPX1(5)
+
+#define GPIO_PMIC_DVS1		EXYSNO4_GPY5(5)
+#define GPIO_PMIC_DVS2		EXYSNO4_GPY5(6)
+#define GPIO_PMIC_DVS3		EXYSNO4_GPY5(7)
+
+#define GPIO_BUCK2_SEL		EXYNOS4_GPY6(0)
+#define GPIO_BUCK3_SEL		EXYNOS4_GPY6(3)
+#define GPIO_BUCK4_SEL		EXYNOS4_GPY6(4)
+
+#define GPIO_TSP_INT		EXYNOS4_GPX0(4)
+#define GPIO_TSP_SDA_18V	EXYNOS4_GPA1(2)
+#define GPIO_TSP_SCL_18V	EXYNOS4_GPA1(3)
+
+#define GPIO_BT_nRST		EXYNOS4_GPL1(0)
+#define GPIO_BT_EN		EXYNOS4_GPL0(6)
+#define GPIO_BT_WAKE		EXYNOS4_GPX3(1)
+#define GPIO_BT_HOST_WAKE	EXYNOS4_GPX2(6)
+#define IRQ_BT_HOST_WAKE	IRQ_EINT(22)
+
+#define GPIO_BT_RXD		EXYNOS4_GPA0(0)
+#define GPIO_BT_RXD_AF		2
+
+#define GPIO_BT_TXD		EXYNOS4_GPA0(1)
+#define GPIO_BT_TXD_AF		2
+
+#define GPIO_BT_CTS		EXYNOS4_GPA0(2)
+#define GPIO_BT_CTS_AF		2
+
+#define GPIO_BT_RTS		EXYNOS4_GPA0(3)
+#define GPIO_BT_RTS_AF		2
+
+#define GPIO_GPS_CNTL		EXYNOS4_GPY3(6)
+#define GPIO_GPS_nRST		EXYNOS4_GPY6(6)
+#define GPIO_GPS_PWR_EN	EXYNOS4_GPY6(7)
+
+#define GPIO_GPS_RXD		EXYNOS4_GPA0(4)
+#define GPIO_GPS_RXD_AF		2
+
+#define GPIO_GPS_TXD		EXYNOS4_GPA0(5)
+#define GPIO_GPS_TXD_AF		2
+
+#define GPIO_GPS_CTS		EXYNOS4_GPA0(6)
+#define GPIO_GPS_CTS_AF		2
+
+#define GPIO_GPS_RTS		EXYNOS4_GPA0(7)
+#define GPIO_GPS_RTS_AF		2
+
+#define GPIO_FLM_RXD		EXYNOS4_GPA1(4)
+#define GPIO_FLM_RXD_AF		2
+
+#define GPIO_FLM_TXD		EXYNOS4_GPA1(5)
+#define GPIO_FLM_TXD_AF		2
+
+#define GPIO_3_TOUCH_SCL	EXYNOS4_GPL0(1)
+#define GPIO_3_TOUCH_SDA	EXYNOS4_GPL0(2)
+#define GPIO_3_TOUCH_INT	EXYNOS4212_GPJ1(0)
+#define GPIO_TOUCH_EN		EXYNOS4212_GPJ0(3)
+
+#define GPIO_PWM0		EXYNOS4_GPD0(0)
+#define GPIO_PWM1		EXYNOS4_GPD0(1)
+#define GPIO_PWM2		EXYNOS4_GPD0(2)
+#define GPIO_PWM3		EXYNOS4_GPD0(3)
+
+#define GPIO_VIBTONE_EN		EXYNOS4212_GPJ0(6)
+
+#define GPIO_WLAN_EN		EXYNOS4212_GPJ0(0)
+#define GPIO_WLAN_EN_AF		1
+#define GPIO_WLAN_HOST_WAKE	EXYNOS4_GPX2(5)
+#define GPIO_WLAN_HOST_WAKE_AF	0xF
+#define GPIO_WLAN_SDIO_CLK	EXYNOS4_GPK3(0)
+#define GPIO_WLAN_SDIO_CLK_AF	2
+#define GPIO_WLAN_SDIO_CMD	EXYNOS4_GPK3(1)
+#define GPIO_WLAN_SDIO_CMD_AF	2
+#define GPIO_WLAN_SDIO_D0	EXYNOS4_GPK3(3)
+#define GPIO_WLAN_SDIO_D0_AF	2
+#define GPIO_WLAN_SDIO_D1	EXYNOS4_GPK3(4)
+#define GPIO_WLAN_SDIO_D1_AF	2
+#define GPIO_WLAN_SDIO_D2	EXYNOS4_GPK3(5)
+#define GPIO_WLAN_SDIO_D2_AF	2
+#define GPIO_WLAN_SDIO_D3	EXYNOS4_GPK3(6)
+#define GPIO_WLAN_SDIO_D3_AF	2
+
+#define GPIO_TA_EN		EXYNOS4_GPL2(2)
+
+#define GPIO_MHL_RST		EXYNOS4_GPF3(4)
+#define GPIO_MHL_SEL		EXYNOS4_GPL0(3)
+#define GPIO_MHL_INT		EXYNOS4_GPF3(5)
+#define GPIO_MHL_INT_AF		S3C_GPIO_SFN(0xF)
+#define GPIO_MHL_WAKE_UP	EXYNOS4212_GPJ1(4)
+
+#define GPIO_MHL_SDA_18V	EXYNOS4_GPY3(0)
+#define GPIO_MHL_SCL_18V	EXYNOS4_GPY3(2)
+
+#define GPIO_MHL_DSDA_28V	EXYNOS4_GPK(2)
+#define GPIO_MHL_DSCL_28V	EXYNOS4_GPK(0)
+
+#define GPIO_AP_HDMI_SDA	GPIO_MSENSOR_MHL_DSDA_28V
+#define	GPIO_AP_HDMI_SDA_AF	GPIO_MSENSOR_MHL_DSDA_AF
+#define GPIO_AP_HDMI_SCL	GPIO_MSENSOR_MHL_DSCL_28V
+#define	GPIO_AP_HDMI_SCL_AF	GPIO_MSENSOR_MHL_DSCL_AF
+
+#define GPIO_AP_SDA_18V		GPIO_MHL_SDA_18V
+#define GPIO_AP_SCL_18V		GPIO_MHL_SCL_18V
+
+#define MHL_INT_IRQ		gpio_to_irq(GPIO_MHL_INT)
+#define MHL_WAKEUP_IRQ		gpio_to_irq(GPIO_MHL_WAKE_UP)
+
+#define GPIO_ACC_INT		EXYNOS4_GPX1(4)
+
+
+#define GPIO_CP_DUMP_INT	EXYNOS4_GPX1(2)
+#define GPIO_IPC_SLAVE_WAKEUP	EXYNOS4_GPX1(0)
+#define GPIO_IPC_HOST_WAKEUP	EXYNOS4_GPX1(1)
+#define GPIO_ACTIVE_STATE	EXYNOS4_GPY3(5)
+
+#define GPIO_VOL_UP		EXYNOS4_GPX2(0)
+#define GPIO_VOL_DOWN		EXYNOS4_GPX2(1)
+#define GPIO_nPOWER		EXYNOS4_GPX2(7)
+#define GPIO_OK_KEY		EXYNOS4_GPX3(5)
+
+
+#define GPIO_ISP_RESET		EXYNOS4_GPY3(7)
+#define GPIO_ISP_STANDBY	EXYNOS4_GPY5(4)
+
+
+#define GPIO_FUEL_SDA		EXYNOS4_GPY4(0)
+#define GPIO_FUEL_SCL		EXYNOS4_GPY4(1)
+
+#define GPIO_MLCD_RST		EXYNOS4_GPY4(5)
+
+
+#define GPIO_PDA_ACTIVE		EXYNOS4_GPY4(2)
+
+#define GPIO_HW_REV0		EXYNOS4_GPY5(0)
+#define GPIO_HW_REV1		EXYNOS4_GPY5(1)
+#define GPIO_HW_REV2		EXYNOS4_GPY5(2)
+#define GPIO_HW_REV3		EXYNOS4_GPY5(3)
+
+#define GPIO_CAM_IO_EN		EXYNOS4_GPY6(1)
+#define GPIO_ISP_CORE_EN	EXYNOS4_GPY6(2)
+#define GPIO_8M_12V_EN		EXYNOS4_GPY6(5)
+
+#define GPIO_CODEC_SDA_18V	EXYNOS4_GPD0(2)
+#define GPIO_CODEC_SCL_18V	EXYNOS4_GPD0(3)
+
+#define GPIO_WM8994_LDO		EXYNOS4212_GPJ0(4)
+
+/* Definitions for XMM6262 and C2C */
+#define CP_PMU_RST_N		EXYNOS4_GPX3(2)
+#define CP_RESET_REQ_N		EXYNOS4_GPY4(6)
+#define CP_ON			EXYNOS4_GPL2(5)
+#define PDA_ACTIVE		EXYNOS4_GPY4(2)
+#define PHONE_ACTIVE		EXYNOS4_GPX1(6)
+#define PHONE_ACTIVE_IRQ	IRQ_EINT(14)
+#define CP_DUMP_INT		EXYNOS4_GPX1(2)
+#define CP_DUMP_INT_IRQ		IRQ_EINT(10)
+
+#endif /* __MACH_GPIO_MIDAS_H */
diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev01-p10-lungo-wifi.h b/arch/arm/mach-exynos/include/mach/gpio-rev01-p10-lungo-wifi.h
new file mode 100644
index 0000000..ce182f0
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/gpio-rev01-p10-lungo-wifi.h
@@ -0,0 +1,387 @@
+#ifndef __MACH_GPIO_P10_H
+#define __MACH_GPIO_P10 __FILE__
+
+#include <mach/gpio.h>
+
+extern void p10_config_gpio_table(void);
+extern void p10_config_sleep_gpio_table(void);
+
+/**
+ * Main GPIO function mapping.
+ */
+#define	GPIO_BT_UART_RXD		EXYNOS5_GPA0(0)
+#define	GPIO_BT_UART_TXD		EXYNOS5_GPA0(1)
+#define	GPIO_BT_UART_CTS		EXYNOS5_GPA0(2)
+#define	GPIO_BT_UART_RTS		EXYNOS5_GPA0(3)
+
+#define	GPIO_HDMI_DCDC_EN		EXYNOS5_GPA0(4)
+
+#define	GPIO_CHG_SDA_18V		EXYNOS5_GPE0(1)
+#define	GPIO_CHG_SCL_18V		EXYNOS5_GPE0(2)
+
+#define	GPIO_AP_RXD			EXYNOS5_GPA1(0)
+#define	GPIO_AP_TXD			EXYNOS5_GPA1(1)
+
+#define	GPIO_TSP_SDA_18V		EXYNOS5_GPA1(2)
+#define	GPIO_TSP_SCL_18V		EXYNOS5_GPA1(3)
+
+#define	GPIO_IPC_RXD			EXYNOS5_GPA1(4)
+#define	GPIO_IPC_TXD			EXYNOS5_GPA1(5)
+
+#define	GPIO_MM_SDA_18V			EXYNOS5_GPA2(0)
+#define	GPIO_MM_SCL_18V			EXYNOS5_GPA2(1)
+
+#define	GPIO_AP_PMIC_SDA		EXYNOS5_GPA2(2)
+#define	GPIO_AP_PMIC_SCL		EXYNOS5_GPA2(3)
+
+#define	GPIO_5M_SPI_CLK			EXYNOS5_GPA2(4)
+#define	GPIO_5M_SPI_CS			EXYNOS5_GPA2(5)
+#define	GPIO_5M_SPI_DI			EXYNOS5_GPA2(6)
+#define	GPIO_5M_SPI_DO			EXYNOS5_GPA2(7)
+
+#define	GPIO_OTG_EN			EXYNOS5_GPB0(3)
+
+#define	GPIO_USB30_EN			EXYNOS5_GPB0(4)
+
+#define	GPIO_POGO_SPDIF			EXYNOS5_GPB1(0)
+
+#define	GPIO_LCD_PWM_IN_18V		EXYNOS5_GPB2(0)
+
+#define	GPIO_ACCESSORY_CHECK	EXYNOS5_GPE0(4)
+#define	GPIO_ACCESSORY_EN	EXYNOS5_GPH1(5)
+#define	GPIO_ACCESSORY_INT	EXYNOS5_GPX3(2)
+
+#define	GPIO_ADC_INT		EXYNOS5_GPX2(4)
+#define	GPIO_ADC_SCL_18V	EXYNOS5_GPV3(0)
+#define	GPIO_ADC_SDA_18V	EXYNOS5_GPV3(1)
+
+#define	GPIO_MOTOR_PWM			EXYNOS5_GPB2(1)
+
+#define	GPIO_CODEC_SDA_18V		EXYNOS5_GPB2(2)
+#define	GPIO_CODEC_SCL_18V		EXYNOS5_GPB2(3)
+
+#define	GPIO_DISP_SDA_18V		EXYNOS5_GPB3(0)
+#define	GPIO_DISP_SCL_18V		EXYNOS5_GPB3(1)
+
+#define	GPIO_SENSE_SDA_18V		EXYNOS5_GPB3(2)
+#define	GPIO_SENSE_SCL_18V		EXYNOS5_GPB3(3)
+
+#define	GPIO_NAND_CLK			EXYNOS5_GPC0(0)
+#define	GPIO_NAND_CMD			EXYNOS5_GPC0(1)
+
+#define	GPIO_eMMC_EN			EXYNOS5_GPC0(2)
+
+#define	GPIO_NAND_D0			EXYNOS5_GPC0(3)
+#define	GPIO_NAND_D1			EXYNOS5_GPC0(4)
+#define	GPIO_NAND_D2			EXYNOS5_GPC0(5)
+#define	GPIO_NAND_D3			EXYNOS5_GPC0(6)
+#define	GPIO_NAND_D4			EXYNOS5_GPC1(0)
+#define	GPIO_NAND_D5			EXYNOS5_GPC1(1)
+#define	GPIO_NAND_D6			EXYNOS5_GPC1(2)
+#define	GPIO_NAND_D7			EXYNOS5_GPC1(3)
+
+#define	GPIO_BTREG_ON		EXYNOS5_GPH0(0)
+#define   IRQ_BT_HOST_WAKE	IRQ_EINT(22)
+
+#define	GPIO_T_FLASH_CLK		EXYNOS5_GPC3(0)
+#define	GPIO_T_FLASH_CMD		EXYNOS5_GPC3(1)
+#define	GPIO_T_FLASH_D0			EXYNOS5_GPC3(3)
+#define	GPIO_T_FLASH_D1			EXYNOS5_GPC3(4)
+#define	GPIO_T_FLASH_D2			EXYNOS5_GPC3(5)
+#define	GPIO_T_FLASH_D3			EXYNOS5_GPC3(6)
+
+#define	GPIO_GPS_UART_RXD		EXYNOS5_GPD0(0)
+#define	GPIO_GPS_UART_TXD		EXYNOS5_GPD0(1)
+#define	GPIO_GPS_UART_CTS		EXYNOS5_GPD0(2)
+#define	GPIO_GPS_UART_RTS		EXYNOS5_GPD0(3)
+
+#define	GPIO_HDMI_EN			EXYNOS5_GPD1(0)
+
+#define	GPIO_TOUCH_EN			EXYNOS5_GPD1(1)
+
+#define	GPIO_LCD_ID			EXYNOS5_GPD1(4)
+
+#define	GPIO_MOTOR_EN			EXYNOS5_GPD1(6)
+
+#define	GPIO_NFC_EN			EXYNOS5_GPD1(7)
+
+#define	GPIO_TA_INT			EXYNOS5_GPX0(0)
+
+#define	GPIO_DET_35			EXYNOS5_GPX0(1)
+
+#define	GPIO_AP_PMIC_IRQ		EXYNOS5_GPX0(2)
+
+#define	GPIO_CHG_INT			EXYNOS5_GPX0(4)
+
+/*#define	GPIO_POGO_DET			EXYNOS5_GPX0(5) */
+
+#define	GPIO_DOCK_INT		EXYNOS5_GPX3(0)
+
+
+#define	GPIO_DP_HPD			EXYNOS5_GPX0(7)
+
+#define	GPIO_DPRAM_A0		EXYNOS5_GPY3(0)
+#define	GPIO_DPRAM_A1		EXYNOS5_GPY3(1)
+#define	GPIO_DPRAM_A2		EXYNOS5_GPY3(2)
+#define	GPIO_DPRAM_A3		EXYNOS5_GPY3(3)
+#define	GPIO_DPRAM_A4		EXYNOS5_GPY3(4)
+#define	GPIO_DPRAM_A5		EXYNOS5_GPY3(5)
+#define	GPIO_DPRAM_A6		EXYNOS5_GPY3(6)
+#define	GPIO_DPRAM_A7		EXYNOS5_GPY3(7)
+#define	GPIO_DPRAM_A8		EXYNOS5_GPY4(0)
+#define	GPIO_DPRAM_A9		EXYNOS5_GPY4(1)
+#define	GPIO_DPRAM_A10		EXYNOS5_GPY4(2)
+#define	GPIO_DPRAM_A11		EXYNOS5_GPY4(3)
+#define	GPIO_DPRAM_A12		EXYNOS5_GPY4(4)
+#define	GPIO_DPRAM_A13		EXYNOS5_GPY4(5)
+#define	GPIO_DPRAM_CSN		EXYNOS5_GPY0(0)
+#define	GPIO_DPRAM_D0		EXYNOS5_GPY5(0)
+#define	GPIO_DPRAM_D1		EXYNOS5_GPY5(1)
+#define	GPIO_DPRAM_D2		EXYNOS5_GPY5(2)
+#define	GPIO_DPRAM_D3		EXYNOS5_GPY5(3)
+#define	GPIO_DPRAM_D4		EXYNOS5_GPY5(4)
+#define	GPIO_DPRAM_D5		EXYNOS5_GPY5(5)
+#define	GPIO_DPRAM_D6		EXYNOS5_GPY5(6)
+#define	GPIO_DPRAM_D7		EXYNOS5_GPY5(7)
+#define	GPIO_DPRAM_D8		EXYNOS5_GPY6(0)
+#define	GPIO_DPRAM_D9		EXYNOS5_GPY6(1)
+#define	GPIO_DPRAM_D10		EXYNOS5_GPY6(2)
+#define	GPIO_DPRAM_D11		EXYNOS5_GPY6(3)
+#define	GPIO_DPRAM_D12		EXYNOS5_GPY6(4)
+#define	GPIO_DPRAM_D13		EXYNOS5_GPY6(5)
+#define	GPIO_DPRAM_D14		EXYNOS5_GPY6(6)
+#define	GPIO_DPRAM_D15		EXYNOS5_GPY6(7)
+#define	GPIO_DPRAM_INT		EXYNOS5_GPX0(5)
+#define	GPIO_DPRAM_REN		EXYNOS5_GPY0(4)
+#define	GPIO_DPRAM_WEN		EXYNOS5_GPY0(5)
+
+#define	GPIO_ACC_INT			EXYNOS5_GPX1(4)
+
+#define	GPIO_NFC_WAKE			EXYNOS5_GPX1(5)
+
+#define	GPIO_SPI_INT			EXYNOS5_GPX1(6)
+
+#define	GPIO_NFC_IRQ			EXYNOS5_GPX1(7)
+
+#define	GPIO_VOL_UP			EXYNOS5_GPX2(0)
+#define	GPIO_VOL_DOWN			EXYNOS5_GPX2(1)
+
+#define	GPIO_MSENSE_RDY			EXYNOS5_GPX2(2)
+
+#define	GPIO_ADC_INT			EXYNOS5_GPX2(4)
+
+#define	GPIO_WLAN_HOST_WAKE		EXYNOS5_GPX2(5)
+
+#define	GPIO_BT_HOST_WAKE		EXYNOS5_GPX2(6)
+
+#define	GPIO_nPOWER			EXYNOS5_GPX2(7)
+
+#define	GPIO_FUEL_ALERT		EXYNOS5_GPX2(3)
+#define	GPIO_FUEL_SCL_18V	EXYNOS5_GPZ(6)
+#define	GPIO_FUEL_SDA_18V	EXYNOS5_GPZ(5)
+
+#define	GPIO_GPS_PWR_EN		EXYNOS5_GPE1(0)
+#define	GPIO_GPS_nRST		EXYNOS5_GPE0(6)
+#define	GPIO_GPS_CTS		EXYNOS5_GPA0(6)
+#define	GPIO_GPS_RTS		EXYNOS5_GPA0(7)
+#define	GPIO_GPS_RXD		EXYNOS5_GPA0(4)
+#define	GPIO_GPS_TXD		EXYNOS5_GPA0(5)
+
+#define	GPIO_GPS_CTS_AF		2
+#define	GPIO_GPS_RTS_AF		2
+#define	GPIO_GPS_RXD_AF		2
+#define	GPIO_GPS_TXD_AF		2
+
+
+#define	GPIO_T_FLASH_DETECT		EXYNOS5_GPX3(4)
+
+#define	GPIO_EAR_SEND_END		EXYNOS5_GPX3(5)
+
+#define	GPIO_HDMI_CEC			EXYNOS5_GPX3(6)
+#define	GPIO_HDMI_HPD			EXYNOS5_GPX3(7)
+
+#define	GPIO_TF_EN			EXYNOS5_GPY2(0)
+
+#define	GPIO_5M_CAM_RESET		EXYNOS5_GPE0(0)
+
+#define	GPIO_CAM_FLASH_EN		EXYNOS5_GPE0(3)
+#define	GPIO_CAM_FLASH_SET		EXYNOS5_GPE0(4)
+
+#define	GPIO_UART_SEL			EXYNOS5_GPE0(5)
+
+#define	GPIO_GPS_nRST			EXYNOS5_GPE0(6)
+
+#define	GPIO_ISP_TXD			EXYNOS5_GPE0(7)
+
+#define	GPIO_GPS_EN			EXYNOS5_GPE1(0)
+
+#define	GPIO_ISP_RXD			EXYNOS5_GPE1(1)
+
+#define	GPIO_5M_CAM_SDA_18V		EXYNOS5_GPF0(0)
+#define	GPIO_5M_CAM_SCL_18V		EXYNOS5_GPF0(1)
+
+#define	GPIO_VT_CAM_SDA_18V		EXYNOS5_GPF0(2)
+#define	GPIO_VT_CAM_SCL_18V		EXYNOS5_GPF0(3)
+
+#define	GPIO_NFC_SPI_CLK		EXYNOS5_GPF1(0)
+#define	GPIO_NFC_SPI_CS			EXYNOS5_GPF1(1)
+#define	GPIO_NFC_SPI_MISO		EXYNOS5_GPF1(2)
+#define	GPIO_NFC_SPI_MOSI		EXYNOS5_GPF1(3)
+
+#define	GPIO_NFC_CLK_REQ		EXYNOS5_GPG0(2)
+
+#define	GPIO_2MIC_WAKE			EXYNOS5_GPG0(3)
+#define	GPIO_2MIC_RST			EXYNOS5_GPG0(4)
+
+#define	GPIO_LED_BACKLIGHT_RESET	EXYNOS5_GPG0(5)
+
+#define	GPIO_HDMI_LS_EN			EXYNOS5_GPG0(7)
+
+#define	GPIO_MHL_DSCL_18V	EXYNOS5_GPB3(1)
+#define	GPIO_MHL_DSDA_18V	EXYNOS5_GPB3(0)
+#define	GPIO_MHL_INT		EXYNOS5_GPG0(6)
+#define	GPIO_MHL_RST		EXYNOS5_GPG0(7)
+#define	GPIO_MHL_SCL_18V	EXYNOS5_GPA0(5)
+#define	GPIO_MHL_SDA_18V	EXYNOS5_GPA0(4)
+
+#define MHL_INT_IRQ		gpio_to_irq(GPIO_MHL_INT)
+#define GPIO_MHL_INT_AF		S3C_GPIO_SFN(0xF)
+
+#define	GPIO_MOTOR_EN		EXYNOS5_GPD1(6)
+#define	GPIO_MOTOR_PWM		EXYNOS5_GPB2(1)
+#define	GPIO_MOTOR_SCL_18V	EXYNOS5_GPD1(3)
+#define	GPIO_MOTOR_SDA_18V	EXYNOS5_GPD1(2)
+
+#define	GPIO_MSENSE_RDY		EXYNOS5_GPX2(2)
+#define	GPIO_MSENSE_RST		EXYNOS5_GPG2(0)
+#define	GPIO_MSENSE_SDA		EXYNOS5_GPV2(7)
+#define	GPIO_MSENSE_SCL		EXYNOS5_GPV2(6)
+
+#define	GPIO_PS_ALS_SDA		EXYNOS5_GPG0(0)
+#define	GPIO_PS_ALS_SCL		EXYNOS5_GPG0(1)
+#define	GPIO_PS_VOUT		EXYNOS5_GPH1(2)
+#define	GPIO_HUM_SDA		EXYNOS5_GPV2(5)
+#define	GPIO_HUM_SCL		EXYNOS5_GPV2(4)
+
+#define	GPIO_CAM_FLASH_EN_T		EXYNOS5_GPG1(0)
+#define	GPIO_CAM_FLASH_SET_T		EXYNOS5_GPG1(1)
+
+#define	GPIO_TOUCH_CHG			EXYNOS5_GPG1(2)
+#define	GPIO_TOUCH_RESET		EXYNOS5_GPG1(3)
+
+#define	GPIO_TA_nCHG			EXYNOS5_GPG1(4)
+#define	GPIO_TA_EN			EXYNOS5_GPG1(5)
+#define	GPIO_TA_nCONNECTED	EXYNOS5_GPX0(0)
+
+#define	GPIO_CAM_VT_nRST		EXYNOS5_GPG1(6)
+
+#define	GPIO_MSENSE_RST			EXYNOS5_GPG2(0)
+
+#define	GPIO_VTCAM_MCLK			EXYNOS5_GPG2(1)
+
+#define	GPIO_USB_SEL1			EXYNOS5_GPH0(1)
+
+#define	GPIO_TP				EXYNOS5_GPH0(2)
+
+#define	GPIO_CAM_MCLK			EXYNOS5_GPH0(3)
+
+#define	GPIO_WM8994_LDO			EXYNOS5_GPH1(1)
+
+#define	GPIO_ALS_nRST			EXYNOS5_GPH1(2)
+
+#define	GPIO_BT_WAKE			EXYNOS5_GPH1(3)
+
+#define	GPIO_LCD_EN			EXYNOS5_GPH1(7)
+
+#define	GPIO_MM_I2S_CLK			EXYNOS5_GPZ(0)
+#define	GPIO_MM_I2S_SYNC		EXYNOS5_GPZ(2)
+#define	GPIO_MM_I2S_DI			EXYNOS5_GPZ(3)
+#define	GPIO_MM_I2S_DO			EXYNOS5_GPZ(4)
+
+#define	GPIO_BUCK4_SEL			EXYNOS5_GPV0(0)
+
+#define	GPIO_BUCK3_SEL			EXYNOS5_GPV0(1)
+
+#define	GPIO_5M_CORE_EN			EXYNOS5_GPV0(2)
+
+#define	GPIO_CAM_IO_EN			EXYNOS5_GPV0(3)
+
+#define	GPIO_BUCK2_SEL			EXYNOS5_GPV0(4)
+
+#define	GPIO_PMIC_DVS3			EXYNOS5_GPV0(5)
+#define	GPIO_PMIC_DVS2			EXYNOS5_GPV0(6)
+#define	GPIO_PMIC_DVS1			EXYNOS5_GPV0(7)
+
+#define	GPIO_WLREG_ON			EXYNOS5_GPV1(0)
+
+#define	GPIO_HW_REV3			EXYNOS5_GPV1(1)
+#define	GPIO_HW_REV2			EXYNOS5_GPV1(2)
+#define	GPIO_HW_REV1			EXYNOS5_GPV1(3)
+#define	GPIO_HW_REV0			EXYNOS5_GPV1(4)
+
+#define GPIO_WLAN_EN            EXYNOS5_GPV1(0)
+#define GPIO_WLAN_EN_AF         1
+#define GPIO_WLAN_HOST_WAKE     EXYNOS5_GPX2(5)
+#define GPIO_WLAN_HOST_WAKE_AF  0xF
+#define GPIO_WLAN_SDIO_CLK      EXYNOS5_GPC3(0)
+#define GPIO_WLAN_SDIO_CLK_AF   2
+#define GPIO_WLAN_SDIO_CMD      EXYNOS5_GPC3(1)
+#define GPIO_WLAN_SDIO_CMD_AF   2
+#define GPIO_WLAN_SDIO_D0       EXYNOS5_GPC3(3)
+#define GPIO_WLAN_SDIO_D0_AF    2
+#define GPIO_WLAN_SDIO_D1       EXYNOS5_GPC3(4)
+#define GPIO_WLAN_SDIO_D1_AF    2
+#define GPIO_WLAN_SDIO_D2       EXYNOS5_GPC3(5)
+#define GPIO_WLAN_SDIO_D2_AF    2
+#define GPIO_WLAN_SDIO_D3       EXYNOS5_GPC3(6)
+#define GPIO_WLAN_SDIO_D3_AF    2
+/**
+ *  Remappig for downward compatibility.
+ */
+#define	GPIO_PMIC_IRQ		GPIO_AP_PMIC_IRQ
+
+#define	GPIO_5M_nRST		GPIO_5M_CAM_RESET
+
+/* Definitions for DPRAM */
+#define GPIO_DPRAM_CSN		EXYNOS5_GPY0(0)
+#define GPIO_DPRAM_CSN0		EXYNOS5_GPY0(0)
+#define GPIO_DPRAM_CSN1		EXYNOS5_GPY0(1)
+#define GPIO_DPRAM_CSN2		EXYNOS5_GPY0(2)
+#define GPIO_DPRAM_CSN3		EXYNOS5_GPY0(3)
+#define GPIO_DPRAM_REN		EXYNOS5_GPY0(4)
+#define GPIO_DPRAM_WEN		EXYNOS5_GPY0(5)
+/* #define GPIO_DPRAM_LBN		EXYNOS4_GPY1(0) // for via modem */
+/* #define GPIO_DPRAM_UBN		EXYNOS4_GPY1(1) // for via modem */
+#define GPIO_SROM_ADDR_BUS_LOW	EXYNOS5_GPY3(0)
+#define GPIO_SROM_ADDR_BUS_HIGH	EXYNOS5_GPY4(0)
+#define GPIO_SROM_DATA_BUS_LOW	EXYNOS5_GPY5(0)
+#define GPIO_SROM_DATA_BUS_HIGH	EXYNOS5_GPY6(0)
+
+/* Definitions for CMC221 */
+#define CP_CMC221_PMIC_PWRON	EXYNOS5_GPD1(5)
+#define CP_CMC221_CPU_RST	EXYNOS5_GPB0(1)
+#define GPIO_LTE_ACTIVE		EXYNOS5_GPX1(6)
+#define LTE_ACTIVE_IRQ		IRQ_EINT(14)	/* IRQ of GPX1[6] */
+
+#define GPIO_CMC_IDPRAM_INT_00	EXYNOS5_GPX0(5)
+#define CMC_IDPRAM_INT_IRQ_00	IRQ_EINT(5)	/* IRQ of GPX0[5] */
+
+#define GPIO_CMC_IDPRAM_STATUS	EXYNOS5_GPX0(3) /* CMC2AP_INT_1 */
+#define GPIO_CMC_IDPRAM_WAKEUP	EXYNOS5_GPX1(2) /* AP2CMC_INT_3 */
+/* #define GPIO_ACTIVE_STATE	EXYNOS4_GPF1(1) // for USB */
+#define GPIO_IPC_SLAVE_WAKEUP	EXYNOS5_GPX0(6) /* AP2CMC_INT_1 */
+#define GPIO_IPC_HOST_WAKEUP	EXYNOS5_GPX1(0) /* CMC2AP_INT_2 */
+
+#define	GPIO_CMC_CLK_18V	GPIO_NFC_SPI_CLK
+#define	GPIO_CMC_CS_18V		GPIO_NFC_SPI_CS
+
+#define	GPIO_FM34_BYPASS	EXYNOS5_GPH1(4)
+#define	GPIO_FM34_PWDN		GPIO_2MIC_WAKE
+#define	GPIO_FM34_RESET		GPIO_2MIC_RST
+#define	GPIO_FM34_SCL_18V	GPIO_MM_SCL_18V
+#define	GPIO_FM34_SDA_18V	GPIO_MM_SDA_18V
+
+#define	GPIO_ES305_WAKEUP	GPIO_2MIC_WAKE
+#define	GPIO_ES305_RESET	GPIO_2MIC_RST
+
+#endif /* __MACH_GPIO_P10_H */
diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev01-p10-lungo.h b/arch/arm/mach-exynos/include/mach/gpio-rev01-p10-lungo.h
new file mode 100644
index 0000000..98d9acf
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/gpio-rev01-p10-lungo.h
@@ -0,0 +1,387 @@
+#ifndef __MACH_GPIO_P10_H
+#define __MACH_GPIO_P10 __FILE__
+
+#include <mach/gpio.h>
+
+extern void p10_config_gpio_table(void);
+extern void p10_config_sleep_gpio_table(void);
+
+/**
+ * Main GPIO function mapping.
+ */
+#define	GPIO_BT_UART_RXD		EXYNOS5_GPA0(0)
+#define	GPIO_BT_UART_TXD		EXYNOS5_GPA0(1)
+#define	GPIO_BT_UART_CTS		EXYNOS5_GPA0(2)
+#define	GPIO_BT_UART_RTS		EXYNOS5_GPA0(3)
+
+#define	GPIO_HDMI_DCDC_EN		EXYNOS5_GPA0(4)
+
+#define	GPIO_CHG_SDA_18V		EXYNOS5_GPE0(1)
+#define	GPIO_CHG_SCL_18V		EXYNOS5_GPE0(2)
+
+#define	GPIO_AP_RXD			EXYNOS5_GPA1(0)
+#define	GPIO_AP_TXD			EXYNOS5_GPA1(1)
+
+#define	GPIO_TSP_SDA_18V		EXYNOS5_GPA1(2)
+#define	GPIO_TSP_SCL_18V		EXYNOS5_GPA1(3)
+
+#define	GPIO_IPC_RXD			EXYNOS5_GPA1(4)
+#define	GPIO_IPC_TXD			EXYNOS5_GPA1(5)
+
+#define	GPIO_MM_SDA_18V			EXYNOS5_GPA2(0)
+#define	GPIO_MM_SCL_18V			EXYNOS5_GPA2(1)
+
+#define	GPIO_AP_PMIC_SDA		EXYNOS5_GPA2(2)
+#define	GPIO_AP_PMIC_SCL		EXYNOS5_GPA2(3)
+
+#define	GPIO_5M_SPI_CLK			EXYNOS5_GPA2(4)
+#define	GPIO_5M_SPI_CS			EXYNOS5_GPA2(5)
+#define	GPIO_5M_SPI_DI			EXYNOS5_GPA2(6)
+#define	GPIO_5M_SPI_DO			EXYNOS5_GPA2(7)
+
+#define	GPIO_OTG_EN			EXYNOS5_GPB0(3)
+
+#define	GPIO_USB30_EN			EXYNOS5_GPB0(4)
+
+#define	GPIO_POGO_SPDIF			EXYNOS5_GPB1(0)
+
+#define	GPIO_LCD_PWM_IN_18V		EXYNOS5_GPB2(0)
+
+#define	GPIO_ACCESSORY_CHECK	EXYNOS5_GPE0(4)
+#define	GPIO_ACCESSORY_EN	EXYNOS5_GPH1(5)
+#define	GPIO_ACCESSORY_INT	EXYNOS5_GPX3(2)
+
+#define	GPIO_ADC_INT		EXYNOS5_GPX2(4)
+#define	GPIO_ADC_SCL_18V	EXYNOS5_GPV3(0)
+#define	GPIO_ADC_SDA_18V	EXYNOS5_GPV3(1)
+
+#define	GPIO_MOTOR_PWM			EXYNOS5_GPB2(1)
+
+#define	GPIO_CODEC_SDA_18V		EXYNOS5_GPB2(2)
+#define	GPIO_CODEC_SCL_18V		EXYNOS5_GPB2(3)
+
+#define	GPIO_DISP_SDA_18V		EXYNOS5_GPB3(0)
+#define	GPIO_DISP_SCL_18V		EXYNOS5_GPB3(1)
+
+#define	GPIO_SENSE_SDA_18V		EXYNOS5_GPB3(2)
+#define	GPIO_SENSE_SCL_18V		EXYNOS5_GPB3(3)
+
+#define	GPIO_NAND_CLK			EXYNOS5_GPC0(0)
+#define	GPIO_NAND_CMD			EXYNOS5_GPC0(1)
+
+#define	GPIO_eMMC_EN			EXYNOS5_GPC0(2)
+
+#define	GPIO_NAND_D0			EXYNOS5_GPC0(3)
+#define	GPIO_NAND_D1			EXYNOS5_GPC0(4)
+#define	GPIO_NAND_D2			EXYNOS5_GPC0(5)
+#define	GPIO_NAND_D3			EXYNOS5_GPC0(6)
+#define	GPIO_NAND_D4			EXYNOS5_GPC1(0)
+#define	GPIO_NAND_D5			EXYNOS5_GPC1(1)
+#define	GPIO_NAND_D6			EXYNOS5_GPC1(2)
+#define	GPIO_NAND_D7			EXYNOS5_GPC1(3)
+
+#define	GPIO_BTREG_ON		EXYNOS5_GPH0(0)
+#define   IRQ_BT_HOST_WAKE	IRQ_EINT(22)
+
+#define	GPIO_T_FLASH_CLK		EXYNOS5_GPC3(0)
+#define	GPIO_T_FLASH_CMD		EXYNOS5_GPC3(1)
+#define	GPIO_T_FLASH_D0			EXYNOS5_GPC3(3)
+#define	GPIO_T_FLASH_D1			EXYNOS5_GPC3(4)
+#define	GPIO_T_FLASH_D2			EXYNOS5_GPC3(5)
+#define	GPIO_T_FLASH_D3			EXYNOS5_GPC3(6)
+
+#define	GPIO_GPS_UART_RXD		EXYNOS5_GPD0(0)
+#define	GPIO_GPS_UART_TXD		EXYNOS5_GPD0(1)
+#define	GPIO_GPS_UART_CTS		EXYNOS5_GPD0(2)
+#define	GPIO_GPS_UART_RTS		EXYNOS5_GPD0(3)
+
+#define	GPIO_HDMI_EN			EXYNOS5_GPD1(0)
+
+#define	GPIO_TOUCH_EN			EXYNOS5_GPD1(1)
+
+#define	GPIO_LCD_ID			EXYNOS5_GPD1(4)
+
+#define	GPIO_MOTOR_EN			EXYNOS5_GPD1(6)
+
+#define	GPIO_NFC_EN			EXYNOS5_GPD1(7)
+
+#define	GPIO_TA_INT			EXYNOS5_GPX0(0)
+
+#define	GPIO_DET_35			EXYNOS5_GPX0(1)
+
+#define	GPIO_AP_PMIC_IRQ		EXYNOS5_GPX0(2)
+
+#define	GPIO_CHG_INT			EXYNOS5_GPX0(4)
+
+/*#define	GPIO_POGO_DET			EXYNOS5_GPX0(5) */
+
+#define	GPIO_DOCK_INT		EXYNOS5_GPX3(0)
+
+
+#define	GPIO_DP_HPD			EXYNOS5_GPX0(7)
+
+#define	GPIO_DPRAM_A0		EXYNOS5_GPY3(0)
+#define	GPIO_DPRAM_A1		EXYNOS5_GPY3(1)
+#define	GPIO_DPRAM_A2		EXYNOS5_GPY3(2)
+#define	GPIO_DPRAM_A3		EXYNOS5_GPY3(3)
+#define	GPIO_DPRAM_A4		EXYNOS5_GPY3(4)
+#define	GPIO_DPRAM_A5		EXYNOS5_GPY3(5)
+#define	GPIO_DPRAM_A6		EXYNOS5_GPY3(6)
+#define	GPIO_DPRAM_A7		EXYNOS5_GPY3(7)
+#define	GPIO_DPRAM_A8		EXYNOS5_GPY4(0)
+#define	GPIO_DPRAM_A9		EXYNOS5_GPY4(1)
+#define	GPIO_DPRAM_A10		EXYNOS5_GPY4(2)
+#define	GPIO_DPRAM_A11		EXYNOS5_GPY4(3)
+#define	GPIO_DPRAM_A12		EXYNOS5_GPY4(4)
+#define	GPIO_DPRAM_A13		EXYNOS5_GPY4(5)
+#define	GPIO_DPRAM_CSN		EXYNOS5_GPY0(0)
+#define	GPIO_DPRAM_D0		EXYNOS5_GPY5(0)
+#define	GPIO_DPRAM_D1		EXYNOS5_GPY5(1)
+#define	GPIO_DPRAM_D2		EXYNOS5_GPY5(2)
+#define	GPIO_DPRAM_D3		EXYNOS5_GPY5(3)
+#define	GPIO_DPRAM_D4		EXYNOS5_GPY5(4)
+#define	GPIO_DPRAM_D5		EXYNOS5_GPY5(5)
+#define	GPIO_DPRAM_D6		EXYNOS5_GPY5(6)
+#define	GPIO_DPRAM_D7		EXYNOS5_GPY5(7)
+#define	GPIO_DPRAM_D8		EXYNOS5_GPY6(0)
+#define	GPIO_DPRAM_D9		EXYNOS5_GPY6(1)
+#define	GPIO_DPRAM_D10		EXYNOS5_GPY6(2)
+#define	GPIO_DPRAM_D11		EXYNOS5_GPY6(3)
+#define	GPIO_DPRAM_D12		EXYNOS5_GPY6(4)
+#define	GPIO_DPRAM_D13		EXYNOS5_GPY6(5)
+#define	GPIO_DPRAM_D14		EXYNOS5_GPY6(6)
+#define	GPIO_DPRAM_D15		EXYNOS5_GPY6(7)
+#define	GPIO_DPRAM_INT		EXYNOS5_GPX0(5)
+#define	GPIO_DPRAM_REN		EXYNOS5_GPY0(4)
+#define	GPIO_DPRAM_WEN		EXYNOS5_GPY0(5)
+
+#define	GPIO_ACC_INT			EXYNOS5_GPX1(4)
+
+#define	GPIO_NFC_WAKE			EXYNOS5_GPX1(5)
+
+#define	GPIO_SPI_INT			EXYNOS5_GPX1(6)
+
+#define	GPIO_NFC_IRQ			EXYNOS5_GPX1(7)
+
+#define	GPIO_VOL_UP			EXYNOS5_GPX2(0)
+#define	GPIO_VOL_DOWN			EXYNOS5_GPX2(1)
+
+#define	GPIO_MSENSE_RDY			EXYNOS5_GPX2(2)
+
+#define	GPIO_ADC_INT			EXYNOS5_GPX2(4)
+
+#define	GPIO_WLAN_HOST_WAKE		EXYNOS5_GPX2(5)
+
+#define	GPIO_BT_HOST_WAKE		EXYNOS5_GPX2(6)
+
+#define	GPIO_nPOWER			EXYNOS5_GPX2(7)
+
+#define	GPIO_FUEL_ALERT		EXYNOS5_GPX2(3)
+#define	GPIO_FUEL_SCL_18V	EXYNOS5_GPZ(6)
+#define	GPIO_FUEL_SDA_18V	EXYNOS5_GPZ(5)
+
+#define	GPIO_GPS_PWR_EN		EXYNOS5_GPE1(0)
+#define	GPIO_GPS_nRST		EXYNOS5_GPE0(6)
+#define	GPIO_GPS_CTS		EXYNOS5_GPA0(6)
+#define	GPIO_GPS_RTS		EXYNOS5_GPA0(7)
+#define	GPIO_GPS_RXD		EXYNOS5_GPA0(4)
+#define	GPIO_GPS_TXD		EXYNOS5_GPA0(5)
+
+#define	GPIO_GPS_CTS_AF		2
+#define	GPIO_GPS_RTS_AF		2
+#define	GPIO_GPS_RXD_AF		2
+#define	GPIO_GPS_TXD_AF		2
+
+
+#define	GPIO_T_FLASH_DETECT		EXYNOS5_GPX3(4)
+
+#define	GPIO_EAR_SEND_END		EXYNOS5_GPX3(5)
+
+#define	GPIO_HDMI_CEC			EXYNOS5_GPX3(6)
+#define	GPIO_HDMI_HPD			EXYNOS5_GPX3(7)
+
+#define	GPIO_TF_EN			EXYNOS5_GPY2(0)
+
+#define	GPIO_5M_CAM_RESET		EXYNOS5_GPE0(0)
+
+#define	GPIO_CAM_FLASH_EN		EXYNOS5_GPE0(3)
+#define	GPIO_CAM_FLASH_SET		EXYNOS5_GPE0(4)
+
+#define	GPIO_UART_SEL			EXYNOS5_GPE0(5)
+
+#define	GPIO_GPS_nRST			EXYNOS5_GPE0(6)
+
+#define	GPIO_ISP_TXD			EXYNOS5_GPE0(7)
+
+#define	GPIO_GPS_EN			EXYNOS5_GPE1(0)
+
+#define	GPIO_ISP_RXD			EXYNOS5_GPE1(1)
+
+#define	GPIO_5M_CAM_SDA_18V		EXYNOS5_GPF0(0)
+#define	GPIO_5M_CAM_SCL_18V		EXYNOS5_GPF0(1)
+
+#define	GPIO_VT_CAM_SDA_18V		EXYNOS5_GPF0(2)
+#define	GPIO_VT_CAM_SCL_18V		EXYNOS5_GPF0(3)
+
+#define	GPIO_NFC_SPI_CLK		EXYNOS5_GPF1(0)
+#define	GPIO_NFC_SPI_CS			EXYNOS5_GPF1(1)
+#define	GPIO_NFC_SPI_MISO		EXYNOS5_GPF1(2)
+#define	GPIO_NFC_SPI_MOSI		EXYNOS5_GPF1(3)
+
+#define	GPIO_NFC_CLK_REQ		EXYNOS5_GPG0(2)
+
+#define	GPIO_2MIC_WAKE			EXYNOS5_GPG0(3)
+#define	GPIO_2MIC_RST			EXYNOS5_GPG0(4)
+
+#define	GPIO_LED_BACKLIGHT_RESET	EXYNOS5_GPG0(5)
+
+#define	GPIO_HDMI_LS_EN			EXYNOS5_GPG0(7)
+
+#define	GPIO_MHL_DSCL_18V	EXYNOS5_GPB3(1)
+#define	GPIO_MHL_DSDA_18V	EXYNOS5_GPB3(0)
+#define	GPIO_MHL_INT		EXYNOS5_GPG0(6)
+#define	GPIO_MHL_RST		EXYNOS5_GPG0(7)
+#define	GPIO_MHL_SCL_18V	EXYNOS5_GPA0(5)
+#define	GPIO_MHL_SDA_18V	EXYNOS5_GPA0(4)
+
+#define MHL_INT_IRQ		gpio_to_irq(GPIO_MHL_INT)
+#define GPIO_MHL_INT_AF		S3C_GPIO_SFN(0xF)
+
+#define	GPIO_MOTOR_EN		EXYNOS5_GPD1(6)
+#define	GPIO_MOTOR_PWM		EXYNOS5_GPB2(1)
+#define	GPIO_MOTOR_SCL_18V	EXYNOS5_GPD1(3)
+#define	GPIO_MOTOR_SDA_18V	EXYNOS5_GPD1(2)
+
+#define	GPIO_MSENSE_RDY		EXYNOS5_GPX2(2)
+#define	GPIO_MSENSE_RST		EXYNOS5_GPG2(0)
+#define	GPIO_MSENSE_SDA		EXYNOS5_GPV2(7)
+#define	GPIO_MSENSE_SCL		EXYNOS5_GPV2(6)
+
+#define	GPIO_PS_ALS_SDA		EXYNOS5_GPG0(0)
+#define	GPIO_PS_ALS_SCL		EXYNOS5_GPG0(1)
+#define	GPIO_PS_VOUT		EXYNOS5_GPH1(2)
+#define	GPIO_HUM_SDA		EXYNOS5_GPV2(5)
+#define	GPIO_HUM_SCL		EXYNOS5_GPV2(4)
+
+#define	GPIO_CAM_FLASH_EN_T		EXYNOS5_GPG1(0)
+#define	GPIO_CAM_FLASH_SET_T		EXYNOS5_GPG1(1)
+
+#define	GPIO_TOUCH_CHG			EXYNOS5_GPG1(2)
+#define	GPIO_TOUCH_RESET		EXYNOS5_GPG1(3)
+
+#define	GPIO_TA_nCHG			EXYNOS5_GPG1(4)
+#define	GPIO_TA_EN			EXYNOS5_GPG1(5)
+#define	GPIO_TA_nCONNECTED	EXYNOS5_GPX0(0)
+
+#define	GPIO_CAM_VT_nRST		EXYNOS5_GPG1(6)
+
+#define	GPIO_MSENSE_RST			EXYNOS5_GPG2(0)
+
+#define	GPIO_VTCAM_MCLK			EXYNOS5_GPG2(1)
+
+#define	GPIO_USB_SEL1			EXYNOS5_GPH0(1)
+
+#define	GPIO_TP 			EXYNOS5_GPH0(2)
+
+#define	GPIO_CAM_MCLK			EXYNOS5_GPH0(3)
+
+#define	GPIO_WM8994_LDO		EXYNOS5_GPH1(1)
+
+#define	GPIO_ALS_nRST			EXYNOS5_GPH1(2)
+
+#define	GPIO_BT_WAKE			EXYNOS5_GPH1(3)
+
+#define	GPIO_LCD_EN			EXYNOS5_GPH1(7)
+
+#define	GPIO_MM_I2S_CLK			EXYNOS5_GPZ(0)
+#define	GPIO_MM_I2S_SYNC		EXYNOS5_GPZ(2)
+#define	GPIO_MM_I2S_DI			EXYNOS5_GPZ(3)
+#define	GPIO_MM_I2S_DO			EXYNOS5_GPZ(4)
+
+#define	GPIO_BUCK4_SEL			EXYNOS5_GPV0(0)
+
+#define	GPIO_BUCK3_SEL			EXYNOS5_GPV0(1)
+
+#define	GPIO_5M_CORE_EN			EXYNOS5_GPV0(2)
+
+#define	GPIO_CAM_IO_EN			EXYNOS5_GPV0(3)
+
+#define	GPIO_BUCK2_SEL			EXYNOS5_GPV0(4)
+
+#define	GPIO_PMIC_DVS3			EXYNOS5_GPV0(5)
+#define	GPIO_PMIC_DVS2			EXYNOS5_GPV0(6)
+#define	GPIO_PMIC_DVS1			EXYNOS5_GPV0(7)
+
+#define	GPIO_WLREG_ON			EXYNOS5_GPV1(0)
+
+#define	GPIO_HW_REV3			EXYNOS5_GPV1(1)
+#define	GPIO_HW_REV2			EXYNOS5_GPV1(2)
+#define	GPIO_HW_REV1			EXYNOS5_GPV1(3)
+#define	GPIO_HW_REV0			EXYNOS5_GPV1(4)
+
+#define GPIO_WLAN_EN            EXYNOS5_GPV1(0)
+#define GPIO_WLAN_EN_AF         1
+#define GPIO_WLAN_HOST_WAKE     EXYNOS5_GPX2(5)
+#define GPIO_WLAN_HOST_WAKE_AF  0xF
+#define GPIO_WLAN_SDIO_CLK      EXYNOS5_GPC3(0)
+#define GPIO_WLAN_SDIO_CLK_AF   2
+#define GPIO_WLAN_SDIO_CMD      EXYNOS5_GPC3(1)
+#define GPIO_WLAN_SDIO_CMD_AF   2
+#define GPIO_WLAN_SDIO_D0       EXYNOS5_GPC3(3)
+#define GPIO_WLAN_SDIO_D0_AF    2
+#define GPIO_WLAN_SDIO_D1       EXYNOS5_GPC3(4)
+#define GPIO_WLAN_SDIO_D1_AF    2
+#define GPIO_WLAN_SDIO_D2       EXYNOS5_GPC3(5)
+#define GPIO_WLAN_SDIO_D2_AF    2
+#define GPIO_WLAN_SDIO_D3       EXYNOS5_GPC3(6)
+#define GPIO_WLAN_SDIO_D3_AF    2
+/**
+ *  Remappig for downward compatibility.
+ */
+#define	GPIO_PMIC_IRQ		GPIO_AP_PMIC_IRQ
+
+#define	GPIO_5M_nRST		GPIO_5M_CAM_RESET
+
+/* Definitions for DPRAM */
+#define GPIO_DPRAM_CSN		EXYNOS5_GPY0(0)
+#define GPIO_DPRAM_CSN0		EXYNOS5_GPY0(0)
+#define GPIO_DPRAM_CSN1		EXYNOS5_GPY0(1)
+#define GPIO_DPRAM_CSN2		EXYNOS5_GPY0(2)
+#define GPIO_DPRAM_CSN3		EXYNOS5_GPY0(3)
+#define GPIO_DPRAM_REN		EXYNOS5_GPY0(4)
+#define GPIO_DPRAM_WEN		EXYNOS5_GPY0(5)
+/* #define GPIO_DPRAM_LBN		EXYNOS4_GPY1(0) // for via modem */
+/* #define GPIO_DPRAM_UBN		EXYNOS4_GPY1(1) // for via modem */
+#define GPIO_SROM_ADDR_BUS_LOW	EXYNOS5_GPY3(0)
+#define GPIO_SROM_ADDR_BUS_HIGH	EXYNOS5_GPY4(0)
+#define GPIO_SROM_DATA_BUS_LOW	EXYNOS5_GPY5(0)
+#define GPIO_SROM_DATA_BUS_HIGH	EXYNOS5_GPY6(0)
+
+/* Definitions for CMC221 */
+#define CP_CMC221_PMIC_PWRON	EXYNOS5_GPD1(5)
+#define CP_CMC221_CPU_RST	EXYNOS5_GPB0(1)
+#define GPIO_LTE_ACTIVE		EXYNOS5_GPX1(6)
+#define LTE_ACTIVE_IRQ		IRQ_EINT(14)	/* IRQ of GPX1[6] */
+
+#define GPIO_CMC_IDPRAM_INT_00	EXYNOS5_GPX0(5)
+#define CMC_IDPRAM_INT_IRQ_00	IRQ_EINT(5)	/* IRQ of GPX0[5] */
+
+#define GPIO_CMC_IDPRAM_STATUS	EXYNOS5_GPX0(3) /* CMC2AP_INT_1 */
+#define GPIO_CMC_IDPRAM_WAKEUP	EXYNOS5_GPX1(2) /* AP2CMC_INT_3 */
+/* #define GPIO_ACTIVE_STATE	EXYNOS4_GPF1(1) // for USB */
+#define GPIO_IPC_SLAVE_WAKEUP	EXYNOS5_GPX0(6) /* AP2CMC_INT_1 */
+#define GPIO_IPC_HOST_WAKEUP	EXYNOS5_GPX1(0) /* CMC2AP_INT_2 */
+
+#define	GPIO_CMC_CLK_18V	GPIO_NFC_SPI_CLK
+#define	GPIO_CMC_CS_18V		GPIO_NFC_SPI_CS
+
+#define	GPIO_FM34_BYPASS	EXYNOS5_GPH1(4)
+#define	GPIO_FM34_PWDN		GPIO_2MIC_WAKE
+#define	GPIO_FM34_RESET		GPIO_2MIC_RST
+#define	GPIO_FM34_SCL_18V	GPIO_MM_SCL_18V
+#define	GPIO_FM34_SDA_18V	GPIO_MM_SDA_18V
+
+#define	GPIO_ES305_WAKEUP	GPIO_2MIC_WAKE
+#define	GPIO_ES305_RESET	GPIO_2MIC_RST
+
+#endif /* __MACH_GPIO_P10_H */
diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev02-midas.h b/arch/arm/mach-exynos/include/mach/gpio-rev02-midas.h
new file mode 100644
index 0000000..d847177
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/gpio-rev02-midas.h
@@ -0,0 +1,244 @@
+#ifndef __MACH_GPIO_MIDAS_H
+#define __MACH_GPIO_MIDAS_H __FILE__
+
+#include <mach/gpio.h>
+
+extern void midas_config_gpio_table(void);
+extern void midas_config_sleep_gpio_table(void);
+
+#define GPIO_eMMC_EN		EXYNOS4_GPK0(2)
+
+#define GPIO_BOOT_MODE		EXYNOS4_GPX0(3)
+
+#define GPIO_REC_PCM_SYNC	EXYSNO4_GPC0(2)
+#define GPIO_REC_PCM_IN		EXYSNO4_GPC0(3)
+#define GPIO_REC_PCM_OUT	EXYSNO4_GPC0(4)
+
+#define GPIO_IF_PMIC_SDA	EXYNOS4_GPB(0)
+#define GPIO_IF_PMIC_SCL	EXYNOS4_GPB(1)
+#define GPIO_PMIC_SDA		EXYNOS4_GPB(2)
+#define GPIO_PMIC_SCL		EXYNOS4_GPB(3)
+
+#define GPIO_CAM_VT_nRST	EXYNOS4212_GPM1(6)
+#define GPIO_VT_CCAM_SCL_18V	EXYNOS4212_GPM4(2)
+#define GPIO_VT_CCAM_SDA_18V	EXYNOS4212_GPM4(3)
+
+#define GPIO_CAM_SPI_SCLK	EXYNOS4_GPB(4)
+#define GPIO_CAM_SPI_SSN	EXYNOS4_GPB(5)
+#define GPIO_CAM_SPI_MISO	EXYNOS4_GPB(6)
+#define GPIO_CAM_SPI_MOSI	EXYNOS4_GPB(7)
+
+#define GPIO_8M_CAM_SDA_18V	EXYNOS4_GPD1(0)
+#define GPIO_8M_CAM_SCL_18V	EXYNOS4_GPD1(1)
+#define GPIO_CAM_MCLK		EXYNOS4212_GPJ1(3)
+#define GPIO_VTCAM_MCLK		EXYNOS4212_GPM2(2)
+
+/* Sensors & NFC*/
+#define GPIO_PS_ALS_EN		EXYNOS4212_GPJ0(5)
+#define GPIO_PS_ALS_SDA_28V	EXYNOS4_GPK1(1)
+#define GPIO_PS_ALS_SCL_28V	EXYNOS4_GPK2(2)
+#define GPIO_PS_ALS_INT		EXYNOS4_GPX0(2)
+
+#define GPIO_GYRO_DE		EXYNOS4_GPL2(0)
+#define GPIO_GYRO_INT		EXYNOS4_GPX0(0)
+#define GPIO_GSENSE_SDA_18V	EXYNOS4_GPD1(2)
+#define GPIO_GSENSE_SCL_18V	EXYNOS4_GPD1(3)
+
+#define GPIO_MSENSOR_INT	EXYNOS4_GPX2(2)
+#define GPIO_MSENSOR_SDA_18V	EXYNOS4_GPY2(4)
+#define GPIO_MSENSOR_SCL_18V	EXYNOS4_GPY2(5)
+
+#define GPIO_BSENSE_SDA_18V	EXYNOS4_GPY4(3)
+#define GPIO_BENSE_SCL_18V	EXYNOS4_GPY4(4)
+#define GPIO_BARO_INT		EXYNOS4_GPX0(1)
+
+#define GPIO_NFC_SCL_18V	EXYNOS4_GPY0(0)
+#define GPIO_NFC_SDA_18V	EXYNOS4_GPY0(1)
+#define GPIO_NFC_IRQ		EXYNOS4_GPX1(7)
+#define GPIO_NFC_EN		EXYNOS4_GPL2(6)
+#define GPIO_NFC_FIRMWARE	EXYNOS4_GPL2(7)
+/* Sensors & NFC*/
+
+#define GPIO_DET_35		EXYNOS4_GPX0(1)
+
+#define GPIO_TF_EN		EXYNOS4_GPY0(4)
+
+
+#define GPIO_PMU_RST		EXYNOS4_GPX3(2)
+
+#define GPIO_PMIC_IRQ		EXYNOS4_GPX0(7)
+#define GPIO_IF_PMIC_IRQ	EXYNOS4_GPX1(5)
+
+#define GPIO_PMIC_DVS1		EXYSNO4_GPY5(5)
+#define GPIO_PMIC_DVS2		EXYSNO4_GPY5(6)
+#define GPIO_PMIC_DVS3		EXYSNO4_GPY5(7)
+
+#define GPIO_BUCK2_SEL		EXYNOS4_GPY6(0)
+#define GPIO_BUCK3_SEL		EXYNOS4_GPY6(3)
+#define GPIO_BUCK4_SEL		EXYNOS4_GPY6(4)
+
+#define GPIO_TSP_INT		EXYNOS4_GPX0(4)
+#define GPIO_TSP_SDA_18V	EXYNOS4_GPA1(2)
+#define GPIO_TSP_SCL_18V	EXYNOS4_GPA1(3)
+
+#define GPIO_BT_nRST		EXYNOS4_GPL1(0)
+#define GPIO_BT_EN		EXYNOS4_GPL0(6)
+#define GPIO_BT_WAKE		EXYNOS4_GPX3(1)
+#define GPIO_BT_HOST_WAKE	EXYNOS4_GPX2(6)
+#define IRQ_BT_HOST_WAKE	IRQ_EINT(22)
+
+#define GPIO_BT_RXD		EXYNOS4_GPA0(0)
+#define GPIO_BT_RXD_AF		2
+
+#define GPIO_BT_TXD		EXYNOS4_GPA0(1)
+#define GPIO_BT_TXD_AF		2
+
+#define GPIO_BT_CTS		EXYNOS4_GPA0(2)
+#define GPIO_BT_CTS_AF		2
+
+#define GPIO_BT_RTS		EXYNOS4_GPA0(3)
+#define GPIO_BT_RTS_AF		2
+
+#define GPIO_GPS_CNTL		EXYNOS4_GPY3(6)
+#define GPIO_GPS_nRST		EXYNOS4_GPY6(6)
+#define GPIO_GPS_PWR_EN		EXYNOS4_GPY6(7)
+
+#define GPIO_GPS_RXD		EXYNOS4_GPA0(4)
+#define GPIO_GPS_RXD_AF		2
+
+#define GPIO_GPS_TXD		EXYNOS4_GPA0(5)
+#define GPIO_GPS_TXD_AF		2
+
+#define GPIO_GPS_CTS		EXYNOS4_GPA0(6)
+#define GPIO_GPS_CTS_AF		2
+
+#define GPIO_GPS_RTS		EXYNOS4_GPA0(7)
+#define GPIO_GPS_RTS_AF		2
+
+#define GPIO_FLM_RXD		EXYNOS4_GPA1(4)
+#define GPIO_FLM_RXD_AF		2
+
+#define GPIO_FLM_TXD		EXYNOS4_GPA1(5)
+#define GPIO_FLM_TXD_AF		2
+
+#define GPIO_3_TOUCH_SCL	EXYNOS4_GPL0(1)
+#define GPIO_3_TOUCH_SDA	EXYNOS4_GPL0(2)
+#define GPIO_3_TOUCH_INT	EXYNOS4212_GPJ1(0)
+#define GPIO_TOUCH_EN		EXYNOS4212_GPJ0(3)
+
+#define GPIO_PWM0		EXYNOS4_GPD0(0)
+#define GPIO_PWM1		EXYNOS4_GPD0(1)
+#define GPIO_PWM2		EXYNOS4_GPD0(2)
+#define GPIO_PWM3		EXYNOS4_GPD0(3)
+
+#define GPIO_VIBTONE_EN		EXYNOS4212_GPJ0(6)
+
+#define GPIO_WLAN_EN		EXYNOS4212_GPJ0(0)
+#define GPIO_WLAN_EN_AF		1
+#define GPIO_WLAN_HOST_WAKE	EXYNOS4_GPX2(5)
+#define GPIO_WLAN_HOST_WAKE_AF	0xF
+#define GPIO_WLAN_SDIO_CLK	EXYNOS4_GPK3(0)
+#define GPIO_WLAN_SDIO_CLK_AF	2
+#define GPIO_WLAN_SDIO_CMD	EXYNOS4_GPK3(1)
+#define GPIO_WLAN_SDIO_CMD_AF	2
+#define GPIO_WLAN_SDIO_D0	EXYNOS4_GPK3(3)
+#define GPIO_WLAN_SDIO_D0_AF	2
+#define GPIO_WLAN_SDIO_D1	EXYNOS4_GPK3(4)
+#define GPIO_WLAN_SDIO_D1_AF	2
+#define GPIO_WLAN_SDIO_D2	EXYNOS4_GPK3(5)
+#define GPIO_WLAN_SDIO_D2_AF	2
+#define GPIO_WLAN_SDIO_D3	EXYNOS4_GPK3(6)
+#define GPIO_WLAN_SDIO_D3_AF	2
+
+#define GPIO_USB_SEL		EXYNOS4212_GPJ0(1)
+#define GPIO_UART_SEL		EXYNOS4_GPY4(7)
+#define GPIO_S_LED_I2C_SCL	EXYNOS4_GPF2(6)
+#define GPIO_S_LED_I2C_SDA	EXYNOS4_GPF2(7)
+
+#define GPIO_OTG_EN		EXYNOS4_GPY3(2)
+
+#define GPIO_ISP_CORE_EN	EXYNOS4_GPY6(2)
+#define GPIO_ISP_TXD		EXYNOS4212_GPM4(5)
+#define GPIO_ISP_RXD		EXYNOS4212_GPM4(6)
+
+#define GPIO_TA_EN		EXYNOS4_GPL2(2)
+
+
+#define GPIO_MHL_SEL		EXYNOS4_GPL0(3)
+
+/* Definitions for Sii 9244B0 */
+#define GPIO_MHL_RST		EXYNOS4_GPF3(4)
+#define GPIO_MHL_INT		EXYNOS4_GPF3(5)
+#define GPIO_MHL_INT_AF		S3C_GPIO_SFN(0xF)
+#define GPIO_MHL_WAKE_UP	EXYNOS4212_GPJ1(4)
+
+#define GPIO_MHL_SCL_1_8V	EXYNOS4_GPY3(2)
+#define GPIO_MHL_SDA_1_8V	EXYNOS4_GPY3(0)
+
+#define GPIO_MHL_DSCL_2_8V	EXYNOS4_GPK1(0)
+#define GPIO_MHL_DSDA_2_8V	EXYNOS4_GPK1(2)
+
+#define MHL_INT_IRQ		gpio_to_irq(GPIO_MHL_INT)
+#define MHL_WAKEUP_IRQ		gpio_to_irq(GPIO_MHL_WAKE_UP)
+
+#define GPIO_HDMI_CEC		EXYNOS4_GPX3(6)
+#define GPIO_HDMI_EN		EXYNOS4_GPL1(1)
+#define GPIO_HDMI_HPD		EXYNOS4_GPX3(7)
+
+#define GPIO_ACC_INT		EXYNOS4_GPX1(4)
+
+#define GPIO_CP_DUMP_INT	EXYNOS4_GPX1(2)
+#define GPIO_IPC_SLAVE_WAKEUP	EXYNOS4_GPX1(0)
+#define GPIO_IPC_HOST_WAKEUP	EXYNOS4_GPX1(1)
+#define GPIO_SUSPEND_REQUEST	EXYNOS4_GPX1(3)
+#define GPIO_SIM_DETECT		EXYNOS4_GPX3(3)
+#define GPIO_ACTIVE_STATE	EXYNOS4_GPY3(5)
+
+#define GPIO_VOL_UP		EXYNOS4_GPX2(0)
+#define GPIO_VOL_DOWN		EXYNOS4_GPX2(1)
+#define GPIO_nPOWER		EXYNOS4_GPX2(7)
+#define GPIO_OK_KEY		EXYNOS4_GPX3(5)
+
+#define GPIO_ISP_RESET		EXYNOS4_GPY3(7)
+#define GPIO_ISP_STANDBY	EXYNOS4_GPY5(4)
+
+#define GPIO_FUEL_SDA		EXYNOS4_GPY4(0)
+#define GPIO_FUEL_SCL		EXYNOS4_GPY4(1)
+#define GPIO_FUEL_ALERT		EXYNOS4_GPX2(3)
+
+#define GPIO_ADC_SDA		EXYNOS4_GPY2(2)
+#define GPIO_ADC_SCL		EXYNOS4_GPY2(3)
+#define GPIO_ADC_INT		EXYNOS4_GPX2(4)
+
+#define GPIO_MLCD_RST		EXYNOS4_GPY4(5)
+
+#define GPIO_PDA_ACTIVE		EXYNOS4_GPY4(2)
+
+#define GPIO_HW_REV0		EXYNOS4_GPY5(0)
+#define GPIO_HW_REV1		EXYNOS4_GPY5(1)
+#define GPIO_HW_REV2		EXYNOS4_GPY5(2)
+#define GPIO_HW_REV3		EXYNOS4_GPY5(3)
+
+#define GPIO_CAM_IO_EN		EXYNOS4_GPY6(1)
+#define GPIO_CAM_AF_EN		EXYNOS4_GPY6(5)
+#define GPIO_VIBTONE_PWM	EXYNOS4_GPD0(1)
+
+#define GPIO_VIBTONE_PWM	EXYNOS4_GPD0(1)
+
+#define GPIO_CODEC_SDA_18V	EXYNOS4_GPD0(2)
+#define GPIO_CODEC_SCL_18V	EXYNOS4_GPD0(3)
+#define GPIO_CODEC_LDO_EN	EXYNOS4212_GPJ0(4)
+
+#define GPIO_WM8994_LDO		EXYNOS4212_GPJ0(4)
+
+/* Definitions for XMM6262 and C2C */
+#define CP_PMU_RST_N		EXYNOS4_GPX3(2)
+#define CP_RESET_REQ_N		EXYNOS4_GPY4(6)
+#define CP_ON			EXYNOS4_GPL2(5)
+#define PDA_ACTIVE		EXYNOS4_GPY4(2)
+#define PHONE_ACTIVE		EXYNOS4_GPX1(6)
+#define PHONE_ACTIVE_IRQ	IRQ_EINT(14)
+#define CP_DUMP_INT		EXYNOS4_GPX1(2)
+#define CP_DUMP_INT_IRQ		IRQ_EINT(10)
+
+#endif /* __MACH_GPIO_MIDAS_H */
diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev03-c1kor.h b/arch/arm/mach-exynos/include/mach/gpio-rev03-c1kor.h
new file mode 100644
index 0000000..809b19d
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/gpio-rev03-c1kor.h
@@ -0,0 +1,346 @@
+#ifndef __MACH_GPIO_C1KOR_H
+#define __MACH_GPIO_C1KOR_H __FILE__
+
+#include <mach/gpio.h>
+
+extern void midas_config_gpio_table(void);
+extern void midas_config_sleep_gpio_table(void);
+
+#define GPIO_eMMC_EN		EXYNOS4_GPK0(2)
+
+#define GPIO_BOOT_MODE		EXYNOS4_GPX0(3)
+
+#define GPIO_FM_I2S_CLK		EXYNOS4_GPC0(0)
+#define GPIO_FM_I2S_SYNC	EXYNOS4_GPC0(2)
+#define GPIO_FM_I2S_DI		EXYNOS4_GPC0(3)
+#define GPIO_FM_I2S_DO		EXYNOS4_GPC0(4)
+
+#define GPIO_IF_PMIC_SDA	EXYNOS4212_GPM2(0)
+#define GPIO_IF_PMIC_SCL	EXYNOS4212_GPM2(1)
+#define GPIO_PMIC_SDA		EXYNOS4_GPB(2)
+#define GPIO_PMIC_SCL		EXYNOS4_GPB(3)
+
+#define GPIO_ADC_SCL		EXYNOS4_GPY0(2)
+#define GPIO_ADC_SDA		EXYNOS4_GPY0(3)
+#define GPIO_ADC_INT		EXYNOS4_GPX2(4)
+
+#define GPIO_CAM_SPI_SCLK	EXYNOS4_GPB(4)
+#define GPIO_CAM_SPI_SSN	EXYNOS4_GPB(5)
+#define GPIO_CAM_SPI_MISO	EXYNOS4_GPB(6)
+#define GPIO_CAM_SPI_MOSI	EXYNOS4_GPB(7)
+
+#define GPIO_CAM_MCLK		EXYNOS4212_GPJ1(3)
+#define GPIO_VTCAM_MCLK		EXYNOS4212_GPM2(2)
+
+#define GPIO_ISP_STANDBY			EXYNOS4212_GPM0(1)
+#define GPIO_CAM_IO_EN				EXYNOS4212_GPM0(2)
+#define GPIO_ISP_CORE_EN			EXYNOS4212_GPM0(3)
+#define GPIO_CAM_AF_EN				EXYNOS4212_GPM0(4)
+#define GPIO_CAM_SENSOR_CORE_EN		EXYNOS4212_GPM0(7)
+#define GPIO_CAM_VT_nRST	EXYNOS4212_GPM1(6)
+
+#define GPIO_8M_CAM_SCL_18V	EXYNOS4_GPD1(0)
+#define GPIO_8M_CAM_SDA_18V	EXYNOS4_GPD1(1)
+
+#define GPIO_VT_CAM_SCL_18V	EXYNOS4212_GPM4(2)
+#define GPIO_VT_CAM_SDA_18V	EXYNOS4212_GPM4(3)
+#define GPIO_VT_CAM_ID		EXYNOS4_GPF1(2)
+
+/* Sensors & NFC*/
+#define GPIO_PS_ALS_EN		EXYNOS4212_GPJ0(5)
+#define GPIO_PS_ALS_SDA_28V	EXYNOS4_GPK1(1)
+#define GPIO_PS_ALS_SCL_28V	EXYNOS4_GPK2(2)
+#define GPIO_PS_ALS_INT		EXYNOS4_GPX0(2)
+
+#define GPIO_ACC_INT		EXYNOS4_GPX0(0)
+
+#define GPIO_GYRO_DE		EXYNOS4_GPL2(0)
+#define GPIO_GPS_nRST		EXYNOS4_GPL2(1)
+#define GPIO_GPS_PWR_EN		EXYNOS4_GPL2(2)
+
+#define GPIO_GYRO_INT		EXYNOS4_GPF0(3)
+#define GPIO_GSENSE_SDA_18V	EXYNOS4_GPD1(2)
+#define GPIO_GSENSE_SCL_18V	EXYNOS4_GPD1(3)
+
+#define GPIO_MSENSOR_INT	EXYNOS4212_GPJ0(7)
+#define GPIO_MSENSOR_SDA_18V	EXYNOS4_GPY2(4)
+#define GPIO_MSENSOR_SCL_18V	EXYNOS4_GPY2(5)
+
+#define GPIO_BENSE_SCL_18V	EXYNOS4_GPY2(3)
+#define GPIO_BSENSE_SDA_18V	EXYNOS4_GPY2(2)
+#define GPIO_BARO_INT		EXYNOS4_GPF0(5)
+
+#define GPIO_TF_EN		EXYNOS4_GPY2(0)
+
+#define GPIO_NFC_SCL_18V	EXYNOS4_GPD1(1)
+#define GPIO_NFC_SDA_18V	EXYNOS4_GPD1(0)
+#define GPIO_NFC_SCL_18V_00	EXYNOS4_GPB(3)
+#define GPIO_NFC_SDA_18V_00	EXYNOS4_GPB(2)
+#define GPIO_NFC_IRQ		EXYNOS4_GPX1(7)
+#define GPIO_NFC_EN		EXYNOS4_GPL2(6)
+#define GPIO_NFC_FIRMWARE	EXYNOS4_GPL2(7)
+#define GPIO_NFC_CLK_REQ	EXYNOS4212_GPM0(0)
+/* Sensors & NFC*/
+
+#define GPIO_DET_35		EXYNOS4_GPX0(1)
+
+#define GPIO_MIC_BIAS_EN	EXYNOS4_GPF1(7)
+#define GPIO_SUB_MIC_BIAS_EN	EXYNOS4_GPF2(0)
+
+#define GPIO_PMIC_IRQ		EXYNOS4_GPX0(7)
+#define GPIO_IF_PMIC_IRQ	EXYNOS4_GPX1(5)
+
+#define GPIO_TSP_INT		EXYNOS4212_GPM2(3)
+#define GPIO_TSP_SDA_18V	EXYNOS4_GPA1(2)
+#define GPIO_TSP_SCL_18V	EXYNOS4_GPA1(3)
+
+#define GPIO_BT_EN		EXYNOS4_GPL0(6)
+#define GPIO_BT_WAKE		EXYNOS4_GPX3(1)
+#define GPIO_BT_HOST_WAKE	EXYNOS4_GPX2(6)
+#define IRQ_BT_HOST_WAKE	IRQ_EINT(22)
+
+#define GPIO_BT_RXD		EXYNOS4_GPA0(0)
+#define GPIO_BT_RXD_AF		2
+
+#define GPIO_BT_TXD		EXYNOS4_GPA0(1)
+#define GPIO_BT_TXD_AF		2
+
+#define GPIO_BT_CTS		EXYNOS4_GPA0(2)
+#define GPIO_BT_CTS_AF		2
+
+#define GPIO_BT_RTS		EXYNOS4_GPA0(3)
+#define GPIO_BT_RTS_AF		2
+
+#define GPIO_GPS_RXD		EXYNOS4_GPA0(4)
+#define GPIO_GPS_RXD_AF		2
+
+#define GPIO_GPS_TXD		EXYNOS4_GPA0(5)
+#define GPIO_GPS_TXD_AF		2
+
+#define GPIO_GPS_CTS		EXYNOS4_GPA0(6)
+#define GPIO_GPS_CTS_AF		2
+
+#define GPIO_GPS_RTS		EXYNOS4_GPA0(7)
+#define GPIO_GPS_RTS_AF		2
+
+#define GPIO_FLM_RXD		EXYNOS4_GPA1(4)
+#define GPIO_FLM_RXD_AF		2
+
+#define GPIO_FLM_TXD		EXYNOS4_GPA1(5)
+#define GPIO_FLM_TXD_AF		2
+
+#ifdef CONFIG_FM34_WE395
+#define	GPIO_FM34_PWDN		EXYNOS4_GPL0(3)
+#define	GPIO_FM34_RESET		EXYNOS4_GPL0(1)
+#define	GPIO_FM34_BYPASS	EXYNOS4_GPL0(2)
+#define	GPIO_FM34_RESET_05	EXYNOS4_GPY1(3)
+#define	GPIO_FM34_BYPASS_05	EXYNOS4_GPY1(2)
+#define GPIO_FM34_SCL		EXYNOS4212_GPM4(0)
+#define GPIO_FM34_SDA		EXYNOS4212_GPM4(1)
+#endif
+
+#define GPIO_3_TOUCH_SCL	EXYNOS4_GPL0(1)
+#define GPIO_3_TOUCH_SDA	EXYNOS4_GPL0(2)
+
+
+#define GPIO_HDMI_EN		EXYNOS4_GPL0(4)
+
+#define GPIO_3_TOUCH_INT	EXYNOS4212_GPJ0(3)
+#define GPIO_OK_KEY_ANDROID	EXYNOS4_GPX0(1)
+#define GPIO_3_TOUCH_EN	EXYNOS4212_GPM0(0)
+#if defined(CONFIG_MACH_C1_KOR_LGT)
+#define GPIO_3_TOUCH_LDO_EN EXYNOS4212_GPM3(4)
+#endif
+
+#define GPIO_PWM0		EXYNOS4_GPD0(0)
+#define GPIO_PWM1		EXYNOS4_GPD0(1)
+#define GPIO_PWM2		EXYNOS4_GPD0(2)
+#define GPIO_PWM3		EXYNOS4_GPD0(3)
+
+#define GPIO_VIBTONE_EN		EXYNOS4212_GPJ0(6)
+
+#define GPIO_WLAN_EN		EXYNOS4212_GPJ0(0)
+#define GPIO_WLAN_EN_AF		1
+#define GPIO_WLAN_HOST_WAKE	EXYNOS4_GPX2(5)
+#define GPIO_WLAN_HOST_WAKE_AF	0xF
+#define GPIO_WLAN_SDIO_CLK	EXYNOS4_GPK3(0)
+#define GPIO_WLAN_SDIO_CLK_AF	2
+#define GPIO_WLAN_SDIO_CMD	EXYNOS4_GPK3(1)
+#define GPIO_WLAN_SDIO_CMD_AF	2
+#define GPIO_WLAN_SDIO_D0	EXYNOS4_GPK3(3)
+#define GPIO_WLAN_SDIO_D0_AF	2
+#define GPIO_WLAN_SDIO_D1	EXYNOS4_GPK3(4)
+#define GPIO_WLAN_SDIO_D1_AF	2
+#define GPIO_WLAN_SDIO_D2	EXYNOS4_GPK3(5)
+#define GPIO_WLAN_SDIO_D2_AF	2
+#define GPIO_WLAN_SDIO_D3	EXYNOS4_GPK3(6)
+#define GPIO_WLAN_SDIO_D3_AF	2
+
+#define GPIO_USB_SEL		EXYNOS4212_GPJ0(1)
+
+#define GPIO_LCD_22V_EN		EXYNOS4212_GPM4(4)
+#define GPIO_LCD_22V_EN_00	EXYNOS4_GPC0(1)
+
+#define GPIO_ISP_TXD		EXYNOS4212_GPM4(5)
+#define GPIO_ISP_RXD		EXYNOS4212_GPM4(6)
+
+#define GPIO_TA_EN		EXYNOS4_GPL2(2)
+
+#if !defined(CONFIG_MACH_C1_KOR_LGT)
+#define GPIO_MHL_SEL		EXYNOS4_GPL0(3)
+#endif
+
+#define GPIO_MHL_SDA_1_8V	EXYNOS4_GPF0(4)
+#define GPIO_MHL_SCL_1_8V	EXYNOS4_GPF0(6)
+#define GPIO_MHL_SDA_1_8V_00	EXYNOS4_GPB(2)
+#define GPIO_MHL_SCL_1_8V_00	EXYNOS4_GPB(3)
+
+#define GPIO_OTG_EN		EXYNOS4_GPF0(7)
+
+#define GPIO_OLED_ID		EXYNOS4_GPF1(0)
+#define GPIO_ISP_RESET		EXYNOS4_GPF1(3)
+#define GPIO_FUEL_SCL		EXYNOS4_GPF1(4)
+#define GPIO_FUEL_SDA		EXYNOS4_GPF1(5)
+
+#define GPIO_MLCD_RST		EXYNOS4_GPF2(1)
+#define GPIO_UART_SEL		EXYNOS4_GPF2(3)
+#if defined(CONFIG_MACH_C1_KOR_LGT)
+#define GPIO_LTE_VIA_UART_SEL	EXYNOS4212_GPJ0(6)
+#endif
+#define GPIO_S_LED_I2C_SCL	EXYNOS4_GPF2(6)
+#define GPIO_S_LED_I2C_SDA	EXYNOS4_GPF2(7)
+#define GPIO_OLED_DET		EXYNOS4_GPF3(0)
+
+#define GPIO_PMIC_DVS1		EXYNOS4212_GPM3(0)
+#define GPIO_PMIC_DVS2		EXYNOS4212_GPM3(1)
+
+/* Definitions for Sii 9244B0 */
+#define GPIO_PMIC_DVS3		EXYNOS4212_GPM3(2)
+#define GPIO_BUCK2_SEL		EXYNOS4_GPF3(1)
+#define GPIO_BUCK3_SEL		EXYNOS4_GPF3(2)
+#define GPIO_BUCK4_SEL		EXYNOS4_GPF3(3)
+#define GPIO_MHL_RST		EXYNOS4_GPF3(4)
+#define GPIO_MHL_INT		EXYNOS4_GPF3(5)
+#define GPIO_MHL_INT_AF		S3C_GPIO_SFN(0xF)
+#define GPIO_MHL_WAKE_UP	EXYNOS4212_GPJ1(4)
+
+#define GPIO_RGB_SDA_1_8V	EXYNOS4_GPF0(0)
+#define GPIO_RGB_SCL_1_8V	EXYNOS4_GPF0(1)
+#define GPIO_RGB_INT		EXYNOS4_GPX2(2)
+#define GPIO_VOL_UP		EXYNOS4212_GPJ1(1)
+#define GPIO_VOL_DOWN		EXYNOS4212_GPJ1(2)
+#define GPIO_VOL_UP_00		EXYNOS4_GPX2(2)
+#define GPIO_VOL_DOWN_00	EXYNOS4_GPX3(3)
+
+#define GPIO_CAM_SW_EN		EXYNOS4212_GPJ1(0)
+#define GPIO_TORCH_EN		EXYNOS4212_GPJ1(1)
+#define GPIO_TORCH_SET		EXYNOS4212_GPJ1(2)
+
+#define GPIO_MHL_DSCL_2_8V	EXYNOS4_GPK1(0)
+#define GPIO_MHL_DSDA_2_8V	EXYNOS4_GPK1(2)
+
+#define MHL_INT_IRQ		gpio_to_irq(GPIO_MHL_INT)
+#define MHL_WAKEUP_IRQ		gpio_to_irq(GPIO_MHL_WAKE_UP)
+
+#define GPIO_HDMI_CEC		EXYNOS4_GPX3(6)
+#define GPIO_HDMI_HPD		EXYNOS4_GPX3(7)
+
+#define GPIO_nPOWER		EXYNOS4_GPX2(7)
+#define GPIO_OK_KEY		EXYNOS4_GPX3(5)
+
+#define GPIO_FUEL_ALERT EXYNOS4_GPX2(3)
+#define GPIO_V_BUS_INT  EXYNOS4_GPX2(4)
+#define GPIO_WPC_INT    EXYNOS4_GPX3(0)
+
+#define GPIO_VIBTONE_PWM	EXYNOS4_GPD0(1)
+
+#define GPIO_CODEC_SDA_18V	EXYNOS4_GPD0(2)
+#define GPIO_CODEC_SCL_18V	EXYNOS4_GPD0(3)
+#define GPIO_CODEC_SDA_18V_00	EXYNOS4_GPB(0)
+#define GPIO_CODEC_SCL_18V_00	EXYNOS4_GPB(1)
+
+#define GPIO_CODEC_LDO_EN	EXYNOS4212_GPJ0(4)
+
+#define GPIO_WM8994_LDO		EXYNOS4212_GPJ0(4)
+
+/* Definitions for DPRAM */
+#define GPIO_DPRAM_CSN		EXYNOS4_GPY0(0)
+#define GPIO_DPRAM_CSN0		EXYNOS4_GPY0(0)
+#define GPIO_DPRAM_CSN1		EXYNOS4_GPY0(1)
+#define GPIO_DPRAM_CSN2		EXYNOS4_GPY0(2)
+#define GPIO_DPRAM_CSN3		EXYNOS4_GPY0(3)
+#define GPIO_DPRAM_REN		EXYNOS4_GPY0(4)
+#define GPIO_DPRAM_WEN		EXYNOS4_GPY0(5)
+#define GPIO_DPRAM_LBN		EXYNOS4_GPY1(0)
+#define GPIO_DPRAM_UBN		EXYNOS4_GPY1(1)
+#define GPIO_SROM_ADDR_BUS_LOW	EXYNOS4_GPY3(0)
+#define GPIO_SROM_ADDR_BUS_HIGH	EXYNOS4_GPY4(0)
+#define GPIO_SROM_DATA_BUS_LOW	EXYNOS4_GPY5(0)
+#define GPIO_SROM_DATA_BUS_HIGH	EXYNOS4_GPY6(0)
+
+/* Definitions for CMC221 */
+#define CP_CMC221_PMIC_PWRON	EXYNOS4_GPL2(5)
+#define CP_CMC221_CPU_RST	EXYNOS4_GPL2(4)
+
+#define GPIO_LTE_ACTIVE		EXYNOS4_GPX1(6)
+#define LTE_ACTIVE_IRQ		IRQ_EINT(14)	/* IRQ of GPX1[6] */
+
+#if defined(CONFIG_MACH_C1_KOR_LGT)
+#define GPIO_CMC_IDPRAM_INT_00	EXYNOS4_GPX3(3)
+#define CMC_IDPRAM_INT_IRQ_00	IRQ_EINT(27)	/* IRQ of GPX3[3] */
+#else
+#define GPIO_CMC_IDPRAM_INT_00	EXYNOS4_GPX2(0)
+#define CMC_IDPRAM_INT_IRQ_00	IRQ_EINT(16)	/* IRQ of GPX2[0] */
+#endif
+#define GPIO_CMC_IDPRAM_INT_01	EXYNOS4_GPX2(0)
+#define CMC_IDPRAM_INT_IRQ_01	IRQ_EINT(16)	/* IRQ of GPX2[0] */
+
+#define GPIO_CMC_IDPRAM_STATUS	EXYNOS4_GPX0(5)
+#define GPIO_CMC_IDPRAM_WAKEUP	EXYNOS4_GPX3(2)
+
+#define GPIO_ACTIVE_STATE	EXYNOS4_GPF1(1)
+#define GPIO_IPC_SLAVE_WAKEUP	EXYNOS4_GPX1(0)
+#define GPIO_IPC_HOST_WAKEUP	EXYNOS4_GPX1(1)
+
+#define GPIO_AP2CMC_INT2	EXYNOS4_GPX1(2)
+
+/* Definitions for an USB HUB for CMC221 */
+#define GPIO_USB_HUB_RST	EXYNOS4_GPL0(0)
+#define GPIO_USB_HUB_SCL	EXYNOS4_GPL1(0)
+#define GPIO_USB_HUB_SDA	EXYNOS4_GPL1(1)
+#define GPIO_USB_HUB_INT	EXYNOS4_GPX2(1)
+
+#if defined(CONFIG_MACH_C1_KOR_LGT)
+/* Definitions for CBP7.2 */
+#define GPIO_CBP_PMIC_PWRON	EXYNOS4212_GPM0(6)
+#define GPIO_CBP_PS_HOLD_OFF	EXYNOS4212_GPM1(0)
+#define GPIO_CBP_CP_RST		EXYNOS4_GPF2(4)
+#define GPIO_PDA_ACTIVE		EXYNOS4_GPF1(6)
+
+#define GPIO_CBP_PHONE_ACTIVE	EXYNOS4_GPX1(3)
+#define CBP_PHONE_ACTIVE_IRQ	IRQ_EINT(11)
+
+#define GPIO_CBP_DPRAM_INT_00	EXYNOS4_GPX2(0)
+#define CBP_DPRAM_INT_IRQ_00	IRQ_EINT(16)	/* IRQ of GPX2[0] */
+#define GPIO_CBP_DPRAM_INT_01	EXYNOS4_GPX3(5)
+#define CBP_DPRAM_INT_IRQ_01	IRQ_EINT(29)	/* IRQ of GPX3[5] */
+
+#define GPIO_CBP_BOOT_SEL	EXYNOS4212_GPM0(5)
+#endif
+
+#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE)
+#if defined(CONFIG_MACH_C1_KOR_LGT)
+#define GPIO_TDMB_EN		EXYNOS4_GPC0(0)
+#else
+#define GPIO_TDMB_EN		EXYNOS4_GPC0(2)
+#endif
+#define GPIO_TDMB_INT		EXYNOS4_GPC0(4)
+#define GPIO_TDMB_IRQ		gpio_to_irq(GPIO_TDMB_INT)
+#define GPIO_TDMB_INT_AF	0xf
+#define GPIO_TDMB_SPI_CLK	EXYNOS4_GPC1(1)
+#define GPIO_TDMB_SPI_CS	EXYNOS4_GPC1(2)
+#define GPIO_TDMB_SPI_MISO	EXYNOS4_GPC1(3)
+#define GPIO_TDMB_SPI_MOSI	EXYNOS4_GPC1(4)
+#endif
+
+#endif /* __MACH_GPIO_C1KOR_H */
diff --git a/arch/arm/mach-exynos/include/mach/gpio-u1.h b/arch/arm/mach-exynos/include/mach/gpio-u1.h
new file mode 100644
index 0000000..a4b85ac
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/gpio-u1.h
@@ -0,0 +1,337 @@
+#ifndef __MACH_GPIO_U1_H
+#define __MACH_GPIO_U1_H __FILE__
+
+#ifdef CONFIG_MACH_U1_KOR_LGT
+#define DUMMY_GPIO EXYNOS4_GPL2(2)
+#endif
+#if defined(CONFIG_MACH_U1_BD)
+
+#define GPIO_XMMC0_CDn		EXYNOS4_GPK0(2)
+
+#define GPIO_PS_ALS_SDA		EXYNOS4_GPK2(2)
+#define GPIO_PS_ALS_SCL		EXYNOS4_GPK3(2)
+
+#define GPIO_GYRO_INT		EXYNOS4_GPX0(0)
+#define GPIO_GYRO_FIFOP_INT	EXYNOS4_GPX0(1)
+#define GPIO_PS_ALS_INT		EXYNOS4_GPX0(2)
+
+#define GPIO_BUCK1_EN_A		EXYNOS4_GPX0(5)
+#define GPIO_BUCK1_EN_B		EXYNOS4_GPX0(6)
+#define GPIO_BUCK2_EN		EXYNOS4_GPL0(0)
+#define GPIO_PMIC_IRQ		EXYNOS4_GPX0(7)
+
+#define GPIO_VOL_UP		EXYNOS4_GPX2(0)
+#define GPIO_VOL_DOWN		EXYNOS4_GPX2(1)
+#define GPIO_nPOWER		EXYNOS4_GPX2(7)
+
+#define GPIO_OK_KEY		EXYNOS4_GPX3(5)
+
+#define VT_CAM_SDA_18V		EXYNOS4_GPC1(0)
+#define VT_CAM_SCL_18V		EXYNOS4_GPC1(2)
+
+#define CODEC_VT_SDA_18V	EXYNOS4_GPC1(3)
+#define CODEC_VT_SCL_18V	EXYNOS4_GPC1(4)
+#ifdef CONFIG_MACH_U1_KOR_LGT
+#define GPIO_ISP_RESET		EXYNOS4210_GPE0(4)
+#else
+#define GPIO_ISP_RESET		EXYNOS4_GPY3(7)
+#endif
+#ifdef CONFIG_MACH_U1_KOR_LGT
+#define GPIO_FUEL_SDA		EXYNOS4210_GPE1(7)
+#define GPIO_FUEL_SCL		EXYNOS4210_GPE2(0)
+#else
+#define GPIO_FUEL_SDA		EXYNOS4_GPY4(0)
+#define GPIO_FUEL_SCL		EXYNOS4_GPY4(1)
+#endif
+#define GPIO_FUEL_ALERT		EXYNOS4_GPX2(3)
+
+#define GPIO_USB_SDA		EXYNOS4210_GPE1(0)
+#define GPIO_USB_SCL		EXYNOS4210_GPE1(1)
+#define GPIO_MASSMEM_EN		EXYNOS4_GPL1(1)
+#define GPIO_MASSMEM_EN_LEVEL	0
+#define GPIO_TSP_INT		EXYNOS4_GPX0(4)
+
+#define GPIO_CAM_IO_EN		EXYNOS4210_GPE2(1)
+#define GPIO_CAM_SENSOR_CORE	EXYNOS4210_GPE2(5)
+#define GPIO_TSP_LDO_ON		EXYNOS4_GPL0(3)
+
+#define GPIO_USB_SEL		EXYNOS4_GPL0(6)
+#if !defined(CONFIG_MACH_U1_KOR_LGT)
+#define GPIO_UART_SEL		EXYNOS4_GPY4(7)
+#else
+#define GPIO_UART_SEL		EXYNOS4_GPL2(7)
+#endif
+
+#define GPIO_3_TOUCH_SCL	EXYNOS4_GPK1(0)
+#define GPIO_8M_AF_EN		EXYNOS4_GPK1(1)
+#define GPIO_3_TOUCH_SDA	EXYNOS4_GPK1(2)
+#define GPIO_3_TOUCH_INT	EXYNOS4_GPL0(5)
+
+#define GPIO_VT_CAM_15V	EXYNOS4210_GPE2(2)
+
+#define GPIO_CAM_MCLK		EXYNOS4210_GPJ1(3)
+
+#define GPIO_CAM_VGA_nSTBY	EXYNOS4_GPL2(0)
+#define GPIO_CAM_VGA_nRST	EXYNOS4_GPL2(1)
+
+#define GPIO_DET_35		EXYNOS4_GPX3(2)
+#define GPIO_DET_35_AF		0xF
+
+#define GPIO_EAR_SEND_END	EXYNOS4_GPX3(6)
+#define GPIO_EAR_SEND_END_AF	0xF
+
+#ifdef CONFIG_MACH_U1_KOR_LGT
+#define GPIO_GPS_PWR_EN		DUMMY_GPIO
+#define GPIO_GPS_nRST		DUMMY_GPIO
+#elif defined(CONFIG_TARGET_LOCALE_NTT)
+#define GPIO_GPS_PWR_EN		EXYNOS4210_GPE2(3)
+#define GPIO_GPS_PWR_EN_SPI	EXYNOS4210_GPE0(3)
+#define GPIO_GPS_nRST		EXYNOS4210_GPE0(4)
+#else
+#define GPIO_GPS_PWR_EN		EXYNOS4210_GPE0(3)
+#define GPIO_GPS_nRST		EXYNOS4210_GPE0(4)
+#endif
+
+#define GPIO_BT_RXD		EXYNOS4_GPA0(0)
+#define GPIO_BT_RXD_AF		2
+
+#define GPIO_BT_TXD		EXYNOS4_GPA0(1)
+#define GPIO_BT_TXD_AF		2
+
+#define GPIO_BT_CTS		EXYNOS4_GPA0(2)
+#define GPIO_BT_CTS_AF		2
+
+#define GPIO_BT_RTS		EXYNOS4_GPA0(3)
+#define GPIO_BT_RTS_AF		2
+
+#if !defined(CONFIG_MACH_U1_KOR_LGT)
+#define GPIO_GPS_RXD		EXYNOS4_GPA0(4)
+#define GPIO_GPS_RXD_AF		2
+
+#define GPIO_GPS_TXD		EXYNOS4_GPA0(5)
+#define GPIO_GPS_TXD_AF		2
+
+#define GPIO_GPS_CTS		EXYNOS4_GPA0(6)
+#define GPIO_GPS_CTS_AF		2
+
+#define GPIO_GPS_RTS		EXYNOS4_GPA0(7)
+#define GPIO_GPS_RTS_AF		2
+#else
+#define GPIO_GPS_RXD		DUMMY_GPIO
+#define GPIO_GPS_RXD_AF		2
+
+#define GPIO_GPS_TXD		DUMMY_GPIO
+#define GPIO_GPS_TXD_AF		2
+
+#define GPIO_GPS_CTS		DUMMY_GPIO
+#define GPIO_GPS_CTS_AF		2
+
+#define GPIO_GPS_RTS		DUMMY_GPIO
+#define GPIO_GPS_RTS_AF		2
+#endif
+
+#if defined(CONFIG_MACH_U1_KOR_LGT)
+#define GPIO_BOOT_SW_SEL	EXYNOS4_GPA0(6)
+#define GPIO_USB_BOOT_EN	EXYNOS4_GPA0(7)
+#endif
+
+#if !defined(CONFIG_MACH_U1_KOR_LGT)
+#define GPIO_NFC_SCL		EXYNOS4_GPY0(0)
+#else
+#define GPIO_NFC_SCL		DUMMY_GPIO
+#endif
+#define GPIO_NFC_SDA		EXYNOS4_GPY0(1)
+#define GPIO_NFC_EN		EXYNOS4_GPL2(6)
+#define GPIO_NFC_FIRM		EXYNOS4_GPL2(7)
+#if !defined(CONFIG_MACH_U1_KOR_LGT)
+#define GPIO_NFC_IRQ		EXYNOS4_GPX1(7)
+#else
+#define GPIO_NFC_IRQ		DUMMY_GPIO
+#endif
+
+#define GPIO_2MIC_PWDN		EXYNOS4_GPL2(3)
+#define GPIO_2MIC_RST		EXYNOS4_GPL2(4)
+#define GPIO_2MIC_EN		EXYNOS4_GPL2(5)
+
+#ifdef	CONFIG_CHARGER_MAX8922_U1	/* sub-charger */
+#define GPIO_CHG_EN		EXYNOS4_GPL2(2)
+#define GPIO_CHG_ING_N		EXYNOS4_GPL2(4)
+#define GPIO_TA_nCONNECTED	EXYNOS4_GPL2(5)
+#endif
+
+#define GPIO_2MIC_SDA		EXYNOS4_GPC1(2)
+#define GPIO_2MIC_SCL		EXYNOS4_GPC1(0)
+
+#define GPIO_FLM_RXD		EXYNOS4_GPA1(4)
+#define GPIO_FLM_RXD_AF		2
+
+#define GPIO_FLM_TXD		EXYNOS4_GPA1(5)
+#define GPIO_FLM_TXD_AF		2
+
+#if defined(CONFIG_MACH_U1_KOR_LGT)
+#define GPIO_DPRAM_INT_N	EXYNOS4_GPX1(0)
+#define GPIO_DPRAM_INT_N_AF	0xF
+#endif
+
+#define GPIO_PHONE_ON		EXYNOS4_GPC1(1)
+#define GPIO_PHONE_ACTIVE	EXYNOS4_GPX1(6)
+#if defined(CONFIG_MACH_U1_KOR_LGT)
+#define GPIO_PHONE_ACTIVE_AF	2
+#endif
+#if !defined(CONFIG_MACH_U1_KOR_LGT)
+#define GPIO_PDA_ACTIVE		EXYNOS4_GPY4(2)
+#define GPIO_CP_DUMP_INT	EXYNOS4_GPX1(2)
+#else
+#define GPIO_PDA_ACTIVE		EXYNOS4_GPX1(7)
+#define GPIO_CP_DUMP_INT	DUMMY_GPIO
+#endif
+#define GPIO_CP_RST		EXYNOS4_GPX1(4)
+#if defined(CONFIG_MACH_U1_KOR_LGT)
+#define GPIO_CP_RST_MSM	EXYNOS4_GPL2(6)
+#endif
+#define GPIO_CP_REQ_RESET	EXYNOS4_GPY4(6)
+#define GPIO_IPC_SLAVE_WAKEUP	EXYNOS4_GPX1(0)
+#ifndef CONFIG_MACH_U1_KOR_LGT
+#define GPIO_IPC_HOST_WAKEUP	EXYNOS4_GPX1(1)
+#else
+#define GPIO_IPC_HOST_WAKEUP		DUMMY_GPIO
+#endif
+#ifndef CONFIG_MACH_U1_KOR_LGT
+#define GPIO_SUSPEND_REQUEST	EXYNOS4_GPX1(3)
+#else
+#define GPIO_SUSPEND_REQUEST		DUMMY_GPIO
+#endif
+#define GPIO_ISP_INT		EXYNOS4_GPX1(5)
+#define GPIO_ACTIVE_STATE	EXYNOS4_GPY3(5)
+
+#define IRQ_PHONE_ACTIVE	IRQ_EINT14
+#define IRQ_SUSPEND_REQUEST	IRQ_EINT11
+#define IRQ_IPC_HOST_WAKEUP	IRQ_EINT9
+
+#define GPIO_WLAN_EN		EXYNOS4_GPL1(2)
+#define GPIO_WLAN_EN_AF		1
+
+#define GPIO_BT_EN		EXYNOS4_GPL0(4)
+#define GPIO_BT_nRST		EXYNOS4_GPL1(0)
+
+#define GPIO_WLAN_HOST_WAKE	EXYNOS4_GPX2(5)
+#define GPIO_WLAN_HOST_WAKE_AF	0xF
+
+#define GPIO_BT_HOST_WAKE	EXYNOS4_GPX2(6)
+#define GPIO_BT_HOST_WAKE_AF	0xF
+#define IRQ_BT_HOST_WAKE	IRQ_EINT(22)
+
+#define GPIO_BT_WAKE		EXYNOS4_GPX3(1)
+
+#define GPIO_WLAN_SDIO_CLK	EXYNOS4_GPK3(0)
+#define GPIO_WLAN_SDIO_CLK_AF	2
+
+#define GPIO_WLAN_SDIO_CMD	EXYNOS4_GPK3(1)
+#define GPIO_WLAN_SDIO_CMD_AF	2
+
+#define GPIO_WLAN_SDIO_D0	EXYNOS4_GPK3(3)
+#define GPIO_WLAN_SDIO_D0_AF	2
+
+#define GPIO_WLAN_SDIO_D1	EXYNOS4_GPK3(4)
+#define GPIO_WLAN_SDIO_D1_AF	2
+
+#define GPIO_WLAN_SDIO_D2	EXYNOS4_GPK3(5)
+#define GPIO_WLAN_SDIO_D2_AF	2
+
+#define GPIO_WLAN_SDIO_D3	EXYNOS4_GPK3(6)
+#define GPIO_WLAN_SDIO_D3_AF	2
+
+#define GPIO_HW_REV0		EXYNOS4210_GPE1(0)
+#define GPIO_HW_REV1		EXYNOS4210_GPE1(1)
+#define GPIO_HW_REV2		EXYNOS4210_GPE1(2)
+#define GPIO_HW_REV3		EXYNOS4210_GPE1(3)
+
+#define GPIO_MHL_RST		EXYNOS4_GPF3(4)
+#define GPIO_MHL_INT		EXYNOS4_GPF3(5)
+#define GPIO_MHL_INT_AF		S3C_GPIO_SFN(0xF)
+#define GPIO_MHL_WAKE_UP	EXYNOS4210_GPJ1(4)
+#define	GPIO_MHL_WAKE_UP_AF	S3C_GPIO_SFN(0xF)
+#define GPIO_MHL_SEL		EXYNOS4_GPL0(1)
+
+#define GPIO_BOOT_MODE		EXYNOS4_GPX0(3)
+
+#define GPIO_MSENSE_INT		EXYNOS4_GPX2(2)
+#define GPIO_HDMI_EN		EXYNOS4_GPX2(4)
+#define GPIO_HDMI_EN_REV07	EXYNOS4_GPL1(1)
+#define GPIO_HDMI_CEC		EXYNOS4_GPX3(6)
+#define GPIO_HDMI_HPD		EXYNOS4_GPX3(7)
+
+#define GPIO_ACC_INT		EXYNOS4_GPX3(0)
+#define GPIO_USB_OTG_EN		EXYNOS4_GPX3(3)
+
+#define GPIO_MSENSOR_MHL_SDA_28V	EXYNOS4_GPD0(2)
+#define	GPIO_MSENSOR_MHL_SDA_AF		0x3
+#define GPIO_MSENSOR_MHL_SCL_28V	EXYNOS4_GPD0(3)
+#define	GPIO_MSENSOR_MHL_SCL_AF		0x3
+#if !defined(CONFIG_MACH_U1_KOR_LGT)
+#define GPIO_MHL_SDA_18V		EXYNOS4_GPY3(0)
+#define GPIO_MHL_SCL_18V		EXYNOS4_GPY3(2)
+#else
+#define GPIO_MHL_SDA_18V		EXYNOS4210_GPE1(6)
+#define GPIO_MHL_SCL_18V		EXYNOS4210_GPE1(5)
+#endif
+
+#define GPIO_AP_HDMI_SDA	GPIO_MSENSOR_MHL_SDA_28V
+#define	GPIO_AP_HDMI_SDA_AF	GPIO_MSENSOR_MHL_SDA_AF
+#define GPIO_AP_HDMI_SCL	GPIO_MSENSOR_MHL_SCL_28V
+#define	GPIO_AP_HDMI_SCL_AF	GPIO_MSENSOR_MHL_SCL_AF
+#define GPIO_AP_SDA_18V		GPIO_MHL_SDA_18V
+#define GPIO_AP_SCL_18V		GPIO_MHL_SCL_18V
+
+#define MHL_INT_IRQ		gpio_to_irq(GPIO_MHL_INT)
+#define MHL_WAKEUP_IRQ		gpio_to_irq(GPIO_MHL_WAKE_UP)
+
+#define GPIO_MIC_BIAS_EN	EXYNOS4210_GPE1(4)
+#ifdef CONFIG_MACH_U1_KOR_LGT
+#define GPIO_SUB_MIC_BIAS_EN	EXYNOS4210_GPE0(2)
+#else
+#define GPIO_SUB_MIC_BIAS_EN	EXYNOS4210_GPE2(0)
+#endif
+#define GPIO_EAR_MIC_BIAS_EN	EXYNOS4210_GPE2(4)
+
+#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE)
+#define GPIO_TDMB_EN		EXYNOS4_GPC0(1)
+#define GPIO_TDMB_RST_N		EXYNOS4_GPB(5)
+#define GPIO_TDMB_INT		EXYNOS4_GPB(4)
+#define GPIO_TDMB_IRQ		gpio_to_irq(GPIO_TDMB_INT)
+#define GPIO_TDMB_INT_AF	0xf
+#define GPIO_TDMB_SPI_CLK	EXYNOS4_GPB(0)
+#define GPIO_TDMB_SPI_CS	EXYNOS4_GPB(1)
+#define GPIO_TDMB_SPI_MISO	EXYNOS4_GPB(2)
+#define GPIO_TDMB_SPI_MOSI	EXYNOS4_GPB(3)
+#endif
+#ifdef CONFIG_FM_SI4709_MODULE
+#define GPIO_FM_RST		EXYNOS4_GPB(0)
+#define GPIO_FM_INT		EXYNOS4_GPB(1)
+#define GPIO_FM_INT_REV07	EXYNOS4_GPX2(4)
+#define GPIO_FM_SDA_28V		EXYNOS4_GPB(2)
+#define GPIO_FM_SCL_28V		EXYNOS4_GPB(3)
+#endif
+
+#ifdef CONFIG_ISDBT_FC8100
+#define	GPIO_ISDBT_SCL_28V		EXYNOS4210_GPE1(6)
+#define	GPIO_ISDBT_SDA_28V		EXYNOS4210_GPE1(7)
+#define	GPIO_ISDBT_PWR_EN		EXYNOS4_GPC0(1)
+#define GPIO_ISDBT_RST			EXYNOS4210_GPE1(5)
+#endif
+
+#if defined(CONFIG_MACH_U1_KOR_LGT)
+/* Definitions for DPRAM */
+#define GPIO_DPRAM_CSN		EXYNOS4_GPY0(0)
+#define GPIO_DPRAM_CSN0		EXYNOS4_GPY0(0)
+#define GPIO_DPRAM_CSN1		EXYNOS4_GPY0(1)
+#define GPIO_DPRAM_CSN2		EXYNOS4_GPY0(2)
+#define GPIO_DPRAM_CSN3		EXYNOS4_GPY0(3)
+#define GPIO_DPRAM_REN		EXYNOS4_GPY0(4)
+#define GPIO_DPRAM_WEN		EXYNOS4_GPY0(5)
+#define GPIO_DPRAM_LBN		EXYNOS4_GPY1(0)
+#define GPIO_DPRAM_UBN		EXYNOS4_GPY1(1)
+#endif
+
+#endif
+#endif /* __MACH_GPIO_U1_H */
diff --git a/arch/arm/mach-exynos/include/mach/gpio-u1camera.h b/arch/arm/mach-exynos/include/mach/gpio-u1camera.h
new file mode 100644
index 0000000..5d7b8c5
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/gpio-u1camera.h
@@ -0,0 +1,296 @@
+#ifndef __MACH_GPIO_U1CAMERA_H
+#define __MACH_GPIO_U1CAMERA_H __FILE__
+
+#ifdef CONFIG_MACH_U1_KOR_LGT
+#define DUMMY_GPIO EXYNOS4_GPL2(2)
+#endif
+#if defined(CONFIG_MACH_U1CAMERA_BD)
+
+#define GPIO_XMMC0_CDn		EXYNOS4_GPK0(2)
+
+#define GPIO_PS_ALS_SDA		EXYNOS4_GPK2(2)
+#define GPIO_PS_ALS_SCL		EXYNOS4_GPK3(2)
+
+#define GPIO_GYRO_INT		0/*EXYNOS4_GPX0(0)*/
+#define GPIO_GYRO_FIFOP_INT	0/*EXYNOS4_GPX0(1)*/
+#define GPIO_PS_ALS_INT		EXYNOS4_GPX0(2)
+
+#define GPIO_BUCK1_EN_A		EXYNOS4_GPX0(5)
+#define GPIO_BUCK1_EN_B		EXYNOS4_GPX0(6)
+#define GPIO_BUCK2_EN		EXYNOS4_GPL0(0)
+#define GPIO_PMIC_IRQ		EXYNOS4_GPX0(7)
+
+#define GPIO_VOL_UP		EXYNOS4_GPX2(0)
+#define GPIO_VOL_DOWN		EXYNOS4_GPX2(1)
+#define GPIO_nPOWER		EXYNOS4_GPX2(7)
+
+#define GPIO_OK_KEY		EXYNOS4_GPX3(5)
+
+#define VT_CAM_SDA_18V		EXYNOS4_GPC1(0)
+#define VT_CAM_SCL_18V		EXYNOS4_GPC1(2)
+
+#define CODEC_VT_SDA_18V	EXYNOS4_GPC1(3)
+#define CODEC_VT_SCL_18V	EXYNOS4_GPC1(4)
+#ifdef CONFIG_MACH_U1_KOR_LGT
+#define GPIO_ISP_RESET		EXYNOS4210_GPE0(4)
+#else
+#define GPIO_ISP_RESET		EXYNOS4_GPY3(7)
+#endif
+#ifdef CONFIG_MACH_U1_KOR_LGT
+#define GPIO_FUEL_SDA		EXYNOS4210_GPE1(7)
+#define GPIO_FUEL_SCL		EXYNOS4210_GPE2(0)
+#else
+#define GPIO_FUEL_SDA		EXYNOS4_GPY4(0)
+#define GPIO_FUEL_SCL		EXYNOS4_GPY4(1)
+#endif
+#define GPIO_FUEL_ALERT		EXYNOS4_GPX2(3)
+
+#define GPIO_USB_SDA		EXYNOS4210_GPE1(0)
+#define GPIO_USB_SCL		EXYNOS4210_GPE1(1)
+#define GPIO_MASSMEM_EN		EXYNOS4_GPL1(1)
+#define GPIO_MASSMEM_EN_LEVEL	0
+#define GPIO_TSP_INT		EXYNOS4_GPX0(4)
+
+#define GPIO_CAM_IO_EN		EXYNOS4210_GPE2(1)
+#define GPIO_CAM_SENSOR_CORE	EXYNOS4210_GPE2(5)
+#define GPIO_TSP_LDO_ON		EXYNOS4_GPL0(3)
+
+#if !defined(CONFIG_MACH_U1_KOR_LGT)
+#define GPIO_UART_SEL		EXYNOS4_GPY4(7)
+#else
+#define GPIO_UART_SEL		EXYNOS4_GPL2(7)
+#endif
+
+#define GPIO_3_TOUCH_SCL	EXYNOS4_GPK1(0)
+#define GPIO_8M_AF_EN		EXYNOS4_GPK1(1)
+#define GPIO_3_TOUCH_SDA	EXYNOS4_GPK1(2)
+#define GPIO_3_TOUCH_INT	EXYNOS4_GPL0(5)
+
+#define GPIO_VT_CAM_15V	EXYNOS4210_GPE2(2)
+
+#define GPIO_CAM_MCLK		EXYNOS4210_GPJ1(3)
+
+#define GPIO_CAM_VGA_nSTBY	EXYNOS4_GPL2(0)
+#define GPIO_CAM_VGA_nRST	EXYNOS4_GPL2(1)
+
+#define GPIO_DET_35		EXYNOS4_GPX3(2)
+#define GPIO_DET_35_AF		0xF
+
+#define GPIO_EAR_SEND_END	EXYNOS4_GPX3(6)
+#define GPIO_EAR_SEND_END_AF	0xF
+
+#define GPIO_GPS_nRST		EXYNOS4_GPL0(6)
+#define GPIO_GPS_PWR_EN		EXYNOS4_GPL0(7)
+
+#define GPIO_GPS_RXD		EXYNOS4_GPA0(0)
+#define GPIO_GPS_RXD_AF		2
+
+#define GPIO_GPS_TXD		EXYNOS4_GPA0(1)
+#define GPIO_GPS_TXD_AF		2
+
+#define GPIO_GPS_CTS		EXYNOS4_GPA0(2)
+#define GPIO_GPS_CTS_AF		2
+
+#define GPIO_GPS_RTS		EXYNOS4_GPA0(3)
+#define GPIO_GPS_RTS_AF		2
+
+
+#if defined(CONFIG_MACH_U1_KOR_LGT)
+#define GPIO_BOOT_SW_SEL	EXYNOS4_GPA0(6)
+#define GPIO_USB_BOOT_EN	EXYNOS4_GPA0(7)
+#endif
+
+#if !defined(CONFIG_MACH_U1_KOR_LGT)
+#define GPIO_NFC_SCL		EXYNOS4_GPY0(0)
+#else
+#define GPIO_NFC_SCL		DUMMY_GPIO
+#endif
+#define GPIO_NFC_SDA		EXYNOS4_GPY0(1)
+#define GPIO_NFC_EN		EXYNOS4_GPL2(6)
+#define GPIO_NFC_FIRM		EXYNOS4_GPL2(7)
+
+#define GPIO_2MIC_PWDN		EXYNOS4_GPL2(3)
+#define GPIO_2MIC_RST		EXYNOS4_GPL2(4)
+#define GPIO_2MIC_EN		EXYNOS4_GPL2(5)
+
+#ifdef	CONFIG_CHARGER_MAX8922_U1	/* sub-charger */
+#define GPIO_CHG_EN		EXYNOS4_GPL2(2)
+#define GPIO_CHG_ING_N		EXYNOS4_GPL2(4)
+#define GPIO_TA_nCONNECTED	EXYNOS4_GPL2(5)
+#endif
+
+#define GPIO_2MIC_SDA		EXYNOS4_GPC1(2)
+#define GPIO_2MIC_SCL		EXYNOS4_GPC1(0)
+
+#define GPIO_FLM_RXD		EXYNOS4_GPA1(4)
+#define GPIO_FLM_RXD_AF		2
+
+#define GPIO_FLM_TXD		EXYNOS4_GPA1(5)
+#define GPIO_FLM_TXD_AF		2
+
+#define GPIO_PHONE_ON		EXYNOS4_GPC1(1)
+
+#if !defined(CONFIG_MACH_U1_KOR_LGT)
+#define GPIO_PDA_ACTIVE		EXYNOS4_GPY4(2)
+#else
+#define GPIO_CP_DUMP_INT	DUMMY_GPIO
+#endif
+#if defined(CONFIG_MACH_U1_KOR_LGT)
+#define GPIO_CP_RST_MSM	EXYNOS4_GPL2(6)
+#endif
+#define GPIO_CP_REQ_RESET	EXYNOS4_GPY4(6)
+
+#define GPIO_S1_KEY			EXYNOS4_GPX0(0)
+#define GPIO_S2_KEY			EXYNOS4_GPX0(1)
+
+#define GPIO_TELE_KEY		EXYNOS4_GPX2(6)
+#define GPIO_WIDE_KEY		EXYNOS4_GPX3(1)
+#define GPIO_RSERVED_KEY	EXYNOS4_GPX1(0)
+#define GPIO_PLAY_KEY		EXYNOS4_GPX1(1)
+#define GPIO_RECORD_KEY		EXYNOS4_GPX1(2)
+#define GPIO_MENU_KEY		EXYNOS4_GPX1(3)
+#define GPIO_ROTARY_PUSH	EXYNOS4_GPX1(4)
+#define GPIO_ISP_INT		EXYNOS4_GPX1(5)
+#define GPIO_HOME_KEY		EXYNOS4_GPX1(6)
+#define GPIO_BACK_KEY		EXYNOS4_GPX1(7)
+#define GPIO_NFC_IRQ		EXYNOS4_GPL2(6)
+#define GPIO_IPC_HOST_WAKEUP		EXYNOS4_GPL2(6)
+#define GPIO_IPC_SLAVE_WAKEUP		EXYNOS4_GPL2(6)
+#define GPIO_CP_RST		EXYNOS4_GPL2(6)
+#define GPIO_PHONE_ACTIVE		EXYNOS4_GPL2(6)
+#define GPIO_CP_DUMP_INT		EXYNOS4_GPL2(6)
+
+
+#define GPIO_ACTIVE_STATE	EXYNOS4_GPY3(5)
+
+#define IRQ_PHONE_ACTIVE	IRQ_EINT14
+#define IRQ_SUSPEND_REQUEST	IRQ_EINT11
+#define IRQ_IPC_HOST_WAKEUP	IRQ_EINT9
+
+#define GPIO_WLAN_EN		EXYNOS4_GPL1(2)
+#define GPIO_WLAN_EN_AF		1
+
+#define GPIO_BT_EN		EXYNOS4_GPL0(4)
+#define GPIO_BT_nRST		EXYNOS4_GPL1(0)
+
+#define GPIO_WLAN_HOST_WAKE	EXYNOS4_GPX2(5)
+#define GPIO_WLAN_HOST_WAKE_AF	0xF
+
+#define GPIO_BT_HOST_WAKE	0/*EXYNOS4_GPX2(6)*/
+#define GPIO_BT_HOST_WAKE_AF	0xF
+#define IRQ_BT_HOST_WAKE	IRQ_EINT(22)
+
+#define GPIO_BT_WAKE		0/*EXYNOS4_GPX3(1)*/
+
+#define GPIO_WLAN_SDIO_CLK	EXYNOS4_GPK3(0)
+#define GPIO_WLAN_SDIO_CLK_AF	2
+
+#define GPIO_WLAN_SDIO_CMD	EXYNOS4_GPK3(1)
+#define GPIO_WLAN_SDIO_CMD_AF	2
+
+#define GPIO_WLAN_SDIO_D0	EXYNOS4_GPK3(3)
+#define GPIO_WLAN_SDIO_D0_AF	2
+
+#define GPIO_WLAN_SDIO_D1	EXYNOS4_GPK3(4)
+#define GPIO_WLAN_SDIO_D1_AF	2
+
+#define GPIO_WLAN_SDIO_D2	EXYNOS4_GPK3(5)
+#define GPIO_WLAN_SDIO_D2_AF	2
+
+#define GPIO_WLAN_SDIO_D3	EXYNOS4_GPK3(6)
+#define GPIO_WLAN_SDIO_D3_AF	2
+
+#define GPIO_HW_REV0		EXYNOS4210_GPE1(0)
+#define GPIO_HW_REV1		EXYNOS4210_GPE1(1)
+#define GPIO_HW_REV2		EXYNOS4210_GPE1(2)
+#define GPIO_HW_REV3		EXYNOS4210_GPE1(3)
+
+#define GPIO_MHL_RST		EXYNOS4_GPF3(4)
+#define GPIO_MHL_INT		EXYNOS4_GPF3(5)
+#define GPIO_MHL_INT_AF		S3C_GPIO_SFN(0xF)
+#define GPIO_MHL_WAKE_UP	EXYNOS4210_GPJ1(4)
+#define	GPIO_MHL_WAKE_UP_AF	S3C_GPIO_SFN(0xF)
+#define GPIO_MHL_SEL		EXYNOS4_GPL0(1)
+
+#define GPIO_BOOT_MODE		EXYNOS4_GPX0(3)
+
+#define GPIO_MSENSE_INT		EXYNOS4_GPX2(2)
+#define GPIO_HDMI_EN		EXYNOS4_GPX2(4)
+#define GPIO_HDMI_EN_REV07	EXYNOS4_GPL1(1)
+#define GPIO_HDMI_CEC		EXYNOS4_GPX3(6)
+#define GPIO_HDMI_HPD		EXYNOS4_GPX3(7)
+
+#define GPIO_ACC_INT		EXYNOS4_GPX3(0)
+#define GPIO_USB_OTG_EN		EXYNOS4_GPX3(3)
+
+#define GPIO_MSENSOR_MHL_SDA_28V	EXYNOS4_GPD0(2)
+#define	GPIO_MSENSOR_MHL_SDA_AF		0x3
+#define GPIO_MSENSOR_MHL_SCL_28V	EXYNOS4_GPD0(3)
+#define	GPIO_MSENSOR_MHL_SCL_AF		0x3
+#if !defined(CONFIG_MACH_U1_KOR_LGT)
+#define GPIO_MHL_SDA_18V		EXYNOS4_GPY3(0)
+#define GPIO_MHL_SCL_18V		EXYNOS4_GPY3(2)
+#else
+#define GPIO_MHL_SDA_18V		EXYNOS4210_GPE1(6)
+#define GPIO_MHL_SCL_18V		EXYNOS4210_GPE1(5)
+#endif
+
+#define GPIO_AP_HDMI_SDA	GPIO_MSENSOR_MHL_SDA_28V
+#define	GPIO_AP_HDMI_SDA_AF	GPIO_MSENSOR_MHL_SDA_AF
+#define GPIO_AP_HDMI_SCL	GPIO_MSENSOR_MHL_SCL_28V
+#define	GPIO_AP_HDMI_SCL_AF	GPIO_MSENSOR_MHL_SCL_AF
+#define GPIO_AP_SDA_18V		GPIO_MHL_SDA_18V
+#define GPIO_AP_SCL_18V		GPIO_MHL_SCL_18V
+
+#define MHL_INT_IRQ		gpio_to_irq(GPIO_MHL_INT)
+#define MHL_WAKEUP_IRQ		gpio_to_irq(GPIO_MHL_WAKE_UP)
+
+#define GPIO_MIC_BIAS_EN	EXYNOS4210_GPE1(4)
+#ifdef CONFIG_MACH_U1_KOR_LGT
+#define GPIO_SUB_MIC_BIAS_EN	EXYNOS4210_GPE0(2)
+#else
+#define GPIO_SUB_MIC_BIAS_EN	EXYNOS4210_GPE2(0)
+#endif
+#define GPIO_EAR_MIC_BIAS_EN	EXYNOS4210_GPE2(4)
+
+#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE)
+#define GPIO_TDMB_EN		EXYNOS4_GPC0(1)
+#define GPIO_TDMB_RST_N		EXYNOS4_GPB(5)
+#define GPIO_TDMB_INT		EXYNOS4_GPB(4)
+#define GPIO_TDMB_IRQ		gpio_to_irq(GPIO_TDMB_INT)
+#define GPIO_TDMB_INT_AF	0xf
+#define GPIO_TDMB_SPI_CLK	EXYNOS4_GPB(0)
+#define GPIO_TDMB_SPI_CS	EXYNOS4_GPB(1)
+#define GPIO_TDMB_SPI_MISO	EXYNOS4_GPB(2)
+#define GPIO_TDMB_SPI_MOSI	EXYNOS4_GPB(3)
+#endif
+#ifdef CONFIG_FM_SI4709_MODULE
+#define GPIO_FM_RST		EXYNOS4_GPB(0)
+#define GPIO_FM_INT		EXYNOS4_GPB(1)
+#define GPIO_FM_INT_REV07	EXYNOS4_GPX2(4)
+#define GPIO_FM_SDA_28V		EXYNOS4_GPB(2)
+#define GPIO_FM_SCL_28V		EXYNOS4_GPB(3)
+#endif
+
+#ifdef CONFIG_ISDBT_FC8100
+#define	GPIO_ISDBT_SCL_28V		EXYNOS4210_GPE1(6)
+#define	GPIO_ISDBT_SDA_28V		EXYNOS4210_GPE1(7)
+#define	GPIO_ISDBT_PWR_EN		EXYNOS4_GPC0(1)
+#define GPIO_ISDBT_RST			EXYNOS4210_GPE1(5)
+#endif
+
+#if defined(CONFIG_MACH_U1_KOR_LGT)
+/* Definitions for DPRAM */
+#define GPIO_DPRAM_CSN		EXYNOS4_GPY0(0)
+#define GPIO_DPRAM_CSN0		EXYNOS4_GPY0(0)
+#define GPIO_DPRAM_CSN1		EXYNOS4_GPY0(1)
+#define GPIO_DPRAM_CSN2		EXYNOS4_GPY0(2)
+#define GPIO_DPRAM_CSN3		EXYNOS4_GPY0(3)
+#define GPIO_DPRAM_REN		EXYNOS4_GPY0(4)
+#define GPIO_DPRAM_WEN		EXYNOS4_GPY0(5)
+#define GPIO_DPRAM_LBN		EXYNOS4_GPY1(0)
+#define GPIO_DPRAM_UBN		EXYNOS4_GPY1(1)
+#endif
+
+#endif
+#endif /* __MACH_GPIO_U1CAMERA_H */
diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h
new file mode 100644
index 0000000..63d66f1
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/gpio.h
@@ -0,0 +1,43 @@
+/* linux/arch/arm/mach-exynos/include/mach/gpio.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * EXYNOS - gpio map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_GPIO_H
+#define __ASM_ARCH_GPIO_H __FILE__
+
+#include "gpio-exynos4.h"
+#include "gpio-exynos5.h"
+
+extern void (*exynos4_sleep_gpio_table_set)(void);
+extern void (*exynos5_sleep_gpio_table_set)(void);
+
+#if defined(CONFIG_ARCH_EXYNOS4)
+#define S3C_GPIO_END		EXYNOS4_GPIO_END
+#define ARCH_NR_GPIOS		(EXYNOS4XXX_GPIO_END +	\
+				CONFIG_SAMSUNG_GPIO_EXTRA)
+#elif defined(CONFIG_ARCH_EXYNOS5)
+#define S3C_GPIO_END		EXYNOS5_GPIO_END
+#define ARCH_NR_GPIOS		(EXYNOS5_GPIO_END +	\
+				CONFIG_SAMSUNG_GPIO_EXTRA)
+#else
+#error "ARCH_EXYNOS* is not defined"
+#endif
+
+#define GPIO_LEVEL_LOW		0
+#define GPIO_LEVEL_HIGH		1
+#define GPIO_LEVEL_NONE		2
+
+#define GPIO_INPUT		0
+#define GPIO_OUTPUT		1
+
+#include <asm-generic/gpio.h>
+
+#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-exynos/include/mach/gpufreq.h b/arch/arm/mach-exynos/include/mach/gpufreq.h
new file mode 100644
index 0000000..3ecb393
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/gpufreq.h
@@ -0,0 +1,38 @@
+/*
+ *  linux/arch/arm/mach-exynos/include/mach/gpufreq.h
+ *
+  *
+  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+  *	http://www.samsung.com
+  *
+  *
+  * This program is free software; you can redistribute it and/or modify
+  * it under the terms of the GNU General Public License version 2 as
+  * published by the Free Software Foundation.
+ */
+
+#ifdef CONFIG_CPU_EXYNOS4210
+extern int mali_dvfs_bottom_lock_push(void);
+extern int mali_dvfs_bottom_lock_pop(void);
+
+static inline int exynos_gpufreq_lock(void)
+{
+	return mali_dvfs_bottom_lock_push();
+}
+
+static inline int exynos_gpufreq_unlock(void)
+{
+	return mali_dvfs_bottom_lock_pop();
+}
+
+#else
+static inline int exynos_gpufreq_lock(void)
+{
+	return 0;
+}
+static inline int exynos_gpufreq_unlock(void)
+{
+	return 0;
+}
+#endif
+
diff --git a/arch/arm/mach-exynos/include/mach/hardware.h b/arch/arm/mach-exynos/include/mach/hardware.h
new file mode 100644
index 0000000..4470917
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/hardware.h
@@ -0,0 +1,18 @@
+/* linux/arch/arm/mach-exynos/include/mach/hardware.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS4 - Hardware support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H __FILE__
+
+/* currently nothing here, placeholder */
+
+#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-exynos/include/mach/iic-hdmiphy.h b/arch/arm/mach-exynos/include/mach/iic-hdmiphy.h
new file mode 100644
index 0000000..4f070e0
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/iic-hdmiphy.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics Co., Ltd.
+ *
+ * S5P series i2c hdmiphy helper definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef PLAT_S5P_IIC_HDMIPHY_H_
+#define PLAT_S5P_IIC_HDMIPHY_H_
+
+#define S5P_IIC_HDMIPHY_BUS_NUM		(8)
+
+#endif
diff --git a/arch/arm/mach-exynos/include/mach/io.h b/arch/arm/mach-exynos/include/mach/io.h
new file mode 100644
index 0000000..0d0544f
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/io.h
@@ -0,0 +1,26 @@
+/* linux/arch/arm/mach-exynos/include/mach/io.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Copyright 2008-2010 Ben Dooks <ben-linux@fluff.org>
+ *
+ * Based on arch/arm/mach-s5p6442/include/mach/io.h
+ *
+ * Default IO routines for EXYNOS4
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H __FILE__
+
+/* No current ISA/PCI bus support. */
+#define __io(a)		__typesafe_io(a)
+#define __mem_pci(a)	(a)
+
+#define IO_SPACE_LIMIT (0xFFFFFFFF)
+
+#endif /* __ASM_ARM_ARCH_IO_H */
diff --git a/arch/arm/mach-exynos/include/mach/irqs-exynos4.h b/arch/arm/mach-exynos/include/mach/irqs-exynos4.h
new file mode 100644
index 0000000..6a9d79d
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/irqs-exynos4.h
@@ -0,0 +1,248 @@
+/* linux/arch/arm/mach-exynos/include/mach/irqs-exynos4.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS4 - IRQ definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_IRQS_EXYNOS4_H
+#define __ASM_ARCH_IRQS_EXYNOS4_H __FILE__
+
+#define IRQ_EINT0		IRQ_SPI(16)
+#define IRQ_EINT1		IRQ_SPI(17)
+#define IRQ_EINT2		IRQ_SPI(18)
+#define IRQ_EINT3		IRQ_SPI(19)
+#define IRQ_EINT4		IRQ_SPI(20)
+#define IRQ_EINT5		IRQ_SPI(21)
+#define IRQ_EINT6		IRQ_SPI(22)
+#define IRQ_EINT7		IRQ_SPI(23)
+#define IRQ_EINT8		IRQ_SPI(24)
+#define IRQ_EINT9		IRQ_SPI(25)
+#define IRQ_EINT10		IRQ_SPI(26)
+#define IRQ_EINT11		IRQ_SPI(27)
+#define IRQ_EINT12		IRQ_SPI(28)
+#define IRQ_EINT13		IRQ_SPI(29)
+#define IRQ_EINT14		IRQ_SPI(30)
+#define IRQ_EINT15		IRQ_SPI(31)
+#define IRQ_EINT16_31		IRQ_SPI(32)
+#define IRQ_MDMA0		IRQ_SPI(33)
+#define IRQ_C2C_SSCM0		IRQ_SPI(33)
+#define IRQ_MDMA1		IRQ_SPI(34)
+#define IRQ_PDMA0		IRQ_SPI(35)
+#define IRQ_PDMA1		IRQ_SPI(36)
+#define IRQ_TIMER0_VIC		IRQ_SPI(37)
+#define IRQ_TIMER1_VIC		IRQ_SPI(38)
+#define IRQ_TIMER2_VIC		IRQ_SPI(39)
+#define IRQ_TIMER3_VIC		IRQ_SPI(40)
+#define IRQ_TIMER4_VIC		IRQ_SPI(41)
+#define IRQ_MCT_L0		IRQ_SPI(42)
+#define IRQ_WDT			IRQ_SPI(43)
+#define IRQ_RTC_ALARM		IRQ_SPI(44)
+#define IRQ_RTC_TIC		IRQ_SPI(45)
+
+#define IRQ_GPIO_XB		IRQ_SPI(46)
+#define IRQ_GPIO_XA		IRQ_SPI(47)
+
+#define IRQ_MCT_L1		IRQ_SPI(48)
+
+#define IRQ_UART0		IRQ_SPI(52)
+#define IRQ_UART1		IRQ_SPI(53)
+#define IRQ_UART2		IRQ_SPI(54)
+#define IRQ_UART3		IRQ_SPI(55)
+#define IRQ_UART4		IRQ_SPI(56)
+#define IRQ_MCT_G0		IRQ_SPI(57)
+#define IRQ_IIC			IRQ_SPI(58)
+#define IRQ_IIC1		IRQ_SPI(59)
+#define IRQ_IIC2		IRQ_SPI(60)
+#define IRQ_IIC3		IRQ_SPI(61)
+#define IRQ_IIC4		IRQ_SPI(62)
+#define IRQ_IIC5		IRQ_SPI(63)
+#define IRQ_IIC6		IRQ_SPI(64)
+#define IRQ_IIC7		IRQ_SPI(65)
+#define IRQ_SPI0		IRQ_SPI(66)
+#define IRQ_SPI1		IRQ_SPI(67)
+#define IRQ_SPI2		IRQ_SPI(68)
+
+#define IRQ_USB_HOST		IRQ_SPI(70)
+#define IRQ_USB_HSOTG		IRQ_SPI(71)
+#define IRQ_MODEM_IF		IRQ_SPI(72)
+#define IRQ_GPIO_C2C		IRQ_SPI(72)
+#define IRQ_HSMMC0		IRQ_SPI(73)
+#define IRQ_HSMMC1		IRQ_SPI(74)
+#define IRQ_HSMMC2		IRQ_SPI(75)
+#define IRQ_HSMMC3		IRQ_SPI(76)
+#define IRQ_DWMCI		IRQ_SPI(77)
+
+#define IRQ_MIPICSI0		IRQ_SPI(78)
+#define IRQ_MIPIDSI0		IRQ_SPI(79)
+#define IRQ_MIPICSI1		IRQ_SPI(80)
+#define IRQ_MIPIDSI1		IRQ_SPI(81)
+
+#define IRQ_ONENAND_AUDI	IRQ_SPI(82)
+#define IRQ_ROTATOR		IRQ_SPI(83)
+#define IRQ_FIMC0		IRQ_SPI(84)
+#define IRQ_FIMC1		IRQ_SPI(85)
+#define IRQ_FIMC2		IRQ_SPI(86)
+#define IRQ_FIMC3		IRQ_SPI(87)
+#define IRQ_JPEG		IRQ_SPI(88)
+#define IRQ_2D			IRQ_SPI(89)
+#define IRQ_PCIE		IRQ_SPI(90)
+#define IRQ_FIMC_IS0		IRQ_SPI(90)
+#define IRQ_MIXER		IRQ_SPI(91)
+#define IRQ_HDMI		IRQ_SPI(92)
+#define IRQ_HDMI_I2C		IRQ_SPI(93)
+#define IRQ_IIC_HDMIPHY		IRQ_SPI(93)
+#define IRQ_MFC			IRQ_SPI(94)
+#define IRQ_TVENC		IRQ_SPI(95)
+#define IRQ_SDO			IRQ_SPI(95)
+#define IRQ_FIMC_IS1		IRQ_SPI(95)
+#define IRQ_AUDIO_SS		IRQ_SPI(96)
+#define IRQ_I2S0		IRQ_SPI(97)
+#define IRQ_I2S1		IRQ_SPI(98)
+#define IRQ_I2S2		IRQ_SPI(99)
+#define IRQ_AC97		IRQ_SPI(100)
+
+#define IRQ_SPDIF		IRQ_SPI(104)
+#define IRQ_ADC0		IRQ_SPI(105)
+#define IRQ_PEN0		IRQ_SPI(106)
+#define IRQ_FIMC_LITE0		IRQ_SPI(105)
+#define IRQ_FIMC_LITE1		IRQ_SPI(106)
+#define IRQ_ADC1		IRQ_SPI(107)
+#define IRQ_PEN1		IRQ_SPI(108)
+#define IRQ_KEYPAD		IRQ_SPI(109)
+#define IRQ_POWER_PMU		IRQ_SPI(110)
+#define IRQ_GPS			IRQ_SPI(111)
+#define IRQ_INTFEEDCTRL_SSS	IRQ_SPI(112)
+#define IRQ_SLIMBUS		IRQ_SPI(113)
+#define IRQ_CEC		IRQ_SPI(114)
+#define IRQ_TSI			IRQ_SPI(115)
+#define IRQ_SATA		IRQ_SPI(116)
+#define IRQ_C2C_SSCM1		IRQ_SPI(116)
+
+#define IRQ_PPMMU0_3D		IRQ_SPI(118)
+#define IRQ_PPMMU1_3D		IRQ_SPI(119)
+#define IRQ_PPMMU2_3D		IRQ_SPI(120)
+#define IRQ_PPMMU3_3D		IRQ_SPI(121)
+#define IRQ_GPMMU_3D		IRQ_SPI(122)
+
+#define IRQ_PP0_3D		IRQ_SPI(123)
+#define IRQ_PP1_3D		IRQ_SPI(124)
+#define IRQ_PP2_3D		IRQ_SPI(125)
+#define IRQ_PP3_3D		IRQ_SPI(126)
+#define IRQ_GP_3D		IRQ_SPI(127)
+#define IRQ_PMU_3D		IRQ_SPI(117)
+
+#define MAX_IRQ_IN_COMBINER	8
+#define COMBINER_GROUP(x)	((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128))
+#define COMBINER_IRQ(x, y)	(COMBINER_GROUP(x) + y)
+
+#define IRQ_LCD_LITE0		COMBINER_IRQ(0, 0)
+#define IRQ_LCD_LITE1		COMBINER_IRQ(0, 1)
+
+#define IRQ_PMU_CPU0		COMBINER_IRQ(2, 2)
+#define IRQ_PMU			IRQ_PMU_CPU0
+#define IRQ_TMU			COMBINER_IRQ(2, 4)
+
+#define IRQ_PMU_CPU1		COMBINER_IRQ(3, 2)
+
+#define IRQ_SYSMMU_MDMA0_0	COMBINER_IRQ(4, 0)
+#define IRQ_SYSMMU_SSS_0	COMBINER_IRQ(4, 1)
+#define IRQ_SYSMMU_FIMC0_0	COMBINER_IRQ(4, 2)
+#define IRQ_SYSMMU_FIMC1_0	COMBINER_IRQ(4, 3)
+#define IRQ_SYSMMU_FIMC2_0	COMBINER_IRQ(4, 4)
+#define IRQ_SYSMMU_FIMC3_0	COMBINER_IRQ(4, 5)
+#define IRQ_SYSMMU_JPEG_0	COMBINER_IRQ(4, 6)
+#define IRQ_SYSMMU_2D_0		COMBINER_IRQ(4, 7)
+
+#define IRQ_SYSMMU_ROTATOR_0	COMBINER_IRQ(5, 0)
+#define IRQ_SYSMMU_MDMA1_0	COMBINER_IRQ(5, 1)
+#define IRQ_SYSMMU_FIMD0_0	COMBINER_IRQ(5, 2)
+#define IRQ_SYSMMU_FIMD1_0	COMBINER_IRQ(5, 3)
+#define IRQ_SYSMMU_TV_0		COMBINER_IRQ(5, 4)
+#define IRQ_SYSMMU_MFC_R_0	COMBINER_IRQ(5, 5)
+#define IRQ_SYSMMU_MFC_L_0	COMBINER_IRQ(5, 6)
+#define IRQ_SYSMMU_PCIE_0	COMBINER_IRQ(5, 7)
+
+#define IRQ_EXYNOS4412_ADC	COMBINER_IRQ(10, 3)
+
+#define IRQ_FIMD0_FIFO		COMBINER_IRQ(11, 0)
+#define IRQ_FIMD0_VSYNC		COMBINER_IRQ(11, 1)
+#define IRQ_FIMD0_SYSTEM	COMBINER_IRQ(11, 2)
+
+#define IRQ_FIMD1_FIFO		COMBINER_IRQ(12, 0)
+#define IRQ_FIMD1_VSYNC		COMBINER_IRQ(12, 1)
+#define IRQ_FIMD1_SYSTEM	COMBINER_IRQ(12, 2)
+
+#define IRQ_SYSMMU_LITE0_0	COMBINER_IRQ(16, 0)
+#define IRQ_SYSMMU_LITE1_0	COMBINER_IRQ(16, 1)
+#define IRQ_SYSMMU_ISP_0	COMBINER_IRQ(16, 2)
+#define IRQ_SYSMMU_DRC_0	COMBINER_IRQ(16, 3)
+#define IRQ_SYSMMU_FD_0		COMBINER_IRQ(16, 4)
+#define IRQ_SYSMMU_MCUISP_0	COMBINER_IRQ(16, 5)
+
+#define IRQ_PMU_CPU2		COMBINER_IRQ(18, 2)
+#define IRQ_PMU_CPU3		COMBINER_IRQ(19, 2)
+
+#define COMMON_COMBINER_NR	16
+#define MAX_COMBINER_NR		20
+
+#define S5P_IRQ_EINT_BASE	COMBINER_IRQ(MAX_COMBINER_NR, 0)
+
+#define S5P_EINT_BASE1		(S5P_IRQ_EINT_BASE + 0)
+#define S5P_EINT_BASE2		(S5P_IRQ_EINT_BASE + 16)
+
+#define IRQ_TVOUT_HPD		(S5P_IRQ_EINT_BASE + 31)
+
+#if defined(CONFIG_CPU_EXYNOS4210)
+#if defined(CONFIG_S3C_DEV_ADC)
+#define IRQ_ADC		IRQ_ADC0
+#define IRQ_TC		IRQ_PEN0
+#else
+#define IRQ_ADC		IRQ_ADC1
+#define IRQ_TC		IRQ_PEN1
+#endif
+#elif defined(CONFIG_CPU_EXYNOS4412)
+#define IRQ_ADC		IRQ_EXYNOS4412_ADC
+#define IRQ_TC		IRQ_PEN0
+#endif
+
+/* optional GPIO interrupts */
+#define S5P_GPIOINT_BASE	(S5P_IRQ_EINT_BASE + 32)
+#define IRQ_GPIO1_NR_GROUPS	16
+#define IRQ_GPIO2_NR_GROUPS	12
+#define IRQ_GPIO_END		(S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
+
+#define IRQ_BOARD_START		IRQ_GPIO_END
+
+#if defined(CONFIG_MFD_MAX77693) || defined(CONFIG_MFD_MAX77686) ||\
+	defined(CONFIG_MFD_S5M_CORE)
+#define IRQ_BOARD_IFIC_START	(IRQ_BOARD_START)
+#define IRQ_BOARD_IFIC_NR	29
+#define IRQ_BOARD_PMIC_START	(IRQ_BOARD_START + IRQ_BOARD_IFIC_NR)
+#define IRQ_BOARD_PMIC_NR	16
+#define IRQ_BOARD_CODEC_START	(IRQ_BOARD_PMIC_START + IRQ_BOARD_PMIC_NR)
+#define IRQ_BOARD_CODEC_NR	32
+#define IRQ_NR_BOARD		(IRQ_BOARD_PMIC_NR + IRQ_BOARD_IFIC_NR \
+				 + IRQ_BOARD_CODEC_NR)
+#elif defined(CONFIG_MFD_MAX8997)
+#define IRQ_BOARD_PMIC_START	(IRQ_BOARD_START)
+#define IRQ_BOARD_PMIC_NR	35
+#define IRQ_BOARD_FUEL_START	(IRQ_BOARD_PMIC_START + IRQ_BOARD_PMIC_NR)
+#define IRQ_BOARD_FUEL_NR	10
+#define IRQ_BOARD_CODEC_START	(IRQ_BOARD_FUEL_START + IRQ_BOARD_FUEL_NR)
+#define IRQ_BOARD_CODEC_NR	32
+#define IRQ_NR_BOARD		(IRQ_BOARD_PMIC_NR + IRQ_BOARD_FUEL_NR \
+				 + IRQ_BOARD_CODEC_NR)
+#else
+#define IRQ_NR_BOARD		40
+#endif
+
+/* Set the default NR_IRQS */
+#define NR_IRQS			(IRQ_GPIO_END + IRQ_NR_BOARD)
+
+#endif /* __ASM_ARCH_IRQS_EXYNOS4_H */
diff --git a/arch/arm/mach-exynos/include/mach/irqs-exynos5.h b/arch/arm/mach-exynos/include/mach/irqs-exynos5.h
new file mode 100644
index 0000000..9885a55
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/irqs-exynos5.h
@@ -0,0 +1,274 @@
+/* linux/arch/arm/mach-exynos/include/mach/irqs-exynos5.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS5 - IRQ definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_IRQS_EXYNOS5_H
+#define __ASM_ARCH_IRQS_EXYNOS5_H __FILE__
+
+#define IRQ_EINT16_31		IRQ_SPI(32)
+#define IRQ_MDMA0		IRQ_SPI(33)
+#define IRQ_PDMA0		IRQ_SPI(34)
+#define IRQ_PDMA1		IRQ_SPI(35)
+#define IRQ_TIMER0_VIC		IRQ_SPI(36)
+#define IRQ_TIMER1_VIC		IRQ_SPI(37)
+#define IRQ_TIMER2_VIC		IRQ_SPI(38)
+#define IRQ_TIMER3_VIC		IRQ_SPI(39)
+#define IRQ_TIMER4_VIC		IRQ_SPI(40)
+#define IRQ_RTIC		IRQ_SPI(41)
+#define IRQ_WDT			IRQ_SPI(42)
+#define IRQ_RTC_ALARM		IRQ_SPI(43)
+#define IRQ_RTC_TIC		IRQ_SPI(44)
+#define IRQ_GPIO_XB		IRQ_SPI(45)
+#define IRQ_GPIO_XA		IRQ_SPI(46)
+#define IRQ_GPIO		IRQ_SPI(47)
+#define IRQ_IEM_IEC		IRQ_SPI(48)
+#define IRQ_IEM_APC		IRQ_SPI(49)
+#define IRQ_GPIO_C2C		IRQ_SPI(50)
+#define IRQ_UART0		IRQ_SPI(51)
+#define IRQ_UART1		IRQ_SPI(52)
+#define IRQ_UART2		IRQ_SPI(53)
+#define IRQ_UART3		IRQ_SPI(54)
+#define IRQ_MONOCNT		IRQ_SPI(55)
+#define IRQ_IIC			IRQ_SPI(56)
+#define IRQ_IIC1		IRQ_SPI(57)
+#define IRQ_IIC2		IRQ_SPI(58)
+#define IRQ_IIC3		IRQ_SPI(59)
+#define IRQ_IIC4		IRQ_SPI(60)
+#define IRQ_IIC5		IRQ_SPI(61)
+#define IRQ_IIC6		IRQ_SPI(62)
+#define IRQ_IIC7		IRQ_SPI(63)
+#define IRQ_IIC_HDMIPHY		IRQ_SPI(64)
+#define IRQ_TMU			IRQ_SPI(65)
+#define IRQ_FIQ_0		IRQ_SPI(66)
+#define IRQ_FIQ_1		IRQ_SPI(67)
+#define IRQ_SPI0		IRQ_SPI(68)
+#define IRQ_SPI1		IRQ_SPI(69)
+#define IRQ_SPI2		IRQ_SPI(70)
+#define IRQ_USB_HOST		IRQ_SPI(71)
+#define IRQ_USB3_DRD		IRQ_SPI(72)
+#define IRQ_MIPI_HSI		IRQ_SPI(73)
+#define IRQ_USB_HSOTG		IRQ_SPI(74)
+#define IRQ_HSMMC0		IRQ_SPI(75)
+#define IRQ_HSMMC1		IRQ_SPI(76)
+#define IRQ_HSMMC2		IRQ_SPI(77)
+#define IRQ_HSMMC3		IRQ_SPI(78)
+#define IRQ_MIPICSI0		IRQ_SPI(79)
+#define IRQ_MIPICSI1		IRQ_SPI(80)
+#define IRQ_EFNFCON_DMA_ABORT	IRQ_SPI(81)
+#define IRQ_MIPIDSI0		IRQ_SPI(82)
+#define IRQ_WDT_IOP		IRQ_SPI(83)
+#define IRQ_ROTATOR		IRQ_SPI(84)
+#define IRQ_GSC0		IRQ_SPI(85)
+#define IRQ_GSC1		IRQ_SPI(86)
+#define IRQ_GSC2		IRQ_SPI(87)
+#define IRQ_GSC3		IRQ_SPI(88)
+#define IRQ_JPEG		IRQ_SPI(89)
+#define IRQ_EFNFCON_DMA		IRQ_SPI(90)
+#define IRQ_2D			IRQ_SPI(91)
+#define IRQ_EFNFCON_0		IRQ_SPI(92)
+#define IRQ_EFNFCON_1		IRQ_SPI(93)
+#define IRQ_MIXER		IRQ_SPI(94)
+#define IRQ_HDMI		IRQ_SPI(95)
+#define IRQ_MFC			IRQ_SPI(96)
+#define IRQ_AUDIO_SS		IRQ_SPI(97)
+#define IRQ_I2S0		IRQ_SPI(98)
+#define IRQ_I2S1		IRQ_SPI(99)
+#define IRQ_I2S2		IRQ_SPI(100)
+#define IRQ_AC97		IRQ_SPI(101)
+#define IRQ_PCM0		IRQ_SPI(102)
+#define IRQ_PCM1		IRQ_SPI(103)
+#define IRQ_PCM2		IRQ_SPI(104)
+#define IRQ_SPDIF		IRQ_SPI(105)
+#define IRQ_ADC0		IRQ_SPI(106)
+#define IRQ_ADC1		IRQ_SPI(107)
+#define IRQ_SATA_PHY		IRQ_SPI(108)
+#define IRQ_SATA_PMEREQ		IRQ_SPI(109)
+#define IRQ_FIMC_LITE2		IRQ_SPI(110)
+#define IRQ_EAGLE_PMU		IRQ_SPI(111)
+#define IRQ_INTFEEDCTRL_SSS	IRQ_SPI(112)
+#define IRQ_DP1_INTP1		IRQ_SPI(113)
+#define IRQ_CEC			IRQ_SPI(114)
+#define IRQ_SATA		IRQ_SPI(115)
+
+#define GPU_IRQ_NUMBER		IRQ_SPI(117)
+#define JOB_IRQ_NUMBER		IRQ_SPI(118)
+#define MMU_IRQ_NUMBER		IRQ_SPI(119)
+#define IRQ_MCT_L0		IRQ_SPI(120)
+#define IRQ_MCT_L1		IRQ_SPI(121)
+
+#define IRQ_DWMCI		IRQ_SPI(123)
+#define IRQ_MDMA1		IRQ_SPI(124)
+#define IRQ_FIMC_LITE0		IRQ_SPI(125)
+#define IRQ_FIMC_LITE1		IRQ_SPI(126)
+#define IRQ_RP_TIMER		IRQ_SPI(127)
+
+#define MAX_IRQ_IN_COMBINER	8
+#define COMBINER_GROUP(x)	((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128))
+#define COMBINER_IRQ(x, y)	(COMBINER_GROUP(x) + y)
+
+#define IRQ_PMU			COMBINER_IRQ(1, 2)
+
+#define EXYNOS5_IRQ_SYSMMU_GSC0_0	COMBINER_IRQ(2, 0)
+#define EXYNOS5_IRQ_SYSMMU_GSC0_1	COMBINER_IRQ(2, 1)
+#define EXYNOS5_IRQ_SYSMMU_GSC1_0	COMBINER_IRQ(2, 2)
+#define EXYNOS5_IRQ_SYSMMU_GSC1_1	COMBINER_IRQ(2, 3)
+#define EXYNOS5_IRQ_SYSMMU_GSC2_0	COMBINER_IRQ(2, 4)
+#define EXYNOS5_IRQ_SYSMMU_GSC2_1	COMBINER_IRQ(2, 5)
+#define EXYNOS5_IRQ_SYSMMU_GSC3_0	COMBINER_IRQ(2, 6)
+#define EXYNOS5_IRQ_SYSMMU_GSC3_1	COMBINER_IRQ(2, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_LITE2_0	COMBINER_IRQ(3, 0)
+#define EXYNOS5_IRQ_SYSMMU_LITE2_1	COMBINER_IRQ(3, 1)
+#define EXYNOS5_IRQ_SYSMMU_FIMD1_0	COMBINER_IRQ(3, 2)
+#define EXYNOS5_IRQ_SYSMMU_FIMD1_1	COMBINER_IRQ(3, 3)
+#define EXYNOS5_IRQ_SYSMMU_LITE0_0	COMBINER_IRQ(3, 4)
+#define EXYNOS5_IRQ_SYSMMU_LITE0_1	COMBINER_IRQ(3, 5)
+#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_0	COMBINER_IRQ(3, 6)
+#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_1	COMBINER_IRQ(3, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_ROTATOR_0	COMBINER_IRQ(4, 0)
+#define EXYNOS5_IRQ_SYSMMU_ROTATOR_1	COMBINER_IRQ(4, 1)
+#define EXYNOS5_IRQ_SYSMMU_JPEG_0	COMBINER_IRQ(4, 2)
+#define EXYNOS5_IRQ_SYSMMU_JPEG_1	COMBINER_IRQ(4, 3)
+
+#define EXYNOS5_IRQ_SYSMMU_FD_0		COMBINER_IRQ(5, 0)
+#define EXYNOS5_IRQ_SYSMMU_FD_1		COMBINER_IRQ(5, 1)
+#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_0	COMBINER_IRQ(5, 2)
+#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_1	COMBINER_IRQ(5, 3)
+#define EXYNOS5_IRQ_SYSMMU_MCUISP_0	COMBINER_IRQ(5, 4)
+#define EXYNOS5_IRQ_SYSMMU_MCUISP_1	COMBINER_IRQ(5, 5)
+#define EXYNOS5_IRQ_SYSMMU_3DNR_0	COMBINER_IRQ(5, 6)
+#define EXYNOS5_IRQ_SYSMMU_3DNR_1	COMBINER_IRQ(5, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_ARM_0	COMBINER_IRQ(6, 0)
+#define EXYNOS5_IRQ_SYSMMU_ARM_1	COMBINER_IRQ(6, 1)
+#define EXYNOS5_IRQ_SYSMMU_MFC_R_0	COMBINER_IRQ(6, 2)
+#define EXYNOS5_IRQ_SYSMMU_MFC_R_1	COMBINER_IRQ(6, 3)
+#define EXYNOS5_IRQ_SYSMMU_RTIC_0	COMBINER_IRQ(6, 4)
+#define EXYNOS5_IRQ_SYSMMU_RTIC_1	COMBINER_IRQ(6, 5)
+#define EXYNOS5_IRQ_SYSMMU_SSS_0	COMBINER_IRQ(6, 6)
+#define EXYNOS5_IRQ_SYSMMU_SSS_1	COMBINER_IRQ(6, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_MDMA0_0	COMBINER_IRQ(7, 0)
+#define EXYNOS5_IRQ_SYSMMU_MDMA0_1	COMBINER_IRQ(7, 1)
+#define EXYNOS5_IRQ_SYSMMU_MDMA1_0	COMBINER_IRQ(7, 2)
+#define EXYNOS5_IRQ_SYSMMU_MDMA1_1	COMBINER_IRQ(7, 3)
+#define EXYNOS5_IRQ_SYSMMU_TV_0		COMBINER_IRQ(7, 4)
+#define EXYNOS5_IRQ_SYSMMU_TV_1		COMBINER_IRQ(7, 5)
+#define EXYNOS5_IRQ_SYSMMU_GPSX_0	COMBINER_IRQ(7, 6)
+#define EXYNOS5_IRQ_SYSMMU_GPSX_1	COMBINER_IRQ(7, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_MFC_L_0	COMBINER_IRQ(8, 5)
+#define EXYNOS5_IRQ_SYSMMU_MFC_L_1	COMBINER_IRQ(8, 6)
+
+#define EXYNOS5_IRQ_SYSMMU_DIS1_0	COMBINER_IRQ(9, 4)
+#define EXYNOS5_IRQ_SYSMMU_DIS1_1	COMBINER_IRQ(9, 5)
+
+#define IRQ_DP				COMBINER_IRQ(10, 3)
+#define EXYNOS5_IRQ_SYSMMU_DIS0_0	COMBINER_IRQ(10, 4)
+#define EXYNOS5_IRQ_SYSMMU_DIS0_1	COMBINER_IRQ(10, 5)
+#define EXYNOS5_IRQ_SYSMMU_ISP_0	COMBINER_IRQ(10, 6)
+#define EXYNOS5_IRQ_SYSMMU_ISP_1	COMBINER_IRQ(10, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_ODC_0	COMBINER_IRQ(11, 0)
+#define EXYNOS5_IRQ_SYSMMU_ODC_1	COMBINER_IRQ(11, 1)
+#define EXYNOS5_IRQ_SYSMMU_DRC_0	COMBINER_IRQ(11, 6)
+#define EXYNOS5_IRQ_SYSMMU_DRC_1	COMBINER_IRQ(11, 7)
+
+#define IRQ_MDMA1_ABORT		COMBINER_IRQ(13, 1)
+
+#define IRQ_MDMA0_ABORT		COMBINER_IRQ(15, 3)
+
+#define IRQ_C2C_SSCM0		COMBINER_IRQ(17, 0)
+#define IRQ_C2C_SSCM1		COMBINER_IRQ(17, 1)
+
+#define IRQ_FIMD0_FIFO		COMBINER_IRQ(18, 0)
+#define IRQ_FIMD0_VSYNC		COMBINER_IRQ(18, 1)
+#define IRQ_FIMD0_SYSTEM	COMBINER_IRQ(18, 2)
+
+#define IRQ_FIMD1_FIFO		COMBINER_IRQ(18, 4)
+#define IRQ_FIMD1_VSYNC		COMBINER_IRQ(18, 5)
+#define IRQ_FIMD1_SYSTEM	COMBINER_IRQ(18, 6)
+
+#define IRQ_ARMIOP_GIC		COMBINER_IRQ(19, 0)
+#define IRQ_ARMISP_GIC		COMBINER_IRQ(19, 1)
+#define IRQ_IOP_GIC		COMBINER_IRQ(19, 3)
+#define IRQ_ISP_GIC		COMBINER_IRQ(19, 4)
+
+#define IRQ_PMU_CPU1		COMBINER_IRQ(22, 4)
+
+#define IRQ_EINT0		COMBINER_IRQ(23, 0)
+#define IRQ_MCT_G0		COMBINER_IRQ(23, 3)
+#define IRQ_MCT_G1		COMBINER_IRQ(23, 4)
+
+#define IRQ_EINT1			COMBINER_IRQ(24, 0)
+#define EXYNOS5_IRQ_SYSMMU_LITE1_0	COMBINER_IRQ(24, 1)
+#define EXYNOS5_IRQ_SYSMMU_LITE1_1	COMBINER_IRQ(24, 2)
+#define EXYNOS5_IRQ_SYSMMU_2D_0		COMBINER_IRQ(24, 5)
+#define EXYNOS5_IRQ_SYSMMU_2D_1		COMBINER_IRQ(24, 6)
+
+#define IRQ_EINT2		COMBINER_IRQ(25, 0)
+#define IRQ_EINT3		COMBINER_IRQ(25, 1)
+
+#define IRQ_EINT4		COMBINER_IRQ(26, 0)
+#define IRQ_EINT5		COMBINER_IRQ(26, 1)
+
+#define IRQ_EINT6		COMBINER_IRQ(27, 0)
+#define IRQ_EINT7		COMBINER_IRQ(27, 1)
+
+#define IRQ_EINT8		COMBINER_IRQ(28, 0)
+#define IRQ_EINT9		COMBINER_IRQ(28, 1)
+
+#define IRQ_EINT10		COMBINER_IRQ(29, 0)
+#define IRQ_EINT11		COMBINER_IRQ(29, 1)
+
+#define IRQ_EINT12		COMBINER_IRQ(30, 0)
+#define IRQ_EINT13		COMBINER_IRQ(30, 1)
+
+#define IRQ_EINT14		COMBINER_IRQ(31, 0)
+#define IRQ_EINT15		COMBINER_IRQ(31, 1)
+
+#define MAX_COMBINER_NR		32
+
+#define S5P_IRQ_EINT_BASE	COMBINER_IRQ(MAX_COMBINER_NR, 0)
+
+#define S5P_EINT_BASE1		(S5P_IRQ_EINT_BASE + 0)
+#define S5P_EINT_BASE2		(S5P_IRQ_EINT_BASE + 16)
+
+#define IRQ_TVOUT_HPD		(S5P_IRQ_EINT_BASE + 31)
+
+#define IRQ_ADC			IRQ_ADC0
+
+/* optional GPIO interrupts */
+#define S5P_GPIOINT_BASE	(S5P_IRQ_EINT_BASE + 32)
+#define IRQ_GPIO1_NR_GROUPS	14
+#define IRQ_GPIO2_NR_GROUPS	9
+#define IRQ_GPIO3_NR_GROUPS	5
+#define IRQ_GPIO4_NR_GROUPS	1
+#define IRQ_GPIO_END		(S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
+
+#define IRQ_BOARD_START		IRQ_GPIO_END
+
+#if defined(CONFIG_MFD_MAX77693) || defined(CONFIG_MFD_MAX77686)
+#define IRQ_BOARD_IFIC_START   (IRQ_BOARD_START)
+#define IRQ_BOARD_IFIC_NR      29
+#define IRQ_BOARD_PMIC_START   (IRQ_BOARD_START + IRQ_BOARD_IFIC_NR)
+#define IRQ_BOARD_PMIC_NR      16
+#define IRQ_BOARD_CODEC_START  (IRQ_BOARD_PMIC_START + IRQ_BOARD_PMIC_NR)
+#define IRQ_BOARD_CODEC_NR     32
+#define IRQ_NR_BOARD           (IRQ_BOARD_PMIC_NR + IRQ_BOARD_IFIC_NR + IRQ_BOARD_CODEC_NR)
+#else
+#define IRQ_NR_BOARD		40
+#endif
+/* Set the default NR_IRQS */
+#define NR_IRQS			(IRQ_GPIO_END + IRQ_NR_BOARD)
+
+#endif /* __ASM_ARCH_IRQS_EXYNOS5_H */
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
new file mode 100644
index 0000000..2c5bb1d
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -0,0 +1,40 @@
+/* linux/arch/arm/mach-exynos/include/mach/irqs.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS - IRQ definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H __FILE__
+
+#include <plat/irqs.h>
+
+/* SGI: Software Generated Interrupt */
+
+#define IRQ_SGI(x)		S5P_IRQ(x)
+
+/* PPI: Private Peripheral Interrupt */
+
+#define IRQ_PPI(x)		S5P_IRQ(x+16)
+
+#define IRQ_PPI_MCT_L		IRQ_PPI(12)
+
+/* SPI: Shared Peripheral Interrupt */
+
+#define IRQ_SPI(x)		S5P_IRQ(x+32)
+
+#if defined(CONFIG_ARCH_EXYNOS4)
+#include "irqs-exynos4.h"
+#elif defined(CONFIG_ARCH_EXYNOS5)
+#include "irqs-exynos5.h"
+#else
+#error "ARCH_EXYNOS* is not defined"
+#endif
+
+#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-exynos/include/mach/map-exynos4.h b/arch/arm/mach-exynos/include/mach/map-exynos4.h
new file mode 100644
index 0000000..0a22891
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/map-exynos4.h
@@ -0,0 +1,319 @@
+/* linux/arch/arm/mach-exynos/include/mach/map-exynos4.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * EXYNOS4 - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_MAP_EXYNOS4_H
+#define __ASM_ARCH_MAP_EXYNOS4_H __FILE__
+
+#define EXYNOS4_PA_SYSRAM0		0x02025000
+#define EXYNOS4_PA_SYSRAM1		0x02020000
+#define EXYNOS4_PA_SYSRAM_NS		0x0203F000
+#define EXYNOS4_PA_SYSRAM_NS_4212	0x0204F000
+
+#define EXYNOS4_PA_FIMC0		0x11800000
+#define EXYNOS4_PA_FIMC1		0x11810000
+#define EXYNOS4_PA_FIMC2		0x11820000
+#define EXYNOS4_PA_FIMC3		0x11830000
+
+#define EXYNOS4_PA_JPEG			0x11840000
+
+#define EXYNOS4_PA_AUDSS		0x03810000
+#define EXYNOS4_PA_I2S0			0x03830000
+#define EXYNOS4_PA_I2S1			0xE2100000
+#define EXYNOS4_PA_I2S2			0xE2A00000
+#define EXYNOS4212_PA_I2S1		0x13960000
+#define EXYNOS4212_PA_I2S2		0x13970000
+
+#define EXYNOS4_PA_PCM0			0x03840000
+#define EXYNOS4_PA_PCM1			0x13980000
+#define EXYNOS4_PA_PCM2			0x13990000
+
+#define EXYNOS4_PA_SROM_BANK(x)		(0x04000000 + ((x) * 0x01000000))
+
+#define EXYNOS4_PA_ONENAND		0x0C000000
+#define EXYNOS4_PA_ONENAND_DMA		0x0C600000
+
+#define EXYNOS4_PA_CHIPID		0x10000000
+
+#define EXYNOS4_PA_SYSCON		0x10010000
+#define EXYNOS4_PA_PMU			0x10020000
+#define EXYNOS4_PA_CMU			0x10030000
+
+#define EXYNOS4_PA_SYSTIMER		0x10050000
+#define EXYNOS4_PA_WATCHDOG		0x10060000
+#define EXYNOS4_PA_RTC			0x10070000
+
+#define EXYNOS4_PA_KEYPAD		0x100A0000
+
+#define EXYNOS4_PA_CEC			0x100B0000
+
+#define EXYNOS4_PA_TMU			0x100C0000
+
+#define EXYNOS4_PA_DMC0			0x10400000
+#define EXYNOS4_PA_DMC1			0x10410000
+
+#define EXYNOS4_PA_COMBINER		0x10440000
+
+#define EXYNOS4_PA_IEM			0x10460000
+
+#define EXYNOS4_PA_GIC_CPU		0x10480000
+#define EXYNOS4_PA_GIC_DIST		0x10490000
+
+#define EXYNOS4_PA_COREPERI		0x10500000
+#define EXYNOS4_PA_TWD			0x10500600
+#define EXYNOS4_PA_L2CC			0x10502000
+
+#define EXYNOS4_PA_C2C			0x10540000
+#define EXYNOS4_PA_C2C_CP		0x10580000
+
+#define EXYNOS4_PA_DMC0_4212		0x10600000
+#define EXYNOS4_PA_DMC1_4212		0x10610000
+
+#define EXYNOS4_PA_PPMU_DMC0		0x106A0000
+#define EXYNOS4_PA_PPMU_DMC1		0x106B0000
+#define EXYNOS4_PA_PPMU_CPU		0x106C0000
+
+#define EXYNOS4_PA_GDL			0x11600000
+#define EXYNOS4_PA_GDR			0x11200000
+
+#define EXYNOS4_PA_S_MDMA0		0x10800000
+#define EXYNOS4_PA_NS_MDMA0		0x10810000
+#define EXYNOS4_PA_ACE			0x10830000
+#define EXYNOS4_PA_S_MDMA1		0x12840000
+#define EXYNOS4_PA_NS_MDMA1		0x12850000
+#define EXYNOS4_PA_PDMA0		0x12680000
+#define EXYNOS4_PA_PDMA1		0x12690000
+
+#define EXYNOS4_PA_SYSMMU_G2D_ACP	0x10A40000
+#define EXYNOS4_PA_SYSMMU_SSS		0x10A50000
+#define EXYNOS4_PA_SYSMMU_FIMC0		0x11A20000
+#define EXYNOS4_PA_SYSMMU_FIMC1		0x11A30000
+#define EXYNOS4_PA_SYSMMU_FIMC2		0x11A40000
+#define EXYNOS4_PA_SYSMMU_FIMC3		0x11A50000
+#define EXYNOS4_PA_SYSMMU_JPEG		0x11A60000
+#define EXYNOS4_PA_LCD_LITE0		0x11C40000
+#define EXYNOS4_PA_DSIM0		0x11C80000
+#define EXYNOS4_PA_MDNIE0		0x11CA0000
+#define EXYNOS4_PA_DSIM1		0x12080000
+#define EXYNOS4_PA_SYSMMU_FIMD0		0x11E20000
+#define EXYNOS4_PA_SYSMMU_FIMD1		0x12220000
+#define EXYNOS4_PA_SYSMMU_ISP		0x12260000
+#define EXYNOS4_PA_SYSMMU_DRC		0x12270000
+#define EXYNOS4_PA_SYSMMU_FD		0x122A0000
+#define EXYNOS4_PA_SYSMMU_ISPCPU	0x122B0000
+#define EXYNOS4_PA_SYSMMU_LITE0		0x123B0000
+#define EXYNOS4_PA_SYSMMU_LITE1		0x123C0000
+#define EXYNOS4_PA_SYSMMU_PCIe		0x12620000
+#define EXYNOS4_PA_SYSMMU_GPS		0x12730000
+#define EXYNOS4_PA_SYSMMU_2D		0x12A20000
+#define EXYNOS4_PA_SYSMMU_ROTATOR	0x12A30000
+#define EXYNOS4_PA_SYSMMU_MDMA2		0x12A40000
+#define EXYNOS4_PA_SYSMMU_TV		0x12E20000
+#define EXYNOS4_PA_SYSMMU_MFC_L		0x13620000
+#define EXYNOS4_PA_SYSMMU_MFC_R		0x13630000
+
+#define EXYNOS4_PA_GPIO1		0x11400000
+#define EXYNOS4_PA_GPIO2		0x11000000
+#define EXYNOS4_PA_GPIO3		0x03860000
+#define EXYNOS4_PA_GPIO4		0x106E0000
+
+#define EXYNOS4_PA_MIPI_CSIS0		0x11880000
+#define EXYNOS4_PA_MIPI_CSIS1		0x11890000
+
+#define EXYNOS4_PA_FIMD0		0x11C00000
+#define EXYNOS4_PA_FIMD1		0x12000000
+#define EXYNOS4_PA_FIMC_IS		0x12000000
+
+#define EXYNOS4_PA_FIMC_LITE0		0x12390000
+#define EXYNOS4_PA_FIMC_LITE1		0x123A0000
+
+#define EXYNOS4_PA_HSOTG		0x12480000
+#define EXYNOS4_PA_HSPHY		0x125B0000
+
+/* s3c-tsi */
+#define EXYNOS4_PA_TSI			(0x12500000)
+
+#define EXYNOS4_PA_HSMMC(x)		(0x12510000 + ((x) * 0x10000))
+#define EXYNOS4_PA_DWMCI		0x12550000
+
+#define EXYNOS4_PA_SATA			0x12560000
+#define EXYNOS4_PA_SATAPHY		0x125D0000
+#define EXYNOS4_PA_SATAPHY_CTRL		0x126B0000
+
+#define EXYNOS4_PA_SROMC		0x12570000
+
+#define EXYNOS4_PA_EHCI			0x12580000
+#define EXYNOS4_PA_OHCI			0x12590000
+#define EXYNOS4_PA_HSPHY		0x125B0000
+
+#define EXYNOS4412_PA_ADC		0x126C0000
+
+#define EXYNOS4_PA_GPS			0x12700000
+
+#define EXYNOS4_PA_FIMG2D		0x10800000
+
+#define EXYNOS4_PA_ROTATOR		0x12810000
+
+#define EXYNOS4_PA_VP			0x12C00000
+#define EXYNOS4_PA_MIXER		0x12C10000
+#define EXYNOS4_PA_TVENC		0x12C20000
+#define EXYNOS4_PA_SDO			0x12C20000
+#define EXYNOS4_PA_HDMI			0x12D00000
+
+#define EXYNOS4_PA_G3D			0x13000000
+
+#define EXYNOS4_PA_MFC			0x13400000
+
+#define EXYNOS4_PA_UART			0x13800000
+
+#define EXYNOS4_PA_IIC(x)		(0x13860000 + ((x) * 0x10000))
+
+#define EXYNOS4_I2C_HDMI_PHY		0x138E0000
+#define EXYNOS4_PA_IIC_HDMIPHY		0x138E0000
+
+#define EXYNOS4210_PA_ADC		0x13910000
+#define EXYNOS4210_PA_ADC1		0x13911000
+
+#define EXYNOS4_PA_SPI0			0x13920000
+#define EXYNOS4_PA_SPI1			0x13930000
+#define EXYNOS4_PA_SPI2			0x13940000
+
+#define EXYNOS4_PA_AC97			0x139A0000
+
+#define EXYNOS4_PA_SPDIF		0x139B0000
+
+#define EXYNOS4_PA_TIMER		0x139D0000
+
+#define EXYNOS4_PA_SDRAM		0x40000000
+
+/* Compatibiltiy Defines */
+
+#define EXYNOS_PA_DWMCI			EXYNOS4_PA_DWMCI
+
+#define EXYNOS_PA_AUDSS			EXYNOS4_PA_AUDSS
+#define EXYNOS_PA_I2S0			EXYNOS4_PA_I2S0
+#define EXYNOS_PA_I2S1			EXYNOS4_PA_I2S1
+#define EXYNOS_PA_I2S2			EXYNOS4_PA_I2S2
+
+#define EXYNOS_PA_PCM0			EXYNOS4_PA_PCM0
+#define EXYNOS_PA_PCM1			EXYNOS4_PA_PCM1
+#define EXYNOS_PA_PCM2			EXYNOS4_PA_PCM2
+
+#define EXYNOS_PA_SPI0			EXYNOS4_PA_SPI0
+#define EXYNOS_PA_SPI1			EXYNOS4_PA_SPI1
+#define EXYNOS_PA_SPI2			EXYNOS4_PA_SPI2
+
+#define EXYNOS_PA_AC97			EXYNOS4_PA_AC97
+
+#define EXYNOS_PA_SPDIF			EXYNOS4_PA_SPDIF
+
+#define EXYNOS_PA_FIMC_LITE0		EXYNOS4_PA_FIMC_LITE0
+#define EXYNOS_PA_FIMC_LITE1		EXYNOS4_PA_FIMC_LITE1
+
+#define EXYNOS_PA_ROTATOR		EXYNOS4_PA_ROTATOR
+
+#define EXYNOS_PA_C2C			EXYNOS4_PA_C2C
+#define EXYNOS_PA_C2C_CP		EXYNOS4_PA_C2C_CP
+
+#define S5P_PA_TSI			EXYNOS4_PA_TSI
+#define S5P_SZ_TSI			SZ_256
+
+#define S3C_PA_HSMMC0			EXYNOS4_PA_HSMMC(0)
+#define S3C_PA_HSMMC1			EXYNOS4_PA_HSMMC(1)
+#define S3C_PA_HSMMC2			EXYNOS4_PA_HSMMC(2)
+#define S3C_PA_HSMMC3			EXYNOS4_PA_HSMMC(3)
+#define S3C_PA_IIC			EXYNOS4_PA_IIC(0)
+#define S3C_PA_IIC1			EXYNOS4_PA_IIC(1)
+#define S3C_PA_IIC2			EXYNOS4_PA_IIC(2)
+#define S3C_PA_IIC3			EXYNOS4_PA_IIC(3)
+#define S3C_PA_IIC4			EXYNOS4_PA_IIC(4)
+#define S3C_PA_IIC5			EXYNOS4_PA_IIC(5)
+#define S3C_PA_IIC6			EXYNOS4_PA_IIC(6)
+#define S3C_PA_IIC7			EXYNOS4_PA_IIC(7)
+#if defined(CONFIG_CPU_EXYNOS4210)
+#define SAMSUNG_PA_ADC			EXYNOS4210_PA_ADC
+#define SAMSUNG_PA_ADC1			EXYNOS4210_PA_ADC1
+#elif defined(CONFIG_CPU_EXYNOS4412)
+#define SAMSUNG_PA_ADC			EXYNOS4412_PA_ADC
+#endif
+#define S3C_PA_RTC			EXYNOS4_PA_RTC
+#define S3C_PA_WDT			EXYNOS4_PA_WATCHDOG
+
+#define S5P_PA_CHIPID			EXYNOS4_PA_CHIPID
+#define S5P_PA_FIMC0			EXYNOS4_PA_FIMC0
+#define S5P_PA_FIMC1			EXYNOS4_PA_FIMC1
+#define S5P_PA_FIMC2			EXYNOS4_PA_FIMC2
+#define S5P_PA_FIMC3			EXYNOS4_PA_FIMC3
+#define S5P_PA_MIPI_CSIS0		EXYNOS4_PA_MIPI_CSIS0
+#define S5P_PA_MIPI_CSIS1		EXYNOS4_PA_MIPI_CSIS1
+#define S5P_PA_FIMD0			EXYNOS4_PA_FIMD0
+#define S5P_PA_FIMD1			EXYNOS4_PA_FIMD1
+#define S5P_PA_FIMG2D			EXYNOS4_PA_FIMG2D
+#define S5P_PA_ONENAND			EXYNOS4_PA_ONENAND
+#define S5P_PA_ONENAND_DMA		EXYNOS4_PA_ONENAND_DMA
+#define S5P_PA_SDRAM			EXYNOS4_PA_SDRAM
+#define S5P_PA_SROMC			EXYNOS4_PA_SROMC
+#define S5P_PA_MFC			EXYNOS4_PA_MFC
+#define S5P_PA_SYSCON			EXYNOS4_PA_SYSCON
+#define S5P_PA_TIMER			EXYNOS4_PA_TIMER
+#define S5P_PA_HSOTG			EXYNOS4_PA_HSOTG
+#define S5P_PA_HSPHY			EXYNOS4_PA_HSPHY
+#define S5P_PA_EHCI			EXYNOS4_PA_EHCI
+#define S5P_PA_OHCI			EXYNOS4_PA_OHCI
+#define S5P_PA_JPEG			EXYNOS4_PA_JPEG
+#define S5P_PA_TMU			EXYNOS4_PA_TMU
+#define S5P_PA_DSIM0			EXYNOS4_PA_DSIM0
+#define S5P_PA_DSIM1			EXYNOS4_PA_DSIM1
+
+#define SAMSUNG_PA_KEYPAD		EXYNOS4_PA_KEYPAD
+
+#define S5P_PA_HDMI_CEC			EXYNOS4_PA_CEC
+#define S5P_SZ_HDMI_CEC			SZ_4K
+
+#define S5P_PA_VP			EXYNOS4_PA_VP
+#define S5P_PA_MIXER			EXYNOS4_PA_MIXER
+#define S5P_PA_TVENC			EXYNOS4_PA_TVENC
+#define S5P_PA_SDO			EXYNOS4_PA_SDO
+#define S5P_PA_HDMI			EXYNOS4_PA_HDMI
+#define S5P_I2C_HDMI_PHY		EXYNOS4_I2C_HDMI_PHY
+#define S5P_PA_IIC_HDMIPHY		EXYNOS4_PA_IIC_HDMIPHY
+#define S5P_SZ_LCD_LITE0		SZ_32K
+#define S5P_SZ_MDNIE0			SZ_4K
+#define S5P_SZ_VP			SZ_64K
+#define S5P_SZ_MIXER			SZ_64K
+#define S5P_SZ_TVENC			SZ_64K
+#define S5P_SZ_SDO			SZ_64K
+#define S5P_SZ_HDMI			SZ_1M
+#define S5P_I2C_HDMI_SZ_PHY		SZ_1K
+#define S5P_SZ_IIC_HDMIPHY		SZ_1K
+#define S5P_PA_ACE			EXYNOS4_PA_ACE
+
+#define S5P_PA_MDMA0			EXYNOS4_PA_NS_MDMA0
+#define S5P_PA_MDMA1			EXYNOS4_PA_NS_MDMA1
+#define S5P_PA_PDMA0			EXYNOS4_PA_PDMA0
+#define S5P_PA_PDMA1			EXYNOS4_PA_PDMA1
+
+/* UART */
+
+#define S3C_VA_UARTx(x)			(S3C_VA_UART + ((x) * S3C_UART_OFFSET))
+
+#define S3C_PA_UART			EXYNOS4_PA_UART
+
+#define S5P_PA_UART(x)			(S3C_PA_UART + ((x) * S3C_UART_OFFSET))
+#define S5P_PA_UART0			S5P_PA_UART(0)
+#define S5P_PA_UART1			S5P_PA_UART(1)
+#define S5P_PA_UART2			S5P_PA_UART(2)
+#define S5P_PA_UART3			S5P_PA_UART(3)
+#define S5P_PA_UART4			S5P_PA_UART(4)
+
+#define S5P_SZ_UART			SZ_256
+
+#endif /* __ASM_ARCH_MAP_EXYNOS4_H */
diff --git a/arch/arm/mach-exynos/include/mach/map-exynos5.h b/arch/arm/mach-exynos/include/mach/map-exynos5.h
new file mode 100644
index 0000000..536356e
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/map-exynos5.h
@@ -0,0 +1,295 @@
+/* linux/arch/arm/mach-exynos/include/mach/map-exynos5.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * EXYNOS5 - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_MAP_EXYNOS5_H
+#define __ASM_ARCH_MAP_EXYNOS5_H __FILE__
+
+#define EXYNOS5_PA_SYSRAM		0x02020000
+#define EXYNOS5_PA_SYSRAM_NS            0x0204F000
+
+#define EXYNOS5_PA_CHIPID		0x10000000
+
+#define EXYNOS5_PA_CMU			0x10010000
+
+#define EXYNOS5_PA_PMU			0x10040000
+
+#define EXYNOS5_PA_HDMI_CEC		0x101B0000
+#define EXYNOS5_PA_SYSTIMER		0x101C0000
+#define EXYNOS5_PA_WATCHDOG		0x101D0000
+#define EXYNOS5_PA_RTC			0x101E0000
+
+#define EXYNOS5_PA_COMBINER		0x10440000
+
+#define EXYNOS5250_REV0_PA_GIC_CPU	0x10480000
+#define EXYNOS5250_REV0_PA_GIC_DIST	0x10490000
+#define EXYNOS5250_REV1_PA_GIC_CPU	0x10482000
+#define EXYNOS5250_REV1_PA_GIC_DIST	0x10481000
+
+#define EXYNOS5_PA_SYSCON		0x10050000
+#define EXYNOS5_PA_TMU			0x10060000
+#define EXYNOS5_PA_ACE			0x10830000
+
+#define EXYNOS5_PA_DMC_PHY0		0x10C00000
+#define EXYNOS5_PA_DMC_PHY1		0x10C10000
+#define EXYNOS5_PA_DMC			0x10DD0000
+
+#define EXYNOS5_PA_PPMU_DDR_C		0x10C40000
+#define EXYNOS5_PA_PPMU_DDR_R1		0x10C50000
+#define EXYNOS5_PA_PPMU_CPU		0x10C60000
+#define EXYNOS5_PA_PPMU_DDR_L		0x10CB0000
+#define EXYNOS5_PA_PPMU_RIGHT0_BUS      0x13660000
+
+#define EXYNOS5_PA_C2C			0x10E00000
+#define EXYNOS5_PA_C2C_CP		0x10E40000
+
+#define EXYNOS5_PA_SYSMMU_MDMA1		0x10A40000
+#define EXYNOS5_PA_SYSMMU_SSS		0x10A50000
+#define EXYNOS5_PA_SYSMMU_2D		0x10A60000
+#define EXYNOS5_PA_SYSMMU_MFC_R		0x11200000
+#define EXYNOS5_PA_SYSMMU_MFC_L		0x11210000
+#define EXYNOS5_PA_SYSMMU_ROTATOR	0x11D40000
+#define EXYNOS5_PA_SYSMMU_MDMA2		0x11D50000
+#define EXYNOS5_PA_SYSMMU_JPEG		0x11F20000
+#define EXYNOS5_PA_SYSMMU_IOP		0x12360000
+#define EXYNOS5_PA_SYSMMU_RTIC		0x12370000
+#define EXYNOS5_PA_SYSMMU_GPS		0x12630000
+#define EXYNOS5_PA_SYSMMU_ISP		0x13260000
+#define EXYNOS5_PA_SYSMMU_DRC		0x13270000
+#define EXYNOS5_PA_SYSMMU_SCALERC	0x13280000
+#define EXYNOS5_PA_SYSMMU_SCALERP	0x13290000
+#define EXYNOS5_PA_SYSMMU_FD		0x132A0000
+#define EXYNOS5_PA_SYSMMU_ISPCPU	0x132B0000
+#define EXYNOS5_PA_SYSMMU_ODC		0x132C0000
+#define EXYNOS5_PA_SYSMMU_DIS0		0x132D0000
+#define EXYNOS5_PA_SYSMMU_DIS1		0x132E0000
+#define EXYNOS5_PA_SYSMMU_3DNR		0x132F0000
+#define EXYNOS5_PA_SYSMMU_LITE0		0x13C40000
+#define EXYNOS5_PA_SYSMMU_LITE1		0x13C50000
+#define EXYNOS5_PA_SYSMMU_LITE2		0x13CA0000
+#define EXYNOS5_PA_SYSMMU_GSC0		0x13E80000
+#define EXYNOS5_PA_SYSMMU_GSC1		0x13E90000
+#define EXYNOS5_PA_SYSMMU_GSC2		0x13EA0000
+#define EXYNOS5_PA_SYSMMU_GSC3		0x13EB0000
+#define EXYNOS5_PA_SYSMMU_FIMD1		0x14640000
+#define EXYNOS5_PA_SYSMMU_TV		0x14650000
+
+#define EXYNOS5_PA_FIMG2D		0x10850000
+#define EXYNOS5_PA_MFC			0x11000000
+
+#define EXYNOS5_PA_GPIO1		0x11400000
+#define EXYNOS5_PA_GPIO2		0x13400000
+#define EXYNOS5_PA_GPIO3		0x10D10000
+#define EXYNOS5_PA_GPIO4		0x03860000
+
+#define EXYNOS5_PA_G3D			0x11800000
+
+#define EXYNOS5_PA_HSMMC(x)		(0x12200000 + ((x) * 0x10000))
+#define EXYNOS5_PA_DWMCI		0x12240000
+
+#define EXYNOS5_PA_SS_UDC		0x1200C100
+#define EXYNOS5_PA_SS_DRD		0x12000000
+#define EXYNOS5_PA_SS_PHY		0x12100000
+#define EXYNOS5_PA_EHCI			0x12110000
+#define EXYNOS5_PA_OHCI			0x12120000
+#define EXYNOS5_PA_HSPHY		0x12130000
+#define EXYNOS5_PA_HSOTG		0x12140000
+
+#define EXYNOS5_PA_SATA_PHY_CTRL	0x12170000
+#define EXYNOS5_PA_SATA_PHY_I2C		0x121D0000
+#define EXYNOS5_PA_SATA_BASE		0x122F0000
+
+#define EXYNOS5_PA_SROMC		0x12250000
+#define EXYNOS4_PA_SROM_BANK(x)		(0x04000000 + ((x) * 0x01000000))
+
+#define EXYNOS5_PA_UART			0x12C00000
+
+#define EXYNOS5_PA_IIC(x)		(0x12C60000 + ((x) * 0x10000))
+#define EXYNOS5_PA_IIC_HDMIPHY		0x12CE0000
+
+#define EXYNOS5_PA_ADC			0x12D10000
+
+#define EXYNOS5_PA_SPI0			0x12D20000
+#define EXYNOS5_PA_SPI1			0x12D30000
+#define EXYNOS5_PA_SPI2			0x12D40000
+
+#define EXYNOS5_PA_TIMER		0x12DD0000
+
+#define EXYNOS5_PA_FIMD0		0x13800000
+#define EXYNOS5_PA_FIMD1		0x14400000
+#define EXYNOS5_PA_MIXER		0x14450000
+#define EXYNOS5_PA_DSIM0		0x14500000
+#define EXYNOS5_PA_DP			0x145B0000
+#define EXYNOS5_PA_HDMI			0x14530000
+
+#define EXYNOS5_PA_FIMC_IS		0x13000000
+
+#define EXYNOS5_PA_FIMC_LITE0		0x13C00000
+#define EXYNOS5_PA_FIMC_LITE1		0x13C10000
+#define EXYNOS5_PA_FIMC_LITE2		0x13C90000
+
+#define EXYNOS5_PA_MIPI_CSIS0		0x13C20000
+#define EXYNOS5_PA_MIPI_CSIS1		0x13C30000
+
+#define EXYNOS5_PA_GSC0 		0x13E00000
+#define EXYNOS5_PA_GSC1 		0x13E10000
+#define EXYNOS5_PA_GSC2 		0x13E20000
+#define EXYNOS5_PA_GSC3 		0x13E30000
+
+#define EXYNOS5_PA_ROTATOR		0x11c00000
+
+#define EXYNOS5_PA_SDRAM		0x40000000
+
+#define EXYNOS5_PA_NS_MDMA0		0x10800000
+#define EXYNOS5_PA_NS_MDMA1		0x11c10000
+#define EXYNOS5_PA_PDMA0		0x121a0000
+#define EXYNOS5_PA_PDMA1		0x121b0000
+
+#define EXYNOS5_PA_AUDSS		0x03810000
+#define EXYNOS5_PA_I2S0			0x03830000
+#define EXYNOS5_PA_I2S1			0x12D60000
+#define EXYNOS5_PA_I2S2			0x12D70000
+
+#define EXYNOS5_PA_PCM0			0x03840000
+#define EXYNOS5_PA_PCM1			0x12D80000
+#define EXYNOS5_PA_PCM2			0x12D90000
+
+#define EXYNOS5_PA_AC97			0x12DA0000
+
+#define EXYNOS5_PA_SPDIF		0x12DB0000
+#define EXYNOS4_PA_JPEG		0x11E00000
+
+#define EXYNOS5_PA_BTS_CPU		0x10C80000
+#define EXYNOS5_PA_BTS_G3D_ACP		0x10EA0000
+#define EXYNOS5_PA_BTS_MFC0		0x11220000
+#define EXYNOS5_PA_BTS_MFC1		0x11230000
+#define EXYNOS5_PA_BTS_ROTATOR		0x11D60000
+#define EXYNOS5_PA_BTS_MDMA1		0x11D70000
+#define EXYNOS5_PA_BTS_JPEG		0x11F40000
+#define EXYNOS5_PA_BTS_GSCL0		0x13EC0000
+#define EXYNOS5_PA_BTS_GSCL1		0x13ED0000
+#define EXYNOS5_PA_BTS_GSCL2		0x13EE0000
+#define EXYNOS5_PA_BTS_GSCL3		0x13EF0000
+#define EXYNOS5_PA_BTS_DISP10		0x14660000
+#define EXYNOS5_PA_BTS_DISP11		0x14670000
+#define EXYNOS5_PA_BTS_TV0		0x14690000
+#define EXYNOS5_PA_BTS_TV1		0x146A0000
+#define EXYNOS5_PA_BTS_C2C		0x10c90000
+#define EXYNOS5_PA_FBM_DDR_R1		0x10c30000
+#define EXYNOS5_PA_FBM_DDR_R0		0x10dc0000
+#define EXYNOS5_PA_BTS_FIMC_ISP		0x13300000
+#define EXYNOS5_PA_BTS_FIMC_SCALER_C	0x13320000
+#define EXYNOS5_PA_BTS_FIMC_SCALER_P	0x13330000
+#define EXYNOS5_PA_BTS_FIMC_FD		0x13340000
+#define EXYNOS5_PA_BTS_FIMC_ODC		0x13370000
+#define EXYNOS5_PA_BTS_FIMC_DIS0	0x13380000
+#define EXYNOS5_PA_BTS_FIMC_DIS1	0x13390000
+#define EXYNOS5_PA_BTS_FIMC_3DNR	0x133A0000
+
+/* Compatibiltiy Defines */
+
+#define EXYNOS_PA_DWMCI			EXYNOS5_PA_DWMCI
+
+#define EXYNOS_PA_SPI0			EXYNOS5_PA_SPI0
+#define EXYNOS_PA_SPI1			EXYNOS5_PA_SPI1
+#define EXYNOS_PA_SPI2			EXYNOS5_PA_SPI2
+
+#define S5P_PA_HDMI_CEC			EXYNOS5_PA_HDMI_CEC
+
+#define S3C_PA_HSMMC0			EXYNOS5_PA_HSMMC(0)
+#define S3C_PA_HSMMC1			EXYNOS5_PA_HSMMC(1)
+#define S3C_PA_HSMMC2			EXYNOS5_PA_HSMMC(2)
+#define S3C_PA_HSMMC3			EXYNOS5_PA_HSMMC(3)
+
+#define EXYNOS_PA_AUDSS			EXYNOS5_PA_AUDSS
+#define EXYNOS_PA_I2S0			EXYNOS5_PA_I2S0
+#define EXYNOS_PA_I2S1			EXYNOS5_PA_I2S1
+#define EXYNOS_PA_I2S2			EXYNOS5_PA_I2S2
+
+#define EXYNOS_PA_PCM0			EXYNOS5_PA_PCM0
+#define EXYNOS_PA_PCM1			EXYNOS5_PA_PCM1
+#define EXYNOS_PA_PCM2			EXYNOS5_PA_PCM2
+
+#define EXYNOS_PA_AC97			EXYNOS5_PA_AC97
+
+#define EXYNOS_PA_SPDIF			EXYNOS5_PA_SPDIF
+
+#define EXYNOS_PA_FIMC_LITE0		EXYNOS5_PA_FIMC_LITE0
+#define EXYNOS_PA_FIMC_LITE1		EXYNOS5_PA_FIMC_LITE1
+#define EXYNOS_PA_FIMC_LITE2		EXYNOS5_PA_FIMC_LITE2
+
+#define EXYNOS_PA_ROTATOR		EXYNOS5_PA_ROTATOR
+
+#define EXYNOS_PA_C2C		EXYNOS5_PA_C2C
+#define EXYNOS_PA_C2C_CP		EXYNOS5_PA_C2C_CP
+
+#define S3C_PA_IIC			EXYNOS5_PA_IIC(0)
+#define S3C_PA_IIC1			EXYNOS5_PA_IIC(1)
+#define S3C_PA_IIC2			EXYNOS5_PA_IIC(2)
+#define S3C_PA_IIC3			EXYNOS5_PA_IIC(3)
+#define S3C_PA_IIC4			EXYNOS5_PA_IIC(4)
+#define S3C_PA_IIC5			EXYNOS5_PA_IIC(5)
+#define S3C_PA_IIC6			EXYNOS5_PA_IIC(6)
+#define S3C_PA_IIC7			EXYNOS5_PA_IIC(7)
+#define SAMSUNG_PA_ADC			EXYNOS5_PA_ADC
+#define S5P_PA_IIC_HDMIPHY		EXYNOS5_PA_IIC_HDMIPHY
+#define S3C_PA_WDT			EXYNOS5_PA_WATCHDOG
+#define S3C_PA_RTC			EXYNOS5_PA_RTC
+#define S5P_PA_CHIPID			EXYNOS5_PA_CHIPID
+#define S5P_PA_SYSCON			EXYNOS5_PA_SYSCON
+#define S5P_PA_SROMC			EXYNOS5_PA_SROMC
+#define S5P_PA_TIMER			EXYNOS5_PA_TIMER
+#define S5P_PA_HSOTG			EXYNOS5_PA_HSOTG
+#define S5P_PA_MFC			EXYNOS5_PA_MFC
+#define S5P_PA_HSPHY			EXYNOS5_PA_HSPHY
+#define S5P_PA_EHCI			EXYNOS5_PA_EHCI
+#define S5P_PA_OHCI			EXYNOS5_PA_OHCI
+#define S5P_PA_FIMD0			EXYNOS5_PA_FIMD0
+#define S5P_PA_FIMD1			EXYNOS5_PA_FIMD1
+#define S5P_PA_MIXER			EXYNOS5_PA_MIXER
+#define S5P_PA_DP			EXYNOS5_PA_DP
+#define S5P_PA_HDMI			EXYNOS5_PA_HDMI
+#define S5P_PA_SDRAM			EXYNOS5_PA_SDRAM
+#define S5P_PA_FIMG2D			EXYNOS5_PA_FIMG2D
+
+#define S5P_PA_MDMA0			EXYNOS5_PA_NS_MDMA0
+#define S5P_PA_MDMA1			EXYNOS5_PA_NS_MDMA1
+#define S5P_PA_PDMA0			EXYNOS5_PA_PDMA0
+#define S5P_PA_PDMA1			EXYNOS5_PA_PDMA1
+#define S5P_PA_DSIM0			EXYNOS5_PA_DSIM0
+#define S5P_PA_JPEG			EXYNOS4_PA_JPEG
+#define S5P_PA_MIPI_CSIS0		EXYNOS5_PA_MIPI_CSIS0
+#define S5P_PA_MIPI_CSIS1		EXYNOS5_PA_MIPI_CSIS1
+
+#define S5P_PA_ACE			EXYNOS5_PA_ACE
+#define S5P_PA_TMU			EXYNOS5_PA_TMU
+/* UART */
+
+#define S3C_VA_UARTx(x)			(S3C_VA_UART + ((x) * S3C_UART_OFFSET))
+
+#define S3C_PA_UART			EXYNOS5_PA_UART
+
+#define S5P_PA_UART(x)			(S3C_PA_UART + ((x) * S3C_UART_OFFSET))
+#define S5P_PA_UART0			S5P_PA_UART(0)
+#define S5P_PA_UART1			S5P_PA_UART(1)
+#define S5P_PA_UART2			S5P_PA_UART(2)
+#define S5P_PA_UART3			S5P_PA_UART(3)
+#define S5P_PA_UART4			S5P_PA_UART(4)
+
+#define S5P_SZ_HDMI_CEC			SZ_64K
+
+#define S5P_SZ_UART			SZ_256
+
+#define S5P_SZ_MIXER			SZ_64K
+#define S5P_SZ_HDMI			SZ_1M
+#define S5P_SZ_IIC_HDMIPHY		SZ_64K
+
+#endif /* __ASM_ARCH_MAP_EXYNOS5_H */
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
new file mode 100644
index 0000000..5efb7b6
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -0,0 +1,34 @@
+/* linux/arch/arm/mach-exynos/include/mach/map.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * EXYNOS - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_MAP_H
+#define __ASM_ARCH_MAP_H __FILE__
+
+#include <plat/map-base.h>
+
+/*
+ * EXYNOS4 UART offset is 0x10000 but the older S5P SoCs are 0x400.
+ * So need to define it, and here is to avoid redefinition warning.
+ */
+#define S3C_UART_OFFSET			(0x10000)
+
+#include <plat/map-s5p.h>
+
+#if defined(CONFIG_ARCH_EXYNOS4)
+#include "map-exynos4.h"
+#elif defined(CONFIG_ARCH_EXYNOS5)
+#include "map-exynos5.h"
+#else
+#error "ARCH_EXYNOS* is not defined"
+#endif
+
+#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-exynos/include/mach/mdm2.h b/arch/arm/mach-exynos/include/mach/mdm2.h
new file mode 100644
index 0000000..78ca88f
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/mdm2.h
@@ -0,0 +1,23 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _ARCH_ARM_MACH_MSM_MDM2_H
+#define _ARCH_ARM_MACH_MSM_MDM2_H
+
+struct mdm_platform_data {
+	char *mdm_version;
+	int ramdump_delay_ms;
+	struct platform_device *peripheral_platform_device;
+};
+
+#endif
+
diff --git a/arch/arm/mach-exynos/include/mach/media.h b/arch/arm/mach-exynos/include/mach/media.h
new file mode 100644
index 0000000..ce0e53e
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/media.h
@@ -0,0 +1,36 @@
+/* linux/arch/arm/mach-exysnos4/include/mach/media.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Samsung Media device descriptions for exynos4
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef _EXYNOS4_MEDIA_H
+#define _EXYNOS4_MEDIA_H
+
+#ifdef CONFIG_CMA
+#define S5P_MDEV_FIMC0		0
+#define S5P_MDEV_FIMC1		1
+#define S5P_MDEV_FIMC2		2
+#define S5P_MDEV_FIMC3		3
+#define S5P_MDEV_MFC		4
+#define S5P_MDEV_JPEG		5
+#define S5P_MDEV_FIMD		6
+#define S5P_MDEV_FIMG2D		7
+#define S5P_MDEV_SRP		8
+#define S5P_MDEV_TVOUT          9
+
+
+#ifdef CONFIG_MACH_U1
+#define S5P_MDEV_PMEM		10
+#endif
+
+
+#define S5P_RANGE_MFC		SZ_256M
+#endif /* CONFIG_CMA */
+#endif
diff --git a/arch/arm/mach-exynos/include/mach/memory.h b/arch/arm/mach-exynos/include/mach/memory.h
new file mode 100644
index 0000000..9e3d051
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/memory.h
@@ -0,0 +1,30 @@
+/* linux/arch/arm/mach-exynos/include/mach/memory.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS4 - Memory definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H __FILE__
+
+#define PLAT_PHYS_OFFSET		UL(0x40000000)
+#define CONSISTENT_DMA_SIZE		(SZ_8M + SZ_8M + SZ_4M)
+
+#if defined(CONFIG_MACH_SMDKV310) || defined(CONFIG_MACH_SMDK5250)
+#define NR_BANKS			16
+#endif
+
+/* Maximum of 256MiB in one bank */
+#define MAX_PHYSMEM_BITS	32
+#define SECTION_SIZE_BITS	28
+
+/* Required by ION to allocate scatterlist(sglist) with nents > 256 */
+#define ARCH_HAS_SG_CHAIN
+
+#endif /* __ASM_ARCH_MEMORY_H */
diff --git a/arch/arm/mach-exynos/include/mach/midas-lcd.h b/arch/arm/mach-exynos/include/mach/midas-lcd.h
new file mode 100644
index 0000000..1e54994
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/midas-lcd.h
@@ -0,0 +1,34 @@
+/*
+ * midas-lcd.h - lcd Driver of MIDAS Project
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __MIDAS_LCD_H
+#define __MIDAS_LCD_H __FILE__
+
+extern struct s3c_platform_fb fb_platform_data;
+extern struct platform_device mdnie_device;
+#ifdef CONFIG_FB_S5P_S6C1372
+extern struct platform_device lcd_s6c1372;
+#endif
+extern struct ld9040_panel_data s2plus_panel_data;
+extern struct samsung_bl_gpio_info smdk4212_bl_gpio_info;
+extern struct platform_pwm_backlight_data smdk4212_bl_data;
+extern unsigned int lcdtype;
+
+void mipi_fb_init(void);
+
+#endif /* __MIDAS_LCD_H */
diff --git a/arch/arm/mach-exynos/include/mach/midas-power.h b/arch/arm/mach-exynos/include/mach/midas-power.h
new file mode 100644
index 0000000..1742a1f
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/midas-power.h
@@ -0,0 +1,35 @@
+/*
+ * midas-power.h - Power Management of MIDAS Project
+ *
+ *  Copyright (C) 2011 Samsung Electrnoics
+ *  Chiwoong Byun <woong.byun@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __MIDAS_POWER_H
+#define __MIDAS_POWER_H __FILE__
+
+#if defined(CONFIG_MFD_S5M_CORE)
+extern struct s5m_platform_data exynos4_s5m8767_info;
+#else
+extern struct max77686_platform_data exynos4_max77686_info;
+extern struct max8997_platform_data exynos4_max8997_info;
+#endif
+
+void midas_power_init(void);
+void midas_power_set_muic_pdata(void *, int);
+void midas_power_gpio_init(void);
+#endif /* __MIDAS_POWER_H */
diff --git a/arch/arm/mach-exynos/include/mach/midas-sound.h b/arch/arm/mach-exynos/include/mach/midas-sound.h
new file mode 100644
index 0000000..184ec7b
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/midas-sound.h
@@ -0,0 +1,32 @@
+/*
+ * midas-sound.h - Sound Management of MIDAS Project
+ *
+ *  Copyright (C) 2012 Samsung Electrnoics
+ *  JS Park <aitdark.park@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __MIDAS_SOUND_H__
+#define __MIDAS_SOUND_H__ __FILE__
+
+void midas_sound_init(void);
+void midas_snd_set_mclk(bool on, bool forced);
+bool midas_snd_get_mclk(void);
+
+extern struct platform_device vbatt_device;
+extern struct platform_device s3c_device_fm34;
+
+#endif /* __MIDAS_SOUND_H__ */
diff --git a/arch/arm/mach-exynos/include/mach/midas-thermistor.h b/arch/arm/mach-exynos/include/mach/midas-thermistor.h
new file mode 100644
index 0000000..4a29313
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/midas-thermistor.h
@@ -0,0 +1,59 @@
+/*
+ * midas-thermistor.h - thermistor of MIDAS Project
+ *
+ * Copyright (C) 2011 Samsung Electrnoics
+ * SangYoung Son <hello.son@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __MIDAS_THERMISTOR_H
+#define __MIDAS_THERMISTOR_H __FILE__
+
+#include <linux/platform_device.h>
+#include <plat/gpio-cfg.h>
+#include <mach/gpio-midas.h>
+#ifdef CONFIG_STMPE811_ADC
+#include <linux/stmpe811-adc.h>
+#endif
+
+/* class for factory mode */
+extern struct class *sec_class;
+
+/*
+ * struct sec_bat_adc_table_data - adc to temperature table for sec battery
+ * driver
+ * @adc: adc value
+ * @value: value
+ */
+struct adc_table_data {
+	int adc;
+	int value;
+};
+
+#ifdef CONFIG_S3C_ADC
+int convert_adc(int adc_data, int channel);
+#endif
+
+#ifdef CONFIG_STMPE811_ADC
+extern struct stmpe811_platform_data stmpe811_pdata;
+#endif
+
+#ifdef CONFIG_SEC_THERMISTOR
+extern struct platform_device sec_device_thermistor;
+#endif
+
+#endif /* __MIDAS_THERMISTOR_H */
+
diff --git a/arch/arm/mach-exynos/include/mach/midas-tsp.h b/arch/arm/mach-exynos/include/mach/midas-tsp.h
new file mode 100644
index 0000000..4cbee4c
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/midas-tsp.h
@@ -0,0 +1,35 @@
+/*
+ * linux/arch/arm/mach-exynos/include/mach/midas-tsp.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MIDAS_TSP_H
+#define __MIDAS_TSP_H __FILE__
+
+#if defined(CONFIG_TOUCHSCREEN_MELFAS)
+#include <linux/platform_data/mms_ts.h>
+#else
+#include <linux/melfas_ts.h>
+#endif
+
+extern int melfas_power(int on);
+void melfas_set_touch_i2c(void);
+void melfas_set_touch_i2c_to_gpio(void);
+void midas_tsp_set_platdata(struct melfas_tsi_platform_data *pdata);
+void midas_tsp_init(void);
+int is_melfas_vdd_on(void);
+int melfas_mux_fw_flash(bool to_gpios);
+void midas_tsp_set_lcdtype(int lcd_type);
+
+#ifdef CONFIG_CPU_FREQ_GOV_ONDEMAND_FLEXRATE
+extern void midas_tsp_request_qos(void *data);
+#else
+#define midas_tsp_request_qos	NULL
+#endif
+
+#endif /* __MIDAS_TSP_H */
diff --git a/arch/arm/mach-exynos/include/mach/mipi_ddi.h b/arch/arm/mach-exynos/include/mach/mipi_ddi.h
new file mode 100644
index 0000000..17fae16
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/mipi_ddi.h
@@ -0,0 +1,63 @@
+/* linux/arm/arch/mach-exynos/include/mach/mipi_ddi.h
+ *
+ * definitions for DDI based MIPI-DSI.
+ *
+ * Copyright (c) 2009 Samsung Electronics
+ * InKi Dae <inki.dae@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef _MIPI_DDI_H
+#define _MIPI_DDI_H
+
+enum mipi_ddi_interface {
+	RGB_IF = 0x4000,
+	I80_IF = 0x8000,
+	YUV_601 = 0x10000,
+	YUV_656 = 0x20000,
+	MIPI_VIDEO = 0x1000,
+	MIPI_COMMAND = 0x2000,
+};
+
+enum mipi_ddi_panel_select {
+	DDI_MAIN_LCD = 0,
+	DDI_SUB_LCD = 1,
+};
+
+enum mipi_ddi_model {
+	S6DR117 = 0,
+};
+
+enum mipi_ddi_parameter {
+	/* DSIM video interface parameter */
+	DSI_VIRTUAL_CH_ID = 0,
+	DSI_FORMAT = 1,
+	DSI_VIDEO_MODE_SEL = 2,
+};
+
+struct mipi_ddi_spec {
+	unsigned int parameter[3];
+};
+
+struct mipi_ddi_platform_data {
+	unsigned int dsim_base;
+	unsigned int te_irq;
+	unsigned int resume_complete;
+
+	int (*lcd_reset) (void);
+	int (*lcd_power_on) (void *pdev, int enable);
+	int (*backlight_on) (int enable);
+
+	unsigned char (*cmd_write) (unsigned int dsim_base, unsigned int data0,
+		unsigned int data1, unsigned int data2);
+	int (*cmd_read) (unsigned int reg_base, u8 addr, u16 count, u8 *buf);
+
+	unsigned int reset_delay;
+	unsigned int power_on_delay;
+	unsigned int power_off_delay;
+};
+
+#endif /* _MIPI_DDI_H */
diff --git a/arch/arm/mach-exynos/include/mach/naples-tsp.h b/arch/arm/mach-exynos/include/mach/naples-tsp.h
new file mode 100644
index 0000000..f3fa320
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/naples-tsp.h
@@ -0,0 +1,20 @@
+/*
+ * linux/arch/arm/mach-exynos/include/mach/naples-tsp.h
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __NAPLES_TSP_H
+#define __NAPLES_TSP_H __FILE__
+#ifdef CONFIG_TOUCHSCREEN_ATMEL_MXT224
+#include <linux/i2c/mxt224.h>
+#endif
+extern bool is_cable_attached;
+void naples_tsp_init(void);
+void tsp_charger_infom(bool en);
+
+#endif /* __MIDAS_TSP_H */
diff --git a/arch/arm/mach-exynos/include/mach/p10-battery.h b/arch/arm/mach-exynos/include/mach/p10-battery.h
new file mode 100644
index 0000000..09989e5
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/p10-battery.h
@@ -0,0 +1,16 @@
+/*
+ *  arch/arm/mach-exynos/include/mach/p10-battery.h
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __P10_BATTERY_H
+#define __P10_BATTERY_H __FILE__
+
+void p10_battery_init(void);
+
+#endif
diff --git a/arch/arm/mach-exynos/include/mach/p10-input.h b/arch/arm/mach-exynos/include/mach/p10-input.h
new file mode 100644
index 0000000..47d96d7
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/p10-input.h
@@ -0,0 +1,17 @@
+/*
+ *  arch/arm/mach-exynos/include/mach/p10-input.h
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __P10_INPUT_H
+#define __P10_INPUT_H __FILE__
+
+void p10_tsp_init(void);
+void p10_key_init(void);
+
+#endif
diff --git a/arch/arm/mach-exynos/include/mach/p4-input.h b/arch/arm/mach-exynos/include/mach/p4-input.h
new file mode 100644
index 0000000..b7ecddb
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/p4-input.h
@@ -0,0 +1,21 @@
+/*
+ *  arch/arm/mach-exynos/include/mach/p4-input.h
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __P4_INPUT_H
+#define __P4_INPUT_H __FILE__
+
+void p4_tsp_init(u32 system_rev);
+void p4_wacom_init(void);
+void p4_key_init(void);
+#if defined(CONFIG_TOUCHSCREEN_SYNAPTICS_S7301)
+extern void synaptics_ts_charger_infom(bool en);
+#endif
+
+#endif /* __P4_INPUT_H */
diff --git a/arch/arm/mach-exynos/include/mach/p4note-jack.h b/arch/arm/mach-exynos/include/mach/p4note-jack.h
new file mode 100644
index 0000000..c6a343c
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/p4note-jack.h
@@ -0,0 +1,25 @@
+/*
+ * p4note-jack.h - Jack Management of P4NOTE Project
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __P4NOTE_JACK_H__
+#define __P4NOTE_JACK_H__ __FILE__
+
+void p4note_jack_init(void);
+void sec_set_jack_micbias(bool);
+
+#endif /* __P4NOTE_JACK_H__ */
diff --git a/arch/arm/mach-exynos/include/mach/pm-core.h b/arch/arm/mach-exynos/include/mach/pm-core.h
new file mode 100644
index 0000000..ef84c7c
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/pm-core.h
@@ -0,0 +1,67 @@
+/* linux/arch/arm/mach-exynos/include/mach/pm-core.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Based on arch/arm/mach-s3c2410/include/mach/pm-core.h,
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * EXYNOS4210 - PM core support for arch/arm/plat-s5p/pm.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <mach/regs-pmu.h>
+#include <mach/regs-gpio.h>
+
+static inline void s3c_pm_debug_init_uart(void)
+{
+	/* nothing here yet */
+}
+
+static inline void s3c_pm_arch_prepare_irqs(void)
+{
+#if defined(CONFIG_EXYNOS4212) || defined(CONFIG_EXYNOS4412)
+       /* Mask externel GIC and GPS_ALIVE wakeup source */
+       s3c_irqwake_intmask |= 0x3BF0000;
+#endif
+	__raw_writel((s3c_irqwake_intmask & S5P_WAKEUP_MASK_BIT), S5P_WAKEUP_MASK);
+	__raw_writel(s3c_irqwake_eintmask, S5P_EINT_WAKEUP_MASK);
+}
+
+static inline void s3c_pm_arch_stop_clocks(void)
+{
+	/* nothing here yet */
+}
+
+static inline void s3c_pm_arch_show_resume_irqs(void)
+{
+#if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_CPU_EXYNOS4412)\
+	|| defined(CONFIG_CPU_EXYNOS5250)
+	pr_info("WAKEUP_STAT: 0x%x\n", __raw_readl(S5P_WAKEUP_STAT));
+	pr_info("WAKEUP_INTx_PEND: 0x%x, 0x%x, 0x%x, 0x%x\n",
+				__raw_readl(S5P_EINT_PEND(0)),
+				__raw_readl(S5P_EINT_PEND(1)),
+				__raw_readl(S5P_EINT_PEND(2)),
+				__raw_readl(S5P_EINT_PEND(3)));
+#endif
+}
+
+static inline void s3c_pm_arch_update_uart(void __iomem *regs,
+					   struct pm_uart_save *save)
+{
+	/* nothing here yet */
+}
+
+static inline void s3c_pm_restored_gpios(void)
+{
+	/* nothing here yet */
+}
+
+static inline void s3c_pm_saved_gpios(void)
+{
+	/* nothing here yet */
+}
diff --git a/arch/arm/mach-exynos/include/mach/pmu.h b/arch/arm/mach-exynos/include/mach/pmu.h
new file mode 100644
index 0000000..d475dd5
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/pmu.h
@@ -0,0 +1,117 @@
+/* linux/arch/arm/mach-exynos/include/mach/pmu.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * EXYNOS4210 - PMU support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_PMU_H
+#define __ASM_ARCH_PMU_H __FILE__
+
+#include <linux/cpu.h>
+#include <linux/io.h>
+#include <mach/regs-pmu.h>
+
+static inline void exynos4_reset_assert_ctrl(unsigned int on)
+{
+	unsigned int i;
+	unsigned int core_option;
+
+	for (i = 0; i < num_possible_cpus(); i++) {
+		core_option = __raw_readl(S5P_ARM_CORE_OPTION(i));
+		core_option &= ~S5P_USE_DELAYED_RESET_ASSERTION;
+		core_option |= (on << S5P_USE_DELAYED_RESET_OFFSET);
+#if !defined(CONFIG_CPU_EXYNOS4210)
+		pr_debug("%s %p %08x\n", __func__,
+		       S5P_ARM_CORE_OPTION(i), core_option);
+#endif
+		__raw_writel(core_option, S5P_ARM_CORE_OPTION(i));
+	}
+}
+
+static inline int exynos4_is_c2c_use(void)
+{
+	unsigned int ret;
+
+	ret = __raw_readl(S5P_C2C_CTRL);
+
+	return ret;
+}
+
+enum sys_powerdown {
+	SYS_AFTR,
+	SYS_LPA,
+	SYS_SLEEP,
+	NUM_SYS_POWERDOWN,
+};
+
+struct exynos4_pmu_conf {
+	void __iomem *reg;
+	unsigned long val[NUM_SYS_POWERDOWN];
+};
+
+enum c2c_pwr_mode {
+	MIN_LATENCY,
+	SHORT_LATENCY,
+	MAX_LATENCY,
+};
+
+#if defined(CONFIG_ARCH_EXYNOS4)
+enum xclkout_select {
+	XCLKOUT_CMU_DMC = 0x0,
+	XCLKOUT_CMU_TOP = 0x1,
+	XCLKOUT_CMU_LEFTBUS = 0x2,
+	XCLKOUT_CMU_RIGHTBUS = 0x3,
+	XCLKOUT_CMU_CPU = 0x4,
+	XCLKOUT_CMU_ISP = 0x5, /* Not support at EXYNOS4210 */
+	XCLKOUT_XXTI = 0x8,
+	XCLKOUT_XUSBXTI = 0x9,
+	XCLKOUT_RTC_TICCLK = 0xC,
+	XCLKOUT_RTCCLK = 0xD,
+	XCLKOUT_CLKOUT_DEBUG = 0xE, /* Not support at EXYNOS4210 */
+};
+#elif defined(CONFIG_CPU_EXYNOS5250)
+enum xclkout_select {
+	XCLKOUT_DEBUG = 0x0,
+	XCLKOUT_CMU_CDREX = 0x1,
+	XCLKOUT_CMU_CORE = 0x2,
+	XCLKOUT_CMU_ISP = 0x3,
+	XCLKOUT_CMU_LEX = 0x4,
+	XCLKOUT_CMU_MIX = 0x5,
+	XCLKOUT_CMU_RIX = 0x6,
+	XCLKOUT_CMU_TOP = 0x7,
+	XCLKOUT_CMU_CPU = 0x8,
+	XCLKOUT_CMU_ACP = 0x9,
+	XCLKOUT_XXTI = 0x10,
+	XCLKOUT_XUSBXTI = 0x11,
+	XCLKOUT_TICCLK = 0x12,
+	XCLKOUT_RTCCLK = 0x13,
+};
+#endif
+
+struct exynos4_c2c_pmu_conf {
+	void __iomem *reg;
+	unsigned long val;
+};
+
+/* external function for exynos4 series */
+extern void exynos4_sys_powerdown_conf(enum sys_powerdown mode);
+extern int exynos4_enter_lp(unsigned long *saveblk, long);
+extern void exynos4_idle_resume(void);
+extern void exynos4_c2c_request_pwr_mode(enum c2c_pwr_mode mode);
+extern void exynos4_sys_powerdown_xusbxti_control(unsigned int enable);
+extern void exynos4_pmu_xclkout_set(unsigned int enable, enum xclkout_select source);
+
+/* external function for exynos5 series */
+extern void exynos5_sys_powerdown_conf(enum sys_powerdown mode);
+extern int exynos5_enter_lp(unsigned long *saveblk, long);
+extern void exynos5_idle_resume(void);
+extern void exynos5_sys_powerdown_xxti_control(unsigned int enable);
+extern void exynos5_pmu_xclkout_set(unsigned int enable, enum xclkout_select source);
+
+#endif /* __ASM_ARCH_PMU_H */
diff --git a/arch/arm/mach-exynos/include/mach/ppmu.h b/arch/arm/mach-exynos/include/mach/ppmu.h
new file mode 100644
index 0000000..684ce5c
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/ppmu.h
@@ -0,0 +1,122 @@
+/* linux/arch/arm/mach-exynos/include/mach/ppmu.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * EXYNOS4 - PPMU support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_PPMU_H
+#define __ASM_ARCH_PPMU_H __FILE__
+
+#define NUMBER_OF_COUNTER	4
+
+#define PPMU_CNTENS	0x10
+#define PPMU_CNTENC	0x20
+#define PPMU_INTENS	0x30
+#define PPMU_INTENC	0x40
+#define PPMU_FLAG	0x50
+
+#define PPMU_CCNT		0x100
+#define PPMU_PMCNT0		0x110
+#define PPMU_PMCNT_OFFSET	0x10
+
+#define PPMU_BEVT0SEL		0x1000
+#define PPMU_BEVTSEL_OFFSET	0x100
+#define PPMU_CNT_RESET		0x1800
+
+#define DEVT0_SEL	0x1000
+#define DEVT0_ID	0x1010
+#define DEVT0_IDMSK	0x1014
+#define DEVT_ID_OFFSET	0x100
+
+#define DEFAULT_WEIGHT	1
+
+#define MAX_CCNT	100
+
+/* For flags */
+#define VIDEO_DOMAIN	0x00000001
+#define AUDIO_DOMAIN	0x00000002
+#define ALL_DOMAIN	0xffffffff
+
+/* For event */
+#define RD_DATA_COUNT		0x00000005
+#define WR_DATA_COUNT		0x00000006
+#define RDWR_DATA_COUNT		0x00000007
+
+#define PMCNT_OFFSET(i)		(PPMU_PMCNT0 + (PPMU_PMCNT_OFFSET * i))
+
+enum ppmu_counter {
+	PPMU_PMNCNT0,
+	PPMU_PMCCNT1,
+	PPMU_PMNCNT2,
+	PPMU_PMNCNT3,
+	PPMU_PMNCNT_MAX,
+};
+
+enum ppmu_ch {
+	DMC0,
+	DMC1,
+};
+
+enum ppmu_type {
+	PPMU_MIF,
+	PPMU_INT,
+	PPMU_TYPE_END,
+};
+
+enum exynos4_ppmu {
+	PPMU_DMC0,
+	PPMU_DMC1,
+	PPMU_CPU,
+#ifdef CONFIG_ARCH_EXYNOS5
+	PPMU_DDR_C,
+	PPMU_DDR_R1,
+	PPMU_DDR_L,
+	PPMU_RIGHT0_BUS,
+#endif
+	PPMU_END,
+};
+
+extern unsigned long long ppmu_load[PPMU_END];
+extern unsigned long long ppmu_load_detail[2][PPMU_END];
+
+struct exynos4_ppmu_hw {
+	struct list_head node;
+	void __iomem *hw_base;
+	unsigned int ccnt;
+	unsigned int event[NUMBER_OF_COUNTER];
+	unsigned int weight;
+	int usage;
+	int id;
+	unsigned int flags;
+	struct device *dev;
+	unsigned int count[NUMBER_OF_COUNTER];
+};
+
+void exynos4_ppc_reset(struct exynos4_ppmu_hw *ppmu);
+void exynos4_ppc_start(struct exynos4_ppmu_hw *ppmu);
+void exynos4_ppc_stop(struct exynos4_ppmu_hw *ppmu);
+void exynos4_ppc_setevent(struct exynos4_ppmu_hw *ppmu,
+				  unsigned int evt_num);
+unsigned long long exynos4_ppc_update(struct exynos4_ppmu_hw *ppmu);
+
+void exynos4_ppmu_reset(struct exynos4_ppmu_hw *ppmu);
+void exynos4_ppmu_start(struct exynos4_ppmu_hw *ppmu);
+void exynos4_ppmu_stop(struct exynos4_ppmu_hw *ppmu);
+void exynos4_ppmu_setevent(struct exynos4_ppmu_hw *ppmu,
+				   unsigned int evt_num);
+unsigned long long exynos4_ppmu_update(struct exynos4_ppmu_hw *ppmu, int ch);
+
+void ppmu_init(struct exynos4_ppmu_hw *ppmu, struct device *dev);
+void ppmu_start(struct device *dev);
+void ppmu_update(struct device *dev, int ch);
+void ppmu_reset(struct device *dev);
+
+extern struct exynos4_ppmu_hw exynos_ppmu[];
+#endif /* __ASM_ARCH_PPMU_H */
+
diff --git a/arch/arm/mach-exynos/include/mach/pwm-clock.h b/arch/arm/mach-exynos/include/mach/pwm-clock.h
new file mode 100644
index 0000000..5e06b94
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/pwm-clock.h
@@ -0,0 +1,70 @@
+/* linux/arch/arm/mach-exynos/include/mach/pwm-clock.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
+ *
+ * EXYNOS4 - pwm clock and timer support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_PWMCLK_H
+#define __ASM_ARCH_PWMCLK_H __FILE__
+
+/**
+ * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
+ * @tcfg: The timer TCFG1 register bits shifted down to 0.
+ *
+ * Return true if the given configuration from TCFG1 is a TCLK instead
+ * any of the TDIV clocks.
+ */
+static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
+{
+	return tcfg == S3C64XX_TCFG1_MUX_TCLK;
+}
+
+/**
+ * tcfg_to_divisor() - convert tcfg1 setting to a divisor
+ * @tcfg1: The tcfg1 setting, shifted down.
+ *
+ * Get the divisor value for the given tcfg1 setting. We assume the
+ * caller has already checked to see if this is not a TCLK source.
+ */
+static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
+{
+	return 1 << tcfg1;
+}
+
+/**
+ * pwm_tdiv_has_div1() - does the tdiv setting have a /1
+ *
+ * Return true if we have a /1 in the tdiv setting.
+ */
+static inline unsigned int pwm_tdiv_has_div1(void)
+{
+	return 1;
+}
+
+/**
+ * pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
+ * @div: The divisor to calculate the bit information for.
+ *
+ * Turn a divisor into the necessary bit field for TCFG1.
+ */
+static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
+{
+	return ilog2(div);
+}
+
+#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK
+
+#endif /* __ASM_ARCH_PWMCLK_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-audss.h b/arch/arm/mach-exynos/include/mach/regs-audss.h
new file mode 100644
index 0000000..a480753
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/regs-audss.h
@@ -0,0 +1,46 @@
+/* arch/arm/mach-exynos/include/mach/regs-audss.h
+ *
+ * Copyright 2011 Samsung Electronics
+ *
+ * EXYNOS4 Audio SubSystem clock register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __PLAT_REGS_AUDSS_H
+#define __PLAT_REGS_AUDSS_H __FILE__
+
+#define EXYNOS4_AUDSSREG(x)			(S5P_VA_AUDSS + (x))
+
+#define S5P_CLKSRC_AUDSS		EXYNOS4_AUDSSREG(0x0)
+#define S5P_CLKDIV_AUDSS		EXYNOS4_AUDSSREG(0x4)
+#define S5P_CLKGATE_AUDSS		EXYNOS4_AUDSSREG(0x8)
+
+/* CLKSRC0 */
+#define S5P_AUDSS_CLKSRC_MAIN_MASK	(0x1<<0)
+#define S5P_AUDSS_CLKSRC_MAIN_SHIFT	(0)
+#define S5P_AUDSS_CLKSRC_I2SCLK_MASK	(0x3<<2)
+#define S5P_AUDSS_CLKSRC_I2SCLK_SHIFT	(2)
+
+/* CLKDIV0 */
+#define S5P_AUDSS_CLKDIV_RP_MASK	(0xf<<0)
+#define S5P_AUDSS_CLKDIV_RP_SHIFT	(0)
+#define S5P_AUDSS_CLKDIV_BUSCLK_MASK	(0xf<<4)
+#define S5P_AUDSS_CLKDIV_BUSCLK_SHIFT	(4)
+#define S5P_AUDSS_CLKDIV_I2SCLK_MASK	(0xf<<8)
+#define S5P_AUDSS_CLKDIV_I2SCLK_SHIFT	(8)
+
+/* IP Clock Gate 0 Registers */
+#define S5P_AUDSS_CLKGATE_RP		(1<<0)
+#define S5P_AUDSS_CLKGATE_INTMEM	(1<<1)
+#define S5P_AUDSS_CLKGATE_I2SBUS	(1<<2)
+#define S5P_AUDSS_CLKGATE_I2SSPECIAL	(1<<3)
+#define S5P_AUDSS_CLKGATE_PCMBUS	(1<<4)
+#define S5P_AUDSS_CLKGATE_PCMSPECIAL	(1<<5)
+#define S5P_AUDSS_CLKGATE_GPIO		(1<<6)
+#define S5P_AUDSS_CLKGATE_UART		(1<<7)
+#define S5P_AUDSS_CLKGATE_TIMER		(1<<8)
+
+#endif /* _PLAT_REGS_AUDSS_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-c2c.h b/arch/arm/mach-exynos/include/mach/regs-c2c.h
new file mode 100644
index 0000000..14b35d2
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/regs-c2c.h
@@ -0,0 +1,73 @@
+/* linux/arch/arm/mach-exynos/include/mach/regs-c2c.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * Register definition file for Samsung C2C
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARM_REGS_S5P_C2C_H
+#define __ASM_ARM_REGS_S5P_C2C_H
+
+#include <plat/map-base.h>
+
+/***************************************************************/
+/* C2C Registers part				*/
+/***************************************************************/
+#define EXYNOS_C2C_REVISION		0x0
+#define EXYNOS_C2C_SYSCONFIG		0x4
+#define EXYNOS_C2C_SYSSTATUS		0x8
+#define EXYNOS_C2C_PORTCONFIG		0xc
+#define EXYNOS_C2C_MIRRORMODE		0x10
+#define EXYNOS_C2C_IRQ_RAW_STAT0	0x14
+#define EXYNOS_C2C_IRQ_RAW_STAT1	0x18
+#define EXYNOS_C2C_IRQ_EN_STAT0	0x1c
+#define EXYNOS_C2C_IRQ_EN_STAT1	0x20
+#define EXYNOS_C2C_IRQ_EN_SET0		0x24
+#define EXYNOS_C2C_IRQ_EN_SET1		0x28
+#define EXYNOS_C2C_IRQ_EN_CLEAR0	0x2c
+#define EXYNOS_C2C_IRQ_EN_CLEAR1	0x30
+#define EXYNOS_C2C_IRQ_EOI		0x34
+
+#define EXYNOS_C2C_FCLK_FREQ		0x40
+#define EXYNOS_C2C_RX_MAX_FREQ		0x44
+#define EXYNOS_C2C_TX_MAX_FREQ		0x48
+#define EXYNOS_C2C_RX_MAX_FREQ_ACK	0x4c
+#define EXYNOS_C2C_WAKE_REQ		0x50
+#define EXYNOS_C2C_WAKE_ACK		0x54
+#define EXYNOS_C2C_STANDBY		0x60
+#define EXYNOS_C2C_STANDBY_IN		0x64
+#define EXYNOS_C2C_WAIT		0x68
+#define EXYNOS_C2C_GENI_CONTROL	0x70
+#define EXYNOS_C2C_GENI_MASK		0x74
+#define EXYNOS_C2C_GENO_STATUS		0x80
+
+#define EXYNOS_C2C_GENO_INT		0x84
+#define EXYNOS_C2C_GENO_LEVEL		0x88
+
+/***************************************************************/
+/* C2C Bit definition part					*/
+/***************************************************************/
+/* SYSREG Bit definition */
+#define C2C_SYSREG_CG		(31) /* C2C Clock Gating [31] */
+#define C2C_SYSREG_MO		(30) /* Master On [30] */
+#define C2C_SYSREG_FCLK		(20) /* Default Functional Clock Freq [29:20] */
+#define C2C_SYSREG_TXW		(18) /* Default Tx Width [19:18] */
+#define C2C_SYSREG_RXW		(16) /* Default Rx Width [17:16] */
+#define C2C_SYSREG_RST		(15) /* Reset [15] */
+#define C2C_SYSREG_MD		(14) /* Master On [14] */
+#define C2C_SYSREG_RTRST	(13) /* Reset retention registers [13] */
+#define C2C_SYSREG_BASE_ADDR	(3)  /* DRAM Base Address [12:3] */
+#define C2C_SYSREG_DRAM_SIZE	(0)  /* DRAM Size [2:0] */
+
+#define C2C_GENIO_LATENCY_INT	(26)
+#define C2C_GENIO_OPP_INT	(27)
+#define C2C_GENIO_OPP_MODE0	(28)
+#define C2C_GENIO_OPP_MODE1	(29)
+#define C2C_GENIO_LATENCY0	(30)
+#define C2C_GENIO_LATENCY1	(31)
+#endif /* __ASM_ARM_REGS_S5P_C2C_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-cec.h b/arch/arm/mach-exynos/include/mach/regs-cec.h
new file mode 100644
index 0000000..1b5ed09
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/regs-cec.h
@@ -0,0 +1,93 @@
+/* linux/arch/arm/mach-exynos/include/mach/regs-cec.h
+ *
+ * Copyright (c) 2010 Samsung Electronics
+ *		http://www.samsung.com/
+ *
+ * CEC register header file for Samsung TVOUT driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_REGS_CEC_H
+#define __ARCH_ARM_REGS_CEC_H
+
+/*
+ * Register part
+ */
+#define S5P_CES_STATUS_0			(0x0000)
+#define S5P_CES_STATUS_1			(0x0004)
+#define S5P_CES_STATUS_2			(0x0008)
+#define S5P_CES_STATUS_3			(0x000C)
+#define S5P_CES_IRQ_MASK			(0x0010)
+#define S5P_CES_IRQ_CLEAR			(0x0014)
+#define S5P_CES_LOGIC_ADDR			(0x0020)
+#define S5P_CES_DIVISOR_0			(0x0030)
+#define S5P_CES_DIVISOR_1			(0x0034)
+#define S5P_CES_DIVISOR_2			(0x0038)
+#define S5P_CES_DIVISOR_3			(0x003C)
+
+#define S5P_CES_TX_CTRL				(0x0040)
+#define S5P_CES_TX_BYTES			(0x0044)
+#define S5P_CES_TX_STAT0			(0x0060)
+#define S5P_CES_TX_STAT1			(0x0064)
+#define S5P_CES_TX_BUFF0			(0x0080)
+#define S5P_CES_TX_BUFF1			(0x0084)
+#define S5P_CES_TX_BUFF2			(0x0088)
+#define S5P_CES_TX_BUFF3			(0x008C)
+#define S5P_CES_TX_BUFF4			(0x0090)
+#define S5P_CES_TX_BUFF5			(0x0094)
+#define S5P_CES_TX_BUFF6			(0x0098)
+#define S5P_CES_TX_BUFF7			(0x009C)
+#define S5P_CES_TX_BUFF8			(0x00A0)
+#define S5P_CES_TX_BUFF9			(0x00A4)
+#define S5P_CES_TX_BUFF10			(0x00A8)
+#define S5P_CES_TX_BUFF11			(0x00AC)
+#define S5P_CES_TX_BUFF12			(0x00B0)
+#define S5P_CES_TX_BUFF13			(0x00B4)
+#define S5P_CES_TX_BUFF14			(0x00B8)
+#define S5P_CES_TX_BUFF15			(0x00BC)
+
+#define S5P_CES_RX_CTRL				(0x00C0)
+#define S5P_CES_RX_STAT0			(0x00E0)
+#define S5P_CES_RX_STAT1			(0x00E4)
+#define S5P_CES_RX_BUFF0			(0x0100)
+#define S5P_CES_RX_BUFF1			(0x0104)
+#define S5P_CES_RX_BUFF2			(0x0108)
+#define S5P_CES_RX_BUFF3			(0x010C)
+#define S5P_CES_RX_BUFF4			(0x0110)
+#define S5P_CES_RX_BUFF5			(0x0114)
+#define S5P_CES_RX_BUFF6			(0x0118)
+#define S5P_CES_RX_BUFF7			(0x011C)
+#define S5P_CES_RX_BUFF8			(0x0120)
+#define S5P_CES_RX_BUFF9			(0x0124)
+#define S5P_CES_RX_BUFF10			(0x0128)
+#define S5P_CES_RX_BUFF11			(0x012C)
+#define S5P_CES_RX_BUFF12			(0x0130)
+#define S5P_CES_RX_BUFF13			(0x0134)
+#define S5P_CES_RX_BUFF14			(0x0138)
+#define S5P_CES_RX_BUFF15			(0x013C)
+
+#define S5P_CES_RX_FILTER_CTRL			(0x0180)
+#define S5P_CES_RX_FILTER_TH			(0x0184)
+
+/*
+ * Bit definition part
+ */
+#define S5P_CES_IRQ_TX_DONE			(1<<0)
+#define S5P_CES_IRQ_TX_ERROR			(1<<1)
+#define S5P_CES_IRQ_RX_DONE			(1<<4)
+#define S5P_CES_IRQ_RX_ERROR			(1<<5)
+
+#define S5P_CES_TX_CTRL_START			(1<<0)
+#define S5P_CES_TX_CTRL_BCAST			(1<<1)
+#define S5P_CES_TX_CTRL_RETRY			(0x04<<4)
+#define S5P_CES_TX_CTRL_RESET			(1<<7)
+
+#define S5P_CES_RX_CTRL_ENABLE			(1<<0)
+#define S5P_CES_RX_CTRL_RESET			(1<<7)
+
+#define S5P_CES_LOGIC_ADDR_MASK			(0xF)
+
+#endif	/* __ARCH_ARM_REGS_CEC_H	*/
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
new file mode 100644
index 0000000..a0aab7c
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -0,0 +1,699 @@
+/* linux/arch/arm/mach-exynos/include/mach/regs-clock.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS - Clock register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_CLOCK_H
+#define __ASM_ARCH_REGS_CLOCK_H __FILE__
+
+#include <mach/map.h>
+
+/* For EXYNOS4 */
+#define EXYNOS_CLKREG(x)		(S5P_VA_CMU + (x))
+
+#define EXYNOS4_CLKSRC_LEFTBUS		EXYNOS_CLKREG(0x04200)
+#define EXYNOS4_CLKMUX_STAT_LEFTBUS	EXYNOS_CLKREG(0x04400)
+#define EXYNOS4_CLKDIV_LEFTBUS		EXYNOS_CLKREG(0x04500)
+#define EXYNOS4_CLKDIV_STAT_LEFTBUS	EXYNOS_CLKREG(0x04600)
+#define EXYNOS4_CLKGATE_IP_LEFTBUS	EXYNOS_CLKREG(0x04800)
+#define EXYNOS4_CLKOUT_CMU_LEFTBUS	EXYNOS_CLKREG(0x04A00)
+
+#define EXYNOS4_CLKSRC_RIGHTBUS		EXYNOS_CLKREG(0x08200)
+#define EXYNOS4_CLKMUX_STAT_RIGHTBUS	EXYNOS_CLKREG(0x08400)
+#define EXYNOS4_CLKDIV_RIGHTBUS		EXYNOS_CLKREG(0x08500)
+#define EXYNOS4_CLKDIV_STAT_RIGHTBUS	EXYNOS_CLKREG(0x08600)
+#define EXYNOS4_CLKGATE_IP_RIGHTBUS	EXYNOS_CLKREG(0x08800)
+#define EXYNOS4_CLKOUT_CMU_RIGHTBUS	EXYNOS_CLKREG(0x08A00)
+
+#define EXYNOS4_EPLL_LOCK		EXYNOS_CLKREG(0x0C010)
+#define EXYNOS4_VPLL_LOCK		EXYNOS_CLKREG(0x0C020)
+
+#define EXYNOS4_EPLL_CON0		EXYNOS_CLKREG(0x0C110)
+#define EXYNOS4_EPLL_CON1		EXYNOS_CLKREG(0x0C114)
+#define EXYNOS4_VPLL_CON0		EXYNOS_CLKREG(0x0C120)
+#define EXYNOS4_VPLL_CON1		EXYNOS_CLKREG(0x0C124)
+
+#define EXYNOS4_CLKSRC_TOP0		EXYNOS_CLKREG(0x0C210)
+#define EXYNOS4_CLKSRC_TOP1		EXYNOS_CLKREG(0x0C214)
+#define EXYNOS4_CLKSRC_CAM		EXYNOS_CLKREG(0x0C220)
+#define EXYNOS4_CLKSRC_TV		EXYNOS_CLKREG(0x0C224)
+#define EXYNOS4_CLKSRC_MFC		EXYNOS_CLKREG(0x0C228)
+#define EXYNOS4_CLKSRC_G3D		EXYNOS_CLKREG(0x0C22C)
+#define EXYNOS4_CLKSRC_IMAGE		EXYNOS_CLKREG(0x0C230)
+#define EXYNOS4_CLKSRC_LCD0		EXYNOS_CLKREG(0x0C234)
+#define EXYNOS4_CLKSRC_MAUDIO		EXYNOS_CLKREG(0x0C23C)
+#define EXYNOS4_CLKSRC_FSYS		EXYNOS_CLKREG(0x0C240)
+#define EXYNOS4_CLKSRC_PERIL0		EXYNOS_CLKREG(0x0C250)
+#define EXYNOS4_CLKSRC_PERIL1		EXYNOS_CLKREG(0x0C254)
+
+#define EXYNOS4_CLKSRC_MASK_TOP		EXYNOS_CLKREG(0x0C310)
+#define EXYNOS4_CLKSRC_MASK_CAM		EXYNOS_CLKREG(0x0C320)
+#define EXYNOS4_CLKSRC_MASK_TV		EXYNOS_CLKREG(0x0C324)
+#define EXYNOS4_CLKSRC_MASK_LCD0	EXYNOS_CLKREG(0x0C334)
+#define EXYNOS4_CLKSRC_MASK_MAUDIO	EXYNOS_CLKREG(0x0C33C)
+#define EXYNOS4_CLKSRC_MASK_FSYS	EXYNOS_CLKREG(0x0C340)
+#define EXYNOS4_CLKSRC_MASK_PERIL0	EXYNOS_CLKREG(0x0C350)
+#define EXYNOS4_CLKSRC_MASK_PERIL1	EXYNOS_CLKREG(0x0C354)
+
+#define EXYNOS4_CLKDIV_TOP		EXYNOS_CLKREG(0x0C510)
+#define EXYNOS4_CLKDIV_CAM		EXYNOS_CLKREG(0x0C520)
+#define EXYNOS4_CLKDIV_TV		EXYNOS_CLKREG(0x0C524)
+#define EXYNOS4_CLKDIV_MFC		EXYNOS_CLKREG(0x0C528)
+#define EXYNOS4_CLKDIV_G3D		EXYNOS_CLKREG(0x0C52C)
+#define EXYNOS4_CLKDIV_IMAGE		EXYNOS_CLKREG(0x0C530)
+#define EXYNOS4_CLKDIV_LCD0		EXYNOS_CLKREG(0x0C534)
+#define EXYNOS4_CLKDIV_ISP		EXYNOS_CLKREG(0x0C538)
+#define EXYNOS4_CLKDIV_MAUDIO		EXYNOS_CLKREG(0x0C53C)
+#define EXYNOS4_CLKDIV_FSYS0		EXYNOS_CLKREG(0x0C540)
+#define EXYNOS4_CLKDIV_FSYS1		EXYNOS_CLKREG(0x0C544)
+#define EXYNOS4_CLKDIV_FSYS2		EXYNOS_CLKREG(0x0C548)
+#define EXYNOS4_CLKDIV_FSYS3		EXYNOS_CLKREG(0x0C54C)
+#define EXYNOS4_CLKDIV_PERIL0		EXYNOS_CLKREG(0x0C550)
+#define EXYNOS4_CLKDIV_PERIL1		EXYNOS_CLKREG(0x0C554)
+#define EXYNOS4_CLKDIV_PERIL2		EXYNOS_CLKREG(0x0C558)
+#define EXYNOS4_CLKDIV_PERIL3		EXYNOS_CLKREG(0x0C55C)
+#define EXYNOS4_CLKDIV_PERIL4		EXYNOS_CLKREG(0x0C560)
+#define EXYNOS4_CLKDIV_PERIL5		EXYNOS_CLKREG(0x0C564)
+
+#define EXYNOS4_CLKDIV_STAT_TOP		EXYNOS_CLKREG(0x0C610)
+#define EXYNOS4_CLKDIV_STAT_CAM		EXYNOS_CLKREG(0x0C620)
+#define EXYNOS4_CLKDIV_STAT_MFC		EXYNOS_CLKREG(0x0C628)
+#define EXYNOS4_CLKDIV_STAT_IMAGE		EXYNOS_CLKREG(0x0C630)
+
+#define EXYNOS4_CLKDIV_STAT_FSYS3	EXYNOS_CLKREG(0x0C64C)
+
+#define EXYNOS4_CLKGATE_SCLKCAM		EXYNOS_CLKREG(0x0C820)
+#define EXYNOS4_CLKGATE_IP_CAM		EXYNOS_CLKREG(0x0C920)
+#define EXYNOS4_CLKGATE_IP_TV		EXYNOS_CLKREG(0x0C924)
+#define EXYNOS4_CLKGATE_IP_MFC		EXYNOS_CLKREG(0x0C928)
+#define EXYNOS4_CLKGATE_IP_G3D		EXYNOS_CLKREG(0x0C92C)
+#define EXYNOS4_CLKGATE_IP_IMAGE	(soc_is_exynos4210() ? \
+					EXYNOS_CLKREG(0x0C930) : \
+					EXYNOS_CLKREG(0x04930))
+#define EXYNOS4_CLKGATE_IP_IMAGE_4210	EXYNOS_CLKREG(0x0C930)
+#define EXYNOS4_CLKGATE_IP_IMAGE_4212	EXYNOS_CLKREG(0x04930)
+#define EXYNOS4_CLKGATE_IP_LCD0		EXYNOS_CLKREG(0x0C934)
+#define EXYNOS4_CLKGATE_IP_FSYS		EXYNOS_CLKREG(0x0C940)
+#define EXYNOS4_CLKGATE_IP_GPS		EXYNOS_CLKREG(0x0C94C)
+#define EXYNOS4_CLKGATE_IP_PERIL	EXYNOS_CLKREG(0x0C950)
+#define EXYNOS4_CLKGATE_IP_PERIR	(soc_is_exynos4210() ? \
+					EXYNOS_CLKREG(0x0C960) : \
+					EXYNOS_CLKREG(0x08960))
+#define EXYNOS4_CLKGATE_IP_PERIR_4210	EXYNOS_CLKREG(0x0C960)
+#define EXYNOS4_CLKGATE_IP_PERIR_4212	EXYNOS_CLKREG(0x08960)
+#define EXYNOS4_CLKGATE_BLOCK		EXYNOS_CLKREG(0x0C970)
+#define EXYNOS4_CLKOUT_CMU_TOP		EXYNOS_CLKREG(0x0CA00)
+
+#define EXYNOS4_CLKSRC_MASK_DMC		EXYNOS_CLKREG(0x10300)
+#define EXYNOS4_CLKSRC_DMC		EXYNOS_CLKREG(0x10200)
+
+#define EXYNOS4_CLKSRC_DMC_MASK		(0xF1111)
+
+#define EXYNOS4_CLKDIV_DMC0		EXYNOS_CLKREG(0x10500)
+#define EXYNOS4_CLKDIV_DMC1		EXYNOS_CLKREG(0x10504)
+#define EXYNOS4_CLKDIV_STAT_DMC0	EXYNOS_CLKREG(0x10600)
+#define EXYNOS4_CLKDIV_STAT_DMC1	EXYNOS_CLKREG(0x10604)
+#define EXYNOS4_CLKGATE_IP_DMC		EXYNOS_CLKREG(0x10900)
+#define EXYNOS4_CLKOUT_CMU_DMC		EXYNOS_CLKREG(0x10A00)
+
+#define EXYNOS4_DMC_PAUSE_CTRL		EXYNOS_CLKREG(0x11094)
+#define DMC_PAUSE_ENABLE		(1 << 0)
+
+#define EXYNOS4_APLL_LOCK		EXYNOS_CLKREG(0x14000)
+#define EXYNOS4_APLL_CON0		EXYNOS_CLKREG(0x14100)
+#define EXYNOS4_APLL_CON1		EXYNOS_CLKREG(0x14104)
+#define EXYNOS4_MPLL_CON0		(soc_is_exynos4210() ? \
+					EXYNOS_CLKREG(0x14108) : \
+					EXYNOS_CLKREG(0x10108))
+#define EXYNOS4_MPLL_CON1		(soc_is_exynos4210() ? \
+					EXYNOS_CLKREG(0x1410C) : \
+					EXYNOS_CLKREG(0x1010C))
+
+#define EXYNOS4_CLKSRC_CPU		EXYNOS_CLKREG(0x14200)
+#define EXYNOS4_CLKMUX_STATCPU		EXYNOS_CLKREG(0x14400)
+
+#define EXYNOS4_CLKDIV_CPU		EXYNOS_CLKREG(0x14500)
+#define EXYNOS4_CLKDIV_CPU1		EXYNOS_CLKREG(0x14504)
+#define EXYNOS4_CLKDIV_STATCPU		EXYNOS_CLKREG(0x14600)
+#define EXYNOS4_CLKDIV_STATCPU1		EXYNOS_CLKREG(0x14604)
+
+#define EXYNOS4_CLKGATE_SCLKCPU		EXYNOS_CLKREG(0x14800)
+#define EXYNOS4_CLKGATE_IP_CPU		EXYNOS_CLKREG(0x14900)
+#define EXYNOS4_CLKOUT_CMU_CPU		EXYNOS_CLKREG(0x14A00)
+
+#define EXYNOS4_PMREG(x)		(S5P_VA_PMU + (x))
+
+#define EXYNOS4_MIPI_CONTROL0		EXYNOS4_PMREG(0x0710)
+#define EXYNOS4_MIPI_CONTROL1		EXYNOS4_PMREG(0x0714)
+#define EXYNOS4_MIPI_DPHY_EN		(1 << 0)
+#define EXYNOS4_MIPI_DPHY_S_RESETN	(1 << 1)
+#define EXYNOS4_MIPI_DPHY_M_RESETN	(1 << 2)
+
+#define EXYNOS4_APLL_CON0L8		EXYNOS_CLKREG(0x15100)
+#define EXYNOS4_APLL_CON0L7		EXYNOS_CLKREG(0x15104)
+#define EXYNOS4_APLL_CON0L6		EXYNOS_CLKREG(0x15108)
+#define EXYNOS4_APLL_CON0L5		EXYNOS_CLKREG(0x1510C)
+#define EXYNOS4_APLL_CON0L4		EXYNOS_CLKREG(0x15110)
+#define EXYNOS4_APLL_CON0L3		EXYNOS_CLKREG(0x15114)
+#define EXYNOS4_APLL_CON0L2		EXYNOS_CLKREG(0x15118)
+#define EXYNOS4_APLL_CON0L1		EXYNOS_CLKREG(0x1511C)
+
+#define EXYNOS4_CLKDIV_IEM_L8		EXYNOS_CLKREG(0x15300)
+#define EXYNOS4_CLKDIV_IEM_L7		EXYNOS_CLKREG(0x15304)
+#define EXYNOS4_CLKDIV_IEM_L6		EXYNOS_CLKREG(0x15308)
+#define EXYNOS4_CLKDIV_IEM_L5		EXYNOS_CLKREG(0x1530C)
+#define EXYNOS4_CLKDIV_IEM_L4		EXYNOS_CLKREG(0x15310)
+#define EXYNOS4_CLKDIV_IEM_L3		EXYNOS_CLKREG(0x15314)
+#define EXYNOS4_CLKDIV_IEM_L2		EXYNOS_CLKREG(0x15318)
+#define EXYNOS4_CLKDIV_IEM_L1		EXYNOS_CLKREG(0x1531C)
+
+#define EXYNOS4_APLL_LOCKTIME		(0x1C20)	/* 300us */
+
+#define EXYNOS4_APLLCON0_ENABLE_SHIFT	(31)
+#define EXYNOS4_APLLCON0_LOCKED_SHIFT	(29)
+#define EXYNOS4_APLLCON0_LOCKED_MASK	(1 << EXYNOS4_APLLCON0_LOCKED_SHIFT)
+#define EXYNOS4_APLL_VAL_1000		((250 << 16) | (6 << 8) | 1)
+#define EXYNOS4_APLL_VAL_800		((200 << 16) | (6 << 8) | 1)
+
+#define EXYNOS4_EPLLCON0_ENABLE_SHIFT	(31)
+#define EXYNOS4_EPLLCON0_LOCKED_SHIFT	(29)
+
+#define EXYNOS4_VPLLCON0_ENABLE_SHIFT	(31)
+#define EXYNOS4_VPLLCON0_LOCKED_SHIFT	(29)
+
+#define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT	(16)
+#define EXYNOS4_CLKSRC_CPU_MUXHPM_SHIFT	(20)
+#define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK	(0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)
+
+#define EXYNOS4_CLKDIV_CPU0_CORE_SHIFT	(0)
+#define EXYNOS4_CLKDIV_CPU0_CORE_MASK	(0x7 << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT)
+#define EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT	(4)
+#define EXYNOS4_CLKDIV_CPU0_COREM0_MASK	(0x7 << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT)
+#define EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT	(8)
+#define EXYNOS4_CLKDIV_CPU0_COREM1_MASK	(0x7 << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT)
+#define EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT	(12)
+#define EXYNOS4_CLKDIV_CPU0_PERIPH_MASK	(0x7 << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT)
+#define EXYNOS4_CLKDIV_CPU0_ATB_SHIFT	(16)
+#define EXYNOS4_CLKDIV_CPU0_ATB_MASK	(0x7 << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT)
+#define EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT	(20)
+#define EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK	(0x7 << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT)
+#define EXYNOS4_CLKDIV_CPU0_APLL_SHIFT	(24)
+#define EXYNOS4_CLKDIV_CPU0_APLL_MASK	(0x7 << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT)
+#define EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT	28
+#define EXYNOS4_CLKDIV_CPU0_CORE2_MASK	(0x7 << EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT)
+
+#define EXYNOS4_CLKDIV_CPU1_COPY_SHIFT	(0)
+#define EXYNOS4_CLKDIV_CPU1_COPY_MASK	(0x7 << EXYNOS4_CLKDIV_CPU1_COPY_SHIFT)
+#define EXYNOS4_CLKDIV_CPU1_HPM_SHIFT	(4)
+#define EXYNOS4_CLKDIV_CPU1_HPM_MASK	(0x7 << EXYNOS4_CLKDIV_CPU1_HPM_SHIFT)
+#define EXYNOS4_CLKDIV_CPU1_CORES_SHIFT	(8)
+#define EXYNOS4_CLKDIV_CPU1_CORES_MASK	(0x7 << EXYNOS4_CLKDIV_CPU1_CORES_SHIFT)
+
+#define EXYNOS4_CLKDIV_DMC0_ACP_SHIFT	(0)
+#define EXYNOS4_CLKDIV_DMC0_ACP_MASK	(0x7 << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT)
+#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT	(4)
+#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK	(0x7 << EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT)
+#define EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT	(8)
+#define EXYNOS4_CLKDIV_DMC0_DPHY_MASK	(0x7 << EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT)
+#define EXYNOS4_CLKDIV_DMC0_DMC_SHIFT	(12)
+#define EXYNOS4_CLKDIV_DMC0_DMC_MASK	(0x7 << EXYNOS4_CLKDIV_DMC0_DMC_SHIFT)
+#define EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT	(16)
+#define EXYNOS4_CLKDIV_DMC0_DMCD_MASK	(0x7 << EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT)
+#define EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT	(20)
+#define EXYNOS4_CLKDIV_DMC0_DMCP_MASK	(0x7 << EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT)
+#define EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT	(24)
+#define EXYNOS4_CLKDIV_DMC0_COPY2_MASK	(0x7 << EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT)
+#define EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT	(28)
+#define EXYNOS4_CLKDIV_DMC0_CORETI_MASK	(0x7 << EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT)
+
+#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT	(0)
+#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK	(0xf << EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT)
+#define EXYNOS4_CLKDIV_DMC1_C2C_SHIFT	(4)
+#define EXYNOS4_CLKDIV_DMC1_C2C_MASK	(0x7 << EXYNOS4_CLKDIV_DMC1_C2C_SHIFT)
+#define EXYNOS4_CLKDIV_DMC1_PWI_SHIFT	(8)
+#define EXYNOS4_CLKDIV_DMC1_PWI_MASK	(0xf << EXYNOS4_CLKDIV_DMC1_PWI_SHIFT)
+#define EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT	(12)
+#define EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK	(0x7 << EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT)
+#define EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT	(16)
+#define EXYNOS4_CLKDIV_DMC1_DVSEM_MASK	(0x7f << EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT)
+#define EXYNOS4_CLKDIV_DMC1_DPM_SHIFT	(24)
+#define EXYNOS4_CLKDIV_DMC1_DPM_MASK	(0x7f << EXYNOS4_CLKDIV_DMC1_DPM_SHIFT)
+
+#define EXYNOS4_CLKDIV_MFC_SHIFT		(0)
+#define EXYNOS4_CLKDIV_MFC_MASK		(0x7 << EXYNOS4_CLKDIV_MFC_SHIFT)
+
+#define EXYNOS4_CLKDIV_CAM_SHIFT		(0)
+#define EXYNOS4_CLKDIV_CAM_MASK		(0xffff << EXYNOS4_CLKDIV_CAM_SHIFT)
+
+#define EXYNOS4_CLKDIV_IMAGE_SHIFT		(0)
+#define EXYNOS4_CLKDIV_IMAGE_MASK		(0x7 << EXYNOS4_CLKDIV_IMAGE_SHIFT)
+
+#define EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT	(0)
+#define EXYNOS4_CLKDIV_TOP_ACLK200_MASK	(0x7 << EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT)
+#define EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT	(4)
+#define EXYNOS4_CLKDIV_TOP_ACLK100_MASK	(0xf << EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT)
+#define EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT	(8)
+#define EXYNOS4_CLKDIV_TOP_ACLK160_MASK	(0x7 << EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT)
+#define EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT	(12)
+#define EXYNOS4_CLKDIV_TOP_ACLK133_MASK	(0x7 << EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT)
+#define EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT	(16)
+#define EXYNOS4_CLKDIV_TOP_ONENAND_MASK	(0x7 << EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT)
+#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT	(20)
+#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK		(0x7 << EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT)
+#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT	(24)
+#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_MASK	(0x7 << EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT)
+
+#define EXYNOS4_CLKDIV_TOP1_ACLK200_SUB_SHIFT		(20)
+#define EXYNOS4_CLKDIV_TOP1_ACLK400_MCUISP_SUB_SHIFT	(24)
+
+#define EXYNOS4_CLKDIV_BUS_GDLR_SHIFT	(0)
+#define EXYNOS4_CLKDIV_BUS_GDLR_MASK	(0x7 << EXYNOS4_CLKDIV_BUS_GDLR_SHIFT)
+#define EXYNOS4_CLKDIV_BUS_GPLR_SHIFT	(4)
+#define EXYNOS4_CLKDIV_BUS_GPLR_MASK	(0x7 << EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)
+
+#define EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT	(0)
+#define EXYNOS4_CLKDIV_CAM_FIMC0_MASK	(0xf << EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT)
+#define EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT	(4)
+#define EXYNOS4_CLKDIV_CAM_FIMC1_MASK	(0xf << EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT)
+#define EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT	(8)
+#define EXYNOS4_CLKDIV_CAM_FIMC2_MASK	(0xf << EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT)
+#define EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT	(12)
+#define EXYNOS4_CLKDIV_CAM_FIMC3_MASK	(0xf << EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT)
+
+#define EXYNOS4_CLKDIV_FSYS3_MMC4_SHIFT	(0)
+#define EXYNOS4_CLKDIV_FSYS3_MMC4_MASK	(0xf << EXYNOS4_CLKDIV_FSYS3_MMC4_SHIFT)
+#define EXYNOS4_CLKDIV_FSYS3_MMC4PRE_SHIFT	(8)
+#define EXYNOS4_CLKDIV_FSYS3_MMC4PRE_MASK	(0xff << EXYNOS4_CLKDIV_FSYS3_MMC4PRE_SHIFT)
+
+/* CLK_GATE_IP_IMAGE */
+#define EXYNOS4_CLKGATE_IP_IMAGE_MDMA	(0x1 << 2)
+#define EXYNOS4_CLKGATE_IP_IMAGE_SMMUMDMA	(0x1 << 5)
+#define EXYNOS4_CLKGATE_IP_IMAGE_QEMDMA	(0x1 << 8)
+
+/*  CLK_GATE_IP_FSYS */
+#define EXYNOS4_CLKGATE_IP_FSYS_PDMA0	(0x1 << 0)
+#define EXYNOS4_CLKGATE_IP_FSYS_PDMA1	(0x1 << 1)
+
+/*  CLK_GATE_IP_PERIL */
+#define EXYNOS4_CLKGATE_IP_PERIL_I2C0_7	(0xff << 6)
+
+/* Only for EXYNOS4210 */
+#define EXYNOS4_CLKSRC_LCD1		EXYNOS_CLKREG(0x0C238)
+#define EXYNOS4_CLKSRC_MASK_LCD1	EXYNOS_CLKREG(0x0C338)
+#define EXYNOS4_CLKDIV_LCD1		EXYNOS_CLKREG(0x0C538)
+#define EXYNOS4_CLKGATE_IP_LCD1		EXYNOS_CLKREG(0x0C938)
+
+/* Only for EXYNOS4212 */
+#define EXYNOS4_CLKGATE_BUS_LEFTBUS	EXYNOS_CLKREG(0x04700)
+#define EXYNOS4_CLKGATE_BUS_IMAGE	EXYNOS_CLKREG(0x04730)
+
+#define EXYNOS4_CLKGATE_BUS_RIGHTBUS	EXYNOS_CLKREG(0x08700)
+#define EXYNOS4_CLKGATE_BUS_PERIR	EXYNOS_CLKREG(0x08760)
+
+#define EXYNOS4_EPLL_CON2		EXYNOS_CLKREG(0x0C118)
+#define EXYNOS4_VPLL_CON2		EXYNOS_CLKREG(0x0C128)
+
+#define EXYNOS4_CLKSRC_ISP		EXYNOS_CLKREG(0x0C238)
+#define EXYNOS4_CLKSRC_CAM1		EXYNOS_CLKREG(0x0C258)
+
+#define EXYNOS4_CLKSRC_MASK_ISP		EXYNOS_CLKREG(0x0C338)
+
+#define EXYNOS4_CLKDIV_ISP		EXYNOS_CLKREG(0x0C538)
+#define EXYNOS4_CLKDIV_CAM1		EXYNOS_CLKREG(0x0C568)
+
+#define EXYNOS4_CLKDIV_STAT_CAM1	EXYNOS_CLKREG(0x0C668)
+
+#define EXYNOS4_CLKGATE_BUS_PERIL	EXYNOS_CLKREG(0x0C750)
+
+#define EXYNOS4_CLKGATE_IP_ISP		EXYNOS_CLKREG(0x0C938)
+#define EXYNOS4_CLKGATE_IP_MAUDIO	EXYNOS_CLKREG(0x0C93C)
+
+#define EXYNOS4_CLKGATE_BUS_DMC0	EXYNOS_CLKREG(0x10700)
+#define EXYNOS4_CLKGATE_BUS_DMC1	EXYNOS_CLKREG(0x10704)
+#define EXYNOS4_CLKGATE_SCLK_DMC	EXYNOS_CLKREG(0x10800)
+#define EXYNOS4_CLKGATE_IP_DMC1		EXYNOS_CLKREG(0x10904)
+
+#define EXYNOS4_PWR_CTRL1		EXYNOS_CLKREG(0x15020)
+#define EXYNOS4_PWR_CTRL2		EXYNOS_CLKREG(0x15024)
+
+#define EXYNOS4_CLKDIV_ISP0		EXYNOS_CLKREG(0x18300)
+#define EXYNOS4_CLKDIV_ISP1		EXYNOS_CLKREG(0x18304)
+
+#define EXYNOS4_CLKDIV_STAT_ISP0	EXYNOS_CLKREG(0x18400)
+#define EXYNOS4_CLKDIV_STAT_ISP1	EXYNOS_CLKREG(0x18404)
+
+#define EXYNOS4_CLKGATE_IP_ISP0		EXYNOS_CLKREG(0x18800)
+#define EXYNOS4_CLKGATE_IP_ISP1		EXYNOS_CLKREG(0x18804)
+#define EXYNOS4_CLKOUT_CMU_ISP		EXYNOS_CLKREG(0x18A00)
+
+#define EXYNOS4_CLKDIV_ISP_PWMISP_SHIFT	(0)
+#define EXYNOS4_CLKDIV_ISP_PWMISP_MASK	(0xf << EXYNOS4_CLKDIV_ISP_PWMISP_SHIFT)
+#define EXYNOS4_CLKDIV_ISP_SPI0ISP_SHIFT	(4)
+#define EXYNOS4_CLKDIV_ISP_SPI0ISP_MASK	(0xf << EXYNOS4_CLKDIV_ISP_SPI0ISP_SHIFT)
+#define EXYNOS4_CLKDIV_ISP_SPI0ISP_PRE_SHIFT	(8)
+#define EXYNOS4_CLKDIV_ISP_SPI0ISP_PRE_MASK		(0xff << EXYNOS4_CLKDIV_ISP_SPI0ISP_PRE_SHIFT)
+#define EXYNOS4_CLKDIV_ISP_SPI1ISP_SHIFT	(16)
+#define EXYNOS4_CLKDIV_ISP_SPI1ISP_MASK	(0xf << EXYNOS4_CLKDIV_ISP_SPI1ISP_SHIFT)
+#define EXYNOS4_CLKDIV_ISP_SPI1ISP_PRE_SHIFT	(20)
+#define EXYNOS4_CLKDIV_ISP_SPI1ISP_PRE_MASK		(0xff << EXYNOS4_CLKDIV_ISP_SPI1ISP_PRE_SHIFT)
+#define EXYNOS4_CLKDIV_ISP_UARTISP_SHIFT	(28)
+#define EXYNOS4_CLKDIV_ISP_UARTISP_MASK	(0xf << EXYNOS4_CLKDIV_ISP_SPI1ISP_SHIFT)
+
+#define EXYNOS4_CLKDIV_ISP0_ISP0_SHIFT	(0)
+#define EXYNOS4_CLKDIV_ISP0_ISP0_MASK	(0x7 << EXYNOS4_CLKDIV_ISP0_ISP0_SHIFT)
+#define EXYNOS4_CLKDIV_ISP0_ISP1_SHIFT	(4)
+#define EXYNOS4_CLKDIV_ISP0_ISP1_MASK	(0x7 << EXYNOS4_CLKDIV_ISP0_ISP1_SHIFT)
+#define EXYNOS4_CLKDIV_ISP1_MPWM_SHIFT	(0)
+#define EXYNOS4_CLKDIV_ISP1_MPWM_MASK	(0x7 << EXYNOS4_CLKDIV_ISP1_MPWM_SHIFT)
+#define EXYNOS4_CLKDIV_ISP1_MCUISP0_SHIFT	(4)
+#define EXYNOS4_CLKDIV_ISP1_MCUISP0_MASK	(0x7 << EXYNOS4_CLKDIV_ISP1_MCUISP0_SHIFT)
+#define EXYNOS4_CLKDIV_ISP1_MCUISP1_SHIFT	(8)
+#define EXYNOS4_CLKDIV_ISP1_MCUISP1_MASK	(0x7 << EXYNOS4_CLKDIV_ISP1_MCUISP1_SHIFT)
+
+#define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT	(0)
+#define EXYNOS4_CLKDIV_CAM1_JPEG_MASK	(0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)
+
+/* PWR_CTRL  */
+#define PWR_CTRL1_CORE2_DOWN_RATIO	28
+#define PWR_CTRL1_CORE2_DOWN_MASK	(0x7 << PWR_CTRL1_CORE2_DOWN_RATIO)
+#define PWR_CTRL1_CORE1_DOWN_RATIO	16
+#define PWR_CTRL1_CORE1_DOWN_MASK	(0x7 << PWR_CTRL1_CORE1_DOWN_RATIO)
+#define PWR_CTRL1_DIV2_DOWN_EN		(1 << 9)
+#define PWR_CTRL1_DIV1_DOWN_EN		(1 << 8)
+
+#define PWR_CTRL1_USE_CORE3_WFE		(1 << 7)
+#define PWR_CTRL1_USE_CORE2_WFE		(1 << 6)
+#define PWR_CTRL1_USE_CORE1_WFE		(1 << 5)
+#define PWR_CTRL1_USE_CORE0_WFE		(1 << 4)
+
+#define PWR_CTRL1_USE_CORE3_WFI		(1 << 3)
+#define PWR_CTRL1_USE_CORE2_WFI		(1 << 2)
+#define PWR_CTRL1_USE_CORE1_WFI		(1 << 1)
+#define PWR_CTRL1_USE_CORE0_WFI		(1 << 0)
+
+#define PWR_CTRL2_DIV2_UP_EN		(1 << 25)
+#define PWR_CTRL2_DIV1_UP_EN		(1 << 24)
+#define PWR_CTRL2_DUR_STANDBY2		16
+#define PWR_CTRL2_DUR_STANDBY2_MASK	(0xff << PWR_CTRL2_DUR_STANDBY2)
+#define PWR_CTRL2_DUR_STANDBY1		8
+#define PWR_CTRL2_DUR_STANDBY1_MASK	(0xff << PWR_CTRL2_DUR_STANDBY1)
+#define PWR_CTRL2_CORE2_UP_RATIO	4
+#define PWR_CTRL2_CORE2_UP_MASK		(0x7 << PWR_CTRL2_CORE2_UP_RATIO)
+#define PWR_CTRL2_CORE1_UP_RATIO	0
+#define PWR_CTRL2_CORE1_UP_MASK		(0x7 << PWR_CTRL2_CORE1_UP_RATIO)
+
+/* For EXYNOS5 */
+#define EXYNOS5_APLL_LOCK		EXYNOS_CLKREG(0x00000)
+#define EXYNOS5_APLL_CON0		EXYNOS_CLKREG(0x00100)
+#define EXYNOS5_APLL_CON1		EXYNOS_CLKREG(0x00104)
+#define EXYNOS5_CLKSRC_CPU		EXYNOS_CLKREG(0x00200)
+#define EXYNOS5_CLKMUX_STATCPU		EXYNOS_CLKREG(0x00400)
+#define EXYNOS5_CLKDIV_CPU0		EXYNOS_CLKREG(0x00500)
+#define EXYNOS5_CLKDIV_CPU1		EXYNOS_CLKREG(0x00504)
+#define EXYNOS5_CLKDIV_STATCPU0		EXYNOS_CLKREG(0x00600)
+#define EXYNOS5_CLKDIV_STATCPU1		EXYNOS_CLKREG(0x00604)
+
+#define EXYNOS5_ARMCLK_STOPCTRL		EXYNOS_CLKREG(0x01000)
+#define EXYNOS5_ATCLK_STOPCTRL		EXYNOS_CLKREG(0x01004)
+
+#define EXYNOS5_PARITYFAIL_STATUS	EXYNOS_CLKREG(0x01010)
+#define EXYNOS5_PARITYFAIL_CLEAR	EXYNOS_CLKREG(0x01014)
+
+#define EXYNOS5_PWR_CTRL1		EXYNOS_CLKREG(0x01020)
+#define EXYNOS5_PWR_CTRL2		EXYNOS_CLKREG(0x01024)
+
+#define EXYNOS5_MPLL_CON0		EXYNOS_CLKREG(0x04100)
+#define EXYNOS5_MPLL_CON1		EXYNOS_CLKREG(0x04104)
+#define EXYNOS5_CLKSRC_CORE0		EXYNOS_CLKREG(0x04200)
+#define EXYNOS5_CLKSRC_CORE1		EXYNOS_CLKREG(0x04204)
+
+#define EXYNOS5_CLKSRC_MASK_CORE	EXYNOS_CLKREG(0x04300)
+
+#define EXYNOS5_C2C_MONITOR		EXYNOS_CLKREG(0x04910)
+
+#define EXYNOS5_C2C_CONFIG		EXYNOS_CLKREG(0x06000)
+
+#define EXYNOS5_UFMC_CONFIG		EXYNOS_CLKREG(0x08A10)
+
+#define EXYNOS5_CPLL_LOCK		EXYNOS_CLKREG(0x10020)
+#define EXYNOS5_EPLL_LOCK		EXYNOS_CLKREG(0x10030)
+#define EXYNOS5_VPLL_LOCK		EXYNOS_CLKREG(0x10040)
+#define EXYNOS5_GPLL_LOCK		EXYNOS_CLKREG(0x10050)
+#define EXYNOS5_CPLL_CON0		EXYNOS_CLKREG(0x10120)
+#define EXYNOS5_CPLL_CON1		EXYNOS_CLKREG(0x10124)
+#define EXYNOS5_EPLL_CON0		EXYNOS_CLKREG(0x10130)
+#define EXYNOS5_EPLL_CON1		EXYNOS_CLKREG(0x10134)
+#define EXYNOS5_EPLL_CON2		EXYNOS_CLKREG(0x10138)
+#define EXYNOS5_VPLL_CON0		EXYNOS_CLKREG(0x10140)
+#define EXYNOS5_VPLL_CON1		EXYNOS_CLKREG(0x10144)
+#define EXYNOS5_VPLL_CON2		EXYNOS_CLKREG(0x10148)
+#define EXYNOS5_GPLL_CON0		EXYNOS_CLKREG(0x10150)
+#define EXYNOS5_GPLL_CON1		EXYNOS_CLKREG(0x10154)
+#define EXYNOS5_BPLL_CON0		EXYNOS_CLKREG(0x20110)
+#define EXYNOS5_BPLL_CON1		EXYNOS_CLKREG(0x20114)
+
+/* Clock Source Control Registers */
+#define EXYNOS5_CLKSRC_TOP0		EXYNOS_CLKREG(0x10210)
+#define EXYNOS5_CLKSRC_TOP1		EXYNOS_CLKREG(0x10214)
+#define EXYNOS5_CLKSRC_TOP2		EXYNOS_CLKREG(0x10218)
+#define EXYNOS5_CLKSRC_TOP3		EXYNOS_CLKREG(0x1021C)
+#define EXYNOS5_CLKSRC_GSCL		EXYNOS_CLKREG(0x10220)
+#define EXYNOS5_CLKSRC_DISP1_0		EXYNOS_CLKREG(0x1022C)
+#define EXYNOS5_CLKSRC_MAUDIO		EXYNOS_CLKREG(0x10240)
+#define EXYNOS5_CLKSRC_FSYS		EXYNOS_CLKREG(0x10244)
+#define EXYNOS5_CLKSRC_GEN		EXYNOS_CLKREG(0x10248)
+#define EXYNOS5_CLKSRC_PERIC0		EXYNOS_CLKREG(0x10250)
+#define EXYNOS5_CLKSRC_PERIC1		EXYNOS_CLKREG(0x10254)
+#define EXYNOS5_SCLK_SRC_ISP		EXYNOS_CLKREG(0x10270)
+#define EXYNOS5_CLKSRC_MASK_TOP		EXYNOS_CLKREG(0x10310)
+#define EXYNOS5_CLKSRC_MASK_GSCL	EXYNOS_CLKREG(0x10320)
+#define EXYNOS5_CLKSRC_MASK_DISP1_0	EXYNOS_CLKREG(0x1032C)
+#define EXYNOS5_CLKSRC_MASK_MAUDIO	EXYNOS_CLKREG(0x10334)
+#define EXYNOS5_CLKSRC_MASK_FSYS	EXYNOS_CLKREG(0x10340)
+#define EXYNOS5_CLKSRC_MASK_GEN		EXYNOS_CLKREG(0x10344)
+#define EXYNOS5_CLKSRC_MASK_PERIC0	EXYNOS_CLKREG(0x10350)
+#define EXYNOS5_CLKSRC_MASK_PERIC1	EXYNOS_CLKREG(0x10354)
+#define EXYNOS5_CLKSRC_MASK_ISP		EXYNOS_CLKREG(0x10370)
+#define EXYNOS5_CLKSRC_LEX		EXYNOS_CLKREG(0x14200)
+#define EXYNOS5_CLKSRC_CDREX		EXYNOS_CLKREG(0x20200)
+
+/* Clock Rate Control Registers */
+#define EXYNOS5_CLKDIV_CORE0		EXYNOS_CLKREG(0x04500)
+#define EXYNOS5_CLKDIV_CORE1		EXYNOS_CLKREG(0x04504)
+#define EXYNOS5_CLKDIV_SYSRGT		EXYNOS_CLKREG(0x04508)
+#define EXYNOS5_CLKDIV_ACP		EXYNOS_CLKREG(0x08500)
+#define EXYNOS5_CLKDIV_SYSLFT		EXYNOS_CLKREG(0x08900)
+#define EXYNOS5_CLKDIV_ISP0		EXYNOS_CLKREG(0x0C300)
+#define EXYNOS5_CLKDIV_ISP1		EXYNOS_CLKREG(0x0C304)
+#define EXYNOS5_CLKDIV_ISP2		EXYNOS_CLKREG(0x0C308)
+#define EXYNOS5_CLKDIV_TOP0		EXYNOS_CLKREG(0x10510)
+#define EXYNOS5_CLKDIV_TOP1		EXYNOS_CLKREG(0x10514)
+#define EXYNOS5_CLKDIV_GSCL		EXYNOS_CLKREG(0x10520)
+#define EXYNOS5_CLKDIV_DISP1_0		EXYNOS_CLKREG(0x1052C)
+#define EXYNOS5_CLKDIV_GEN		EXYNOS_CLKREG(0x1053C)
+#define EXYNOS5_CLKDIV_MAUDIO		EXYNOS_CLKREG(0x10544)
+#define EXYNOS5_CLKDIV_FSYS0		EXYNOS_CLKREG(0x10548)
+#define EXYNOS5_CLKDIV_FSYS1		EXYNOS_CLKREG(0x1054C)
+#define EXYNOS5_CLKDIV_FSYS2		EXYNOS_CLKREG(0x10550)
+#define EXYNOS5_CLKDIV_FSYS3		EXYNOS_CLKREG(0x10554)
+#define EXYNOS5_CLKDIV_PERIC0		EXYNOS_CLKREG(0x10558)
+#define EXYNOS5_CLKDIV_PERIC1		EXYNOS_CLKREG(0x1055C)
+#define EXYNOS5_CLKDIV_PERIC2		EXYNOS_CLKREG(0x10560)
+#define EXYNOS5_CLKDIV_PERIC3		EXYNOS_CLKREG(0x10564)
+#define EXYNOS5_CLKDIV_PERIC4		EXYNOS_CLKREG(0x10568)
+#define EXYNOS5_CLKDIV_PERIC5		EXYNOS_CLKREG(0x1056C)
+#define EXYNOS5_SCLK_DIV_ISP		EXYNOS_CLKREG(0x10580)
+#define EXYNOS5_CLKDIV_ISP0		EXYNOS_CLKREG(0x0C300)
+#define EXYNOS5_CLKDIV_ISP1		EXYNOS_CLKREG(0x0C304)
+#define EXYNOS5_CLKDIV_ISP2		EXYNOS_CLKREG(0x0C308)
+#define EXYNOS5_CLKDIV2_RATIO0		EXYNOS_CLKREG(0x10590)
+#define EXYNOS5_CLKDIV2_RATIO1		EXYNOS_CLKREG(0x10594)
+#define EXYNOS5_CLKDIV4_RATIO		EXYNOS_CLKREG(0x105A0)
+#define EXYNOS5_CLKDIV_LEX		EXYNOS_CLKREG(0x14500)
+#define EXYNOS5_CLKDIV_R0X		EXYNOS_CLKREG(0x18500)
+#define EXYNOS5_CLKDIV_R1X		EXYNOS_CLKREG(0x1C500)
+#define EXYNOS5_CLKDIV_CDREX		EXYNOS_CLKREG(0x20500)
+#define EXYNOS5_CLKDIV_CDREX2		EXYNOS_CLKREG(0x20504)
+
+#define EXYNOS5_CLKDIV_STAT_CPU0	EXYNOS_CLKREG(0x00600)
+#define EXYNOS5_CLKDIV_STAT_CPU1	EXYNOS_CLKREG(0x00604)
+#define EXYNOS5_CLKDIV_STAT_CORE0	EXYNOS_CLKREG(0x04600)
+#define EXYNOS5_CLKDIV_STAT_CORE1	EXYNOS_CLKREG(0x04604)
+#define EXYNOS5_CLKDIV_STAT_SYSRGT	EXYNOS_CLKREG(0x04608)
+#define EXYNOS5_CLKDIV_STAT_ACP		EXYNOS_CLKREG(0x08600)
+#define EXYNOS5_CLKDIV_STAT_SYSLFT	EXYNOS_CLKREG(0x08910)
+#define EXYNOS5_CLKDIV_STAT_ISP0	EXYNOS_CLKREG(0x0C400)
+#define EXYNOS5_CLKDIV_STAT_ISP1	EXYNOS_CLKREG(0x0C404)
+#define EXYNOS5_CLKDIV_STAT_ISP2	EXYNOS_CLKREG(0x0C408)
+#define EXYNOS5_CLKDIV_STAT_TOP0	EXYNOS_CLKREG(0x10610)
+#define EXYNOS5_CLKDIV_STAT_TOP1	EXYNOS_CLKREG(0x10614)
+#define EXYNOS5_CLKDIV_STAT_GSCL	EXYNOS_CLKREG(0x10620)
+#define EXYNOS5_CLKDIV_STAT_DISP1_0	EXYNOS_CLKREG(0x1062C)
+#define EXYNOS5_CLKDIV_STAT_GEN		EXYNOS_CLKREG(0x1063C)
+#define EXYNOS5_CLKDIV_STAT_MAUDIO	EXYNOS_CLKREG(0x10644)
+#define EXYNOS5_CLKDIV_STAT_FSYS0	EXYNOS_CLKREG(0x10648)
+#define EXYNOS5_CLKDIV_STAT_FSYS1	EXYNOS_CLKREG(0x1064C)
+#define EXYNOS5_CLKDIV_STAT_FSYS2	EXYNOS_CLKREG(0x10650)
+#define EXYNOS5_CLKDIV_STAT_PERIC0	EXYNOS_CLKREG(0x10658)
+#define EXYNOS5_CLKDIV_STAT_PERIC1	EXYNOS_CLKREG(0x1065C)
+#define EXYNOS5_CLKDIV_STAT_PERIC2	EXYNOS_CLKREG(0x10660)
+#define EXYNOS5_CLKDIV_STAT_PERIC3	EXYNOS_CLKREG(0x10664)
+#define EXYNOS5_CLKDIV_STAT_PERIC4	EXYNOS_CLKREG(0x10668)
+#define EXYNOS5_CLKDIV_STAT_PERIC5	EXYNOS_CLKREG(0x1066C)
+#define EXYNOS5_SCLK_DIV_STAT_ISP	EXYNOS_CLKREG(0x10680)
+#define EXYNOS5_CLKDIV_STAT_LEX		EXYNOS_CLKREG(0x14600)
+#define EXYNOS5_CLKDIV_STAT_R0X		EXYNOS_CLKREG(0x18600)
+#define EXYNOS5_CLKDIV_STAT_R1X		EXYNOS_CLKREG(0x1C600)
+#define EXYNOS5_CLKDIV_STAT_CDREX	EXYNOS_CLKREG(0x20600)
+#define EXYNOS5_CLKDIV_STAT_CDREX2	EXYNOS_CLKREG(0x20604)
+
+/* Clock Gate Control Registers */
+#define EXYNOS5_CLKGATE_IP_CORE		EXYNOS_CLKREG(0x04900)
+#define EXYNOS5_CLKGATE_IP_SYSRGT	EXYNOS_CLKREG(0x04904)
+#define EXYNOS5_CLKGATE_IP_ACP		EXYNOS_CLKREG(0x08800)
+#define EXYNOS5_CLKGATE_IP_SYSLFT	EXYNOS_CLKREG(0x08930)
+#define EXYNOS5_CLKGATE_ISP0		EXYNOS_CLKREG(0x0C800)
+#define EXYNOS5_CLKGATE_ISP1		EXYNOS_CLKREG(0x0C804)
+#define EXYNOS5_CLKGATE_SCLK_ISP	EXYNOS_CLKREG(0x0C900)
+#define EXYNOS5_CLKGATE_TOP_SCLK_DISP1	EXYNOS_CLKREG(0x10828)
+#define EXYNOS5_CLKGATE_TOP_SCLK_GEN	EXYNOS_CLKREG(0x1082C)
+#define EXYNOS5_CLKGATE_TOP_SCLK_MAUDIO	EXYNOS_CLKREG(0x1083C)
+#define EXYNOS5_CLKGATE_TOP_SCLK_FSYS	EXYNOS_CLKREG(0x10840)
+#define EXYNOS5_CLKGATE_TOP_SCLK_PERIC	EXYNOS_CLKREG(0x10850)
+#define EXYNOS5_CLKGATE_TOP_SCLK_ISP	EXYNOS_CLKREG(0x10870)
+#define EXYNOS5_CLKGATE_IP_GSCL		EXYNOS_CLKREG(0x10920)
+#define EXYNOS5_CLKGATE_IP_DISP1	EXYNOS_CLKREG(0x10928)
+#define EXYNOS5_CLKGATE_IP_MFC		EXYNOS_CLKREG(0x1092C)
+#define EXYNOS5_CLKGATE_IP_G3D		EXYNOS_CLKREG(0x10930)
+#define EXYNOS5_CLKGATE_IP_GEN		EXYNOS_CLKREG(0x10934)
+#define EXYNOS5_CLKGATE_IP_FSYS		EXYNOS_CLKREG(0x10944)
+#define EXYNOS5_CLKGATE_IP_GPS		EXYNOS_CLKREG(0x1094C)
+#define EXYNOS5_CLKGATE_IP_PERIC	EXYNOS_CLKREG(0x10950)
+#define EXYNOS5_CLKGATE_IP_PERIS	EXYNOS_CLKREG(0x10960)
+#define EXYNOS5_CLKGATE_BLOCK		EXYNOS_CLKREG(0x10980)
+#define EXYNOS5_CLKGATE_ISP0		EXYNOS_CLKREG(0x0C800)
+#define EXYNOS5_CLKGATE_ISP1		EXYNOS_CLKREG(0x0C804)
+
+#define EXYNOS5_CLKOUT_CMU_CPU		EXYNOS_CLKREG(0x00A00)
+#define EXYNOS5_CLKOUT_CMU_CORE		EXYNOS_CLKREG(0x04A00)
+#define EXYNOS5_CLKOUT_CMU_ACP		EXYNOS_CLKREG(0x08A00)
+#define EXYNOS5_CLKOUT_CMU_ISP		EXYNOS_CLKREG(0x0CA00)
+#define EXYNOS5_CLKOUT_CMU_TOP		EXYNOS_CLKREG(0x10A00)
+#define EXYNOS5_CLKOUT_CMU_LEX		EXYNOS_CLKREG(0x14A00)
+#define EXYNOS5_CLKOUT_CMU_R0X		EXYNOS_CLKREG(0x18A00)
+#define EXYNOS5_CLKOUT_CMU_R1X		EXYNOS_CLKREG(0x1CA00)
+#define EXYNOS5_CLKOUT_CMU_CDREX	EXYNOS_CLKREG(0x20A00)
+#define EXYNOS5_CLKGATE_IP_LEX		EXYNOS_CLKREG(0x14800)
+#define EXYNOS5_CLKGATE_IP_R0X		EXYNOS_CLKREG(0x18800)
+#define EXYNOS5_CLKGATE_IP_R1X		EXYNOS_CLKREG(0x1C800)
+#define EXYNOS5_CLKGATE_IP_CDREX	EXYNOS_CLKREG(0x20900)
+
+#define EXYNOS5_MCUIOP_PWR_CTRL		EXYNOS_CLKREG(0x109A0)
+
+#define EXYNOS5_CLKOUT_CMU_ACP		EXYNOS_CLKREG(0x08A00)
+#define EXYNOS5_CLKOUT_CMU_ISP		EXYNOS_CLKREG(0x0CA00)
+#define EXYNOS5_CLKOUT_CMU_TOP		EXYNOS_CLKREG(0x10A00)
+#define EXYNOS5_CLKOUT_CMU_LEX		EXYNOS_CLKREG(0x14A00)
+#define EXYNOS5_CLKOUT_CMU_R0X		EXYNOS_CLKREG(0x18A00)
+#define EXYNOS5_CLKOUT_CMU_R1X		EXYNOS_CLKREG(0x1CA00)
+#define EXYNOS5_CLKOUT_CMU_CDREX	EXYNOS_CLKREG(0x20A00)
+
+#define EXYNOS5_CLKGATE_IP_CPU		EXYNOS_CLKREG(0x20900)
+#define EXYNOS5_DMC_FREQ_CTRL		EXYNOS_CLKREG(0x20914)
+#define EXYNOS5_DREX2_PAUSE		EXYNOS_CLKREG(0x2091C)
+
+#define EXYNOS5_LPDDR3PHY_CTRL		EXYNOS_CLKREG(0x20A10)
+#define EXYNOS5_LPDDR3PHY_CON0		EXYNOS_CLKREG(0x20A14)
+#define EXYNOS5_LPDDR3PHY_CON1		EXYNOS_CLKREG(0x20A18)
+#define EXYNOS5_LPDDR3PHY_CON2		EXYNOS_CLKREG(0x20A1C)
+#define EXYNOS5_LPDDR3PHY_CON3		EXYNOS_CLKREG(0x20A20)
+#define EXYNOS5_PLL_DIV2_SEL		EXYNOS_CLKREG(0x20A24)
+
+
+
+#define EXYNOS5_EPLLCON0_ENABLE_SHIFT	(31)
+#define EXYNOS5_EPLLCON0_LOCKED_SHIFT	(29)
+#define EXYNOS5_VPLLCON0_LOCKED_SHIFT	(29)
+
+#define EXYNOS5_CLKDIV_TOP0_ACLK300_DISP1_SHIFT	(28)
+#define EXYNOS5_CLKDIV_TOP0_ACLK300_DISP1_MASK	(0x7 << EXYNOS5_CLKDIV_TOP0_ACLK300_DISP1_SHIFT)
+#define EXYNOS5_CLKDIV_TOP0_ACLK400_SHIFT	(24)
+#define EXYNOS5_CLKDIV_TOP0_ACLK400_MASK	(0x7 << EXYNOS5_CLKDIV_TOP0_ACLK400_SHIFT)
+#define EXYNOS5_CLKDIV_TOP0_ACLK333_SHIFT	(20)
+#define EXYNOS5_CLKDIV_TOP0_ACLK333_MASK	(0x7 << EXYNOS5_CLKDIV_TOP0_ACLK333_SHIFT)
+#define EXYNOS5_CLKDIV_TOP0_ACLK266_SHIFT	(16)
+#define EXYNOS5_CLKDIV_TOP0_ACLK266_MASK	(0x7 << EXYNOS5_CLKDIV_TOP0_ACLK266_SHIFT)
+#define EXYNOS5_CLKDIV_TOP0_ACLK200_SHIFT	(12)
+#define EXYNOS5_CLKDIV_TOP0_ACLK200_MASK	(0x7 << EXYNOS5_CLKDIV_TOP0_ACLK200_SHIFT)
+#define EXYNOS5_CLKDIV_TOP0_ACLK166_SHIFT	(8)
+#define EXYNOS5_CLKDIV_TOP0_ACLK166_MASK	(0x7 << EXYNOS5_CLKDIV_TOP0_ACLK166_SHIFT)
+#define EXYNOS5_CLKDIV_TOP0_ACLK133_SHIFT	(4)
+#define EXYNOS5_CLKDIV_TOP0_ACLK133_MASK	(0x7 << EXYNOS5_CLKDIV_TOP0_ACLK133_SHIFT)
+#define EXYNOS5_CLKDIV_TOP0_ACLK66_SHIFT	(0)
+#define EXYNOS5_CLKDIV_TOP0_ACLK66_MASK		(0x7 << EXYNOS5_CLKDIV_TOP0_ACLK66_SHIFT)
+
+#define EXYNOS5_CLKDIV_TOP1_ACLK66_PRE_SHIFT	(24)
+#define EXYNOS5_CLKDIV_TOP1_ACLK66_PRE_MASK	(0x7 << EXYNOS5_CLKDIV_TOP1_ACLK66_PRE_SHIFT)
+#define EXYNOS5_CLKDIV_TOP1_ACLK400_ISP_SHIFT	(20)
+#define EXYNOS5_CLKDIV_TOP1_ACLK400_ISP_MASK	(0x7 << EXYNOS5_CLKDIV_TOP1_ACLK400_ISP_SHIFT)
+#define EXYNOS5_CLKDIV_TOP1_ACLK400_IOP_SHIFT	(16)
+#define EXYNOS5_CLKDIV_TOP1_ACLK400_IOP_MASK	(0x7 << EXYNOS5_CLKDIV_TOP1_ACLK400_IOP_SHIFT)
+#define EXYNOS5_CLKDIV_TOP1_ACLK300_GSCL_SHIFT	(12)
+#define EXYNOS5_CLKDIV_TOP1_ACLK300_GSCL_MASK	(0x7 << EXYNOS5_CLKDIV_TOP1_ACLK300_GSCL_SHIFT)
+#define EXYNOS5_CLKDIV_TOP1_ACLK266_GPS_SHIFT	(8)
+#define EXYNOS5_CLKDIV_TOP1_ACLK266_GPS_MASK	(0x7 << EXYNOS5_CLKDIV_TOP1_ACLK266_GPS_SHIFT)
+
+#define EXYNOS5_CLKDIV_LEX_ATCLK_LEX_SHIFT	(8)
+#define EXYNOS5_CLKDIV_LEX_ATCLK_LEX_MASK	(0x7 << EXYNOS5_CLKDIV_LEX_ATCLK_LEX_SHIFT)
+#define EXYNOS5_CLKDIV_LEX_PCLK_LEX_SHIFT	(4)
+#define EXYNOS5_CLKDIV_LEX_PCLK_LEX_MASK	(0x7 << EXYNOS5_CLKDIV_LEX_PCLK_LEX_SHIFT)
+
+#define EXYNOS5_CLKDIV_R0X_PCLK_R0X_SHIFT	(4)
+#define EXYNOS5_CLKDIV_R0X_PCLK_R0X_MASK	(0x7 << EXYNOS5_CLKDIV_R0X_PCLK_R0X_SHIFT)
+
+#define EXYNOS5_CLKDIV_R1X_PCLK_R1X_SHIFT	(4)
+#define EXYNOS5_CLKDIV_R1X_PCLK_R1X_MASK	(0x7 << EXYNOS5_CLKDIV_R1X_PCLK_R1X_SHIFT)
+
+#define EXYNOS5_CLKDIV_CDREX_MCLK_CDREX2_SHIFT	(28)
+#define EXYNOS5_CLKDIV_CDREX_MCLK_CDREX2_MASK	(0x7 << EXYNOS5_CLKDIV_CDREX_MCLK_CDREX2_SHIFT)
+#define EXYNOS5_CLKDIV_CDREX_ACLK_EFCON_SHIFT	(24)
+#define EXYNOS5_CLKDIV_CDREX_ACLK_EFCON_MASK	(0x7 << EXYNOS5_CLKDIV_CDREX_ACLK_EFCON_SHIFT)
+#define EXYNOS5_CLKDIV_CDREX_MCLK_DPHY_SHIFT	(20)
+#define EXYNOS5_CLKDIV_CDREX_MCLK_DPHY_MASK	(0x7 << EXYNOS5_CLKDIV_CDREX_MCLK_DPHY_SHIFT)
+#define EXYNOS5_CLKDIV_CDREX_MCLK_CDREX_SHIFT	(16)
+#define EXYNOS5_CLKDIV_CDREX_MCLK_CDREX_MASK	(0x7 << EXYNOS5_CLKDIV_CDREX_MCLK_CDREX_SHIFT)
+#define EXYNOS5_CLKDIV_CDREX_ACLK_C2C200_SHIFT	(12)
+#define EXYNOS5_CLKDIV_CDREX_ACLK_C2C200_MASK	(0x7 << EXYNOS5_CLKDIV_CDREX_ACLK_C2C200_SHIFT)
+#define EXYNOS5_CLKDIV_CDREX_ACLK_CLK400_SHIFT	(8)
+#define EXYNOS5_CLKDIV_CDREX_ACLK_CLK400_MASK	(0x7 << EXYNOS5_CLKDIV_CDREX_ACLK_CLK400_SHIFT)
+#define EXYNOS5_CLKDIV_CDREX_PCLK_CDREX_SHIFT	(4)
+#define EXYNOS5_CLKDIV_CDREX_PCLK_CDREX_MASK	(0x7 << EXYNOS5_CLKDIV_CDREX_PCLK_CDREX_SHIFT)
+#define EXYNOS5_CLKDIV_CDREX_ACLK_CDREX_SHIFT	(0)
+#define EXYNOS5_CLKDIV_CDREX_ACLK_CDREX_MASK	(0x7 << EXYNOS5_CLKDIV_CDREX_ACLK_CDREX_SHIFT)
+
+#define EXYNOS5_CLKDIV_CDREX2_MCLK_EFPHY_SHIFT	(0)
+#define EXYNOS5_CLKDIV_CDREX2_MCLK_EFPHY_MASK	(0xf << EXYNOS5_CLKDIV_CDREX2_MCLK_EFPHY_SHIFT)
+
+#define EXYNOS5_VPLLCON0_LOCKED_SHIFT		(29)
+#define EXYNOS5_GPLLCON0_LOCKED_SHIFT		(29)
+
+/* Compatibility defines and inclusion */
+
+#include <mach/regs-pmu.h>
+
+#if defined(CONFIG_ARCH_EXYNOS4)
+#define S5P_EPLL_CON			EXYNOS4_EPLL_CON0
+#elif defined(CONFIG_ARCH_EXYNOS5)
+#define S5P_EPLL_CON			EXYNOS5_EPLL_CON0
+#else
+#error "ARCH_EXYNOS* is not defined"
+#endif
+
+#endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-fimg2d3x.h b/arch/arm/mach-exynos/include/mach/regs-fimg2d3x.h
new file mode 100644
index 0000000..5c62252
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/regs-fimg2d3x.h
@@ -0,0 +1,162 @@
+/* linux/arch/arm/mach-exynos/include/mach/regs-fimg2d3x.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *	http://www.samsung.com/
+ *
+ * Register Definitions for Samsung Graphics 2D Hardware
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_FIMG2D3X_H
+#define __ASM_ARCH_REGS_FIMG2D3X_H __FILE__
+
+/* Macros */
+#define FIMG2D_ADDR(v)			((v) << 0)
+#define FIMG2D_STRIDE(v)		(((v) & (0xffff)) << 0)
+#define FIMG2D_OFFSET(x, y)		((((y) & 0x1fff) << 16) | (((x) & 0x1fff) << 0))
+#define FIMG2D_SIZE(w, h)		((((h) & 0x1fff) << 16) | (((w) & 0x1fff) << 0))
+#define FIMG2D_COLOR(v)			((v) << 0)
+
+/* Registers */
+#define FIMG2D_SOFT_RESET_REG		(0x000)
+#define FIMG2D_INTEN_REG		(0x004)
+#define FIMG2D_INTC_PEND_REG		(0x00c)
+#define FIMG2D_FIFO_STAT_REG		(0x010)
+#define FIMG2D_AXI_ID_MODE_REG		(0x014)
+#define FIMG2D_CACHECTL_REG		(0x018)
+#define FIMG2D_BITBLT_START_REG		(0x100)
+#define FIMG2D_BITBLT_COMMAND_REG	(0x104)
+#define FIMG2D_ROTATE_REG		(0x200)
+#define FIMG2D_SRC_MSK_DIRECT_REG	(0x204)
+#define FIMG2D_DST_PAT_DIRECT_REG	(0x208)
+#define FIMG2D_SRC_SELECT_REG		(0x300)
+#define FIMG2D_SRC_BASE_ADDR_REG	(0x304)
+#define FIMG2D_SRC_STRIDE_REG		(0x308)
+#define FIMG2D_SRC_COLOR_MODE_REG	(0x30c)
+#define FIMG2D_SRC_LEFT_TOP_REG		(0x310)
+#define FIMG2D_SRC_RIGHT_BOTTOM_REG	(0x314)
+#define FIMG2D_DST_SELECT_REG		(0x400)
+#define FIMG2D_DST_BASE_ADDR_REG	(0x404)
+#define FIMG2D_DST_STRIDE_REG		(0x408)
+#define FIMG2D_DST_COLOR_MODE_REG	(0x40c)
+#define FIMG2D_DST_LEFT_TOP_REG		(0x410)
+#define FIMG2D_DST_RIGHT_BOTTOM_REG	(0x414)
+#define FIMG2D_PAT_BASE_ADDR_REG	(0x500)
+#define FIMG2D_PAT_SIZE_REG		(0x504)
+#define FIMG2D_PAT_COLOR_MODE_REG	(0x508)
+#define FIMG2D_PAT_OFFSET_REG		(0x50c)
+#define FIMG2D_PAT_STRIDE_REG		(0x510)
+#define FIMG2D_CW_LT_REG		(0x600)
+#define FIMG2D_CW_RB_REG		(0x604)
+#define FIMG2D_THIRD_OPERAND_REG	(0x610)
+#define FIMG2D_ROP4_REG			(0x614)
+#define FIMG2D_ALPHA_REG		(0x618)
+#define FIMG2D_FG_COLOR_REG		(0x700)
+#define FIMG2D_BG_COLOR_REG		(0x704)
+#define FIMG2D_BS_COLOR_REG		(0x708)
+#define FIMG2D_SRC_COLORKEY_CTRL_REG	(0x710)
+#define FIMG2D_SRC_COLORKEY_DR_MIN_REG	(0x714)
+#define FIMG2D_SRC_COLORKEY_DR_MAX_REG	(0x718)
+#define FIMG2D_DST_COLORKEY_CTRL_REG	(0x71c)
+#define FIMG2D_DST_COLORKEY_DR_MIN_REG	(0x720)
+#define FIMG2D_DST_COLORKEY_DR_MAX_REG	(0x724)
+
+/* Bit Definitions */
+
+/* SOFT_RESET_REG */
+#define FIMG2D_SOFT_RESET		(1 << 0)
+
+/* INTEN_REG */
+#define FIMG2D_INT_EN			(1 << 0)
+
+/* INTC_PEND_REG */
+#define FIMG2D_INTP_CMD_FIN		(1 << 0)
+
+/* FIFO_STAT_REG */
+#define FIMG2D_CMD_FIN			(1 << 0)
+
+/* CACHECTL_REG */
+#define FIMG2D_PATCACHE_CLEAR		(1 << 2)
+#define FIMG2D_SRCBUFFER_CLEAR		(1 << 1)
+#define FIMG2D_MASKBUFFER_CLEAR		(1 << 0)
+
+/* BITBLT_START_REG */
+#define FIMG2D_START_BITBLT		(1 << 0)
+
+/* BITBLT_COMMAND_REG */
+#define FIMG2D_NONPREBLEND_DISABLE	(0 << 22)
+#define FIMG2D_NONPREBLEND_CONSTANT	(1 << 22)
+#define FIMG2D_NONPREBLEND_PERPIXEL	(2 << 22)
+#define FIMG2D_NONPREBLEND_MASK		(3 << 22)
+
+#define FIMG2D_ALPHA_MODE_NONE		(0 << 20)
+#define FIMG2D_ALPHA_MODE_ALPHA		(1 << 20)
+#define FIMG2D_ALPHA_MODE_FADING	(2 << 20)
+#define FIMG2D_ALPHA_MODE_MASK		(3 << 20)
+
+#define FIMG2D_ENABLE_CW		(1 << 8)
+#define FIMG2D_ENABLE_STRETCH		(1 << 4)
+#define FIMG2D_ENABLE_MASK		(1 << 0)
+
+/* ROTATE_REG */
+#define FIMG2D_ROTATE_90_ENABLE		(1 << 0)
+
+/* SRC_MSK_DIRECT_REG */
+#define FIMG2D_MSK_X_DIR_NEGATIVE	(1 << 4)
+#define FIMG2D_MSK_Y_DIR_NEGATIVE	(1 << 5)
+#define FIMG2D_MSK_DIR_MASK		(3 << 4)
+
+#define FIMG2D_SRC_X_DIR_NEGATIVE	(1 << 0)
+#define FIMG2D_SRC_Y_DIR_NEGATIVE	(1 << 1)
+#define FIMG2D_SRC_DIR_MASK		(3 << 0)
+
+/* DST_PAT_DIRECT_REG */
+#define FIMG2D_PAT_X_DIR_NEGATIVE	(1 << 4)
+#define FIMG2D_PAT_Y_DIR_NEGATIVE	(1 << 5)
+#define FIMG2D_PAT_DIR_MASK		(3 << 4)
+
+#define FIMG2D_DST_X_DIR_NEGATIVE	(1 << 0)
+#define FIMG2D_DST_Y_DIR_NEGATIVE	(1 << 1)
+#define FIMG2D_DST_DIR_MASK		(3 << 0)
+
+/* XXX_SELECT_REG */
+#define FIMG2D_IMG_TYPE_MEMORY		(0 << 0)
+#define FIMG2D_IMG_TYPE_FGCOLOR		(1 << 0)
+#define FIMG2D_IMG_TYPE_BGCOLOR		(2 << 0)
+#define FIMG2D_IMG_TYPE_MASK		(3 << 0)
+
+/* XXX_COLOR_MODE_REG */
+#define FIMG2D_CHANNEL_ORDER_SHIFT	(4)
+#define FIMG2D_COLOR_FORMAT_SHIFT	(0)
+
+/* XXX_LEFT_TOP_REG & XXX_RIGHT_BOTTOM_REG */
+#define FIMG2D_COORD_TOP_Y_SHIFT	(16)
+#define FIMG2D_COORD_LEFT_X_SHIFT	(0)
+#define FIMG2D_COORD_BOTTOM_Y_SHIFT	(16)
+#define FIMG2D_COORD_RIGHT_X_SHIFT	(0)
+
+/* THIRD_OPERAND_REG */
+#define FIMG2D_MASKED_OPR3_PATTERN	(0 << 4)
+#define FIMG2D_MASKED_OPR3_FGCOLOR	(1 << 4)
+#define FIMG2D_MASKED_OPR3_BGCOLOR	(2 << 4)
+#define FIMG2D_MASKED_OPR3_MASK		(3 << 4)
+
+#define FIMG2D_UNMASKED_OPR3_PATTERN	(0 << 0)
+#define FIMG2D_UNMASKED_OPR3_FGCOLOR	(1 << 0)
+#define FIMG2D_UNMASKED_OPR3_BGCOLOR	(2 << 0)
+#define FIMG2D_UNMASKED_OPR3_MASK	(3 << 0)
+
+/* ROP4_REG */
+#define FIMG2D_MASKED_ROP3_SHIFT	(8)
+#define FIMG2D_UNMASKED_ROP3_SHIFT	(0)
+
+/* ALPHA_REG */
+#define FIMG2D_FADING_OFFSET_SHIFT	(8)
+#define FIMG2D_FADING_OFFSET_MASK	(0xff)
+#define FIMG2D_ALPHA_VALUE_SHIFT	(0)
+#define FIMG2D_ALPHA_VALUE_MASK		(0xff)
+
+#endif /* __ASM_MACH_REGS_FIMG2D3X_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-gpio.h b/arch/arm/mach-exynos/include/mach/regs-gpio.h
new file mode 100644
index 0000000..b03f2d3
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/regs-gpio.h
@@ -0,0 +1,53 @@
+/* linux/arch/arm/mach-exynos/include/mach/regs-gpio.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS4 - GPIO (including EINT) register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_GPIO_H
+#define __ASM_ARCH_REGS_GPIO_H __FILE__
+
+#include <mach/map.h>
+#include <mach/irqs.h>
+
+#if defined(CONFIG_ARCH_EXYNOS4)
+#define EINT_BASE_ADD			S5P_VA_GPIO2
+#define EINT_GPIO_0(x)			EXYNOS4_GPX0(x)
+#define EINT_GPIO_1(x)			EXYNOS4_GPX1(x)
+#define EINT_GPIO_2(x)			EXYNOS4_GPX2(x)
+#define EINT_GPIO_3(x)			EXYNOS4_GPX3(x)
+
+#elif defined(CONFIG_ARCH_EXYNOS5)
+#define EINT_BASE_ADD			S5P_VA_GPIO1
+#define EINT_GPIO_0(x)			EXYNOS5_GPX0(x)
+#define EINT_GPIO_1(x)			EXYNOS5_GPX1(x)
+#define EINT_GPIO_2(x)			EXYNOS5_GPX2(x)
+#define EINT_GPIO_3(x)			EXYNOS5_GPX3(x)
+#else
+#error "ARCH_EXYNOS* is not defined"
+#endif
+
+#define EXYNOS_EINT40CON		(EINT_BASE_ADD + 0xE00)
+#define S5P_EINT_CON(x)			(EXYNOS_EINT40CON + ((x) * 0x4))
+
+#define EXYNOS_EINT40FLTCON0		(EINT_BASE_ADD + 0xE80)
+#define S5P_EINT_FLTCON(x)		(EXYNOS_EINT40FLTCON0 + ((x) * 0x4))
+
+#define EXYNOS_EINT40MASK		(EINT_BASE_ADD + 0xF00)
+#define S5P_EINT_MASK(x)		(EXYNOS_EINT40MASK + ((x) * 0x4))
+
+#define EXYNOS_EINT40PEND		(EINT_BASE_ADD + 0xF40)
+#define S5P_EINT_PEND(x)		(EXYNOS_EINT40PEND + ((x) * 0x4))
+
+#define EINT_REG_NR(x)			(EINT_OFFSET(x) >> 3)
+
+#define eint_irq_to_bit(irq)		(1 << (EINT_OFFSET(irq) & 0x7))
+
+#define EINT_MODE			S3C_GPIO_SFN(0xf)
+#endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-hdmi.h b/arch/arm/mach-exynos/include/mach/regs-hdmi.h
new file mode 100644
index 0000000..6a9df06
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/regs-hdmi.h
@@ -0,0 +1,1787 @@
+/* linux/arch/arm/mach-exynos/include/mach/regs-hdmi.h
+ *
+ * Copyright (c) 2010 Samsung Electronics
+ *		http://www.samsung.com/
+ *
+ * HDMI register header file for Samsung TVOUT driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ARCH_ARM_REGS_HDMI_H
+#define __ARCH_ARM_REGS_HDMI_H
+
+/*
+ * Register part
+*/
+
+#ifdef CONFIG_HDMI_14A_3D
+
+#define S5P_HDMI_I2C_PHY_BASE(x)		(x)
+
+#define HDMI_I2C_CON				S5P_HDMI_I2C_PHY_BASE(0x0000)
+#define HDMI_I2C_STAT				S5P_HDMI_I2C_PHY_BASE(0x0004)
+#define HDMI_I2C_ADD				S5P_HDMI_I2C_PHY_BASE(0x0008)
+#define HDMI_I2C_DS				S5P_HDMI_I2C_PHY_BASE(0x000c)
+#define HDMI_I2C_LC				S5P_HDMI_I2C_PHY_BASE(0x0010)
+
+#define S5P_HDMI_CTRL_BASE(x)			(x)
+#define S5P_HDMI_BASE(x)			((x) + 0x00010000)
+#define S5P_HDMI_SPDIF_BASE(x)			((x) + 0x00030000)
+#define S5P_HDMI_I2S_BASE(x)			((x) + 0x00040000)
+#define S5P_HDMI_TG_BASE(x)			((x) + 0x00050000)
+#define S5P_HDMI_EFUSE_BASE(x)			((x) + 0x00060000)
+
+/* HDMIControlRegister */
+#define S5P_HDMI_INTC_CON0			S5P_HDMI_CTRL_BASE(0x000)
+#define S5P_HDMI_INTC_FLAG0			S5P_HDMI_CTRL_BASE(0x004)
+#define S5P_HDMI_AES_KEY_LOAD			S5P_HDMI_CTRL_BASE(0x008)
+#define S5P_HDMI_HPD_STATUS			S5P_HDMI_CTRL_BASE(0x00C)
+
+#define S5P_HDMI_INTC_CON1			S5P_HDMI_CTRL_BASE(0x010)
+#define S5P_HDMI_INTC_FLAG1			S5P_HDMI_CTRL_BASE(0x014)
+#define S5P_HDMI_PHY_STATUS0			S5P_HDMI_CTRL_BASE(0x020)
+#define S5P_HDMI_PHY_STATUS_PLL			S5P_HDMI_CTRL_BASE(0x028)
+#define S5P_HDMI_PHY_CON_0			S5P_HDMI_CTRL_BASE(0x030)
+
+#define S5P_HDMI_HPD_CTRL			S5P_HDMI_CTRL_BASE(0x040)
+#define S5P_HDMI_HPD_th_0			S5P_HDMI_CTRL_BASE(0x050)
+#define S5P_HDMI_HPD_th_1			S5P_HDMI_CTRL_BASE(0x054)
+#define S5P_HDMI_HPD_th_2			S5P_HDMI_CTRL_BASE(0x058)
+#define S5P_HDMI_HPD_th_3			S5P_HDMI_CTRL_BASE(0x05C)
+
+#define S5P_HDMI_AUDIO_CLKSEL			S5P_HDMI_CTRL_BASE(0x070)
+#define S5P_HDMI_PHY_RSTOUT			S5P_HDMI_CTRL_BASE(0x074)
+#define S5P_HDMI_PHY_VPLL			S5P_HDMI_CTRL_BASE(0x078)
+#define S5P_HDMI_PHY_CMU			S5P_HDMI_CTRL_BASE(0x07C)
+#define S5P_HDMI_CORE_RSTOUT			S5P_HDMI_CTRL_BASE(0x080)
+
+/* HDMICoreRegister */
+#define S5P_HDMI_CON_0				S5P_HDMI_BASE(0x000)
+#define S5P_HDMI_CON_1				S5P_HDMI_BASE(0x004)
+#define S5P_HDMI_CON_2				S5P_HDMI_BASE(0x008)
+#define S5P_HDMI_SIM_MODE			S5P_HDMI_BASE(0x00C)
+#define S5P_HDMI_SYS_STATUS			S5P_HDMI_BASE(0x010)
+#define S5P_HDMI_PHY_STATUS			S5P_HDMI_BASE(0x014)
+#define S5P_HDMI_STATUS_EN			S5P_HDMI_BASE(0x020)
+#define S5P_HDMI_HPD				S5P_HDMI_BASE(0x030)
+#define S5P_HDMI_MODE_SEL			S5P_HDMI_BASE(0x040)
+#define S5P_HDMI_ENC_EN				S5P_HDMI_BASE(0x044)
+
+#define S5P_HDMI_YMAX				S5P_HDMI_BASE(0x060)
+#define S5P_HDMI_YMIN				S5P_HDMI_BASE(0x064)
+#define S5P_HDMI_CMAX				S5P_HDMI_BASE(0x068)
+#define S5P_HDMI_CMIN				S5P_HDMI_BASE(0x06c)
+
+#define S5P_HDMI_DI_PREFIX			S5P_HDMI_BASE(0x078)
+#define S5P_HDMI_VBI_ST_MG			S5P_HDMI_BASE(0x080)
+#define S5P_HDMI_END_MG				S5P_HDMI_BASE(0x084)
+
+#define S5P_HDMI_AUTH_ST_MG0			S5P_HDMI_BASE(0x090)
+#define S5P_HDMI_AUTH_ST_MG1			S5P_HDMI_BASE(0x094)
+#define S5P_HDMI_AUTH_END_MG0			S5P_HDMI_BASE(0x098)
+#define S5P_HDMI_AUTH_END_MG1			S5P_HDMI_BASE(0x09C)
+
+#define S5P_HDMI_H_BLANK_0			S5P_HDMI_BASE(0x0a0)
+#define S5P_HDMI_H_BLANK_1			S5P_HDMI_BASE(0x0a4)
+
+#define S5P_HDMI_V2_BLANK_0			S5P_HDMI_BASE(0x0b0)
+#define S5P_HDMI_V2_BLANK_1			S5P_HDMI_BASE(0x0b4)
+#define S5P_HDMI_V1_BLANK_0			S5P_HDMI_BASE(0x0b8)
+#define S5P_HDMI_V1_BLANK_1			S5P_HDMI_BASE(0x0bC)
+
+#define S5P_HDMI_V_LINE_0			S5P_HDMI_BASE(0x0c0)
+#define S5P_HDMI_V_LINE_1			S5P_HDMI_BASE(0x0c4)
+#define S5P_HDMI_H_LINE_0			S5P_HDMI_BASE(0x0c8)
+#define S5P_HDMI_H_LINE_1			S5P_HDMI_BASE(0x0cC)
+#define S5P_HDMI_HSYNC_POL			S5P_HDMI_BASE(0x0E0)
+
+#define S5P_HDMI_VSYNC_POL			S5P_HDMI_BASE(0x0e4)
+#define S5P_HDMI_INT_PRO_MODE			S5P_HDMI_BASE(0x0e8)
+
+#define S5P_HDMI_V_BLANK_F0_0			S5P_HDMI_BASE(0x110)
+#define S5P_HDMI_V_BLANK_F0_1			S5P_HDMI_BASE(0x114)
+#define S5P_HDMI_V_BLANK_F1_0			S5P_HDMI_BASE(0x118)
+#define S5P_HDMI_V_BLANK_F1_1			S5P_HDMI_BASE(0x11C)
+
+#define S5P_HDMI_H_SYNC_START_0			S5P_HDMI_BASE(0x120)
+#define S5P_HDMI_H_SYNC_START_1			S5P_HDMI_BASE(0x124)
+#define S5P_HDMI_H_SYNC_END_0			S5P_HDMI_BASE(0x128)
+#define S5P_HDMI_H_SYNC_END_1			S5P_HDMI_BASE(0x12C)
+
+#define S5P_HDMI_V_SYNC_LINE_BEF_2_0		S5P_HDMI_BASE(0x130)
+#define S5P_HDMI_V_SYNC_LINE_BEF_2_1		S5P_HDMI_BASE(0x134)
+#define S5P_HDMI_V_SYNC_LINE_BEF_1_0		S5P_HDMI_BASE(0x138)
+#define S5P_HDMI_V_SYNC_LINE_BEF_1_1		S5P_HDMI_BASE(0x13C)
+
+#define S5P_HDMI_V_SYNC_LINE_AFT_2_0		S5P_HDMI_BASE(0x140)
+#define S5P_HDMI_V_SYNC_LINE_AFT_2_1		S5P_HDMI_BASE(0x144)
+#define S5P_HDMI_V_SYNC_LINE_AFT_1_0		S5P_HDMI_BASE(0x148)
+#define S5P_HDMI_V_SYNC_LINE_AFT_1_1		S5P_HDMI_BASE(0x14C)
+
+#define S5P_HDMI_V_SYNC_LINE_AFT_PXL_2_0	S5P_HDMI_BASE(0x150)
+#define S5P_HDMI_V_SYNC_LINE_AFT_PXL_2_1	S5P_HDMI_BASE(0x154)
+#define S5P_HDMI_V_SYNC_LINE_AFT_PXL_1_0	S5P_HDMI_BASE(0x158)
+#define S5P_HDMI_V_SYNC_LINE_AFT_PXL_1_1	S5P_HDMI_BASE(0x15C)
+
+#define S5P_HDMI_V_BLANK_F2_0			S5P_HDMI_BASE(0x160)
+#define S5P_HDMI_V_BLANK_F2_1			S5P_HDMI_BASE(0x164)
+#define S5P_HDMI_V_BLANK_F3_0			S5P_HDMI_BASE(0x168)
+#define S5P_HDMI_V_BLANK_F3_1			S5P_HDMI_BASE(0x16C)
+#define S5P_HDMI_V_BLANK_F4_0			S5P_HDMI_BASE(0x170)
+#define S5P_HDMI_V_BLANK_F4_1			S5P_HDMI_BASE(0x174)
+#define S5P_HDMI_V_BLANK_F5_0			S5P_HDMI_BASE(0x178)
+#define S5P_HDMI_V_BLANK_F5_1			S5P_HDMI_BASE(0x17C)
+
+#define S5P_HDMI_V_SYNC_LINE_AFT_3_0		S5P_HDMI_BASE(0x180)
+#define S5P_HDMI_V_SYNC_LINE_AFT_3_1		S5P_HDMI_BASE(0x184)
+#define S5P_HDMI_V_SYNC_LINE_AFT_4_0		S5P_HDMI_BASE(0x188)
+#define S5P_HDMI_V_SYNC_LINE_AFT_4_1		S5P_HDMI_BASE(0x18C)
+#define S5P_HDMI_V_SYNC_LINE_AFT_5_0		S5P_HDMI_BASE(0x190)
+#define S5P_HDMI_V_SYNC_LINE_AFT_5_1		S5P_HDMI_BASE(0x194)
+#define S5P_HDMI_V_SYNC_LINE_AFT_6_0		S5P_HDMI_BASE(0x198)
+#define S5P_HDMI_V_SYNC_LINE_AFT_6_1		S5P_HDMI_BASE(0x19C)
+
+#define S5P_HDMI_V_SYNC_LINE_AFT_PXL_3_0	S5P_HDMI_BASE(0x1A0)
+#define S5P_HDMI_V_SYNC_LINE_AFT_PXL_3_1	S5P_HDMI_BASE(0x1A4)
+#define S5P_HDMI_V_SYNC_LINE_AFT_PXL_4_0	S5P_HDMI_BASE(0x1A8)
+#define S5P_HDMI_V_SYNC_LINE_AFT_PXL_4_1	S5P_HDMI_BASE(0x1AC)
+#define S5P_HDMI_V_SYNC_LINE_AFT_PXL_5_0	S5P_HDMI_BASE(0x1B0)
+#define S5P_HDMI_V_SYNC_LINE_AFT_PXL_5_1	S5P_HDMI_BASE(0x1B4)
+#define S5P_HDMI_V_SYNC_LINE_AFT_PXL_6_0	S5P_HDMI_BASE(0x1B8)
+#define S5P_HDMI_V_SYNC_LINE_AFT_PXL_6_1	S5P_HDMI_BASE(0x1BC)
+
+#define S5P_HDMI_VACT_SPACE_1_0			S5P_HDMI_BASE(0x1C0)
+#define S5P_HDMI_VACT_SPACE_1_1			S5P_HDMI_BASE(0x1C4)
+#define S5P_HDMI_VACT_SPACE_2_0			S5P_HDMI_BASE(0x1C8)
+#define S5P_HDMI_VACT_SPACE_2_1			S5P_HDMI_BASE(0x1CC)
+#define S5P_HDMI_VACT_SPACE_3_0			S5P_HDMI_BASE(0x1D0)
+#define S5P_HDMI_VACT_SPACE_3_1			S5P_HDMI_BASE(0x1D4)
+#define S5P_HDMI_VACT_SPACE_4_0			S5P_HDMI_BASE(0x1D8)
+#define S5P_HDMI_VACT_SPACE_4_1			S5P_HDMI_BASE(0x1DC)
+#define S5P_HDMI_VACT_SPACE_5_0			S5P_HDMI_BASE(0x1E0)
+#define S5P_HDMI_VACT_SPACE_5_1			S5P_HDMI_BASE(0x1E4)
+#define S5P_HDMI_VACT_SPACE_6_0			S5P_HDMI_BASE(0x1E8)
+#define S5P_HDMI_VACT_SPACE_6_1			S5P_HDMI_BASE(0x1EC)
+#define S5P_HDMI_CSC_MUX			S5P_HDMI_BASE(0x1F0)
+#define S5P_HDMI_SYNC_GEN_MUX			S5P_HDMI_BASE(0x1F4)
+
+#define S5P_HDMI_GCP_CON			S5P_HDMI_BASE(0x200)
+#define S5P_HDMI_GCP_CON_EX			S5P_HDMI_BASE(0x204)
+#define S5P_HDMI_GCP_BYTE1			S5P_HDMI_BASE(0x210)
+#define S5P_HDMI_GCP_BYTE2			S5P_HDMI_BASE(0x214)
+#define S5P_HDMI_GCP_BYTE3			S5P_HDMI_BASE(0x218)
+
+#define S5P_HDMI_ASP_CON			S5P_HDMI_BASE(0x300)
+#define S5P_HDMI_ASP_SP_FLAT			S5P_HDMI_BASE(0x304)
+#define S5P_HDMI_ASP_CHCFG0			S5P_HDMI_BASE(0x310)
+#define S5P_HDMI_ASP_CHCFG1			S5P_HDMI_BASE(0x314)
+#define S5P_HDMI_ASP_CHCFG2			S5P_HDMI_BASE(0x318)
+#define S5P_HDMI_ASP_CHCFG3			S5P_HDMI_BASE(0x31c)
+
+#define S5P_HDMI_ACR_CON			S5P_HDMI_BASE(0x400)
+#define S5P_HDMI_ACR_MCTS0			S5P_HDMI_BASE(0x410)
+#define S5P_HDMI_ACR_MCTS1			S5P_HDMI_BASE(0x414)
+#define S5P_HDMI_ACR_MCTS2			S5P_HDMI_BASE(0x418)
+#define S5P_HDMI_ACR_CTS0			S5P_HDMI_BASE(0x420)
+#define S5P_HDMI_ACR_CTS1			S5P_HDMI_BASE(0x424)
+#define S5P_HDMI_ACR_CTS2			S5P_HDMI_BASE(0x428)
+#define S5P_HDMI_ACR_N0				S5P_HDMI_BASE(0x430)
+#define S5P_HDMI_ACR_N1				S5P_HDMI_BASE(0x434)
+#define S5P_HDMI_ACR_N2				S5P_HDMI_BASE(0x438)
+#define S5P_HDMI_ACR_LSB2			S5P_HDMI_BASE(0x440)
+#define S5P_HDMI_ACR_TXCNT			S5P_HDMI_BASE(0x444)
+#define S5P_HDMI_ACR_TXINTERNAL			S5P_HDMI_BASE(0x448)
+#define S5P_HDMI_ACR_CTS_OFFSET			S5P_HDMI_BASE(0x44c)
+
+#define S5P_HDMI_ACP_CON			S5P_HDMI_BASE(0x500)
+#define S5P_HDMI_ACP_TYPE			S5P_HDMI_BASE(0x514)
+#define S5P_HDMI_ACP_DATA00			S5P_HDMI_BASE(0x520)
+#define S5P_HDMI_ACP_DATA01			S5P_HDMI_BASE(0x524)
+#define S5P_HDMI_ACP_DATA02			S5P_HDMI_BASE(0x528)
+#define S5P_HDMI_ACP_DATA03			S5P_HDMI_BASE(0x52C)
+#define S5P_HDMI_ACP_DATA04			S5P_HDMI_BASE(0x530)
+#define S5P_HDMI_ACP_DATA05			S5P_HDMI_BASE(0x534)
+#define S5P_HDMI_ACP_DATA06			S5P_HDMI_BASE(0x538)
+#define S5P_HDMI_ACP_DATA07			S5P_HDMI_BASE(0x53c)
+#define S5P_HDMI_ACP_DATA08			S5P_HDMI_BASE(0x540)
+#define S5P_HDMI_ACP_DATA09			S5P_HDMI_BASE(0x544)
+#define S5P_HDMI_ACP_DATA10			S5P_HDMI_BASE(0x548)
+#define S5P_HDMI_ACP_DATA11			S5P_HDMI_BASE(0x54c)
+#define S5P_HDMI_ACP_DATA12			S5P_HDMI_BASE(0x550)
+#define S5P_HDMI_ACP_DATA13			S5P_HDMI_BASE(0x554)
+#define S5P_HDMI_ACP_DATA14			S5P_HDMI_BASE(0x558)
+#define S5P_HDMI_ACP_DATA15			S5P_HDMI_BASE(0x55c)
+#define S5P_HDMI_ACP_DATA16			S5P_HDMI_BASE(0x560)
+
+#define S5P_HDMI_ISRC_CON			S5P_HDMI_BASE(0x600)
+#define S5P_HDMI_ISRC1_HEADER1			S5P_HDMI_BASE(0x614)
+#define S5P_HDMI_ISRC1_DATA00			S5P_HDMI_BASE(0x620)
+#define S5P_HDMI_ISRC1_DATA01			S5P_HDMI_BASE(0x624)
+#define S5P_HDMI_ISRC1_DATA02			S5P_HDMI_BASE(0x628)
+#define S5P_HDMI_ISRC1_DATA03			S5P_HDMI_BASE(0x62c)
+#define S5P_HDMI_ISRC1_DATA04			S5P_HDMI_BASE(0x630)
+#define S5P_HDMI_ISRC1_DATA05			S5P_HDMI_BASE(0x634)
+#define S5P_HDMI_ISRC1_DATA06			S5P_HDMI_BASE(0x638)
+#define S5P_HDMI_ISRC1_DATA07			S5P_HDMI_BASE(0x63c)
+#define S5P_HDMI_ISRC1_DATA08			S5P_HDMI_BASE(0x640)
+#define S5P_HDMI_ISRC1_DATA09			S5P_HDMI_BASE(0x644)
+#define S5P_HDMI_ISRC1_DATA10			S5P_HDMI_BASE(0x648)
+#define S5P_HDMI_ISRC1_DATA11			S5P_HDMI_BASE(0x64c)
+#define S5P_HDMI_ISRC1_DATA12			S5P_HDMI_BASE(0x650)
+#define S5P_HDMI_ISRC1_DATA13			S5P_HDMI_BASE(0x654)
+#define S5P_HDMI_ISRC1_DATA14			S5P_HDMI_BASE(0x658)
+#define S5P_HDMI_ISRC1_DATA15			S5P_HDMI_BASE(0x65c)
+#define S5P_HDMI_ISRC2_DATA00			S5P_HDMI_BASE(0x6A0)
+#define S5P_HDMI_ISRC2_DATA01			S5P_HDMI_BASE(0x6A4)
+#define S5P_HDMI_ISRC2_DATA02			S5P_HDMI_BASE(0x6A8)
+#define S5P_HDMI_ISRC2_DATA03			S5P_HDMI_BASE(0x6Ac)
+#define S5P_HDMI_ISRC2_DATA04			S5P_HDMI_BASE(0x6B0)
+#define S5P_HDMI_ISRC2_DATA05			S5P_HDMI_BASE(0x6B4)
+#define S5P_HDMI_ISRC2_DATA06			S5P_HDMI_BASE(0x6B8)
+#define S5P_HDMI_ISRC2_DATA07			S5P_HDMI_BASE(0x6Bc)
+#define S5P_HDMI_ISRC2_DATA08			S5P_HDMI_BASE(0x6C0)
+#define S5P_HDMI_ISRC2_DATA09			S5P_HDMI_BASE(0x6C4)
+#define S5P_HDMI_ISRC2_DATA10			S5P_HDMI_BASE(0x6C8)
+#define S5P_HDMI_ISRC2_DATA11			S5P_HDMI_BASE(0x6Cc)
+#define S5P_HDMI_ISRC2_DATA12			S5P_HDMI_BASE(0x6D0)
+#define S5P_HDMI_ISRC2_DATA13			S5P_HDMI_BASE(0x6D4)
+#define S5P_HDMI_ISRC2_DATA14			S5P_HDMI_BASE(0x6D8)
+#define S5P_HDMI_ISRC2_DATA15			S5P_HDMI_BASE(0x6Dc)
+
+#define S5P_HDMI_AVI_CON			S5P_HDMI_BASE(0x700)
+#define S5P_HDMI_AVI_HEADER0			S5P_HDMI_BASE(0x710)
+#define S5P_HDMI_AVI_HEADER1			S5P_HDMI_BASE(0x714)
+#define S5P_HDMI_AVI_HEADER2			S5P_HDMI_BASE(0x718)
+#define S5P_HDMI_AVI_CHECK_SUM			S5P_HDMI_BASE(0x71C)
+#define S5P_HDMI_AVI_BYTE1			S5P_HDMI_BASE(0x720)
+#define S5P_HDMI_AVI_BYTE2			S5P_HDMI_BASE(0x724)
+#define S5P_HDMI_AVI_BYTE3			S5P_HDMI_BASE(0x728)
+#define S5P_HDMI_AVI_BYTE4			S5P_HDMI_BASE(0x72c)
+#define S5P_HDMI_AVI_BYTE5			S5P_HDMI_BASE(0x730)
+#define S5P_HDMI_AVI_BYTE6			S5P_HDMI_BASE(0x734)
+#define S5P_HDMI_AVI_BYTE7			S5P_HDMI_BASE(0x738)
+#define S5P_HDMI_AVI_BYTE8			S5P_HDMI_BASE(0x73c)
+#define S5P_HDMI_AVI_BYTE9			S5P_HDMI_BASE(0x740)
+#define S5P_HDMI_AVI_BYTE10			S5P_HDMI_BASE(0x744)
+#define S5P_HDMI_AVI_BYTE11			S5P_HDMI_BASE(0x748)
+#define S5P_HDMI_AVI_BYTE12			S5P_HDMI_BASE(0x74c)
+#define S5P_HDMI_AVI_BYTE13			S5P_HDMI_BASE(0x750)
+
+#define S5P_HDMI_AUI_CON			S5P_HDMI_BASE(0x800)
+#define S5P_HDMI_AUI_HEADER0			S5P_HDMI_BASE(0x810)
+#define S5P_HDMI_AUI_HEADER1			S5P_HDMI_BASE(0x814)
+#define S5P_HDMI_AUI_HEADER2			S5P_HDMI_BASE(0x818)
+#define S5P_HDMI_AUI_CHECK_SUM			S5P_HDMI_BASE(0x81C)
+#define S5P_HDMI_AUI_BYTE1			S5P_HDMI_BASE(0x820)
+#define S5P_HDMI_AUI_BYTE2			S5P_HDMI_BASE(0x824)
+#define S5P_HDMI_AUI_BYTE3			S5P_HDMI_BASE(0x828)
+#define S5P_HDMI_AUI_BYTE4			S5P_HDMI_BASE(0x82c)
+#define S5P_HDMI_AUI_BYTE5			S5P_HDMI_BASE(0x830)
+#define S5P_HDMI_AUI_BYTE6			S5P_HDMI_BASE(0x834)
+#define S5P_HDMI_AUI_BYTE7			S5P_HDMI_BASE(0x838)
+#define S5P_HDMI_AUI_BYTE8			S5P_HDMI_BASE(0x83C)
+#define S5P_HDMI_AUI_BYTE9			S5P_HDMI_BASE(0x840)
+#define S5P_HDMI_AUI_BYTE10			S5P_HDMI_BASE(0x844)
+#define S5P_HDMI_AUI_BYTE11			S5P_HDMI_BASE(0x848)
+#define S5P_HDMI_AUI_BYTE12			S5P_HDMI_BASE(0x84C)
+
+#define S5P_HDMI_MPG_CON			S5P_HDMI_BASE(0x900)
+#define S5P_HDMI_MPG_CHECK_SUM			S5P_HDMI_BASE(0x91C)
+#define S5P_HDMI_MPG_BYTE1			S5P_HDMI_BASE(0x920)
+#define S5P_HDMI_MPG_BYTE2			S5P_HDMI_BASE(0x924)
+#define S5P_HDMI_MPG_BYTE3			S5P_HDMI_BASE(0x928)
+#define S5P_HDMI_MPG_BYTE4			S5P_HDMI_BASE(0x92c)
+#define S5P_HDMI_MPG_BYTE5			S5P_HDMI_BASE(0x930)
+#define S5P_HDMI_MPG_BYTE6			S5P_HDMI_BASE(0x934)
+
+#define S5P_HDMI_SPD_CON			S5P_HDMI_BASE(0xA00)
+#define S5P_HDMI_SPD_HEADER0			S5P_HDMI_BASE(0xA10)
+#define S5P_HDMI_SPD_HEADER1			S5P_HDMI_BASE(0xA14)
+#define S5P_HDMI_SPD_HEADER2			S5P_HDMI_BASE(0xA18)
+#define S5P_HDMI_SPD_DATA00			S5P_HDMI_BASE(0xA20)
+#define S5P_HDMI_SPD_DATA01			S5P_HDMI_BASE(0xA24)
+#define S5P_HDMI_SPD_DATA02			S5P_HDMI_BASE(0xA28)
+#define S5P_HDMI_SPD_DATA03			S5P_HDMI_BASE(0xA2c)
+#define S5P_HDMI_SPD_DATA04			S5P_HDMI_BASE(0xA30)
+#define S5P_HDMI_SPD_DATA05			S5P_HDMI_BASE(0xA34)
+#define S5P_HDMI_SPD_DATA06			S5P_HDMI_BASE(0xA38)
+#define S5P_HDMI_SPD_DATA07			S5P_HDMI_BASE(0xA3c)
+#define S5P_HDMI_SPD_DATA08			S5P_HDMI_BASE(0xA40)
+#define S5P_HDMI_SPD_DATA09			S5P_HDMI_BASE(0xA44)
+#define S5P_HDMI_SPD_DATA10			S5P_HDMI_BASE(0xA48)
+#define S5P_HDMI_SPD_DATA11			S5P_HDMI_BASE(0xA4c)
+#define S5P_HDMI_SPD_DATA12			S5P_HDMI_BASE(0xA50)
+#define S5P_HDMI_SPD_DATA13			S5P_HDMI_BASE(0xA54)
+#define S5P_HDMI_SPD_DATA14			S5P_HDMI_BASE(0xA58)
+#define S5P_HDMI_SPD_DATA15			S5P_HDMI_BASE(0xA5c)
+#define S5P_HDMI_SPD_DATA16			S5P_HDMI_BASE(0xA60)
+#define S5P_HDMI_SPD_DATA17			S5P_HDMI_BASE(0xA64)
+#define S5P_HDMI_SPD_DATA18			S5P_HDMI_BASE(0xA68)
+#define S5P_HDMI_SPD_DATA19			S5P_HDMI_BASE(0xA6c)
+#define S5P_HDMI_SPD_DATA20			S5P_HDMI_BASE(0xA70)
+#define S5P_HDMI_SPD_DATA21			S5P_HDMI_BASE(0xA74)
+#define S5P_HDMI_SPD_DATA22			S5P_HDMI_BASE(0xA78)
+#define S5P_HDMI_SPD_DATA23			S5P_HDMI_BASE(0xA7c)
+#define S5P_HDMI_SPD_DATA24			S5P_HDMI_BASE(0xA80)
+#define S5P_HDMI_SPD_DATA25			S5P_HDMI_BASE(0xA84)
+#define S5P_HDMI_SPD_DATA26			S5P_HDMI_BASE(0xA88)
+#define S5P_HDMI_SPD_DATA27			S5P_HDMI_BASE(0xA8c)
+
+#define S5P_HDMI_GAMUT_CON			S5P_HDMI_BASE(0xB00)
+#define S5P_HDMI_GAMUT_HEADER0			S5P_HDMI_BASE(0xB10)
+#define S5P_HDMI_GAMUT_HEADER1			S5P_HDMI_BASE(0xB14)
+#define S5P_HDMI_GAMUT_HEADER2			S5P_HDMI_BASE(0xB18)
+#define S5P_HDMI_GAMUT_DATA00			S5P_HDMI_BASE(0xB20)
+#define S5P_HDMI_GAMUT_DATA01			S5P_HDMI_BASE(0xB24)
+#define S5P_HDMI_GAMUT_DATA02			S5P_HDMI_BASE(0xB28)
+#define S5P_HDMI_GAMUT_DATA03			S5P_HDMI_BASE(0xB2c)
+#define S5P_HDMI_GAMUT_DATA04			S5P_HDMI_BASE(0xB30)
+#define S5P_HDMI_GAMUT_DATA05			S5P_HDMI_BASE(0xB34)
+#define S5P_HDMI_GAMUT_DATA06			S5P_HDMI_BASE(0xB38)
+#define S5P_HDMI_GAMUT_DATA07			S5P_HDMI_BASE(0xB3c)
+#define S5P_HDMI_GAMUT_DATA08			S5P_HDMI_BASE(0xB40)
+#define S5P_HDMI_GAMUT_DATA09			S5P_HDMI_BASE(0xB44)
+#define S5P_HDMI_GAMUT_DATA10			S5P_HDMI_BASE(0xB48)
+#define S5P_HDMI_GAMUT_DATA11			S5P_HDMI_BASE(0xB4c)
+#define S5P_HDMI_GAMUT_DATA12			S5P_HDMI_BASE(0xB50)
+#define S5P_HDMI_GAMUT_DATA13			S5P_HDMI_BASE(0xB54)
+#define S5P_HDMI_GAMUT_DATA14			S5P_HDMI_BASE(0xB58)
+#define S5P_HDMI_GAMUT_DATA15			S5P_HDMI_BASE(0xB5c)
+#define S5P_HDMI_GAMUT_DATA16			S5P_HDMI_BASE(0xB60)
+#define S5P_HDMI_GAMUT_DATA17			S5P_HDMI_BASE(0xB64)
+#define S5P_HDMI_GAMUT_DATA18			S5P_HDMI_BASE(0xB68)
+#define S5P_HDMI_GAMUT_DATA19			S5P_HDMI_BASE(0xB6c)
+#define S5P_HDMI_GAMUT_DATA20			S5P_HDMI_BASE(0xB70)
+#define S5P_HDMI_GAMUT_DATA21			S5P_HDMI_BASE(0xB74)
+#define S5P_HDMI_GAMUT_DATA22			S5P_HDMI_BASE(0xB78)
+#define S5P_HDMI_GAMUT_DATA23			S5P_HDMI_BASE(0xB7c)
+#define S5P_HDMI_GAMUT_DATA24			S5P_HDMI_BASE(0xB80)
+#define S5P_HDMI_GAMUT_DATA25			S5P_HDMI_BASE(0xB84)
+#define S5P_HDMI_GAMUT_DATA26			S5P_HDMI_BASE(0xB88)
+#define S5P_HDMI_GAMUT_DATA27			S5P_HDMI_BASE(0xB8c)
+
+#define S5P_HDMI_VSI_CON			S5P_HDMI_BASE(0xC00)
+#define S5P_HDMI_VSI_HEADER0			S5P_HDMI_BASE(0xC10)
+#define S5P_HDMI_VSI_HEADER1			S5P_HDMI_BASE(0xC14)
+#define S5P_HDMI_VSI_HEADER2			S5P_HDMI_BASE(0xC18)
+#define S5P_HDMI_VSI_DATA00			S5P_HDMI_BASE(0xC20)
+#define S5P_HDMI_VSI_DATA01			S5P_HDMI_BASE(0xC24)
+#define S5P_HDMI_VSI_DATA02			S5P_HDMI_BASE(0xC28)
+#define S5P_HDMI_VSI_DATA03			S5P_HDMI_BASE(0xC2c)
+#define S5P_HDMI_VSI_DATA04			S5P_HDMI_BASE(0xC30)
+#define S5P_HDMI_VSI_DATA05			S5P_HDMI_BASE(0xC34)
+#define S5P_HDMI_VSI_DATA06			S5P_HDMI_BASE(0xC38)
+#define S5P_HDMI_VSI_DATA07			S5P_HDMI_BASE(0xC3c)
+#define S5P_HDMI_VSI_DATA08			S5P_HDMI_BASE(0xC40)
+#define S5P_HDMI_VSI_DATA09			S5P_HDMI_BASE(0xC44)
+#define S5P_HDMI_VSI_DATA10			S5P_HDMI_BASE(0xC48)
+#define S5P_HDMI_VSI_DATA11			S5P_HDMI_BASE(0xC4c)
+#define S5P_HDMI_VSI_DATA12			S5P_HDMI_BASE(0xC50)
+#define S5P_HDMI_VSI_DATA13			S5P_HDMI_BASE(0xC54)
+#define S5P_HDMI_VSI_DATA14			S5P_HDMI_BASE(0xC58)
+#define S5P_HDMI_VSI_DATA15			S5P_HDMI_BASE(0xC5c)
+#define S5P_HDMI_VSI_DATA16			S5P_HDMI_BASE(0xC60)
+#define S5P_HDMI_VSI_DATA17			S5P_HDMI_BASE(0xC64)
+#define S5P_HDMI_VSI_DATA18			S5P_HDMI_BASE(0xC68)
+#define S5P_HDMI_VSI_DATA19			S5P_HDMI_BASE(0xC6c)
+#define S5P_HDMI_VSI_DATA20			S5P_HDMI_BASE(0xC70)
+#define S5P_HDMI_VSI_DATA21			S5P_HDMI_BASE(0xC74)
+#define S5P_HDMI_VSI_DATA22			S5P_HDMI_BASE(0xC78)
+#define S5P_HDMI_VSI_DATA23			S5P_HDMI_BASE(0xC7c)
+#define S5P_HDMI_VSI_DATA24			S5P_HDMI_BASE(0xC80)
+#define S5P_HDMI_VSI_DATA25			S5P_HDMI_BASE(0xC84)
+#define S5P_HDMI_VSI_DATA26			S5P_HDMI_BASE(0xC88)
+#define S5P_HDMI_VSI_DATA27			S5P_HDMI_BASE(0xC8c)
+
+#define S5P_HDMI_DC_CONTROL			S5P_HDMI_BASE(0xD00)
+#define S5P_HDMI_VIDEO_PATTERN_GEN		S5P_HDMI_BASE(0xD04)
+#define S5P_HDMI_HPD_GEN0			S5P_HDMI_BASE(0xD08)
+#define S5P_HDMI_HPD_GEN1			S5P_HDMI_BASE(0xD0C)
+#define S5P_HDMI_HPD_GEN2			S5P_HDMI_BASE(0xD10)
+#define S5P_HDMI_HPD_GEN3			S5P_HDMI_BASE(0xD14)
+
+#define S5P_HDMI_DIM_CON			S5P_HDMI_BASE(0xD30)
+
+#define S5P_HDMI_HDCP_RX_SHA1_0_0		S5P_HDMI_BASE(0x7000)
+#define S5P_HDMI_HDCP_RX_SHA1_0_1		S5P_HDMI_BASE(0x7004)
+#define S5P_HDMI_HDCP_RX_SHA1_0_2		S5P_HDMI_BASE(0x7008)
+#define S5P_HDMI_HDCP_RX_SHA1_0_3		S5P_HDMI_BASE(0x700c)
+#define S5P_HDMI_HDCP_RX_SHA1_1_0		S5P_HDMI_BASE(0x7010)
+#define S5P_HDMI_HDCP_RX_SHA1_1_1		S5P_HDMI_BASE(0x7014)
+#define S5P_HDMI_HDCP_RX_SHA1_1_2		S5P_HDMI_BASE(0x7018)
+#define S5P_HDMI_HDCP_RX_SHA1_1_3		S5P_HDMI_BASE(0x701c)
+#define S5P_HDMI_HDCP_RX_SHA1_2_0		S5P_HDMI_BASE(0x7020)
+#define S5P_HDMI_HDCP_RX_SHA1_2_1		S5P_HDMI_BASE(0x7024)
+#define S5P_HDMI_HDCP_RX_SHA1_2_2		S5P_HDMI_BASE(0x7028)
+#define S5P_HDMI_HDCP_RX_SHA1_2_3		S5P_HDMI_BASE(0x702c)
+#define S5P_HDMI_HDCP_RX_SHA1_3_0		S5P_HDMI_BASE(0x7030)
+#define S5P_HDMI_HDCP_RX_SHA1_3_1		S5P_HDMI_BASE(0x7034)
+#define S5P_HDMI_HDCP_RX_SHA1_3_2		S5P_HDMI_BASE(0x7038)
+#define S5P_HDMI_HDCP_RX_SHA1_3_3		S5P_HDMI_BASE(0x703c)
+#define S5P_HDMI_HDCP_RX_SHA1_4_0		S5P_HDMI_BASE(0x7040)
+#define S5P_HDMI_HDCP_RX_SHA1_4_1		S5P_HDMI_BASE(0x7044)
+#define S5P_HDMI_HDCP_RX_SHA1_4_2		S5P_HDMI_BASE(0x7048)
+#define S5P_HDMI_HDCP_RX_SHA1_4_3		S5P_HDMI_BASE(0x704c)
+
+#define S5P_HDMI_HDCP_RX_KSV_0_0		S5P_HDMI_BASE(0x7050)
+#define S5P_HDMI_HDCP_RX_KSV_0_1		S5P_HDMI_BASE(0x7054)
+#define S5P_HDMI_HDCP_RX_KSV_0_2		S5P_HDMI_BASE(0x7058)
+#define S5P_HDMI_HDCP_RX_KSV_0_3		S5P_HDMI_BASE(0x705c)
+#define S5P_HDMI_HDCP_RX_KSV_0_4		S5P_HDMI_BASE(0x7060)
+
+#define S5P_HDMI_HDCP_KSV_LIST_CON		S5P_HDMI_BASE(0x7064)
+#define S5P_HDMI_HDCP_SHA_RESULT		S5P_HDMI_BASE(0x7070)
+#define S5P_HDMI_HDCP_CTRL1			S5P_HDMI_BASE(0x7080)
+#define S5P_HDMI_HDCP_CTRL2			S5P_HDMI_BASE(0x7084)
+#define S5P_HDMI_HDCP_CHECK_RESULT		S5P_HDMI_BASE(0x7090)
+
+#define S5P_HDMI_HDCP_BKSV_0_0			S5P_HDMI_BASE(0x70a0)
+#define S5P_HDMI_HDCP_BKSV_0_1			S5P_HDMI_BASE(0x70a4)
+#define S5P_HDMI_HDCP_BKSV_0_2			S5P_HDMI_BASE(0x70a8)
+#define S5P_HDMI_HDCP_BKSV_0_3			S5P_HDMI_BASE(0x70ac)
+#define S5P_HDMI_HDCP_BKSV_1			S5P_HDMI_BASE(0x70b0)
+
+#define S5P_HDMI_HDCP_AKSV_0_0			S5P_HDMI_BASE(0x70c0)
+#define S5P_HDMI_HDCP_AKSV_0_1			S5P_HDMI_BASE(0x70c4)
+#define S5P_HDMI_HDCP_AKSV_0_2			S5P_HDMI_BASE(0x70c8)
+#define S5P_HDMI_HDCP_AKSV_0_3			S5P_HDMI_BASE(0x70cc)
+#define S5P_HDMI_HDCP_AKSV_1			S5P_HDMI_BASE(0x70d0)
+
+#define S5P_HDMI_HDCP_An_0_0			S5P_HDMI_BASE(0x70e0)
+#define S5P_HDMI_HDCP_An_0_1			S5P_HDMI_BASE(0x70e4)
+#define S5P_HDMI_HDCP_An_0_2			S5P_HDMI_BASE(0x70e8)
+#define S5P_HDMI_HDCP_An_0_3			S5P_HDMI_BASE(0x70ec)
+#define S5P_HDMI_HDCP_An_1_0			S5P_HDMI_BASE(0x70f0)
+#define S5P_HDMI_HDCP_An_1_1			S5P_HDMI_BASE(0x70f4)
+#define S5P_HDMI_HDCP_An_1_2			S5P_HDMI_BASE(0x70f8)
+#define S5P_HDMI_HDCP_An_1_3			S5P_HDMI_BASE(0x70fc)
+
+#define S5P_HDMI_HDCP_BCAPS			S5P_HDMI_BASE(0x7100)
+#define S5P_HDMI_HDCP_BSTATUS_0			S5P_HDMI_BASE(0x7110)
+#define S5P_HDMI_HDCP_BSTATUS_1			S5P_HDMI_BASE(0x7114)
+#define S5P_HDMI_HDCP_Ri_0			S5P_HDMI_BASE(0x7140)
+#define S5P_HDMI_HDCP_Ri_1			S5P_HDMI_BASE(0x7144)
+#define S5P_HDMI_HDCP_I2C_INT			S5P_HDMI_BASE(0x7180)
+#define S5P_HDMI_HDCP_AN_INT			S5P_HDMI_BASE(0x7190)
+#define S5P_HDMI_HDCP_WDT_INT			S5P_HDMI_BASE(0x71a0)
+#define S5P_HDMI_HDCP_RI_INT			S5P_HDMI_BASE(0x71b0)
+
+#define S5P_HDMI_HDCP_RI_COMPARE_0		S5P_HDMI_BASE(0x71d0)
+#define S5P_HDMI_HDCP_RI_COMPARE_1		S5P_HDMI_BASE(0x71d4)
+#define S5P_HDMI_HDCP_FRAME_COUNT		S5P_HDMI_BASE(0x71e0)
+
+#define S5P_HDMI_RGB_ROUND_EN			S5P_HDMI_BASE(0xD500)
+
+#define S5P_HDMI_VACT_SPACE_R_0			S5P_HDMI_BASE(0xD504)
+#define S5P_HDMI_VACT_SPACE_R_1			S5P_HDMI_BASE(0xD508)
+
+#define S5P_HDMI_VACT_SPACE_G_0			S5P_HDMI_BASE(0xD50C)
+#define S5P_HDMI_VACT_SPACE_G_1			S5P_HDMI_BASE(0xD510)
+
+#define S5P_HDMI_VACT_SPACE_B_0			S5P_HDMI_BASE(0xD514)
+#define S5P_HDMI_VACT_SPACE_B_1			S5P_HDMI_BASE(0xD518)
+
+#define S5P_HDMI_BLUE_SCREEN_B_0		S5P_HDMI_BASE(0xD520)
+#define S5P_HDMI_BLUE_SCREEN_B_1		S5P_HDMI_BASE(0xD524)
+#define S5P_HDMI_BLUE_SCREEN_G_0		S5P_HDMI_BASE(0xD528)
+#define S5P_HDMI_BLUE_SCREEN_G_1		S5P_HDMI_BASE(0xD52C)
+#define S5P_HDMI_BLUE_SCREEN_R_0		S5P_HDMI_BASE(0xD530)
+#define S5P_HDMI_BLUE_SCREEN_R_1		S5P_HDMI_BASE(0xD534)
+
+/* HDMISPDIFregister */
+#define S5P_HDMI_SPDIFIN_CLK_CTRL		S5P_HDMI_SPDIF_BASE(0x0000)
+#define S5P_HDMI_SPDIFIN_OP_CTRL		S5P_HDMI_SPDIF_BASE(0x0004)
+#define S5P_HDMI_SPDIFIN_IRQ_MASK		S5P_HDMI_SPDIF_BASE(0x0008)
+#define S5P_HDMI_SPDIFIN_IRQ_STATUS		S5P_HDMI_SPDIF_BASE(0x000C)
+#define S5P_HDMI_SPDIFIN_CONFIG_1		S5P_HDMI_SPDIF_BASE(0x0010)
+#define S5P_HDMI_SPDIFIN_CONFIG_2		S5P_HDMI_SPDIF_BASE(0x0014)
+#define S5P_HDMI_SPDIFIN_USER_VALUE_1		S5P_HDMI_SPDIF_BASE(0x0020)
+#define S5P_HDMI_SPDIFIN_USER_VALUE_2		S5P_HDMI_SPDIF_BASE(0x0024)
+#define S5P_HDMI_SPDIFIN_USER_VALUE_3		S5P_HDMI_SPDIF_BASE(0x0028)
+#define S5P_HDMI_SPDIFIN_USER_VALUE_4		S5P_HDMI_SPDIF_BASE(0x002C)
+#define S5P_HDMI_SPDIFIN_CH_STATUS_0_1		S5P_HDMI_SPDIF_BASE(0x0030)
+#define S5P_HDMI_SPDIFIN_CH_STATUS_0_2		S5P_HDMI_SPDIF_BASE(0x0034)
+#define S5P_HDMI_SPDIFIN_CH_STATUS_0_3		S5P_HDMI_SPDIF_BASE(0x0038)
+#define S5P_HDMI_SPDIFIN_CH_STATUS_0_4		S5P_HDMI_SPDIF_BASE(0x003C)
+#define S5P_HDMI_SPDIFIN_CH_STATUS_1		S5P_HDMI_SPDIF_BASE(0x0040)
+#define S5P_HDMI_SPDIFIN_FRAME_PERIOD_1		S5P_HDMI_SPDIF_BASE(0x0048)
+#define S5P_HDMI_SPDIFIN_FRAME_PERIOD_2		S5P_HDMI_SPDIF_BASE(0x004C)
+#define S5P_HDMI_SPDIFIN_Pc_INFO_1		S5P_HDMI_SPDIF_BASE(0x0050)
+#define S5P_HDMI_SPDIFIN_Pc_INFO_2		S5P_HDMI_SPDIF_BASE(0x0054)
+#define S5P_HDMI_SPDIFIN_Pd_INFO_1		S5P_HDMI_SPDIF_BASE(0x0058)
+#define S5P_HDMI_SPDIFIN_Pd_INFO_2		S5P_HDMI_SPDIF_BASE(0x005C)
+#define S5P_HDMI_SPDIFIN_DATA_BUF_0_1		S5P_HDMI_SPDIF_BASE(0x0060)
+#define S5P_HDMI_SPDIFIN_DATA_BUF_0_2		S5P_HDMI_SPDIF_BASE(0x0064)
+#define S5P_HDMI_SPDIFIN_DATA_BUF_0_3		S5P_HDMI_SPDIF_BASE(0x0068)
+#define S5P_HDMI_SPDIFIN_USER_BUF_0		S5P_HDMI_SPDIF_BASE(0x006C)
+#define S5P_HDMI_SPDIFIN_DATA_BUF_1_1		S5P_HDMI_SPDIF_BASE(0x0070)
+#define S5P_HDMI_SPDIFIN_DATA_BUF_1_2		S5P_HDMI_SPDIF_BASE(0x0074)
+#define S5P_HDMI_SPDIFIN_DATA_BUF_1_3		S5P_HDMI_SPDIF_BASE(0x0078)
+#define S5P_HDMI_SPDIFIN_USER_BUF_1		S5P_HDMI_SPDIF_BASE(0x007C)
+
+/* HDMII2Sregister */
+#define S5P_HDMI_I2S_CLK_CON			S5P_HDMI_I2S_BASE(0x000)
+#define S5P_HDMI_I2S_CON_1			S5P_HDMI_I2S_BASE(0x004)
+#define S5P_HDMI_I2S_CON_2			S5P_HDMI_I2S_BASE(0x008)
+#define S5P_HDMI_I2S_PIN_SEL_0			S5P_HDMI_I2S_BASE(0x00c)
+#define S5P_HDMI_I2S_PIN_SEL_1			S5P_HDMI_I2S_BASE(0x010)
+#define S5P_HDMI_I2S_PIN_SEL_2			S5P_HDMI_I2S_BASE(0x014)
+#define S5P_HDMI_I2S_PIN_SEL_3			S5P_HDMI_I2S_BASE(0x018)
+#define S5P_HDMI_I2S_DSD_CON			S5P_HDMI_I2S_BASE(0x01c)
+#define S5P_HDMI_I2S_MUX_CON			S5P_HDMI_I2S_BASE(0x020)
+#define S5P_HDMI_I2S_CH_ST_CON			S5P_HDMI_I2S_BASE(0x024)
+#define S5P_HDMI_I2S_CH_ST_0			S5P_HDMI_I2S_BASE(0x028)
+#define S5P_HDMI_I2S_CH_ST_1			S5P_HDMI_I2S_BASE(0x02c)
+#define S5P_HDMI_I2S_CH_ST_2			S5P_HDMI_I2S_BASE(0x030)
+#define S5P_HDMI_I2S_CH_ST_3			S5P_HDMI_I2S_BASE(0x034)
+#define S5P_HDMI_I2S_CH_ST_4			S5P_HDMI_I2S_BASE(0x038)
+#define S5P_HDMI_I2S_CH_ST_SH_0			S5P_HDMI_I2S_BASE(0x03c)
+#define S5P_HDMI_I2S_CH_ST_SH_1			S5P_HDMI_I2S_BASE(0x040)
+#define S5P_HDMI_I2S_CH_ST_SH_2			S5P_HDMI_I2S_BASE(0x044)
+#define S5P_HDMI_I2S_CH_ST_SH_3			S5P_HDMI_I2S_BASE(0x048)
+#define S5P_HDMI_I2S_CH_ST_SH_4			S5P_HDMI_I2S_BASE(0x04c)
+#define S5P_HDMI_I2S_VD_DATA			S5P_HDMI_I2S_BASE(0x050)
+#define S5P_HDMI_I2S_MUX_CH			S5P_HDMI_I2S_BASE(0x054)
+#define S5P_HDMI_I2S_MUX_CUV			S5P_HDMI_I2S_BASE(0x058)
+#define S5P_HDMI_I2S_IRQ_MASK			S5P_HDMI_I2S_BASE(0x05c)
+#define S5P_HDMI_I2S_IRQ_STATUS			S5P_HDMI_I2S_BASE(0x060)
+
+/* HDMITGregister */
+#define S5P_HDMI_TG_CMD				S5P_HDMI_TG_BASE(0x000)
+#define S5P_HDMI_TG_CFG				S5P_HDMI_TG_BASE(0x004)
+#define S5P_HDMI_TG_CB_SZ			S5P_HDMI_TG_BASE(0x008)
+#define S5P_HDMI_TG_INDELAY_L			S5P_HDMI_TG_BASE(0x00c)
+#define S5P_HDMI_TG_INDELAY_H			S5P_HDMI_TG_BASE(0x010)
+#define S5P_HDMI_TG_POL_CTRL			S5P_HDMI_TG_BASE(0x014)
+#define S5P_HDMI_TG_H_FSZ_L			S5P_HDMI_TG_BASE(0x018)
+#define S5P_HDMI_TG_H_FSZ_H			S5P_HDMI_TG_BASE(0x01c)
+#define S5P_HDMI_TG_HACT_ST_L			S5P_HDMI_TG_BASE(0x020)
+#define S5P_HDMI_TG_HACT_ST_H			S5P_HDMI_TG_BASE(0x024)
+#define S5P_HDMI_TG_HACT_SZ_L			S5P_HDMI_TG_BASE(0x028)
+#define S5P_HDMI_TG_HACT_SZ_H			S5P_HDMI_TG_BASE(0x02c)
+#define S5P_HDMI_TG_V_FSZ_L			S5P_HDMI_TG_BASE(0x030)
+#define S5P_HDMI_TG_V_FSZ_H			S5P_HDMI_TG_BASE(0x034)
+#define S5P_HDMI_TG_VSYNC_L			S5P_HDMI_TG_BASE(0x038)
+#define S5P_HDMI_TG_VSYNC_H			S5P_HDMI_TG_BASE(0x03c)
+#define S5P_HDMI_TG_VSYNC2_L			S5P_HDMI_TG_BASE(0x040)
+#define S5P_HDMI_TG_VSYNC2_H			S5P_HDMI_TG_BASE(0x044)
+#define S5P_HDMI_TG_VACT_ST_L			S5P_HDMI_TG_BASE(0x048)
+#define S5P_HDMI_TG_VACT_ST_H			S5P_HDMI_TG_BASE(0x04c)
+#define S5P_HDMI_TG_VACT_SZ_L			S5P_HDMI_TG_BASE(0x050)
+#define S5P_HDMI_TG_VACT_SZ_H			S5P_HDMI_TG_BASE(0x054)
+#define S5P_HDMI_TG_FIELD_CHG_L			S5P_HDMI_TG_BASE(0x058)
+#define S5P_HDMI_TG_FIELD_CHG_H			S5P_HDMI_TG_BASE(0x05c)
+#define S5P_HDMI_TG_VACT_ST2_L			S5P_HDMI_TG_BASE(0x060)
+#define S5P_HDMI_TG_VACT_ST2_H			S5P_HDMI_TG_BASE(0x064)
+
+#define S5P_HDMI_TG_VACT_ST3_L			S5P_HDMI_TG_BASE(0x068)
+#define S5P_HDMI_TG_VACT_ST3_H			S5P_HDMI_TG_BASE(0x06c)
+#define S5P_HDMI_TG_VACT_ST4_L			S5P_HDMI_TG_BASE(0x070)
+#define S5P_HDMI_TG_VACT_ST4_H			S5P_HDMI_TG_BASE(0x074)
+
+#define S5P_HDMI_TG_VSYNC_TOP_HDMI_L		S5P_HDMI_TG_BASE(0x078)
+#define S5P_HDMI_TG_VSYNC_TOP_HDMI_H		S5P_HDMI_TG_BASE(0x07c)
+#define S5P_HDMI_TG_VSYNC_BOT_HDMI_L		S5P_HDMI_TG_BASE(0x080)
+#define S5P_HDMI_TG_VSYNC_BOT_HDMI_H		S5P_HDMI_TG_BASE(0x084)
+#define S5P_HDMI_TG_FIELD_TOP_HDMI_L		S5P_HDMI_TG_BASE(0x088)
+#define S5P_HDMI_TG_FIELD_TOP_HDMI_H		S5P_HDMI_TG_BASE(0x08c)
+#define S5P_HDMI_TG_FIELD_BOT_HDMI_L		S5P_HDMI_TG_BASE(0x090)
+#define S5P_HDMI_TG_FIELD_BOT_HDMI_H		S5P_HDMI_TG_BASE(0x094)
+
+#define S5P_HDMI_TG_3D				S5P_HDMI_TG_BASE(0x0F0)
+
+#define S5P_HDMI_MHL_HSYNC_WIDTH		S5P_HDMI_TG_BASE(0x17C)
+#define S5P_HDMI_MHL_VSYNC_WIDTH		S5P_HDMI_TG_BASE(0x180)
+#define S5P_HDMI_MHL_CLK_INV			S5P_HDMI_TG_BASE(0x184)
+
+/* HDMIE-FUSEregiseter */
+#define S5P_HDMI_EFUSE_CTRL			S5P_HDMI_EFUSE_BASE(0x000)
+#define S5P_HDMI_EFUSE_STATUS			S5P_HDMI_EFUSE_BASE(0x004)
+#define S5P_HDMI_EFUSE_ADDR_WIDTH		S5P_HDMI_EFUSE_BASE(0x008)
+#define S5P_HDMI_EFUSE_SIGDEV_ASSERT		S5P_HDMI_EFUSE_BASE(0x00c)
+#define S5P_HDMI_EFUSE_SIGDEV_DEASSERT		S5P_HDMI_EFUSE_BASE(0x010)
+#define S5P_HDMI_EFUSE_PRCHG_ASSERT		S5P_HDMI_EFUSE_BASE(0x014)
+#define S5P_HDMI_EFUSE_PRCHG_DEASSERT		S5P_HDMI_EFUSE_BASE(0x018)
+#define S5P_HDMI_EFUSE_FSET_ASSERT		S5P_HDMI_EFUSE_BASE(0x01c)
+#define S5P_HDMI_EFUSE_FSET_DEASSERT		S5P_HDMI_EFUSE_BASE(0x020)
+#define S5P_HDMI_EFUSE_SENSING			S5P_HDMI_EFUSE_BASE(0x024)
+#define S5P_HDMI_EFUSE_SCK_ASSERT		S5P_HDMI_EFUSE_BASE(0x028)
+#define S5P_HDMI_EFUSE_SCK_DEASSERT		S5P_HDMI_EFUSE_BASE(0x02c)
+#define S5P_HDMI_EFUSE_SDOUT_OFFSET		S5P_HDMI_EFUSE_BASE(0x030)
+#define S5P_HDMI_EFUSE_READ_OFFSET		S5P_HDMI_EFUSE_BASE(0x034)
+#else
+
+#define S5P_HDMI_I2C_PHY_BASE(x)		(x)
+
+#define HDMI_I2C_CON				S5P_HDMI_I2C_PHY_BASE(0x0000)
+#define HDMI_I2C_STAT				S5P_HDMI_I2C_PHY_BASE(0x0004)
+#define HDMI_I2C_ADD				S5P_HDMI_I2C_PHY_BASE(0x0008)
+#define HDMI_I2C_DS				S5P_HDMI_I2C_PHY_BASE(0x000c)
+#define HDMI_I2C_LC				S5P_HDMI_I2C_PHY_BASE(0x0010)
+
+#define S5P_HDMI_CTRL_BASE(x)			(x)
+#define S5P_HDMI_BASE(x)			((x) + 0x00010000)
+#define S5P_HDMI_SPDIF_BASE(x)			((x) + 0x00030000)
+#define S5P_HDMI_I2S_BASE(x)			((x) + 0x00040000)
+#define S5P_HDMI_TG_BASE(x)			((x) + 0x00050000)
+#define S5P_HDMI_EFUSE_BASE(x)			((x) + 0x00060000)
+
+#define S5P_HDMI_INTC_CON			S5P_HDMI_CTRL_BASE(0x0000)
+#define S5P_HDMI_INTC_FLAG			S5P_HDMI_CTRL_BASE(0x0004)
+#define S5P_HDMI_HDCP_KEY_LOAD			S5P_HDMI_CTRL_BASE(0x0008)
+#define S5P_HDMI_HPD_STATUS			S5P_HDMI_CTRL_BASE(0x000C)
+#define S5P_HDMI_AUDIO_CLKSEL			S5P_HDMI_CTRL_BASE(0x0010)
+#define S5P_HDMI_PHY_RSTOUT			S5P_HDMI_CTRL_BASE(0x0014)
+#define S5P_HDMI_PHY_VPLL			S5P_HDMI_CTRL_BASE(0x0018)
+#define S5P_HDMI_PHY_CMU			S5P_HDMI_CTRL_BASE(0x001C)
+#define S5P_HDMI_CORE_RSTOUT			S5P_HDMI_CTRL_BASE(0x0020)
+
+#define S5P_HDMI_CON_0				S5P_HDMI_BASE(0x0000)
+#define S5P_HDMI_CON_1				S5P_HDMI_BASE(0x0004)
+#define S5P_HDMI_CON_2				S5P_HDMI_BASE(0x0008)
+#define S5P_HDMI_SYS_STATUS			S5P_HDMI_BASE(0x0010)
+#define S5P_HDMI_PHY_STATUS			S5P_HDMI_BASE(0x0014)
+#define S5P_HDMI_STATUS_EN			S5P_HDMI_BASE(0x0020)
+#define S5P_HDMI_HPD				S5P_HDMI_BASE(0x0030)
+#define S5P_HDMI_MODE_SEL			S5P_HDMI_BASE(0x0040)
+#define S5P_HDMI_ENC_EN				S5P_HDMI_BASE(0x0044)
+
+#define S5P_HDMI_BLUE_SCREEN_0			S5P_HDMI_BASE(0x0050)
+#define S5P_HDMI_BLUE_SCREEN_1			S5P_HDMI_BASE(0x0054)
+#define S5P_HDMI_BLUE_SCREEN_2			S5P_HDMI_BASE(0x0058)
+
+#define S5P_HDMI_YMAX				S5P_HDMI_BASE(0x0060)
+#define S5P_HDMI_YMIN				S5P_HDMI_BASE(0x0064)
+#define S5P_HDMI_CMAX				S5P_HDMI_BASE(0x0068)
+#define S5P_HDMI_CMIN				S5P_HDMI_BASE(0x006C)
+
+#define S5P_HDMI_H_BLANK_0			S5P_HDMI_BASE(0x00A0)
+#define S5P_HDMI_H_BLANK_1			S5P_HDMI_BASE(0x00A4)
+#define S5P_HDMI_V_BLANK_0			S5P_HDMI_BASE(0x00B0)
+#define S5P_HDMI_V_BLANK_1			S5P_HDMI_BASE(0x00B4)
+#define S5P_HDMI_V_BLANK_2			S5P_HDMI_BASE(0x00B8)
+#define S5P_HDMI_H_V_LINE_0			S5P_HDMI_BASE(0x00C0)
+#define S5P_HDMI_H_V_LINE_1			S5P_HDMI_BASE(0x00C4)
+#define S5P_HDMI_H_V_LINE_2			S5P_HDMI_BASE(0x00C8)
+
+#define S5P_HDMI_SYNC_MODE			S5P_HDMI_BASE(0x00E4)
+#define S5P_HDMI_INT_PRO_MODE			S5P_HDMI_BASE(0x00E8)
+
+#define S5P_HDMI_V_BLANK_F_0			S5P_HDMI_BASE(0x0110)
+#define S5P_HDMI_V_BLANK_F_1			S5P_HDMI_BASE(0x0114)
+#define S5P_HDMI_V_BLANK_F_2			S5P_HDMI_BASE(0x0118)
+#define S5P_HDMI_H_SYNC_GEN_0			S5P_HDMI_BASE(0x0120)
+#define S5P_HDMI_H_SYNC_GEN_1			S5P_HDMI_BASE(0x0124)
+#define S5P_HDMI_H_SYNC_GEN_2			S5P_HDMI_BASE(0x0128)
+#define S5P_HDMI_V_SYNC_GEN_1_0			S5P_HDMI_BASE(0x0130)
+#define S5P_HDMI_V_SYNC_GEN_1_1			S5P_HDMI_BASE(0x0134)
+#define S5P_HDMI_V_SYNC_GEN_1_2			S5P_HDMI_BASE(0x0138)
+#define S5P_HDMI_V_SYNC_GEN_2_0			S5P_HDMI_BASE(0x0140)
+#define S5P_HDMI_V_SYNC_GEN_2_1			S5P_HDMI_BASE(0x0144)
+#define S5P_HDMI_V_SYNC_GEN_2_2			S5P_HDMI_BASE(0x0148)
+#define S5P_HDMI_V_SYNC_GEN_3_0			S5P_HDMI_BASE(0x0150)
+#define S5P_HDMI_V_SYNC_GEN_3_1			S5P_HDMI_BASE(0x0154)
+#define S5P_HDMI_V_SYNC_GEN_3_2			S5P_HDMI_BASE(0x0158)
+
+#define S5P_HDMI_ASP_CON			S5P_HDMI_BASE(0x0160)
+#define S5P_HDMI_ASP_SP_FLAT			S5P_HDMI_BASE(0x0164)
+#define S5P_HDMI_ASP_CHCFG0			S5P_HDMI_BASE(0x0170)
+#define S5P_HDMI_ASP_CHCFG1			S5P_HDMI_BASE(0x0174)
+#define S5P_HDMI_ASP_CHCFG2			S5P_HDMI_BASE(0x0178)
+#define S5P_HDMI_ASP_CHCFG3			S5P_HDMI_BASE(0x017C)
+
+#define S5P_HDMI_ACR_CON			S5P_HDMI_BASE(0x0180)
+#define S5P_HDMI_ACR_MCTS0			S5P_HDMI_BASE(0x0184)
+#define S5P_HDMI_ACR_MCTS1			S5P_HDMI_BASE(0x0188)
+#define S5P_HDMI_ACR_MCTS2			S5P_HDMI_BASE(0x018C)
+#define S5P_HDMI_ACR_CTS0			S5P_HDMI_BASE(0x0190)
+#define S5P_HDMI_ACR_CTS1			S5P_HDMI_BASE(0x0194)
+#define S5P_HDMI_ACR_CTS2			S5P_HDMI_BASE(0x0198)
+#define S5P_HDMI_ACR_N0				S5P_HDMI_BASE(0x01A0)
+#define S5P_HDMI_ACR_N1				S5P_HDMI_BASE(0x01A4)
+#define S5P_HDMI_ACR_N2				S5P_HDMI_BASE(0x01A8)
+#define S5P_HDMI_ACR_LSB2			S5P_HDMI_BASE(0x01B0)
+#define S5P_HDMI_ACR_TXCNT			S5P_HDMI_BASE(0x01B4)
+#define S5P_HDMI_ACR_TXINTERVAL			S5P_HDMI_BASE(0x01B8)
+#define S5P_HDMI_ACR_CTS_OFFSET			S5P_HDMI_BASE(0x01BC)
+
+#define S5P_HDMI_GCP_CON			S5P_HDMI_BASE(0x01C0)
+#define S5P_HDMI_GCP_BYTE1			S5P_HDMI_BASE(0x01D0)
+#define S5P_HDMI_GCP_BYTE2			S5P_HDMI_BASE(0x01D4)
+#define S5P_HDMI_GCP_BYTE3			S5P_HDMI_BASE(0x01D8)
+
+#define S5P_HDMI_ACP_CON			S5P_HDMI_BASE(0x01E0)
+#define S5P_HDMI_ACP_TYPE			S5P_HDMI_BASE(0x01E4)
+#define S5P_HDMI_ACP_DATA			S5P_HDMI_BASE(0x0200)
+
+#define S5P_HDMI_ISRC_CON			S5P_HDMI_BASE(0x0250)
+#define S5P_HDMI_ISRC1_HEADER1			S5P_HDMI_BASE(0x0264)
+#define S5P_HDMI_ISRC1_DATA			S5P_HDMI_BASE(0x0270)
+#define S5P_HDMI_ISRC2_DATA			S5P_HDMI_BASE(0x02b0)
+
+#define S5P_HDMI_AVI_CON			S5P_HDMI_BASE(0x0300)
+#define S5P_HDMI_AVI_CHECK_SUM			S5P_HDMI_BASE(0x0310)
+#define S5P_HDMI_AVI_DATA			S5P_HDMI_BASE(0x0320)
+
+#define S5P_HDMI_AUI_CON			S5P_HDMI_BASE(0x0360)
+#define S5P_HDMI_AUI_CHECK_SUM			S5P_HDMI_BASE(0x0370)
+
+#define S5P_HDMI_AUI_BYTE1			S5P_HDMI_BASE(0x0380)
+#define S5P_HDMI_AUI_BYTE2			S5P_HDMI_BASE(0x0384)
+#define S5P_HDMI_AUI_BYTE3			S5P_HDMI_BASE(0x0388)
+#define S5P_HDMI_AUI_BYTE4			S5P_HDMI_BASE(0x038c)
+#define S5P_HDMI_AUI_BYTE5			S5P_HDMI_BASE(0x0390)
+
+#define S5P_HDMI_MPG_CON			S5P_HDMI_BASE(0x03A0)
+#define S5P_HDMI_MPG_CHECK_SUM			S5P_HDMI_BASE(0x03B0)
+#define S5P_HDMI_MPG_DATA			S5P_HDMI_BASE(0x03c0)
+
+#define S5P_HDMI_SPD_CON			S5P_HDMI_BASE(0x0400)
+#define S5P_HDMI_SPD_HEADER			S5P_HDMI_BASE(0x0410)
+#define S5P_HDMI_SPD_DATA			S5P_HDMI_BASE(0x0420)
+
+#define S5P_HDMI_HDCP_RX_SHA1_0_0		S5P_HDMI_BASE(0x0600)
+#define S5P_HDMI_HDCP_RX_SHA1_0_1		S5P_HDMI_BASE(0x0604)
+#define S5P_HDMI_HDCP_RX_SHA1_0_2		S5P_HDMI_BASE(0x0608)
+#define S5P_HDMI_HDCP_RX_SHA1_0_3		S5P_HDMI_BASE(0x060C)
+#define S5P_HDMI_HDCP_RX_SHA1_1_0		S5P_HDMI_BASE(0x0610)
+#define S5P_HDMI_HDCP_RX_SHA1_1_1		S5P_HDMI_BASE(0x0614)
+#define S5P_HDMI_HDCP_RX_SHA1_1_2		S5P_HDMI_BASE(0x0618)
+#define S5P_HDMI_HDCP_RX_SHA1_1_3		S5P_HDMI_BASE(0x061C)
+#define S5P_HDMI_HDCP_RX_SHA1_2_0		S5P_HDMI_BASE(0x0620)
+#define S5P_HDMI_HDCP_RX_SHA1_2_1		S5P_HDMI_BASE(0x0624)
+#define S5P_HDMI_HDCP_RX_SHA1_2_2		S5P_HDMI_BASE(0x0628)
+#define S5P_HDMI_HDCP_RX_SHA1_2_3		S5P_HDMI_BASE(0x062C)
+#define S5P_HDMI_HDCP_RX_SHA1_3_0		S5P_HDMI_BASE(0x0630)
+#define S5P_HDMI_HDCP_RX_SHA1_3_1		S5P_HDMI_BASE(0x0634)
+#define S5P_HDMI_HDCP_RX_SHA1_3_2		S5P_HDMI_BASE(0x0638)
+#define S5P_HDMI_HDCP_RX_SHA1_3_3		S5P_HDMI_BASE(0x063C)
+#define S5P_HDMI_HDCP_RX_SHA1_4_0		S5P_HDMI_BASE(0x0640)
+#define S5P_HDMI_HDCP_RX_SHA1_4_1		S5P_HDMI_BASE(0x0644)
+#define S5P_HDMI_HDCP_RX_SHA1_4_2		S5P_HDMI_BASE(0x0648)
+#define S5P_HDMI_HDCP_RX_SHA1_4_3		S5P_HDMI_BASE(0x064C)
+
+#define S5P_HDMI_HDCP_RX_KSV_0_0		S5P_HDMI_BASE(0x0650)
+#define S5P_HDMI_HDCP_RX_KSV_0_1		S5P_HDMI_BASE(0x0654)
+#define S5P_HDMI_HDCP_RX_KSV_0_2		S5P_HDMI_BASE(0x0658)
+#define S5P_HDMI_HDCP_RX_KSV_0_3		S5P_HDMI_BASE(0x065C)
+#define S5P_HDMI_HDCP_RX_KSV_0_4		S5P_HDMI_BASE(0x0660)
+
+#define S5P_HDMI_HDCP_KSV_LIST_CON		S5P_HDMI_BASE(0x0664)
+#define S5P_HDMI_HDCP_SHA_RESULT		S5P_HDMI_BASE(0x0670)
+#define S5P_HDMI_HDCP_CTRL1			S5P_HDMI_BASE(0x0680)
+#define S5P_HDMI_HDCP_CTRL2			S5P_HDMI_BASE(0x0684)
+#define S5P_HDMI_HDCP_CHECK_RESULT		S5P_HDMI_BASE(0x0690)
+
+#define S5P_HDMI_HDCP_BKSV_0_0			S5P_HDMI_BASE(0x06A0)
+#define S5P_HDMI_HDCP_BKSV_0_1			S5P_HDMI_BASE(0x06A4)
+#define S5P_HDMI_HDCP_BKSV_0_2			S5P_HDMI_BASE(0x06A8)
+#define S5P_HDMI_HDCP_BKSV_0_3			S5P_HDMI_BASE(0x06AC)
+#define S5P_HDMI_HDCP_BKSV_1			S5P_HDMI_BASE(0x06B0)
+
+#define S5P_HDMI_HDCP_AKSV_0_0			S5P_HDMI_BASE(0x06C0)
+#define S5P_HDMI_HDCP_AKSV_0_1			S5P_HDMI_BASE(0x06C4)
+#define S5P_HDMI_HDCP_AKSV_0_2			S5P_HDMI_BASE(0x06C8)
+#define S5P_HDMI_HDCP_AKSV_0_3			S5P_HDMI_BASE(0x06CC)
+#define S5P_HDMI_HDCP_AKSV_1			S5P_HDMI_BASE(0x06D0)
+
+#define S5P_HDMI_HDCP_An_0_0			S5P_HDMI_BASE(0x06E0)
+#define S5P_HDMI_HDCP_An_0_1			S5P_HDMI_BASE(0x06E4)
+#define S5P_HDMI_HDCP_An_0_2			S5P_HDMI_BASE(0x06E8)
+#define S5P_HDMI_HDCP_An_0_3			S5P_HDMI_BASE(0x06EC)
+#define S5P_HDMI_HDCP_An_1_0			S5P_HDMI_BASE(0x06F0)
+#define S5P_HDMI_HDCP_An_1_1			S5P_HDMI_BASE(0x06F4)
+#define S5P_HDMI_HDCP_An_1_2			S5P_HDMI_BASE(0x06F8)
+#define S5P_HDMI_HDCP_An_1_3			S5P_HDMI_BASE(0x06FC)
+
+#define S5P_HDMI_HDCP_BCAPS			S5P_HDMI_BASE(0x0700)
+#define S5P_HDMI_HDCP_BSTATUS_0			S5P_HDMI_BASE(0x0710)
+#define S5P_HDMI_HDCP_BSTATUS_1			S5P_HDMI_BASE(0x0714)
+#define S5P_HDMI_HDCP_Ri_0			S5P_HDMI_BASE(0x0740)
+#define S5P_HDMI_HDCP_Ri_1			S5P_HDMI_BASE(0x0744)
+
+#define S5P_HDMI_HDCP_I2C_INT			S5P_HDMI_BASE(0x0780)
+#define S5P_HDMI_HDCP_AN_INT			S5P_HDMI_BASE(0x0790)
+#define S5P_HDMI_HDCP_WDT_INT			S5P_HDMI_BASE(0x07a0)
+#define S5P_HDMI_HDCP_RI_INT			S5P_HDMI_BASE(0x07b0)
+
+#define S5P_HDMI_HDCP_RI_COMPARE_0		S5P_HDMI_BASE(0x07d0)
+#define S5P_HDMI_HDCP_RI_COMPARE_1		S5P_HDMI_BASE(0x07d4)
+#define S5P_HDMI_HDCP_FRAME_COUNT		S5P_HDMI_BASE(0x07e0)
+
+#define S5P_HDMI_GAMUT_CON			S5P_HDMI_BASE(0x0500)
+#define S5P_HDMI_GAMUT_HEADER0			S5P_HDMI_BASE(0x0504)
+#define S5P_HDMI_GAMUT_HEADER1			S5P_HDMI_BASE(0x0508)
+#define S5P_HDMI_GAMUT_HEADER2			S5P_HDMI_BASE(0x050c)
+#define S5P_HDMI_GAMUT_DATA			S5P_HDMI_BASE(0x0510)
+
+#define S5P_HDMI_DC_CONTROL			S5P_HDMI_BASE(0x05C0)
+#define S5P_HDMI_VIDEO_PATTERN_GEN		S5P_HDMI_BASE(0x05C4)
+#define S5P_HDMI_HPD_GEN			S5P_HDMI_BASE(0x05C8)
+
+#define S5P_HDMI_SPDIFIN_CLK_CTRL		S5P_HDMI_SPDIF_BASE(0x0000)
+#define S5P_HDMI_SPDIFIN_OP_CTRL		S5P_HDMI_SPDIF_BASE(0x0004)
+#define S5P_HDMI_SPDIFIN_IRQ_MASK		S5P_HDMI_SPDIF_BASE(0x0008)
+#define S5P_HDMI_SPDIFIN_IRQ_STATUS		S5P_HDMI_SPDIF_BASE(0x000C)
+#define S5P_HDMI_SPDIFIN_CONFIG_1		S5P_HDMI_SPDIF_BASE(0x0010)
+#define S5P_HDMI_SPDIFIN_CONFIG_2		S5P_HDMI_SPDIF_BASE(0x0014)
+#define S5P_HDMI_SPDIFIN_USER_VALUE_1		S5P_HDMI_SPDIF_BASE(0x0020)
+#define S5P_HDMI_SPDIFIN_USER_VALUE_2		S5P_HDMI_SPDIF_BASE(0x0024)
+#define S5P_HDMI_SPDIFIN_USER_VALUE_3		S5P_HDMI_SPDIF_BASE(0x0028)
+#define S5P_HDMI_SPDIFIN_USER_VALUE_4		S5P_HDMI_SPDIF_BASE(0x002C)
+#define S5P_HDMI_SPDIFIN_CH_STATUS_0_1		S5P_HDMI_SPDIF_BASE(0x0030)
+#define S5P_HDMI_SPDIFIN_CH_STATUS_0_2		S5P_HDMI_SPDIF_BASE(0x0034)
+#define S5P_HDMI_SPDIFIN_CH_STATUS_0_3		S5P_HDMI_SPDIF_BASE(0x0038)
+#define S5P_HDMI_SPDIFIN_CH_STATUS_0_4		S5P_HDMI_SPDIF_BASE(0x003C)
+#define S5P_HDMI_SPDIFIN_CH_STATUS_1		S5P_HDMI_SPDIF_BASE(0x0040)
+#define S5P_HDMI_SPDIFIN_FRAME_PERIOD_1		S5P_HDMI_SPDIF_BASE(0x0048)
+#define S5P_HDMI_SPDIFIN_FRAME_PERIOD_2		S5P_HDMI_SPDIF_BASE(0x004C)
+#define S5P_HDMI_SPDIFIN_Pc_INFO_1		S5P_HDMI_SPDIF_BASE(0x0050)
+#define S5P_HDMI_SPDIFIN_Pc_INFO_2		S5P_HDMI_SPDIF_BASE(0x0054)
+#define S5P_HDMI_SPDIFIN_Pd_INFO_1		S5P_HDMI_SPDIF_BASE(0x0058)
+#define S5P_HDMI_SPDIFIN_Pd_INFO_2		S5P_HDMI_SPDIF_BASE(0x005C)
+#define S5P_HDMI_SPDIFIN_DATA_BUF_0_1		S5P_HDMI_SPDIF_BASE(0x0060)
+#define S5P_HDMI_SPDIFIN_DATA_BUF_0_2		S5P_HDMI_SPDIF_BASE(0x0064)
+#define S5P_HDMI_SPDIFIN_DATA_BUF_0_3		S5P_HDMI_SPDIF_BASE(0x0068)
+#define S5P_HDMI_SPDIFIN_USER_BUF_0		S5P_HDMI_SPDIF_BASE(0x006C)
+#define S5P_HDMI_SPDIFIN_DATA_BUF_1_1		S5P_HDMI_SPDIF_BASE(0x0070)
+#define S5P_HDMI_SPDIFIN_DATA_BUF_1_2		S5P_HDMI_SPDIF_BASE(0x0074)
+#define S5P_HDMI_SPDIFIN_DATA_BUF_1_3		S5P_HDMI_SPDIF_BASE(0x0078)
+#define S5P_HDMI_SPDIFIN_USER_BUF_1		S5P_HDMI_SPDIF_BASE(0x007C)
+
+#define S5P_HDMI_I2S_CLK_CON			S5P_HDMI_I2S_BASE(0x0000)
+#define S5P_HDMI_I2S_CON_1			S5P_HDMI_I2S_BASE(0x0004)
+#define S5P_HDMI_I2S_CON_2			S5P_HDMI_I2S_BASE(0x0008)
+#define S5P_HDMI_I2S_PIN_SEL_0			S5P_HDMI_I2S_BASE(0x000C)
+#define S5P_HDMI_I2S_PIN_SEL_1			S5P_HDMI_I2S_BASE(0x0010)
+#define S5P_HDMI_I2S_PIN_SEL_2			S5P_HDMI_I2S_BASE(0x0014)
+#define S5P_HDMI_I2S_PIN_SEL_3			S5P_HDMI_I2S_BASE(0x0018)
+#define S5P_HDMI_I2S_DSD_CON			S5P_HDMI_I2S_BASE(0x001C)
+#define S5P_HDMI_I2S_MUX_CON			S5P_HDMI_I2S_BASE(0x0020)
+#define S5P_HDMI_I2S_CH_ST_CON			S5P_HDMI_I2S_BASE(0x0024)
+#define S5P_HDMI_I2S_CH_ST_0			S5P_HDMI_I2S_BASE(0x0028)
+#define S5P_HDMI_I2S_CH_ST_1			S5P_HDMI_I2S_BASE(0x002C)
+#define S5P_HDMI_I2S_CH_ST_2			S5P_HDMI_I2S_BASE(0x0030)
+#define S5P_HDMI_I2S_CH_ST_3			S5P_HDMI_I2S_BASE(0x0034)
+#define S5P_HDMI_I2S_CH_ST_4			S5P_HDMI_I2S_BASE(0x0038)
+#define S5P_HDMI_I2S_CH_ST_SH_0			S5P_HDMI_I2S_BASE(0x003C)
+#define S5P_HDMI_I2S_CH_ST_SH_1			S5P_HDMI_I2S_BASE(0x0040)
+#define S5P_HDMI_I2S_CH_ST_SH_2			S5P_HDMI_I2S_BASE(0x0044)
+#define S5P_HDMI_I2S_CH_ST_SH_3			S5P_HDMI_I2S_BASE(0x0048)
+#define S5P_HDMI_I2S_CH_ST_SH_4			S5P_HDMI_I2S_BASE(0x004C)
+#define S5P_HDMI_I2S_VD_DATA			S5P_HDMI_I2S_BASE(0x0050)
+#define S5P_HDMI_I2S_MUX_CH			S5P_HDMI_I2S_BASE(0x0054)
+#define S5P_HDMI_I2S_MUX_CUV			S5P_HDMI_I2S_BASE(0x0058)
+#define S5P_HDMI_I2S_IRQ_MASK			S5P_HDMI_I2S_BASE(0x005C)
+#define S5P_HDMI_I2S_IRQ_STATUS			S5P_HDMI_I2S_BASE(0x0060)
+#define S5P_HDMI_I2S_CH0_L_0			S5P_HDMI_I2S_BASE(0x0064)
+#define S5P_HDMI_I2S_CH0_L_1			S5P_HDMI_I2S_BASE(0x0068)
+#define S5P_HDMI_I2S_CH0_L_2			S5P_HDMI_I2S_BASE(0x006C)
+#define S5P_HDMI_I2S_CH0_L_3			S5P_HDMI_I2S_BASE(0x0070)
+#define S5P_HDMI_I2S_CH0_R_0			S5P_HDMI_I2S_BASE(0x0074)
+#define S5P_HDMI_I2S_CH0_R_1			S5P_HDMI_I2S_BASE(0x0078)
+#define S5P_HDMI_I2S_CH0_R_2			S5P_HDMI_I2S_BASE(0x007C)
+#define S5P_HDMI_I2S_CH0_R_3			S5P_HDMI_I2S_BASE(0x0080)
+#define S5P_HDMI_I2S_CH1_L_0			S5P_HDMI_I2S_BASE(0x0084)
+#define S5P_HDMI_I2S_CH1_L_1			S5P_HDMI_I2S_BASE(0x0088)
+#define S5P_HDMI_I2S_CH1_L_2			S5P_HDMI_I2S_BASE(0x008C)
+#define S5P_HDMI_I2S_CH1_L_3			S5P_HDMI_I2S_BASE(0x0090)
+#define S5P_HDMI_I2S_CH1_R_0			S5P_HDMI_I2S_BASE(0x0094)
+#define S5P_HDMI_I2S_CH1_R_1			S5P_HDMI_I2S_BASE(0x0098)
+#define S5P_HDMI_I2S_CH1_R_2			S5P_HDMI_I2S_BASE(0x009C)
+#define S5P_HDMI_I2S_CH1_R_3			S5P_HDMI_I2S_BASE(0x00A0)
+#define S5P_HDMI_I2S_CH2_L_0			S5P_HDMI_I2S_BASE(0x00A4)
+#define S5P_HDMI_I2S_CH2_L_1			S5P_HDMI_I2S_BASE(0x00A8)
+#define S5P_HDMI_I2S_CH2_L_2			S5P_HDMI_I2S_BASE(0x00AC)
+#define S5P_HDMI_I2S_CH2_L_3			S5P_HDMI_I2S_BASE(0x00B0)
+#define S5P_HDMI_I2S_CH2_R_0			S5P_HDMI_I2S_BASE(0x00B4)
+#define S5P_HDMI_I2S_CH2_R_1			S5P_HDMI_I2S_BASE(0x00B8)
+#define S5P_HDMI_I2S_CH2_R_2			S5P_HDMI_I2S_BASE(0x00BC)
+#define S5P_HDMI_I2S_Ch2_R_3			S5P_HDMI_I2S_BASE(0x00C0)
+#define S5P_HDMI_I2S_CH3_L_0			S5P_HDMI_I2S_BASE(0x00C4)
+#define S5P_HDMI_I2S_CH3_L_1			S5P_HDMI_I2S_BASE(0x00C8)
+#define S5P_HDMI_I2S_CH3_L_2			S5P_HDMI_I2S_BASE(0x00CC)
+#define S5P_HDMI_I2S_CH3_R_0			S5P_HDMI_I2S_BASE(0x00D0)
+#define S5P_HDMI_I2S_CH3_R_1			S5P_HDMI_I2S_BASE(0x00D4)
+#define S5P_HDMI_I2S_CH3_R_2			S5P_HDMI_I2S_BASE(0x00D8)
+#define S5P_HDMI_I2S_CUV_L_R			S5P_HDMI_I2S_BASE(0x00DC)
+
+#define S5P_HDMI_TG_CMD				S5P_HDMI_TG_BASE(0x0000)
+#define S5P_HDMI_TG_H_FSZ_L			S5P_HDMI_TG_BASE(0x0018)
+#define S5P_HDMI_TG_H_FSZ_H			S5P_HDMI_TG_BASE(0x001C)
+#define S5P_HDMI_TG_HACT_ST_L			S5P_HDMI_TG_BASE(0x0020)
+#define S5P_HDMI_TG_HACT_ST_H			S5P_HDMI_TG_BASE(0x0024)
+#define S5P_HDMI_TG_HACT_SZ_L			S5P_HDMI_TG_BASE(0x0028)
+#define S5P_HDMI_TG_HACT_SZ_H			S5P_HDMI_TG_BASE(0x002C)
+#define S5P_HDMI_TG_V_FSZ_L			S5P_HDMI_TG_BASE(0x0030)
+#define S5P_HDMI_TG_V_FSZ_H			S5P_HDMI_TG_BASE(0x0034)
+#define S5P_HDMI_TG_VSYNC_L			S5P_HDMI_TG_BASE(0x0038)
+#define S5P_HDMI_TG_VSYNC_H			S5P_HDMI_TG_BASE(0x003C)
+#define S5P_HDMI_TG_VSYNC2_L			S5P_HDMI_TG_BASE(0x0040)
+#define S5P_HDMI_TG_VSYNC2_H			S5P_HDMI_TG_BASE(0x0044)
+#define S5P_HDMI_TG_VACT_ST_L			S5P_HDMI_TG_BASE(0x0048)
+#define S5P_HDMI_TG_VACT_ST_H			S5P_HDMI_TG_BASE(0x004C)
+#define S5P_HDMI_TG_VACT_SZ_L			S5P_HDMI_TG_BASE(0x0050)
+#define S5P_HDMI_TG_VACT_SZ_H			S5P_HDMI_TG_BASE(0x0054)
+#define S5P_HDMI_TG_FIELD_CHG_L			S5P_HDMI_TG_BASE(0x0058)
+#define S5P_HDMI_TG_FIELD_CHG_H			S5P_HDMI_TG_BASE(0x005C)
+#define S5P_HDMI_TG_VACT_ST2_L			S5P_HDMI_TG_BASE(0x0060)
+#define S5P_HDMI_TG_VACT_ST2_H			S5P_HDMI_TG_BASE(0x0064)
+
+#define S5P_HDMI_TG_VSYNC_TOP_HDMI_L		S5P_HDMI_TG_BASE(0x0078)
+#define S5P_HDMI_TG_VSYNC_TOP_HDMI_H		S5P_HDMI_TG_BASE(0x007C)
+#define S5P_HDMI_TG_VSYNC_BOT_HDMI_L		S5P_HDMI_TG_BASE(0x0080)
+#define S5P_HDMI_TG_VSYNC_BOT_HDMI_H		S5P_HDMI_TG_BASE(0x0084)
+#define S5P_HDMI_TG_FIELD_TOP_HDMI_L		S5P_HDMI_TG_BASE(0x0088)
+#define S5P_HDMI_TG_FIELD_TOP_HDMI_H		S5P_HDMI_TG_BASE(0x008C)
+#define S5P_HDMI_TG_FIELD_BOT_HDMI_L		S5P_HDMI_TG_BASE(0x0090)
+#define S5P_HDMI_TG_FIELD_BOT_HDMI_H		S5P_HDMI_TG_BASE(0x0094)
+
+#define S5P_HDMI_EFUSE_CTRL			S5P_HDMI_EFUSE_BASE(0x0000)
+#define S5P_HDMI_EFUSE_STATUS			S5P_HDMI_EFUSE_BASE(0x0004)
+#define S5P_HDMI_EFUSE_ADDR_WIDTH		S5P_HDMI_EFUSE_BASE(0x0008)
+#define S5P_HDMI_EFUSE_SIGDEV_ASSERT		S5P_HDMI_EFUSE_BASE(0x000c)
+#define S5P_HDMI_EFUSE_SIGDEV_DEASSERT		S5P_HDMI_EFUSE_BASE(0x0010)
+#define S5P_HDMI_EFUSE_PRCHG_ASSERT		S5P_HDMI_EFUSE_BASE(0x0014)
+#define S5P_HDMI_EFUSE_PRCHG_DEASSERT		S5P_HDMI_EFUSE_BASE(0x0018)
+#define S5P_HDMI_EFUSE_FSET_ASSERT		S5P_HDMI_EFUSE_BASE(0x001c)
+#define S5P_HDMI_EFUSE_FSET_DEASSERT		S5P_HDMI_EFUSE_BASE(0x0020)
+#define S5P_HDMI_EFUSE_SENSING			S5P_HDMI_EFUSE_BASE(0x0024)
+#define S5P_HDMI_EFUSE_SCK_ASSERT		S5P_HDMI_EFUSE_BASE(0x0028)
+#define S5P_HDMI_EFUSE_SCK_DEASSERT		S5P_HDMI_EFUSE_BASE(0x002c)
+#define S5P_HDMI_EFUSE_SDOUT_OFFSET		S5P_HDMI_EFUSE_BASE(0x0030)
+#define S5P_HDMI_EFUSE_READ_OFFSET		S5P_HDMI_EFUSE_BASE(0x0034)
+#endif
+
+#define S5P_HDMI_AUI_SZ				5
+#define S5P_HDMI_GCP_SZ				3
+#define S5P_HDMI_SPD_SZ				28
+#define S5P_HDMI_AVI_SZ				13
+#define S5P_HDMI_MPG_SZ				5
+#define S5P_HDMI_GMU_SX				28
+#define S5P_HDMI_ISRC_SZ			16
+#define S5P_HDMI_ACP_SZ				17
+
+/*
+ * Bit definition part
+ */
+
+/* Control Register */
+
+/* INTC_CON */
+#define S5P_HDMI_INTC_ACT_HI			(1 << 7)
+#define S5P_HDMI_INTC_ACT_LOW			(0 << 7)
+#define S5P_HDMI_INTC_EN_GLOBAL			(1 << 6)
+#define S5P_HDMI_INTC_DIS_GLOBAL		(0 << 6)
+#define S5P_HDMI_INTC_EN_I2S			(1 << 5)
+#define S5P_HDMI_INTC_DIS_I2S			(0 << 5)
+#define S5P_HDMI_INTC_EN_CEC			(1 << 4)
+#define S5P_HDMI_INTC_DIS_CEC			(0 << 4)
+#define S5P_HDMI_INTC_EN_HPD_PLUG		(1 << 3)
+#define S5P_HDMI_INTC_DIS_HPD_PLUG		(0 << 3)
+#define S5P_HDMI_INTC_EN_HPD_UNPLUG		(1 << 2)
+#define S5P_HDMI_INTC_DIS_HPD_UNPLUG		(0 << 2)
+#define S5P_HDMI_INTC_EN_SPDIF			(1 << 1)
+#define S5P_HDMI_INTC_DIS_SPDIF			(0 << 1)
+#define S5P_HDMI_INTC_EN_HDCP			(1 << 0)
+#define S5P_HDMI_INTC_DIS_HDCP			(0 << 0)
+
+/* INTC_FLAG */
+#define S5P_HDMI_INTC_FLAG_I2S			(1 << 5)
+#define S5P_HDMI_INTC_FLAG_CEC			(1 << 4)
+#define S5P_HDMI_INTC_FLAG_HPD_PLUG		(1 << 3)
+#define S5P_HDMI_INTC_FLAG_HPD_UNPLUG		(1 << 2)
+#define S5P_HDMI_INTC_FLAG_SPDIF		(1 << 1)
+#define S5P_HDMI_INTC_FLAG_HDCP			(1 << 0)
+
+/* HDCP_KEY_LOAD_DONE */
+#define S5P_HDMI_HDCP_KEY_LOAD_DONE		(1 << 0)
+
+/* HPD_STATUS */
+#define S5P_HDMI_HPD_PLUGED			(1 << 0)
+
+/* AUDIO_CLKSEL */
+#define S5P_HDMI_AUDIO_SPDIF_CLK		(1 << 0)
+#define S5P_HDMI_AUDIO_PCLK			(0 << 0)
+
+/* HDMI_PHY_RSTOUT */
+#define S5P_HDMI_PHY_SW_RSTOUT			(1 << 0)
+
+/* HDMI_PHY_VPLL */
+#define S5P_HDMI_PHY_VPLL_LOCK			(1 << 7)
+#define S5P_HDMI_PHY_VPLL_CODE_MASK		(0x7 << 0)
+
+/* HDMI_PHY_CMU */
+#define S5P_HDMI_PHY_CMU_LOCK			(1 << 7)
+#define S5P_HDMI_PHY_CMU_CODE_MASK		(0x7 << 0)
+
+/* HDMI_CORE_RSTOUT */
+#define S5P_HDMI_CORE_SW_RSTOUT			(1 << 0)
+
+/* Core Register */
+
+/* HDMI_CON_0 */
+#define S5P_HDMI_BLUE_SCR_EN			(1 << 5)
+#define S5P_HDMI_BLUE_SCR_DIS			(0 << 5)
+#define S5P_HDMI_ENC_OPTION			(1 << 4)
+#define S5P_HDMI_ASP_EN				(1 << 2)
+#define S5P_HDMI_ASP_DIS			(0 << 2)
+#define S5P_HDMI_PWDN_ENB_NORMAL		(1 << 1)
+#define S5P_HDMI_PWDN_ENB_PD			(0 << 1)
+#define S5P_HDMI_EN				(1 << 0)
+#define S5P_HDMI_DIS				(~(1 << 0))
+
+/* HDMI_CON_1 */
+#define S5P_HDMI_PX_LMT_CTRL_BYPASS		(0 << 5)
+#define S5P_HDMI_PX_LMT_CTRL_RGB		(1 << 5)
+#define S5P_HDMI_PX_LMT_CTRL_YPBPR		(2 << 5)
+#define S5P_HDMI_PX_LMT_CTRL_RESERVED		(3 << 5)
+#define S5P_HDMI_CON_PXL_REP_RATIO_MASK		(1 << 1 | 1 << 0)
+#define S5P_HDMI_DOUBLE_PIXEL_REPETITION	(0x01)
+
+/* HDMI_CON_2 */
+#define S5P_HDMI_VID_PREAMBLE_EN		(0 << 5)
+#define S5P_HDMI_VID_PREAMBLE_DIS		(1 << 5)
+#define S5P_HDMI_GUARD_BAND_EN			(0 << 1)
+#define S5P_HDMI_GUARD_BAND_DIS			(1 << 1)
+
+/* STATUS */
+#define S5P_HDMI_AUTHEN_ACK_AUTH		(1 << 7)
+#define S5P_HDMI_AUTHEN_ACK_NOT			(0 << 7)
+#define S5P_HDMI_AUD_FIFO_OVF_FULL		(1 << 6)
+#define S5P_HDMI_AUD_FIFO_OVF_NOT		(0 << 6)
+#define S5P_HDMI_UPDATE_RI_INT_OCC		(1 << 4)
+#define S5P_HDMI_UPDATE_RI_INT_NOT		(0 << 4)
+#define S5P_HDMI_UPDATE_RI_INT_CLEAR		(1 << 4)
+#define S5P_HDMI_UPDATE_PJ_INT_OCC		(1 << 3)
+#define S5P_HDMI_UPDATE_PJ_INT_NOT		(0 << 3)
+#define S5P_HDMI_UPDATE_PJ_INT_CLEAR		(1 << 3)
+#define S5P_HDMI_WRITE_INT_OCC			(1 << 2)
+#define S5P_HDMI_WRITE_INT_NOT			(0 << 2)
+#define S5P_HDMI_WRITE_INT_CLEAR		(1 << 2)
+#define S5P_HDMI_WATCHDOG_INT_OCC		(1 << 1)
+#define S5P_HDMI_WATCHDOG_INT_NOT		(0 << 1)
+#define S5P_HDMI_WATCHDOG_INT_CLEAR		(1 << 1)
+#define S5P_HDMI_WTFORACTIVERX_INT_OCC		(1)
+#define S5P_HDMI_WTFORACTIVERX_INT_NOT		(0)
+#define S5P_HDMI_WTFORACTIVERX_INT_CLEAR	(1)
+
+/* PHY_STATUS */
+#define S5P_HDMI_PHY_STATUS_READY		(1)
+
+/* STATUS_EN */
+#define S5P_HDMI_AUD_FIFO_OVF_EN		(1 << 6)
+#define S5P_HDMI_AUD_FIFO_OVF_DIS		(0 << 6)
+#define S5P_HDMI_UPDATE_RI_INT_EN		(1 << 4)
+#define S5P_HDMI_UPDATE_RI_INT_DIS		(0 << 4)
+#define S5P_HDMI_UPDATE_PJ_INT_EN		(1 << 3)
+#define S5P_HDMI_UPDATE_PJ_INT_DIS		(0 << 3)
+#define S5P_HDMI_WRITE_INT_EN			(1 << 2)
+#define S5P_HDMI_WRITE_INT_DIS			(0 << 2)
+#define S5P_HDMI_WATCHDOG_INT_EN		(1 << 1)
+#define S5P_HDMI_WATCHDOG_INT_DIS		(0 << 1)
+#define S5P_HDMI_WTFORACTIVERX_INT_EN		(1)
+#define S5P_HDMI_WTFORACTIVERX_INT_DIS		(0)
+#define S5P_HDMI_INT_EN_ALL			(S5P_HDMI_UPDATE_RI_INT_EN|\
+						S5P_HDMI_UPDATE_PJ_INT_DIS|\
+						S5P_HDMI_WRITE_INT_EN|\
+						S5P_HDMI_WATCHDOG_INT_EN|\
+						S5P_HDMI_WTFORACTIVERX_INT_EN)
+#define S5P_HDMI_INT_DIS_ALL			(~0x1F)
+
+/* HPD */
+#define S5P_HDMI_SW_HPD_PLUGGED			(1 << 1)
+#define S5P_HDMI_SW_HPD_UNPLUGGED		(0 << 1)
+#define S5P_HDMI_HPD_SEL_I_HPD			(1)
+#define S5P_HDMI_HPD_SEL_SW_HPD			(0)
+
+/* MODE_SEL */
+#define S5P_HDMI_MODE_EN			(1 << 1)
+#define S5P_HDMI_MODE_DIS			(0 << 1)
+#define S5P_HDMI_DVI_MODE_EN			(1)
+#define S5P_HDMI_DVI_MODE_DIS			(0)
+
+/* ENC_EN */
+#define S5P_HDMI_HDCP_ENC_ENABLE		(1)
+#define S5P_HDMI_HDCP_ENC_DISABLE		(0)
+
+/* Video Related Register */
+
+/* BLUESCREEN_0/1/2 */
+
+/* HDMI_YMAX/YMIN/CMAX/CMIN */
+
+/* H_BLANK_0/1 */
+
+/* V_BLANK_0/1/2 */
+
+/* H_V_LINE_0/1/2 */
+
+/* VSYNC_POL */
+#define S5P_HDMI_V_SYNC_POL_ACT_LOW		(1)
+#define S5P_HDMI_V_SYNC_POL_ACT_HIGH		(0)
+
+/* INT_PRO_MODE */
+#define S5P_HDMI_INTERLACE_MODE			(1)
+#define S5P_HDMI_PROGRESSIVE_MODE		(0)
+
+/* V_BLANK_F_0/1/2 */
+
+/* H_SYNC_GEN_0/1/2 */
+
+/* V_SYNC_GEN1_0/1/2 */
+
+/* V_SYNC_GEN2_0/1/2 */
+
+/* V_SYNC_GEN3_0/1/2 */
+
+/* Audio Related Packet Register */
+
+/* ASP_CON */
+#define S5P_HDMI_AUD_DST_DOUBLE			(1 << 7)
+#define S5P_HDMI_AUD_NO_DST_DOUBLE		(0 << 7)
+#define S5P_HDMI_AUD_TYPE_SAMPLE		(0 << 5)
+#define S5P_HDMI_AUD_TYPE_ONE_BIT		(1 << 5)
+#define S5P_HDMI_AUD_TYPE_HBR			(2 << 5)
+#define S5P_HDMI_AUD_TYPE_DST			(3 << 5)
+#define S5P_HDMI_AUD_MODE_TWO_CH		(0 << 4)
+#define S5P_HDMI_AUD_MODE_MULTI_CH		(1 << 4)
+#define S5P_HDMI_AUD_SP_AUD3_EN			(1 << 3)
+#define S5P_HDMI_AUD_SP_AUD2_EN			(1 << 2)
+#define S5P_HDMI_AUD_SP_AUD1_EN			(1 << 1)
+#define S5P_HDMI_AUD_SP_AUD0_EN			(1 << 0)
+#define S5P_HDMI_AUD_SP_ALL_DIS			(0 << 0)
+
+#define S5P_HDMI_AUD_SET_SP_PRE(x)		((x) & 0xF)
+
+/* ASP_SP_FLAT */
+#define S5P_HDMI_ASP_SP_FLAT_AUD_SAMPLE		(0)
+
+/* ASP_CHCFG0/1/2/3 */
+#define S5P_HDMI_SPK3R_SEL_I_PCM0L		(0 << 27)
+#define S5P_HDMI_SPK3R_SEL_I_PCM0R		(1 << 27)
+#define S5P_HDMI_SPK3R_SEL_I_PCM1L		(2 << 27)
+#define S5P_HDMI_SPK3R_SEL_I_PCM1R		(3 << 27)
+#define S5P_HDMI_SPK3R_SEL_I_PCM2L		(4 << 27)
+#define S5P_HDMI_SPK3R_SEL_I_PCM2R		(5 << 27)
+#define S5P_HDMI_SPK3R_SEL_I_PCM3L		(6 << 27)
+#define S5P_HDMI_SPK3R_SEL_I_PCM3R		(7 << 27)
+#define S5P_HDMI_SPK3L_SEL_I_PCM0L		(0 << 24)
+#define S5P_HDMI_SPK3L_SEL_I_PCM0R		(1 << 24)
+#define S5P_HDMI_SPK3L_SEL_I_PCM1L		(2 << 24)
+#define S5P_HDMI_SPK3L_SEL_I_PCM1R		(3 << 24)
+#define S5P_HDMI_SPK3L_SEL_I_PCM2L		(4 << 24)
+#define S5P_HDMI_SPK3L_SEL_I_PCM2R		(5 << 24)
+#define S5P_HDMI_SPK3L_SEL_I_PCM3L		(6 << 24)
+#define S5P_HDMI_SPK3L_SEL_I_PCM3R		(7 << 24)
+#define S5P_HDMI_SPK2R_SEL_I_PCM0L		(0 << 19)
+#define S5P_HDMI_SPK2R_SEL_I_PCM0R		(1 << 19)
+#define S5P_HDMI_SPK2R_SEL_I_PCM1L		(2 << 19)
+#define S5P_HDMI_SPK2R_SEL_I_PCM1R		(3 << 19)
+#define S5P_HDMI_SPK2R_SEL_I_PCM2L		(4 << 19)
+#define S5P_HDMI_SPK2R_SEL_I_PCM2R		(5 << 19)
+#define S5P_HDMI_SPK2R_SEL_I_PCM3L		(6 << 19)
+#define S5P_HDMI_SPK2R_SEL_I_PCM3R		(7 << 19)
+#define S5P_HDMI_SPK2L_SEL_I_PCM0L		(0 << 16)
+#define S5P_HDMI_SPK2L_SEL_I_PCM0R		(1 << 16)
+#define S5P_HDMI_SPK2L_SEL_I_PCM1L		(2 << 16)
+#define S5P_HDMI_SPK2L_SEL_I_PCM1R		(3 << 16)
+#define S5P_HDMI_SPK2L_SEL_I_PCM2L		(4 << 16)
+#define S5P_HDMI_SPK2L_SEL_I_PCM2R		(5 << 16)
+#define S5P_HDMI_SPK2L_SEL_I_PCM3L		(6 << 16)
+#define S5P_HDMI_SPK2L_SEL_I_PCM3R		(7 << 16)
+#define S5P_HDMI_SPK1R_SEL_I_PCM0L		(0 << 11)
+#define S5P_HDMI_SPK1R_SEL_I_PCM0R		(1 << 11)
+#define S5P_HDMI_SPK1R_SEL_I_PCM1L		(2 << 11)
+#define S5P_HDMI_SPK1R_SEL_I_PCM1R		(3 << 11)
+#define S5P_HDMI_SPK1R_SEL_I_PCM2L		(4 << 11)
+#define S5P_HDMI_SPK1R_SEL_I_PCM2R		(5 << 11)
+#define S5P_HDMI_SPK1R_SEL_I_PCM3L		(6 << 11)
+#define S5P_HDMI_SPK1R_SEL_I_PCM3R		(7 << 11)
+#define S5P_HDMI_SPK1L_SEL_I_PCM0L		(0 << 8)
+#define S5P_HDMI_SPK1L_SEL_I_PCM0R		(1 << 8)
+#define S5P_HDMI_SPK1L_SEL_I_PCM1L		(2 << 8)
+#define S5P_HDMI_SPK1L_SEL_I_PCM1R		(3 << 8)
+#define S5P_HDMI_SPK1L_SEL_I_PCM2L		(4 << 8)
+#define S5P_HDMI_SPK1L_SEL_I_PCM2R		(5 << 8)
+#define S5P_HDMI_SPK1L_SEL_I_PCM3L		(6 << 8)
+#define S5P_HDMI_SPK1L_SEL_I_PCM3R		(7 << 8)
+#define S5P_HDMI_SPK0R_SEL_I_PCM0L		(0 << 3)
+#define S5P_HDMI_SPK0R_SEL_I_PCM0R		(1 << 3)
+#define S5P_HDMI_SPK0R_SEL_I_PCM1L		(2 << 3)
+#define S5P_HDMI_SPK0R_SEL_I_PCM1R		(3 << 3)
+#define S5P_HDMI_SPK0R_SEL_I_PCM2L		(4 << 3)
+#define S5P_HDMI_SPK0R_SEL_I_PCM2R		(5 << 3)
+#define S5P_HDMI_SPK0R_SEL_I_PCM3L		(6 << 3)
+#define S5P_HDMI_SPK0R_SEL_I_PCM3R		(7 << 3)
+#define S5P_HDMI_SPK0L_SEL_I_PCM0L		(0)
+#define S5P_HDMI_SPK0L_SEL_I_PCM0R		(1)
+#define S5P_HDMI_SPK0L_SEL_I_PCM1L		(2)
+#define S5P_HDMI_SPK0L_SEL_I_PCM1R		(3)
+#define S5P_HDMI_SPK0L_SEL_I_PCM2L		(4)
+#define S5P_HDMI_SPK0L_SEL_I_PCM2R		(5)
+#define S5P_HDMI_SPK0L_SEL_I_PCM3L		(6)
+#define S5P_HDMI_SPK0L_SEL_I_PCM3R		(7)
+
+/* ACR_CON */
+#define S5P_HDMI_ALT_CTS_RATE_CTS_1		(0 << 3)
+#define S5P_HDMI_ALT_CTS_RATE_CTS_11		(1 << 3)
+#define S5P_HDMI_ALT_CTS_RATE_CTS_21		(2 << 3)
+#define S5P_HDMI_ALT_CTS_RATE_CTS_31		(3 << 3)
+#define S5P_HDMI_ACR_TX_MODE_NO_TX		(0)
+#define S5P_HDMI_ACR_TX_MODE_TX_ONCE		(1)
+#define S5P_HDMI_ACR_TX_MODE_TXCNT_VBI		(2)
+#define S5P_HDMI_ACR_TX_MODE_TX_VPC		(3)
+#define S5P_HDMI_ACR_TX_MODE_MESURE_CTS		(4)
+
+/* ACR_MCTS0/1/2 */
+
+/* ACR_CTS0/1/2 */
+
+/* ACR_N0/1/2 */
+
+/* ACR_LSB2 */
+#define S5P_HDMI_ACR_LSB2_MASK			(0xFF)
+
+/* ACR_TXCNT */
+#define S5P_HDMI_ACR_TXCNT_MASK			(0x1F)
+
+/* ACR_TXINTERNAL */
+#define S5P_HDMI_ACR_TX_INTERNAL_MASK		(0xFF)
+
+/* ACR_CTS_OFFSET */
+#define S5P_HDMI_ACR_CTS_OFFSET_MASK		(0xFF)
+
+/* GCP_CON */
+#define S5P_HDMI_GCP_CON_EN_1ST_VSYNC		(1 << 3)
+#define S5P_HDMI_GCP_CON_EN_2ST_VSYNC		(1 << 2)
+#define S5P_HDMI_GCP_CON_TRANS_EVERY_VSYNC	(2)
+#define S5P_HDMI_GCP_CON_NO_TRAN		(0)
+#define S5P_HDMI_GCP_CON_TRANS_ONCE		(1)
+#define S5P_HDMI_GCP_CON_TRANS_EVERY_VSYNC	(2)
+
+/* GCP_BYTE1 */
+#define S5P_HDMI_GCP_BYTE1_MASK			(0xFF)
+
+/* GCP_BYTE2 */
+#define S5P_HDMI_GCP_BYTE2_PP_MASK		(0xF << 4)
+#define S5P_HDMI_GCP_24BPP			(1 << 2)
+#define S5P_HDMI_GCP_30BPP			(1 << 0 | 1 << 2)
+#define S5P_HDMI_GCP_36BPP			(1 << 1 | 1 << 2)
+#define S5P_HDMI_GCP_48BPP			(1 << 0 | 1 << 1 | 1 << 2)
+
+/* GCP_BYTE3 */
+#define S5P_HDMI_GCP_BYTE3_MASK			(0xFF)
+
+/* ACP Packet Register */
+
+/* ACP_CON */
+#define S5P_HDMI_ACP_FR_RATE_MASK		(0x1F << 3)
+#define S5P_HDMI_ACP_CON_NO_TRAN		(0)
+#define S5P_HDMI_ACP_CON_TRANS_ONCE		(1)
+#define S5P_HDMI_ACP_CON_TRANS_EVERY_VSYNC	(2)
+
+/* ACP_TYPE */
+#define S5P_HDMI_ACP_TYPE_MASK			(0xFF)
+
+/* ACP_DATA00~16 */
+#define S5P_HDMI_ACP_DATA_MASK			(0xFF)
+
+/* ISRC1/2 Packet Register */
+
+/* ISRC_CON */
+#define S5P_HDMI_ISRC_FR_RATE_MASK		(0x1F << 3)
+#define S5P_HDMI_ISRC_EN			(1 << 2)
+#define S5P_HDMI_ISRC_DIS			(0 << 2)
+
+/* ISRC1_HEADER1 */
+#define S5P_HDMI_ISRC1_HEADER_MASK		(0xFF)
+
+/* ISRC1_DATA 00~15 */
+#define S5P_HDMI_ISRC1_DATA_MASK		(0xFF)
+
+/* ISRC2_DATA 00~15 */
+#define S5P_HDMI_ISRC2_DATA_MASK		(0xFF)
+
+/* AVI InfoFrame Register */
+
+/* AVI_CON */
+
+/* AVI_CHECK_SUM */
+
+/* AVI_DATA01~13 */
+#define S5P_HDMI_AVI_PIXEL_REPETITION_DOUBLE	(1<<0)
+#define S5P_HDMI_AVI_PICTURE_ASPECT_4_3		(1<<4)
+#define S5P_HDMI_AVI_PICTURE_ASPECT_16_9	(1<<5)
+
+/* Audio InfoFrame Register */
+
+/* AUI_CON */
+
+/* AUI_CHECK_SUM */
+
+/* AUI_DATA1~5 */
+
+/* MPEG Source InfoFrame registers */
+
+/* MPG_CON */
+
+/* HDMI_MPG_CHECK_SUM */
+
+/* MPG_DATA1~5 */
+
+/* Source Product Descriptor Infoframe registers */
+
+/* SPD_CON */
+
+/* SPD_HEADER0/1/2 */
+
+/* SPD_DATA0~27 */
+
+/* HDCP Register */
+
+/* HDCP_SHA1_00~19 */
+
+/* HDCP_KSV_LIST_0~4 */
+
+/* HDCP_KSV_LIST_CON */
+#define S5P_HDMI_HDCP_KSV_WRITE_DONE		(0x1 << 3)
+#define S5P_HDMI_HDCP_KSV_LIST_EMPTY		(0x1 << 2)
+#define S5P_HDMI_HDCP_KSV_END			(0x1 << 1)
+#define S5P_HDMI_HDCP_KSV_READ			(0x1 << 0)
+
+/* HDCP_CTRL1 */
+#define S5P_HDMI_HDCP_EN_PJ_EN			(1 << 4)
+#define S5P_HDMI_HDCP_EN_PJ_DIS			(~(1 << 4))
+#define S5P_HDMI_HDCP_SET_REPEATER_TIMEOUT	(1 << 2)
+#define S5P_HDMI_HDCP_CLEAR_REPEATER_TIMEOUT	(~(1 << 2))
+#define S5P_HDMI_HDCP_CP_DESIRED_EN		(1 << 1)
+#define S5P_HDMI_HDCP_CP_DESIRED_DIS		(~(1 << 1))
+#define S5P_HDMI_HDCP_ENABLE_1_1_FEATURE_EN	(1)
+#define S5P_HDMI_HDCP_ENABLE_1_1_FEATURE_DIS	(~(1))
+
+/* HDCP_CHECK_RESULT */
+#define S5P_HDMI_HDCP_Pi_MATCH_RESULT_Y		((0x1 << 3) | (0x1 << 2))
+#define S5P_HDMI_HDCP_Pi_MATCH_RESULT_N		((0x1 << 3) | (0x0 << 2))
+#define S5P_HDMI_HDCP_Ri_MATCH_RESULT_Y		((0x1 << 1) | (0x1 << 0))
+#define S5P_HDMI_HDCP_Ri_MATCH_RESULT_N		((0x1 << 1) | (0x0 << 0))
+#define S5P_HDMI_HDCP_CLR_ALL_RESULTS		(0)
+
+/* HDCP_BKSV0~4 */
+/* HDCP_AKSV0~4 */
+
+/* HDCP_BCAPS */
+#define S5P_HDMI_HDCP_BCAPS_REPEATER		(1 << 6)
+#define S5P_HDMI_HDCP_BCAPS_READY		(1 << 5)
+#define S5P_HDMI_HDCP_BCAPS_FAST		(1 << 4)
+#define S5P_HDMI_HDCP_BCAPS_1_1_FEATURES	(1 << 1)
+#define S5P_HDMI_HDCP_BCAPS_FAST_REAUTH		(1)
+
+/* HDCP_BSTATUS_0/1 */
+/* HDCP_Ri_0/1 */
+/* HDCP_I2C_INT */
+/* HDCP_AN_INT */
+/* HDCP_WATCHDOG_INT */
+/* HDCP_RI_INT/1 */
+/* HDCP_Ri_Compare_0 */
+/* HDCP_Ri_Compare_1 */
+/* HDCP_Frame_Count */
+
+/* Gamut Metadata Packet Register */
+
+/* GAMUT_CON */
+/* GAMUT_HEADER0 */
+/* GAMUT_HEADER1 */
+/* GAMUT_HEADER2 */
+/* GAMUT_METADATA0~27 */
+
+/* Video Mode Register */
+
+/* VIDEO_PATTERN_GEN */
+/* HPD_GEN */
+/* HDCP_Ri_Compare_0 */
+/* HDCP_Ri_Compare_0 */
+/* HDCP_Ri_Compare_0 */
+/* HDCP_Ri_Compare_0 */
+/* HDCP_Ri_Compare_0 */
+/* HDCP_Ri_Compare_0 */
+/* HDCP_Ri_Compare_0 */
+/* HDCP_Ri_Compare_0 */
+/* HDCP_Ri_Compare_0 */
+/* HDCP_Ri_Compare_0 */
+
+/* SPDIF Register */
+
+/* SPDIFIN_CLK_CTRL */
+#define S5P_HDMI_SPDIFIN_READY_CLK_DOWN		(1 << 1)
+#define S5P_HDMI_SPDIFIN_CLK_ON			(1)
+
+/* SPDIFIN_OP_CTRL */
+#define S5P_HDMI_SPDIFIN_SW_RESET		(0)
+#define S5P_HDMI_SPDIFIN_STATUS_CHECK_MODE	(1)
+#define S5P_HDMI_SPDIFIN_STATUS_CHK_OP_MODE	(3)
+
+/* SPDIFIN_IRQ_MASK */
+
+/* SPDIFIN_IRQ_STATUS */
+#define S5P_HDMI_SPDIFIN_IRQ_OVERFLOW_EN			(1 << 7)
+#define S5P_HDMI_SPDIFIN_IRQ_ABNORMAL_PD_EN			(1 << 6)
+#define S5P_HDMI_SPDIFIN_IRQ_SH_NOT_DETECTED_RIGHTTIME_EN	(1 << 5)
+#define S5P_HDMI_SPDIFIN_IRQ_SH_DETECTED_EN			(1 << 4)
+#define S5P_HDMI_SPDIFIN_IRQ_SH_NOT_DETECTED_EN			(1 << 3)
+#define S5P_HDMI_SPDIFIN_IRQ_WRONG_PREAMBLE_EN			(1 << 2)
+#define S5P_HDMI_SPDIFIN_IRQ_CH_STATUS_RECOVERED_EN		(1 << 1)
+#define S5P_HDMI_SPDIFIN_IRQ_WRONG_SIG_EN			(1 << 0)
+
+/* SPDIFIN_CONFIG_1 */
+#define S5P_HDMI_SPDIFIN_CFG_FILTER_3_SAMPLE			(0 << 6)
+#define S5P_HDMI_SPDIFIN_CFG_FILTER_2_SAMPLE			(1 << 6)
+#define S5P_HDMI_SPDIFIN_CFG_LINEAR_PCM_TYPE			(0 << 5)
+#define S5P_HDMI_SPDIFIN_CFG_NO_LINEAR_PCM_TYPE			(1 << 5)
+#define S5P_HDMI_SPDIFIN_CFG_PCPD_AUTO_SET			(0 << 4)
+#define S5P_HDMI_SPDIFIN_CFG_PCPD_MANUAL_SET			(1 << 4)
+#define S5P_HDMI_SPDIFIN_CFG_WORD_LENGTH_A_SET			(0 << 3)
+#define S5P_HDMI_SPDIFIN_CFG_WORD_LENGTH_M_SET			(1 << 3)
+#define S5P_HDMI_SPDIFIN_CFG_U_V_C_P_NEGLECT			(0 << 2)
+#define S5P_HDMI_SPDIFIN_CFG_U_V_C_P_REPORT			(1 << 2)
+#define S5P_HDMI_SPDIFIN_CFG_BURST_SIZE_1			(0 << 1)
+#define S5P_HDMI_SPDIFIN_CFG_BURST_SIZE_2			(1 << 1)
+#define S5P_HDMI_SPDIFIN_CFG_DATA_ALIGN_16BIT			(0 << 0)
+#define S5P_HDMI_SPDIFIN_CFG_DATA_ALIGN_32BIT			(1 << 0)
+
+/* SPDIFIN_CONFIG_2 */
+#define S5P_HDMI_SPDIFIN_CFG2_NO_CLK_DIV			(0)
+
+/* SPDIFIN_USER_VALUE_1 */
+/* SPDIFIN_USER_VALUE_2 */
+/* SPDIFIN_USER_VALUE_3 */
+/* SPDIFIN_USER_VALUE_4 */
+/* SPDIFIN_CH_STATUS_0_1 */
+/* SPDIFIN_CH_STATUS_0_2 */
+/* SPDIFIN_CH_STATUS_0_3 */
+/* SPDIFIN_CH_STATUS_0_4 */
+/* SPDIFIN_CH_STATUS_1 */
+/* SPDIFIN_FRAME_PERIOD_1 */
+/* SPDIFIN_FRAME_PERIOD_2 */
+/* SPDIFIN_PC_INFO_1 */
+/* SPDIFIN_PC_INFO_2 */
+/* SPDIFIN_PD_INFO_1 */
+/* SPDIFIN_PD_INFO_2 */
+/* SPDIFIN_DATA_BUF_0_1 */
+/* SPDIFIN_DATA_BUF_0_2 */
+/* SPDIFIN_DATA_BUF_0_3 */
+/* SPDIFIN_USER_BUF_0 */
+/* SPDIFIN_USER_BUF_1_1 */
+/* SPDIFIN_USER_BUF_1_2 */
+/* SPDIFIN_USER_BUF_1_3 */
+/* SPDIFIN_USER_BUF_1 */
+
+/* I2S Register */
+
+/* I2S_CLK_CON */
+#define S5P_HDMI_I2S_CLK_DIS			(0)
+#define S5P_HDMI_I2S_CLK_EN			(1)
+
+/* I2S_CON_1 */
+#define S5P_HDMI_I2S_SCLK_FALLING_EDGE		(0 << 1)
+#define S5P_HDMI_I2S_SCLK_RISING_EDGE		(1 << 1)
+#define S5P_HDMI_I2S_L_CH_LOW_POL		(0)
+#define S5P_HDMI_I2S_L_CH_HIGH_POL		(1)
+
+/* I2S_CON_2 */
+#define S5P_HDMI_I2S_MSB_FIRST_MODE		(0 << 6)
+#define S5P_HDMI_I2S_LSB_FIRST_MODE		(1 << 6)
+#define S5P_HDMI_I2S_BIT_CH_32FS		(0 << 4)
+#define S5P_HDMI_I2S_BIT_CH_48FS		(1 << 4)
+#define S5P_HDMI_I2S_BIT_CH_RESERVED		(2 << 4)
+#define S5P_HDMI_I2S_SDATA_16BIT		(1 << 2)
+#define S5P_HDMI_I2S_SDATA_20BIT		(2 << 2)
+#define S5P_HDMI_I2S_SDATA_24BIT		(3 << 2)
+#define S5P_HDMI_I2S_BASIC_FORMAT		(0)
+#define S5P_HDMI_I2S_L_JUST_FORMAT		(2)
+#define S5P_HDMI_I2S_R_JUST_FORMAT		(3)
+#define S5P_HDMI_I2S_CON_2_CLR			(~(0xFF))
+#define S5P_HDMI_I2S_SET_BIT_CH(x)		(((x) & 0x7) << 4)
+#define S5P_HDMI_I2S_SET_SDATA_BIT(x)		(((x) & 0x7) << 2)
+
+/* I2S_PIN_SEL_0 */
+#define S5P_HDMI_I2S_SEL_SCLK(x)		(((x) & 0x7) << 4)
+#define S5P_HDMI_I2S_SEL_SCLK_DEFAULT_1		(0x7 << 4)
+#define S5P_HDMI_I2S_SEL_LRCK(x)		((x) & 0x7)
+#define S5P_HDMI_I2S_SEL_LRCK_DEFAULT_0		(0x7)
+
+/* I2S_PIN_SEL_1 */
+#define S5P_HDMI_I2S_SEL_SDATA1(x)		(((x) & 0x7) << 4)
+#define S5P_HDMI_I2S_SEL_SDATA1_DEFAULT_3	(0x7 << 4)
+#define S5P_HDMI_I2S_SEL_SDATA2(x)		((x) & 0x7)
+#define S5P_HDMI_I2S_SEL_SDATA2_DEFAULT_2	(0x7)
+
+/* I2S_PIN_SEL_2 */
+#define S5P_HDMI_I2S_SEL_SDATA3(x)		(((x) & 0x7) << 4)
+#define S5P_HDMI_I2S_SEL_SDATA3_DEFAULT_5	(0x7 << 4)
+#define S5P_HDMI_I2S_SEL_SDATA2(x)		((x) & 0x7)
+#define S5P_HDMI_I2S_SEL_SDATA2_DEFAULT_4	(0x7)
+
+/* I2S_PIN_SEL_3 */
+#define S5P_HDMI_I2S_SEL_DSD(x)			((x) & 0x7)
+#define S5P_HDMI_I2S_SEL_DSD_DEFAULT_6		(0x7)
+
+/* I2S_DSD_CON */
+#define S5P_HDMI_I2S_DSD_CLK_RI_EDGE		(1 << 1)
+#define S5P_HDMI_I2S_DSD_CLK_FA_EDGE		(0 << 1)
+#define S5P_HDMI_I2S_DSD_ENABLE			(1)
+#define S5P_HDMI_I2S_DSD_DISABLE		(0)
+
+/* I2S_MUX_CON */
+#define S5P_HDMI_I2S_NOISE_FILTER_ZERO		(0 << 5)
+#define S5P_HDMI_I2S_NOISE_FILTER_2_STAGE	(1 << 5)
+#define S5P_HDMI_I2S_NOISE_FILTER_3_STAGE	(2 << 5)
+#define S5P_HDMI_I2S_NOISE_FILTER_4_STAGE	(3 << 5)
+#define S5P_HDMI_I2S_NOISE_FILTER_5_STAGE	(4 << 5)
+#define S5P_HDMI_I2S_IN_DISABLE			(1 << 4)
+#define S5P_HDMI_I2S_IN_ENABLE			(0 << 4)
+#define S5P_HDMI_I2S_AUD_SPDIF			(0 << 2)
+#define S5P_HDMI_I2S_AUD_I2S			(1 << 2)
+#define S5P_HDMI_I2S_AUD_DSD			(2 << 2)
+#define S5P_HDMI_I2S_CUV_SPDIF_ENABLE		(0 << 1)
+#define S5P_HDMI_I2S_CUV_I2S_ENABLE		(1 << 1)
+#define S5P_HDMI_I2S_MUX_DISABLE		(0)
+#define S5P_HDMI_I2S_MUX_ENABLE			(1)
+#define S5P_HDMI_I2S_MUX_CON_CLR		(~(0xFF))
+
+/* I2S_CH_ST_CON */
+#define S5P_HDMI_I2S_CH_STATUS_RELOAD		(1)
+#define S5P_HDMI_I2S_CH_ST_CON_CLR		(~(1))
+
+/* I2S_CH_ST_0 / I2S_CH_ST_SH_0 */
+#define S5P_HDMI_I2S_CH_STATUS_MODE_0		(0 << 6)
+#define S5P_HDMI_I2S_2AUD_CH_WITHOUT_PREEMPH	(0 << 3)
+#define S5P_HDMI_I2S_2AUD_CH_WITH_PREEMPH	(1 << 3)
+#define S5P_HDMI_I2S_DEFAULT_EMPHASIS		(0 << 3)
+#define S5P_HDMI_I2S_COPYRIGHT			(0 << 2)
+#define S5P_HDMI_I2S_NO_COPYRIGHT		(1 << 2)
+#define S5P_HDMI_I2S_LINEAR_PCM			(0 << 1)
+#define S5P_HDMI_I2S_NO_LINEAR_PCM		(1 << 1)
+#define S5P_HDMI_I2S_CONSUMER_FORMAT		(0)
+#define S5P_HDMI_I2S_PROF_FORMAT		(1)
+#define S5P_HDMI_I2S_CH_ST_0_CLR		(~(0xFF))
+
+/* I2S_CH_ST_1 / I2S_CH_ST_SH_1 */
+#define S5P_HDMI_I2S_CD_PLAYER			(0x00)
+#define S5P_HDMI_I2S_DAT_PLAYER			(0x03)
+#define S5P_HDMI_I2S_DCC_PLAYER			(0x43)
+#define S5P_HDMI_I2S_MINI_DISC_PLAYER		(0x49)
+
+/* I2S_CH_ST_2 / I2S_CH_ST_SH_2 */
+#define S5P_HDMI_I2S_CHANNEL_NUM_MASK		(0xF << 4)
+#define S5P_HDMI_I2S_SOURCE_NUM_MASK		(0xF)
+#define S5P_HDMI_I2S_SET_CHANNEL_NUM(x)		(((x) & (0xF)) << 4)
+#define S5P_HDMI_I2S_SET_SOURCE_NUM(x)		((x) & (0xF))
+
+/* I2S_CH_ST_3 / I2S_CH_ST_SH_3 */
+#define S5P_HDMI_I2S_CLK_ACCUR_LEVEL_1		(1 << 4)
+#define S5P_HDMI_I2S_CLK_ACCUR_LEVEL_2		(0 << 4)
+#define S5P_HDMI_I2S_CLK_ACCUR_LEVEL_3		(2 << 4)
+#define S5P_HDMI_I2S_SAMPLING_FREQ_44_1		(0x0)
+#define S5P_HDMI_I2S_SAMPLING_FREQ_48		(0x2)
+#define S5P_HDMI_I2S_SAMPLING_FREQ_32		(0x3)
+#define S5P_HDMI_I2S_SAMPLING_FREQ_96		(0xA)
+#define S5P_HDMI_I2S_SET_SAMPLING_FREQ(x)	((x) & (0xF))
+
+/* I2S_CH_ST_4 / I2S_CH_ST_SH_4 */
+#define S5P_HDMI_I2S_ORG_SAMPLING_FREQ_44_1	(0xF << 4)
+#define S5P_HDMI_I2S_ORG_SAMPLING_FREQ_88_2	(0x7 << 4)
+#define S5P_HDMI_I2S_ORG_SAMPLING_FREQ_22_05	(0xB << 4)
+#define S5P_HDMI_I2S_ORG_SAMPLING_FREQ_176_4	(0x3 << 4)
+#define S5P_HDMI_I2S_WORD_LENGTH_NOT_DEFINE	(0x0 << 1)
+#define S5P_HDMI_I2S_WORD_LENGTH_MAX24_20BITS	(0x1 << 1)
+#define S5P_HDMI_I2S_WORD_LENGTH_MAX24_22BITS	(0x2 << 1)
+#define S5P_HDMI_I2S_WORD_LENGTH_MAX24_23BITS	(0x4 << 1)
+#define S5P_HDMI_I2S_WORD_LENGTH_MAX24_24BITS	(0x5 << 1)
+#define S5P_HDMI_I2S_WORD_LENGTH_MAX24_21BITS	(0x6 << 1)
+#define S5P_HDMI_I2S_WORD_LENGTH_MAX20_16BITS	(0x1 << 1)
+#define S5P_HDMI_I2S_WORD_LENGTH_MAX20_18BITS	(0x2 << 1)
+#define S5P_HDMI_I2S_WORD_LENGTH_MAX20_19BITS	(0x4 << 1)
+#define S5P_HDMI_I2S_WORD_LENGTH_MAX20_20BITS	(0x5 << 1)
+#define S5P_HDMI_I2S_WORD_LENGTH_MAX20_17BITS	(0x6 << 1)
+#define S5P_HDMI_I2S_WORD_LENGTH_MAX_24BITS	(1)
+#define S5P_HDMI_I2S_WORD_LENGTH_MAX_20BITS	(0)
+
+/* I2S_VD_DATA */
+#define S5P_HDMI_I2S_VD_AUD_SAMPLE_RELIABLE	(0)
+#define S5P_HDMI_I2S_VD_AUD_SAMPLE_UNRELIABLE	(1)
+
+/* I2S_MUX_CH */
+#define S5P_HDMI_I2S_CH3_R_EN			(1 << 7)
+#define S5P_HDMI_I2S_CH3_L_EN			(1 << 6)
+#define S5P_HDMI_I2S_CH3_EN			(3 << 6)
+#define S5P_HDMI_I2S_CH2_R_EN			(1 << 5)
+#define S5P_HDMI_I2S_CH2_L_EN			(1 << 4)
+#define S5P_HDMI_I2S_CH2_EN			(3 << 4)
+#define S5P_HDMI_I2S_CH1_R_EN			(1 << 3)
+#define S5P_HDMI_I2S_CH1_L_EN			(1 << 2)
+#define S5P_HDMI_I2S_CH1_EN			(3 << 2)
+#define S5P_HDMI_I2S_CH0_R_EN			(1 << 1)
+#define S5P_HDMI_I2S_CH0_L_EN			(1)
+#define S5P_HDMI_I2S_CH0_EN			(3)
+#define S5P_HDMI_I2S_CH_ALL_EN			(0xFF)
+#define S5P_HDMI_I2S_MUX_CH_CLR			(~S5P_HDMI_I2S_CH_ALL_EN)
+
+/* I2S_MUX_CUV */
+#define S5P_HDMI_I2S_CUV_R_EN			(1 << 1)
+#define S5P_HDMI_I2S_CUV_L_EN			(1)
+#define S5P_HDMI_I2S_CUV_RL_EN			(0x03)
+
+/* I2S_IRQ_MASK */
+#define S5P_HDMI_I2S_INT2_DIS			(0 << 1)
+#define S5P_HDMI_I2S_INT2_EN			(1 << 1)
+
+/* I2S_IRQ_STATUS */
+#define S5P_HDMI_I2S_INT2_STATUS		(1 << 1)
+
+/* I2S_CH0_L_0 */
+/* I2S_CH0_L_1 */
+/* I2S_CH0_L_2 */
+/* I2S_CH0_L_3 */
+/* I2S_CH0_R_0 */
+/* I2S_CH0_R_1 */
+/* I2S_CH0_R_2 */
+/* I2S_CH0_R_3 */
+/* I2S_CH1_L_0 */
+/* I2S_CH1_L_1 */
+/* I2S_CH1_L_2 */
+/* I2S_CH1_L_3 */
+/* I2S_CH1_R_0 */
+/* I2S_CH1_R_1 */
+/* I2S_CH1_R_2 */
+/* I2S_CH1_R_3 */
+/* I2S_CH2_L_0 */
+/* I2S_CH2_L_1 */
+/* I2S_CH2_L_2 */
+/* I2S_CH2_L_3 */
+/* I2S_CH2_R_0 */
+/* I2S_CH2_R_1 */
+/* I2S_CH2_R_2 */
+/* I2S_Ch2_R_3 */
+/* I2S_CH3_L_0 */
+/* I2S_CH3_L_1 */
+/* I2S_CH3_L_2 */
+/* I2S_CH3_R_0 */
+/* I2S_CH3_R_1 */
+/* I2S_CH3_R_2 */
+
+/* I2S_CUV_L_R */
+#define S5P_HDMI_I2S_CUV_R_DATA_MASK		(0x7 << 4)
+#define S5P_HDMI_I2S_CUV_L_DATA_MASK		(0x7)
+
+/* Timing Generator Register */
+/* TG_CMD */
+#define S5P_HDMI_GETSYNC_TYPE			(1 << 4)
+#define S5P_HDMI_GETSYNC			(1 << 3)
+#define S5P_HDMI_FIELD				(1 << 1)
+#define S5P_HDMI_TG				(1)
+
+/* TG_CFG */
+/* TG_CB_SZ */
+/* TG_INDELAY_L */
+/* TG_INDELAY_H */
+/* TG_POL_CTRL */
+
+/* TG_H_FSZ_L */
+/* TG_H_FSZ_H */
+/* TG_HACT_ST_L */
+/* TG_HACT_ST_H */
+/* TG_HACT_SZ_L */
+/* TG_HACT_SZ_H */
+/* TG_V_FSZ_L */
+/* TG_V_FSZ_H */
+/* TG_VSYNC_L */
+/* TG_VSYNC_H */
+/* TG_VSYNC2_L */
+/* TG_VSYNC2_H */
+/* TG_VACT_ST_L */
+/* TG_VACT_ST_H */
+/* TG_VACT_SZ_L */
+/* TG_VACT_SZ_H */
+/* TG_FIELD_CHG_L */
+/* TG_FIELD_CHG_H */
+/* TG_VACT_ST2_L */
+/* TG_VACT_ST2_H */
+/* TG_VACT_SC_ST_L */
+/* TG_VACT_SC_ST_H */
+/* TG_VACT_SC_SZ_L */
+/* TG_VACT_SC_SZ_H */
+
+/* TG_VSYNC_TOP_HDMI_L */
+/* TG_VSYNC_TOP_HDMI_H */
+/* TG_VSYNC_BOT_HDMI_L */
+/* TG_VSYNC_BOT_HDMI_H */
+/* TG_FIELD_TOP_HDMI_L */
+/* TG_FIELD_TOP_HDMI_H */
+/* TG_FIELD_BOT_HDMI_L */
+/* TG_FIELD_BOT_HDMI_H */
+/* TG_HSYNC_HDOUT_ST_L */
+/* TG_HSYNC_HDOUT_ST_H */
+/* TG_HSYNC_HDOUT_END_L */
+/* TG_HSYNC_HDOUT_END_H */
+/* TG_VSYNC_HDOUT_ST_L */
+/* TG_VSYNC_HDOUT_ST_H */
+/* TG_VSYNC_HDOUT_END_L */
+/* TG_VSYNC_HDOUT_END_H */
+/* TG_VSYNC_HDOUT_DLY_L */
+/* TG_VSYNC_HDOUT_DLY_H */
+/* TG_BT_ERR_RANGE */
+/* TG_BT_ERR_RESULT */
+/* TG_COR_THR */
+/* TG_COR_NUM */
+/* TG_BT_CON */
+/* TG_BT_H_FSZ_L */
+/* TG_BT_H_FSZ_H */
+/* TG_BT_HSYNC_ST */
+/* TG_BT_HSYNC_SZ */
+/* TG_BT_FSZ_L */
+/* TG_BT_FSZ_H */
+/* TG_BT_VACT_T_ST_L */
+/* TG_BT_VACT_T_ST_H */
+/* TG_BT_VACT_B_ST_L */
+/* TG_BT_VACT_B_ST_H */
+/* TG_BT_VACT_SZ_L */
+/* TG_BT_VACT_SZ_H */
+/* TG_BT_VSYNC_SZ */
+
+/* HDCP E-FUSE Control Register */
+/* HDCP_E_FUSE_CTRL */
+#define S5P_HDMI_EFUSE_CTRL_HDCP_KEY_READ	(1)
+
+/* HDCP_E_FUSE_STATUS */
+#define S5P_HDMI_EFUSE_ECC_FAIL			(1 << 2)
+#define S5P_HDMI_EFUSE_ECC_BUSY			(1 << 1)
+#define S5P_HDMI_EFUSE_ECC_DONE			(1)
+
+/* EFUSE_ADDR_WIDTH */
+/* EFUSE_SIGDEV_ASSERT */
+/* EFUSE_SIGDEV_DE-ASSERT */
+/* EFUSE_PRCHG_ASSERT */
+/* EFUSE_PRCHG_DE-ASSERT */
+/* EFUSE_FSET_ASSERT */
+/* EFUSE_FSET_DE-ASSERT */
+/* EFUSE_SENSING */
+/* EFUSE_SCK_ASSERT */
+/* EFUSE_SCK_DEASSERT */
+/* EFUSE_SDOUT_OFFSET */
+/* EFUSE_READ_OFFSET */
+
+/* HDCP_SHA_RESULT */
+#define S5P_HDMI_HDCP_SHA_VALID_NO_RD		(0 << 1)
+#define S5P_HDMI_HDCP_SHA_VALID_RD		(1 << 1)
+#define S5P_HDMI_HDCP_SHA_VALID			(1)
+#define S5P_HDMI_HDCP_SHA_NO_VALID		(0)
+
+/* DC_CONTRAL */
+#define S5P_HDMI_DC_CTL_12			(1 << 1)
+#define S5P_HDMI_DC_CTL_8			(0)
+#define S5P_HDMI_DC_CTL_10			(1)
+#endif	/* __ARCH_ARM_REGS_HDMI_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-iem.h b/arch/arm/mach-exynos/include/mach/regs-iem.h
new file mode 100644
index 0000000..d9bf177
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/regs-iem.h
@@ -0,0 +1,27 @@
+/* linux/arch/arm/mach-exynos/include/mach/regs-iem.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * EXYNOS4 - IEM(INTELLIGENT ENERGY MANAGEMENT) register discription
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_IEM_H
+#define __ASM_ARCH_REGS_IEM_H __FILE__
+
+/* Register for IEC  */
+#define EXYNOS4_IECDPCCR		(0x00000)
+
+/* Register for APC */
+#define EXYNOS4_APC_CONTROL		(0x10010)
+#define EXYNOS4_APC_PREDLYSEL		(0x10024)
+#define EXYNOS4_APC_DBG_DLYCODE		(0x100E0)
+
+#define APC_HPM_EN			(1 << 4)
+#define IEC_EN				(1 << 0)
+
+#endif /* __ASM_ARCH_REGS_IEM_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-irq.h b/arch/arm/mach-exynos/include/mach/regs-irq.h
new file mode 100644
index 0000000..d2653c1
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/regs-irq.h
@@ -0,0 +1,19 @@
+/* linux/arch/arm/mach-exynos/include/mach/regs-irq.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS4 - IRQ register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_IRQ_H
+#define __ASM_ARCH_REGS_IRQ_H __FILE__
+
+#include <asm/hardware/gic.h>
+#include <mach/map.h>
+
+#endif /* __ASM_ARCH_REGS_IRQ_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-mct.h b/arch/arm/mach-exynos/include/mach/regs-mct.h
new file mode 100644
index 0000000..96cf40a
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/regs-mct.h
@@ -0,0 +1,53 @@
+/* arch/arm/mach-exynos/include/mach/regs-mct.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS4 MCT configutation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_MCT_H
+#define __ASM_ARCH_REGS_MCT_H __FILE__
+
+#include <mach/map.h>
+
+#define EXYNOS4_MCTREG(x)		(S5P_VA_SYSTIMER + (x))
+
+#define EXYNOS4_MCT_G_CNT_L		EXYNOS4_MCTREG(0x100)
+#define EXYNOS4_MCT_G_CNT_U		EXYNOS4_MCTREG(0x104)
+#define EXYNOS4_MCT_G_CNT_WSTAT		EXYNOS4_MCTREG(0x110)
+
+#define EXYNOS4_MCT_G_COMP0_L		EXYNOS4_MCTREG(0x200)
+#define EXYNOS4_MCT_G_COMP0_U		EXYNOS4_MCTREG(0x204)
+#define EXYNOS4_MCT_G_COMP0_ADD_INCR	EXYNOS4_MCTREG(0x208)
+
+#define EXYNOS4_MCT_G_TCON		EXYNOS4_MCTREG(0x240)
+
+#define EXYNOS4_MCT_G_INT_CSTAT		EXYNOS4_MCTREG(0x244)
+#define EXYNOS4_MCT_G_INT_ENB		EXYNOS4_MCTREG(0x248)
+#define EXYNOS4_MCT_G_WSTAT		EXYNOS4_MCTREG(0x24C)
+
+#define _EXYNOS4_MCT_L_BASE		EXYNOS4_MCTREG(0x300)
+#define EXYNOS4_MCT_L_BASE(x)		(_EXYNOS4_MCT_L_BASE + (0x100 * x))
+#define EXYNOS4_MCT_L_MASK		(0xffffff00)
+
+#define MCT_L_TCNTB_OFFSET		(0x00)
+#define MCT_L_ICNTB_OFFSET		(0x08)
+#define MCT_L_TCON_OFFSET		(0x20)
+#define MCT_L_INT_CSTAT_OFFSET		(0x30)
+#define MCT_L_INT_ENB_OFFSET		(0x34)
+#define MCT_L_WSTAT_OFFSET		(0x40)
+
+#define MCT_G_TCON_START		(1 << 8)
+#define MCT_G_TCON_COMP0_AUTO_INC	(1 << 1)
+#define MCT_G_TCON_COMP0_ENABLE		(1 << 0)
+
+#define MCT_L_TCON_INTERVAL_MODE	(1 << 2)
+#define MCT_L_TCON_INT_START		(1 << 1)
+#define MCT_L_TCON_TIMER_START		(1 << 0)
+
+#endif /* __ASM_ARCH_REGS_MCT_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-mem.h b/arch/arm/mach-exynos/include/mach/regs-mem.h
new file mode 100644
index 0000000..23eb23c8
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/regs-mem.h
@@ -0,0 +1,23 @@
+/* linux/arch/arm/mach-exynos/include/mach/regs-mem.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS4 - SROMC and DMC register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_MEM_H
+#define __ASM_ARCH_REGS_MEM_H __FILE__
+
+#include <mach/map.h>
+
+#define S5P_DMC0_MEMCON_OFFSET		0x04
+
+#define S5P_DMC0_MEMTYPE_SHIFT		8
+#define S5P_DMC0_MEMTYPE_MASK		0xF
+
+#endif /* __ASM_ARCH_REGS_MEM_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-mfc.h b/arch/arm/mach-exynos/include/mach/regs-mfc.h
new file mode 100644
index 0000000..1fe42f0
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/regs-mfc.h
@@ -0,0 +1,197 @@
+/*
+ * linux/arch/arm/mach-exynos/include/mach/regs-mfc.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Register definition for Samsung MFC (Multi Function Codec - FIMV) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __REGS_MFC_H
+#define __REGS_MFC_H __FILE__
+
+#define S5P_MFCREG(x)			(x)
+
+#define MFC_START_ADDR			S5P_MFCREG(0x0000)
+#define MFC_END_ADDR			S5P_MFCREG(0xe008)
+
+#define MFC_SW_RESET			S5P_MFCREG(0x0000)
+#define MFC_RISC_HOST_INT		S5P_MFCREG(0x0008)
+
+/* Command from HOST to RISC */
+#define MFC_HOST2RISC_CMD		S5P_MFCREG(0x0030)
+#define MFC_HOST2RISC_ARG1		S5P_MFCREG(0x0034)
+#define MFC_HOST2RISC_ARG2		S5P_MFCREG(0x0038)
+#define MFC_HOST2RISC_ARG3		S5P_MFCREG(0x003c)
+#define MFC_HOST2RISC_ARG4		S5P_MFCREG(0x0040)
+
+/* Command from RISC to HOST */
+#define MFC_RISC2HOST_CMD		S5P_MFCREG(0x0044)
+#define MFC_RISC2HOST_ARG1		S5P_MFCREG(0x0048)
+#define MFC_RISC2HOST_ARG2		S5P_MFCREG(0x004c)
+#define MFC_RISC2HOST_ARG3		S5P_MFCREG(0x0050)
+#define MFC_RISC2HOST_ARG4		S5P_MFCREG(0x0054)
+
+#define MFC_FW_VERSION			S5P_MFCREG(0x0058)
+#define MFC_SYS_MEM_SZ			S5P_MFCREG(0x005c)
+#define MFC_FW_STATUS			S5P_MFCREG(0x0080)
+
+/* Memory controller register */
+#define MFC_MC_DRAMBASE_ADR_A		S5P_MFCREG(0x0508)
+#define MFC_MC_DRAMBASE_ADR_B		S5P_MFCREG(0x050c)
+#define MFC_MC_STATUS			S5P_MFCREG(0x0510)
+
+/* Common register */
+#define MFC_SYS_MEM_ADR			S5P_MFCREG(0x0600) /* firmware buffer */
+#define MFC_CPB_BUF_ADR			S5P_MFCREG(0x0604) /* stream buffer */
+#define MFC_DESC_BUF_ADR		S5P_MFCREG(0x0608) /* descriptor buffer */
+#define MFC_LUMA_ADR			S5P_MFCREG(0x0700) /* Luma0 ~ Luma18 */
+#define MFC_CHROMA_ADR			S5P_MFCREG(0x0600) /* Chroma0 ~ Chroma18 */
+
+#define MFC_B_RECON_LUMA_ADR		S5P_MFCREG(0x062c)
+#define MFC_B_RECON_CHROMA_ADR		S5P_MFCREG(0x0630)
+
+/* H264 decoding */
+#define MFC_VERT_NB_MV_ADR		S5P_MFCREG(0x068c) /* vertical neighbor motion vector */
+#define MFC_VERT_NB_IP_ADR		S5P_MFCREG(0x0690) /* neighbor pixels for intra pred */
+#define MFC_MV_ADR			S5P_MFCREG(0x0780) /* H264 motion vector */
+
+/* H263/MPEG4/MPEG2/VC-1 decoding */
+#define MFC_NB_DCAC_ADR			S5P_MFCREG(0x068c) /* neighbor AC/DC coeff. buffer */
+#define MFC_UP_NB_MV_ADR		S5P_MFCREG(0x0690) /* upper neighbor motion vector buffer */
+#define MFC_SA_MV_ADR			S5P_MFCREG(0x0694) /* subseq. anchor motion vector buffer */
+#define MFC_OT_LINE_ADR			S5P_MFCREG(0x0698) /* overlap transform line buffer */
+#define MFC_BITPLANE3_ADR		S5P_MFCREG(0x069c) /* bitplane3 addr */
+#define MFC_BITPLANE2_ADR		S5P_MFCREG(0x06a0) /* bitplane2 addr */
+#define MFC_BITPLANE1_ADR		S5P_MFCREG(0x06a4) /* bitplane1 addr */
+#define MFC_SP_ADR			S5P_MFCREG(0x06a8) /* syntax parser addr */
+
+/* Encoder register */
+#define MFC_UP_MV_ADR			S5P_MFCREG(0x0600) /* upper motion vector addr */
+#define MFC_COLZERO_FLAG_ADR		S5P_MFCREG(0x0610) /* direct colocaated zero flag addr */
+#define MFC_UP_INTRA_MD_ADR		S5P_MFCREG(0x0608) /* upper intra MD addr */
+#define MFC_UP_INTRA_PRED_ADR		S5P_MFCREG(0x0740) /* upper intra PRED addr */
+#define MFC_NBOR_INFO_ADR		S5P_MFCREG(0x0604) /* entropy engine's neighbor inform and AC/DC coeff. */
+
+#define MFC_ENC_REF0_LUMA_ADR		S5P_MFCREG(0x061c) /* ref0 Luma addr */
+#define MFC_ENC_REF0_CHROMA_ADR		S5P_MFCREG(0x0700) /* ref0 Chroma addr */
+#define MFC_ENC_REF1_LUMA_ADR		S5P_MFCREG(0x0620) /* ref1 Luma addr */
+#define MFC_ENC_REF1_CHROMA_ADR		S5P_MFCREG(0x0704) /* ref1 Chroma addr */
+#define MFC_ENC_REF2_LUMA_ADR		S5P_MFCREG(0x0710) /* ref2 Luma addr */
+#define MFC_ENC_REF2_CHROMA_ADR		S5P_MFCREG(0x0708) /* ref2 Chroma addr */
+#define MFC_ENC_REF3_LUMA_ADR		S5P_MFCREG(0x0714) /* ref3 Luma addr */
+#define MFC_ENC_REF3_CHROMA_ADR		S5P_MFCREG(0x070c) /* ref3 Chroma addr */
+
+/* Codec common register */
+#define MFC_ENC_HSIZE_PX		S5P_MFCREG(0x0818) /* frame width at encoder */
+#define MFC_ENC_VSIZE_PX		S5P_MFCREG(0x081c) /* frame height at encoder */
+#define MFC_ENC_PROFILE			S5P_MFCREG(0x0830) /* profile register */
+#define MFC_ENC_PIC_STRUCT		S5P_MFCREG(0x083c) /* picture field/frame flag */
+#define MFC_ENC_LF_CTRL			S5P_MFCREG(0x0848) /* loop filter control */
+#define MFC_ENC_ALPHA_OFF		S5P_MFCREG(0x084c) /* loop filter alpha offset */
+#define MFC_ENC_BETA_OFF		S5P_MFCREG(0x0850) /* loop filter beta offset */
+#define MFC_MR_BUSIF_CTRL		S5P_MFCREG(0x0854) /* hidden, bus interface ctrl */
+#define MFC_ENC_PXL_CACHE_CTRL		S5P_MFCREG(0x0a00) /* pixel cache control */
+
+/* Channel & stream interface register */
+#define MFC_SI_RTN_CHID			S5P_MFCREG(0x2000) /* Return CH instance ID register */
+#define MFC_SI_CH1_INST_ID		S5P_MFCREG(0x2040) /* codec instance ID */
+#define MFC_SI_CH2_INST_ID		S5P_MFCREG(0x2080) /* codec instance ID */
+
+/* Decoder */
+#define MFC_SI_VRESOL			S5P_MFCREG(0x2004) /* vertical resolution of decoder */
+#define MFC_SI_HRESOL			S5P_MFCREG(0x2008) /* horizontal resolution of decoder */
+#define MFC_SI_BUF_NUMBER		S5P_MFCREG(0x200c) /* number of frames in the decoded pic */
+#define MFC_SI_DISPLAY_Y_ADR		S5P_MFCREG(0x2010) /* luma address of displayed pic */
+#define MFC_SI_DISPLAY_C_ADR		S5P_MFCREG(0x2014) /* chroma address of displayed pic */
+#define MFC_SI_FRM_COUNT		S5P_MFCREG(0x2018) /* the number of frames so far decoded */
+#define MFC_SI_DISPLAY_STATUS		S5P_MFCREG(0x201c) /* Display status of decoded picture */
+#define MFC_SI_FRAME_TYPE		S5P_MFCREG(0x2020) /* frame type such as skip/I/P/B */
+#define MFC_SI_DECODE_Y_ADR		S5P_MFCREG(0x2024) /* luma address of decoded pic */
+#define MFC_SI_DECODE_C_ADR		S5P_MFCREG(0x2028) /* chroma address of decoded pic */
+#define MFC_SI_DECODE_STATUS		S5P_MFCREG(0x202c) /* decoded status */
+
+#define MFC_SI_CH1_ES_ADR		S5P_MFCREG(0x2044) /* start addr of stream buf */
+#define MFC_SI_CH1_ES_SIZE		S5P_MFCREG(0x2048) /* size of stream buf */
+#define MFC_SI_CH1_DESC_ADR		S5P_MFCREG(0x204c) /* addr of descriptor buf */
+#define MFC_SI_CH1_CPB_SIZE		S5P_MFCREG(0x2058) /* max size of coded pic. buf */
+#define MFC_SI_CH1_DESC_SIZE		S5P_MFCREG(0x205c) /* max size of descriptor buf */
+#define MFC_SI_CH1_RELEASE_BUF		S5P_MFCREG(0x2060) /* release buffer register */
+#define MFC_SI_CH1_HOST_WR_ADR		S5P_MFCREG(0x2064) /* shared memory address */
+#define MFC_SI_CH1_DPB_CONF_CTRL	S5P_MFCREG(0x2068) /* DPB Configuration Control Register */
+
+#define MFC_SI_CH2_ES_ADR		S5P_MFCREG(0x2084) /* start addr of stream buf */
+#define MFC_SI_CH2_ES_SIZE		S5P_MFCREG(0x2088) /* size of stream buf */
+#define MFC_SI_CH2_DESC_ADR		S5P_MFCREG(0x208c) /* addr of descriptor buf */
+#define MFC_SI_CH2_CPB_SIZE		S5P_MFCREG(0x2098) /* max size of coded pic. buf */
+#define MFC_SI_CH2_DESC_SIZE		S5P_MFCREG(0x209c) /* max size of descriptor buf */
+#define MFC_SI_CH2_RELEASE_BUF		S5P_MFCREG(0x20a0) /* release buffer register */
+#define MFC_SI_CH2_HOST_WR_ADR		S5P_MFCREG(0x20a4) /* shared memory address */
+#define MFC_SI_CH2_DPB_CONF_CTRL	S5P_MFCREG(0x20a8) /* DPB Configuration Control Register */
+
+#define MFC_SI_FIMV1_VRESOL		S5P_MFCREG(0x2050) /* vertical resolution */
+#define MFC_SI_FIMV1_HRESOL		S5P_MFCREG(0x2054) /* horizontal resolution */
+#define MFC_CRC_LUMA0			S5P_MFCREG(0x2030) /* luma crc data per frame(or top field) */
+#define MFC_CRC_CHROMA0			S5P_MFCREG(0x2034) /* chroma crc data per frame(or top field) */
+#define MFC_CRC_LUMA1			S5P_MFCREG(0x2038) /* luma crc data per bottom field */
+#define MFC_CRC_CHROMA1			S5P_MFCREG(0x203c) /* chroma crc data per bottom field */
+
+/* Encoder */
+#define MFC_ENC_SI_STRM_SIZE		S5P_MFCREG(0x2004) /* stream size */
+#define MFC_ENC_SI_PIC_CNT		S5P_MFCREG(0x2008) /* picture count */
+#define MFC_ENC_SI_WRITE_PTR		S5P_MFCREG(0x200c) /* write pointer */
+#define MFC_ENC_SI_SLICE_TYPE		S5P_MFCREG(0x2010) /* slice type(I/P/B/IDR) */
+#define MFC_ENCODED_Y_ADDR		S5P_MFCREG(0x2014) /* the address of the encoded luminance picture */
+#define MFC_ENCODED_C_ADDR		S5P_MFCREG(0x2018) /* the address of the encoded chrominance picture */
+
+#define MFC_ENC_SI_CH1_SB_ADR		S5P_MFCREG(0x2044) /* addr of stream buf */
+#define MFC_ENC_SI_CH1_SB_SIZE		S5P_MFCREG(0x204c) /* size of stream buf */
+#define MFC_ENC_SI_CH1_CUR_Y_ADR	S5P_MFCREG(0x2050) /* current Luma addr */
+#define MFC_ENC_SI_CH1_CUR_C_ADR	S5P_MFCREG(0x2054) /* current Chroma addr */
+#define MFC_ENC_SI_CH1_FRAME_INS	S5P_MFCREG(0x2058) /* frame insertion control register */
+#define MFC_ENC_SI_CH1_INPUT_FLUSH	S5P_MFCREG(0x2068) /* flusing input buffer */
+
+#define MFC_ENC_SI_CH2_SB_ADR		S5P_MFCREG(0x2084) /* addr of stream buf */
+#define MFC_ENC_SI_CH2_SB_SIZE		S5P_MFCREG(0x208c) /* size of stream buf */
+#define MFC_ENC_SI_CH2_CUR_Y_ADR	S5P_MFCREG(0x2090) /* current Luma addr */
+#define MFC_ENC_SI_CH2_CUR_C_ADR	S5P_MFCREG(0x2094) /* current Chroma addr */
+#define MFC_ENC_SI_CH2_FRAME_INS	S5P_MFCREG(0x2098) /* frame insertion control register */
+#define MFC_ENC_SI_CH2_INPUT_FLUSH	S5P_MFCREG(0x20A8) /* flusing input buffer */
+
+#define MFC_ENC_PIC_TYPE_CTRL		S5P_MFCREG(0xc504) /* pic type level control */
+#define MFC_ENC_B_RECON_WRITE_ON	S5P_MFCREG(0xc508) /* B frame recon data write cotrl */
+#define MFC_ENC_MSLICE_CTRL		S5P_MFCREG(0xc50c) /* multi slice control */
+#define MFC_ENC_MSLICE_MB		S5P_MFCREG(0xc510) /* MB number in the one slice */
+#define MFC_ENC_MSLICE_BIT		S5P_MFCREG(0xc514) /* bit count number for one slice */
+#define MFC_ENC_CIR_CTRL		S5P_MFCREG(0xc518) /* number of intra refresh MB */
+#define MFC_ENC_MAP_FOR_CUR		S5P_MFCREG(0xc51c) /* linear or 64x32 tiled mode */
+#define MFC_ENC_PADDING_CTRL		S5P_MFCREG(0xc520) /* padding control */
+
+#define MFC_ENC_NV21_SEL		S5P_MFCREG(0xc548) /* chroma interleaving order */
+
+#define MFC_ENC_INTRA_BIAS		S5P_MFCREG(0xc588) /* intra mode bias for the MB mode */
+#define MFC_ENC_BI_DIRECT_BIAS		S5P_MFCREG(0xc58c) /* bi-directional mode bias for the MB mode */
+
+#define MFC_ENC_RC_CONFIG		S5P_MFCREG(0xc5a0) /* RC config */
+#define MFC_ENC_RC_BIT_RATE		S5P_MFCREG(0xc5a8) /* bit rate */
+#define MFC_ENC_RC_QBOUND		S5P_MFCREG(0xc5ac) /* max/min QP */
+#define MFC_ENC_RC_RPARA		S5P_MFCREG(0xc5b0) /* rate control reaction coeff. */
+#define MFC_ENC_RC_MB_CTRL		S5P_MFCREG(0xc5b4) /* MB adaptive scaling */
+
+/* Encoder for H264 */
+#define MFC_ENC_H264_ENTRP_MODE		S5P_MFCREG(0xd004) /* CAVLC or CABAC */
+#define MFC_ENC_H264_ALPHA_OFF		S5P_MFCREG(0xd008) /* loop filter alpha offset */
+#define MFC_ENC_H264_BETA_OFF		S5P_MFCREG(0xd00c) /* loop filter beta offset */
+#define MFC_ENC_H264_NUM_OF_REF		S5P_MFCREG(0xd010) /* number of reference for P/B */
+#define MFC_ENC_H264_TRANS_FLAG		S5P_MFCREG(0xd034) /* 8x8 transform flag in PPS & high profile */
+
+#define MFC_ENC_RC_FRAME_RATE		S5P_MFCREG(0xd0d0) /* frame rate */
+
+/* Encoder for MPEG4 */
+#define MFC_ENC_MPEG4_QUART_PXL		S5P_MFCREG(0xe008) /* quarter pel interpolation control */
+
+#endif /* __REGS_MFC_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-mixer.h b/arch/arm/mach-exynos/include/mach/regs-mixer.h
new file mode 100644
index 0000000..a9e905e
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/regs-mixer.h
@@ -0,0 +1,216 @@
+/* linux/arch/arm/mach-exynos/include/mach/regs-mixer.h
+ *
+ * Copyright (c) 2010 Samsung Electronics
+ *		http://www.samsung.com/
+ *
+ * Mixer register header file for Samsung TVOUT driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_REGS_MIXER_H
+#define __ARCH_ARM_REGS_MIXER_H
+
+/*
+ * Register part
+ */
+#define S5P_MXR_STATUS				(0x0000)
+#define S5P_MXR_CFG				(0x0004)
+#define S5P_MXR_INT_EN				(0x0008)
+#define S5P_MXR_INT_STATUS			(0x000C)
+#define S5P_MXR_LAYER_CFG			(0x0010)
+#define S5P_MXR_VIDEO_CFG			(0x0014)
+#define S5P_MXR_VIDEO_LIMITER_PARA_CFG		(0x0018)
+#define S5P_MXR_GRAPHIC0_CFG			(0x0020)
+#define S5P_MXR_GRAPHIC0_BASE			(0x0024)
+#define S5P_MXR_GRAPHIC0_SPAN			(0x0028)
+#define S5P_MXR_GRAPHIC0_SXY			(0x002C)
+#define S5P_MXR_GRAPHIC0_WH			(0x0030)
+#define S5P_MXR_GRAPHIC0_DXY			(0x0034)
+#define S5P_MXR_GRAPHIC0_BLANK			(0x0038)
+#define S5P_MXR_GRAPHIC1_CFG			(0x0040)
+#define S5P_MXR_GRAPHIC1_BASE			(0x0044)
+#define S5P_MXR_GRAPHIC1_SPAN			(0x0048)
+#define S5P_MXR_GRAPHIC1_SXY			(0x004C)
+#define S5P_MXR_GRAPHIC1_WH			(0x0050)
+#define S5P_MXR_GRAPHIC1_DXY			(0x0054)
+#define S5P_MXR_GRAPHIC1_BLANK			(0x0058)
+#define S5P_MXR_BG_CFG				(0x0060)
+#define S5P_MXR_BG_COLOR0			(0x0064)
+#define S5P_MXR_BG_COLOR1			(0x0068)
+#define S5P_MXR_BG_COLOR2			(0x006C)
+#define S5P_MXR_CM_COEFF_Y			(0x0080)
+#define S5P_MXR_CM_COEFF_CB			(0x0084)
+#define S5P_MXR_CM_COEFF_CR			(0x0088)
+#define S5P_MXR_VER				(0x0100)
+
+#define S5P_MXR_STATUS_S			(0x2000)
+#define S5P_MXR_CFG_S				(0x2004)
+#define S5P_MXR_LAYER_CFG_S			(0x2010)
+#define S5P_MXR_VIDEO_CFG_S			(0x2014)
+#define S5P_MXR_VIDEO_LIMITER_PARA_CFG_S	(0x2018)
+#define S5P_MXR_GRAPHIC0_CFG_S			(0x2020)
+#define S5P_MXR_GRAPHIC0_BASE_S			(0x2024)
+#define S5P_MXR_GRAPHIC0_SPAN_S			(0x2028)
+#define S5P_MXR_GRAPHIC0_SXY_S			(0x202C)
+#define S5P_MXR_GRAPHIC0_WH_S			(0x2030)
+#define S5P_MXR_GRAPHIC0_DXY_S			(0x2034)
+#define S5P_MXR_GRAPHIC0_BLANK_PIXEL_S		(0x2038)
+#define S5P_MXR_GRAPHIC1_CFG_S			(0x2040)
+#define S5P_MXR_GRAPHIC1_BASE_S			(0x2044)
+#define S5P_MXR_GRAPHIC1_SPAN_S			(0x2048)
+#define S5P_MXR_GRAPHIC1_SXY_S			(0x204C)
+#define S5P_MXR_GRAPHIC1_WH_S			(0x2050)
+#define S5P_MXR_GRAPHIC1_DXY_S			(0x2054)
+#define S5P_MXR_GRAPHIC1_BLANK_PIXEL_S		(0x2058)
+#define S5P_MXR_BG_COLOR0_S			(0x2064)
+#define S5P_MXR_BG_COLOR1_S			(0x2068)
+#define S5P_MXR_BG_COLOR2_S			(0x206C)
+
+/*
+ * Bit definition part
+ */
+/* MIXER_STATUS */
+#define S5P_MXR_STATUS_16_BURST			(1 << 7)
+#define S5P_MXR_STATUS_8_BURST			(0 << 7)
+#define S5P_MXR_STATUS_LITTLE_ENDIAN		(0 << 3)
+#define S5P_MXR_STATUS_BIG_ENDIAN		(1 << 3)
+#define S5P_MXR_STATUS_SYNC_DISABLE		(0 << 2)
+#define S5P_MXR_STATUS_SYNC_ENABLE		(1 << 2)
+#define S5P_MXR_STATUS_OPERATING		(0 << 1)
+#define S5P_MXR_STATUS_IDLE_MODE		(1 << 1)
+#define S5P_MXR_STATUS_STOP			(0 << 0)
+#define S5P_MXR_STATUS_RUN			(1 << 0)
+
+/* MIXER_CGF */
+#define S5P_MXR_CFG_TV_OUT			(~(1 << 7))
+#define S5P_MXR_CFG_HDMI_OUT			(1 << 7)
+#define S5P_MXR_CFG_HD_720P			(0 << 6)
+#define S5P_MXR_CFG_HD_1080I			(1 << 6)
+#define S5P_MXR_CFG_HD_1080P			(1 << 6)
+#define S5P_MXR_CFG_GRAPHIC1_DISABLE		(0 << 5)
+#define S5P_MXR_CFG_GRAPHIC1_ENABLE		(1 << 5)
+#define S5P_MXR_CFG_GRAPHIC0_DISABLE		(0 << 4)
+#define S5P_MXR_CFG_GRAPHIC0_ENABLE		(1 << 4)
+#define S5P_MXR_CFG_VIDEO_DISABLE		(0 << 3)
+#define S5P_MXR_CFG_VIDEO_ENABLE		(1 << 3)
+#define S5P_MXR_CFG_INTERLACE			(~(1 << 2))
+#define S5P_MXR_CFG_PROGRASSIVE			(1 << 2)
+#define S5P_MXR_CFG_NTSC			(0 << 1)
+#define S5P_MXR_CFG_PAL				(1 << 1)
+#define S5P_MXR_CFG_SD				(0 << 0)
+#define S5P_MXR_CFG_HD				(1 << 0)
+#define S5P_MXR_CFG_RGB_FORMAT_MASK		(0xFF << 9)
+
+/* MIXER_INT_EN */
+#define S5P_MXR_INT_EN_VSYNC_ENABLE		(1 << 11)
+#define S5P_MXR_INT_EN_VP_DISABLE		(0 << 10)
+#define S5P_MXR_INT_EN_VP_ENABLE		(1 << 10)
+#define S5P_MXR_INT_EN_GRP1_DISABLE		(0 << 9)
+#define S5P_MXR_INT_EN_GRP1_ENABLE		(1 << 9)
+#define S5P_MXR_INT_EN_GRP0_DISABLE		(0 << 8)
+#define S5P_MXR_INT_EN_GRP0_ENABLE		(1 << 8)
+
+/* MIXER_INT_STATUS */
+#define S5P_MXR_INT_STATUS_VSYNC_CLEARED	(1 << 11)
+#define S5P_MXR_INT_STATUS_VP_N_FIRED		(0 << 10)
+#define S5P_MXR_INT_STATUS_VP_FIRED		(1 << 10)
+#define S5P_MXR_INT_STATUS_GRP1_N_FIRED		(0 << 9)
+#define S5P_MXR_INT_STATUS_GRP1_FIRED		(1 << 9)
+#define S5P_MXR_INT_STATUS_GRP0_N_FIRED		(0 << 8)
+#define S5P_MXR_INT_STATUS_GRP0_FIRED		(1 << 8)
+#define S5P_MXR_INT_STATUS_INT_FIRED		(1 << 0)
+
+/* MIXER_LAYER_CFG */
+#define S5P_MXR_LAYER_CFG_GRP1_HIDE		(0 << 8)
+#define S5P_MXR_LAYER_CFG_GRP1_PRIORITY(x)	(((x) & 0xF) << 8)
+#define S5P_MXR_LAYER_CFG_GRP1_PRIORITY_CLR(x)	((x) & (~(0xF << 8)))
+#define S5P_MXR_LAYER_CFG_GRP1_PRIORITY_INFO(x)	((x) & (0xF << 8))
+#define S5P_MXR_LAYER_CFG_GRP0_HIDE		(0 << 4)
+#define S5P_MXR_LAYER_CFG_GRP0_PRIORITY(x)	(((x) & 0xF) << 4)
+#define S5P_MXR_LAYER_CFG_GRP0_PRIORITY_CLR(x)	((x) & (~(0xF << 4)))
+#define S5P_MXR_LAYER_CFG_GRP0_PRIORITY_INFO(x)	((x) & (0xF << 4))
+#define S5P_MXR_LAYER_CFG_VID_HIDE		(0 << 0)
+#define S5P_MXR_LAYER_CFG_VID_PRIORITY(x)	(((x) & 0xF) << 0)
+#define S5P_MXR_LAYER_CFG_VID_PRIORITY_CLR(x)	((x) & (~(0xF << 0)))
+#define S5P_MXR_LAYER_CFG_VID_PRIORITY_INFO(x)	((x) & (0xF << 0))
+
+/* MIXER_VIDEO_CFG */
+#define S5P_MXR_VIDEO_CFG_LIMITER_DIS		(0 << 17)
+#define S5P_MXR_VIDEO_CFG_LIMITER_EN		(1 << 17)
+#define S5P_MXR_VIDEO_CFG_BLEND_DIS		(0 << 16)
+#define S5P_MXR_VIDEO_CFG_BLEND_EN		(1 << 16)
+#define S5P_MXR_VIDEO_CFG_ALPHA_MASK		(0xFF)
+#define S5P_MXR_VIDEO_CFG_ALPHA_VALUE(x)	(((x) & 0xFF) << 0)
+#define S5P_MXR_VIDEO_CFG_ALPHA_VALUE_CLR(x)	((x) & (~(0xFF << 0)))
+
+/* MIXER_VIDEO_LIMITER_PARA_CFG */
+#define S5P_MXR_VIDEO_LIMITER_PARA_Y_UPPER(x)   (((x) & 0xFF) << 24)
+#define S5P_MXR_VIDEO_LIMITER_PARA_Y_LOWER(x)   (((x) & 0xFF) << 16)
+#define S5P_MXR_VIDEO_LIMITER_PARA_C_UPPER(x)   (((x) & 0xFF) << 8)
+#define S5P_MXR_VIDEO_LIMITER_PARA_C_LOWER(x)   (((x) & 0xFF) << 0)
+
+/* MIXER_GRAPHIC0_CFG */
+/* MIXER_GRAPHIC1_CFG */
+#define S5P_MXR_BLANK_CHANGE_NEW_PIXEL		(1 << 21)
+#define S5P_MXR_BLANK_NOT_CHANGE_NEW_PIXEL	(0 << 21)
+#define S5P_MXR_PRE_MUL_MODE			(1 << 20)
+#define S5P_MXR_NORMAL_MODE			(0 << 20)
+#define S5P_MXR_WIN_BLEND_ENABLE		(1 << 17)
+#define S5P_MXR_WIN_BLEND_DISABLE		(0 << 17)
+#define S5P_MXR_PIXEL_BLEND_ENABLE		(1 << 16)
+#define S5P_MXR_PIXEL_BLEND_DISABLE		(0 << 16)
+#define S5P_MXR_EG_COLOR_FORMAT(x)		(((x) & 0xF) << 8)
+#define S5P_MXR_EG_COLOR_FORMAT_CLEAR(x)	((x) & (~(0xF << 8)))
+#define S5P_MXR_GRP_ALPHA_VALUE(x)		(((x) & 0xFF) << 0)
+#define S5P_MXR_GRP_ALPHA_VALUE_CLEAR(x)	((x) & (~(0xFF << 0)))
+
+/* MIXER_GRAPHIC0_BASE */
+/* MIXER_GRAPHIC1_BASE */
+#define S5P_MXR_GPR_BASE(x)			((x) & 0xFFFFFFFF)
+#define S5P_MXR_GRP_ADDR_ILLEGAL(x)		((x) & 0x3)
+
+/* MIXER_GRAPHIC0_SPAN */
+#define S5P_MXR_GRP_SPAN(x)			((x) & 0x7FFF)
+
+/* MIXER_GRAPHIC0_WH */
+#define S5P_MXR_GRP_H_SCALE(x)			(((x) & 0x1) << 28)
+#define S5P_MXR_GRP_V_SCALE(x)			(((x) & 0x1) << 12)
+#define S5P_MXR_GRP_WIDTH(x)			(((x) & 0x7FF) << 16)
+#define S5P_MXR_GRP_HEIGHT(x)			(((x) & 0x7FF) << 0)
+
+/* MIXER_GRAPHIC0_XY */
+#define S5P_MXR_GRP_STARTX(x)			(((x) & 0x7FF) << 16)
+#define S5P_MXR_GRP_STARTY(x)			(((x) & 0x7FF) << 0)
+
+/* MIXER_GRAPHIC0_DXY */
+#define S5P_MXR_GRP_DESTX(x)			(((x) & 0x7FF) << 16)
+#define S5P_MXR_GRP_DESTY(x)			(((x) & 0x7FF) << 0)
+
+/* MIXER_GRAPHIC0_BLANK */
+#define S5P_MXR_GPR_BLANK_COLOR(x)		((x) & 0xFFFFFFFF)
+
+/* MIXER_BG_CFG */
+#define S5P_MXR_BG_CR_DIHER_EN			(1 << 19)	/* Not support in S5PV210 */
+#define S5P_MXR_BG_CB_DIHER_EN			(1 << 18)	/* Not support in S5PV210 */
+#define S5P_MXR_BG_Y_DIHER_EN			(1 << 17)	/* Not support in S5PV210 */
+
+/* MIXER_BG_COLOR0/1/2 */
+#define S5P_MXR_BG_COEFF_0(x)			(((x) & 0x3F) << 20)
+#define S5P_MXR_BG_COEFF_1(x)			(((x) & 0x3F) << 10)
+#define S5P_MXR_BG_COEFF_2(x)			(((x) & 0x3F) << 0)
+
+/* MIXER_CM_COEFF_Y */
+#define S5P_MXR_BG_COLOR_WIDE			(1 << 30)
+#define S5P_MXR_BG_COLOR_NARROW			(0 << 30)
+#define S5P_MXR_BG_COLOR_Y(x)			(((x) & 0xFF) << 16)
+
+/* MIXER_CM_COEFF_CB */
+#define S5P_MXR_BG_COLOR_CB(x)			(((x) & 0xFF) << 8)
+
+/* MIXER_CM_COEFF_Cr */
+#define S5P_MXR_BG_COLOR_CR(x)			(((x) & 0xFF) << 0)
+#endif /* __ARCH_ARM_REGS_MIXER_H */
+
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu-4210.h b/arch/arm/mach-exynos/include/mach/regs-pmu-4210.h
new file mode 100644
index 0000000..0fc1da0
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu-4210.h
@@ -0,0 +1,32 @@
+/* linux/arch/arm/mach-exynos/include/mach/regs-pmu-4210.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS4 - 4210 Power management unit definition
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_PMU_4210_H
+#define __ASM_ARCH_REGS_PMU_4210_H __FILE__
+
+#define S5P_USBOTG_PHY_CONTROL		S5P_PMUREG(0x0704)
+#define S5P_USBHOST_PHY_CONTROL		S5P_PMUREG(0x0708)
+#define S5P_USBOTG_PHY_ENABLE		(1 << 0)
+#define S5P_USBHOST_PHY_ENABLE		(1 << 0)
+
+#define S5P_PMU_SATA_PHY_CONTROL	S5P_PMUREG(0x0720)
+
+#define S5P_CMU_CLKSTOP_LCD1_SYS	S5P_PMUREG(0x1154)
+#define S5P_CMU_RESET_LCD1_SYS		S5P_PMUREG(0x1174)
+#define S5P_MODIMIF_MEM_SYS		S5P_PMUREG(0x11C4)
+#define S5P_PCIE_MEM_SYS		S5P_PMUREG(0x11E0)
+#define S5P_SATA_MEM_SYS		S5P_PMUREG(0x11E4)
+#define S5P_LCD1_SYS			S5P_PMUREG(0x1394)
+
+#define S5P_PMU_LCD1_CONF		S5P_PMUREG(0x3CA0)
+
+#endif /* __ASM_ARCH_REGS_PMU_4210_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu-4212.h b/arch/arm/mach-exynos/include/mach/regs-pmu-4212.h
new file mode 100644
index 0000000..0c0d90c
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu-4212.h
@@ -0,0 +1,134 @@
+/* linux/arch/arm/mach-exynos/include/mach/regs-pmu-4212.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS4 - 4212 Power management unit definition
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_PMU_4212_H
+#define __ASM_ARCH_REGS_PMU_4212_H __FILE__
+
+#define S5P_LPI_MASK0				S5P_PMUREG(0x0004)
+#define S5P_LPI_MASK1				S5P_PMUREG(0x0008)
+#define S5P_LPI_MASK2				S5P_PMUREG(0x000C)
+
+#define S5P_LPI_DENIAL_MASK0			S5P_PMUREG(0x0018)
+#define S5P_LPI_DENIAL_MASK1			S5P_PMUREG(0x001C)
+#define S5P_LPI_DENIAL_MASK2			S5P_PMUREG(0x0020)
+
+#define S5P_C2C_CTRL				S5P_PMUREG(0x0024)
+
+#define S5P_CENTRAL_SEQ_CONFIGURATION_COREBLK	S5P_PMUREG(0x0240)
+
+#define S5P_CENTRAL_SEQ_COREBLK_CONF		(0x1 << 16)
+
+#define S5P_SYS_WDTRESET			(0x1 << 20)
+#define S5P_AUTOMATIC_WDT_RESET_DISABLE		S5P_PMUREG(0x0408)
+#define S5P_MASK_WDT_RESET_REQUEST		S5P_PMUREG(0x040C)
+
+#define S5P_WAKEUP_STAT_COREBLK			S5P_PMUREG(0x0620)
+#define S5P_WAKEUP_MASK_COREBLK			S5P_PMUREG(0x0628)
+
+#define S5P_USB_PHY_CONTROL			S5P_PMUREG(0x0704)
+#define S5P_HSIC_1_PHY_CONTROL			S5P_PMUREG(0x0708)
+#define S5P_HSIC_2_PHY_CONTROL			S5P_PMUREG(0x070C)
+#define S5P_USB_PHY_ENABLE			(0x1 << 0)
+#define S5P_HSIC_1_PHY_ENABLE			(0x1 << 0)
+#define S5P_HSIC_2_PHY_ENABLE			(0x1 << 0)
+
+#define S5P_ABB_INT				S5P_PMUREG(0x0780)
+#define S5P_ABB_MIF				S5P_PMUREG(0x0784)
+#define S5P_ABB_G3D				S5P_PMUREG(0x0788)
+#define S5P_ABB_ARM				S5P_PMUREG(0x078C)
+
+#define S5P_ABB_MEMBER(_nr)			(S5P_ABB_INT + (_nr * 0x4))
+
+#define ABB_MODE_060V				0
+#define ABB_MODE_065V				1
+#define ABB_MODE_070V				2
+#define ABB_MODE_075V				3
+#define ABB_MODE_080V				4
+#define ABB_MODE_085V				5
+#define ABB_MODE_090V				6
+#define ABB_MODE_095V				7
+#define ABB_MODE_100V				8
+#define ABB_MODE_105V				9
+#define ABB_MODE_110V				10
+#define ABB_MODE_115V				11
+#define ABB_MODE_120V				12
+#define ABB_MODE_125V				13
+#define ABB_MODE_130V				14
+#define ABB_MODE_135V				15
+#define ABB_MODE_140V				16
+#define ABB_MODE_145V				17
+#define ABB_MODE_150V				18
+#define ABB_MODE_155V				19
+#define ABB_MODE_160V				20
+#define ABB_MODE_BYPASS				255
+
+#define S5P_ABB_INIT				(0x80000080)
+#define S5P_ABB_INIT_BYPASS			(0x80000000)
+
+/* SYS_PWR registers */
+#define S5P_ARM_CORE2_SYS			S5P_PMUREG(0x1020)
+#define S5P_DIS_IRQ_ARM_CORE2_LOCAL_SYS		S5P_PMUREG(0x1024)
+#define S5P_DIS_IRQ_ARM_CORE2_CENTRAL_SYS	S5P_PMUREG(0x1028)
+#define S5P_ARM_CORE3_SYS			S5P_PMUREG(0x1030)
+#define S5P_DIS_IRQ_ARM_CORE3_LOCAL_SYS		S5P_PMUREG(0x1034)
+#define S5P_DIS_IRQ_ARM_CORE3_CENTRAL_SYS	S5P_PMUREG(0x1038)
+#define S5P_ISP_ARM_SYS				S5P_PMUREG(0x1050)
+#define S5P_DIS_IRQ_ISP_ARM_LOCAL_SYS		S5P_PMUREG(0x1054)
+#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_SYS		S5P_PMUREG(0x1058)
+#define S5P_CMU_ACLKSTOP_COREBLK_SYS		S5P_PMUREG(0x1110)
+#define S5P_CMU_SCLKSTOP_COREBLK_SYS		S5P_PMUREG(0x1114)
+#define S5P_CMU_RESET_COREBLK_SYS		S5P_PMUREG(0x111C)
+#define S5P_MPLLUSER_SYSCLK_SYS			S5P_PMUREG(0x1130)
+#define S5P_CMU_CLKSTOP_ISP_SYS			S5P_PMUREG(0x1154)
+#define S5P_CMU_RESET_ISP_SYS			S5P_PMUREG(0x1174)
+#define S5P_TOP_BUS_COREBLK_SYS			S5P_PMUREG(0x1190)
+#define S5P_TOP_RETENTION_COREBLK_SYS		S5P_PMUREG(0x1194)
+#define S5P_TOP_PWR_COREBLK_SYS			S5P_PMUREG(0x1198)
+#define S5P_OSCCLK_GATE_SYS			S5P_PMUREG(0x11A4)
+#define S5P_LOGIC_RESET_COREBLK_SYS		S5P_PMUREG(0x11B0)
+#define S5P_OSCCLK_GATE_COREBLK_SYS		S5P_PMUREG(0x11B4)
+#define S5P_HSI_MEM_SYS				S5P_PMUREG(0x11C4)
+#define S5P_ROTATOR_MEM_SYS			S5P_PMUREG(0x11DC)
+#define S5P_PAD_RETENTION_GPIO_COREBLK_SYS	S5P_PMUREG(0x123C)
+#define S5P_PAD_ISOLATION_COREBLK_SYS		S5P_PMUREG(0x1250)
+#define S5P_GPIO_MODE_COREBLK_SYS		S5P_PMUREG(0x1320)
+#define S5P_TOP_ASB_RESET_SYS			S5P_PMUREG(0x1344)
+#define S5P_TOP_ASB_ISOLATION_SYS		S5P_PMUREG(0x1348)
+#define S5P_ISP_SYS				S5P_PMUREG(0x1394)
+#define S5P_DRAM_FREQ_DOWN_SYS			S5P_PMUREG(0x13B0)
+#define S5P_DDRPHY_DLLOFF_SYS			S5P_PMUREG(0x13B4)
+#define S5P_CMU_SYSCLK_ISP_SYS			S5P_PMUREG(0x13B8)
+#define S5P_CMU_SYSCLK_GPS_SYS			S5P_PMUREG(0x13BC)
+#define S5P_LPDDR_PHY_DLL_LOCK_SYS		S5P_PMUREG(0x13C0)
+
+/* OPTION registers */
+#define S5P_ISP_ARM_OPTION			S5P_PMUREG(0x2288)
+#define S5P_ARM_L2_0_OPTION			S5P_PMUREG(0x2608)
+#define S5P_ARM_L2_1_OPTION			S5P_PMUREG(0x2628)
+#define S5P_ONENAND_MEM_OPTION			S5P_PMUREG(0x2E08)
+#define S5P_HSI_MEM_OPTION			S5P_PMUREG(0x2E28)
+#define S5P_G2D_ACP_MEM_OPTION			S5P_PMUREG(0x2E48)
+#define S5P_USBOTG_MEM_OPTION			S5P_PMUREG(0x2E68)
+#define S5P_SDMMC_MEM_OPTION			S5P_PMUREG(0x2E88)
+#define S5P_CSSYS_MEM_OPTION			S5P_PMUREG(0x2EA8)
+#define S5P_SECSS_MEM_OPTION			S5P_PMUREG(0x2EC8)
+#define S5P_ROTATOR_MEM_OPTION			S5P_PMUREG(0x2F48)
+#define S5P_PAD_RETENTION_GPIO_COREBLK_OPTION	S5P_PMUREG(0x31E8)
+
+#define S5P_PS_HOLD_CONTROL			S5P_PMUREG(0x330C)
+
+#define S5P_PMU_ISP_CONF			S5P_PMUREG(0x3CA0)
+#define S5P_PMU_GPS_ALIVE_CONF			S5P_PMUREG(0x3D00)
+#define S5P_PMU_GPS_ALIVE_CONF			S5P_PMUREG(0x3D00)
+#define S5P_PMU_MAUDIO_CONF			S5P_PMUREG(0x3CC0)
+
+#endif /* __ASM_ARCH_REGS_PMU_4212_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu-5210.h b/arch/arm/mach-exynos/include/mach/regs-pmu-5210.h
new file mode 100644
index 0000000..48301b8
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu-5210.h
@@ -0,0 +1,34 @@
+/* linux/arch/arm/mach-exynos/include/mach/regs-pmu-5210.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS5 - 5210 Power management unit definition
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_PMU_5210_H
+#define __ASM_ARCH_REGS_PMU_5210_H __FILE__
+
+#define EXYNOS5_OneNANDXL_MEM_SYS_PWR_REG			S5P_PMUREG(0x11C0)
+#define EXYNOS5_USBDEV_MEM_SYS_PWR_REG				S5P_PMUREG(0x11CC)
+
+#define EXYNOS5_CMU_CLKSTOP_DISP0_SYS_PWR_REG			S5P_PMUREG(0x1490)
+#define EXYNOS5_CMU_SYSCLK_DISP0_SYS_PWR_REG			S5P_PMUREG(0x14D0)
+#define EXYNOS5_CMU_RESET_DISP0_SYS_PWR_REG			S5P_PMUREG(0x1590)
+
+#define EXYNOS5_DISP0_CONFIGURATION				S5P_PMUREG(0x4080)
+#define EXYNOS5_DISP0_STATUS					S5P_PMUREG(0x4084)
+#define EXYNOS5_DISP0_OPTION					S5P_PMUREG(0x4088)
+
+#define EXYNOS5_CMU_CLKSTOP_DISP0_CONFIGURATION			S5P_PMUREG(0x4480)
+#define EXYNOS5_CMU_CLKSTOP_DISP0_STATUS			S5P_PMUREG(0x4484)
+#define EXYNOS5_CMU_CLKSTOP_DISP0_OPTION			S5P_PMUREG(0x4488)
+
+#define EXYNOS5_CMU_SYSCLK_DISP0_STATUS				S5P_PMUREG(0x4684)
+#define EXYNOS5_CMU_SYSCLK_DISP0_OPTION				S5P_PMUREG(0x4688)
+
+#endif /* __ASM_ARCH_REGS_PMU_5210_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu-5250.h b/arch/arm/mach-exynos/include/mach/regs-pmu-5250.h
new file mode 100644
index 0000000..2e5a187
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu-5250.h
@@ -0,0 +1,36 @@
+/* linux/arch/arm/mach-exynos/include/mach/regs-pmu-5250.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS5 - 5250 Power management unit definition
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_PMU_5250_H
+#define __ASM_ARCH_REGS_PMU_5250_H __FILE__
+
+#define EXYNOS5_SATA_PHY_CONTROL				S5P_PMUREG(0x0724)
+
+#define EXYNOS5_ABBG_INT_CONTROL				S5P_PMUREG(0x0780)
+#define EXYNOS5_ABBG_ARM_CONTROL				S5P_PMUREG(0x0784)
+
+#define EXYNOS5_USBOTG_MEM_SYS_PWR_REG				S5P_PMUREG(0x11C0)
+#define EXYNOS5_USBDRD_MEM_SYS_PWR_REG				S5P_PMUREG(0x11CC)
+#define EXYNOS5_SATA_MEM_SYS_PWR_REG				S5P_PMUREG(0x11FC)
+
+#define EXYNOS5_PAD_RETENTION_EFNAND_SYS_PWR_REG		S5P_PMUREG(0x1208)
+
+#define EXYNOS5_SATA_MEM_CONFIGURATION				S5P_PMUREG(0x2FC0)
+#define EXYNOS5_SATA_MEM_STATUS					S5P_PMUREG(0x2FC4)
+#define EXYNOS5_SATA_MEM_OPTION					S5P_PMUREG(0x2FC8)
+
+#define S5P_MIPI_DPHY_CONTROL(n)		S5P_PMUREG(0x0710 + (n) * 4)
+#define S5P_MIPI_DPHY_ENABLE			(1 << 0)
+#define S5P_MIPI_DPHY_SRESETN			(1 << 1)
+#define S5P_MIPI_DPHY_MRESETN			(1 << 2)
+
+#endif /* __ASM_ARCH_REGS_PMU_5250_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
new file mode 100644
index 0000000..21a9f05
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
@@ -0,0 +1,207 @@
+/* linux/arch/arm/mach-exynos/include/mach/regs-pmu.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS4 - Power management unit definition
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_PMU_H
+#define __ASM_ARCH_REGS_PMU_H __FILE__
+
+#include <mach/map.h>
+
+#define S5P_PMUREG(x)				(S5P_VA_PMU + (x))
+
+#include "regs-pmu-4210.h"
+#include "regs-pmu-4212.h"
+
+#define S5P_CENTRAL_SEQ_CONFIGURATION		S5P_PMUREG(0x0200)
+
+#define S5P_CENTRAL_LOWPWR_CFG			(1 << 16)
+
+#define S5P_CENTRAL_SEQ_OPTION			S5P_PMUREG(0x0208)
+
+#define S5P_USE_STANDBY_WFI0			(1 << 16)
+#define S5P_USE_STANDBY_WFI1			(1 << 17)
+#define S5P_USE_STANDBYWFI_ISP_ARM		(1 << 18)
+#define S5P_USE_STANDBY_WFE0			(1 << 24)
+#define S5P_USE_STANDBY_WFE1			(1 << 25)
+#define S5P_USE_STANDBYWFE_ISP_ARM		(1 << 26)
+#define S5P_USE_MASK				((0x3 << 16) | (0x3 << 24))
+
+#define S5P_SWRESET				S5P_PMUREG(0x0400)
+
+#define S5P_WAKEUP_STAT				S5P_PMUREG(0x0600)
+#define	S5P_WAKEUP_STAT_SYSTIMER		(1 << 14)
+#define S5P_WAKEUP_STAT_AUDIO			(1 << 13)
+#define S5P_WAKEUP_STAT_MMC3			(1 << 12)
+#define S5P_WAKEUP_STAT_MMC2			(1 << 11)
+#define S5P_WAKEUP_STAT_RTCTICK			(1 << 2)
+#define S5P_WAKEUP_STAT_RTCALARM		(1 << 1)
+#define S5P_WAKEUP_STAT_EINT			(1 << 0)
+
+#define S5P_EINT_WAKEUP_MASK			S5P_PMUREG(0x0604)
+#define S5P_WAKEUP_MASK				S5P_PMUREG(0x0608)
+
+#if defined(CONFIG_CPU_EXYNOS4212) || defined(CONFIG_CPU_EXYNOS4412)
+#define S5P_WAKEUP_MASK_BIT                    0x3FFFFFF
+#else
+#define S5P_WAKEUP_MASK_BIT                    0xFFFF
+#endif
+
+#define S5P_HDMI_PHY_CONTROL			S5P_PMUREG(0x0700)
+#define S5P_HDMI_PHY_ENABLE			(1 << 0)
+
+#define S5P_DAC_CONTROL				S5P_PMUREG(0x70C)
+#define S5P_DAC_ENABLE				(1)
+#define S5P_DAC_DISABLE				(0)
+
+#define S5P_DAC_PHY_CONTROL			S5P_PMUREG(0x070C)
+#define S5P_DAC_PHY_ENABLE			(1 << 0)
+#define S5P_DAC_DISABLE				(0)
+
+#define S5P_MIPI_DPHY_CONTROL(n)		S5P_PMUREG(0x0710 + (n) * 4)
+#define S5P_MIPI_DPHY_ENABLE			(1 << 0)
+#define S5P_MIPI_DPHY_SRESETN			(1 << 1)
+#define S5P_MIPI_DPHY_MRESETN			(1 << 2)
+
+#define S5P_DPTX_PHY_CONTROL			S5P_PMUREG(0x720)
+#define S5P_DPTX_PHY_ENABLE			(1 << 0)
+
+#define S5P_INFORM0				S5P_PMUREG(0x0800)
+#define S5P_INFORM1				S5P_PMUREG(0x0804)
+#define S5P_INFORM2				S5P_PMUREG(0x0808)
+#define S5P_INFORM3				S5P_PMUREG(0x080C)
+#define S5P_INFORM4				S5P_PMUREG(0x0810)
+#define S5P_INFORM5				S5P_PMUREG(0x0814)
+#define S5P_INFORM6				S5P_PMUREG(0x0818)
+#define S5P_INFORM7				S5P_PMUREG(0x081C)
+
+#define S5P_PMU_DEBUG				S5P_PMUREG(0x0A00)
+#define S5P_PMU_CLKOUT_SEL_SHIFT		(8)
+#define S5P_CLKOUT_DISABLE			(0x1 << 0)
+
+#define S5P_ARM_CORE0_SYS			S5P_PMUREG(0x1000)
+#define S5P_DIS_IRQ_ARM_CORE0_LOCAL_SYS		S5P_PMUREG(0x1004)
+#define S5P_DIS_IRQ_ARM_CORE0_CENTRAL_SYS	S5P_PMUREG(0x1008)
+#define S5P_ARM_CORE1_SYS			S5P_PMUREG(0x1010)
+#define S5P_DIS_IRQ_ARM_CORE1_LOCAL_SYS		S5P_PMUREG(0x1014)
+#define S5P_DIS_IRQ_ARM_CORE1_CENTRAL_SYS	S5P_PMUREG(0x1018)
+#define S5P_ARM_COMMON_SYS			S5P_PMUREG(0x1080)
+#define S5P_ARM_L2_0_SYS			S5P_PMUREG(0x10C0)
+#define S5P_ARM_L2_1_SYS			S5P_PMUREG(0x10C4)
+#define S5P_CMU_ACLKSTOP_SYS			S5P_PMUREG(0x1100)
+#define S5P_CMU_SCLKSTOP_SYS			S5P_PMUREG(0x1104)
+#define S5P_CMU_RESET_SYS			S5P_PMUREG(0x110C)
+#define S5P_APLL_SYSCLK_SYS			S5P_PMUREG(0x1120)
+#define S5P_MPLL_SYSCLK_SYS			S5P_PMUREG(0x1124)
+#define S5P_VPLL_SYSCLK_SYS			S5P_PMUREG(0x1128)
+#define S5P_EPLL_SYSCLK_SYS			S5P_PMUREG(0x112C)
+#define S5P_CMU_CLKSTOP_GPS_ALIVE_SYS		S5P_PMUREG(0x1138)
+#define S5P_CMU_RESET_GPSALIVE_SYS		S5P_PMUREG(0x113C)
+#define S5P_CMU_CLKSTOP_CAM_SYS			S5P_PMUREG(0x1140)
+#define S5P_CMU_CLKSTOP_TV_SYS			S5P_PMUREG(0x1144)
+#define S5P_CMU_CLKSTOP_MFC_SYS			S5P_PMUREG(0x1148)
+#define S5P_CMU_CLKSTOP_G3D_SYS			S5P_PMUREG(0x114C)
+#define S5P_CMU_CLKSTOP_LCD0_SYS		S5P_PMUREG(0x1150)
+#define S5P_CMU_CLKSTOP_MAUDIO_SYS		S5P_PMUREG(0x1158)
+#define S5P_CMU_CLKSTOP_GPS_SYS			S5P_PMUREG(0x115C)
+#define S5P_CMU_RESET_CAM_SYS			S5P_PMUREG(0x1160)
+#define S5P_CMU_RESET_TV_SYS			S5P_PMUREG(0x1164)
+#define S5P_CMU_RESET_MFC_SYS			S5P_PMUREG(0x1168)
+#define S5P_CMU_RESET_G3D_SYS			S5P_PMUREG(0x116C)
+#define S5P_CMU_RESET_LCD0_SYS			S5P_PMUREG(0x1170)
+#define S5P_CMU_RESET_MAUDIO_SYS		S5P_PMUREG(0x1178)
+#define S5P_CMU_RESET_GPS_SYS			S5P_PMUREG(0x117C)
+#define S5P_TOP_BUS_SYS				S5P_PMUREG(0x1180)
+#define S5P_TOP_RETENTION_SYS			S5P_PMUREG(0x1184)
+#define S5P_TOP_PWR_SYS				S5P_PMUREG(0x1188)
+#define S5P_LOGIC_RESET_SYS			S5P_PMUREG(0x11A0)
+#define S5P_ONENAND_MEM_SYS			S5P_PMUREG(0x11C0)
+#define S5P_G2D_ACP_MEM_SYS			S5P_PMUREG(0x11C8)
+#define S5P_USBOTG_MEM_SYS			S5P_PMUREG(0x11CC)
+#define S5P_SDMMC_MEM_SYS			S5P_PMUREG(0x11D0)
+#define S5P_CSSYS_MEM_SYS			S5P_PMUREG(0x11D4)
+#define S5P_SECSS_MEM_SYS			S5P_PMUREG(0x11D8)
+#define S5P_PAD_RETENTION_DRAM_SYS		S5P_PMUREG(0x1200)
+#define S5P_PAD_RETENTION_MAUDIO_SYS		S5P_PMUREG(0x1204)
+#define S5P_PAD_RETENTION_GPIO_SYS		S5P_PMUREG(0x1220)
+#define S5P_PAD_RETENTION_UART_SYS		S5P_PMUREG(0x1224)
+#define S5P_PAD_RETENTION_MMCA_SYS		S5P_PMUREG(0x1228)
+#define S5P_PAD_RETENTION_MMCB_SYS		S5P_PMUREG(0x122C)
+#define S5P_PAD_RETENTION_EBIA_SYS		S5P_PMUREG(0x1230)
+#define S5P_PAD_RETENTION_EBIB_SYS		S5P_PMUREG(0x1234)
+#define S5P_PAD_ISOLATION_SYS			S5P_PMUREG(0x1240)
+#define S5P_PAD_ALV_SEL_SYS			S5P_PMUREG(0x1260)
+#define S5P_XUSBXTI_SYS				S5P_PMUREG(0x1280)
+#define S5P_XXTI_SYS				S5P_PMUREG(0x1284)
+#define S5P_EXT_REGULATOR_SYS			S5P_PMUREG(0x12C0)
+#define S5P_GPIO_MODE_SYS			S5P_PMUREG(0x1300)
+#define S5P_GPIO_MODE_MAUDIO_SYS		S5P_PMUREG(0x1340)
+#define S5P_CAM_SYS				S5P_PMUREG(0x1380)
+#define S5P_TV_SYS				S5P_PMUREG(0x1384)
+#define S5P_MFC_SYS				S5P_PMUREG(0x1388)
+#define S5P_G3D_SYS				S5P_PMUREG(0x138C)
+#define S5P_LCD0_SYS				S5P_PMUREG(0x1390)
+#define S5P_LCD1_SYS				S5P_PMUREG(0x1394)
+#define S5P_MAUDIO_SYS				S5P_PMUREG(0x1398)
+#define S5P_GPS_SYS				S5P_PMUREG(0x139C)
+#define S5P_GPS_ALIVE_SYS			S5P_PMUREG(0x13A0)
+
+#define S5P_ARM_CORE0_CONFIGURATION		S5P_PMUREG(0x2000)
+#define S5P_ARM_CORE0_STATUS			S5P_PMUREG(0x2004)
+#define S5P_ARM_CORE0_OPTION			S5P_PMUREG(0x2008)
+
+#define S5P_ARM_CORE_OPTION(_nr)		(S5P_ARM_CORE0_OPTION + ((_nr) * 0x80))
+#define S5P_ARM_CORE_STATUS(_nr)		(S5P_ARM_CORE0_STATUS + ((_nr) * 0x80))
+#define S5P_ARM_CORE_CONFIGURATION(_nr)		(S5P_ARM_CORE0_CONFIGURATION + ((_nr) * 0x80))
+
+#define S5P_CORE_OPTION_DIS			(1 << 8)
+
+#define S5P_ARM_COMMON_OPTION			S5P_PMUREG(0x2408)
+#define S5P_CAM_OPTION				S5P_PMUREG(0x3C08)
+#define S5P_TV_OPTION				S5P_PMUREG(0x3C28)
+#define S5P_MFC_OPTION				S5P_PMUREG(0x3C48)
+#define S5P_G3D_OPTION				S5P_PMUREG(0x3C68)
+#define S5P_LCD0_OPTION				S5P_PMUREG(0x3C88)
+#define S5P_LCD1_OPTION				S5P_PMUREG(0x3CA8)
+#define S5P_MAUDIO_OPTION			S5P_PMUREG(0x3CC8)
+#define S5P_GPS_OPTION				S5P_PMUREG(0x3CE8)
+#define S5P_GPS_ALIVE_OPTION			S5P_PMUREG(0x3D08)
+
+#define S5P_PAD_RET_MAUDIO_OPTION		S5P_PMUREG(0x3028)
+#define S5P_PAD_RET_GPIO_OPTION			S5P_PMUREG(0x3108)
+#define S5P_PAD_RET_UART_OPTION			S5P_PMUREG(0x3128)
+#define S5P_PAD_RET_MMCA_OPTION			S5P_PMUREG(0x3148)
+#define S5P_PAD_RET_MMCB_OPTION			S5P_PMUREG(0x3168)
+#define S5P_PAD_RET_EBIA_OPTION			S5P_PMUREG(0x3188)
+#define S5P_PAD_RET_EBIB_OPTION			S5P_PMUREG(0x31A8)
+
+#define S5P_XXTI_CONFIGURATION			S5P_PMUREG(0x3420)
+#define S5P_XXTI_STATUS				S5P_PMUREG(0x3424)
+
+#define S5P_PMU_CAM_CONF			S5P_PMUREG(0x3C00)
+#define S5P_PMU_TV_CONF				S5P_PMUREG(0x3C20)
+#define S5P_PMU_MFC_CONF			S5P_PMUREG(0x3C40)
+#define S5P_PMU_G3D_CONF			S5P_PMUREG(0x3C60)
+#define S5P_PMU_LCD0_CONF			S5P_PMUREG(0x3C80)
+#define S5P_PMU_GPS_CONF			S5P_PMUREG(0x3CE0)
+
+#define S5P_CORE_LOCAL_PWR_EN			0x3
+
+#define S5P_USE_DELAYED_RESET_ASSERTION		(1 << 12)
+#define S5P_USE_DELAYED_RESET_OFFSET		12
+
+#define S5P_PMU_SATA_PHY_CONTROL_EN		0x1
+#define S5P_INT_LOCAL_PWR_EN			0x7
+
+#define S5P_CHECK_SLEEP				0x00000BAD
+#define S5P_CHECK_DIDLE				0xBAD00000
+#define S5P_CHECK_LPA				0xABAD0000
+
+#endif /* __ASM_ARCH_REGS_PMU_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu5.h b/arch/arm/mach-exynos/include/mach/regs-pmu5.h
new file mode 100644
index 0000000..6bd9481
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu5.h
@@ -0,0 +1,568 @@
+/* linux/arch/arm/mach-exynos/include/mach/regs-pmu5.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS5 - Power management unit definition
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_PMU5_H
+#define __ASM_ARCH_REGS_PMU5_H __FILE__
+
+#include "regs-pmu-5210.h"
+#include "regs-pmu-5250.h"
+
+#define S5P_PMUREG(x)						(S5P_VA_PMU + (x))
+
+#define EXYNOS5_OM_STAT						S5P_PMUREG(0x0000)
+#define EXYNOS5_GPS_LPI						S5P_PMUREG(0x0004)
+#define EXYNOS5_RTC_CLKO_SEL					S5P_PMUREG(0x001C)
+#define EXYNOS5_GNSS_RTC_OUT_CTRL				S5P_PMUREG(0x0020)
+#define EXYNOS5_C2C_CTRL					S5P_PMUREG(0x0024)
+#define EXYNOS5_CENTRAL_SEQ_CONFIGURATION			S5P_PMUREG(0x0200)
+#define EXYNOS5_CENTRAL_LOWPWR_CFG				(1 << 16)
+
+#define EXYNOS5_CENTRAL_SEQ_STATUS				S5P_PMUREG(0x0204)
+#define EXYNOS5_CENTRAL_SEQ_OPTION				S5P_PMUREG(0x0208)
+
+#define EXYNOS5_USE_STANDBYWFE_ISP_ARM				(1 << 29)
+#define EXYNOS5_USE_STANDBYWFE_FSYS_ARM				(1 << 28)
+#define EXYNOS5_USE_STANDBYWFE_ARM_CORE1			(1 << 25)
+#define EXYNOS5_USE_STANDBYWFE_ARM_CORE0			(1 << 24)
+#define EXYNOS5_USE_STANDBYWFI_ISP_ARM				(1 << 21)
+#define EXYNOS5_USE_STANDBYWFI_FSYS_ARM				(1 << 20)
+#define EXYNOS5_USE_STANDBYWFI_ARM_CORE1			(1 << 17)
+#define EXYNOS5_USE_STANDBYWFI_ARM_CORE0			(1 << 16)
+#define EXYNOS5_FAST_PWUP					(1 << 9)
+#define EXYNOS5_FAST_PWDN					(1 << 8)
+
+#define EXYNOS5_SEQ_TRANSITION0					S5P_PMUREG(0x0220)
+#define EXYNOS5_SEQ_TRANSITION1					S5P_PMUREG(0x0224)
+#define EXYNOS5_SEQ_TRANSITION2					S5P_PMUREG(0x0228)
+#define EXYNOS5_SEQ_TRANSITION3					S5P_PMUREG(0x022C)
+#define EXYNOS5_SEQ_TRANSITION4					S5P_PMUREG(0x0230)
+#define EXYNOS5_SEQ_TRANSITION5					S5P_PMUREG(0x0234)
+#define EXYNOS5_SEQ_TRANSITION6					S5P_PMUREG(0x0238)
+#define EXYNOS5_SEQ_TRANSITION7					S5P_PMUREG(0x023C)
+#define EXYNOS5_CENTRAL_SEQ_SYSMEM_CONFIGURATION		S5P_PMUREG(0x0240)
+#define EXYNOS5_CENTRAL_SEQ_SYSMEM_STATUS			S5P_PMUREG(0x0244)
+#define EXYNOS5_CENTRAL_SEQ_SYSMEM_OPTION			S5P_PMUREG(0x0248)
+#define EXYNOS5_SEQ_SYSMEM_TRANSITION0				S5P_PMUREG(0x0260)
+#define EXYNOS5_SEQ_SYSMEM_TRANSITION1				S5P_PMUREG(0x0264)
+#define EXYNOS5_SEQ_SYSMEM_TRANSITION2				S5P_PMUREG(0x0268)
+#define EXYNOS5_SEQ_SYSMEM_TRANSITION3				S5P_PMUREG(0x026C)
+#define EXYNOS5_SEQ_SYSMEM_TRANSITION4				S5P_PMUREG(0x0270)
+#define EXYNOS5_SEQ_SYSMEM_TRANSITION5				S5P_PMUREG(0x0274)
+#define EXYNOS5_SEQ_SYSMEM_TRANSITION6				S5P_PMUREG(0x0278)
+#define EXYNOS5_SEQ__TRANSITION7				S5P_PMUREG(0x027C)
+#define EXYNOS5_SWRESET						S5P_PMUREG(0x0400)
+#define EXYNOS5_RST_STAT					S5P_PMUREG(0x0404)
+
+#define EXYNOS5_SYS_WDTRESET					(1 << 20)
+
+#define EXYNOS5_AUTOMATIC_WDT_RESET_DISABLE			S5P_PMUREG(0x0408)
+#define EXYNOS5_MASK_WDT_RESET_REQUEST				S5P_PMUREG(0x040C)
+#define EXYNOS5_RESET_SEQUENCER_CONFIGURATION			S5P_PMUREG(0x0500)
+#define EXYNOS5_RESET_SEQUENCER_STATUS				S5P_PMUREG(0x0504)
+#define EXYNOS5_RESET_SEQUENCER_OPTION				S5P_PMUREG(0x0508)
+#define EXYNOS5_WAKEUP_STAT					S5P_PMUREG(0x0600)
+#define EXYNOS5_EINT_WAKEUP_MASK				S5P_PMUREG(0x0604)
+#define EXYNOS5_WAKEUP_MASK					S5P_PMUREG(0x0608)
+
+#define EXYNOS5_DEFAULT_WAKEUP_MACK				(0xF << 16)
+#define EXYNOS5_MASK_RTC_ALARM					(1 << 1)
+#define EXYNOS5_MASK_RTC_TICK					(1 << 2)
+#define EXYNOS5_MASK_KEY					(1 << 5)
+#define EXYNOS5_MASK_HSI					(1 << 8)
+#define EXYNOS5_MASK_MMC0					(1 << 9)
+#define EXYNOS5_MASK_MMC1					(1 << 10)
+#define EXYNOS5_MASK_MMC2					(1 << 11)
+#define EXYNOS5_MASK_MMC3					(1 << 12)
+#define EXYNOS5_MASK_I2S					(1 << 13)
+#define EXYNOS5_MASK_TIMER					(1 << 14)
+#define EXYNOS5_MASK_CEC					(1 << 15)
+#define EXYNOS5_MASK_EXT_GIC0_IRQ				(1 << 16)
+#define EXYNOS5_MASK_EXT_GIC0_FIQ				(1 << 17)
+#define EXYNOS5_MASK_EXT_GIC1_IRQ				(1 << 18)
+#define EXYNOS5_MASK_EXT_GIC1_FIQ				(1 << 19)
+#define EXYNOS5_MASK_C2C_RESET_REQ				(1 << 20)
+#define EXYNOS5_MASK_GPS					(1 << 21)
+
+#define EXYNOS5_DEFAULT_WAKEUP_MASK				(EXYNOS5_MASK_EXT_GIC0_IRQ |\
+								 EXYNOS5_MASK_EXT_GIC0_FIQ |\
+								 EXYNOS5_MASK_EXT_GIC1_IRQ |\
+								 EXYNOS5_MASK_EXT_GIC1_FIQ)
+
+#define EXYNOS5_WAKEUP_INTERRUPT				S5P_PMUREG(0x060C)
+#define EXYNOS5_WAKEUP_STAT_SYSMEM				S5P_PMUREG(0x0620)
+#define EXYNOS5_EINT_WAKEUP_MASK_SYSMEM				S5P_PMUREG(0x0624)
+#define EXYNOS5_WAKEUP_MASK_SYSMEM				S5P_PMUREG(0x0628)
+#define EXYNOS5_WAKEUP_INTERRUPT_SYSMEM				S5P_PMUREG(0x062C)
+#define EXYNOS5_HDMI_PHY_CONTROL				S5P_PMUREG(0x0700)
+#define EXYNOS5_USBDEV_PHY_CONTROL				S5P_PMUREG(0x0704)
+#define EXYNOS5_USBHOST_PHY_CONTROL				S5P_PMUREG(0x0708)
+#define EXYNOS5_MIPI_PHY0_CONTROL				S5P_PMUREG(0x0710)
+#define EXYNOS5_MIPI_PHY1_CONTROL				S5P_PMUREG(0x0714)
+#define EXYNOS5_ADC_PHY_CONTROL					S5P_PMUREG(0x0718)
+#define EXYNOS5_MTCADC_PHY_CONTROL				S5P_PMUREG(0x071C)
+#define EXYNOS5_DPTX_PHY_CONTROL				S5P_PMUREG(0x0720)
+#define EXYNOS5_SATA_PHY_CONTROL				S5P_PMUREG(0x0724)
+
+#define EXYNOS5_ABB_INT						S5P_PMUREG(0x0780)
+#define EXYNOS5_ABB_ARM						S5P_PMUREG(0x0784)
+#define EXYNOS5_ABB_G3D						S5P_PMUREG(0x0788)
+#define EXYNOS5_ABB_MIF						S5P_PMUREG(0x078C)
+
+#define EXYNOS5_ABB_MEMBER(_member)				EXYNOS5_##_member
+
+#define EXYNOS5_INFORM0						S5P_PMUREG(0x0800)
+#define EXYNOS5_INFORM1						S5P_PMUREG(0x0804)
+#define EXYNOS5_INFORM2						S5P_PMUREG(0x0808)
+#define EXYNOS5_INFORM3						S5P_PMUREG(0x080C)
+#define EXYNOS5_INFORM4						S5P_PMUREG(0x0810)
+#define EXYNOS5_INFORM5						S5P_PMUREG(0x0814)
+#define EXYNOS5_INFORM6						S5P_PMUREG(0x0818)
+#define EXYNOS5_INFORM7						S5P_PMUREG(0x081C)
+#define EXYNOS5_PMU_SPARE0					S5P_PMUREG(0x0900)
+#define EXYNOS5_PMU_SPARE1					S5P_PMUREG(0x0904)
+#define EXYNOS5_PMU_SPARE2					S5P_PMUREG(0x0908)
+#define EXYNOS5_PMU_SPARE3					S5P_PMUREG(0x090C)
+#define EXYNOS5_IROM_DATA_REG0					S5P_PMUREG(0x0980)
+#define EXYNOS5_IROM_DATA_REG1					S5P_PMUREG(0x0984)
+#define EXYNOS5_IROM_DATA_REG2					S5P_PMUREG(0x0988)
+#define EXYNOS5_IROM_DATA_REG3					S5P_PMUREG(0x098C)
+
+#define EXYNOS5_ARM_CORE0_SYS_PWR_REG				S5P_PMUREG(0x1000)
+#define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG		S5P_PMUREG(0x1004)
+#define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG		S5P_PMUREG(0x1008)
+#define EXYNOS5_ARM_CORE1_SYS_PWR_REG				S5P_PMUREG(0x1010)
+#define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG		S5P_PMUREG(0x1014)
+#define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG		S5P_PMUREG(0x1018)
+#define EXYNOS5_FSYS_ARM_SYS_PWR_REG				S5P_PMUREG(0x1040)
+#define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG		S5P_PMUREG(0x1048)
+#define EXYNOS5_ISP_ARM_SYS_PWR_REG				S5P_PMUREG(0x1050)
+#define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG		S5P_PMUREG(0x1054)
+#define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG		S5P_PMUREG(0x1058)
+#define EXYNOS5_ARM_COMMON_SYS_PWR_REG				S5P_PMUREG(0x1080)
+#define EXYNOS5_ARM_L2_SYS_PWR_REG				S5P_PMUREG(0x10C0)
+#define EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG			S5P_PMUREG(0x1100)
+#define EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG			S5P_PMUREG(0x1104)
+#define EXYNOS5_CMU_RESET_SYS_PWR_REG				S5P_PMUREG(0x110C)
+#define EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG			S5P_PMUREG(0x1120)
+#define EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG			S5P_PMUREG(0x1124)
+#define EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG			S5P_PMUREG(0x112C)
+#define EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG			S5P_PMUREG(0x1130)
+#define EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG			S5P_PMUREG(0x1134)
+#define EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG			S5P_PMUREG(0x1138)
+#define EXYNOS5_APLL_SYSCLK_SYS_PWR_REG				S5P_PMUREG(0x1140)
+#define EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG				S5P_PMUREG(0x1144)
+#define EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG				S5P_PMUREG(0x1148)
+#define EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG				S5P_PMUREG(0x114C)
+#define EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG				S5P_PMUREG(0x1150)
+#define EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG				S5P_PMUREG(0x1154)
+#define EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG			S5P_PMUREG(0x1164)
+#define EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG			S5P_PMUREG(0x1170)
+#define EXYNOS5_TOP_BUS_SYS_PWR_REG				S5P_PMUREG(0x1180)
+#define EXYNOS5_TOP_RETENTION_SYS_PWR_REG			S5P_PMUREG(0x1184)
+#define EXYNOS5_TOP_PWR_SYS_PWR_REG				S5P_PMUREG(0x1188)
+#define EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG			S5P_PMUREG(0x1190)
+#define EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG		S5P_PMUREG(0x1194)
+#define EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG			S5P_PMUREG(0x1198)
+#define EXYNOS5_LOGIC_RESET_SYS_PWR_REG				S5P_PMUREG(0x11A0)
+#define EXYNOS5_OSCCLK_GATE_SYS_PWR_REG				S5P_PMUREG(0x11A4)
+#define EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG			S5P_PMUREG(0x11B0)
+#define EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG			S5P_PMUREG(0x11B4)
+#define EXYNOS5_G2D_MEM_SYS_PWR_REG				S5P_PMUREG(0x11C8)
+#define EXYNOS5_SDMMC_MEM_SYS_PWR_REG				S5P_PMUREG(0x11D0)
+#define EXYNOS5_CSSYS_MEM_SYS_PWR_REG				S5P_PMUREG(0x11D4)
+#define EXYNOS5_SECSS_MEM_SYS_PWR_REG				S5P_PMUREG(0x11D8)
+#define EXYNOS5_ROTATOR_MEM_SYS_PWR_REG				S5P_PMUREG(0x11DC)
+#define EXYNOS5_INTRAM_MEM_SYS_PWR_REG				S5P_PMUREG(0x11E0)
+#define EXYNOS5_INTROM_MEM_SYS_PWR_REG				S5P_PMUREG(0x11E4)
+#define EXYNOS5_JPEG_MEM_SYS_PWR_REG				S5P_PMUREG(0x11E8)
+#define EXYNOS5_HSI_MEM_SYS_PWR_REG				S5P_PMUREG(0x11EC)
+#define EXYNOS5_MCUIOP_MEM_SYS_PWR_REG				S5P_PMUREG(0x11F4)
+#define EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG			S5P_PMUREG(0x1200)
+#define EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG			S5P_PMUREG(0x1204)
+#define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG			S5P_PMUREG(0x1220)
+#define EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG			S5P_PMUREG(0x1224)
+#define EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG			S5P_PMUREG(0x1228)
+#define EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG			S5P_PMUREG(0x122C)
+#define EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG			S5P_PMUREG(0x1230)
+#define EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG			S5P_PMUREG(0x1234)
+#define EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG			S5P_PMUREG(0x1238)
+#define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG		S5P_PMUREG(0x123C)
+#define EXYNOS5_PAD_ISOLATION_SYS_PWR_REG			S5P_PMUREG(0x1240)
+#define EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG		S5P_PMUREG(0x1250)
+#define EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG				S5P_PMUREG(0x1260)
+#define EXYNOS5_XUSBXTI_SYS_PWR_REG				S5P_PMUREG(0x1280)
+#define EXYNOS5_XXTI_SYS_PWR_REG				S5P_PMUREG(0x1284)
+#define EXYNOS5_EXT_REGULATOR_SYS_PWR_REG			S5P_PMUREG(0x12C0)
+#define EXYNOS5_GPIO_MODE_SYS_PWR_REG				S5P_PMUREG(0x1300)
+#define EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG			S5P_PMUREG(0x1320)
+#define EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG			S5P_PMUREG(0x1340)
+#define EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG			S5P_PMUREG(0x1344)
+#define EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG			S5P_PMUREG(0x1348)
+#define EXYNOS5_GSCL_SYS_PWR_REG				S5P_PMUREG(0x1400)
+#define EXYNOS5_ISP_SYS_PWR_REG					S5P_PMUREG(0x1404)
+#define EXYNOS5_MFC_SYS_PWR_REG					S5P_PMUREG(0x1408)
+#define EXYNOS5_G3D_SYS_PWR_REG					S5P_PMUREG(0x140C)
+#define EXYNOS5_DISP0_SYS_PWR_REG				S5P_PMUREG(0x1410)
+#define EXYNOS5_DISP1_SYS_PWR_REG				S5P_PMUREG(0x1414)
+#define EXYNOS5_MAU_SYS_PWR_REG					S5P_PMUREG(0x1418)
+#define EXYNOS5_GPS_SYS_PWR_REG					S5P_PMUREG(0x141C)
+#define EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG			S5P_PMUREG(0x1480)
+#define EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG			S5P_PMUREG(0x1484)
+#define EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG			S5P_PMUREG(0x1488)
+#define EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG			S5P_PMUREG(0x148C)
+#define EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG			S5P_PMUREG(0x1494)
+#define EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG			S5P_PMUREG(0x1498)
+#define EXYNOS5_CMU_CLKSTOP_GPS_SYS_PWR_REG			S5P_PMUREG(0x149C)
+#define EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG			S5P_PMUREG(0x14C0)
+#define EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG			S5P_PMUREG(0x14C4)
+#define EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG			S5P_PMUREG(0x14C8)
+#define EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG			S5P_PMUREG(0x14CC)
+#define EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG			S5P_PMUREG(0x14D4)
+#define EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG			S5P_PMUREG(0x14D8)
+#define EXYNOS5_CMU_SYSCLK_GPS_SYS_PWR_REG			S5P_PMUREG(0x14DC)
+#define EXYNOS5_CMU_SCLKSTOP_GSCL_SYS_PWR_REG			S5P_PMUREG(0x1500)
+#define EXYNOS5_CMU_SCLKSTOP_ISP_SYS_PWR_REG			S5P_PMUREG(0x1504)
+#define EXYNOS5_CMU_SCLKSTOP_MFC_SYS_PWR_REG			S5P_PMUREG(0x1508)
+#define EXYNOS5_CMU_SCLKSTOP_G3D_SYS_PWR_REG			S5P_PMUREG(0x150C)
+#define EXYNOS5_CMU_SCLKSTOP_DISP1_SYS_PWR_REG			S5P_PMUREG(0x1514)
+#define EXYNOS5_CMU_SCLKSTOP_MAU_SYS_PWR_REG			S5P_PMUREG(0x1518)
+#define EXYNOS5_CMU_SCLKSTOP_GPS_SYS_PWR_REG			S5P_PMUREG(0x151C)
+#define EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG			S5P_PMUREG(0x1580)
+#define EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG			S5P_PMUREG(0x1584)
+#define EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG			S5P_PMUREG(0x1588)
+#define EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG			S5P_PMUREG(0x158C)
+#define EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG			S5P_PMUREG(0x1594)
+#define EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG			S5P_PMUREG(0x1598)
+#define EXYNOS5_CMU_RESET_GPS_SYS_PWR_REG			S5P_PMUREG(0x159C)
+
+/* Definition for XXX_OPTION */
+#define EXYNOS5_OPTION_USE_STANDBYWFE				(1 << 24)
+#define EXYNOS5_OPTION_USE_STANDBYWFI				(1 << 16)
+#define EXYNOS5_OPTION_USE_RETENTION				(1 << 4)
+#define EXYNOS5_USE_SC_FEEDBACK					(1 << 1)
+#define EXYNOS5_USE_SC_COUNTER					(1 << 0)
+
+#define EXYNOS5_ARM_CORE0_CONFIGURATION				S5P_PMUREG(0x2000)
+#define EXYNOS5_ARM_CORE0_STATUS				S5P_PMUREG(0x2004)
+#define EXYNOS5_ARM_CORE0_OPTION				S5P_PMUREG(0x2008)
+#define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_CONFIGURATION		S5P_PMUREG(0x2020)
+#define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_STATUS			S5P_PMUREG(0x2024)
+#define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_OPTION			S5P_PMUREG(0x2028)
+#define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_CONFIGURATION		S5P_PMUREG(0x2040)
+#define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_STATUS		S5P_PMUREG(0x2044)
+#define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_OPTION		S5P_PMUREG(0x2048)
+#define EXYNOS5_ARM_CORE1_CONFIGURATION				S5P_PMUREG(0x2080)
+#define EXYNOS5_ARM_CORE1_STATUS				S5P_PMUREG(0x2084)
+#define EXYNOS5_ARM_CORE1_OPTION				S5P_PMUREG(0x2088)
+#define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_CONFIGURATION		S5P_PMUREG(0x20A0)
+#define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_STATUS			S5P_PMUREG(0x20A4)
+#define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_OPTION			S5P_PMUREG(0x20A8)
+#define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_CONFIGURATION		S5P_PMUREG(0x20C0)
+#define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_STATUS		S5P_PMUREG(0x20C4)
+#define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_OPTION		S5P_PMUREG(0x20C8)
+#define EXYNOS5_FSYS_ARM_CONFIGURATION				S5P_PMUREG(0x2200)
+#define EXYNOS5_FSYS_ARM_STATUS					S5P_PMUREG(0x2204)
+#define EXYNOS5_FSYS_ARM_OPTION					S5P_PMUREG(0x2208)
+#define EXYNOS5_DIS_IRQ_FSYS_ARM_LOCAL_CONFIGURATION		S5P_PMUREG(0x2220)
+#define EXYNOS5_DIS_IRQ_FSYS_ARM_LOCAL_STATUS			S5P_PMUREG(0x2224)
+#define EXYNOS5_DIS_IRQ_FSYS_ARM_LOCAL_OPTION			S5P_PMUREG(0x2228)
+#define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_CONFIGURATION		S5P_PMUREG(0x2240)
+#define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_STATUS			S5P_PMUREG(0x2244)
+#define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_OPTION			S5P_PMUREG(0x2248)
+#define EXYNOS5_ISP_ARM_CONFIGURATION				S5P_PMUREG(0x2280)
+#define EXYNOS5_ISP_ARM_STATUS					S5P_PMUREG(0x2284)
+#define EXYNOS5_ISP_ARM_OPTION					S5P_PMUREG(0x2288)
+
+#define EXYNOS5_ISP_ARM_ENABLE					(1 << 15)
+
+#define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_CONFIGURATION		S5P_PMUREG(0x22A0)
+#define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_STATUS			S5P_PMUREG(0x22A4)
+#define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_OPTION			S5P_PMUREG(0x22A8)
+#define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_CONFIGURATION		S5P_PMUREG(0x22C0)
+#define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_STATUS			S5P_PMUREG(0x22C4)
+#define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_OPTION			S5P_PMUREG(0x22C8)
+#define EXYNOS5_ARM_COMMON_CONFIGURATION			S5P_PMUREG(0x2400)
+#define EXYNOS5_ARM_COMMON_STATUS				S5P_PMUREG(0x2404)
+#define EXYNOS5_ARM_COMMON_OPTION				S5P_PMUREG(0x2408)
+
+#define EXYNOS5_MANUAL_L2RSTDISABLE_CONTROL			(1 << 2)
+#define EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN			(1 << 7)
+
+#define EXYNOS5_ARM_L2_CONFIGURATION				S5P_PMUREG(0x2600)
+#define EXYNOS5_ARM_L2_STATUS					S5P_PMUREG(0x2604)
+#define EXYNOS5_ARM_L2_OPTION					S5P_PMUREG(0x2608)
+#define EXYNOS5_CMU_ACLKSTOP_CONFIGURATION			S5P_PMUREG(0x2800)
+#define EXYNOS5_CMU_ACLKSTOP_STATUS				S5P_PMUREG(0x2804)
+#define EXYNOS5_CMU_ACLKSTOP_OPTION				S5P_PMUREG(0x2808)
+#define EXYNOS5_CMU_SCLKSTOP_CONFIGURATION			S5P_PMUREG(0x2820)
+#define EXYNOS5_CMU_SCLKSTOP_STATUS				S5P_PMUREG(0x2824)
+#define EXYNOS5_CMU_SCLKSTOP_OPTION				S5P_PMUREG(0x2828)
+#define EXYNOS5_CMU_RESET_CONFIGURATION				S5P_PMUREG(0x2860)
+#define EXYNOS5_CMU_RESET_STATUS				S5P_PMUREG(0x2864)
+#define EXYNOS5_CMU_RESET_OPTION				S5P_PMUREG(0x2868)
+#define EXYNOS5_CMU_ACLKSTOP_SYSMEM_CONFIGURATION		S5P_PMUREG(0x2900)
+#define EXYNOS5_CMU_ACLKSTOP_SYSMEM_STATUS			S5P_PMUREG(0x2904)
+#define EXYNOS5_CMU_ACLKSTOP_SYSMEM_OPTION			S5P_PMUREG(0x2908)
+#define EXYNOS5_CMU_SCLKSTOP_SYSMEM_CONFIGURATION		S5P_PMUREG(0x2920)
+#define EXYNOS5_CMU_SCLKSTOP_SYSMEM_STATUS			S5P_PMUREG(0x2924)
+#define EXYNOS5_CMU_SCLKSTOP_SYSMEM_OPTION			S5P_PMUREG(0x2928)
+#define EXYNOS5_CMU_RESET_SYSMEM_CONFIGURATION			S5P_PMUREG(0x2960)
+#define EXYNOS5_CMU_RESET_SYSMEM_STATUS				S5P_PMUREG(0x2964)
+#define EXYNOS5_CMU_RESET_SYSMEM_OPTION				S5P_PMUREG(0x2968)
+#define EXYNOS5_DRAM_FREQ_DOWN_CONFIGURATION			S5P_PMUREG(0x2980)
+#define EXYNOS5_DRAM_FREQ_DOWN_STATUS				S5P_PMUREG(0x2984)
+#define EXYNOS5_DRAM_FREQ_DOWN_OPTION				S5P_PMUREG(0x2988)
+#define EXYNOS5_DDRPHY_DLLOFF_CONFIGURATION			S5P_PMUREG(0x29A0)
+#define EXYNOS5_DDRPHY_DLLOFF_STATUS				S5P_PMUREG(0x29A4)
+#define EXYNOS5_DDRPHY_DLLOFF_OPTION				S5P_PMUREG(0x29A8)
+#define EXYNOS5_DDRPHY_DLLLOCK_CONFIGURATION			S5P_PMUREG(0x29C0)
+#define EXYNOS5_DDRPHY_DLLLOCK_STATUS				S5P_PMUREG(0x29C4)
+#define EXYNOS5_DDRPHY_DLLLOCK_OPTION				S5P_PMUREG(0x29C8)
+#define EXYNOS5_APLL_SYSCLK_CONFIGURATION			S5P_PMUREG(0x2A00)
+#define EXYNOS5_APLL_SYSCLK_STATUS				S5P_PMUREG(0x2A04)
+#define EXYNOS5_APLL_SYSCLK_OPTION				S5P_PMUREG(0x2A08)
+#define EXYNOS5_MPLL_SYSCLK_STATUS				S5P_PMUREG(0x2A24)
+#define EXYNOS5_MPLL_SYSCLK_OPTION				S5P_PMUREG(0x2A28)
+#define EXYNOS5_VPLL_SYSCLK_CONFIGURATION			S5P_PMUREG(0x2A40)
+#define EXYNOS5_VPLL_SYSCLK_STATUS				S5P_PMUREG(0x2A44)
+#define EXYNOS5_VPLL_SYSCLK_OPTION				S5P_PMUREG(0x2A48)
+#define EXYNOS5_EPLL_SYSCLK_CONFIGURATION			S5P_PMUREG(0x2A60)
+#define EXYNOS5_EPLL_SYSCLK_STATUS				S5P_PMUREG(0x2A64)
+#define EXYNOS5_EPLL_SYSCLK_OPTION				S5P_PMUREG(0x2A68)
+#define EXYNOS5_BPLL_SYSCLK_CONFIGURATION			S5P_PMUREG(0x2A80)
+#define EXYNOS5_BPLL_SYSCLK_STATUS				S5P_PMUREG(0x2A84)
+#define EXYNOS5_BPLL_SYSCLK_OPTION				S5P_PMUREG(0x2A88)
+#define EXYNOS5_CPLL_SYSCLK_CONFIGURATION			S5P_PMUREG(0x2AA0)
+#define EXYNOS5_CPLL_SYSCLK_STATUS				S5P_PMUREG(0x2AA4)
+#define EXYNOS5_CPLL_SYSCLK_OPTION				S5P_PMUREG(0x2AA8)
+#define EXYNOS5_MPLLUSER_SYSCLK_CONFIGURATION			S5P_PMUREG(0x2B20)
+#define EXYNOS5_MPLLUSER_SYSCLK_STATUS				S5P_PMUREG(0x2B24)
+#define EXYNOS5_MPLLUSER_SYSCLK_OPTION				S5P_PMUREG(0x2B28)
+#define EXYNOS5_BPLLUSER_SYSCLK_CONFIGURATION			S5P_PMUREG(0x2B80)
+#define EXYNOS5_BPLLUSER_SYSCLK_STATUS				S5P_PMUREG(0x2B84)
+#define EXYNOS5_BPLLUSER_SYSCLK_OPTION				S5P_PMUREG(0x2B88)
+#define EXYNOS5_TOP_BUS_CONFIGURATION				S5P_PMUREG(0x2C00)
+#define EXYNOS5_TOP_BUS_STATUS					S5P_PMUREG(0x2C04)
+#define EXYNOS5_TOP_BUS_OPTION					S5P_PMUREG(0x2C08)
+#define EXYNOS5_TOP_RETENTION_CONFIGURATION			S5P_PMUREG(0x2C20)
+#define EXYNOS5_TOP_RETENTION_STATUS				S5P_PMUREG(0x2C24)
+#define EXYNOS5_TOP_RETENTION_OPTION				S5P_PMUREG(0x2C28)
+#define EXYNOS5_TOP_PWR_CONFIGURATION				S5P_PMUREG(0x2C40)
+#define EXYNOS5_TOP_PWR_STATUS					S5P_PMUREG(0x2C44)
+#define EXYNOS5_TOP_PWR_OPTION					S5P_PMUREG(0x2C48)
+#define EXYNOS5_TOP_BUS_SYSMEM_CONFIGURATION			S5P_PMUREG(0x2C80)
+#define EXYNOS5_TOP_BUS_SYSMEM_STATUS				S5P_PMUREG(0x2C84)
+#define EXYNOS5_TOP_BUS_SYSMEM_OPTION				S5P_PMUREG(0x2C88)
+#define EXYNOS5_TOP_RETENTION_SYSMEM_CONFIGURATION		S5P_PMUREG(0x2CA0)
+#define EXYNOS5_TOP_RETENTION_SYSMEM_STATUS			S5P_PMUREG(0x2CA4)
+#define EXYNOS5_TOP_RETENTION_SYSMEM_OPTION			S5P_PMUREG(0x2CA8)
+#define EXYNOS5_TOP_PWR_SYSMEM_CONFIGURATION			S5P_PMUREG(0x2CC0)
+#define EXYNOS5_TOP_PWR_SYSMEM_STATUS				S5P_PMUREG(0x2CC4)
+#define EXYNOS5_TOP_PWR_SYSMEM_OPTION				S5P_PMUREG(0x2CC8)
+#define EXYNOS5_LOGIC_RESET_CONFIGURATION			S5P_PMUREG(0x2D00)
+#define EXYNOS5_LOGIC_RESET_STATUS				S5P_PMUREG(0x2D04)
+#define EXYNOS5_LOGIC_RESET_OPTION				S5P_PMUREG(0x2D08)
+#define EXYNOS5_OSCCLK_GATE_CONFIGURATION			S5P_PMUREG(0x2D20)
+#define EXYNOS5_OSCCLK_GATE_STATUS				S5P_PMUREG(0x2D24)
+#define EXYNOS5_OSCCLK_GATE_OPTION				S5P_PMUREG(0x2D28)
+#define EXYNOS5_LOGIC_RESET_SYSMEM_CONFIGURATION		S5P_PMUREG(0x2D80)
+#define EXYNOS5_LOGIC_RESET_SYSMEM_STATUS			S5P_PMUREG(0x2D84)
+#define EXYNOS5_LOGIC_RESET_SYSMEM_OPTION			S5P_PMUREG(0x2D88)
+#define EXYNOS5_OSCCLK_GATE_SYSMEM_CONFIGURATION		S5P_PMUREG(0x2DA0)
+#define EXYNOS5_OSCCLK_GATE_SYSMEM_STATUS			S5P_PMUREG(0x2DA4)
+#define EXYNOS5_OSCCLK_GATE_SYSMEM_OPTION			S5P_PMUREG(0x2DA8)
+#define EXYNOS5_OneNANDXL_MEM_CONFIGURATION			S5P_PMUREG(0x2E00)
+#define EXYNOS5_OneNANDXL_MEM_STATUS				S5P_PMUREG(0x2E04)
+#define EXYNOS5_OneNANDXL_MEM_OPTION				S5P_PMUREG(0x2E08)
+#define EXYNOS5_G2D_MEM_CONFIGURATION				S5P_PMUREG(0x2E40)
+#define EXYNOS5_G2D_MEM_STATUS					S5P_PMUREG(0x2E44)
+#define EXYNOS5_G2D_MEM_OPTION					S5P_PMUREG(0x2E48)
+#define EXYNOS5_USBDEV_MEM_CONFIGURATION			S5P_PMUREG(0x2E60)
+#define EXYNOS5_USBDEV_MEM_STATUS				S5P_PMUREG(0x2E64)
+#define EXYNOS5_USBDEV_MEM_OPTION				S5P_PMUREG(0x2E68)
+#define EXYNOS5_SDMMC_MEM_CONFIGURATION				S5P_PMUREG(0x2E80)
+#define EXYNOS5_SDMMC_MEM_STATUS				S5P_PMUREG(0x2E84)
+#define EXYNOS5_SDMMC_MEM_OPTION				S5P_PMUREG(0x2E88)
+#define EXYNOS5_CSSYS_MEM_CONFIGURATION				S5P_PMUREG(0x2EA0)
+#define EXYNOS5_CSSYS_MEM_STATUS				S5P_PMUREG(0x2EA4)
+#define EXYNOS5_CSSYS_MEM_OPTION				S5P_PMUREG(0x2EA8)
+#define EXYNOS5_SECSS_MEM_CONFIGURATION				S5P_PMUREG(0x2EC0)
+#define EXYNOS5_SECSS_MEM_STATUS				S5P_PMUREG(0x2EC4)
+#define EXYNOS5_SECSS_MEM_OPTION				S5P_PMUREG(0x2EC8)
+#define EXYNOS5_ROTATOR_MEM_CONFIGURATION			S5P_PMUREG(0x2EE0)
+#define EXYNOS5_ROTATOR_MEM_STATUS				S5P_PMUREG(0x2EE4)
+#define EXYNOS5_ROTATOR_MEM_OPTION				S5P_PMUREG(0x2EE8)
+#define EXYNOS5_INTRAM_MEM_CONFIGURATION			S5P_PMUREG(0x2F00)
+#define EXYNOS5_INTRAM_MEM_STATUS				S5P_PMUREG(0x2F04)
+#define EXYNOS5_INTRAM_MEM_OPTION				S5P_PMUREG(0x2F08)
+#define EXYNOS5_INTROM_MEM_CONFIGURATION			S5P_PMUREG(0x2F20)
+#define EXYNOS5_INTROM_MEM_STATUS				S5P_PMUREG(0x2F24)
+#define EXYNOS5_INTROM_MEM_OPTION				S5P_PMUREG(0x2F28)
+#define EXYNOS5_JPEG_MEM_CONFIGURATION				S5P_PMUREG(0x2F40)
+#define EXYNOS5_JPEG_MEM_STATUS					S5P_PMUREG(0x2F44)
+#define EXYNOS5_JPEG_MEM_OPTION					S5P_PMUREG(0x2F48)
+#define EXYNOS5_HSI_MEM_CONFIGURATION				S5P_PMUREG(0x2F60)
+#define EXYNOS5_HSI_MEM_STATUS					S5P_PMUREG(0x2F64)
+#define EXYNOS5_HSI_MEM_OPTION					S5P_PMUREG(0x2F68)
+#define EXYNOS5_MCUIOP_MEM_CONFIGURATION			S5P_PMUREG(0x2FA0)
+#define EXYNOS5_MCUIOP_MEM_STATUS				S5P_PMUREG(0x2FA4)
+#define EXYNOS5_MCUIOP_MEM_OPTION				S5P_PMUREG(0x2FA8)
+#define EXYNOS5_PAD_RETENTION_DRAM_CONFIGURATION		S5P_PMUREG(0x3000)
+#define EXYNOS5_PAD_RETENTION_DRAM_STATUS			S5P_PMUREG(0x3004)
+#define EXYNOS5_PAD_RETENTION_DRAM_OPTION			S5P_PMUREG(0x3008)
+#define EXYNOS5_PAD_RETENTION_MAU_CONFIGURATION			S5P_PMUREG(0x3020)
+#define EXYNOS5_PAD_RETENTION_MAU_STATUS			S5P_PMUREG(0x3024)
+#define EXYNOS5_PAD_RETENTION_MAU_OPTION			S5P_PMUREG(0x3028)
+#define EXYNOS5_PAD_RETENTION_GPIO_CONFIGURATION		S5P_PMUREG(0x3100)
+#define EXYNOS5_PAD_RETENTION_GPIO_STATUS			S5P_PMUREG(0x3104)
+#define EXYNOS5_PAD_RETENTION_GPIO_OPTION			S5P_PMUREG(0x3108)
+#define EXYNOS5_PAD_RETENTION_UART_CONFIGURATION		S5P_PMUREG(0x3120)
+#define EXYNOS5_PAD_RETENTION_UART_STATUS			S5P_PMUREG(0x3124)
+#define EXYNOS5_PAD_RETENTION_UART_OPTION			S5P_PMUREG(0x3128)
+#define EXYNOS5_PAD_RETENTION_MMCA_CONFIGURATION		S5P_PMUREG(0x3140)
+#define EXYNOS5_PAD_RETENTION_MMCA_STATUS			S5P_PMUREG(0x3144)
+#define EXYNOS5_PAD_RETENTION_MMCA_OPTION			S5P_PMUREG(0x3148)
+#define EXYNOS5_PAD_RETENTION_MMCB_CONFIGURATION		S5P_PMUREG(0x3160)
+#define EXYNOS5_PAD_RETENTION_MMCB_STATUS			S5P_PMUREG(0x3164)
+#define EXYNOS5_PAD_RETENTION_MMCB_OPTION			S5P_PMUREG(0x3168)
+#define EXYNOS5_PAD_RETENTION_EBIA_CONFIGURATION		S5P_PMUREG(0x3180)
+#define EXYNOS5_PAD_RETENTION_EBIA_STATUS			S5P_PMUREG(0x3184)
+#define EXYNOS5_PAD_RETENTION_EBIA_OPTION			S5P_PMUREG(0x3188)
+#define EXYNOS5_PAD_RETENTION_EBIB_CONFIGURATION		S5P_PMUREG(0x31A0)
+#define EXYNOS5_PAD_RETENTION_EBIB_STATUS			S5P_PMUREG(0x31A4)
+#define EXYNOS5_PAD_RETENTION_EBIB_OPTION			S5P_PMUREG(0x31A8)
+#define EXYNOS5_PAD_RETENTION_SPI_CONFIGURATION			S5P_PMUREG(0x31C0)
+#define EXYNOS5_PAD_RETENTION_SPI_STATUS			S5P_PMUREG(0x31C4)
+#define EXYNOS5_PAD_RETENTION_SPI_OPTION			S5P_PMUREG(0x31C8)
+#define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_CONFIGURATION		S5P_PMUREG(0x31E0)
+#define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_STATUS		S5P_PMUREG(0x31E4)
+#define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_OPTION		S5P_PMUREG(0x31E8)
+#define EXYNOS5_PAD_ISOLATION_CONFIGURATION			S5P_PMUREG(0x3200)
+#define EXYNOS5_PAD_ISOLATION_STATUS				S5P_PMUREG(0x3204)
+#define EXYNOS5_PAD_ISOLATION_OPTION				S5P_PMUREG(0x3208)
+#define EXYNOS5_PAD_ISOLATION_SYSMEM_CONFIGURATION		S5P_PMUREG(0x3280)
+#define EXYNOS5_PAD_ISOLATION_SYSMEM_STATUS			S5P_PMUREG(0x3284)
+#define EXYNOS5_PAD_ISOLATION_SYSMEM_OPTION			S5P_PMUREG(0x3288)
+#define EXYNOS5_PAD_ALV_SEL_CONFIGURATION			S5P_PMUREG(0x3300)
+#define EXYNOS5_PAD_ALV_SEL_STATUS				S5P_PMUREG(0x3304)
+#define EXYNOS5_PAD_ALV_SEL_OPTION0				S5P_PMUREG(0x3308)
+#define EXYNOS5_PS_HOLD_CONTROL					S5P_PMUREG(0x330C)
+#define EXYNOS5_XUSBXTI_CONFIGURATION				S5P_PMUREG(0x3400)
+#define EXYNOS5_XUSBXTI_STATUS					S5P_PMUREG(0x3404)
+#define EXYNOS5_XUSBXTI_OPTION					S5P_PMUREG(0x3408)
+#define EXYNOS5_XUSBXTI_DURATION3				S5P_PMUREG(0x341C)
+#define EXYNOS5_XXTI_CONFIGURATION				S5P_PMUREG(0x3420)
+#define EXYNOS5_XXTI_STATUS					S5P_PMUREG(0x3424)
+#define EXYNOS5_XXTI_OPTION					S5P_PMUREG(0x3428)
+#define EXYNOS5_XXTI_DURATION3					S5P_PMUREG(0x343C)
+#define EXYNOS5_EXT_REGULATOR_CONFIGURATION			S5P_PMUREG(0x3600)
+#define EXYNOS5_EXT_REGULATOR_STATUS				S5P_PMUREG(0x3604)
+#define EXYNOS5_EXT_REGULATOR_OPTION				S5P_PMUREG(0x3608)
+#define EXYNOS5_EXT_REGULATOR_DURATION3				S5P_PMUREG(0x361C)
+#define EXYNOS5_GPIO_MODE_CONFIGURATION				S5P_PMUREG(0x3800)
+#define EXYNOS5_GPIO_MODE_STATUS				S5P_PMUREG(0x3804)
+#define EXYNOS5_GPIO_MODE_OPTION				S5P_PMUREG(0x3808)
+#define EXYNOS5_GPIO_MODE_SYSMEM_CONFIGURATION			S5P_PMUREG(0x3900)
+#define EXYNOS5_GPIO_MODE_SYSMEM_STATUS				S5P_PMUREG(0x3904)
+#define EXYNOS5_GPIO_MODE_SYSMEM_OPTION				S5P_PMUREG(0x3908)
+#define EXYNOS5_GPIO_MODE_MAU_CONFIGURATION			S5P_PMUREG(0x39E0)
+#define EXYNOS5_GPIO_MODE_MAU_STATUS				S5P_PMUREG(0x39E4)
+#define EXYNOS5_GPIO_MODE_MAU_OPTION				S5P_PMUREG(0x39E8)
+#define EXYNOS5_TOP_ASB_RESET_CONFIGURATION			S5P_PMUREG(0x3A00)
+#define EXYNOS5_TOP_ASB_RESET_STATUS				S5P_PMUREG(0x3A04)
+#define EXYNOS5_TOP_ASB_RESET_OPTION				S5P_PMUREG(0x3A08)
+#define EXYNOS5_TOP_ASB_ISOLATION_CONFIGURATION			S5P_PMUREG(0x3A20)
+#define EXYNOS5_TOP_ASB_ISOLATION_STATUS			S5P_PMUREG(0x3A24)
+#define EXYNOS5_TOP_ASB_ISOLATION_OPTION			S5P_PMUREG(0x3A28)
+#define EXYNOS5_GSCL_CONFIGURATION				S5P_PMUREG(0x4000)
+#define EXYNOS5_GSCL_STATUS					S5P_PMUREG(0x4004)
+#define EXYNOS5_GSCL_OPTION					S5P_PMUREG(0x4008)
+#define EXYNOS5_ISP_CONFIGURATION				S5P_PMUREG(0x4020)
+#define EXYNOS5_ISP_STATUS					S5P_PMUREG(0x4024)
+#define EXYNOS5_ISP_OPTION					S5P_PMUREG(0x4028)
+#define EXYNOS5_MFC_CONFIGURATION				S5P_PMUREG(0x4040)
+#define EXYNOS5_MFC_STATUS					S5P_PMUREG(0x4044)
+#define EXYNOS5_MFC_OPTION					S5P_PMUREG(0x4048)
+#define EXYNOS5_G3D_CONFIGURATION				S5P_PMUREG(0x4060)
+#define EXYNOS5_G3D_STATUS					S5P_PMUREG(0x4064)
+#define EXYNOS5_G3D_OPTION					S5P_PMUREG(0x4068)
+#define EXYNOS5_DISP1_CONFIGURATION				S5P_PMUREG(0x40A0)
+#define EXYNOS5_DISP1_STATUS					S5P_PMUREG(0x40A4)
+#define EXYNOS5_DISP1_OPTION					S5P_PMUREG(0x40A8)
+#define EXYNOS5_MAU_CONFIGURATION				S5P_PMUREG(0x40C0)
+#define EXYNOS5_MAU_STATUS					S5P_PMUREG(0x40C4)
+#define EXYNOS5_MAU_OPTION					S5P_PMUREG(0x40C8)
+#define EXYNOS5_GPS_CONFIGURATION				S5P_PMUREG(0x40E0)
+#define EXYNOS5_GPS_STATUS					S5P_PMUREG(0x40E4)
+#define EXYNOS5_GPS_OPTION					S5P_PMUREG(0x40E8)
+#define EXYNOS5_CMU_CLKSTOP_GSCL_CONFIGURATION			S5P_PMUREG(0x4400)
+#define EXYNOS5_CMU_CLKSTOP_GSCL_STATUS				S5P_PMUREG(0x4404)
+#define EXYNOS5_CMU_CLKSTOP_GSCL_OPTION				S5P_PMUREG(0x4408)
+#define EXYNOS5_CMU_CLKSTOP_ISP_CONFIGURATION			S5P_PMUREG(0x4420)
+#define EXYNOS5_CMU_CLKSTOP_ISP_STATUS				S5P_PMUREG(0x4424)
+#define EXYNOS5_CMU_CLKSTOP_ISP_OPTION				S5P_PMUREG(0x4428)
+#define EXYNOS5_CMU_CLKSTOP_MFC_CONFIGURATION			S5P_PMUREG(0x4440)
+#define EXYNOS5_CMU_CLKSTOP_MFC_STATUS				S5P_PMUREG(0x4444)
+#define EXYNOS5_CMU_CLKSTOP_MFC_OPTION				S5P_PMUREG(0x4448)
+#define EXYNOS5_CMU_CLKSTOP_G3D_CONFIGURATION			S5P_PMUREG(0x4460)
+#define EXYNOS5_CMU_CLKSTOP_G3D_STATUS				S5P_PMUREG(0x4464)
+#define EXYNOS5_CMU_CLKSTOP_G3D_OPTION				S5P_PMUREG(0x4468)
+#define EXYNOS5_CMU_CLKSTOP_DISP1_CONFIGURATION			S5P_PMUREG(0x44A0)
+#define EXYNOS5_CMU_CLKSTOP_DISP1_STATUS			S5P_PMUREG(0x44A4)
+#define EXYNOS5_CMU_CLKSTOP_DISP1_OPTION			S5P_PMUREG(0x44A8)
+#define EXYNOS5_CMU_CLKSTOP_MAU_CONFIGURATION			S5P_PMUREG(0x44C0)
+#define EXYNOS5_CMU_CLKSTOP_MAU_STATUS				S5P_PMUREG(0x44C4)
+#define EXYNOS5_CMU_CLKSTOP_MAU_OPTION				S5P_PMUREG(0x44C8)
+#define EXYNOS5_CMU_CLKSTOP_GPS_CONFIGURATION			S5P_PMUREG(0x44E0)
+#define EXYNOS5_CMU_CLKSTOP_GPS_STATUS				S5P_PMUREG(0x44E4)
+#define EXYNOS5_CMU_CLKSTOP_GPS_OPTION				S5P_PMUREG(0x44E8)
+#define EXYNOS5_CMU_SYSCLK_GSCL_CONFIGURATION			S5P_PMUREG(0x4600)
+#define EXYNOS5_CMU_SYSCLK_GSCL_STATUS				S5P_PMUREG(0x4604)
+#define EXYNOS5_CMU_SYSCLK_GSCL_OPTION				S5P_PMUREG(0x4608)
+#define EXYNOS5_CMU_SYSCLK_ISP_STATUS				S5P_PMUREG(0x4624)
+#define EXYNOS5_CMU_SYSCLK_ISP_OPTION				S5P_PMUREG(0x4628)
+#define EXYNOS5_CMU_SYSCLK_MFC_STATUS				S5P_PMUREG(0x4644)
+#define EXYNOS5_CMU_SYSCLK_MFC_OPTION				S5P_PMUREG(0x4648)
+#define EXYNOS5_CMU_SYSCLK_G3D_STATUS				S5P_PMUREG(0x4664)
+#define EXYNOS5_CMU_SYSCLK_G3D_OPTION				S5P_PMUREG(0x4668)
+#define EXYNOS5_CMU_SYSCLK_DISP1_STATUS				S5P_PMUREG(0x46A4)
+#define EXYNOS5_CMU_SYSCLK_DISP1_OPTION				S5P_PMUREG(0x46A8)
+#define EXYNOS5_CMU_SYSCLK_MAU_STATUS				S5P_PMUREG(0x46C4)
+#define EXYNOS5_CMU_SYSCLK_MAU_OPTION				S5P_PMUREG(0x46C8)
+#define EXYNOS5_CMU_SYSCLK_GPS_STATUS				S5P_PMUREG(0x46E4)
+#define EXYNOS5_CMU_SYSCLK_GPS_OPTION				S5P_PMUREG(0x46E8)
+#define EXYNOS5_CMU_RESET_GSCL_CONFIGURATION			S5P_PMUREG(0x4C00)
+#define EXYNOS5_CMU_RESET_GSCL_STATUS				S5P_PMUREG(0x4C04)
+#define EXYNOS5_CMU_RESET_GSCL_OPTION				S5P_PMUREG(0x4C08)
+#define EXYNOS5_CMU_RESET_ISP_CONFIGURATION			S5P_PMUREG(0x4C20)
+#define EXYNOS5_CMU_RESET_ISP_STATUS				S5P_PMUREG(0x4C24)
+#define EXYNOS5_CMU_RESET_ISP_OPTION				S5P_PMUREG(0x4C28)
+#define EXYNOS5_CMU_RESET_MFC_CONFIGURATION			S5P_PMUREG(0x4C40)
+#define EXYNOS5_CMU_RESET_MFC_STATUS				S5P_PMUREG(0x4C44)
+#define EXYNOS5_CMU_RESET_MFC_OPTION				S5P_PMUREG(0x4C48)
+#define EXYNOS5_CMU_RESET_G3D_CONFIGURATION			S5P_PMUREG(0x4C60)
+#define EXYNOS5_CMU_RESET_G3D_STATUS				S5P_PMUREG(0x4C64)
+#define EXYNOS5_CMU_RESET_G3D_OPTION				S5P_PMUREG(0x4C68)
+#define EXYNOS5_CMU_RESET_DISP0_CONFIGURATION			S5P_PMUREG(0x4C80)
+#define EXYNOS5_CMU_RESET_DISP0_STATUS				S5P_PMUREG(0x4C84)
+#define EXYNOS5_CMU_RESET_DISP0_OPTION				S5P_PMUREG(0x4C88)
+#define EXYNOS5_CMU_RESET_DISP1_CONFIGURATION			S5P_PMUREG(0x4CA0)
+#define EXYNOS5_CMU_RESET_DISP1_STATUS				S5P_PMUREG(0x4CA4)
+#define EXYNOS5_CMU_RESET_DISP1_OPTION				S5P_PMUREG(0x4CA8)
+#define EXYNOS5_CMU_RESET_MAU_CONFIGURATION			S5P_PMUREG(0x4CC0)
+#define EXYNOS5_CMU_RESET_MAU_STATUS				S5P_PMUREG(0x4CC4)
+#define EXYNOS5_CMU_RESET_MAU_OPTION				S5P_PMUREG(0x4CC8)
+#define EXYNOS5_CMU_RESET_GPS_CONFIGURATION			S5P_PMUREG(0x4CE0)
+#define EXYNOS5_CMU_RESET_GPS_STATUS				S5P_PMUREG(0x4CE4)
+#define EXYNOS5_CMU_RESET_GPS_OPTION				S5P_PMUREG(0x4CE8)
+
+#endif /* __ASM_ARCH_REGS_PMU5_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-sdo.h b/arch/arm/mach-exynos/include/mach/regs-sdo.h
new file mode 100644
index 0000000..7e1344c
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/regs-sdo.h
@@ -0,0 +1,449 @@
+/* linux/arch/arm/mach-exynos/include/mach/regs-sdo.h
+ *
+ * Copyright (c) 2010 Samsung Electronics
+ *		http://www.samsung.com/
+ *
+ * SDO register description file for Samsung TVOUT driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_REGS_SDO_H
+#define __ARCH_ARM_REGS_SDO_H
+
+/*
+ * Register part
+ */
+#define S5P_SDO_CLKCON				(0x0000)
+#define S5P_SDO_CONFIG				(0x0008)
+#define S5P_SDO_SCALE				(0x000C)
+#define S5P_SDO_SYNC				(0x0010)
+#define S5P_SDO_VBI				(0x0014)
+#define S5P_SDO_SCALE_CH0			(0x001C)
+#define S5P_SDO_SCALE_CH1			(0x0020)
+#define S5P_SDO_SCALE_CH2			(0x0024)
+#define S5P_SDO_YCDELAY				(0x0034)
+#define S5P_SDO_SCHLOCK				(0x0038)
+#define S5P_SDO_DAC				(0x003C)
+#define S5P_SDO_FINFO				(0x0040)
+#define S5P_SDO_Y0				(0x0044)
+#define S5P_SDO_Y1				(0x0048)
+#define S5P_SDO_Y2				(0x004C)
+#define S5P_SDO_Y3				(0x0050)
+#define S5P_SDO_Y4				(0x0054)
+#define S5P_SDO_Y5				(0x0058)
+#define S5P_SDO_Y6				(0x005C)
+#define S5P_SDO_Y7				(0x0060)
+#define S5P_SDO_Y8				(0x0064)
+#define S5P_SDO_Y9				(0x0068)
+#define S5P_SDO_Y10				(0x006C)
+#define S5P_SDO_Y11				(0x0070)
+#define S5P_SDO_CB0				(0x0080)
+#define S5P_SDO_CB1				(0x0084)
+#define S5P_SDO_CB2				(0x0088)
+#define S5P_SDO_CB3				(0x008C)
+#define S5P_SDO_CB4				(0x0090)
+#define S5P_SDO_CB5				(0x0094)
+#define S5P_SDO_CB6				(0x0098)
+#define S5P_SDO_CB7				(0x009C)
+#define S5P_SDO_CB8				(0x00A0)
+#define S5P_SDO_CB9				(0x00A4)
+#define S5P_SDO_CB10				(0x00A8)
+#define S5P_SDO_CB11				(0x00AC)
+#define S5P_SDO_CR0				(0x00C0)
+#define S5P_SDO_CR1				(0x00C4)
+#define S5P_SDO_CR2				(0x00C8)
+#define S5P_SDO_CR3				(0x00CC)
+#define S5P_SDO_CR4				(0x00D0)
+#define S5P_SDO_CR5				(0x00D4)
+#define S5P_SDO_CR6				(0x00D8)
+#define S5P_SDO_CR7				(0x00DC)
+#define S5P_SDO_CR8				(0x00E0)
+#define S5P_SDO_CR9				(0x00E4)
+#define S5P_SDO_CR10				(0x00E8)
+#define S5P_SDO_CR11				(0x00EC)
+#define S5P_SDO_MV_ON				(0x0100)
+#define S5P_SDO_MV_SLINE_FIRST_EVEN		(0x0104)
+#define S5P_SDO_MV_SLINE_FIRST_SPACE_EVEN	(0x0108)
+#define S5P_SDO_MV_SLINE_FIRST_ODD		(0x010C)
+#define S5P_SDO_MV_SLINE_FIRST_SPACE_ODD	(0x0110)
+#define S5P_SDO_MV_SLINE_SPACING		(0x0114)
+#define S5P_SDO_MV_STRIPES_NUMBER		(0x0118)
+#define S5P_SDO_MV_STRIPES_THICKNESS		(0x011C)
+#define S5P_SDO_MV_PSP_DURATION			(0x0120)
+#define S5P_SDO_MV_PSP_FIRST			(0x0124)
+#define S5P_SDO_MV_PSP_SPACING			(0x0128)
+#define S5P_SDO_MV_SEL_LINE_PSP_AGC		(0x012C)
+#define S5P_SDO_MV_SEL_FORMAT_PSP_AGC		(0x0130)
+#define S5P_SDO_MV_PSP_AGC_A_ON			(0x0134)
+#define S5P_SDO_MV_PSP_AGC_B_ON			(0x0138)
+#define S5P_SDO_MV_BACK_PORCH			(0x013C)
+#define S5P_SDO_MV_BURST_ADVANCED_ON		(0x0140)
+#define S5P_SDO_MV_BURST_DURATION_ZONE1		(0x0144)
+#define S5P_SDO_MV_BURST_DURATION_ZONE2		(0x0148)
+#define S5P_SDO_MV_BURST_DURATION_ZONE3		(0x014C)
+#define S5P_SDO_MV_BURST_PHASE_ZONE		(0x0150)
+#define S5P_SDO_MV_SLICE_PHASE_LINE		(0x0154)
+#define S5P_SDO_MV_RGB_PROTECTION_ON		(0x0158)
+#define S5P_SDO_MV_480P_PROTECTION_ON		(0x015C)
+#define S5P_SDO_CCCON				(0x0180)
+#define S5P_SDO_YSCALE				(0x0184)
+#define S5P_SDO_CBSCALE				(0x0188)
+#define S5P_SDO_CRSCALE				(0x018C)
+#define S5P_SDO_CB_CR_OFFSET			(0x0190)
+#define S5P_SDO_CVBS_CC_Y1			(0x0198)
+#define S5P_SDO_CVBS_CC_Y2			(0x019C)
+#define S5P_SDO_CVBS_CC_C			(0x01A0)
+#define S5P_SDO_CSC_525_PORCH			(0x01B0)
+#define S5P_SDO_CSC_625_PORCH			(0x01B4)
+#define S5P_SDO_OSFC00_0			(0x0200)
+#define S5P_SDO_OSFC01_0			(0x0204)
+#define S5P_SDO_OSFC02_0			(0x0208)
+#define S5P_SDO_OSFC03_0			(0x020C)
+#define S5P_SDO_OSFC04_0			(0x0210)
+#define S5P_SDO_OSFC05_0			(0x0214)
+#define S5P_SDO_OSFC06_0			(0x0218)
+#define S5P_SDO_OSFC07_0			(0x021C)
+#define S5P_SDO_OSFC08_0			(0x0220)
+#define S5P_SDO_OSFC09_0			(0x0224)
+#define S5P_SDO_OSFC10_0			(0x0228)
+#define S5P_SDO_OSFC11_0			(0x022C)
+#define S5P_SDO_OSFC12_0			(0x0230)
+#define S5P_SDO_OSFC13_0			(0x0234)
+#define S5P_SDO_OSFC14_0			(0x0238)
+#define S5P_SDO_OSFC15_0			(0x023C)
+#define S5P_SDO_OSFC16_0			(0x0240)
+#define S5P_SDO_OSFC17_0			(0x0244)
+#define S5P_SDO_OSFC18_0			(0x0248)
+#define S5P_SDO_OSFC19_0			(0x024C)
+#define S5P_SDO_OSFC20_0			(0x0250)
+#define S5P_SDO_OSFC21_0			(0x0254)
+#define S5P_SDO_OSFC22_0			(0x0258)
+#define S5P_SDO_OSFC23_0			(0x025C)
+#define S5P_SDO_XTALK0				(0x0260)
+#define S5P_SDO_XTALK1				(0x0264)
+#define S5P_SDO_XTALK2				(0x0268)
+#define S5P_SDO_BB_CTRL				(0x026C)
+#define S5P_SDO_IRQ				(0x0280)
+#define S5P_SDO_IRQMASK				(0x0284)
+#define S5P_SDO_OSFC00_1			(0x02C0)
+#define S5P_SDO_OSFC01_1			(0x02C4)
+#define S5P_SDO_OSFC02_1			(0x02C8)
+#define S5P_SDO_OSFC03_1			(0x02CC)
+#define S5P_SDO_OSFC04_1			(0x02D0)
+#define S5P_SDO_OSFC05_1			(0x02D4)
+#define S5P_SDO_OSFC06_1			(0x02D8)
+#define S5P_SDO_OSFC07_1			(0x02DC)
+#define S5P_SDO_OSFC08_1			(0x02E0)
+#define S5P_SDO_OSFC09_1			(0x02E4)
+#define S5P_SDO_OSFC10_1			(0x02E8)
+#define S5P_SDO_OSFC11_1			(0x02EC)
+#define S5P_SDO_OSFC12_1			(0x02E0)
+#define S5P_SDO_OSFC13_1			(0x02F4)
+#define S5P_SDO_OSFC14_1			(0x02F8)
+#define S5P_SDO_OSFC15_1			(0x02FC)
+#define S5P_SDO_OSFC16_1			(0x0300)
+#define S5P_SDO_OSFC17_1			(0x0304)
+#define S5P_SDO_OSFC18_1			(0x0308)
+#define S5P_SDO_OSFC19_1			(0x030C)
+#define S5P_SDO_OSFC20_1			(0x0310)
+#define S5P_SDO_OSFC21_1			(0x0314)
+#define S5P_SDO_OSFC22_1			(0x0318)
+#define S5P_SDO_OSFC23_1			(0x031C)
+#define S5P_SDO_OSFC00_2			(0x0320)
+#define S5P_SDO_OSFC01_2			(0x0324)
+#define S5P_SDO_OSFC02_2			(0x0328)
+#define S5P_SDO_OSFC03_2			(0x032C)
+#define S5P_SDO_OSFC04_2			(0x0330)
+#define S5P_SDO_OSFC05_2			(0x0334)
+#define S5P_SDO_OSFC06_2			(0x0338)
+#define S5P_SDO_OSFC07_2			(0x033C)
+#define S5P_SDO_OSFC08_2			(0x0340)
+#define S5P_SDO_OSFC09_2			(0x0344)
+#define S5P_SDO_OSFC10_2			(0x0348)
+#define S5P_SDO_OSFC11_2			(0x034C)
+#define S5P_SDO_OSFC12_2			(0x0350)
+#define S5P_SDO_OSFC13_2			(0x0354)
+#define S5P_SDO_OSFC14_2			(0x0358)
+#define S5P_SDO_OSFC15_2			(0x035C)
+#define S5P_SDO_OSFC16_2			(0x0360)
+#define S5P_SDO_OSFC17_2			(0x0364)
+#define S5P_SDO_OSFC18_2			(0x0368)
+#define S5P_SDO_OSFC19_2			(0x036C)
+#define S5P_SDO_OSFC20_2			(0x0370)
+#define S5P_SDO_OSFC21_2			(0x0374)
+#define S5P_SDO_OSFC22_2			(0x0378)
+#define S5P_SDO_OSFC23_2			(0x037C)
+#define S5P_SDO_ARMCC				(0x03C0)
+#define S5P_SDO_ARMWSS525			(0x03C4)
+#define S5P_SDO_ARMWSS625			(0x03C8)
+#define S5P_SDO_ARMCGMS525			(0x03CC)
+#define S5P_SDO_ARMCGMS625			(0x03D4)
+#define S5P_SDO_VERSION				(0x03D8)
+#define S5P_SDO_CC				(0x0380)
+#define S5P_SDO_WSS525				(0x0384)
+#define S5P_SDO_WSS625				(0x0388)
+#define S5P_SDO_CGMS525				(0x038C)
+#define S5P_SDO_CGMS625				(0x0394)
+
+/*
+ * Bit definition part
+*/
+/* SDO Clock Control Register (SDO_CLKCON) */
+#define S5P_SDO_TVOUT_SW_RESET			(1 << 4)
+#define S5P_SDO_TVOUT_CLOCK_ON			(1)
+#define S5P_SDO_TVOUT_CLOCK_OFF			(0)
+
+/* SDO Video Standard Configuration Register (SDO_CONFIG) */
+#define S5P_SDO_DAC2_Y_G			(0 << 20)
+#define S5P_SDO_DAC2_PB_B			(1 << 20)
+#define S5P_SDO_DAC2_PR_R			(2 << 20)
+#define S5P_SDO_DAC1_Y_G			(0 << 18)
+#define S5P_SDO_DAC1_PB_B			(1 << 18)
+#define S5P_SDO_DAC1_PR_R			(2 << 18)
+#define S5P_SDO_DAC0_Y_G			(0 << 16)
+#define S5P_SDO_DAC0_PB_B			(1 << 16)
+#define S5P_SDO_DAC0_PR_R			(2 << 16)
+#define S5P_SDO_DAC2_CVBS			(0 << 12)
+#define S5P_SDO_DAC2_Y				(1 << 12)
+#define S5P_SDO_DAC2_C				(2 << 12)
+#define S5P_SDO_DAC1_CVBS			(0 << 10)
+#define S5P_SDO_DAC1_Y				(1 << 10)
+#define S5P_SDO_DAC1_C				(2 << 10)
+#define S5P_SDO_DAC0_CVBS			(0 << 8)
+#define S5P_SDO_DAC0_Y				(1 << 8)
+#define S5P_SDO_DAC0_C				(2 << 8)
+#define S5P_SDO_COMPOSITE			(0 << 6)
+#define S5P_SDO_COMPONENT			(1 << 6)
+#define S5P_SDO_RGB				(0 << 5)
+#define S5P_SDO_YPBPR				(1 << 5)
+#define S5P_SDO_INTERLACED			(0 << 4)
+#define S5P_SDO_PROGRESSIVE			(1 << 4)
+#define S5P_SDO_NTSC_M				(0)
+#define S5P_SDO_PAL_M				(1)
+#define S5P_SDO_PAL_BGHID			(2)
+#define S5P_SDO_PAL_N				(3)
+#define S5P_SDO_PAL_NC				(4)
+#define S5P_SDO_NTSC_443			(8)
+#define S5P_SDO_PAL_60				(9)
+
+/* SDO Video Scale Configuration Register (SDO_SCALE) */
+#define S5P_SDO_COMPONENT_LEVEL_SEL_0IRE	(0 << 3)
+#define S5P_SDO_COMPONENT_LEVEL_SEL_75IRE	(1 << 3)
+#define S5P_SDO_COMPONENT_VTOS_RATIO_10_4	(0 << 2)
+#define S5P_SDO_COMPONENT_VTOS_RATIO_7_3	(1 << 2)
+#define S5P_SDO_COMPOSITE_LEVEL_SEL_0IRE	(0 << 1)
+#define S5P_SDO_COMPOSITE_LEVEL_SEL_75IRE	(1 << 1)
+#define S5P_SDO_COMPOSITE_VTOS_RATIO_10_4	(0)
+#define S5P_SDO_COMPOSITE_VTOS_RATIO_7_3	(1)
+
+/* SDO Video sync Register  */
+#define S5P_SDO_COMPONENT_SYNC_ABSENT		(0)
+#define S5P_SDO_COMPONENT_SYNC_YG		(1)
+#define S5P_SDO_COMPONENT_SYNC_ALL		(3)
+
+/* SDO VBI Configuration Register (SDO_VBI) */
+#define S5P_SDO_CVBS_NO_WSS			(0 << 14)
+#define S5P_SDO_CVBS_WSS_INS			(1 << 14)
+#define S5P_SDO_CVBS_NO_CLOSED_CAPTION		(0 << 12)
+#define S5P_SDO_CVBS_21H_CLOSED_CAPTION		(1 << 12)
+#define S5P_SDO_CVBS_21H_284H_CLOSED_CAPTION	(2 << 12)
+#define S5P_SDO_CVBS_USE_OTHERS			(3 << 12)
+
+/* SDO Channel #0 Scale Control Register (SDO_SCALE_CH0) */
+#define S5P_SDO_SCALE_CONV_OFFSET(x)		(((x) & 0x3FF) << 16)
+#define S5P_SDO_SCALE_CONV_GAIN(x)		((x) & 0xFFF)
+
+/* SDO Video Delay Control Register (SDO_YCDELAY) */
+#define S5P_SDO_DELAY_YTOC(x)			(((x) & 0xF) << 16)
+#define S5P_SDO_ACTIVE_START_OFFSET(x)		(((x) & 0xFF) << 8)
+#define S5P_SDO_ACTIVE_END_OFFSET(x)		((x) & 0xFF)
+
+/* SDO SCH Phase Control Register (SDO_SCHLOCK) */
+#define S5P_SDO_COLOR_SC_PHASE_ADJ		(1)
+#define S5P_SDO_COLOR_SC_PHASE_NOADJ		(0)
+
+/* SDO DAC Configuration Register (SDO_DAC) */
+#define S5P_SDO_POWER_ON_DAC			(1 << 0)
+#define S5P_SDO_POWER_DOWN_DAC			(0 << 0)
+
+/* SDO Status Register (SDO_FINFO) */
+#define S5P_SDO_FIELD_MOD_1001(x)		(((x) & (0x3ff << 16)) >> 16)
+#define S5P_SDO_FIELD_ID_BOTTOM(x)		((x) & (1 << 1))
+#define S5P_SDO_FIELD_ID_BOTTOM_PI_INCATION(x)	(1)
+
+#define S5P_SDO_MV_AGC_103_ON			(1)
+
+/* SDO Color Compensation On/Off Control (SDO_CCCON) */
+#define S5P_SDO_COMPENSATION_BHS_ADJ_ON		(0 << 4)
+#define S5P_SDO_COMPENSATION_BHS_ADJ_OFF	(1 << 4)
+#define S5P_SDO_COMPENSATION_CVBS_COMP_ON	(0)
+#define S5P_SDO_COMPENSATION_CVBS_COMP_OFF	(1)
+
+/* SDO Brightness Control for Y (SDO_YSCALE) */
+#define S5P_SDO_BRIGHTNESS_GAIN(x)		(((x) & 0xFF) << 16)
+#define S5P_SDO_BRIGHTNESS_OFFSET(x)		((x) & 0xFF)
+
+/* SDO Hue/Saturation Control for CB (SDO_CBSCALE) */
+#define S5P_SDO_HS_CB_GAIN0(x)			(((x) & 0x1FF) << 16)
+#define S5P_SDO_HS_CB_GAIN1(x)			((x) & 0x1FF)
+
+/* SDO Hue/Saturation Control for CR (SDO_CRSCALE) */
+#define S5P_SDO_HS_CR_GAIN0(x)			(((x) & 0x1FF) << 16)
+#define S5P_SDO_HS_CR_GAIN1(x)			((x) & 0x1FF)
+
+/* SDO Hue/Saturation Control for CB/CR (SDO_CB_CR_OFFSET) */
+#define S5P_SDO_HS_CR_OFFSET(x)			(((x) & 0x3FF) << 16)
+#define S5P_SDO_HS_CB_OFFSET(x)			((x) & 0x3FF)
+
+#define S5P_SDO_MAX_RGB_CUBE(x)			(((x) & 0xFF) << 8)
+#define S5P_SDO_MIN_RGB_CUBE(x)			((x) & 0xFF)
+
+/* Color Compensation Control Register for CVBS Output (SDO_CVBS_CC_Y1) */
+#define S5P_SDO_Y_LOWER_MID_CVBS_CORN(x)	(((x) & 0x3FF) << 16)
+#define S5P_SDO_Y_BOTTOM_CVBS_CORN(x)		((x) & 0x3FF)
+
+/* Color Compensation Control Register for CVBS Output (SDO_CVBS_CC_Y2) */
+#define S5P_SDO_Y_TOP_CVBS_CORN(x)		(((x) & 0x3FF) << 16)
+#define S5P_SDO_Y_UPPER_MID_CVBS_CORN(x)	((x) & 0x3FF)
+
+/* Color Compensation Control Register for CVBS Output (SDO_CVBS_CC_C) */
+#define S5P_SDO_RADIUS_CVBS_CORN(x)		((x) & 0x1FF)
+
+/*
+ * SDO 525 Line Component Front/Back Porch Position
+ * Control Register (SDO_CSC_525_PORCH)
+ */
+#define S5P_SDO_COMPONENT_525_BP(x)		(((x) & 0x3FF) << 16)
+#define S5P_SDO_COMPONENT_525_FP(x)		((x) & 0x3FF)
+
+/*
+ * SDO 625 Line Component Front/Back Porch Position
+ * Control Resigter(SDO_CSC_625_PORCH
+ */
+#define S5P_SDO_COMPONENT_625_BP(x)		(((x) & 0x3FF) << 16)
+#define S5P_SDO_COMPONENT_625_FP(x)		((x) & 0x3FF)
+
+/* SDO Oversampling #0 Filter Coefficient (SDO_OSFC00_0) */
+#define S5P_SDO_OSF_COEF_ODD(x)			(((x) & 0xFFF) << 16)
+#define S5P_SDO_OSF_COEF_EVEN(x)		((x) & 0xFFF)
+
+/* SDO Channel Crosstalk Cancellation Coefficient for Ch. 0 (SDO_XTALK0) */
+#define S5P_SDO_XTALK_COEF02(x)			(((x) & 0xFF) << 16)
+#define S5P_SDO_XTALK_COEF01(x)			((x) & 0xFF)
+
+/* SDO Black Burst Control Register (SDO_BB_CTRL) */
+#define S5P_SDO_REF_BB_LEVEL_NTSC		(0x11A << 8)
+#define S5P_SDO_REF_BB_LEVEL_PAL		(0xFB << 8)
+#define S5P_SDO_SEL_BB_CJAN_CVBS0_BB1_BB2	(0 << 4)
+#define S5P_SDO_SEL_BB_CJAN_BB0_CVBS1_BB2	(1 << 4)
+#define S5P_SDO_SEL_BB_CJAN_BB0_BB1_CVBS2	(2 << 4)
+#define S5P_SDO_BB_MODE_ENABLE			(1)
+#define S5P_SDO_BB_MODE_DISABLE			(0)
+
+/* SDO Interrupt Request Register (SDO_IRQ) */
+#define S5P_SDO_VSYNC_IRQ_PEND			(1)
+#define S5P_SDO_VSYNC_NO_IRQ			(0)
+
+/* SDO Interrupt Request Masking Register (SDO_IRQMASK) */
+#define S5P_SDO_VSYNC_IRQ_ENABLE		(0)
+#define S5P_SDO_VSYNC_IRQ_DISABLE		(1)
+
+/* SDO Closed Caption Data Registers (SDO_ARMCC) */
+#define S5P_SDO_DISPLAY_CC_CAPTION(x)		(((x) & 0xFF) << 16)
+#define S5P_SDO_NON_DISPLAY_CC_CAPTION(x)	((x) & 0xFF)
+
+/* SDO WSS 525 Data Registers (SDO_ARMWSS525) */
+#define S5P_SDO_CRC_WSS525(x)				(((x) & 0x3F) << 14)
+#define S5P_SDO_WORD2_WSS525_COPY_PERMIT		(0 << 6)
+#define S5P_SDO_WORD2_WSS525_ONECOPY_PERMIT		(1 << 6)
+#define S5P_SDO_WORD2_WSS525_NOCOPY_PERMIT		(3 << 6)
+#define S5P_SDO_WORD2_WSS525_MV_PSP_OFF			(0 << 8)
+#define S5P_SDO_WORD2_WSS525_MV_PSP_ON_2LINE_BURST	(1 << 8)
+#define S5P_SDO_WORD2_WSS525_MV_PSP_ON_BURST_OFF	(2 << 8)
+#define S5P_SDO_WORD2_WSS525_MV_PSP_ON_4LINE_BURST	(3 << 8)
+#define S5P_SDO_WORD2_WSS525_ANALOG_OFF			(0 << 10)
+#define S5P_SDO_WORD2_WSS525_ANALOG_ON			(1 << 10)
+#define S5P_SDO_WORD1_WSS525_COPY_INFO			(0 << 2)
+#define S5P_SDO_WORD1_WSS525_DEFAULT			(0xF << 2)
+#define S5P_SDO_WORD0_WSS525_4_3_NORMAL			(0)
+#define S5P_SDO_WORD0_WSS525_16_9_ANAMORPIC		(1)
+#define S5P_SDO_WORD0_WSS525_4_3_LETTERBOX		(2)
+
+/* SDO WSS 625 Data Registers (SDO_ARMWSS625) */
+#define S5P_SDO_WSS625_SURROUND_SOUND_DISABLE		(0 << 11)
+#define S5P_SDO_WSS625_SURROUND_SOUND_ENABLE		(1 << 11)
+#define S5P_SDO_WSS625_NO_COPYRIGHT			(0 << 12)
+#define S5P_SDO_WSS625_COPYRIGHT			(1 << 12)
+#define S5P_SDO_WSS625_COPY_NOT_RESTRICTED		(0 << 13)
+#define S5P_SDO_WSS625_COPY_RESTRICTED			(1 << 13)
+#define S5P_SDO_WSS625_TELETEXT_NO_SUBTITLES		(0 << 8)
+#define S5P_SDO_WSS625_TELETEXT_SUBTITLES		(1 << 8)
+#define S5P_SDO_WSS625_NO_OPEN_SUBTITLES		(0 << 9)
+#define S5P_SDO_WSS625_INACT_OPEN_SUBTITLES		(1 << 9)
+#define S5P_SDO_WSS625_OUTACT_OPEN_SUBTITLES		(2 << 9)
+#define S5P_SDO_WSS625_CAMERA				(0 << 4)
+#define S5P_SDO_WSS625_FILM				(1 << 4)
+#define S5P_SDO_WSS625_NORMAL_PAL			(0 << 5)
+#define S5P_SDO_WSS625_MOTION_ADAPTIVE_COLORPLUS	(1 << 5)
+#define S5P_SDO_WSS625_HELPER_NO_SIG			(0 << 6)
+#define S5P_SDO_WSS625_HELPER_SIG			(1 << 6)
+#define S5P_SDO_WSS625_4_3_FULL_576			(0x8)
+#define S5P_SDO_WSS625_14_9_LETTERBOX_CENTER_504	(0x1)
+#define S5P_SDO_WSS625_14_9_LETTERBOX_TOP_504		(0x2)
+#define S5P_SDO_WSS625_16_9_LETTERBOX_CENTER_430	(0xb)
+#define S5P_SDO_WSS625_16_9_LETTERBOX_TOP_430		(0x4)
+#define S5P_SDO_WSS625_16_9_LETTERBOX_CENTER		(0xd)
+#define S5P_SDO_WSS625_14_9_FULL_CENTER_576		(0xe)
+#define S5P_SDO_WSS625_16_9_ANAMORPIC_576		(0x7)
+
+/* SDO CGMS-A 525 Data Registers (SDO_ARMCGMS525) */
+#define S5P_SDO_CRC_CGMS525(x)				(((x) & 0x3F) << 14)
+#define S5P_SDO_WORD2_CGMS525_COPY_PERMIT		(0 << 6)
+#define S5P_SDO_WORD2_CGMS525_ONECOPY_PERMIT		(1 << 6)
+#define S5P_SDO_WORD2_CGMS525_NOCOPY_PERMIT		(3 << 6)
+#define S5P_SDO_WORD2_CGMS525_MV_PSP_OFF		(0 << 8)
+#define S5P_SDO_WORD2_CGMS525_MV_PSP_ON_2LINE_BURST	(1 << 8)
+#define S5P_SDO_WORD2_CGMS525_MV_PSP_ON_BURST_OFF	(2 << 8)
+#define S5P_SDO_WORD2_CGMS525_MV_PSP_ON_4LINE_BURST	(3 << 8)
+#define S5P_SDO_WORD2_CGMS525_ANALOG_OFF		(0 << 10)
+#define S5P_SDO_WORD2_CGMS525_ANALOG_ON			(1 << 10)
+#define S5P_SDO_WORD1_CGMS525_COPY_INFO			(0 << 2)
+#define S5P_SDO_WORD1_CGMS525_DEFAULT			(0xF << 2)
+#define S5P_SDO_WORD0_CGMS525_4_3_NORMAL		(0)
+#define S5P_SDO_WORD0_CGMS525_16_9_ANAMORPIC		(1)
+#define S5P_SDO_WORD0_CGMS525_4_3_LETTERBOX		(2)
+
+/* SDO CGMS-A 625 Data Registers (SDO_ARMCGMS625) */
+#define S5P_SDO_CGMS625_SURROUND_SOUND_DISABLE		(0 << 11)
+#define S5P_SDO_CGMS625_SURROUND_SOUND_ENABLE		(1 << 11)
+#define S5P_SDO_CGMS625_NO_COPYRIGHT			(0 << 12)
+#define S5P_SDO_CGMS625_COPYRIGHT			(1 << 12)
+#define S5P_SDO_CGMS625_COPY_NOT_RESTRICTED		(0 << 13)
+#define S5P_SDO_CGMS625_COPY_RESTRICTED			(1 << 13)
+#define S5P_SDO_CGMS625_TELETEXT_NO_SUBTITLES		(0 << 8)
+#define S5P_SDO_CGMS625_TELETEXT_SUBTITLES		(1 << 8)
+#define S5P_SDO_CGMS625_NO_OPEN_SUBTITLES		(0 << 9)
+#define S5P_SDO_CGMS625_INACT_OPEN_SUBTITLES		(1 << 9)
+#define S5P_SDO_CGMS625_OUTACT_OPEN_SUBTITLES		(2 << 9)
+#define S5P_SDO_CGMS625_CAMERA				(0 << 4)
+#define S5P_SDO_CGMS625_FILM				(1 << 4)
+#define S5P_SDO_CGMS625_NORMAL_PAL			(0 << 5)
+#define S5P_SDO_CGMS625_MOTION_ADAPTIVE_COLORPLUS	(1 << 5)
+#define S5P_SDO_CGMS625_HELPER_NO_SIG			(0 << 6)
+#define S5P_SDO_CGMS625_HELPER_SIG			(1 << 6)
+#define S5P_SDO_CGMS625_4_3_FULL_576			(0x8)
+#define S5P_SDO_CGMS625_14_9_LETTERBOX_CENTER_504	(0x1)
+#define S5P_SDO_CGMS625_14_9_LETTERBOX_TOP_504		(0x2)
+#define S5P_SDO_CGMS625_16_9_LETTERBOX_CENTER_430	(0xb)
+#define S5P_SDO_CGMS625_16_9_LETTERBOX_TOP_430		(0x4)
+#define S5P_SDO_CGMS625_16_9_LETTERBOX_CENTER		(0xd)
+#define S5P_SDO_CGMS625_14_9_FULL_CENTER_576		(0xe)
+#define S5P_SDO_CGMS625_16_9_ANAMORPIC_576		(0x7)
+
+/* SDO Version Register (SDO_VERSION) */
+#define S5P_SDO_VERSION_NUMBER_MASK			(0xFFFFFFFF)
+
+#endif /* __ARCH_ARM_REGS_SDO_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-sysmmu.h b/arch/arm/mach-exynos/include/mach/regs-sysmmu.h
new file mode 100644
index 0000000..a0626fa
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/regs-sysmmu.h
@@ -0,0 +1,33 @@
+/* linux/arch/arm/mach-exynos/include/mach/regs-sysmmu.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS4 - System MMU register
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_SYSMMU_H
+#define __ASM_ARCH_REGS_SYSMMU_H __FILE__
+
+#define S5P_MMU_CTRL			0x000
+#define S5P_MMU_CFG			0x004
+#define S5P_MMU_STATUS			0x008
+#define S5P_MMU_FLUSH			0x00C
+#define S5P_PT_BASE_ADDR		0x014
+#define S5P_INT_STATUS			0x018
+#define S5P_INT_CLEAR			0x01C
+#define S5P_PAGE_FAULT_ADDR		0x024
+#define S5P_AW_FAULT_ADDR		0x028
+#define S5P_AR_FAULT_ADDR		0x02C
+#define S5P_DEFAULT_SLAVE_ADDR		0x030
+#define S5P_MMU_VERSION			0x034
+#define S5P_PB0_SADDR			0x04C
+#define S5P_PB0_EADDR			0x050
+#define S5P_PB1_SADDR			0x054
+#define S5P_PB1_EADDR			0x058
+
+#endif /* __ASM_ARCH_REGS_SYSMMU_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-tmu.h b/arch/arm/mach-exynos/include/mach/regs-tmu.h
new file mode 100644
index 0000000..8bfa3f5
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/regs-tmu.h
@@ -0,0 +1,164 @@
+/* linux/arch/arm/mach-exynos/include/mach/regs-tmu.h
+
+* Copyright (c) 2010 Samsung Electronics Co., Ltd.
+*      http://www.samsung.com/
+*
+* EXYNOS4 - Thermal Management support
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License version 2 as
+* published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_TMU_H
+#define __ASM_ARCH_REGS_TMU_H __FILE__
+
+enum tmu_state_t {
+	TMU_STATUS_NORMAL = 0,
+	TMU_STATUS_THROTTLED,
+	TMU_STATUS_WARNING,
+	TMU_STATUS_TRIPPED,
+	TMU_STATUS_INIT,
+	TMU_STATUS_TC,
+};
+
+#define FREQ_IN_PLL       24000000  /* 24MHZ in Hz */
+#define AUTO_REFRESH_PERIOD_TQ0    1950
+#define AUTO_REFRESH_PERIOD_NORMAL 3900
+
+/* TMU Common registers */
+#define EXYNOS4_TMU_TRIMINFO		(0x0000)
+#define TMU_TRIMINFO_MASK		(0xFF)
+
+#define EXYNOS4_TMU_CONTROL		(0x0020)
+#define TMUCORE_ENABLE      (1 << 0)
+
+#define EXYNOS4_TMU_STATUS		(0x0028)
+#define TMU_IDLE	(1 << 0)
+#define TMU_BUSY	(0 << 0)
+
+#define EXYNOS4_TMU_SAMPLING_INTERNAL	(0x002C)
+#define EXYNOS4_TMU_COUNTER_VALUE0	(0x0030)
+#define EXYNOS4_TMU_COUNTER_VALUE1	(0x0034)
+
+#define EXYNOS4_TMU_CURRENT_TEMP	(0x0040)
+/* TMU has temperature code within a temperature range of 25C to 125C */
+#define TEMP_MIN_CELCIUS	25
+#define TEMP_MAX_CELCIUS	125
+#define TMU_DC_VALUE		25
+
+#define EXYNOS4_TMU_INTEN		(0x0070)
+#define EXYNOS4_TMU_INTSTAT		(0x0074)
+#define EXYNOS4_TMU_INTCLEAR		(0x0078)
+
+/*
+ * The below registers and definition is used
+ * in only EXYNOS4210
+ *
+*/
+/* Below 3line is used to exynos4210 evt0 without right e-fusing */
+#define EFUSE_MIN_VALUE 60
+#define EFUSE_AVG_VALUE 80
+#define EFUSE_MAX_VALUE 100
+
+/* To get rightly current temperature, EXYNOS4_TMU_CONTROL setting value */
+#define VREF_SLOPE     0x07000F02
+
+#define EXYNOS4210_TMU_THRESHOLD_TEMP	(0x0044)
+#define EXYNOS4210_TMU_TRIG_LEVEL0	(0x0050)
+#define EXYNOS4210_TMU_TRIG_LEVEL1	(0x0054)
+#define EXYNOS4210_TMU_TRIG_LEVEL2	(0x0058)
+#define EXYNOS4210_TMU_TRIG_LEVEL3	(0x005C)
+#define TRIGGER_LEV_MAX   (0xFF)
+
+#define EXYNOS4210_TMU_PAST_TMEP0	(0x0060)
+#define EXYNOS4210_TMU_PAST_TMEP1		(0x0064)
+#define EXYNOS4210_TMU_PAST_TMEP2		(0x0068)
+#define EXYNOS4210_TMU_PAST_TMEP3		(0x006C)
+
+/* bit definition at EXYNOS4_TMU_INTEN reg of exynos4210 */
+#define INTEN0			(1 << 0)
+#define INTEN1			(1 << 4)
+#define INTEN2			(1 << 8)
+#define INTEN3			(1 << 12)
+
+/* bit definition at EXYNOS4_TMU_INTSTAT reg of exynos4210 */
+#define TMU_INTSTAT0		(1 << 0)
+#define TMU_INTSTAT1		(1 << 4)
+#define TMU_INTSTAT2		(1 << 8)
+#define TMU_INTSTAT3		(1 << 12)
+
+
+/* bit definition at EXYNOS4_TMU_INTCLEAR regof exynos4210 */
+#define INTCLEAR0		(1 << 0)
+#define INTCLEAR1		(1 << 4)
+#define INTCLEAR2		(1 << 8)
+#define INTCLEAR3		(1 << 12)
+
+#ifdef CONFIG_CPU_EXYNOS4210
+#define INTCLEARALL	(INTCLEAR0 | INTCLEAR1 | INTCLEAR2 | INTCLEAR3)
+#else
+#define INTCLEARALL	(INTCLEAR_RISE0 | INTCLEAR_RISE1 | INTCLEAR_RISE2 \
+			| INTCLEAR_FALL0 | INTCLEAR_FALL1 | INTCLEAR_FALL2)
+#endif
+
+/*
+ * The below registers and definition is added or changed
+ * in EXYNOS4x12
+ *
+*/
+#define EXYNOS4x12_TMU_TRIMINFO_CONROL	(0x0014)
+#define TMU_RELOAD			(1 << 0)
+#define TMU_ACTIME			(1 << 0)
+
+/* Newly added bit definition at EXYNOS4_TMU_CONTROL register,  */
+#define THERM_TRIP_ENABLE	(1 << 12)
+#define THERM_TRIP_MODE_000	(0 << 13)
+#define THERM_TRIP_MODE_100	(4 << 13)
+#define THERM_TRIP_MODE_101	(5 << 13)
+#define THERM_TRIP_MODE_110	(6 << 13)
+#define THERM_TRIP_MODE_111	(7 << 13)
+
+#define EXYNOS4x12_TMU_TRESHOLD_TEMP_RISE	(0x0050)
+#define THRES_LEVEL_RISE0_SHIFT		(1 << 0)
+#define THRES_LEVEL_RISE1_SHIFT		(1 << 8)
+#define THRES_LEVEL_RISE2_SHIFT		(1 << 16)
+#define THRES_LEVEL_RISE3_SHIFT		(1 << 24)
+
+#define EXYNOS4x12_TMU_TRESHOLD_TEMP_FALL	(0x0054)
+#define THRES_LEVEL_FALL0_SHIFT		(1 << 0)
+#define THRES_LEVEL_FALL1_SHIFT		(1 << 8)
+#define THRES_LEVEL_FALL2_SHIFT		(1 << 16)
+
+#define EXYNOS4x12_TMU_PAST_TMEP3_0	(0x0060)
+#define EXYNOS4x12_TMU_PAST_TMEP7_4	(0x0064)
+#define EXYNOS4x12_TMU_PAST_TMEP11_8	(0x0068)
+#define EXYNOS4x12_TMU_PAST_TMEP15_12	(0x006C)
+
+/* Newly changed bit definition at EXYNOS4_TMU_INTEN register,  */
+#define INTEN_RISE0			(1 << 0)
+#define INTEN_RISE1			(1 << 4)
+#define INTEN_RISE2			(1 << 8)
+#define INTEN_FALL0			(1 << 16)
+#define INTEN_FALL1			(1 << 20)
+#define INTEN_FALL2			(1 << 24)
+
+/* Newly changed bit definition at EXYNOS4_TMU_INSTAT */
+#define INTSTAT_RISE0		(1 << 0)
+#define INTSTAT_RISE1		(1 << 4)
+#define INTSTAT_RISE2		(1 << 8)
+#define INTSTAT_FALL0		(1 << 16)
+#define INTSTAT_FALL1		(1 << 20)
+#define INTSTAT_FALL2		(1 << 24)
+
+/* Newly changed bit definition at EXYNOS4_TMU_CLEAR */
+#define INTCLEAR_RISE0		(1 << 0)
+#define INTCLEAR_RISE1		(1 << 4)
+#define INTCLEAR_RISE2		(1 << 8)
+#define INTCLEAR_FALL0		(1 << 12)
+#define INTCLEAR_FALL1		(1 << 16)
+#define INTCLEAR_FALL2		(1 << 20)
+
+#define EXYNOS4x12_TMU_EMUL_CON	(0x0080)
+
+#endif /* ___ASM_ARCH_REGS_TMU_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-tsi.h b/arch/arm/mach-exynos/include/mach/regs-tsi.h
new file mode 100644
index 0000000..d7d03ca
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/regs-tsi.h
@@ -0,0 +1,163 @@
+/* arch/arm/plat-s3c/include/plat/regs-tsi.h
+ *
+ * Copyright (c) 2004 Samsung
+ *
+ * This program is free software; yosu can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S5PC110 TSI registers
+*/
+#ifndef __ASM_ARCH_REGS_TSI_H
+#define __ASM_ARCH_REGS_TSI_H "regs-tsi.h"
+
+#define S3C_TSIREG(x)			(x)
+
+#define	S3C_TS_CLKCON			S3C_TSIREG(0x00)
+#define	S3C_TS_CON			S3C_TSIREG(0x04)
+#define	S3C_TS_SYNC			S3C_TSIREG(0x08)
+#define	S3C_TS_CNT			S3C_TSIREG(0x0C)
+#define	S3C_TS_BASE			S3C_TSIREG(0x10)
+#define	S3C_TS_SIZE			S3C_TSIREG(0x14)
+#define	S3C_TS_CADDR			S3C_TSIREG(0x18)
+#define	S3C_TS_INTMASK			S3C_TSIREG(0x1C)
+#define	S3C_TS_INT			S3C_TSIREG(0x20)
+#define	S3C_TS_PID0			S3C_TSIREG(0x24)
+#define	S3C_TS_PID1			S3C_TSIREG(0x28)
+#define	S3C_TS_PID2			S3C_TSIREG(0x2C)
+#define	S3C_TS_PID3			S3C_TSIREG(0x30)
+#define	S3C_TS_PID4			S3C_TSIREG(0x34)
+#define	S3C_TS_PID5			S3C_TSIREG(0x38)
+#define	S3C_TS_PID6			S3C_TSIREG(0x3C)
+#define	S3C_TS_PID7			S3C_TSIREG(0x40)
+#define	S3C_TS_PID8			S3C_TSIREG(0x44)
+#define	S3C_TS_PID9			S3C_TSIREG(0x48)
+#define	S3C_TS_PID10			S3C_TSIREG(0x4C)
+#define	S3C_TS_PID11			S3C_TSIREG(0x50)
+#define	S3C_TS_PID12			S3C_TSIREG(0x54)
+#define	S3C_TS_PID13			S3C_TSIREG(0x58)
+#define	S3C_TS_PID14			S3C_TSIREG(0x5C)
+#define	S3C_TS_PID15			S3C_TSIREG(0x60)
+#define	S3C_TS_PID16			S3C_TSIREG(0x64)
+#define	S3C_TS_PID17			S3C_TSIREG(0x68)
+#define	S3C_TS_PID18			S3C_TSIREG(0x6C)
+#define	S3C_TS_PID19			S3C_TSIREG(0x70)
+#define	S3C_TS_PID20			S3C_TSIREG(0x74)
+#define	S3C_TS_PID21			S3C_TSIREG(0x78)
+#define	S3C_TS_PID22			S3C_TSIREG(0x7C)
+#define	S3C_TS_PID23			S3C_TSIREG(0x80)
+#define	S3C_TS_PID24			S3C_TSIREG(0x84)
+#define	S3C_TS_PID25			S3C_TSIREG(0x88)
+#define	S3C_TS_PID26			S3C_TSIREG(0x8C)
+#define	S3C_TS_PID27			S3C_TSIREG(0x90)
+#define	S3C_TS_PID28			S3C_TSIREG(0x94)
+#define	S3C_TS_PID29			S3C_TSIREG(0x98)
+#define	S3C_TS_PID30			S3C_TSIREG(0x9C)
+#define	S3C_TS_PID31			S3C_TSIREG(0xA0)
+#define	S3C_TS_BYTE_SWAP		S3C_TSIREG(0xBC)
+
+#define TS_TIMEOUT_CNT_MAX		(0x00FFFFFF)
+#define TS_NUM_PKT			(4)
+#define TS_PKT_SIZE			47
+#define TS_PKT_BUF_SIZE			(TS_PKT_SIZE*TS_NUM_PKT)
+#define TSI_CLK_START			1
+#define TSI_CLK_STOP			0
+
+
+
+
+/*bit definitions*/
+/*CLKCON*/
+
+#define S3C_TSI_ON			(0x1<<0)
+#define S3C_TSI_ON_MASK			(0x1<<0)
+#define S3C_TSI_BLK_READY		(0x1<<1)
+
+/*TS_CON*/
+#define S3C_TSI_SWRESET			(0x1 << 31)
+#define S3C_TSI_SWRESET_MASK		(0x1 << 31)
+#define S3C_TSI_CLKFILTER_ON		(0x1 << 30)
+#define S3C_TSI_CLKFILTER_MASK		(0x1 << 30)
+#define S3C_TSI_CLKFILTER_SHIFT		30
+#define S3C_TSI_BURST_LEN_0		(0x0 << 28)
+#define S3C_TSI_BURST_LEN_4		(0x1 << 28)
+#define S3C_TSI_BURST_LEN_8		(0x2 << 28)
+#define S3C_TSI_BURST_LEN_MASK		(0x3 << 28)
+#define S3C_TSI_BURST_LEN_SHIFT		(28)
+
+#define S3C_TSI_OUT_BUF_FULL_INT_ENA	(0x1 << 27)
+#define S3C_TSI_OUT_BUF_FULL_INT_MASK	(0x1 << 27)
+#define S3C_TSI_INT_FIFO_FULL_INT_ENA   (0x1 << 26)
+#define S3C_TSI_INT_FIFO_FULL_INT_ENA_MASK   (0x1 << 26)
+
+#define S3C_TSI_SYNC_MISMATCH_INT_SKIP	(0x2 << 24)
+#define S3C_TSI_SYNC_MISMATCH_INT_STOP	(0x3 << 24)
+#define S3C_TSI_SYNC_MISMATCH_INT_MASK	(0x3 << 24)
+
+#define S3C_TSI_PSUF_INT_SKIP		(0x2 << 22)
+#define S3C_TSI_PSUF_INT_STOP		(0x3 << 22)
+#define S3C_TSI_PSUF_INT_MASK		(0x3 << 22)
+
+#define S3C_TSI_PSOF_INT_SKIP		(0x2 << 20)
+#define S3C_TSI_PSOF_INT_STOP		(0x3 << 20)
+#define S3C_TSI_PSOF_INT_MASK		(0x3 << 20)
+
+#define S3C_TSI_TS_CLK_TIME_OUT_INT	(0x1 << 19)
+#define S3C_TSI_TS_CLK_TIME_OUT_INT_MASK (0x1 << 19)
+
+#define S3C_TSI_TS_ERROR_SKIP_SIZE_INT		(4<<16)
+#define S3C_TSI_TS_ERROR_STOP_SIZE_INT		(5<<16)
+#define S3C_TSI_TS_ERROR_SKIP_PKT_INT		(6<<16)
+#define S3C_TSI_TS_ERROR_STOP_PKT_INT		(7<<16)
+#define S3C_TSI_TS_ERROR_MASK			(7<<16)
+#define S3C_TSI_PAD_PATTERN_SHIFT		(8)
+#define S3C_TSI_PID_FILTER_ENA			(1 << 7)
+#define S3C_TSI_PID_FILTER_MASK			(1 << 7)
+#define S3C_TSI_PID_FILTER_SHIFT		(7)
+#define S3C_TSI_ERROR_ACTIVE_LOW		(1<<6)
+#define S3C_TSI_ERROR_ACTIVE_HIGH		(0<<6)
+#define S3C_TSI_ERROR_ACTIVE_MASK		(1<<6)
+
+#define S3C_TSI_DATA_BYTE_ORDER_M2L		(0 << 5)
+#define S3C_TSI_DATA_BYTE_ORDER_L2M		(1 << 5)
+#define S3C_TSI_DATA_BYTE_ORDER_MASK		(1 << 5)
+#define S3C_TSI_DATA_BYTE_ORDER_SHIFT		(5)
+#define S3C_TSI_TS_VALID_ACTIVE_HIGH		(0<<4)
+#define S3C_TSI_TS_VALID_ACTIVE_LOW		(1<<4)
+#define S3C_TSI_TS_VALID_ACTIVE_MASK		(1<<4)
+
+#define S3C_TSI_SYNC_ACTIVE_HIGH		(0 << 3)
+#define S3C_TSI_SYNC_ACTIVE_LOW			(1 << 3)
+#define S3C_TSI_SYNC_ACTIVE_MASK		(1 << 3)
+
+#define S3C_TSI_CLK_INVERT_HIGH			(0 << 2)
+#define S3C_TSI_CLK_INVERT_LOW			(1 << 2)
+#define S3C_TSI_CLK_INVERT_MASK			(1 << 2)
+
+/*TS_SYNC*/
+#define S3C_TSI_SYNC_DET_MODE_TS_SYNC8			(0<<0)
+#define S3C_TSI_SYNC_DET_MODE_TS_SYNC1			(1<<0)
+#define S3C_TSI_SYNC_DET_MODE_TS_SYNC_BYTE		(2<<0)
+#define S3C_TSI_SYNC_DET_MODE_TS_SYNC_MASK		(3<<0)
+
+
+/* TS_INT_MASK */
+#define S3C_TSI_DMA_COMPLETE_ENA			(1 << 7)
+#define S3C_TSI_OUTPUT_BUF_FULL_ENA			(1 << 6)
+#define S3C_TSI_INT_FIFO_FULL_ENA			(1 << 5)
+#define S3C_TSI_SYNC_MISMATCH_ENA			(1 << 4)
+#define S3C_TSI_PKT_SIZE_UNDERFLOW_ENA			(1 << 3)
+#define S3C_TSI_PKT_SIZE_OVERFLOW_ENA			(1 << 2)
+#define S3C_TSI_TS_CLK_ENA				(1 << 1)
+#define S3C_TSI_TS_ERROR_ENA				(1 << 0)
+
+/* TS_INT_FLAG */
+#define S3C_TSI_DMA_COMPLETE				(1<<7)
+#define S3C_TSI_OUT_BUF_FULL				(1<<6)
+#define S3C_TSI_INT_FIFO_FULL				(1<<5)
+#define S3C_TSI_SYNC_MISMATCH				(1<<4)
+#define S3C_TSI_PKT_UNDERFLOW				(1<<3)
+#define S3C_TSI_PKT_OVERFLOW				(1<<2)
+#define S3C_TSI_PKT_CLK					(1<<1)
+#define S3C_TSI_ERROR					(1<<0)
+#endif /* __ASM_ARCH_REGS_TSI_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-usb-host.h b/arch/arm/mach-exynos/include/mach/regs-usb-host.h
new file mode 100644
index 0000000..95132e6
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/regs-usb-host.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics Co.Ltd
+ * Author: Yulgon Kim <Yulgon.kim@samsung.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __ASM_ARCH_MACH_REGS_USB_HOST_H
+#define __ASM_ARCH_MACH_REGS_USB_HOST_H
+
+#define INSNREG00(base)				(base + 0x90)
+#define ENA_DMA_INCR				(0xF << 22)
+#define ENA_INCR16				(1 << 25)
+#define ENA_INCR8				(1 << 24)
+#define ENA_INCR4				(1 << 23)
+#define ENA_INCRX_ALIGN				(1 << 22)
+#define APP_START_CLK				(1 << 21)
+#define OHCI_SUSP_LGCY				(1 << 20)
+#define MICROFRAME_BASE_VALUE_MASK		(0x1FFF << 1)
+#define MICROFRAME_BASE_VALUE_SHIFT		(1)
+#define ENA_MICROFRAME_LENGTH_VALUE		(1 << 0)
+
+#define INSNREG01(base, offset)			(base + 0x94)
+#define PACKET_BUFFER_THRESHOLDS_OUT_MASK	(0xFFFF << 16)
+#define PACKET_BUFFER_THRESHOLDS_OUT_SHIFT	(16)
+#define PACKET_BUFFER_THRESHOLDS_IN_MASK	(0xFFFF << 0)
+#define PACKET_BUFFER_THRESHOLDS_IN_SHIFT	(0)
+
+#define INSNREG02(base, offset)			(base + 0x98)
+#define PACKET_BUFFER_DEPTH_MASK		(0xFFFFFFFF << 0)
+
+#define INSNREG03(base, offset)			(base + 0x9C)
+#define TX_TURNAROUD_DELAY_ADD_MASK		(0x7 << 10)
+#define TX_TURNAROUD_DELAY_ADD_SHIFT		(10)
+#define PERIODIC_FRAME_LIST_FETCH		(1 << 9)
+#define TIME_AVAILABLE_OFFSET_MASK		(0xFF << 1)
+#define TIME_AVAILABLE_OFFSET_SHIFT		(1)
+#define BREAK_MEMORY_TRANSFER			(1 << 0)
+
+#define INSNREG04(base, offset)			(base + 0xA0)
+
+#define INSNREG05(base, offset)			(base + 0xA4)
+
+#define INSNREG06(base, offset)			(base + 0xA8)
+#define AHB_ERROR_CAPTURED			(1 << 31)
+#define HBURST_VALUE_OF_CONTROL_MASK		(0x7 << 9)
+#define HBURST_VALUE_OF_CONTROL_SHIFT		(9)
+#define NUMBER_OF_BEATS_EXPECTED_MASK		(0x1F << 4)
+#define NUMBER_OF_BEATS_EXPECTED_SHIFT		(4)
+#define NUMBER_OF_SUCCESSFULLY_MASK		(0xF << 0)
+#define NUMBER_OF_SUCCESSFULLY_SHIFT		(0)
+
+#define INSNREG07(base, offset)			(base + 0xAC)
+#define AHB_MASTER_ERROR_ADDRESS_MASK		(0xFFFFFFFF << 0)
+#define AHB_MASTER_ERROR_ADDRESS_SHIFT		(0)
+
+#endif /* __ASM_ARCH_MACH_REGS_USB_HOST_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-usb-phy-4210.h b/arch/arm/mach-exynos/include/mach/regs-usb-phy-4210.h
new file mode 100644
index 0000000..eccf619
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/regs-usb-phy-4210.h
@@ -0,0 +1,42 @@
+/* linux/arch/arm/mach-exynos/include/mach/regs-usb-phy-4210.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS4 - 4210 USB PHY definition
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_USB_PHY_4210_H
+#define __ASM_ARCH_REGS_USB_PHY_4210_H __FILE__
+
+/* EXYNOS4210 HSIC PHYPWR */
+#define EXYNOS4210_HSIC1_NORMAL_MASK		(0x3 << 11)
+#define EXYNOS4210_HSIC1_SLEEP			(1 << 12)
+#define EXYNOS4210_HSIC1_FORCE_SUSPEND		(1 << 11)
+#define EXYNOS4210_HSIC0_NORMAL_MASK		(0x3 << 9)
+#define EXYNOS4210_HSIC0_SLEEP			(1 << 10)
+#define EXYNOS4210_HSIC0_FORCE_SUSPEND		(1 << 9)
+
+/* EXYNOS4210 PHYCLK */
+#define EXYNOS4210_PHY0_ID_PULLUP		(1 << 2)
+#define EXYNOS4210_CLKSEL_MASK			(0x3 << 0)
+#define EXYNOS4210_CLKSEL_48M			(0x0 << 0)
+#define EXYNOS4210_CLKSEL_12M			(0x2 << 0)
+#define EXYNOS4210_CLKSEL_24M			(0x3 << 0)
+
+/* EXYNOS4210 PHYCLK */
+#define EXYNOS4210_HOST_LINK_PORT_SWRST_MASK	(0xf << 6)
+#define EXYNOS4210_HOST_LINK_PORT2_SWRST	(1 << 9)
+#define EXYNOS4210_HOST_LINK_PORT1_SWRST	(1 << 8)
+#define EXYNOS4210_HOST_LINK_PORT0_SWRST	(1 << 7)
+#define EXYNOS4210_HOST_LINK_ALL_SWRST		(1 << 6)
+#define EXYNOS4210_PHY1_SWRST_MASK		(0x7 << 3)
+#define EXYNOS4210_PHY1_HSIC_SWRST		(1 << 5)
+#define EXYNOS4210_PHY1_STD_SWRST		(1 << 4)
+#define EXYNOS4210_PHY1_ALL_SWRST		(1 << 3)
+
+#endif /* __ASM_ARCH_REGS_USB_PHY_4210_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-usb-phy-4212.h b/arch/arm/mach-exynos/include/mach/regs-usb-phy-4212.h
new file mode 100644
index 0000000..e56eb16
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/regs-usb-phy-4212.h
@@ -0,0 +1,49 @@
+/* linux/arch/arm/mach-exynos/include/mach/regs-usb-phy-4212.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS4 - 4212 USB PHY definition
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_USB_PHY_4212_H
+#define __ASM_ARCH_REGS_USB_PHY_4212_H __FILE__
+
+/* EXYNOS4212 HSIC PHYPWR */
+#define EXYNOS4212_HSIC1_NORMAL_MASK		(0x7 << 12)
+#define EXYNOS4212_HSIC1_SLEEP			(1 << 14)
+#define EXYNOS4212_HSIC1_ANALOG_POWERDOWN	(1 << 13)
+#define EXYNOS4212_HSIC1_FORCE_SUSPEND		(1 << 12)
+#define EXYNOS4212_HSIC0_NORMAL_MASK		(0x7 << 9)
+#define EXYNOS4212_HSIC0_SLEEP			(1 << 11)
+#define EXYNOS4212_HSIC0_ANALOG_POWERDOWN	(1 << 10)
+#define EXYNOS4212_HSIC0_FORCE_SUSPEND		(1 << 9)
+
+/* EXYNOS4212 PHYCLK */
+#define EXYNOS4212_PHY0_ID_PULLUP		(1 << 3)
+#define EXYNOS4212_CLKSEL_MASK			(0x7 << 0)
+#define EXYNOS4212_CLKSEL_SHIFT			(0)
+#define EXYNOS4212_CLKSEL_9600K			(0x0 << 0)
+#define EXYNOS4212_CLKSEL_10M			(0x1 << 0)
+#define EXYNOS4212_CLKSEL_12M			(0x2 << 0)
+#define EXYNOS4212_CLKSEL_19200K		(0x3 << 0)
+#define EXYNOS4212_CLKSEL_20M			(0x4 << 0)
+#define EXYNOS4212_CLKSEL_24M			(0x5 << 0)
+
+/* EXYNOS4212 PHYCLK */
+#define EXYNOS4212_HOST_LINK_PORT_SWRST_MASK	(0xf << 7)
+#define EXYNOS4212_HOST_LINK_PORT2_SWRST	(1 << 10)
+#define EXYNOS4212_HOST_LINK_PORT1_SWRST	(1 << 9)
+#define EXYNOS4212_HOST_LINK_PORT0_SWRST	(1 << 8)
+#define EXYNOS4212_HOST_LINK_ALL_SWRST		(1 << 7)
+#define EXYNOS4212_PHY1_SWRST_MASK		(0xf << 3)
+#define EXYNOS4212_PHY1_HSIC1_SWRST		(1 << 6)
+#define EXYNOS4212_PHY1_HSIC0_SWRST		(1 << 5)
+#define EXYNOS4212_PHY1_SWRST			(1 << 4)
+#define EXYNOS4212_HOST_PHY_SWRST		(1 << 3)
+
+#endif /* __ASM_ARCH_REGS_USB_PHY_4212_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
new file mode 100644
index 0000000..39a475f
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
@@ -0,0 +1,118 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics Co.Ltd
+ * Author: Yulgon Kim <yulgon.kim@samsung.com>
+ * Author: Joonyoung Shim <jy0922.shim@samsung.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __ASM_ARCH_REGS_USB_PHY_H
+#define __ASM_ARCH_REGS_USB_PHY_H
+
+#define EXYNOS4_HSOTG_PHYREG(x)			((x) + S3C_VA_USB_HSPHY)
+
+#include "regs-usb-phy-4210.h"
+#include "regs-usb-phy-4212.h"
+
+/* For Exynos4 */
+#define EXYNOS4_PHYPWR				EXYNOS4_HSOTG_PHYREG(0x00)
+
+#define PHY1_STD_SLEEP				(1 << 8)
+#define PHY1_STD_ANALOG_POWERDOWN		(1 << 7)
+#define PHY1_STD_FORCE_SUSPEND			(1 << 6)
+#define PHY1_STD_NORMAL_MASK			(0x7 << 6)
+
+#define PHY0_SLEEP				(1 << 5)
+#define PHY0_OTG_DISABLE			(1 << 4)
+#define PHY0_ANALOG_POWERDOWN			(1 << 3)
+#define PHY0_FORCE_SUSPEND			(1 << 0)
+#define PHY0_NORMAL_MASK			(0x29 << 0)
+#define PHY0_PHYTUNE				EXYNOS4_HSOTG_PHYREG(0x24)
+#define PHY1_PHYTUNE				EXYNOS4_HSOTG_PHYREG(0x20)
+
+#define EXYNOS4_PHYCLK				EXYNOS4_HSOTG_PHYREG(0x04)
+#define PHY1_COMMON_ON_N			(1 << 7)
+#define PHY0_COMMON_ON_N			(1 << 4)
+
+#define CLKSEL_SHIFT				(0)
+
+#define EXYNOS4_RSTCON				EXYNOS4_HSOTG_PHYREG(0x08)
+
+#define PHY0_SWRST_MASK				(0x7 << 0)
+#define PHY0_PHYLINK_SWRST			(1 << 2)
+#define PHY0_HLINK_SWRST			(1 << 1)
+#define PHY0_SWRST				(1 << 0)
+
+#define EXYNOS4_PHY1CON				EXYNOS4_HSOTG_PHYREG(0x34)
+#define FPENABLEN				(1 << 0)
+
+/* For Exynos5 */
+#define EXYNOS5_PHY_HOST_CTRL0			EXYNOS4_HSOTG_PHYREG(0x00)
+#define HOST_CTRL0_PHYSWRSTALL			(0x1 << 31)
+#define HOST_CTRL0_REFCLKSEL(val)		(val << 19)
+#define EXYNOS5_CLKSEL_50M			(0x7)
+#define EXYNOS5_CLKSEL_24M			(0x5)
+#define EXYNOS5_CLKSEL_20M			(0x4)
+#define EXYNOS5_CLKSEL_19200K			(0x3)
+#define EXYNOS5_CLKSEL_12M			(0x2)
+#define EXYNOS5_CLKSEL_10M			(0x1)
+#define EXYNOS5_CLKSEL_9600K			(0x0)
+#define HOST_CTRL0_CLKSEL_SHIFT			(16)
+#define HOST_CTRL0_FSEL_MASK			(0x7 << 16)
+
+#define HOST_CTRL0_COMMONON_N			(0x1 << 9)
+#define HOST_CTRL0_SIDDQ			(0x1 << 6)
+#define HOST_CTRL0_FORCESLEEP			(0x1 << 5)
+#define HOST_CTRL0_FORCESUSPEND			(0x1 << 4)
+#define HOST_CTRL0_WORDINTERFACE		(0x1 << 3)
+#define HOST_CTRL0_UTMISWRST			(0x1 << 2)
+#define HOST_CTRL0_LINKSWRST			(0x1 << 1)
+#define HOST_CTRL0_PHYSWRST			(0x1 << 0)
+
+#define EXYNOS5_PHY_HOST_TUNE0			EXYNOS4_HSOTG_PHYREG(0x04)
+#define EXYNOS5_PHY_HOST_TEST0			EXYNOS4_HSOTG_PHYREG(0x08)
+
+#define EXYNOS5_PHY_HSIC_CTRL1			EXYNOS4_HSOTG_PHYREG(0x10)
+#define EXYNOS5_PHY_HSIC_CTRL2			EXYNOS4_HSOTG_PHYREG(0x20)
+#define HSIC_CTRL_REFCLKSEL(val)		((val&0x3) << 23)
+#define HSIC_CTRL_REFCLKDIV(val)		((val&0x7f) << 16)
+#define HSIC_CTRL_SIDDQ				(0x1 << 6)
+#define HSIC_CTRL_FORCESLEEP			(0x1 << 5)
+#define HSIC_CTRL_FORCESUSPEND			(0x1 << 4)
+#define HSIC_CTRL_WORDINTERFACE			(0x1 << 3)
+#define HSIC_CTRL_UTMISWRST			(0x1 << 2)
+#define HSIC_CTRL_PHYSWRST			(0x1 << 0)
+
+#define EXYNOS5_PHY_HOST_EHCICTRL		EXYNOS4_HSOTG_PHYREG(0x30)
+#define EHCICTRL_ENAINCRXALIGN			(0x1 << 29)
+#define EHCICTRL_ENAINCR4			(0x1 << 28)
+#define EHCICTRL_ENAINCR8			(0x1 << 27)
+#define EHCICTRL_ENAINCR16			(0x1 << 26)
+
+#define EXYNOS5_PHY_HOST_OHCICTRL		EXYNOS4_HSOTG_PHYREG(0x34)
+#define OHCICTRL_SUSPLGCY			(0x1 << 3)
+#define OHCICTRL_APPSTARTCLK			(0x1 << 2)
+#define OHCICTRL_CNTSEL				(0x1 << 1)
+#define OHCICTRL_CLKCKTRST			(0x1 << 0)
+
+#define EXYNOS5_PHY_OTG_SYS			EXYNOS4_HSOTG_PHYREG(0x38)
+#define OTG_SYS_PHYLINK_SW_RESET		(0x1 << 14)
+#define OTG_SYS_LINK_SW_RST_UOTG		(0x1 << 13)
+#define OTG_SYS_PHY0_SW_RST			(0x1 << 12)
+#define OTG_SYS_REF_CLK_SEL(val)		((val&0x3) << 9)
+#define OTG_SYS_REF_CLK_SEL_MASK		(0x3 << 9)
+#define OTG_SYS_IP_PULLUP_UOTG			(0x1 << 8)
+#define OTG_SYS_COMMON_ON			(0x1 << 7)
+#define OTG_SYS_CLKSEL_SHIFT			(4)
+#define OTG_SYS_CTRL0_FSEL_MASK			(0x7 << 4)
+#define OTG_SYS_FORCE_SLEEP			(0x1 <<3)
+#define OTG_SYS_OTGDISABLE			(0x1 <<2)
+#define OTG_SYS_SIDDQ_UOTG			(0x1 <<1)
+#define OTG_SYS_FORCE_SUSPEND			(0x1 <<0)
+
+extern int exynos_check_usb_op(void);
+
+#endif /* __ASM_ARCH_REGS_USB_PHY_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-vp.h b/arch/arm/mach-exynos/include/mach/regs-vp.h
new file mode 100644
index 0000000..68a2b0d
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/regs-vp.h
@@ -0,0 +1,293 @@
+/* linux/arch/arm/mach-exynos/include/mach/regs-vp.h
+ *
+ * Copyright (c) 2009 Samsung Electronics
+ *		http://www.samsung.com/
+ *
+ * Video processor register header file for Samsung TVOUT driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_REGS_VP_H
+#define __ARCH_ARM_REGS_VP_H
+
+/*
+ * Register part
+ */
+#define S5P_VP_ENABLE				(0x0000)
+#define S5P_VP_SRESET				(0x0004)
+#define S5P_VP_SHADOW_UPDATE			(0x0008)
+#define S5P_VP_FIELD_ID				(0x000C)
+#define S5P_VP_MODE				(0x0010)
+#define S5P_VP_IMG_SIZE_Y			(0x0014)
+#define S5P_VP_IMG_SIZE_C			(0x0018)
+#define S5P_VP_PER_RATE_CTRL			(0x001C)
+#define S5P_VP_TOP_Y_PTR			(0x0028)
+#define S5P_VP_BOT_Y_PTR			(0x002C)
+#define S5P_VP_TOP_C_PTR			(0x0030)
+#define S5P_VP_BOT_C_PTR			(0x0034)
+#define S5P_VP_ENDIAN_MODE			(0x03CC)
+#define S5P_VP_SRC_H_POSITION			(0x0044)
+#define S5P_VP_SRC_V_POSITION			(0x0048)
+#define S5P_VP_SRC_WIDTH			(0x004C)
+#define S5P_VP_SRC_HEIGHT			(0x0050)
+#define S5P_VP_DST_H_POSITION			(0x0054)
+#define S5P_VP_DST_V_POSITION			(0x0058)
+#define S5P_VP_DST_WIDTH			(0x005C)
+#define S5P_VP_DST_HEIGHT			(0x0060)
+#define S5P_VP_H_RATIO				(0x0064)
+#define S5P_VP_V_RATIO				(0x0068)
+#define S5P_VP_POLY8_Y0_LL			(0x006C)
+#define S5P_VP_POLY8_Y0_LH			(0x0070)
+#define S5P_VP_POLY8_Y0_HL			(0x0074)
+#define S5P_VP_POLY8_Y0_HH			(0x0078)
+#define S5P_VP_POLY8_Y1_LL			(0x007C)
+#define S5P_VP_POLY8_Y1_LH			(0x0080)
+#define S5P_VP_POLY8_Y1_HL			(0x0084)
+#define S5P_VP_POLY8_Y1_HH			(0x0088)
+#define S5P_VP_POLY8_Y2_LL			(0x008C)
+#define S5P_VP_POLY8_Y2_LH			(0x0090)
+#define S5P_VP_POLY8_Y2_HL			(0x0094)
+#define S5P_VP_POLY8_Y2_HH			(0x0098)
+#define S5P_VP_POLY8_Y3_LL			(0x009C)
+#define S5P_VP_POLY8_Y3_LH			(0x00A0)
+#define S5P_VP_POLY8_Y3_HL			(0x00A4)
+#define S5P_VP_POLY8_Y3_HH			(0x00A8)
+#define S5P_VP_POLY4_Y0_LL			(0x00EC)
+#define S5P_VP_POLY4_Y0_LH			(0x00F0)
+#define S5P_VP_POLY4_Y0_HL			(0x00F4)
+#define S5P_VP_POLY4_Y0_HH			(0x00F8)
+#define S5P_VP_POLY4_Y1_LL			(0x00FC)
+#define S5P_VP_POLY4_Y1_LH			(0x0100)
+#define S5P_VP_POLY4_Y1_HL			(0x0104)
+#define S5P_VP_POLY4_Y1_HH			(0x0108)
+#define S5P_VP_POLY4_Y2_LL			(0x010C)
+#define S5P_VP_POLY4_Y2_LH			(0x0110)
+#define S5P_VP_POLY4_Y2_HL			(0x0114)
+#define S5P_VP_POLY4_Y2_HH			(0x0118)
+#define S5P_VP_POLY4_Y3_LL			(0x011C)
+#define S5P_VP_POLY4_Y3_LH			(0x0120)
+#define S5P_VP_POLY4_Y3_HL			(0x0124)
+#define S5P_VP_POLY4_Y3_HH			(0x0128)
+#define S5P_VP_POLY4_C0_LL			(0x012C)
+#define S5P_VP_POLY4_C0_LH			(0x0130)
+#define S5P_VP_POLY4_C0_HL			(0x0134)
+#define S5P_VP_POLY4_C0_HH			(0x0138)
+#define S5P_VP_POLY4_C1_LL			(0x013C)
+#define S5P_VP_POLY4_C1_LH			(0x0140)
+#define S5P_VP_POLY4_C1_HL			(0x0144)
+#define S5P_VP_POLY4_C1_HH			(0x0148)
+#define S5P_VP_FIELD_ID_S			(0x016C)
+#define S5P_VP_MODE_S				(0x0170)
+#define S5P_VP_IMG_SIZE_Y_S			(0x0174)
+#define S5P_VP_IMG_SIZE_C_S			(0x0178)
+#define S5P_VP_TOP_Y_PTR_S			(0x0190)
+#define S5P_VP_BOT_Y_PTR_S			(0x0194)
+#define S5P_VP_TOP_C_PTR_S			(0x0198)
+#define S5P_VP_BOT_C_PTR_S			(0x019C)
+#define S5P_VP_SRC_H_POSITION_S			(0x01AC)
+#define S5P_VP_SRC_V_POSITION_S			(0x01B0)
+#define S5P_VP_SRC_WIDTH_S			(0x01B4)
+#define S5P_VP_SRC_HEIGHT_S			(0x01B8)
+#define S5P_VP_DST_H_POSITION_S			(0x01BC)
+#define S5P_VP_DST_V_POSITION_S			(0x01C0)
+#define S5P_VP_DST_WIDTH_S			(0x01C4)
+#define S5P_VP_DST_HEIGHT_S			(0x01C8)
+#define S5P_VP_H_RATIO_S			(0x01CC)
+#define S5P_VP_V_RATIO_S			(0x01D0)
+#define S5P_PP_CSC_Y2Y_COEF			(0x01D4)
+#define S5P_PP_CSC_CB2Y_COEF			(0x01D8)
+#define S5P_PP_CSC_CR2Y_COEF			(0x01DC)
+#define S5P_PP_CSC_Y2CB_COEF			(0x01E0)
+#define S5P_PP_CSC_CB2CB_COEF			(0x01E4)
+#define S5P_PP_CSC_CR2CB_COEF			(0x01E8)
+#define S5P_PP_CSC_Y2CR_COEF			(0x01EC)
+#define S5P_PP_CSC_CB2CR_COEF			(0x01F0)
+#define S5P_PP_CSC_CR2CR_COEF			(0x01F4)
+#define S5P_PP_BYPASS				(0x0200)
+#define S5P_PP_SATURATION			(0x020C)
+#define S5P_PP_SHARPNESS			(0x0210)
+#define S5P_PP_LINE_EQ0				(0x0218)
+#define S5P_PP_LINE_EQ1				(0x021C)
+#define S5P_PP_LINE_EQ2				(0x0220)
+#define S5P_PP_LINE_EQ3				(0x0224)
+#define S5P_PP_LINE_EQ4				(0x0228)
+#define S5P_PP_LINE_EQ5				(0x022C)
+#define S5P_PP_LINE_EQ6				(0x0230)
+#define S5P_PP_LINE_EQ7				(0x0234)
+#define S5P_PP_BRIGHT_OFFSET			(0x0238)
+#define S5P_PP_CSC_EN				(0x023C)
+#define S5P_PP_BYPASS_S				(0x0258)
+#define S5P_PP_SATURATION_S			(0x025C)
+#define S5P_PP_SHARPNESS_S			(0x0260)
+#define S5P_PP_LINE_EQ0_S			(0x0268)
+#define S5P_PP_LINE_EQ1_S			(0x026C)
+#define S5P_PP_LINE_EQ2_S			(0x0270)
+#define S5P_PP_LINE_EQ3_S			(0x0274)
+#define S5P_PP_LINE_EQ4_S			(0x0278)
+#define S5P_PP_LINE_EQ5_S			(0x027C)
+#define S5P_PP_LINE_EQ6_S			(0x0280)
+#define S5P_PP_LINE_EQ7_S			(0x0284)
+#define S5P_PP_BRIGHT_OFFSET_S			(0x0288)
+#define S5P_PP_CSC_EN_S				(0x028C)
+#define S5P_PP_CSC_Y2Y_COEF_S			(0x0290)
+#define S5P_PP_CSC_CB2Y_COEF_S			(0x0294)
+#define S5P_PP_CSC_CR2Y_COEF_S			(0x0298)
+#define S5P_PP_CSC_Y2CB_COEF_S			(0x029C)
+#define S5P_PP_CSC_CB2CB_COEF_S			(0x02A0)
+#define S5P_PP_CSC_CR2CB_COEF_S			(0x02A4)
+#define S5P_PP_CSC_Y2CR_COEF_S			(0x02A8)
+#define S5P_PP_CSC_CB2CR_COEF_S			(0x02AC)
+#define S5P_PP_CSC_CR2CR_COEF_S			(0x02B0)
+#define S5P_VP_ENDIAN_MODE_S			(0x03EC)
+#define S5P_VP_VERSION_INFO			(0x03FC)
+
+/*
+ * Bit definition part
+ */
+ /* VP_ENABLE */
+#define S5P_VP_ENABLE_ON_S			(1 << 2)
+#define S5P_VP_ENABLE_OPERATING			(1 << 1)
+#define S5P_VP_ENABLE_IDLE_MODE			(0 << 1)
+#define S5P_VP_ENABLE_ON			(1 << 0)
+#define S5P_VP_ENABLE_OFF			(0 << 0)
+
+/* VP_SRESET */
+#define S5P_VP_SRESET_LAST_COMPLETE		(0 << 0)
+#define S5P_VP_SRESET_PROCESSING		(1 << 0)
+
+/* VP_SHADOW_UPDATE */
+#define S5P_VP_SHADOW_UPDATE_DISABLE		(0 << 0)
+#define S5P_VP_SHADOW_UPDATE_ENABLE		(1 << 0)
+
+/* VP_FIELD_ID */
+#define S5P_VP_FIELD_ID_TOP			(0 << 0)
+#define S5P_VP_FIELD_ID_BOTTOM			(1 << 0)
+
+/* VP_MODE */
+#define S5P_VP_MODE_IMG_TYPE_YUV420_NV12	(0 << 6)
+#define S5P_VP_MODE_IMG_TYPE_YUV420_NV21	(1 << 6)
+#define S5P_VP_MODE_LINE_SKIP_OFF		(0 << 5)
+#define S5P_VP_MODE_LINE_SKIP_ON		(1 << 5)
+#define S5P_VP_MODE_MEM_MODE_LINEAR		(0 << 4)
+#define S5P_VP_MODE_MEM_MODE_2D_TILE		(1 << 4)
+#define S5P_VP_MODE_CROMA_EXP_C_TOP_PTR		(0 << 3)
+#define S5P_VP_MODE_CROMA_EXP_C_TOPBOTTOM_PTR	(1 << 3)
+#define S5P_VP_MODE_FIELD_ID_MAN_TOGGLING	(0 << 2)
+#define S5P_VP_MODE_FIELD_ID_AUTO_TOGGLING	(1 << 2)
+#define S5P_VP_MODE_2D_IPC_DISABLE		(0 << 1)
+#define S5P_VP_MODE_2D_IPC_ENABLE		(1 << 1)
+
+/* VP_IMG_SIZE_Y */
+/* VP_IMG_SIZE_C */
+#define S5P_VP_IMG_HSIZE(x)			(((x) & 0x3FFF) << 16)
+#define S5P_VP_IMG_VSIZE(x)			(((x) & 0x3FFF) << 0)
+#define S5P_VP_IMG_SIZE_ILLEGAL(x)		((x) & 0x7)
+
+/* VP_PER_RATE_CTRL */ /* Not support in S5PV210 */
+#define S5P_VP_PEL_RATE_CTRL(x)			(((x) & 0x3) << 0)
+
+/* VP_TOP_Y_PTR */
+/* VP_BOT_Y_PTR */
+/* VP_TOP_C_PTR */
+/* VP_BOT_C_PTR */
+#define S5P_VP_PTR_ILLEGAL(x)			((x) & 0x7)
+
+/* VP_ENDIAN_MODE */
+#define S5P_VP_ENDIAN_MODE_BIG			(0 << 0)
+#define S5P_VP_ENDIAN_MODE_LITTLE		(1 << 0)
+
+/* VP_SRC_H_POSITION */
+#define S5P_VP_SRC_H_POSITION_VAL(x)		(((x) & 0x7FF) << 4)
+#define S5P_VP_SRC_X_FRACT_STEP(x)		((x) & 0xF)
+
+/* VP_SRC_V_POSITION */
+#define S5P_VP_SRC_V_POSITION_VAL(x)		((x) & 0x7FF)
+
+/* VP_SRC_WIDTH */
+/* VP_SRC_HEIGHT */
+#define S5P_VP_SRC_WIDTH_VAL(x)			((x) & 0x7FF)
+#define S5P_VP_SRC_HEIGHT_VAL(x)		((x) & 0x7FF)
+
+/* VP_DST_H_POSITION */
+/* VP_DST_V_POSITION */
+#define S5P_VP_DST_H_POSITION_VAL(x)		((x) & 0x7FF)
+#define S5P_VP_DST_V_POSITION_VAL(x)		((x) & 0x7FF)
+
+/* VP_DST_WIDTH */
+/* VP_DST_HEIGHT */
+#define S5P_VP_DST_WIDTH_VAL(x)			((x) & 0x7FF)
+#define S5P_VP_DST_HEIGHT_VAL(x)		((x) & 0x7FF)
+
+/* VP_H_RATIO */
+/* VP_V_RATIO */
+#define S5P_VP_H_RATIO_VAL(x)			((x) & 0x7FFFF)
+#define S5P_VP_V_RATIO_VAL(x)			((x) & 0x7FFFF)
+
+/* PP_CSC_Y2Y_COEF */
+#define S5P_PP_Y2Y_COEF_601_TO_709		(0x400)
+#define S5P_PP_Y2Y_COEF_709_TO_601		(0x400)
+
+/* PP_CSC_CB2Y_COEF */
+#define S5P_PP_CB2Y_COEF_601_TO_709		(0x879)
+#define S5P_PP_CB2Y_COEF_709_TO_601		(0x068)
+
+/* PP_CSC_CR2Y_COEF */
+#define S5P_PP_CR2Y_COEF_601_TO_709		(0x8D9)
+#define S5P_PP_CR2Y_COEF_709_TO_601		(0x0C9)
+
+/* PP_CSC_Y2CB_COEF */
+#define S5P_PP_Y2CB_COEF_601_TO_709		(0x0)
+#define S5P_PP_Y2CB_COEF_709_TO_601		(0x0)
+
+/* PP_CSC_CB2CB_COEF */
+#define S5P_PP_CB2CB_COEF_601_TO_709		(0x413)
+#define S5P_PP_CB2CB_COEF_709_TO_601		(0x3F6)
+
+/* PP_CSC_CR2CB_COEF */
+#define S5P_PP_CR2CB_COEF_601_TO_709		(0x875)
+#define S5P_PP_CR2CB_COEF_709_TO_601		(0x871)
+
+/* PP_CSC_Y2CR_COEF */
+#define S5P_PP_Y2CR_COEF_601_TO_709		(0x0)
+#define S5P_PP_Y2CR_COEF_709_TO_601		(0x0)
+
+/* PP_CSC_CB2CR_COEF */
+#define S5P_PP_CB2CR_COEF_601_TO_709		(0x04D)
+#define S5P_PP_CB2CR_COEF_709_TO_601		(0x84A)
+
+/* PP_CSC_CR2CR_COEF */
+#define S5P_PP_CR2CR_COEF_601_TO_709		(0x41A)
+#define S5P_PP_CR2CR_COEF_709_TO_601		(0xBEF)
+
+#define S5P_PP_CSC_COEF(x)			((x) & 0xFFF)
+
+/* PP_BYPASS */
+#define S5P_VP_BY_PASS_ENABLE			(0)
+#define S5P_VP_BY_PASS_DISABLE			(1)
+
+/* PP_SATURATION */
+#define S5P_VP_SATURATION(x)			((x) & 0xFF)
+
+/* PP_SHARPNESS */
+#define S5P_VP_TH_HNOISE(x)			(((x) & 0xF) << 8)
+#define S5P_VP_SHARPNESS(x)			((x) & 0x3)
+
+/* PP_LINE_EQ0 ~ 7 */
+#define S5P_VP_LINE_INTC(x)			(((x) & 0xFFFF) << 8)
+#define S5P_VP_LINE_SLOPE(x)			((x) & 0xFF)
+#define S5P_VP_LINE_INTC_CLEAR(x)		((x) & ~(0xFFFF << 8))
+#define S5P_VP_LINE_SLOPE_CLEAR(x)		((x) & ~0xFF)
+
+/* PP_BRIGHT_OFFSET */
+#define S5P_VP_BRIGHT_OFFSET(x)			((x) & 0x1FF)
+
+/* PP_CSC_EN */
+#define S5P_VP_SUB_Y_OFFSET_ENABLE		(1 << 1)
+#define S5P_VP_SUB_Y_OFFSET_DISABLE		(0 << 1)
+#define S5P_VP_CSC_ENABLE			(1)
+#define S5P_VP_CSC_DISABLE			(0)
+
+#endif /* __ARCH_ARM_REGS_VP_H */
diff --git a/arch/arm/mach-exynos/include/mach/restart.h b/arch/arm/mach-exynos/include/mach/restart.h
new file mode 100644
index 0000000..84df9bc
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/restart.h
@@ -0,0 +1,29 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _ASM_ARCH_MSM_RESTART_H_
+#define _ASM_ARCH_MSM_RESTART_H_
+
+#define RESTART_NORMAL 0x0
+#define RESTART_DLOAD  0x1
+
+#ifdef CONFIG_MSM_NATIVE_RESTART
+void msm_set_restart_mode(int mode);
+#else
+#define msm_set_restart_mode(mode)
+#endif
+
+extern int pmic_reset_irq;
+
+#endif
+
diff --git a/arch/arm/mach-exynos/include/mach/sec_debug.h b/arch/arm/mach-exynos/include/mach/sec_debug.h
new file mode 100644
index 0000000..53ca0cb
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/sec_debug.h
@@ -0,0 +1,196 @@
+#ifndef SEC_DEBUG_H
+#define SEC_DEBUG_H
+
+#include <linux/sched.h>
+#include <linux/semaphore.h>
+
+#ifdef CONFIG_SEC_DEBUG
+
+union sec_debug_level_t {
+	struct {
+		u16 kernel_fault;
+		u16 user_fault;
+	} en;
+	u32 uint_val;
+};
+
+extern union sec_debug_level_t sec_debug_level;
+
+extern int sec_debug_init(void);
+
+extern int sec_debug_magic_init(void);
+
+extern void sec_debug_check_crash_key(unsigned int code, int value);
+
+extern void sec_getlog_supply_fbinfo(void *p_fb, u32 res_x, u32 res_y, u32 bpp,
+				     u32 frames);
+extern void sec_getlog_supply_loggerinfo(void *p_main, void *p_radio,
+					 void *p_events, void *p_system);
+extern void sec_getlog_supply_kloginfo(void *klog_buf);
+
+extern void sec_gaf_supply_rqinfo(unsigned short curr_offset,
+				  unsigned short rq_offset);
+#else
+static inline int sec_debug_init(void)
+{
+	return 0;
+}
+
+static inline int sec_debug_magic_init(void)
+{
+	return 0;
+}
+
+static inline void sec_debug_check_crash_key(unsigned int code, int value)
+{
+}
+
+static inline void sec_getlog_supply_fbinfo(void *p_fb, u32 res_x, u32 res_y,
+					    u32 bpp, u32 frames)
+{
+}
+
+static inline void sec_getlog_supply_meminfo(u32 size0, u32 addr0, u32 size1,
+					     u32 addr1)
+{
+}
+
+static inline void sec_getlog_supply_loggerinfo(void *p_main,
+						void *p_radio, void *p_events,
+						void *p_system)
+{
+}
+
+static inline void sec_getlog_supply_kloginfo(void *klog_buf)
+{
+}
+
+static inline void sec_gaf_supply_rqinfo(unsigned short curr_offset,
+					 unsigned short rq_offset)
+{
+}
+
+#endif
+
+struct worker;
+struct work_struct;
+
+#ifdef CONFIG_SEC_DEBUG_SCHED_LOG
+extern void __sec_debug_task_log(int cpu, struct task_struct *task);
+extern void __sec_debug_irq_log(unsigned int irq, void *fn, int en);
+extern void __sec_debug_work_log(struct worker *worker,
+				 struct work_struct *work, work_func_t f);
+
+static inline void sec_debug_task_log(int cpu, struct task_struct *task)
+{
+	if (unlikely(sec_debug_level.en.kernel_fault))
+		__sec_debug_task_log(cpu, task);
+}
+
+static inline void sec_debug_irq_log(unsigned int irq, void *fn, int en)
+{
+	if (unlikely(sec_debug_level.en.kernel_fault))
+		__sec_debug_irq_log(irq, fn, en);
+}
+
+static inline void sec_debug_work_log(struct worker *worker,
+				      struct work_struct *work, work_func_t f)
+{
+	if (unlikely(sec_debug_level.en.kernel_fault))
+		__sec_debug_work_log(worker, work, f);
+}
+
+#ifdef CONFIG_SEC_DEBUG_SOFTIRQ_LOG
+static inline void sec_debug_softirq_log(unsigned int irq, void *fn, int en)
+{
+	if (unlikely(sec_debug_level.en.kernel_fault))
+		__sec_debug_irq_log(irq, fn, en);
+}
+#else
+static inline void sec_debug_softirq_log(unsigned int irq, void *fn, int en)
+{
+}
+#endif
+#else
+static inline void sec_debug_task_log(int cpu, struct task_struct *task)
+{
+}
+
+static inline void sec_debug_irq_log(unsigned int irq, void *fn, int en)
+{
+}
+
+static inline void sec_debug_work_log(struct worker *worker,
+				      struct work_struct *work, work_func_t f)
+{
+}
+
+static inline void sec_debug_softirq_log(unsigned int irq, void *fn, int en)
+{
+}
+#endif
+
+#ifdef CONFIG_SEC_DEBUG_IRQ_EXIT_LOG
+extern void sec_debug_irq_last_exit_log(void);
+#else
+static inline void sec_debug_irq_last_exit_log(void)
+{
+}
+#endif
+
+#ifdef CONFIG_SEC_DEBUG_SEMAPHORE_LOG
+extern void debug_semaphore_init(void);
+extern void debug_semaphore_down_log(struct semaphore *sem);
+extern void debug_semaphore_up_log(struct semaphore *sem);
+extern void debug_rwsemaphore_init(void);
+extern void debug_rwsemaphore_down_log(struct rw_semaphore *sem, int dir);
+extern void debug_rwsemaphore_up_log(struct rw_semaphore *sem);
+#define debug_rwsemaphore_down_read_log(x) \
+	debug_rwsemaphore_down_log(x,READ_SEM)
+#define debug_rwsemaphore_down_write_log(x) \
+	debug_rwsemaphore_down_log(x,WRITE_SEM)
+#else
+static inline void debug_semaphore_init(void)
+{
+}
+
+static inline void debug_semaphore_down_log(struct semaphore *sem)
+{
+}
+
+static inline void debug_semaphore_up_log(struct semaphore *sem)
+{
+}
+
+static inline void debug_rwsemaphore_init(void)
+{
+}
+
+static inline void debug_rwsemaphore_down_read_log(struct rw_semaphore *sem)
+{
+}
+
+static inline void debug_rwsemaphore_down_write_log(struct rw_semaphore *sem)
+{
+}
+
+static inline void debug_rwsemaphore_up_log(struct rw_semaphore *sem)
+{
+}
+#endif
+
+enum sec_debug_aux_log_idx {
+	SEC_DEBUG_AUXLOG_CPU_BUS_CLOCK_CHANGE,
+	SEC_DEBUG_AUXLOG_LOGBUF_LOCK_CHANGE,
+	SEC_DEBUG_AUXLOG_ITEM_MAX,
+};
+
+#ifdef CONFIG_SEC_DEBUG_AUXILIARY_LOG
+extern void sec_debug_aux_log(int idx, char *fmt, ...);
+#else
+#define sec_debug_aux_log(idx, ...) do { } while (0)
+#endif
+
+extern void read_lcd_register(void);
+
+#endif				/* SEC_DEBUG_H */
diff --git a/arch/arm/mach-exynos/include/mach/sec_modem.h b/arch/arm/mach-exynos/include/mach/sec_modem.h
new file mode 100644
index 0000000..097726b
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/sec_modem.h
@@ -0,0 +1,18 @@
+#ifndef _SEC_MODEM_H_
+#define _SEC_MODEM_H_
+
+enum hsic_lpa_states {
+	STATE_HSIC_LPA_ENTER,
+	STATE_HSIC_LPA_WAKE,
+	STATE_HSIC_LPA_PHY_INIT,
+};
+
+#if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB)
+void set_host_states(struct platform_device *pdev, int type);
+void set_hsic_lpa_states(int states);
+int get_cp_active_state(void);
+#else
+#define set_hsic_lpa_states(states) do {} while (0);
+#endif
+
+#endif
diff --git a/arch/arm/mach-exynos/include/mach/sec_thermistor.h b/arch/arm/mach-exynos/include/mach/sec_thermistor.h
new file mode 100644
index 0000000..0df32ed
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/sec_thermistor.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_SEC_THERMISTOR_H
+#define __MACH_SEC_THERMISTOR_H __FILE__
+
+
+/**
+ * struct sec_therm_adc_table - adc to temperature table for sec thermistor
+ * driver
+ * @adc: adc value
+ * @temperature: temperature(C) * 10
+ */
+struct sec_therm_adc_table {
+	int adc;
+	int temperature;
+};
+
+/**
+ * struct sec_bat_plaform_data - init data for sec batter driver
+ * @adc_channel: adc channel that connected to thermistor
+ * @adc_table: array of adc to temperature data
+ * @adc_arr_size: size of adc_table
+ * @polling_interval: interval for polling thermistor (msecs)
+ */
+struct sec_therm_platform_data {
+	unsigned int adc_channel;
+	unsigned int adc_arr_size;
+	struct sec_therm_adc_table *adc_table;
+	unsigned int polling_interval;
+	int (*get_siop_level)(int);
+};
+
+#endif /* __MACH_SEC_THERMISTOR_H */
diff --git a/arch/arm/mach-exynos/include/mach/secmem.h b/arch/arm/mach-exynos/include/mach/secmem.h
new file mode 100644
index 0000000..2b21366
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/secmem.h
@@ -0,0 +1,70 @@
+/* linux/arch/arm/mach-exynos/include/mach/secmem.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS - Secure memory support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_SECMEM_H
+#define __ASM_ARCH_SECMEM_H __FILE__
+
+#include <linux/miscdevice.h>
+#if defined(CONFIG_ION)
+#include <linux/ion.h>
+#endif
+
+struct secchunk_info {
+	int		index;
+	phys_addr_t	base;
+	size_t		size;
+};
+
+extern struct miscdevice secmem;
+#if defined(CONFIG_ION)
+struct secfd_info {
+	int             fd;
+	ion_phys_addr_t phys;
+};
+#endif
+
+
+struct secmem_crypto_driver_ftn {
+	int (*lock) (void);
+	int (*release) (void);
+};
+
+struct secmem_region {
+	char		*virt_addr;
+	unsigned long	phys_addr;
+	unsigned long	len;
+};
+
+#if defined(CONFIG_CPU_EXYNOS4212) || defined(CONFIG_CPU_EXYNOS4412) || \
+		defined(CONFIG_CPU_EXYNOS5250)
+void secmem_crypto_register(struct secmem_crypto_driver_ftn *ftn);
+void secmem_crypto_deregister(void);
+#else
+#define secmem_crypto_register(ftn)
+#define secmem_crypto_deregister()
+#endif
+
+#define SECMEM_IOC_CHUNKINFO		_IOWR('S', 1, struct secchunk_info)
+#define SECMEM_IOC_SET_DRM_ONOFF	_IOWR('S', 2, int)
+#define SECMEM_IOC_GET_DRM_ONOFF	_IOWR('S', 3, int)
+#define SECMEM_IOC_GET_CRYPTO_LOCK	_IOR('S', 4, int)
+#define SECMEM_IOC_RELEASE_CRYPTO_LOCK	_IOR('S', 5, int)
+#define SECMEM_IOC_GET_ADDR		_IOWR('S', 6, int)
+#define SECMEM_IOC_RELEASE_ADDR		_IOWR('S', 7, int)
+#if defined(CONFIG_CPU_EXYNOS5250)
+#define SECMEM_IOC_GET_FD_PHYS_ADDR    _IOWR('S', 8, int)
+#endif
+
+#define SECMEM_IOC_MFC_MAGIC_KEY	_IOWR('S', 9, int)
+
+
+#endif /* __ASM_ARCH_SECMEM_H */
diff --git a/arch/arm/mach-exynos/include/mach/smc.h b/arch/arm/mach-exynos/include/mach/smc.h
new file mode 100644
index 0000000..dd0eb36c
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/smc.h
@@ -0,0 +1,50 @@
+/* linux/arch/arm/mach-exynos/include/mach/smc.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS - SMC Call
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_SMC_H
+#define __ASM_ARCH_SMC_H __FILE__
+
+#define SMC_CMD_INIT		(-1)
+#define SMC_CMD_INFO		(-2)
+/* For Power Management */
+#define SMC_CMD_SLEEP		(-3)
+#define SMC_CMD_CPU1BOOT	(-4)
+#define SMC_CMD_CPU0AFTR	(-5)
+/* For CP15 Access */
+#define SMC_CMD_C15RESUME	(-11)
+/* For L2 Cache Access */
+#define SMC_CMD_L2X0CTRL	(-21)
+#define SMC_CMD_L2X0SETUP1	(-22)
+#define SMC_CMD_L2X0SETUP2	(-23)
+#define SMC_CMD_L2X0INVALL	(-24)
+#define SMC_CMD_L2X0DEBUG	(-25)
+
+/* For Accessing CP15/SFR (General) */
+#define SMC_CMD_REG             (-101)
+
+/* MACRO for SMC_CMD_REG */
+#define SMC_REG_CLASS_CP15	(0x0 << 30)
+#define SMC_REG_CLASS_SFR_W	(0x1 << 30)
+#define SMC_REG_CLASS_SFR_R	(0x3 << 30)
+#define SMC_REG_CLASS_MASK	(0x3 << 30)
+#define SMC_REG_ID_CP15(CRn, Op1, CRm, Op2) \
+	   (SMC_REG_CLASS_CP15 | \
+	    ((CRn) << 10) | ((Op1) << 7) | ((CRm) << 3) | (Op2))
+#define SMC_REG_ID_SFR_W(ADDR)	(SMC_REG_CLASS_SFR_W | ((ADDR) >> 2))
+#define SMC_REG_ID_SFR_R(ADDR)	(SMC_REG_CLASS_SFR_R | ((ADDR) >> 2))
+
+#ifndef __ASSEMBLY__
+extern u32 exynos_smc(u32 cmd, u32 arg1, u32 arg2, u32 arg3);
+extern u32 exynos_smc_readsfr(u32 addr, u32 *val);
+#endif
+
+#endif /* __ASM_ARCH_SMC_H */
diff --git a/arch/arm/mach-exynos/include/mach/spi-clocks.h b/arch/arm/mach-exynos/include/mach/spi-clocks.h
new file mode 100644
index 0000000..d544241
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/spi-clocks.h
@@ -0,0 +1,17 @@
+/* linux/arch/arm/mach-exynos/include/mach/spi-clocks.h
+ *
+ * Copyright (C) 2010 Samsung Electronics Co. Ltd.
+ *	Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __EXYNOS_PLAT_SPI_CLKS_H
+#define __EXYNOS_PLAT_SPI_CLKS_H __FILE__
+
+/* Must source from SCLK_SPI */
+#define EXYNOS_SPI_SRCCLK_SCLK		0
+
+#endif /* __EXYNOS4_PLAT_SPI_CLKS_H */
diff --git a/arch/arm/mach-exynos/include/mach/subsystem_notif.h b/arch/arm/mach-exynos/include/mach/subsystem_notif.h
new file mode 100644
index 0000000..37d4eec
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/subsystem_notif.h
@@ -0,0 +1,80 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *
+ * Subsystem restart notifier API header
+ *
+ */
+
+#ifndef _SUBSYS_NOTIFIER_H
+#define _SUBSYS_NOTIFIER_H
+
+#include <linux/notifier.h>
+
+enum subsys_notif_type {
+	SUBSYS_BEFORE_SHUTDOWN,
+	SUBSYS_AFTER_SHUTDOWN,
+	SUBSYS_BEFORE_POWERUP,
+	SUBSYS_AFTER_POWERUP,
+	SUBSYS_NOTIF_TYPE_COUNT
+};
+
+#if defined(CONFIG_MSM_SUBSYSTEM_RESTART)
+/* Use the subsys_notif_register_notifier API to register for notifications for
+ * a particular subsystem. This API will return a handle that can be used to
+ * un-reg for notifications using the subsys_notif_unregister_notifier API by
+ * passing in that handle as an argument.
+ *
+ * On receiving a notification, the second (unsigned long) argument of the
+ * notifier callback will contain the notification type, and the third (void *)
+ * argument will contain the handle that was returned by
+ * subsys_notif_register_notifier.
+ */
+void *subsys_notif_register_notifier(
+			const char *subsys_name, struct notifier_block *nb);
+int subsys_notif_unregister_notifier(void *subsys_handle,
+				struct notifier_block *nb);
+
+/* Use the subsys_notif_init_subsys API to initialize the notifier chains form
+ * a particular subsystem. This API will return a handle that can be used to
+ * queue notifications using the subsys_notif_queue_notification API by passing
+ * in that handle as an argument.
+ */
+void *subsys_notif_add_subsys(const char *);
+int subsys_notif_queue_notification(void *subsys_handle,
+					enum subsys_notif_type notif_type);
+#else
+
+static inline void *subsys_notif_register_notifier(
+			const char *subsys_name, struct notifier_block *nb)
+{
+	return NULL;
+}
+
+static inline int subsys_notif_unregister_notifier(void *subsys_handle,
+					struct notifier_block *nb)
+{
+	return 0;
+}
+
+static inline void *subsys_notif_add_subsys(const char *subsys_name)
+{
+	return NULL;
+}
+
+static inline int subsys_notif_queue_notification(void *subsys_handle,
+					enum subsys_notif_type notif_type)
+{
+	return 0;
+}
+#endif /* CONFIG_MSM_SUBSYSTEM_RESTART */
+
+#endif
diff --git a/arch/arm/mach-exynos/include/mach/subsystem_restart.h b/arch/arm/mach-exynos/include/mach/subsystem_restart.h
new file mode 100644
index 0000000..f7becef
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/subsystem_restart.h
@@ -0,0 +1,72 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __SUBSYS_RESTART_H
+#define __SUBSYS_RESTART_H
+
+#include <linux/spinlock.h>
+
+#define SUBSYS_NAME_MAX_LENGTH 40
+
+enum {
+	RESET_SOC = 1,
+	RESET_SUBSYS_COUPLED,
+	RESET_SUBSYS_INDEPENDENT,
+	RESET_SUBSYS_MIXED = 25,
+	RESET_LEVEL_MAX
+};
+
+struct subsys_data {
+	const char *name;
+	int (*shutdown) (const struct subsys_data *);
+	int (*powerup) (const struct subsys_data *);
+	void (*crash_shutdown) (const struct subsys_data *);
+	int (*ramdump) (int, const struct subsys_data *);
+
+	/* Internal use only */
+	struct list_head list;
+	void *notif_handle;
+
+	struct mutex shutdown_lock;
+	struct mutex powerup_lock;
+
+	void *restart_order;
+	struct subsys_data *single_restart_list[1];
+};
+
+#if defined(CONFIG_MSM_SUBSYSTEM_RESTART)
+
+int get_restart_level(void);
+int subsystem_restart(const char *subsys_name);
+int ssr_register_subsystem(struct subsys_data *subsys);
+
+#else
+
+static inline int get_restart_level(void)
+{
+	return 0;
+}
+
+static inline int subsystem_restart(const char *subsystem_name)
+{
+	return 0;
+}
+
+static inline int ssr_register_subsystem(struct subsys_data *subsys)
+{
+	return 0;
+}
+
+#endif /* CONFIG_MSM_SUBSYSTEM_RESTART */
+
+#endif
diff --git a/arch/arm/mach-exynos/include/mach/sysmmu.h b/arch/arm/mach-exynos/include/mach/sysmmu.h
new file mode 100644
index 0000000..ccdb975
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/sysmmu.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS - System MMU support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _ARM_MACH_EXYNOS_SYSMMU_H_
+#define _ARM_MACH_EXYNOS_SYSMMU_H_
+
+struct sysmmu_platform_data {
+	char *dbgname;
+	/* comma(,) separated list of clock names for clock gating */
+	char *clockname;
+};
+
+#define SYSMMU_DEVNAME_BASE "exynos-sysmmu"
+
+#define SYSMMU_CLOCK_NAME "sysmmu"
+#define SYSMMU_CLOCK_NAME2 "sysmmu_mc"
+
+#ifdef CONFIG_EXYNOS_DEV_SYSMMU
+#include <linux/device.h>
+struct platform_device;
+
+#define SYSMMU_PLATDEV(ipname) exynos_device_sysmmu_##ipname
+
+extern struct platform_device SYSMMU_PLATDEV(mfc_lr);
+extern struct platform_device SYSMMU_PLATDEV(tv);
+extern struct platform_device SYSMMU_PLATDEV(jpeg);
+extern struct platform_device SYSMMU_PLATDEV(rot);
+extern struct platform_device SYSMMU_PLATDEV(fimc0);
+extern struct platform_device SYSMMU_PLATDEV(fimc1);
+extern struct platform_device SYSMMU_PLATDEV(fimc2);
+extern struct platform_device SYSMMU_PLATDEV(fimc3);
+extern struct platform_device SYSMMU_PLATDEV(gsc0);
+extern struct platform_device SYSMMU_PLATDEV(gsc1);
+extern struct platform_device SYSMMU_PLATDEV(gsc2);
+extern struct platform_device SYSMMU_PLATDEV(gsc3);
+extern struct platform_device SYSMMU_PLATDEV(isp);
+extern struct platform_device SYSMMU_PLATDEV(fimd0);
+extern struct platform_device SYSMMU_PLATDEV(fimd1);
+extern struct platform_device SYSMMU_PLATDEV(camif0);
+extern struct platform_device SYSMMU_PLATDEV(camif1);
+extern struct platform_device SYSMMU_PLATDEV(camif2);
+extern struct platform_device SYSMMU_PLATDEV(2d);
+
+#ifdef CONFIG_IOMMU_API
+static inline void platform_set_sysmmu(
+				struct device *sysmmu, struct device *dev)
+{
+	dev->archdata.iommu = sysmmu;
+}
+#else
+#define platform_set_sysmmu(dev, sysmmu) do { } while (0)
+#endif
+
+#else /* !CONFIG_EXYNOS_DEV_SYSMMU */
+#define platform_set_sysmmu(dev, sysmmu) do { } while (0)
+#endif
+
+#define SYSMMU_CLOCK_DEVNAME(ipname, id) (SYSMMU_DEVNAME_BASE "." #id)
+
+#endif /* _ARM_MACH_EXYNOS_SYSMMU_H_ */
diff --git a/arch/arm/mach-exynos/include/mach/system.h b/arch/arm/mach-exynos/include/mach/system.h
new file mode 100644
index 0000000..51d9bca
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/system.h
@@ -0,0 +1,22 @@
+/* linux/arch/arm/mach-exynos/include/mach/system.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS4 - system support header
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H __FILE__
+
+#include <plat/system-reset.h>
+
+static void arch_idle(void)
+{
+	/* nothing here yet */
+}
+#endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-exynos/include/mach/tdmb_pdata.h b/arch/arm/mach-exynos/include/mach/tdmb_pdata.h
new file mode 100644
index 0000000..ce8a986
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/tdmb_pdata.h
@@ -0,0 +1,31 @@
+/*
+*
+* arch/arm/mach-s5pv310/include/mach/tdmb_pdata.h
+*
+* tdmb driver
+*
+* Copyright (C) (2011, Samsung Electronics)
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation version 2.
+*
+* This program is distributed "as is" WITHOUT ANY WARRANTY of any
+* kind, whether express or implied; without even the implied warranty
+* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+* GNU General Public License for more details.
+*
+*/
+
+#ifndef _TDMB_PDATA_H_
+#define _TDMB_PDATA_H_
+
+
+#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE)
+struct tdmb_platform_data {
+	void (*gpio_on) (void);
+	void (*gpio_off)(void);
+	int	irq;
+};
+#endif
+#endif
diff --git a/arch/arm/mach-exynos/include/mach/timex.h b/arch/arm/mach-exynos/include/mach/timex.h
new file mode 100644
index 0000000..cb5ada2
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/timex.h
@@ -0,0 +1,29 @@
+/* linux/arch/arm/mach-exynos/include/mach/timex.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Copyright (c) 2003-2010 Simtec Electronics
+ *	Ben Dooks <ben@simtec.co.uk>
+ *
+ * Based on arch/arm/mach-s5p6442/include/mach/timex.h
+ *
+ * EXYNOS4 - time parameters
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_TIMEX_H
+#define __ASM_ARCH_TIMEX_H __FILE__
+
+/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it
+ * a variable is useless. It seems as long as we make our timers an
+ * exact multiple of HZ, any value that makes a 1->1 correspondence
+ * for the time conversion functions to/from jiffies is acceptable.
+*/
+
+#define CLOCK_TICK_RATE 12000000
+
+#endif /* __ASM_ARCH_TIMEX_H */
diff --git a/arch/arm/mach-exynos/include/mach/uncompress.h b/arch/arm/mach-exynos/include/mach/uncompress.h
new file mode 100644
index 0000000..0180490
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/uncompress.h
@@ -0,0 +1,30 @@
+/* linux/arch/arm/mach-exynos/include/mach/uncompress.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS4 - uncompress code
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_UNCOMPRESS_H
+#define __ASM_ARCH_UNCOMPRESS_H __FILE__
+
+#include <mach/map.h>
+#include <plat/uncompress.h>
+
+static void arch_detect_cpu(void)
+{
+	/* we do not need to do any cpu detection here at the moment. */
+
+	/*
+	 * For preventing FIFO overrun or infinite loop of UART console,
+	 * fifo_max should be the minimum fifo size of all of the UART channels
+	 */
+	fifo_mask = S5PV210_UFSTAT_TXMASK;
+	fifo_max = 15 << S5PV210_UFSTAT_TXSHIFT;
+}
+#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-exynos/include/mach/usb_bridge.h b/arch/arm/mach-exynos/include/mach/usb_bridge.h
new file mode 100644
index 0000000..1a1c23b
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/usb_bridge.h
@@ -0,0 +1,156 @@
+/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+
+#ifndef __LINUX_USB_BRIDGE_H__
+#define __LINUX_USB_BRIDGE_H__
+
+#include <linux/netdevice.h>
+#include <linux/usb.h>
+
+/* bridge device 0: DUN
+ * bridge device 1 : Tethered RMNET
+ */
+#define MAX_BRIDGE_DEVICES 2
+
+struct bridge_ops {
+	int (*send_pkt)(void *, void *, size_t actual);
+	void (*send_cbits)(void *, unsigned int);
+
+	/* flow control */
+	void (*unthrottle_tx)(void *);
+};
+
+#define TX_THROTTLED BIT(0)
+#define RX_THROTTLED BIT(1)
+
+struct bridge {
+	/* context of the gadget port using bridge driver */
+	void *ctx;
+
+	/* bridge device array index mapped to the gadget port array index.
+	 * data bridge[ch_id] <-- bridge --> gadget port[ch_id]
+	 */
+	unsigned int ch_id;
+
+	/* flow control bits */
+	unsigned long flags;
+
+	/* data/ctrl bridge callbacks */
+	struct bridge_ops ops;
+};
+
+/**
+ * timestamp_info: stores timestamp info for skb life cycle during data
+ * transfer for tethered rmnet/DUN.
+ * @created: stores timestamp at the time of creation of SKB.
+ * @rx_queued: stores timestamp when SKB queued to HW to receive
+ * data.
+ * @rx_done: stores timestamp when skb queued to h/w is completed.
+ * @rx_done_sent: stores timestamp when SKB is sent from gadget rmnet/DUN
+ * driver to bridge rmnet/DUN driver or vice versa.
+ * @tx_queued: stores timestamp when SKB is queued to send data.
+ *
+ * note that size of this struct shouldnt exceed 48bytes that's the max skb->cb
+ * holds.
+ */
+struct timestamp_info {
+	struct data_bridge	*dev;
+
+	unsigned int		created;
+	unsigned int		rx_queued;
+	unsigned int		rx_done;
+	unsigned int		rx_done_sent;
+	unsigned int		tx_queued;
+};
+
+/* Maximum timestamp message length */
+#define DBG_DATA_MSG	128UL
+
+/* Maximum timestamp messages */
+#define DBG_DATA_MAX	32UL
+
+/* timestamp buffer descriptor */
+struct timestamp_buf {
+	char		(buf[DBG_DATA_MAX])[DBG_DATA_MSG];   /* buffer */
+	unsigned	idx;   /* index */
+	rwlock_t	lck;   /* lock */
+};
+
+#if defined(CONFIG_USB_QCOM_MDM_BRIDGE) ||	\
+	defined(CONFIG_USB_QCOM_MDM_BRIDGE_MODULE)
+
+/* Bridge APIs called by gadget driver */
+int ctrl_bridge_open(struct bridge *);
+void ctrl_bridge_close(unsigned int);
+int ctrl_bridge_write(unsigned int, char *, size_t);
+int ctrl_bridge_set_cbits(unsigned int, unsigned int);
+unsigned int ctrl_bridge_get_cbits_tohost(unsigned int);
+int data_bridge_open(struct bridge *brdg);
+void data_bridge_close(unsigned int);
+int data_bridge_write(unsigned int , struct sk_buff *);
+int data_bridge_unthrottle_rx(unsigned int);
+
+/* defined in control bridge */
+int ctrl_bridge_probe(struct usb_interface *, struct usb_host_endpoint *, int);
+void ctrl_bridge_disconnect(unsigned int);
+int ctrl_bridge_resume(unsigned int);
+int ctrl_bridge_suspend(unsigned int);
+
+#else
+
+static inline int __maybe_unused ctrl_bridge_open(struct bridge *brdg)
+{
+	return -ENODEV;
+}
+
+static inline void __maybe_unused ctrl_bridge_close(unsigned int id) { }
+
+static inline int __maybe_unused ctrl_bridge_write(unsigned int id,
+						char *data, size_t size)
+{
+	return -ENODEV;
+}
+
+static inline int __maybe_unused ctrl_bridge_set_cbits(unsigned int id,
+					unsigned int cbits)
+{
+	return -ENODEV;
+}
+
+static inline unsigned int __maybe_unused
+ctrl_bridge_get_cbits_tohost(unsigned int id)
+{
+	return -ENODEV;
+}
+
+static inline int __maybe_unused data_bridge_open(struct bridge *brdg)
+{
+	return -ENODEV;
+}
+
+static inline void __maybe_unused data_bridge_close(unsigned int id) { }
+
+static inline int __maybe_unused data_bridge_write(unsigned int id,
+					    struct sk_buff *skb)
+{
+	return -ENODEV;
+}
+
+static inline int __maybe_unused data_bridge_unthrottle_rx(unsigned int id)
+{
+	return -ENODEV;
+}
+
+#endif
+
+#endif
diff --git a/arch/arm/mach-exynos/include/mach/usb_switch.h b/arch/arm/mach-exynos/include/mach/usb_switch.h
new file mode 100644
index 0000000..de054b6
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/usb_switch.h
@@ -0,0 +1,28 @@
+#ifndef __USB_SWITCH_H__
+#define __USB_SWITCH_H__
+
+extern struct class *sec_class;
+
+enum usb_path_t {
+	USB_PATH_NONE = 0,
+	USB_PATH_ADCCHECK = (1 << 28),
+	USB_PATH_TA = (1 << 24),
+	USB_PATH_CP = (1 << 20),
+#if defined(CONFIG_MACH_P4NOTE)
+	USB_PATH_AP = (1 << 16),
+#else
+	USB_PATH_OTG = (1 << 16),
+	USB_PATH_HOST = (1 << 12)
+#endif
+};
+
+extern int usb_switch_lock(void);
+extern int usb_switch_trylock(void);
+extern void usb_switch_unlock(void);
+
+extern void usb_switch_set_path(enum usb_path_t path);
+extern void usb_switch_clr_path(enum usb_path_t path);
+
+extern void set_usb_connection_state(bool connected);
+
+#endif
diff --git a/arch/arm/mach-exynos/include/mach/usbdiag.h b/arch/arm/mach-exynos/include/mach/usbdiag.h
new file mode 100644
index 0000000..d1e3605
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/usbdiag.h
@@ -0,0 +1,58 @@
+/* include/asm-arm/arch-msm/usbdiag.h
+ *
+ * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ *
+ * All source code in this file is licensed under the following license except
+ * where indicated.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, you can find it at http://www.fsf.org
+ */
+
+#ifndef _DRIVERS_USB_DIAG_H_
+#define _DRIVERS_USB_DIAG_H_
+
+#define DIAG_LEGACY		"diag"
+#define DIAG_MDM		"diag_mdm"
+
+#define USB_DIAG_CONNECT	0
+#define USB_DIAG_DISCONNECT	1
+#define USB_DIAG_WRITE_DONE	2
+#define USB_DIAG_READ_DONE	3
+
+struct diag_request {
+	char *buf;
+	int length;
+	int actual;
+	int status;
+	void *context;
+};
+
+struct usb_diag_ch {
+	const char *name;
+	struct list_head list;
+	void (*notify)(void *priv, unsigned event, struct diag_request *d_req);
+	void *priv;
+	void *priv_usb;
+};
+
+struct usb_diag_ch *usb_diag_open(const char *name, void *priv,
+		void (*notify)(void *, unsigned, struct diag_request *));
+void usb_diag_close(struct usb_diag_ch *ch);
+int usb_diag_alloc_req(struct usb_diag_ch *ch, int n_write, int n_read);
+void usb_diag_free_req(struct usb_diag_ch *ch);
+int usb_diag_read(struct usb_diag_ch *ch, struct diag_request *d_req);
+int usb_diag_write(struct usb_diag_ch *ch, struct diag_request *d_req);
+
+int diag_read_from_cb(unsigned char * , int);
+
+#endif /* _DRIVERS_USB_DIAG_H_ */
diff --git a/arch/arm/mach-exynos/include/mach/videonode-exynos4.h b/arch/arm/mach-exynos/include/mach/videonode-exynos4.h
new file mode 100644
index 0000000..48af509
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/videonode-exynos4.h
@@ -0,0 +1,21 @@
+/* linux/arch/arm/mach-exynos/include/mach/videonode-exynos4.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS4 - Video node definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __MACH_VIDEONODE_EXYNOS4_H
+#define __MACH_VIDEONODE_EXYNOS4_H __FILE__
+
+#define S5P_VIDEONODE_MFC_DEC		6
+#define S5P_VIDEONODE_MFC_ENC		7
+
+#define EXYNOS_VIDEONODE_ROTATOR		21
+
+#endif /* __MACH_VIDEONODE_EXYNOS4_H */
diff --git a/arch/arm/mach-exynos/include/mach/videonode-exynos5.h b/arch/arm/mach-exynos/include/mach/videonode-exynos5.h
new file mode 100644
index 0000000..fc8065c
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/videonode-exynos5.h
@@ -0,0 +1,32 @@
+/* linux/arch/arm/mach-exynos/include/mach/videonode-exynos5.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS5 - Video node definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __MACH_VIDEONODE_EXYNOS5_H
+#define __MACH_VIDEONODE_EXYNOS5_H __FILE__
+
+#define S5P_VIDEONODE_MFC_DEC		6
+#define S5P_VIDEONODE_MFC_ENC		7
+
+#define EXYNOS_VIDEONODE_ROTATOR		21
+
+#define EXYNOS_VIDEONODE_GSC_M2M(x)		(23 + (x) * 3)
+#define EXYNOS_VIDEONODE_GSC_OUT(x)		(24 + (x) * 3)
+#define EXYNOS_VIDEONODE_GSC_CAP(x)		(25 + (x) * 3)
+
+#define EXYNOS_VIDEONODE_FLITE(x)		(36 + x)
+/* Exynos4x12 supports video, graphic0~1 layer
+ * Exynos5250 supports graphic0~3 layer */
+#define EXYNOS_VIDEONODE_MXR_GRP(x)		(16 + x)
+#define EXYNOS_VIDEONODE_MXR_VIDEO		20
+#define EXYNOS_VIDEONODE_FIMC_IS			(40)
+
+#endif /* __MACH_VIDEONODE_EXYNOS5_H */
diff --git a/arch/arm/mach-exynos/include/mach/videonode.h b/arch/arm/mach-exynos/include/mach/videonode.h
new file mode 100644
index 0000000..b0502d4
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/videonode.h
@@ -0,0 +1,24 @@
+/* linux/arch/arm/mach-exynos/include/mach/videonode.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS - Video node  definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __MACH_VIDEONODE_H
+#define __MACH_VIDEONODE_H __FILE__
+
+#if defined(CONFIG_ARCH_EXYNOS4)
+#include "videonode-exynos4.h"
+#elif defined(CONFIG_ARCH_EXYNOS5)
+#include "videonode-exynos5.h"
+#else
+#error "ARCH_EXYNOS* is not defined"
+#endif
+
+#endif /* __MACH_VIDEONODE */
diff --git a/arch/arm/mach-exynos/include/mach/vmalloc.h b/arch/arm/mach-exynos/include/mach/vmalloc.h
new file mode 100644
index 0000000..30b2e38
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/vmalloc.h
@@ -0,0 +1,22 @@
+/* linux/arch/arm/mach-exynos/include/mach/vmalloc.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Copyright 2010 Ben Dooks <ben-linux@fluff.org>
+ *
+ * Based on arch/arm/mach-s5p6440/include/mach/vmalloc.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * EXYNOS4 vmalloc definition
+*/
+
+#ifndef __ASM_ARCH_VMALLOC_H
+#define __ASM_ARCH_VMALLOC_H __FILE__
+
+#define VMALLOC_END	(unsigned long)CONFIG_S3C_ADDR_BASE
+
+#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-exynos/init.c b/arch/arm/mach-exynos/init.c
new file mode 100644
index 0000000..e24d848
--- /dev/null
+++ b/arch/arm/mach-exynos/init.c
@@ -0,0 +1,42 @@
+/* linux/arch/arm/mach-exynos/init.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/serial_core.h>
+
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/regs-serial.h>
+
+static struct s3c24xx_uart_clksrc exynos_serial_clocks[] = {
+	[0] = {
+		.name		= "uclk1",
+		.divisor	= 1,
+		.min_baud	= 0,
+		.max_baud	= 0,
+	},
+};
+
+/* uart registration process */
+void __init exynos_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+{
+	struct s3c2410_uartcfg *tcfg = cfg;
+	u32 ucnt;
+
+	for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
+		if (!tcfg->clocks) {
+			tcfg->has_fracval = 1;
+			tcfg->clocks = exynos_serial_clocks;
+			tcfg->clocks_size = ARRAY_SIZE(exynos_serial_clocks);
+		}
+		tcfg->flags |= NO_NEED_CHECK_CLKSRC;
+	}
+
+	s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no);
+}
diff --git a/arch/arm/mach-exynos/irq-combiner.c b/arch/arm/mach-exynos/irq-combiner.c
new file mode 100644
index 0000000..f2855de
--- /dev/null
+++ b/arch/arm/mach-exynos/irq-combiner.c
@@ -0,0 +1,154 @@
+/* linux/arch/arm/mach-exynos/irq-combiner.c
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Based on arch/arm/common/gic.c
+ *
+ * IRQ COMBINER support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/io.h>
+#include <linux/interrupt.h>
+
+#include <asm/mach/irq.h>
+#include <plat/cpu.h>
+#include <mach/map.h>
+
+#define COMBINER_ENABLE_SET	0x0
+#define COMBINER_ENABLE_CLEAR	0x4
+#define COMBINER_INT_STATUS	0xC
+
+static DEFINE_SPINLOCK(irq_controller_lock);
+
+struct combiner_chip_data {
+	unsigned int irq_offset;
+	unsigned int irq_mask;
+	void __iomem *base;
+	unsigned int parent_irq;
+};
+
+static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
+
+static inline void __iomem *combiner_base(struct irq_data *data)
+{
+	struct combiner_chip_data *combiner_data =
+		irq_data_get_irq_chip_data(data);
+
+	return combiner_data->base;
+}
+
+static void combiner_mask_irq(struct irq_data *data)
+{
+	u32 mask = 1 << (data->irq % 32);
+
+	__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
+}
+
+static void combiner_unmask_irq(struct irq_data *data)
+{
+	u32 mask = 1 << (data->irq % 32);
+
+	__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
+}
+
+static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
+{
+	struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
+	struct irq_chip *chip = irq_get_chip(irq);
+	unsigned int cascade_irq, combiner_irq;
+	unsigned long status;
+
+	chained_irq_enter(chip, desc);
+
+	spin_lock(&irq_controller_lock);
+	status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
+	spin_unlock(&irq_controller_lock);
+	status &= chip_data->irq_mask;
+
+	if (status == 0) {
+		do_bad_IRQ(irq, desc);
+		goto out;
+	}
+
+	combiner_irq = __ffs(status);
+
+	cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
+	if (unlikely(cascade_irq >= NR_IRQS))
+		do_bad_IRQ(cascade_irq, desc);
+	else
+		generic_handle_irq(cascade_irq);
+
+ out:
+	chained_irq_exit(chip, desc);
+}
+
+#ifdef CONFIG_SMP
+static int combiner_set_affinity(struct irq_data *d,
+				 const struct cpumask *mask_val,
+				 bool force)
+{
+	struct combiner_chip_data *cd = irq_data_get_irq_chip_data(d);
+	struct irq_chip *chip = irq_get_chip(cd->parent_irq);
+	struct irq_data *pd = irq_get_irq_data(cd->parent_irq);
+
+	if (chip && chip->irq_set_affinity)
+		return chip->irq_set_affinity(pd, mask_val, force);
+	else
+		return -EINVAL;
+}
+#endif
+
+static struct irq_chip combiner_chip = {
+	.name			= "COMBINER",
+	.irq_mask		= combiner_mask_irq,
+	.irq_unmask		= combiner_unmask_irq,
+#ifdef CONFIG_SMP
+	.irq_set_affinity	= combiner_set_affinity,
+#endif
+};
+
+void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
+{
+	if (combiner_nr >= MAX_COMBINER_NR)
+		BUG();
+	if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
+		BUG();
+	irq_set_chained_handler(irq, combiner_handle_cascade_irq);
+
+	combiner_data[combiner_nr].parent_irq = irq;
+}
+
+void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
+			  unsigned int irq_start)
+{
+	unsigned int i;
+
+	if (combiner_nr >= MAX_COMBINER_NR)
+		BUG();
+
+	combiner_data[combiner_nr].base = base;
+	combiner_data[combiner_nr].irq_offset = irq_start;
+	combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
+
+	/* Disable all interrupts */
+
+	__raw_writel(combiner_data[combiner_nr].irq_mask,
+		     base + COMBINER_ENABLE_CLEAR);
+
+	if (soc_is_exynos4210())
+		__raw_writel(0x01010101, S5P_VA_COMBINER_BASE + 0x40);
+
+	/* Setup the Linux IRQ subsystem */
+
+	for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
+				+ MAX_IRQ_IN_COMBINER; i++) {
+		irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq);
+		irq_set_chip_data(i, &combiner_data[combiner_nr]);
+		set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
+	}
+}
diff --git a/arch/arm/mach-exynos/irq-eint.c b/arch/arm/mach-exynos/irq-eint.c
new file mode 100644
index 0000000..1241dfc
--- /dev/null
+++ b/arch/arm/mach-exynos/irq-eint.c
@@ -0,0 +1,232 @@
+/* linux/arch/arm/mach-exynos/irq-eint.c
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS - IRQ EINT support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/sysdev.h>
+#include <linux/gpio.h>
+
+#include <asm/mach/irq.h>
+
+#include <plat/pm.h>
+#include <plat/cpu.h>
+#include <plat/gpio-cfg.h>
+
+#include <mach/regs-gpio.h>
+
+static DEFINE_SPINLOCK(eint_lock);
+
+static unsigned int eint0_15_data[16];
+
+static unsigned int eint0_15_src_int[16] = {
+	IRQ_EINT0, IRQ_EINT1, IRQ_EINT2, IRQ_EINT3,
+	IRQ_EINT4, IRQ_EINT5, IRQ_EINT6, IRQ_EINT7,
+	IRQ_EINT8, IRQ_EINT9, IRQ_EINT10, IRQ_EINT11,
+	IRQ_EINT12, IRQ_EINT13, IRQ_EINT14, IRQ_EINT15,
+};
+
+static inline void exynos_irq_eint_mask(struct irq_data *data)
+{
+	u32 mask;
+
+	spin_lock(&eint_lock);
+	mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
+	mask |= eint_irq_to_bit(data->irq);
+	__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
+	spin_unlock(&eint_lock);
+}
+
+static void exynos_irq_eint_unmask(struct irq_data *data)
+{
+	u32 mask;
+
+	spin_lock(&eint_lock);
+	mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
+	mask &= ~(eint_irq_to_bit(data->irq));
+	__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
+	spin_unlock(&eint_lock);
+}
+
+static inline void exynos_irq_eint_ack(struct irq_data *data)
+{
+	__raw_writel(eint_irq_to_bit(data->irq),
+		     S5P_EINT_PEND(EINT_REG_NR(data->irq)));
+}
+
+static void exynos_irq_eint_maskack(struct irq_data *data)
+{
+	exynos_irq_eint_mask(data);
+	exynos_irq_eint_ack(data);
+}
+
+static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
+{
+	int offs = EINT_OFFSET(data->irq);
+	int shift;
+	u32 ctrl, mask;
+	u32 newvalue = 0;
+	struct irq_desc *desc = irq_to_desc(data->irq);
+
+	switch (type) {
+	case IRQ_TYPE_EDGE_RISING:
+		newvalue = S5P_IRQ_TYPE_EDGE_RISING;
+		break;
+
+	case IRQ_TYPE_EDGE_FALLING:
+		newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
+		break;
+
+	case IRQ_TYPE_EDGE_BOTH:
+		newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
+		break;
+
+	case IRQ_TYPE_LEVEL_LOW:
+		newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
+		break;
+
+	case IRQ_TYPE_LEVEL_HIGH:
+		newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
+		break;
+
+	default:
+		printk(KERN_ERR "No such irq type %d", type);
+		return -EINVAL;
+	}
+
+	shift = (offs & 0x7) * 4;
+	mask = 0x7 << shift;
+
+	spin_lock(&eint_lock);
+	ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
+	ctrl &= ~mask;
+	ctrl |= newvalue << shift;
+	__raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
+	spin_unlock(&eint_lock);
+
+	switch (offs) {
+	case 0 ... 7:
+		s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
+		break;
+	case 8 ... 15:
+		s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
+		break;
+	case 16 ... 23:
+		s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
+		break;
+	case 24 ... 31:
+		s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
+		break;
+	default:
+		printk(KERN_ERR "No such irq number %d", offs);
+	}
+
+	if (type & IRQ_TYPE_EDGE_BOTH)
+		desc->handle_irq = handle_edge_irq;
+	else
+		desc->handle_irq = handle_level_irq;
+
+	return 0;
+}
+
+static struct irq_chip exynos_irq_eint = {
+	.name		= "exynos-eint",
+	.irq_mask	= exynos_irq_eint_mask,
+	.irq_unmask	= exynos_irq_eint_unmask,
+	.irq_mask_ack	= exynos_irq_eint_maskack,
+	.irq_disable	= exynos_irq_eint_maskack,
+	.irq_ack	= exynos_irq_eint_ack,
+	.irq_set_type	= exynos_irq_eint_set_type,
+#ifdef CONFIG_PM
+	.irq_set_wake	= s3c_irqext_wake,
+#endif
+};
+
+/* exynos_irq_demux_eint
+ *
+ * This function demuxes the IRQ from from EINTs 16 to 31.
+ * It is designed to be inlined into the specific handler
+ * s5p_irq_demux_eintX_Y.
+ *
+ * Each EINT pend/mask registers handle eight of them.
+ */
+static inline u32 exynos_irq_demux_eint(unsigned int start)
+{
+	unsigned int irq;
+
+	u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
+	u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
+	u32 action = 0;
+
+	status &= ~mask;
+	status &= 0xff;
+
+	while (status) {
+		irq = fls(status) - 1;
+		generic_handle_irq(irq + start);
+		status &= ~(1 << irq);
+		++action;
+	}
+
+	return action;
+}
+
+static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
+{
+	struct irq_chip *chip = irq_get_chip(irq);
+	u32 a16_23, a24_31;
+
+	chained_irq_enter(chip, desc);
+	a16_23 = exynos_irq_demux_eint(IRQ_EINT(16));
+	a24_31 = exynos_irq_demux_eint(IRQ_EINT(24));
+	chained_irq_exit(chip, desc);
+
+	if (!a16_23 && !a24_31)
+		do_bad_IRQ(irq, desc);
+}
+
+static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
+{
+	u32 *irq_data = irq_get_handler_data(irq);
+	struct irq_chip *chip = irq_get_chip(irq);
+
+	chained_irq_enter(chip, desc);
+	generic_handle_irq(*irq_data);
+	chained_irq_exit(chip, desc);
+}
+
+int __init exynos_init_irq_eint(void)
+{
+	int irq;
+
+	for (irq = 0 ; irq <= 31 ; irq++) {
+		irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
+					 handle_level_irq);
+		set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
+	}
+
+	irq_set_chained_handler(IRQ_EINT16_31, exynos_irq_demux_eint16_31);
+
+	for (irq = 0 ; irq <= 15 ; irq++) {
+		eint0_15_data[irq] = IRQ_EINT(irq);
+
+		irq_set_handler_data(eint0_15_src_int[irq],
+				     &eint0_15_data[irq]);
+		irq_set_chained_handler(eint0_15_src_int[irq],
+					exynos_irq_eint0_15);
+	}
+
+	return 0;
+}
+
+arch_initcall(exynos_init_irq_eint);
diff --git a/arch/arm/mach-exynos/irq-sgi.c b/arch/arm/mach-exynos/irq-sgi.c
new file mode 100644
index 0000000..ca5973c
--- /dev/null
+++ b/arch/arm/mach-exynos/irq-sgi.c
@@ -0,0 +1,76 @@
+/* linux/arch/arm/mach-exynos/irq-sgi.c
+ *
+ * Copyright (c) 2011 Gisecke & Devrient
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *
+ * Based on linux/arch/arm/plat-s5p/irq-eint.c
+ *
+ * EXYNOS - Software Generated Interrupts Dummy chip support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+
+#include <mach/regs-irq.h>
+
+static inline void exynos_irq_sgi_mask(struct irq_data *d)
+{
+	/* Do nothing, because SGIs are always enabled. */
+}
+
+static void exynos_irq_sgi_unmask(struct irq_data *d)
+{
+	/* Do nothing, because SGIs are always enabled. */
+}
+
+static inline void exynos_irq_sgi_eoi(struct irq_data *d)
+{
+	unsigned int irq = (d->irq - S5P_IRQ_OFFSET);
+
+	writel(irq, S5P_VA_GIC_CPU + GIC_CPU_EOI);
+}
+
+static int exynos_irq_sgi_set_type(struct irq_data *d, unsigned int type)
+{
+	return 0;
+}
+
+static struct irq_chip exynos_irq_sgi = {
+	.name		= "exynos_sgi",
+	.irq_mask	= exynos_irq_sgi_mask,
+	.irq_unmask	= exynos_irq_sgi_unmask,
+	.irq_eoi	= exynos_irq_sgi_eoi,
+	.irq_set_type	= exynos_irq_sgi_set_type,
+};
+
+/*
+ * exynos_init_irq_sgi
+ *
+ * Setup the SGI IRQ to a dummy GIC. The interrupts use the same id
+ * as provided by get_irqnr_and_base, no demuxing is necesarry but
+ * we are handling the last 8 SGIs as normal interrupts in
+ * get_irqnr_and_base.
+ *
+ * NOTE: SGIs are bound to the CPU for which they have been generated
+ * so use with care.
+ */
+int __init exynos_init_irq_sgi(void)
+{
+	int irq;
+
+	for (irq = 8; irq <= 15; irq++) {
+		irq_set_chip_and_handler(IRQ_SGI(irq), &exynos_irq_sgi, handle_fasteoi_irq);
+		set_irq_flags(IRQ_SGI(irq), IRQF_VALID);
+	}
+
+	return 0;
+}
+
+arch_initcall(exynos_init_irq_sgi);
diff --git a/arch/arm/mach-exynos/mach-armlex4210.c b/arch/arm/mach-exynos/mach-armlex4210.c
new file mode 100644
index 0000000..f6b0ba7
--- /dev/null
+++ b/arch/arm/mach-exynos/mach-armlex4210.c
@@ -0,0 +1,214 @@
+/* linux/arch/arm/mach-exynos/mach-armlex4210.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/gpio.h>
+#include <linux/io.h>
+#include <linux/mmc/host.h>
+#include <linux/platform_device.h>
+#include <linux/serial_core.h>
+#include <linux/smsc911x.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/exynos4.h>
+#include <plat/gpio-cfg.h>
+#include <plat/regs-serial.h>
+#include <plat/regs-srom.h>
+#include <plat/sdhci.h>
+
+#include <mach/map.h>
+
+/* Following are default values for UCON, ULCON and UFCON UART registers */
+#define ARMLEX4210_UCON_DEFAULT	(S3C2410_UCON_TXILEVEL |	\
+				 S3C2410_UCON_RXILEVEL |	\
+				 S3C2410_UCON_TXIRQMODE |	\
+				 S3C2410_UCON_RXIRQMODE |	\
+				 S3C2410_UCON_RXFIFO_TOI |	\
+				 S3C2443_UCON_RXERR_IRQEN)
+
+#define ARMLEX4210_ULCON_DEFAULT	S3C2410_LCON_CS8
+
+#define ARMLEX4210_UFCON_DEFAULT	(S3C2410_UFCON_FIFOMODE |	\
+				 S5PV210_UFCON_TXTRIG4 |	\
+				 S5PV210_UFCON_RXTRIG4)
+
+static struct s3c2410_uartcfg armlex4210_uartcfgs[] __initdata = {
+	[0] = {
+		.hwport		= 0,
+		.flags		= 0,
+		.ucon		= ARMLEX4210_UCON_DEFAULT,
+		.ulcon		= ARMLEX4210_ULCON_DEFAULT,
+		.ufcon		= ARMLEX4210_UFCON_DEFAULT,
+	},
+	[1] = {
+		.hwport		= 1,
+		.flags		= 0,
+		.ucon		= ARMLEX4210_UCON_DEFAULT,
+		.ulcon		= ARMLEX4210_ULCON_DEFAULT,
+		.ufcon		= ARMLEX4210_UFCON_DEFAULT,
+	},
+	[2] = {
+		.hwport		= 2,
+		.flags		= 0,
+		.ucon		= ARMLEX4210_UCON_DEFAULT,
+		.ulcon		= ARMLEX4210_ULCON_DEFAULT,
+		.ufcon		= ARMLEX4210_UFCON_DEFAULT,
+	},
+	[3] = {
+		.hwport		= 3,
+		.flags		= 0,
+		.ucon		= ARMLEX4210_UCON_DEFAULT,
+		.ulcon		= ARMLEX4210_ULCON_DEFAULT,
+		.ufcon		= ARMLEX4210_UFCON_DEFAULT,
+	},
+};
+
+static struct s3c_sdhci_platdata armlex4210_hsmmc0_pdata __initdata = {
+	.cd_type		= S3C_SDHCI_CD_PERMANENT,
+	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
+#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
+	.max_width		= 8,
+	.host_caps		= MMC_CAP_8_BIT_DATA,
+#endif
+};
+
+static struct s3c_sdhci_platdata armlex4210_hsmmc2_pdata __initdata = {
+	.cd_type		= S3C_SDHCI_CD_GPIO,
+	.ext_cd_gpio		= EXYNOS4_GPX2(5),
+	.ext_cd_gpio_invert	= 1,
+	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
+	.max_width		= 4,
+};
+
+static struct s3c_sdhci_platdata armlex4210_hsmmc3_pdata __initdata = {
+	.cd_type		= S3C_SDHCI_CD_PERMANENT,
+	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
+	.max_width		= 4,
+};
+
+static void __init armlex4210_sdhci_init(void)
+{
+	s3c_sdhci0_set_platdata(&armlex4210_hsmmc0_pdata);
+	s3c_sdhci2_set_platdata(&armlex4210_hsmmc2_pdata);
+	s3c_sdhci3_set_platdata(&armlex4210_hsmmc3_pdata);
+}
+
+static void __init armlex4210_wlan_init(void)
+{
+	/* enable */
+	s3c_gpio_cfgpin(EXYNOS4_GPX2(0), S3C_GPIO_SFN(0xf));
+	s3c_gpio_setpull(EXYNOS4_GPX2(0), S3C_GPIO_PULL_UP);
+
+	/* reset */
+	s3c_gpio_cfgpin(EXYNOS4_GPX1(6), S3C_GPIO_SFN(0xf));
+	s3c_gpio_setpull(EXYNOS4_GPX1(6), S3C_GPIO_PULL_UP);
+
+	/* wakeup */
+	s3c_gpio_cfgpin(EXYNOS4_GPX1(5), S3C_GPIO_SFN(0xf));
+	s3c_gpio_setpull(EXYNOS4_GPX1(5), S3C_GPIO_PULL_UP);
+}
+
+static struct resource armlex4210_smsc911x_resources[] = {
+	[0] = {
+		.start	= EXYNOS4_PA_SROM_BANK(3),
+		.end	= EXYNOS4_PA_SROM_BANK(3) + SZ_64K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= IRQ_EINT(27),
+		.end	= IRQ_EINT(27),
+		.flags	= IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
+	},
+};
+
+static struct smsc911x_platform_config smsc9215_config = {
+	.irq_polarity	= SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
+	.irq_type	= SMSC911X_IRQ_TYPE_PUSH_PULL,
+	.flags		= SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
+	.phy_interface	= PHY_INTERFACE_MODE_MII,
+	.mac		= {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
+};
+
+static struct platform_device armlex4210_smsc911x = {
+	.name		= "smsc911x",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(armlex4210_smsc911x_resources),
+	.resource	= armlex4210_smsc911x_resources,
+	.dev		= {
+		.platform_data	= &smsc9215_config,
+	},
+};
+
+static struct platform_device *armlex4210_devices[] __initdata = {
+	&s3c_device_hsmmc0,
+	&s3c_device_hsmmc2,
+	&s3c_device_hsmmc3,
+	&s3c_device_rtc,
+	&s3c_device_wdt,
+	&samsung_asoc_dma,
+	&armlex4210_smsc911x,
+	&exynos4_device_ahci,
+};
+
+static void __init armlex4210_smsc911x_init(void)
+{
+	u32 cs1;
+
+	/* configure nCS1 width to 16 bits */
+	cs1 = __raw_readl(S5P_SROM_BW) &
+		~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
+	cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
+		(0 << S5P_SROM_BW__WAITENABLE__SHIFT) |
+		(1 << S5P_SROM_BW__ADDRMODE__SHIFT) |
+		(1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
+		S5P_SROM_BW__NCS1__SHIFT;
+	__raw_writel(cs1, S5P_SROM_BW);
+
+	/* set timing for nCS1 suitable for ethernet chip */
+	__raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
+		     (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
+		     (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
+		     (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
+		     (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
+		     (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
+		     (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
+}
+
+static void __init armlex4210_map_io(void)
+{
+	s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+	s3c24xx_init_clocks(24000000);
+	s3c24xx_init_uarts(armlex4210_uartcfgs,
+			   ARRAY_SIZE(armlex4210_uartcfgs));
+}
+
+static void __init armlex4210_machine_init(void)
+{
+	armlex4210_smsc911x_init();
+
+	armlex4210_sdhci_init();
+
+	armlex4210_wlan_init();
+
+	platform_add_devices(armlex4210_devices,
+			     ARRAY_SIZE(armlex4210_devices));
+}
+
+MACHINE_START(ARMLEX4210, "ARMLEX4210")
+	/* Maintainer: Alim Akhtar <alim.akhtar@samsung.com> */
+	.boot_params	= S5P_PA_SDRAM + 0x100,
+	.init_irq	= exynos4_init_irq,
+	.map_io		= armlex4210_map_io,
+	.init_machine	= armlex4210_machine_init,
+	.timer		= &exynos4_timer,
+MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-midas.c b/arch/arm/mach-exynos/mach-midas.c
new file mode 100644
index 0000000..5603258
--- /dev/null
+++ b/arch/arm/mach-exynos/mach-midas.c
@@ -0,0 +1,2802 @@
+/* linux/arch/arm/mach-exynos/mach-smdk4212.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/serial_core.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi_gpio.h>
+#include <linux/clk.h>
+#include <linux/gpio.h>
+#include <linux/gpio_keys.h>
+#include <linux/gpio_event.h>
+#include <linux/i2c.h>
+#include <linux/i2c-gpio.h>
+#include <linux/pwm_backlight.h>
+#include <linux/input.h>
+#include <linux/mmc/host.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/max8649.h>
+#include <linux/regulator/fixed.h>
+#ifdef CONFIG_LEDS_AAT1290A
+#include <linux/leds-aat1290a.h>
+#endif
+#ifdef CONFIG_MFD_MAX77693
+#include <linux/mfd/max77693.h>
+#include <linux/mfd/max77693-private.h>
+#include <linux/leds-max77693.h>
+#endif
+
+#ifdef CONFIG_BATTERY_MAX17047_FUELGAUGE
+#include <linux/battery/max17047_fuelgauge.h>
+#endif
+#if defined(CONFIG_BATTERY_SAMSUNG) || defined(CONFIG_BATTERY_SAMSUNG_S2PLUS)
+#include <linux/power_supply.h>
+#include <linux/battery/samsung_battery.h>
+#endif
+#if defined(CONFIG_CHARGER_MAX8922_U1) || defined(CONFIG_CHARGER_MAX8922_S2PLUS)
+#include <linux/power/max8922_charger_u1.h>
+#endif
+#ifdef CONFIG_STMPE811_ADC
+#include <linux/stmpe811-adc.h>
+#endif
+#include <linux/v4l2-mediabus.h>
+#include <linux/memblock.h>
+#include <linux/delay.h>
+#include <linux/bootmem.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <plat/regs-serial.h>
+#include <plat/exynos4.h>
+#include <plat/cpu.h>
+#include <plat/clock.h>
+#include <plat/keypad.h>
+#include <plat/devs.h>
+#include <plat/fb-s5p.h>
+#include <plat/fb-core.h>
+#include <plat/regs-fb-v4.h>
+#include <plat/backlight.h>
+#include <plat/gpio-cfg.h>
+#include <plat/iic.h>
+#include <plat/pd.h>
+#include <plat/sdhci.h>
+#include <plat/mshci.h>
+#include <plat/ehci.h>
+#include <plat/usbgadget.h>
+#include <plat/s3c64xx-spi.h>
+#include <plat/tvout.h>
+#include <plat/csis.h>
+#include <plat/media.h>
+#include <plat/adc.h>
+#include <media/exynos_fimc_is.h>
+#include <mach/exynos-ion.h>
+
+#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE)
+#include <mach/tdmb_pdata.h>
+#endif
+
+#include <mach/map.h>
+#include <mach/spi-clocks.h>
+
+#include <mach/dev.h>
+#include <mach/ppmu.h>
+
+#ifdef CONFIG_EXYNOS4_SETUP_THERMAL
+#include <plat/s5p-tmu.h>
+#include <mach/regs-tmu.h>
+#endif
+
+#ifdef CONFIG_EXYNOS_C2C
+#include <mach/c2c.h>
+#endif
+#if defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC) || defined(CONFIG_VIDEO_MFC5X)
+#include <plat/s5p-mfc.h>
+#endif
+
+#include <plat/fb-s5p.h>
+
+#ifdef CONFIG_FB_S5P_EXTDSP
+struct s3cfb_extdsp_lcd {
+	int	width;
+	int	height;
+	int	bpp;
+};
+#endif
+#include <mach/dev-sysmmu.h>
+
+#ifdef CONFIG_VIDEO_JPEG_V2X
+#include <plat/jpeg.h>
+#endif
+
+#include <plat/fimg2d.h>
+#include <plat/s5p-sysmmu.h>
+
+#include <mach/sec_debug.h>
+
+#include <mach/gpio-midas.h>
+#ifdef CONFIG_MACH_GC1
+#include <mach/gc1-power.h>
+#else
+#include <mach/midas-power.h>
+#endif
+#ifdef CONFIG_SEC_THERMISTOR
+#include <mach/sec_thermistor.h>
+#endif
+#include <mach/midas-thermistor.h>
+#include <mach/midas-tsp.h>
+#include <mach/regs-clock.h>
+
+#include <mach/midas-lcd.h>
+#include <mach/midas-sound.h>
+
+#ifdef CONFIG_USB_HOST_NOTIFY
+#include <linux/host_notify.h>
+#endif
+
+#if defined(CONFIG_PHONE_IPC_SPI)
+#include <linux/phone_svn/ipc_spi.h>
+#include <linux/irq.h>
+#endif
+
+#ifdef CONFIG_KEYBOARD_CYPRESS_TOUCH
+#include <linux/i2c/touchkey_i2c.h>
+#endif
+
+#include "board-mobile.h"
+
+/* Following are default values for UCON, ULCON and UFCON UART registers */
+#define SMDK4212_UCON_DEFAULT	(S3C2410_UCON_TXILEVEL |	\
+				 S3C2410_UCON_RXILEVEL |	\
+				 S3C2410_UCON_TXIRQMODE |	\
+				 S3C2410_UCON_RXIRQMODE |	\
+				 S3C2410_UCON_RXFIFO_TOI |	\
+				 S3C2443_UCON_RXERR_IRQEN)
+
+#define SMDK4212_ULCON_DEFAULT	S3C2410_LCON_CS8
+
+#define SMDK4212_UFCON_DEFAULT	(S3C2410_UFCON_FIFOMODE |	\
+				 S5PV210_UFCON_TXTRIG4 |	\
+				 S5PV210_UFCON_RXTRIG4)
+
+#define SMDK4212_UFCON_GPS	(S3C2410_UFCON_FIFOMODE |	\
+				S5PV210_UFCON_TXTRIG8 |	\
+				S5PV210_UFCON_RXTRIG32)
+
+static struct s3c2410_uartcfg smdk4212_uartcfgs[] __initdata = {
+	[0] = {
+		.hwport		= 0,
+		.flags		= 0,
+		.ucon		= SMDK4212_UCON_DEFAULT,
+		.ulcon		= SMDK4212_ULCON_DEFAULT,
+		.ufcon		= SMDK4212_UFCON_DEFAULT,
+	},
+	[1] = {
+		.hwport		= 1,
+		.flags		= 0,
+		.ucon		= SMDK4212_UCON_DEFAULT,
+		.ulcon		= SMDK4212_ULCON_DEFAULT,
+		.ufcon		= SMDK4212_UFCON_GPS,
+		.set_runstate	= set_gps_uart_op,
+	},
+	[2] = {
+		.hwport		= 2,
+		.flags		= 0,
+		.ucon		= SMDK4212_UCON_DEFAULT,
+		.ulcon		= SMDK4212_ULCON_DEFAULT,
+		.ufcon		= SMDK4212_UFCON_DEFAULT,
+	},
+	[3] = {
+		.hwport		= 3,
+		.flags		= 0,
+		.ucon		= SMDK4212_UCON_DEFAULT,
+		.ulcon		= SMDK4212_ULCON_DEFAULT,
+		.ufcon		= SMDK4212_UFCON_DEFAULT,
+	},
+};
+
+#if defined(CONFIG_S3C64XX_DEV_SPI)
+#if defined(CONFIG_VIDEO_S5C73M3_SPI)
+
+static struct s3c64xx_spi_csinfo spi1_csi[] = {
+	[0] = {
+		.line = EXYNOS4_GPB(5),
+		.set_level = gpio_set_value,
+		.fb_delay = 0x2,
+	},
+};
+
+static struct spi_board_info spi1_board_info[] __initdata = {
+	{
+		.modalias = "s5c73m3_spi",
+		.platform_data = NULL,
+		.max_speed_hz = 50000000,
+		.bus_num = 1,
+		.chip_select = 0,
+		.mode = SPI_MODE_0,
+		.controller_data = &spi1_csi[0],
+	}
+};
+#endif
+
+#if defined(CONFIG_PHONE_IPC_SPI) \
+	|| defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE)
+static struct s3c64xx_spi_csinfo spi2_csi[] = {
+	[0] = {
+		.line = EXYNOS4_GPC1(2),
+		.set_level = gpio_set_value,
+	},
+};
+
+static struct spi_board_info spi2_board_info[] __initdata = {
+#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE)
+	{
+		.modalias = "tdmbspi",
+		.platform_data = NULL,
+		.max_speed_hz = 5000000,
+		.bus_num = 2,
+		.chip_select = 0,
+		.mode = SPI_MODE_0,
+		.controller_data = &spi2_csi[0],
+	},
+#else
+	{
+		.modalias = "ipc_spi",
+		.platform_data = NULL,
+		.bus_num = 2,
+		.chip_select = 0,
+		.max_speed_hz = 12*1000*1000,
+		.mode = SPI_MODE_1,
+		.controller_data = &spi2_csi[0],
+	}
+#endif
+};
+#endif
+#endif
+
+static struct i2c_board_info i2c_devs8_emul[];
+
+#ifdef CONFIG_KEYBOARD_CYPRESS_TOUCH
+static void touchkey_init_hw(void)
+{
+#if defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_C1VZW)\
+|| defined(CONFIG_MACH_C1)
+#if defined(CONFIG_MACH_M0_CHNOPEN) || defined(CONFIG_MACH_M0_HKTW)\
+|| defined(CONFIG_TARGET_LOCALE_KOR)
+/* do nothing */
+#elif defined(CONFIG_MACH_C1)
+#if defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT)
+	if (system_rev < 8)
+		return ;
+#elif defined(CONFIG_MACH_C1_KOR_LGT)
+	if (system_rev < 5)
+		return ;
+#else
+	if (system_rev < 7)
+		return ;
+#endif 
+#else
+	/*rev 1.0*/
+	if (system_rev < 11)
+		return ;
+#endif
+#endif
+#if defined(CONFIG_MACH_S2PLUS)\
+|| defined(CONFIG_TARGET_LOCALE_KOR)\
+|| defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_C1VZW)\
+|| defined(CONFIG_MACH_C1)
+	gpio_request(GPIO_3_TOUCH_EN, "gpio_3_touch_en");
+#if defined(CONFIG_MACH_C1_KOR_LGT)
+	gpio_request(GPIO_3_TOUCH_LDO_EN, "gpio_3_touch_ldo_en");
+#endif
+#endif
+	gpio_request(GPIO_3_TOUCH_INT, "3_TOUCH_INT");
+	s3c_gpio_setpull(GPIO_3_TOUCH_INT, S3C_GPIO_PULL_NONE);
+	s5p_register_gpio_interrupt(GPIO_3_TOUCH_INT);
+	gpio_direction_input(GPIO_3_TOUCH_INT);
+
+	i2c_devs8_emul[0].irq = gpio_to_irq(GPIO_3_TOUCH_INT);
+	irq_set_irq_type(gpio_to_irq(GPIO_3_TOUCH_INT), IRQF_TRIGGER_FALLING);
+	s3c_gpio_cfgpin(GPIO_3_TOUCH_INT, S3C_GPIO_SFN(0xf));
+
+	s3c_gpio_setpull(GPIO_3_TOUCH_SCL, S3C_GPIO_PULL_DOWN);
+	s3c_gpio_setpull(GPIO_3_TOUCH_SDA, S3C_GPIO_PULL_DOWN);
+
+}
+
+static int touchkey_suspend(void)
+{
+	struct regulator *regulator;
+
+	regulator = regulator_get(NULL, TK_REGULATOR_NAME);
+	if (IS_ERR(regulator))
+		return 0;
+	if (regulator_is_enabled(regulator))
+		regulator_force_disable(regulator);
+
+	#if defined(CONFIG_MACH_C1_KOR_LGT)
+	gpio_request(GPIO_3_TOUCH_LDO_EN, "gpio_3_touch_ldo_en");
+	gpio_direction_output(GPIO_3_TOUCH_LDO_EN, 0);
+	#endif
+
+	s3c_gpio_setpull(GPIO_3_TOUCH_SCL, S3C_GPIO_PULL_DOWN);
+	s3c_gpio_setpull(GPIO_3_TOUCH_SDA, S3C_GPIO_PULL_DOWN);
+
+	regulator_put(regulator);
+
+	return 1;
+}
+
+static int touchkey_resume(void)
+{
+	struct regulator *regulator;
+
+	regulator = regulator_get(NULL, TK_REGULATOR_NAME);
+	if (IS_ERR(regulator))
+		return 0;
+	regulator_enable(regulator);
+	#if defined(CONFIG_MACH_C1_KOR_LGT)
+	gpio_request(GPIO_3_TOUCH_LDO_EN, "gpio_3_touch_ldo_en");
+	gpio_direction_output(GPIO_3_TOUCH_LDO_EN, 1);
+	#endif
+	regulator_put(regulator);
+
+	s3c_gpio_setpull(GPIO_3_TOUCH_SCL, S3C_GPIO_PULL_NONE);
+	s3c_gpio_setpull(GPIO_3_TOUCH_SDA, S3C_GPIO_PULL_NONE);
+
+	return 1;
+}
+
+static int touchkey_power_on(bool on)
+{
+	int ret;
+
+	if (on) {
+		gpio_direction_output(GPIO_3_TOUCH_INT, 1);
+		irq_set_irq_type(gpio_to_irq(GPIO_3_TOUCH_INT), IRQF_TRIGGER_FALLING);
+		s3c_gpio_cfgpin(GPIO_3_TOUCH_INT, S3C_GPIO_SFN(0xf));
+		s3c_gpio_setpull(GPIO_3_TOUCH_INT, S3C_GPIO_PULL_NONE);
+	} else
+		gpio_direction_input(GPIO_3_TOUCH_INT);
+
+	if (on)
+		ret = touchkey_resume();
+	else
+		ret = touchkey_suspend();
+
+	return ret;
+}
+
+static int touchkey_led_power_on(bool on)
+{
+#if defined(LED_LDO_WITH_EN_PIN)
+	if (on)
+		gpio_direction_output(GPIO_3_TOUCH_EN, 1);
+	else
+		gpio_direction_output(GPIO_3_TOUCH_EN, 0);
+#else
+	struct regulator *regulator;
+
+	if (on) {
+		regulator = regulator_get(NULL, "touch_led");
+		if (IS_ERR(regulator))
+			return 0;
+		regulator_enable(regulator);
+		regulator_put(regulator);
+	} else {
+		regulator = regulator_get(NULL, "touch_led");
+		if (IS_ERR(regulator))
+			return 0;
+		if (regulator_is_enabled(regulator))
+			regulator_force_disable(regulator);
+		regulator_put(regulator);
+	}
+#endif
+	return 1;
+}
+
+static struct touchkey_platform_data touchkey_pdata = {
+	.gpio_sda = GPIO_3_TOUCH_SDA,
+	.gpio_scl = GPIO_3_TOUCH_SCL,
+	.gpio_int = GPIO_3_TOUCH_INT,
+	.init_platform_hw = touchkey_init_hw,
+	.suspend = touchkey_suspend,
+	.resume = touchkey_resume,
+	.power_on = touchkey_power_on,
+	.led_power_on = touchkey_led_power_on,
+};
+#endif /*CONFIG_KEYBOARD_CYPRESS_TOUCH*/
+
+
+#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE)
+static void tdmb_set_config_poweron(void)
+{
+	s3c_gpio_cfgpin(GPIO_TDMB_EN, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TDMB_EN, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TDMB_EN, GPIO_LEVEL_LOW);
+
+	s3c_gpio_cfgpin(GPIO_TDMB_INT, S3C_GPIO_SFN(GPIO_TDMB_INT_AF));
+	s3c_gpio_setpull(GPIO_TDMB_INT, S3C_GPIO_PULL_NONE);
+
+	s3c_gpio_cfgpin(GPIO_TDMB_SPI_CLK, S3C_GPIO_SFN(5));
+	s3c_gpio_cfgpin(GPIO_TDMB_SPI_MISO, S3C_GPIO_SFN(5));
+	s3c_gpio_cfgpin(GPIO_TDMB_SPI_MOSI, S3C_GPIO_SFN(5));
+	s3c_gpio_setpull(GPIO_TDMB_SPI_CLK, S3C_GPIO_PULL_DOWN);
+	s3c_gpio_setpull(GPIO_TDMB_SPI_MISO, S3C_GPIO_PULL_DOWN);
+	s3c_gpio_setpull(GPIO_TDMB_SPI_MOSI, S3C_GPIO_PULL_DOWN);
+}
+static void tdmb_set_config_poweroff(void)
+{
+	s3c_gpio_cfgpin(GPIO_TDMB_EN, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TDMB_EN, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TDMB_EN, GPIO_LEVEL_LOW);
+
+	s3c_gpio_cfgpin(GPIO_TDMB_INT, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TDMB_INT, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TDMB_INT, GPIO_LEVEL_LOW);
+}
+
+static void tdmb_gpio_on(void)
+{
+	printk(KERN_DEBUG "tdmb_gpio_on\n");
+
+	tdmb_set_config_poweron();
+
+	gpio_set_value(GPIO_TDMB_EN, GPIO_LEVEL_LOW);
+	usleep_range(1000, 1000);
+	gpio_set_value(GPIO_TDMB_EN, GPIO_LEVEL_HIGH);
+}
+
+static void tdmb_gpio_off(void)
+{
+	printk(KERN_DEBUG "tdmb_gpio_off\n");
+
+	tdmb_set_config_poweroff();
+
+	gpio_set_value(GPIO_TDMB_EN, GPIO_LEVEL_LOW);
+}
+
+static struct tdmb_platform_data tdmb_pdata = {
+	.gpio_on = tdmb_gpio_on,
+	.gpio_off = tdmb_gpio_off,
+};
+
+static struct platform_device tdmb_device = {
+	.name			= "tdmb",
+	.id				= -1,
+	.dev			= {
+		.platform_data = &tdmb_pdata,
+	},
+};
+
+static int __init tdmb_dev_init(void)
+{
+	tdmb_set_config_poweroff();
+	s5p_register_gpio_interrupt(GPIO_TDMB_INT);
+	tdmb_pdata.irq = GPIO_TDMB_IRQ;
+	platform_device_register(&tdmb_device);
+
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_PHONE_IPC_SPI)
+static void ipc_spi_cfg_gpio(void);
+
+static struct ipc_spi_platform_data ipc_spi_data = {
+	.gpio_ipc_mrdy = GPIO_IPC_MRDY,
+	.gpio_ipc_srdy = GPIO_IPC_SRDY,
+	.gpio_ipc_sub_mrdy = GPIO_IPC_SUB_MRDY,
+	.gpio_ipc_sub_srdy = GPIO_IPC_SUB_SRDY,
+
+	.cfg_gpio = ipc_spi_cfg_gpio,
+};
+
+static struct resource ipc_spi_res[] = {
+	[0] = {
+		.start = IRQ_IPC_SRDY,
+		.end = IRQ_IPC_SRDY,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device ipc_spi_device = {
+	.name = "onedram",
+	.id = -1,
+	.num_resources = ARRAY_SIZE(ipc_spi_res),
+	.resource = ipc_spi_res,
+	.dev = {
+		.platform_data = &ipc_spi_data,
+	},
+};
+
+static void ipc_spi_cfg_gpio(void)
+{
+	int err = 0;
+
+	unsigned gpio_ipc_mrdy = ipc_spi_data.gpio_ipc_mrdy;
+	unsigned gpio_ipc_srdy = ipc_spi_data.gpio_ipc_srdy;
+	unsigned gpio_ipc_sub_mrdy = ipc_spi_data.gpio_ipc_sub_mrdy;
+	unsigned gpio_ipc_sub_srdy = ipc_spi_data.gpio_ipc_sub_srdy;
+
+	err = gpio_request(gpio_ipc_mrdy, "IPC_MRDY");
+	if (err) {
+		printk(KERN_ERR "ipc_spi_cfg_gpio - fail to request gpio %s : %d\n",
+			"IPC_MRDY", err);
+	} else {
+		gpio_direction_output(gpio_ipc_mrdy, 0);
+	}
+
+	err = gpio_request(gpio_ipc_srdy, "IPC_SRDY");
+	if (err) {
+		printk(KERN_ERR "ipc_spi_cfg_gpio - fail to request gpio %s : %d\n",
+			"IPC_SRDY", err);
+	} else {
+		gpio_direction_input(gpio_ipc_srdy);
+		s3c_gpio_cfgpin(gpio_ipc_srdy, S3C_GPIO_SFN(0xF));
+		s3c_gpio_setpull(gpio_ipc_srdy, S3C_GPIO_PULL_DOWN);
+	}
+
+	err = gpio_request(gpio_ipc_sub_mrdy, "IPC_SUB_MRDY");
+	if (err) {
+		printk(KERN_ERR "ipc_spi_cfg_gpio - fail to request gpio %s : %d\n",
+			"IPC_SUB_MRDY", err);
+	} else {
+		gpio_direction_output(gpio_ipc_sub_mrdy, 0);
+	}
+
+	err = gpio_request(gpio_ipc_sub_srdy, "IPC_SUB_SRDY");
+	if (err) {
+		printk(KERN_ERR "ipc_spi_cfg_gpio - fail to request gpio %s : %d\n",
+			"IPC_SUB_SRDY", err);
+	} else {
+		gpio_direction_input(gpio_ipc_sub_srdy);
+		s3c_gpio_cfgpin(gpio_ipc_sub_srdy, S3C_GPIO_SFN(0xF));
+		s3c_gpio_setpull(gpio_ipc_sub_srdy, S3C_GPIO_PULL_DOWN);
+	}
+
+	irq_set_irq_type(gpio_to_irq(GPIO_IPC_SRDY), IRQ_TYPE_EDGE_RISING);
+	irq_set_irq_type(gpio_to_irq(GPIO_IPC_SUB_SRDY), IRQ_TYPE_EDGE_RISING);
+}
+#endif
+
+#ifdef CONFIG_LEDS_AAT1290A
+static int aat1290a_initGpio(void)
+{
+	int err;
+
+	err = gpio_request(GPIO_CAM_SW_EN, "CAM_SW_EN");
+	if (err) {
+		printk(KERN_ERR "failed to request CAM_SW_EN\n");
+		return -EPERM;
+	}
+	gpio_direction_output(GPIO_CAM_SW_EN, 1);
+
+	return 0;
+}
+
+static void aat1290a_switch(int enable)
+{
+	gpio_set_value(GPIO_CAM_SW_EN, enable);
+}
+
+static int aat1290a_setGpio(void)
+{
+	int err;
+
+	err = gpio_request(GPIO_TORCH_EN, "TORCH_EN");
+	if (err) {
+		printk(KERN_ERR "failed to request TORCH_EN\n");
+		return -EPERM;
+	}
+	gpio_direction_output(GPIO_TORCH_EN, 0);
+	err = gpio_request(GPIO_TORCH_SET, "TORCH_SET");
+	if (err) {
+		printk(KERN_ERR "failed to request TORCH_SET\n");
+		gpio_free(GPIO_TORCH_EN);
+		return -EPERM;
+	}
+	gpio_direction_output(GPIO_TORCH_SET, 0);
+
+	return 0;
+}
+
+static int aat1290a_freeGpio(void)
+{
+	gpio_free(GPIO_TORCH_EN);
+	gpio_free(GPIO_TORCH_SET);
+
+	return 0;
+}
+
+static void aat1290a_torch_en(int onoff)
+{
+	gpio_set_value(GPIO_TORCH_EN, onoff);
+}
+
+static void aat1290a_torch_set(int onoff)
+{
+	gpio_set_value(GPIO_TORCH_SET, onoff);
+}
+
+static struct aat1290a_led_platform_data aat1290a_led_data = {
+	.brightness = TORCH_BRIGHTNESS_50,
+	.status	= STATUS_UNAVAILABLE,
+	.switch_sel = aat1290a_switch,
+	.initGpio = aat1290a_initGpio,
+	.setGpio = aat1290a_setGpio,
+	.freeGpio = aat1290a_freeGpio,
+	.torch_en = aat1290a_torch_en,
+	.torch_set = aat1290a_torch_set,
+};
+
+static struct platform_device s3c_device_aat1290a_led = {
+	.name	= "aat1290a-led",
+	.id	= -1,
+	.dev	= {
+		.platform_data	= &aat1290a_led_data,
+	},
+};
+#endif
+
+static DEFINE_MUTEX(notify_lock);
+
+#define DEFINE_MMC_CARD_NOTIFIER(num) \
+static void (*hsmmc##num##_notify_func)(struct platform_device *, int state); \
+static int ext_cd_init_hsmmc##num(void (*notify_func)( \
+			struct platform_device *, int state)) \
+{ \
+	mutex_lock(&notify_lock); \
+	WARN_ON(hsmmc##num##_notify_func); \
+	hsmmc##num##_notify_func = notify_func; \
+	mutex_unlock(&notify_lock); \
+	return 0; \
+} \
+static int ext_cd_cleanup_hsmmc##num(void (*notify_func)( \
+			struct platform_device *, int state)) \
+{ \
+	mutex_lock(&notify_lock); \
+	WARN_ON(hsmmc##num##_notify_func != notify_func); \
+	hsmmc##num##_notify_func = NULL; \
+	mutex_unlock(&notify_lock); \
+	return 0; \
+}
+
+#ifdef CONFIG_S3C_DEV_HSMMC3
+	DEFINE_MMC_CARD_NOTIFIER(3)
+#endif
+
+/*
+ * call this when you need sd stack to recognize insertion or removal of card
+ * that can't be told by SDHCI regs
+ */
+void mmc_force_presence_change(struct platform_device *pdev)
+{
+	void (*notify_func)(struct platform_device *, int state) = NULL;
+	mutex_lock(&notify_lock);
+#ifdef CONFIG_S3C_DEV_HSMMC3
+	if (pdev == &s3c_device_hsmmc3)
+		notify_func = hsmmc3_notify_func;
+#endif
+
+	if (notify_func)
+		notify_func(pdev, 1);
+	else
+		pr_warn("%s: called for device with no notifier\n", __func__);
+	mutex_unlock(&notify_lock);
+}
+EXPORT_SYMBOL_GPL(mmc_force_presence_change);
+
+#ifdef CONFIG_S3C_DEV_HSMMC
+static struct s3c_sdhci_platdata smdk4212_hsmmc0_pdata __initdata = {
+	.cd_type		= S3C_MSHCI_CD_PERMANENT,
+	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
+#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
+	.max_width		= 8,
+	.host_caps		= MMC_CAP_8_BIT_DATA,
+#endif
+};
+#endif
+
+#ifdef CONFIG_S3C_DEV_HSMMC1
+static struct s3c_sdhci_platdata smdk4212_hsmmc1_pdata __initdata = {
+	.cd_type		= S3C_SDHCI_CD_INTERNAL,
+	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+#endif
+
+#ifdef CONFIG_S3C_DEV_HSMMC2
+static struct s3c_sdhci_platdata smdk4212_hsmmc2_pdata __initdata = {
+	.cd_type		= S3C_SDHCI_CD_GPIO,
+	.ext_cd_gpio		= EXYNOS4_GPX3(4),
+	.ext_cd_gpio_invert	= true,
+	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
+	.vmmc_name		= "vtf_2.8v"
+#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
+	.max_width		= 8,
+	.host_caps		= MMC_CAP_8_BIT_DATA,
+#endif
+};
+#endif
+
+#ifdef CONFIG_S3C_DEV_HSMMC3
+static struct s3c_sdhci_platdata smdk4212_hsmmc3_pdata __initdata = {
+/* new code for brm4334 */
+	.cd_type		= S3C_SDHCI_CD_EXTERNAL,
+
+	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
+	.pm_flags = S3C_SDHCI_PM_IGNORE_SUSPEND_RESUME,
+	.ext_cd_init = ext_cd_init_hsmmc3,
+	.ext_cd_cleanup = ext_cd_cleanup_hsmmc3,
+};
+#endif
+
+#ifdef CONFIG_EXYNOS4_DEV_MSHC
+static struct s3c_mshci_platdata exynos4_mshc_pdata __initdata = {
+	.cd_type		= S3C_MSHCI_CD_PERMANENT,
+	.fifo_depth		= 0x80,
+#if defined(CONFIG_EXYNOS4_MSHC_8BIT) && \
+	defined(CONFIG_EXYNOS4_MSHC_DDR)
+	.max_width		= 8,
+	.host_caps		= MMC_CAP_8_BIT_DATA | MMC_CAP_1_8V_DDR |
+				  MMC_CAP_UHS_DDR50 | MMC_CAP_CMD23,
+	.host_caps2		= MMC_CAP2_PACKED_CMD,
+#elif defined(CONFIG_EXYNOS4_MSHC_8BIT)
+	.max_width		= 8,
+	.host_caps		= MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
+#elif defined(CONFIG_EXYNOS4_MSHC_DDR)
+	.host_caps		= MMC_CAP_1_8V_DDR | MMC_CAP_UHS_DDR50 |
+				  MMC_CAP_CMD23,
+#endif
+	.int_power_gpio		= GPIO_eMMC_EN,
+};
+#endif
+
+#ifdef CONFIG_USB_EHCI_S5P
+static struct s5p_ehci_platdata smdk4212_ehci_pdata;
+
+static void __init smdk4212_ehci_init(void)
+{
+	struct s5p_ehci_platdata *pdata = &smdk4212_ehci_pdata;
+
+	s5p_ehci_set_platdata(pdata);
+}
+#endif
+
+#ifdef CONFIG_USB_OHCI_S5P
+static struct s5p_ohci_platdata smdk4212_ohci_pdata;
+
+static void __init smdk4212_ohci_init(void)
+{
+	struct s5p_ohci_platdata *pdata = &smdk4212_ohci_pdata;
+
+	s5p_ohci_set_platdata(pdata);
+}
+#endif
+
+/* USB GADGET */
+#ifdef CONFIG_USB_GADGET
+static struct s5p_usbgadget_platdata smdk4212_usbgadget_pdata;
+
+#include <linux/usb/android_composite.h>
+static void __init smdk4212_usbgadget_init(void)
+{
+	struct s5p_usbgadget_platdata *pdata = &smdk4212_usbgadget_pdata;
+	struct android_usb_platform_data *android_pdata =
+		s3c_device_android_usb.dev.platform_data;
+	if (android_pdata) {
+#if defined(CONFIG_MACH_M0_CTC)
+		/*FOR CTC PC-MODEM START*/
+		unsigned int newluns = 3;
+		/*FOR CTC PC-MODEM END*/
+#else
+		unsigned int newluns = 2;
+#endif
+		printk(KERN_DEBUG "usb: %s: default luns=%d, new luns=%d\n",
+				__func__, android_pdata->nluns, newluns);
+		android_pdata->nluns = newluns;
+	} else {
+		printk(KERN_DEBUG "usb: %s android_pdata is not available\n",
+				__func__);
+	}
+
+	s5p_usbgadget_set_platdata(pdata);
+
+#if defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT) || \
+	defined(CONFIG_MACH_C1_KOR_LGT)
+	pdata = s3c_device_usbgadget.dev.platform_data;
+	if (pdata) {
+		/* Squelch Threshold Tune [13:11] (111 : -20%) */
+		pdata->phy_tune_mask |= (0x7 << 11);
+		pdata->phy_tune |= (0x7 << 11);
+		printk(KERN_DEBUG "usb: %s tune_mask=0x%x, tune=0x%x\n",
+			__func__, pdata->phy_tune_mask, pdata->phy_tune);
+	}
+#endif
+
+}
+#endif
+
+#ifdef CONFIG_MFD_MAX77693
+#ifdef CONFIG_VIBETONZ
+static struct max77693_haptic_platform_data max77693_haptic_pdata = {
+	.max_timeout = 10000,
+	.duty = 37050,
+	.period = 38054,
+	.reg2 = MOTOR_LRA | EXT_PWM | DIVIDER_128,
+	.init_hw = NULL,
+	.motor_en = NULL,
+	.pwm_id = 0,
+	.regulator_name = "vmotor",
+};
+#endif
+
+#ifdef CONFIG_LEDS_MAX77693
+static struct max77693_led_platform_data max77693_led_pdata = {
+	.num_leds = 4,
+
+	.leds[0].name = "leds-sec1",
+	.leds[0].id = MAX77693_FLASH_LED_1,
+	.leds[0].timer = MAX77693_FLASH_TIME_500MS,
+	.leds[0].timer_mode = MAX77693_TIMER_MODE_MAX_TIMER,
+	.leds[0].cntrl_mode = MAX77693_LED_CTRL_BY_FLASHSTB,
+	.leds[0].brightness = 0x1F,
+
+	.leds[1].name = "leds-sec2",
+	.leds[1].id = MAX77693_FLASH_LED_2,
+	.leds[1].timer = MAX77693_FLASH_TIME_500MS,
+	.leds[1].timer_mode = MAX77693_TIMER_MODE_MAX_TIMER,
+	.leds[1].cntrl_mode = MAX77693_LED_CTRL_BY_FLASHSTB,
+	.leds[1].brightness = 0x1F,
+
+	.leds[2].name = "torch-sec1",
+	.leds[2].id = MAX77693_TORCH_LED_1,
+	.leds[2].cntrl_mode = MAX77693_LED_CTRL_BY_FLASHSTB,
+	.leds[2].brightness = 0x0F,
+
+	.leds[3].name = "torch-sec2",
+	.leds[3].id = MAX77693_TORCH_LED_2,
+	.leds[3].cntrl_mode = MAX77693_LED_CTRL_BY_I2C,
+	.leds[3].brightness = 0x0F,
+};
+
+#endif
+
+#ifdef CONFIG_BATTERY_MAX77693_CHARGER
+static struct max77693_charger_platform_data max77693_charger_pdata = {
+#ifdef CONFIG_BATTERY_WPC_CHARGER
+	.wpc_irq_gpio = GPIO_WPC_INT,
+#if defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_C1) || \
+				defined(CONFIG_MACH_C1VZW)
+	.vbus_irq_gpio = GPIO_V_BUS_INT,
+#endif
+	.wc_pwr_det = false,
+#endif
+};
+#endif
+
+extern struct max77693_muic_data max77693_muic;
+extern struct max77693_regulator_data max77693_regulators;
+
+static bool is_muic_default_uart_path_cp(void)
+{
+#if defined(CONFIG_MACH_M0_CTC)
+	return false;
+#endif
+#ifdef CONFIG_MACH_M0
+	if (system_rev == 5)
+		return true;
+#endif
+#ifdef CONFIG_MACH_C1
+	if (system_rev == 4)
+		return true;
+#endif
+#ifdef CONFIG_MACH_S2PLUS
+	if (system_rev >= 2)
+		return true;
+#endif
+	return false;
+}
+
+struct max77693_platform_data exynos4_max77693_info = {
+	.irq_base	= IRQ_BOARD_IFIC_START,
+	.irq_gpio	= GPIO_IF_PMIC_IRQ,
+	.wakeup		= 1,
+	.muic = &max77693_muic,
+	.is_default_uart_path_cp =  is_muic_default_uart_path_cp,
+	.regulators = &max77693_regulators,
+	.num_regulators = MAX77693_REG_MAX,
+#ifdef CONFIG_VIBETONZ
+	.haptic_data = &max77693_haptic_pdata,
+#endif
+#ifdef CONFIG_LEDS_MAX77693
+	.led_data = &max77693_led_pdata,
+#endif
+#ifdef CONFIG_BATTERY_MAX77693_CHARGER
+	.charger_data = &max77693_charger_pdata,
+#endif
+};
+#endif
+
+#if defined(CONFIG_CHARGER_MAX8922_U1) || defined(CONFIG_CHARGER_MAX8922_S2PLUS)
+static int max8922_cfg_gpio(void)
+{
+	printk(KERN_INFO "[Battery] %s called.\n", __func__);
+
+	s3c_gpio_cfgpin(GPIO_CHG_EN, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_CHG_EN, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_CHG_EN, GPIO_LEVEL_LOW);
+
+	s3c_gpio_cfgpin(GPIO_CHG_ING_N, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_CHG_ING_N, S3C_GPIO_PULL_NONE);
+
+	s3c_gpio_cfgpin(GPIO_TA_nCONNECTED, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_TA_nCONNECTED, S3C_GPIO_PULL_NONE);
+
+	return 0;
+}
+
+static struct max8922_platform_data max8922_pdata = {
+	.cfg_gpio = max8922_cfg_gpio,
+	.gpio_chg_en = GPIO_CHG_EN,
+	.gpio_chg_ing = GPIO_CHG_ING_N,
+	.gpio_ta_nconnected = GPIO_TA_nCONNECTED,
+};
+
+static struct platform_device max8922_device_charger = {
+	.name = "max8922-charger",
+	.id = -1,
+	.dev.platform_data = &max8922_pdata,
+};
+#endif /* CONFIG_CHARGER_MAX8922_U1 || CONFIG_CHARGER_MAX8922_S2PLUS */
+
+/* I2C0 */
+static struct i2c_board_info i2c_devs0[] __initdata = {
+};
+
+/* I2C1 */
+static struct i2c_board_info i2c_devs1[] __initdata = {
+};
+
+#ifdef CONFIG_S3C_DEV_I2C4
+#ifdef CONFIG_MFD_MAX77693
+static struct i2c_board_info i2c_devs4_max77693[] __initdata = {
+	{
+		I2C_BOARD_INFO("max77693", (0xCC >> 1)),
+		.platform_data	= &exynos4_max77693_info,
+	}
+};
+#endif
+#endif
+
+#ifdef CONFIG_S3C_DEV_I2C5
+#ifdef CONFIG_MACH_GC1
+static struct i2c_board_info i2c_devs5[] __initdata = {
+	/* HDMI */
+	{
+		I2C_BOARD_INFO("s5p_ddc", (0x74 >> 1)),
+	},
+};
+#else
+static struct i2c_board_info i2c_devs5[] __initdata = {
+#ifdef CONFIG_REGULATOR_MAX8997
+	{
+		I2C_BOARD_INFO("max8997", (0xcc >> 1)),
+		.platform_data = &exynos4_max8997_info,
+	},
+#endif
+
+#if defined(CONFIG_REGULATOR_MAX77686)
+	/* max77686 on i2c5 other than M1 board */
+	{
+		I2C_BOARD_INFO("max77686", (0x12 >> 1)),
+		.platform_data	= &exynos4_max77686_info,
+	},
+#elif defined(CONFIG_REGULATOR_S5M8767)
+	/* s5m on i2c5 other than M1 board */
+	{
+		I2C_BOARD_INFO("s5m87xx", (0x12 >> 1)),
+		.platform_data	= &exynos4_s5m8767_info,
+	},
+#endif
+};
+#endif /* CONFIG_MACH_GC1 */
+#ifdef CONFIG_MACH_GC1
+static void hdmi_ext_ic_control_gc1(bool ic_on)
+{
+	if (ic_on)
+		gpio_set_value(GPIO_HDMI_EN, GPIO_LEVEL_HIGH);
+	else
+		gpio_set_value(GPIO_HDMI_EN, GPIO_LEVEL_LOW);
+}
+
+static void s3c_i2c5_cfg_gpio_gc1(struct platform_device *dev)
+{
+	s3c_gpio_cfgall_range(EXYNOS4_GPB(2), 2,
+		S3C_GPIO_SFN(3), S3C_GPIO_PULL_NONE);
+	s5p_gpio_set_drvstr(EXYNOS4_GPB(2), S5P_GPIO_DRVSTR_LV4);
+	s5p_gpio_set_drvstr(EXYNOS4_GPB(3), S5P_GPIO_DRVSTR_LV4);
+	s3c_gpio_cfgpin(GPIO_HDMI_EN, S3C_GPIO_OUTPUT);	/* HDMI_EN */
+	s3c_gpio_setpull(GPIO_HDMI_EN, S3C_GPIO_PULL_NONE);
+}
+#endif
+struct s3c2410_platform_i2c default_i2c5_data __initdata = {
+	.bus_num        = 5,
+	.flags          = 0,
+	.slave_addr     = 0x10,
+	.frequency      = 100*1000,
+	.sda_delay      = 100,
+#ifdef CONFIG_MACH_GC1
+	.cfg_gpio	= s3c_i2c5_cfg_gpio_gc1,
+#endif
+};
+
+#endif
+
+#ifdef CONFIG_MACH_GC1
+static struct i2c_board_info i2c_devs7[] __initdata = {
+	{
+		I2C_BOARD_INFO("max77686", (0x12 >> 1)),
+		.platform_data	= &exynos4_max77686_info,
+	},
+};
+static struct i2c_board_info i2c_devs7_s5m[] __initdata = {
+	{
+		I2C_BOARD_INFO("s5m87xx", 0xCC >> 1),
+		.platform_data = &exynos4_s5m8767_info,
+	},
+};
+#else
+static struct i2c_board_info i2c_devs7[] __initdata = {
+#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) || \
+	defined(CONFIG_MACH_JENGA) || defined(CONFIG_MACH_S2PLUS) || \
+	defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_M3)
+#if defined(CONFIG_REGULATOR_MAX77686) /* max77686 on i2c7 with M1 board */
+	{
+		I2C_BOARD_INFO("max77686", (0x12 >> 1)),
+		.platform_data	= &exynos4_max77686_info,
+	},
+#endif
+
+#if defined(CONFIG_REGULATOR_S5M8767)
+	{
+		I2C_BOARD_INFO("s5m87xx", 0xCC >> 1),
+		.platform_data = &exynos4_s5m8767_info,
+		.irq	= IRQ_EINT(7),
+	},
+#endif
+#endif
+};
+#endif /* CONFIG_MACH_GC1 */
+
+/* Bluetooth */
+#ifdef CONFIG_BT_BCM4334
+static struct platform_device bcm4334_bluetooth_device = {
+	.name = "bcm4334_bluetooth",
+	.id = -1,
+};
+#endif
+
+#if !defined(CONFIG_MACH_M0_GRANDECTC)
+static struct i2c_gpio_platform_data gpio_i2c_data8 = {
+	.sda_pin = GPIO_3_TOUCH_SDA,
+	.scl_pin = GPIO_3_TOUCH_SCL,
+};
+
+struct platform_device s3c_device_i2c8 = {
+	.name = "i2c-gpio",
+	.id = 8,
+	.dev.platform_data = &gpio_i2c_data8,
+};
+#endif
+
+/* I2C8 */
+static struct i2c_board_info i2c_devs8_emul[] = {
+#ifdef CONFIG_KEYBOARD_CYPRESS_TOUCH
+	{
+		I2C_BOARD_INFO("sec_touchkey", 0x20),
+		.platform_data = &touchkey_pdata,
+	},
+#endif
+};
+
+/* I2C9 */
+static struct i2c_board_info i2c_devs9_emul[] __initdata = {
+};
+
+/* I2C10 */
+static struct i2c_board_info i2c_devs10_emul[] __initdata = {
+};
+
+/* I2C11 */
+static struct i2c_board_info i2c_devs11_emul[] __initdata = {
+};
+
+/* I2C12 */
+#if defined(CONFIG_PN65N_NFC) && !defined(CONFIG_MACH_C1) \
+	&& !defined(CONFIG_MACH_C1VZW) && !defined(CONFIG_MACH_M3)
+static struct i2c_board_info i2c_devs12_emul[] __initdata = {
+};
+#endif
+
+#if defined(CONFIG_MACH_S2PLUS)
+static struct i2c_gpio_platform_data gpio_i2c_data13 = {
+	.sda_pin = GPIO_VT_CAM_SDA_18V,
+	.scl_pin = GPIO_VT_CAM_SCL_18V,
+};
+
+struct platform_device s3c_device_i2c13 = {
+	.name = "i2c-gpio",
+	.id = 13,
+	.dev.platform_data = &gpio_i2c_data13,
+};
+
+/* I2C13 */
+static struct i2c_board_info i2c_devs13_emul[] __initdata = {
+};
+#endif
+
+#ifdef CONFIG_BATTERY_MAX17047_FUELGAUGE
+static struct i2c_gpio_platform_data gpio_i2c_data14 = {
+	.sda_pin = GPIO_FUEL_SDA,
+	.scl_pin = GPIO_FUEL_SCL,
+};
+
+struct platform_device s3c_device_i2c14 = {
+	.name = "i2c-gpio",
+	.id = 14,
+	.dev.platform_data = &gpio_i2c_data14,
+};
+
+static struct max17047_platform_data max17047_pdata = {
+	.irq_gpio = GPIO_FUEL_ALERT,
+};
+
+/* I2C14 */
+static struct i2c_board_info i2c_devs14_emul[] __initdata = {
+	{
+		I2C_BOARD_INFO("max17047-fuelgauge", 0x36),
+		.platform_data = &max17047_pdata,
+	},
+};
+#endif
+
+#if !defined(CONFIG_MACH_M0_GRANDECTC)
+/* I2C15 */
+static struct i2c_gpio_platform_data gpio_i2c_data15 = {
+	.sda_pin = GPIO_MHL_SDA_1_8V,
+	.scl_pin = GPIO_MHL_SCL_1_8V,
+	.udelay = 3,
+	.timeout = 0,
+};
+
+struct platform_device s3c_device_i2c15 = {
+	.name = "i2c-gpio",
+	.id = 15,
+	.dev = {
+		.platform_data = &gpio_i2c_data15,
+	}
+};
+
+static struct i2c_board_info i2c_devs15_emul[] __initdata = {
+};
+
+/* I2C16 */
+static struct i2c_gpio_platform_data gpio_i2c_data16 = {
+	.sda_pin = GPIO_MHL_DSDA_2_8V,
+	.scl_pin = GPIO_MHL_DSCL_2_8V,
+};
+
+struct platform_device s3c_device_i2c16 = {
+	.name = "i2c-gpio",
+	.id = 16,
+	.dev.platform_data = &gpio_i2c_data16,
+};
+
+static struct i2c_board_info i2c_devs16_emul[] __initdata = {
+};
+#endif
+
+#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) || \
+	defined(CONFIG_MACH_JENGA) || defined(CONFIG_MACH_S2PLUS) || \
+	defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_M3) || \
+	defined(CONFIG_MACH_GC1)
+static struct i2c_gpio_platform_data gpio_i2c_data17 = {
+	.sda_pin = GPIO_IF_PMIC_SDA,
+	.scl_pin = GPIO_IF_PMIC_SCL,
+};
+
+struct platform_device s3c_device_i2c17 = {
+	.name = "i2c-gpio",
+	.id = 17,
+	.dev.platform_data = &gpio_i2c_data17,
+};
+
+/* I2C17 */
+static struct i2c_board_info i2c_devs17_emul[] __initdata = {
+#ifdef CONFIG_MFD_MAX77693
+	{
+		I2C_BOARD_INFO("max77693", (0xCC >> 1)),
+		.platform_data	= &exynos4_max77693_info,
+	}
+#endif
+};
+#endif
+
+#if 0
+#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) || \
+	defined(CONFIG_MACH_JENGA) || defined(CONFIG_MACH_S2PLUS) || \
+	defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_M3)
+static struct i2c_gpio_platform_data i2c18_platdata = {
+	.sda_pin		= GPIO_8M_CAM_SDA_18V,
+	.scl_pin		= GPIO_8M_CAM_SCL_18V,
+	.udelay			= 2, /* 250 kHz */
+	.sda_is_open_drain	= 0,
+	.scl_is_open_drain	= 0,
+	.scl_is_output_only = 0,
+};
+
+static struct platform_device s3c_device_i2c18 = {
+	.name	= "i2c-gpio",
+	.id	= 18,
+	.dev.platform_data	= &i2c18_platdata,
+};
+
+/* I2C18 */
+/* No explicit i2c client array here. The channel number 18 is passed
+   to camera driver from midas-camera.c instead. */
+#endif
+#endif
+
+#if defined(CONFIG_STMPE811_ADC) || defined(CONFIG_FM_SI4709_MODULE) \
+	|| defined(CONFIG_FM_SI4705_MODULE)
+static struct i2c_gpio_platform_data gpio_i2c_data19 = {
+	.sda_pin = GPIO_ADC_SDA,
+	.scl_pin = GPIO_ADC_SCL,
+};
+
+struct platform_device s3c_device_i2c19 = {
+	.name = "i2c-gpio",
+	.id = 19,
+	.dev.platform_data = &gpio_i2c_data19,
+};
+
+
+/* I2C19 */
+static struct i2c_board_info i2c_devs19_emul[] __initdata = {
+#if defined(CONFIG_STMPE811_ADC)
+	{
+		I2C_BOARD_INFO("stmpe811-adc", (0x82 >> 1)),
+		.platform_data	= &stmpe811_pdata,
+	},
+#endif
+#ifdef CONFIG_FM_SI4705_MODULE
+	{
+		I2C_BOARD_INFO("Si4709", (0x22 >> 1)),
+	},
+#endif
+#ifdef CONFIG_FM_SI4709_MODULE
+	{
+		I2C_BOARD_INFO("Si4709", (0x20 >> 1)),
+	},
+#endif
+
+};
+#endif
+
+/* I2C21 */
+#ifdef CONFIG_LEDS_AN30259A
+static struct i2c_gpio_platform_data gpio_i2c_data21 = {
+	.scl_pin = GPIO_S_LED_I2C_SCL,
+	.sda_pin = GPIO_S_LED_I2C_SDA,
+};
+
+struct platform_device s3c_device_i2c21 = {
+	.name = "i2c-gpio",
+	.id = 21,
+	.dev.platform_data = &gpio_i2c_data21,
+};
+#endif
+
+/* I2C21 */
+#ifdef CONFIG_LEDS_AN30259A
+static struct i2c_board_info i2c_devs21_emul[] __initdata = {
+	{
+		I2C_BOARD_INFO("an30259a", 0x30),
+	},
+};
+#endif
+
+#ifdef CONFIG_ANDROID_RAM_CONSOLE
+static struct resource ram_console_resource[] = {
+	{
+		.flags = IORESOURCE_MEM,
+	}
+};
+
+static struct platform_device ram_console_device = {
+	.name = "ram_console",
+	.id = -1,
+	.num_resources = ARRAY_SIZE(ram_console_resource),
+	.resource = ram_console_resource,
+};
+
+static int __init setup_ram_console_mem(char *str)
+{
+	unsigned size = memparse(str, &str);
+
+	if (size && (*str == '@')) {
+		unsigned long long base = 0;
+
+		base = simple_strtoul(++str, &str, 0);
+		if (reserve_bootmem(base, size, BOOTMEM_EXCLUSIVE)) {
+			pr_err("%s: failed reserving size %d "
+			       "at base 0x%llx\n", __func__, size, base);
+			return -1;
+		}
+
+		ram_console_resource[0].start = base;
+		ram_console_resource[0].end = base + size - 1;
+		pr_err("%s: %x at %llx\n", __func__, size, base);
+	}
+	return 0;
+}
+
+__setup("ram_console=", setup_ram_console_mem);
+#endif
+
+#if defined(CONFIG_BATTERY_SAMSUNG) || defined(CONFIG_BATTERY_SAMSUNG_S2PLUS)
+static struct samsung_battery_platform_data samsung_battery_pdata = {
+	.charger_name	= "max77693-charger",
+	.fuelgauge_name	= "max17047-fuelgauge",
+#if defined(CONFIG_CHARGER_MAX8922_U1) || defined(CONFIG_CHARGER_MAX8922_S2PLUS)
+	.sub_charger_name   = "max8922-charger",
+#if defined(CONFIG_CHARGER_MAX8922_S2PLUS)
+	.use_sub_charger = true,
+#endif
+#endif
+#if defined(CONFIG_BATTERY_SAMSUNG_S2PLUS)
+	.voltage_max = 4200000,
+#else
+	.voltage_max = 4350000,
+#endif
+	.voltage_min = 3400000,
+
+	.in_curr_limit = 1000,
+#if defined(CONFIG_MACH_GC1)
+	.chg_curr_ta = 700,
+#else
+	.chg_curr_ta = 1000,
+#endif
+	.chg_curr_usb = 475,
+	.chg_curr_cdp = 1000,
+	.chg_curr_wpc = 475,
+	.chg_curr_dock = 1000,
+	.chg_curr_etc = 475,
+
+	.chng_interval = 30,
+	.chng_susp_interval = 60,
+	.norm_interval = 120,
+	.norm_susp_interval = 7200,
+	.emer_lv1_interval = 30,
+	.emer_lv2_interval = 10,
+
+#if defined(CONFIG_BATTERY_SAMSUNG_S2PLUS)
+	.recharge_voltage = 4150000,
+#else
+	.recharge_voltage = 4300000,	/* it will be cacaluated in probe */
+#endif
+
+#if defined(CONFIG_TARGET_LOCALE_KOR) || defined(CONFIG_MACH_M0_CTC)
+	.abstimer_charge_duration = 8 * 60 * 60,
+	.abstimer_recharge_duration = 2 * 60 * 60,
+#else
+	.abstimer_charge_duration = 6 * 60 * 60,
+	.abstimer_recharge_duration = 1.5 * 60 * 60,
+#endif
+
+	.cb_det_src = CABLE_DET_CHARGER,
+#if defined(CONFIG_TARGET_LOCALE_KOR)
+#if defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT)
+	.overheat_stop_temp = 640,
+	.overheat_recovery_temp = 429,
+	.freeze_stop_temp = -70,
+	.freeze_recovery_temp = 8,
+#elif defined(CONFIG_MACH_C1_KOR_LGT)
+	.overheat_stop_temp = 630,
+	.overheat_recovery_temp = 430,
+	.freeze_stop_temp = -50,
+	.freeze_recovery_temp = 0,
+#elif defined(CONFIG_MACH_M0_KOR_SKT) || defined(CONFIG_MACH_M0_KOR_KT)
+	.overheat_stop_temp = 710,
+	.overheat_recovery_temp = 430,
+	.freeze_stop_temp = -40,
+	.freeze_recovery_temp = 30,
+#else
+	.overheat_stop_temp = 600,
+	.overheat_recovery_temp = 430,
+	.freeze_stop_temp = -50,
+	.freeze_recovery_temp = 0,
+#endif /* KOR model */
+#elif defined(CONFIG_MACH_M0_CTC)
+	.overheat_stop_temp = 640,
+	.overheat_recovery_temp = 400,
+	.freeze_stop_temp = -50,
+	.freeze_recovery_temp = 30,
+#else
+	.overheat_stop_temp = 600,
+	.overheat_recovery_temp = 400,
+	.freeze_stop_temp = -50,
+	.freeze_recovery_temp = 0,
+#endif
+
+	.temper_src = TEMPER_AP_ADC,
+	.temper_ch = 2,
+#ifdef CONFIG_S3C_ADC
+	/* s3c adc driver does not convert raw adc data.
+	 * so, register convert function.
+	 */
+	.covert_adc = convert_adc,
+#endif
+
+	.suspend_chging = true,
+
+	.led_indicator = false,
+
+	.battery_standever = false,
+};
+
+static struct platform_device samsung_device_battery = {
+	.name	= "samsung-battery",
+	.id	= -1,
+	.dev.platform_data = &samsung_battery_pdata,
+};
+#endif
+
+#define GPIO_KEYS(_code, _gpio, _active_low, _iswake, _hook)	\
+	{							\
+		.code = _code,					\
+		.gpio = _gpio,					\
+		.active_low = _active_low,			\
+		.type = EV_KEY,					\
+		.wakeup = _iswake,				\
+		.debounce_interval = 10,			\
+		.isr_hook = _hook,				\
+		.value = 1					\
+	}
+
+struct gpio_keys_button midas_buttons[] = {
+#if defined(CONFIG_MACH_GC1)
+	GPIO_KEYS(KEY_POWER, GPIO_nPOWER,
+			1, 1, sec_debug_check_crash_key),
+	GPIO_KEYS(KEY_RECORD, GPIO_RECORD_KEY,
+			1, 1, sec_debug_check_crash_key),
+#if 0
+	GPIO_KEYS(KEY_HOMEPAGE, GPIO_OK_KEY_ANDROID,
+			1, 1, sec_debug_check_crash_key),
+	GPIO_KEYS(KEY_MENU, GPIO_MENU_KEY,
+			1, 1, sec_debug_check_crash_key),
+	GPIO_KEYS(KEY_BACK, GPIO_BACK_KEY,
+			1, 1, sec_debug_check_crash_key),
+#endif
+	GPIO_KEYS(KEY_PLAY, GPIO_PLAY_KEY,
+			1, 1, sec_debug_check_crash_key),
+	GPIO_KEYS(KEY_CAMERA_FOCUS, GPIO_S1_KEY,
+			1, 1, sec_debug_check_crash_key),
+	/*KEY_CAMERA_SHUTTER*/
+	GPIO_KEYS(0x220, GPIO_S2_KEY,
+			1, 1, sec_debug_check_crash_key),
+	GPIO_KEYS(KEY_CAMERA_ZOOMIN, GPIO_TELE_KEY,
+			1, 1, sec_debug_check_crash_key),
+	GPIO_KEYS(KEY_CAMERA_ZOOMOUT, GPIO_WIDE_KEY,
+			1, 1, sec_debug_check_crash_key),
+#else
+	GPIO_KEYS(KEY_VOLUMEUP, GPIO_VOL_UP,
+		  1, 0, sec_debug_check_crash_key),
+	GPIO_KEYS(KEY_VOLUMEDOWN, GPIO_VOL_DOWN,
+		  1, 0, sec_debug_check_crash_key),
+	GPIO_KEYS(KEY_POWER, GPIO_nPOWER,
+		  1, 1, sec_debug_check_crash_key),
+#endif
+};
+
+struct gpio_keys_button m0_buttons[] = {
+	GPIO_KEYS(KEY_VOLUMEUP, GPIO_VOL_UP_00,
+		  1, 0, sec_debug_check_crash_key),
+	GPIO_KEYS(KEY_VOLUMEDOWN, GPIO_VOL_DOWN_00,
+		  1, 0, sec_debug_check_crash_key),
+	GPIO_KEYS(KEY_POWER, GPIO_nPOWER,
+		  1, 1, sec_debug_check_crash_key),
+#if defined(CONFIG_MACH_S2PLUS)
+	GPIO_KEYS(KEY_HOME, GPIO_OK_KEY,
+		  1, 1, sec_debug_check_crash_key),
+#endif
+};
+
+#if defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_C1VZW) || \
+	defined(CONFIG_MACH_C1_USA_ATT)
+struct gpio_keys_button m0_rev11_buttons[] = {
+	GPIO_KEYS(KEY_VOLUMEUP, GPIO_VOL_UP_00,
+		  1, 0, sec_debug_check_crash_key),
+	GPIO_KEYS(KEY_VOLUMEDOWN, GPIO_VOL_DOWN_00,
+		  1, 0, sec_debug_check_crash_key),
+	GPIO_KEYS(KEY_POWER, GPIO_nPOWER,
+		  1, 1, sec_debug_check_crash_key),
+	GPIO_KEYS(KEY_HOMEPAGE, GPIO_OK_KEY_ANDROID,
+		  1, 1, sec_debug_check_crash_key),
+};
+#endif
+
+#if defined(CONFIG_TARGET_LOCALE_KOR)
+struct gpio_keys_button c1_rev04_buttons[] = {
+	GPIO_KEYS(KEY_VOLUMEUP, GPIO_VOL_UP_00,
+		  1, 0, sec_debug_check_crash_key),
+	GPIO_KEYS(KEY_VOLUMEDOWN, GPIO_VOL_DOWN_00,
+		  1, 0, sec_debug_check_crash_key),
+	GPIO_KEYS(KEY_POWER, GPIO_nPOWER,
+		  1, 1, sec_debug_check_crash_key),
+	GPIO_KEYS(KEY_HOMEPAGE, GPIO_OK_KEY_ANDROID,
+		  1, 1, sec_debug_check_crash_key),
+};
+#endif
+
+struct gpio_keys_platform_data midas_gpiokeys_platform_data = {
+	midas_buttons,
+	ARRAY_SIZE(midas_buttons),
+};
+
+static struct platform_device midas_keypad = {
+	.name	= "gpio-keys",
+	.dev	= {
+		.platform_data = &midas_gpiokeys_platform_data,
+	},
+};
+
+#ifdef CONFIG_VIDEO_FIMG2D
+static struct fimg2d_platdata fimg2d_data __initdata = {
+	.hw_ver = 0x41,
+	.parent_clkname = "mout_g2d0",
+	.clkname = "sclk_fimg2d",
+	.gate_clkname = "fimg2d",
+	.clkrate = 199 * 1000000,	/* 160 Mhz */
+};
+#endif
+
+#ifdef CONFIG_EXYNOS_C2C
+struct exynos_c2c_platdata smdk4212_c2c_pdata = {
+	.setup_gpio	= NULL,
+	.shdmem_addr	= C2C_SHAREDMEM_BASE,
+	.shdmem_size	= C2C_MEMSIZE_64,
+	.ap_sscm_addr	= NULL,
+	.cp_sscm_addr	= NULL,
+	.rx_width	= C2C_BUSWIDTH_16,
+	.tx_width	= C2C_BUSWIDTH_16,
+	.clk_opp100	= 400,
+	.clk_opp50	= 266,
+	.clk_opp25	= 0,
+	.default_opp_mode	= C2C_OPP50,
+	.get_c2c_state	= NULL,
+};
+#endif
+/* BUSFREQ to control memory/bus */
+static struct device_domain busfreq;
+
+static struct platform_device exynos4_busfreq = {
+	.id = -1,
+	.name = "exynos-busfreq",
+};
+
+static struct i2c_gpio_platform_data i2c9_platdata = {
+#if defined(CONFIG_SENSORS_CM3663)
+	.sda_pin	= GPIO_PS_ALS_SDA_18V,
+	.scl_pin	= GPIO_PS_ALS_SCL_18V,
+#elif defined(CONFIG_SENSORS_BH1721)
+	.sda_pin	= GPIO_PS_ALS_SDA_28V,
+	.scl_pin	= GPIO_PS_ALS_SCL_28V,
+#elif defined(CONFIG_SENSORS_CM36651)
+	.sda_pin	= GPIO_RGB_SDA_1_8V,
+	.scl_pin	= GPIO_RGB_SCL_1_8V,
+#endif
+	.udelay	= 2, /* 250KHz */
+	.sda_is_open_drain	= 0,
+	.scl_is_open_drain	= 0,
+	.scl_is_output_only = 0,
+};
+
+static struct platform_device s3c_device_i2c9 = {
+	.name	= "i2c-gpio",
+	.id	= 9,
+	.dev.platform_data	= &i2c9_platdata,
+};
+
+#ifdef CONFIG_SENSORS_AK8975C
+static struct i2c_gpio_platform_data i2c10_platdata = {
+	.sda_pin	= GPIO_MSENSOR_SDA_18V,
+	.scl_pin	= GPIO_MSENSOR_SCL_18V,
+	.udelay	= 2, /* 250KHz */
+	.sda_is_open_drain	= 0,
+	.scl_is_open_drain	= 0,
+	.scl_is_output_only = 0,
+};
+
+static struct platform_device s3c_device_i2c10 = {
+	.name	= "i2c-gpio",
+	.id	= 10,
+	.dev.platform_data	= &i2c10_platdata,
+};
+#endif
+
+#ifdef CONFIG_SENSORS_LPS331
+static struct i2c_gpio_platform_data i2c11_platdata = {
+	.sda_pin	= GPIO_BSENSE_SDA_18V,
+	.scl_pin	= GPIO_BENSE_SCL_18V,
+	.udelay	= 2, /* 250KHz */
+	.sda_is_open_drain	= 0,
+	.scl_is_open_drain	= 0,
+	.scl_is_output_only = 0,
+};
+
+static struct platform_device s3c_device_i2c11 = {
+	.name			= "i2c-gpio",
+	.id	= 11,
+	.dev.platform_data	= &i2c11_platdata,
+};
+#endif
+
+#if defined(CONFIG_PN65N_NFC) && !defined(CONFIG_MACH_C1) \
+	&& !defined(CONFIG_MACH_C1VZW) && !defined(CONFIG_MACH_M3)
+static struct i2c_gpio_platform_data i2c12_platdata = {
+	.sda_pin		= GPIO_NFC_SDA_18V,
+	.scl_pin		= GPIO_NFC_SCL_18V,
+	.udelay			= 2, /* 250 kHz */
+	.sda_is_open_drain	= 0,
+	.scl_is_open_drain	= 0,
+	.scl_is_output_only = 0,
+};
+
+static struct platform_device s3c_device_i2c12 = {
+	.name	= "i2c-gpio",
+	.id		= 12,
+	.dev.platform_data	= &i2c12_platdata,
+};
+#endif
+
+#ifdef CONFIG_USB_HOST_NOTIFY
+static void otg_accessory_power(int enable)
+{
+	u8 on = (u8)!!enable;
+
+	/* max77693 otg power control */
+	otg_control(enable);
+
+	gpio_request(GPIO_OTG_EN, "USB_OTG_EN");
+	gpio_direction_output(GPIO_OTG_EN, on);
+	gpio_free(GPIO_OTG_EN);
+	pr_info("%s: otg accessory power = %d\n", __func__, on);
+}
+
+static void otg_accessory_powered_booster(int enable)
+{
+	u8 on = (u8)!!enable;
+
+	/* max77693 powered otg power control */
+	powered_otg_control(enable);
+	pr_info("%s: otg accessory power = %d\n", __func__, on);
+}
+
+static struct host_notifier_platform_data host_notifier_pdata = {
+	.ndev.name	= "usb_otg",
+	.booster	= otg_accessory_power,
+	.powered_booster = otg_accessory_powered_booster,
+	.thread_enable	= 0,
+};
+
+struct platform_device host_notifier_device = {
+	.name = "host_notifier",
+	.dev.platform_data = &host_notifier_pdata,
+};
+#endif
+
+#ifdef CONFIG_SEC_WATCHDOG_RESET
+static struct platform_device watchdog_reset_device = {
+	.name = "watchdog-reset",
+	.id = -1,
+};
+#endif
+
+static struct platform_device *midas_devices[] __initdata = {
+#ifdef CONFIG_SEC_WATCHDOG_RESET
+	&watchdog_reset_device,
+#endif
+#ifdef CONFIG_ANDROID_RAM_CONSOLE
+	&ram_console_device,
+#endif
+	/* Samsung Power Domain */
+	&exynos4_device_pd[PD_MFC],
+	&exynos4_device_pd[PD_G3D],
+	&exynos4_device_pd[PD_LCD0],
+	&exynos4_device_pd[PD_CAM],
+	&exynos4_device_pd[PD_TV],
+	&exynos4_device_pd[PD_GPS],
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_IS
+	&exynos4_device_pd[PD_ISP],
+#endif
+	&exynos4_device_pd[PD_GPS_ALIVE],
+	/* legacy fimd */
+#ifdef CONFIG_FB_S5P
+	&s3c_device_fb,
+#ifdef CONFIG_FB_S5P_LMS501KF03
+	&s3c_device_spi_gpio,
+#endif
+#endif
+
+#ifdef CONFIG_FB_S5P_MDNIE
+	&mdnie_device,
+#endif
+
+#ifdef CONFIG_HAVE_PWM
+	&s3c_device_timer[0],
+	&s3c_device_timer[1],
+	&s3c_device_timer[2],
+	&s3c_device_timer[3],
+#endif
+
+#ifdef CONFIG_SND_SOC_WM8994
+	&vbatt_device,
+#endif
+
+	&s3c_device_wdt,
+	&s3c_device_rtc,
+
+	&s3c_device_i2c0,
+	&s3c_device_i2c1,
+	&s3c_device_i2c3,
+#ifdef CONFIG_S3C_DEV_I2C4
+	&s3c_device_i2c4,
+#endif
+	/* &s3c_device_i2c5, */
+
+#ifdef CONFIG_AUDIENCE_ES305
+	&s3c_device_i2c6,
+#endif
+	&s3c_device_i2c7,
+#if !defined(CONFIG_MACH_M0_GRANDECTC)
+	&s3c_device_i2c8,
+#endif
+	&s3c_device_i2c9,
+#ifdef CONFIG_SENSORS_AK8975C
+	&s3c_device_i2c10,
+#endif
+#ifdef CONFIG_SENSORS_LPS331
+	&s3c_device_i2c11,
+#endif
+	/* &s3c_device_i2c12, */
+#if defined(CONFIG_MACH_S2PLUS)
+	&s3c_device_i2c13,
+#endif
+#ifdef CONFIG_BATTERY_MAX17047_FUELGAUGE
+	&s3c_device_i2c14,	/* max17047-fuelgauge */
+#endif
+
+#ifdef CONFIG_SAMSUNG_MHL
+	&s3c_device_i2c15,
+	&s3c_device_i2c16,
+#endif
+#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) || \
+	defined(CONFIG_MACH_JENGA) || defined(CONFIG_MACH_S2PLUS) || \
+	defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_M3) || \
+	defined(CONFIG_MACH_GC1)
+	&s3c_device_i2c17,
+#if 0
+	&s3c_device_i2c18,
+#endif
+#endif
+#ifdef CONFIG_LEDS_AN30259A
+	&s3c_device_i2c21,
+#endif
+
+#if defined CONFIG_USB_EHCI_S5P && !defined CONFIG_LINK_DEVICE_HSIC
+	&s5p_device_ehci,
+#endif
+#if defined CONFIG_USB_OHCI_S5P && !defined CONFIG_LINK_DEVICE_HSIC
+	&s5p_device_ohci,
+#endif
+#ifdef CONFIG_USB_GADGET
+	&s3c_device_usbgadget,
+#endif
+#ifdef CONFIG_USB_ANDROID_RNDIS
+	&s3c_device_rndis,
+#endif
+#if defined(CONFIG_USB_ANDROID) || defined(CONFIG_USB_G_ANDROID)
+	&s3c_device_android_usb,
+	&s3c_device_usb_mass_storage,
+#endif
+#ifdef CONFIG_EXYNOS4_DEV_MSHC
+	&s3c_device_mshci,
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC
+	&s3c_device_hsmmc0,
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC1
+	&s3c_device_hsmmc1,
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC2
+	&s3c_device_hsmmc2,
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC3
+	&s3c_device_hsmmc3,
+#endif
+
+#ifdef CONFIG_SND_SAMSUNG_AC97
+	&exynos_device_ac97,
+#endif
+#ifdef CONFIG_SND_SAMSUNG_I2S
+	&exynos_device_i2s0,
+#endif
+#ifdef CONFIG_SND_SAMSUNG_PCM
+	&exynos_device_pcm0,
+#endif
+#ifdef CONFIG_SND_SAMSUNG_SPDIF
+	&exynos_device_spdif,
+#endif
+#if defined(CONFIG_SND_SAMSUNG_RP) || defined(CONFIG_SND_SAMSUNG_ALP)
+	&exynos_device_srp,
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_IS
+	&exynos4_device_fimc_is,
+#endif
+#ifdef CONFIG_FB_S5P_LD9040
+	&ld9040_spi_gpio,
+#endif
+#ifdef CONFIG_VIDEO_TVOUT
+	&s5p_device_tvout,
+	&s5p_device_cec,
+	&s5p_device_hpd,
+#endif
+#ifdef CONFIG_FB_S5P_EXTDSP
+	&s3c_device_extdsp,
+#endif
+#ifdef CONFIG_VIDEO_FIMC
+	&s3c_device_fimc0,
+	&s3c_device_fimc1,
+	&s3c_device_fimc2,
+	&s3c_device_fimc3,
+/* CONFIG_VIDEO_SAMSUNG_S5P_FIMC is the feature for mainline */
+#elif defined(CONFIG_VIDEO_SAMSUNG_S5P_FIMC)
+	&s5p_device_fimc0,
+	&s5p_device_fimc1,
+	&s5p_device_fimc2,
+	&s5p_device_fimc3,
+#endif
+#if defined(CONFIG_VIDEO_FIMC_MIPI)
+	&s3c_device_csis0,
+	&s3c_device_csis1,
+#endif
+#if defined(CONFIG_VIDEO_MFC5X) || defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC)
+	&s5p_device_mfc,
+#endif
+#ifdef CONFIG_S5P_SYSTEM_MMU
+	&SYSMMU_PLATDEV(g2d_acp),
+	&SYSMMU_PLATDEV(fimc0),
+	&SYSMMU_PLATDEV(fimc1),
+	&SYSMMU_PLATDEV(fimc2),
+	&SYSMMU_PLATDEV(fimc3),
+	&SYSMMU_PLATDEV(jpeg),
+	&SYSMMU_PLATDEV(mfc_l),
+	&SYSMMU_PLATDEV(mfc_r),
+	&SYSMMU_PLATDEV(tv),
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_IS
+	&SYSMMU_PLATDEV(is_isp),
+	&SYSMMU_PLATDEV(is_drc),
+	&SYSMMU_PLATDEV(is_fd),
+	&SYSMMU_PLATDEV(is_cpu),
+#endif
+#endif
+#ifdef CONFIG_ION_EXYNOS
+	&exynos_device_ion,
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_LITE
+	&exynos_device_flite0,
+	&exynos_device_flite1,
+#endif
+#ifdef CONFIG_VIDEO_FIMG2D
+	&s5p_device_fimg2d,
+#endif
+
+#ifdef CONFIG_VIDEO_JPEG_V2X
+	&s5p_device_jpeg,
+#endif
+	&samsung_asoc_dma,
+#ifndef CONFIG_SND_SOC_SAMSUNG_USE_DMA_WRAPPER
+	&samsung_asoc_idma,
+#endif
+#if defined(CONFIG_CHARGER_MAX8922_U1) || defined(CONFIG_CHARGER_MAX8922_S2PLUS)
+	&max8922_device_charger,
+#endif
+#ifdef CONFIG_EXYNOS_C2C
+	&exynos_device_c2c,
+#endif
+#if defined(CONFIG_S3C64XX_DEV_SPI)
+#if defined(CONFIG_VIDEO_S5C73M3_SPI)
+	&exynos_device_spi1,
+#endif
+#if defined(CONFIG_PHONE_IPC_SPI)
+	&exynos_device_spi2,
+	&ipc_spi_device,
+#elif defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE)
+	&exynos_device_spi2,
+#endif
+#endif
+
+#ifdef CONFIG_BT_BCM4334
+	&bcm4334_bluetooth_device,
+#endif
+#ifdef CONFIG_S5P_DEV_ACE
+	&s5p_device_ace,
+#endif
+	&exynos4_busfreq,
+#ifdef CONFIG_USB_HOST_NOTIFY
+	&host_notifier_device,
+#endif
+#ifdef CONFIG_EXYNOS4_SETUP_THERMAL
+	&s5p_device_tmu,
+#endif
+};
+
+#ifdef CONFIG_EXYNOS4_SETUP_THERMAL
+/* below temperature base on the celcius degree */
+struct s5p_platform_tmu midas_tmu_data __initdata = {
+	.ts = {
+		.stop_1st_throttle  = 78,
+		.start_1st_throttle = 80,
+		.stop_2nd_throttle  = 87,
+		.start_2nd_throttle = 103,
+		.start_tripping	    = 110, /* temp to do tripping */
+		.start_emergency    = 120, /* To protect chip,forcely kernel panic */
+		.stop_mem_throttle  = 80,
+		.start_mem_throttle = 85,
+		.stop_tc  = 13,
+		.start_tc = 10,
+	},
+	.cpufreq = {
+		.limit_1st_throttle  = 800000, /* 800MHz in KHz order */
+		.limit_2nd_throttle  = 200000, /* 200MHz in KHz order */
+	},
+	.temp_compensate = {
+		.arm_volt = 925000, /* vdd_arm in uV for temperature compensation */
+		.bus_volt = 900000, /* vdd_bus in uV for temperature compensation */
+		.g3d_volt = 900000, /* vdd_g3d in uV for temperature compensation */
+	},
+};
+#endif
+
+#if defined CONFIG_USB_OHCI_S5P && defined CONFIG_LINK_DEVICE_HSIC
+static int __init s5p_ohci_device_initcall(void)
+{
+	return platform_device_register(&s5p_device_ohci);
+}
+late_initcall(s5p_ohci_device_initcall);
+#endif
+#if defined CONFIG_USB_EHCI_S5P && defined CONFIG_LINK_DEVICE_HSIC
+static int __init s5p_ehci_device_initcall(void)
+{
+	return platform_device_register(&s5p_device_ehci);
+}
+late_initcall(s5p_ehci_device_initcall);
+#endif
+
+#if defined(CONFIG_VIDEO_TVOUT)
+static struct s5p_platform_hpd hdmi_hpd_data __initdata = {
+#if defined(CONFIG_MACH_GC1) && defined(CONFIG_HDMI_CONTROLLED_BY_EXT_IC)
+	.ext_ic_control = hdmi_ext_ic_control_gc1,
+#endif
+
+};
+static struct s5p_platform_cec hdmi_cec_data __initdata = {
+
+};
+#endif
+
+#if defined(CONFIG_CMA)
+static void __init exynos4_reserve_mem(void)
+{
+	static struct cma_region regions[] = {
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_IS
+		{
+			.name = "fimc_is",
+			.size = CONFIG_VIDEO_EXYNOS_MEMSIZE_FIMC_IS * SZ_1K,
+			{
+				.alignment = 1 << 26,
+			},
+			.start = 0
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMD
+		{
+			.name = "fimd",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMD * SZ_1K,
+			{
+				.alignment = 1 << 20,
+			},
+			.start = 0
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC0
+		{
+			.name = "fimc0",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC0 * SZ_1K,
+			.start = 0
+		},
+#endif
+#if !defined(CONFIG_EXYNOS_CONTENT_PATH_PROTECTION) && \
+	defined(CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC0)
+		{
+			.name = "mfc0",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC0 * SZ_1K,
+			{
+				.alignment = 1 << 17,
+			},
+			.start = 0,
+		},
+#endif
+#if !defined(CONFIG_EXYNOS_CONTENT_PATH_PROTECTION) && \
+	defined(CONFIG_ION_EXYNOS_CONTIGHEAP_SIZE)
+		{
+			.name	= "ion",
+			.size	= CONFIG_ION_EXYNOS_CONTIGHEAP_SIZE * SZ_1K,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC
+		{
+			.name = "mfc",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC * SZ_1K,
+			{
+				.alignment = 1 << 17,
+			},
+			.start = 0
+		},
+#endif
+#if !defined(CONFIG_EXYNOS_CONTENT_PATH_PROTECTION) && \
+	defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC)
+		{
+			.name		= "b2",
+			.size		= 32 << 20,
+			{ .alignment	= 128 << 10 },
+		},
+		{
+			.name		= "b1",
+			.size		= 32 << 20,
+			{ .alignment	= 128 << 10 },
+		},
+		{
+			.name		= "fw",
+			.size		= 1 << 20,
+			{ .alignment	= 128 << 10 },
+		},
+#endif
+#ifdef CONFIG_AUDIO_SAMSUNG_MEMSIZE_SRP
+		{
+			.name = "srp",
+			.size = CONFIG_AUDIO_SAMSUNG_MEMSIZE_SRP * SZ_1K,
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMG2D
+		{
+			.name = "fimg2d",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMG2D * SZ_1K,
+			.start = 0
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC1
+		{
+			.name = "fimc1",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC1 * SZ_1K,
+			.start = 0x65c00000,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC1
+		{
+			.name = "mfc1",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC1 * SZ_1K,
+			{
+				.alignment = 1 << 26,
+			},
+			.start = 0x64000000,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC_NORMAL
+		{
+			.name = "mfc-normal",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC_NORMAL * SZ_1K,
+			.start = 0x64000000,
+		},
+#endif
+		{
+			.size = 0
+		},
+	};
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+	static struct cma_region regions_secure[] = {
+#ifdef CONFIG_ION_EXYNOS_CONTIGHEAP_SIZE
+		{
+			.name	= "ion",
+			.size	= CONFIG_ION_EXYNOS_CONTIGHEAP_SIZE * SZ_1K,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC_SECURE
+		{
+			.name = "mfc-secure",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC_SECURE * SZ_1K,
+		},
+#endif
+		{
+			.name = "sectbl",
+			.size = SZ_1M,
+		},
+		{
+			.size = 0
+		},
+	};
+#else /* !CONFIG_EXYNOS_CONTENT_PATH_PROTECTION */
+	struct cma_region *regions_secure = NULL;
+#endif
+
+	static const char map[] __initconst =
+#ifdef CONFIG_EXYNOS_C2C
+		"samsung-c2c=c2c_shdmem;"
+#endif
+		"s3cfb.0=fimd;exynos4-fb.0=fimd;"
+		"s3c-fimc.0=fimc0;s3c-fimc.1=fimc1;s3c-fimc.2=fimc2;s3c-fimc.3=fimc3;"
+		"exynos4210-fimc.0=fimc0;exynos4210-fimc.1=fimc1;exynos4210-fimc.2=fimc2;exynos4210-fimc.3=fimc3;"
+#ifdef CONFIG_ION_EXYNOS
+		"ion-exynos=ion;"
+#endif
+#ifdef CONFIG_VIDEO_MFC5X
+		"s3c-mfc/A=mfc0,mfc-secure;"
+		"s3c-mfc/B=mfc1,mfc-normal;"
+		"s3c-mfc/AB=mfc;"
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_S5P_MFC
+		"s5p-mfc/f=fw;"
+		"s5p-mfc/a=b1;"
+		"s5p-mfc/b=b2;"
+#endif
+		"samsung-rp=srp;"
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_IS
+		"exynos4-fimc-is=fimc_is;"
+#endif
+		"s5p-fimg2d=fimg2d;"
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+		"s5p-smem/sectbl=sectbl;"
+#endif
+		"s5p-smem/mfc=mfc-secure;"
+		"s5p-smem/fimc=ion;"
+		"s5p-smem/mfc-shm=mfc-normal;"
+		"s5p-smem/fimd=fimd;";
+
+		s5p_cma_region_reserve(regions, regions_secure, 0, map);
+}
+#else
+static inline void exynos4_reserve_mem(void)
+{
+}
+#endif
+
+#ifdef CONFIG_BACKLIGHT_PWM
+/* LCD Backlight data */
+static struct samsung_bl_gpio_info smdk4212_bl_gpio_info = {
+	.no = EXYNOS4_GPD0(1),
+	.func = S3C_GPIO_SFN(2),
+};
+
+static struct platform_pwm_backlight_data smdk4212_bl_data = {
+	.pwm_id = 1,
+#ifdef CONFIG_FB_S5P_LMS501KF03
+	.pwm_period_ns = 1000,
+#endif
+};
+#endif
+
+static void __init midas_map_io(void)
+{
+	clk_xusbxti.rate = 24000000;
+	s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+	s3c24xx_init_clocks(24000000);
+	s3c24xx_init_uarts(smdk4212_uartcfgs, ARRAY_SIZE(smdk4212_uartcfgs));
+
+#if defined(CONFIG_S5P_MEM_CMA)
+	exynos4_reserve_mem();
+#endif
+
+	/* as soon as INFORM6 is visible, sec_debug is ready to run */
+	sec_debug_init();
+}
+
+static void __init exynos_sysmmu_init(void)
+{
+	ASSIGN_SYSMMU_POWERDOMAIN(fimc0, &exynos4_device_pd[PD_CAM].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(fimc1, &exynos4_device_pd[PD_CAM].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(fimc2, &exynos4_device_pd[PD_CAM].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(fimc3, &exynos4_device_pd[PD_CAM].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(jpeg, &exynos4_device_pd[PD_CAM].dev);
+
+#if defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC) || defined(CONFIG_VIDEO_MFC5X)
+	ASSIGN_SYSMMU_POWERDOMAIN(mfc_l, &exynos4_device_pd[PD_MFC].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(mfc_r, &exynos4_device_pd[PD_MFC].dev);
+#endif
+	ASSIGN_SYSMMU_POWERDOMAIN(tv, &exynos4_device_pd[PD_TV].dev);
+#ifdef CONFIG_VIDEO_FIMG2D
+	sysmmu_set_owner(&SYSMMU_PLATDEV(g2d_acp).dev, &s5p_device_fimg2d.dev);
+#endif
+#ifdef CONFIG_VIDEO_MFC5X
+	sysmmu_set_owner(&SYSMMU_PLATDEV(mfc_l).dev, &s5p_device_mfc.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(mfc_r).dev, &s5p_device_mfc.dev);
+#endif
+#ifdef CONFIG_VIDEO_FIMC
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc0).dev, &s3c_device_fimc0.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc1).dev, &s3c_device_fimc1.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc2).dev, &s3c_device_fimc2.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc3).dev, &s3c_device_fimc3.dev);
+#endif
+#ifdef CONFIG_VIDEO_TVOUT
+	sysmmu_set_owner(&SYSMMU_PLATDEV(tv).dev, &s5p_device_tvout.dev);
+#endif
+#ifdef CONFIG_VIDEO_JPEG_V2X
+	sysmmu_set_owner(&SYSMMU_PLATDEV(jpeg).dev, &s5p_device_jpeg.dev);
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_IS
+	ASSIGN_SYSMMU_POWERDOMAIN(is_isp, &exynos4_device_pd[PD_ISP].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(is_drc, &exynos4_device_pd[PD_ISP].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(is_fd, &exynos4_device_pd[PD_ISP].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(is_cpu, &exynos4_device_pd[PD_ISP].dev);
+
+	sysmmu_set_owner(&SYSMMU_PLATDEV(is_isp).dev,
+		&exynos4_device_fimc_is.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(is_drc).dev,
+		&exynos4_device_fimc_is.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(is_fd).dev,
+		&exynos4_device_fimc_is.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(is_cpu).dev,
+		&exynos4_device_fimc_is.dev);
+#endif
+}
+
+#ifdef CONFIG_FB_S5P_EXTDSP
+struct platform_device s3c_device_extdsp = {
+	.name		= "s3cfb_extdsp",
+	.id		= 0,
+};
+
+static struct s3cfb_extdsp_lcd dummy_buffer = {
+	.width = 1920,
+	.height = 1080,
+	.bpp = 16,
+};
+
+static struct s3c_platform_fb default_extdsp_data __initdata = {
+	.hw_ver		= 0x70,
+	.nr_wins	= 1,
+	.default_win	= 0,
+	.swap		= FB_SWAP_WORD | FB_SWAP_HWORD,
+	.lcd		= &dummy_buffer
+};
+
+void __init s3cfb_extdsp_set_platdata(struct s3c_platform_fb *pd)
+{
+	struct s3c_platform_fb *npd;
+	int i;
+
+	if (!pd)
+		pd = &default_extdsp_data;
+
+	npd = kmemdup(pd, sizeof(struct s3c_platform_fb), GFP_KERNEL);
+	if (!npd)
+		printk(KERN_ERR "%s: no memory for platform data\n", __func__);
+	else {
+		for (i = 0; i < npd->nr_wins; i++)
+			npd->nr_buffers[i] = 1;
+		s3c_device_extdsp.dev.platform_data = npd;
+	}
+}
+#endif
+
+static inline int need_i2c5(void)
+{
+#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) || \
+	defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_M3)
+	return system_rev != 3;
+#elif defined(CONFIG_MACH_JENGA)
+	return 0;
+#else
+	return 1;
+#endif
+}
+
+static void __init midas_machine_init(void)
+{
+	struct clk *ppmu_clk = NULL;
+
+#if defined(CONFIG_S3C64XX_DEV_SPI)
+#if defined(CONFIG_VIDEO_S5C73M3_SPI)
+	unsigned int gpio;
+	struct clk *sclk = NULL;
+	struct clk *prnt = NULL;
+	struct device *spi1_dev = &exynos_device_spi1.dev;
+#endif
+#if defined(CONFIG_PHONE_IPC_SPI) \
+	|| defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE)
+	struct device *spi2_dev = &exynos_device_spi2.dev;
+#endif
+#endif
+
+	/*
+	  * prevent 4x12 ISP power off problem
+	  * ISP_SYS Register has to be 0 before ISP block power off.
+	  */
+	__raw_writel(0x0, S5P_CMU_RESET_ISP_SYS);
+
+	/* initialise the gpios */
+	midas_config_gpio_table();
+	exynos4_sleep_gpio_table_set = midas_config_sleep_gpio_table;
+
+	midas_power_init();
+
+	s3c_i2c0_set_platdata(NULL);
+	i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
+
+	s3c_i2c1_set_platdata(NULL);
+	i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
+
+	s3c_i2c3_set_platdata(NULL);
+	midas_tsp_init();
+#ifndef CONFIG_TOUCHSCREEN_MELFAS_GC
+#if !defined(CONFIG_MACH_M0_GRANDECTC)
+	midas_tsp_set_lcdtype(lcdtype);
+#endif
+#endif
+
+#ifdef CONFIG_LEDS_AAT1290A
+	platform_device_register(&s3c_device_aat1290a_led);
+#endif
+
+#ifdef CONFIG_S3C_DEV_I2C4
+#ifdef CONFIG_MACH_MIDAS_02_BD
+	s3c_i2c4_set_platdata(NULL);
+	i2c_register_board_info(4, i2c_devs4_max77693,
+		ARRAY_SIZE(i2c_devs4_max77693));
+#else
+	s3c_i2c4_set_platdata(NULL);
+	if (!(system_rev != 3 && system_rev >= 0)) {
+		i2c_register_board_info(4, i2c_devs4_max77693,
+			ARRAY_SIZE(i2c_devs4_max77693));
+	}
+#endif
+#endif
+	midas_sound_init();
+
+#ifdef CONFIG_S3C_DEV_I2C5
+	if (need_i2c5()) {
+		s3c_i2c5_set_platdata(&default_i2c5_data);
+		i2c_register_board_info(5, i2c_devs5,
+			ARRAY_SIZE(i2c_devs5));
+	}
+#endif
+
+#ifdef CONFIG_MACH_GC1
+	s3c_i2c7_set_platdata(NULL);
+	if (system_rev < 1) {
+		i2c_register_board_info(7, i2c_devs7, ARRAY_SIZE(i2c_devs7));
+	} else {
+		i2c_register_board_info(7, i2c_devs7_s5m,
+						ARRAY_SIZE(i2c_devs7_s5m));
+	}
+#else
+	s3c_i2c7_set_platdata(NULL);
+	i2c_register_board_info(7, i2c_devs7, ARRAY_SIZE(i2c_devs7));
+#endif
+#ifdef CONFIG_KEYBOARD_CYPRESS_TOUCH
+	touchkey_init_hw();
+#endif
+	i2c_register_board_info(8, i2c_devs8_emul, ARRAY_SIZE(i2c_devs8_emul));
+
+#ifndef CONFIG_LEDS_AAT1290A
+	gpio_request(GPIO_3_TOUCH_INT, "3_TOUCH_INT");
+	s5p_register_gpio_interrupt(GPIO_3_TOUCH_INT);
+#endif
+
+	i2c_register_board_info(9, i2c_devs9_emul, ARRAY_SIZE(i2c_devs9_emul));
+
+	i2c_register_board_info(10, i2c_devs10_emul,
+				ARRAY_SIZE(i2c_devs10_emul));
+
+	i2c_register_board_info(11, i2c_devs11_emul,
+				ARRAY_SIZE(i2c_devs11_emul));
+
+#if defined(CONFIG_PN65N_NFC) && !defined(CONFIG_MACH_C1) \
+	&& !defined(CONFIG_MACH_C1VZW) && !defined(CONFIG_MACH_M3)
+	i2c_register_board_info(12, i2c_devs12_emul,
+				ARRAY_SIZE(i2c_devs12_emul));
+#endif
+
+#if defined(CONFIG_MACH_S2PLUS)
+	i2c_register_board_info(13, i2c_devs13_emul,
+				ARRAY_SIZE(i2c_devs13_emul));
+#endif
+
+#ifdef CONFIG_BATTERY_MAX17047_FUELGAUGE
+	/* max17047 fuel gauge */
+	i2c_register_board_info(14, i2c_devs14_emul,
+				ARRAY_SIZE(i2c_devs14_emul));
+#endif
+#ifdef CONFIG_SAMSUNG_MHL
+	printk(KERN_INFO "%s() register sii9234 driver\n", __func__);
+
+	i2c_register_board_info(15, i2c_devs15_emul,
+				ARRAY_SIZE(i2c_devs15_emul));
+	i2c_register_board_info(16, i2c_devs16_emul,
+				ARRAY_SIZE(i2c_devs16_emul));
+#endif
+#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) || \
+	defined(CONFIG_MACH_JENGA) || defined(CONFIG_MACH_S2PLUS) || \
+	defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_M3) || \
+	defined(CONFIG_MACH_GC1)
+	i2c_register_board_info(17, i2c_devs17_emul,
+				ARRAY_SIZE(i2c_devs17_emul));
+#endif
+#if defined(CONFIG_STMPE811_ADC) || defined(CONFIG_FM_SI4709_MODULE) \
+	|| defined(CONFIG_FM_SI4705_MODULE)
+	i2c_register_board_info(19, i2c_devs19_emul,
+				ARRAY_SIZE(i2c_devs19_emul));
+#endif
+
+#ifdef CONFIG_LEDS_AN30259A
+	i2c_register_board_info(21, i2c_devs21_emul,
+				ARRAY_SIZE(i2c_devs21_emul));
+#endif
+
+#if defined(GPIO_OLED_DET)
+	gpio_request(GPIO_OLED_DET, "OLED_DET");
+	s5p_register_gpio_interrupt(GPIO_OLED_DET);
+	gpio_free(GPIO_OLED_DET);
+#endif
+
+#ifdef CONFIG_FB_S5P
+#ifdef CONFIG_FB_S5P_LMS501KF03
+	spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
+	s3cfb_set_platdata(&lms501kf03_data);
+#endif
+#if defined(CONFIG_FB_S5P_MIPI_DSIM)
+	mipi_fb_init();
+#elif defined(CONFIG_FB_S5P_LD9040)
+	ld9040_fb_init();
+#elif defined(CONFIG_BACKLIGHT_PWM)
+	samsung_bl_set(&smdk4212_bl_gpio_info, &smdk4212_bl_data);
+#endif
+	s3cfb_set_platdata(&fb_platform_data);
+
+#ifdef CONFIG_EXYNOS_DEV_PD
+	s3c_device_fb.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
+#endif
+#endif
+#ifdef CONFIG_USB_EHCI_S5P
+	smdk4212_ehci_init();
+#endif
+#ifdef CONFIG_USB_OHCI_S5P
+	smdk4212_ohci_init();
+#endif
+#ifdef CONFIG_USB_GADGET
+	smdk4212_usbgadget_init();
+#endif
+
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_IS
+	exynos4_fimc_is_set_platdata(NULL);
+#ifdef CONFIG_EXYNOS_DEV_PD
+	exynos4_device_fimc_is.dev.parent = &exynos4_device_pd[PD_ISP].dev;
+#endif
+#endif
+#ifdef CONFIG_EXYNOS4_DEV_MSHC
+	s3c_mshci_set_platdata(&exynos4_mshc_pdata);
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC
+	s3c_sdhci0_set_platdata(&smdk4212_hsmmc0_pdata);
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC1
+	s3c_sdhci1_set_platdata(&smdk4212_hsmmc1_pdata);
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC2
+	s3c_sdhci2_set_platdata(&smdk4212_hsmmc2_pdata);
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC3
+	s3c_sdhci3_set_platdata(&smdk4212_hsmmc3_pdata);
+#endif
+
+	midas_camera_init();
+
+#ifdef CONFIG_FB_S5P_EXTDSP
+	s3cfb_extdsp_set_platdata(&default_extdsp_data);
+#endif
+
+#if defined(CONFIG_VIDEO_TVOUT)
+	s5p_hdmi_hpd_set_platdata(&hdmi_hpd_data);
+	s5p_hdmi_cec_set_platdata(&hdmi_cec_data);
+#ifdef CONFIG_EXYNOS_DEV_PD
+	s5p_device_tvout.dev.parent = &exynos4_device_pd[PD_TV].dev;
+	exynos4_device_pd[PD_TV].dev.parent = &exynos4_device_pd[PD_LCD0].dev;
+#endif
+#endif
+
+#ifdef CONFIG_VIDEO_JPEG_V2X
+#ifdef CONFIG_EXYNOS_DEV_PD
+	s5p_device_jpeg.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+	exynos4_jpeg_setup_clock(&s5p_device_jpeg.dev, 160000000);
+#endif
+#endif
+
+#ifdef CONFIG_ION_EXYNOS
+	exynos_ion_set_platdata();
+#endif
+
+#if defined(CONFIG_VIDEO_MFC5X) || defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC)
+#ifdef CONFIG_EXYNOS_DEV_PD
+	s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
+#endif
+	exynos4_mfc_setup_clock(&s5p_device_mfc.dev, 200 * MHZ);
+#endif
+
+#if defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC)
+	dev_set_name(&s5p_device_mfc.dev, "s3c-mfc");
+	clk_add_alias("mfc", "s5p-mfc", "mfc", &s5p_device_mfc.dev);
+	s5p_mfc_setname(&s5p_device_mfc, "s5p-mfc");
+#endif
+#ifdef CONFIG_VIDEO_FIMG2D
+	s5p_fimg2d_set_platdata(&fimg2d_data);
+#endif
+#ifdef CONFIG_EXYNOS_C2C
+	exynos_c2c_set_platdata(&smdk4212_c2c_pdata);
+#endif
+
+	brcm_wlan_init();
+
+#ifdef CONFIG_EXYNOS4_SETUP_THERMAL
+	s5p_tmu_set_platdata(&midas_tmu_data);
+#endif
+
+	exynos_sysmmu_init();
+
+	platform_add_devices(midas_devices, ARRAY_SIZE(midas_devices));
+
+#ifdef CONFIG_S3C_ADC
+#if defined(CONFIG_MACH_S2PLUS)
+	platform_device_register(&s3c_device_adc);
+#else
+	if (system_rev != 3)
+		platform_device_register(&s3c_device_adc);
+#endif
+#endif
+#if defined(CONFIG_STMPE811_ADC) || defined(CONFIG_FM_SI4709_MODULE) \
+	|| defined(CONFIG_FM_SI4705_MODULE)
+	platform_device_register(&s3c_device_i2c19);
+#endif
+#if defined(CONFIG_BATTERY_SAMSUNG) || defined(CONFIG_BATTERY_SAMSUNG_S2PLUS)
+	platform_device_register(&samsung_device_battery);
+#endif
+#ifdef CONFIG_SEC_THERMISTOR
+	platform_device_register(&sec_device_thermistor);
+#endif
+#if defined(CONFIG_MACH_M0_CTC)
+	midas_gpiokeys_platform_data.buttons = m0_buttons;
+	midas_gpiokeys_platform_data.nbuttons = ARRAY_SIZE(m0_buttons);
+#elif defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) || \
+	defined(CONFIG_MACH_JENGA) || defined(CONFIG_MACH_S2PLUS) || \
+	defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_M3)
+	if (system_rev != 3 && system_rev >= 1) {
+		midas_gpiokeys_platform_data.buttons = m0_buttons;
+		midas_gpiokeys_platform_data.nbuttons = ARRAY_SIZE(m0_buttons);
+	}
+#endif
+	/* Above logic is too complex. Let's override whatever the
+	   result is... */
+
+#if defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_C1VZW)
+#if defined(CONFIG_MACH_M0_CHNOPEN) || defined(CONFIG_MACH_M0_HKTW)
+	{
+#else
+	if (system_rev >= 11) {
+#endif
+		s3c_gpio_setpull(GPIO_OK_KEY_ANDROID, S3C_GPIO_PULL_NONE);
+		midas_gpiokeys_platform_data.buttons = m0_rev11_buttons;
+		midas_gpiokeys_platform_data.nbuttons =
+			ARRAY_SIZE(m0_rev11_buttons);
+	}
+#elif defined(CONFIG_TARGET_LOCALE_KOR)
+		s3c_gpio_setpull(GPIO_OK_KEY_ANDROID, S3C_GPIO_PULL_NONE);
+		midas_gpiokeys_platform_data.buttons = c1_rev04_buttons;
+		midas_gpiokeys_platform_data.nbuttons =
+			ARRAY_SIZE(c1_rev04_buttons);
+
+#elif defined(CONFIG_MACH_C1_USA_ATT)
+	if (system_rev >= 7) {
+		s3c_gpio_setpull(GPIO_OK_KEY_ANDROID, S3C_GPIO_PULL_UP);
+		midas_gpiokeys_platform_data.buttons = m0_rev11_buttons;
+		midas_gpiokeys_platform_data.nbuttons =
+			ARRAY_SIZE(m0_rev11_buttons);
+	}
+#endif
+
+	platform_device_register(&midas_keypad);
+#ifdef CONFIG_MACH_GC1
+	gpio_direction_output(GPIO_TOP_PCB_PWREN, 1);
+#endif
+
+#if defined(CONFIG_S3C_DEV_I2C5)
+	if (need_i2c5())
+		platform_device_register(&s3c_device_i2c5);
+#endif
+
+#if defined(CONFIG_PN65N_NFC) && !defined(CONFIG_MACH_C1) \
+	&& !defined(CONFIG_MACH_C1VZW) && !defined(CONFIG_MACH_M3)
+	platform_device_register(&s3c_device_i2c12);
+#endif
+
+#if defined(CONFIG_S3C64XX_DEV_SPI)
+#if defined(CONFIG_VIDEO_S5C73M3_SPI)
+	sclk = clk_get(spi1_dev, "dout_spi1");
+	if (IS_ERR(sclk))
+		dev_err(spi1_dev, "failed to get sclk for SPI-1\n");
+	prnt = clk_get(spi1_dev, "mout_mpll_user");
+	if (IS_ERR(prnt))
+		dev_err(spi1_dev, "failed to get prnt\n");
+	if (clk_set_parent(sclk, prnt))
+		printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
+		       prnt->name, sclk->name);
+
+	clk_set_rate(sclk, 88 * 1000 * 1000);
+	clk_put(sclk);
+	clk_put(prnt);
+
+	if (!gpio_request(EXYNOS4_GPB(5), "SPI_CS1")) {
+		gpio_direction_output(EXYNOS4_GPB(5), 1);
+		s3c_gpio_cfgpin(EXYNOS4_GPB(5), S3C_GPIO_SFN(1));
+		s3c_gpio_setpull(EXYNOS4_GPB(5), S3C_GPIO_PULL_UP);
+		exynos_spi_set_info(1, EXYNOS_SPI_SRCCLK_SCLK,
+				    ARRAY_SIZE(spi1_csi));
+	}
+
+	for (gpio = EXYNOS4_GPB(4); gpio < EXYNOS4_GPB(8); gpio++)
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV3);
+
+	spi_register_board_info(spi1_board_info, ARRAY_SIZE(spi1_board_info));
+#endif
+
+#if defined(CONFIG_PHONE_IPC_SPI) \
+	|| defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE)
+	sclk = NULL;
+	prnt = NULL;
+
+	sclk = clk_get(spi2_dev, "dout_spi2");
+	if (IS_ERR(sclk))
+		dev_err(spi2_dev, "failed to get sclk for SPI-2\n");
+	prnt = clk_get(spi2_dev, "mout_mpll_user");
+	if (IS_ERR(prnt))
+		dev_err(spi2_dev, "failed to get prnt\n");
+	if (clk_set_parent(sclk, prnt))
+		printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
+		       prnt->name, sclk->name);
+
+	clk_put(sclk);
+	clk_put(prnt);
+
+	if (!gpio_request(EXYNOS4_GPC1(2), "SPI_CS2")) {
+		gpio_direction_output(EXYNOS4_GPC1(2), 1);
+		s3c_gpio_cfgpin(EXYNOS4_GPC1(2), S3C_GPIO_SFN(1));
+		s3c_gpio_setpull(EXYNOS4_GPC1(2), S3C_GPIO_PULL_UP);
+		exynos_spi_set_info(2, EXYNOS_SPI_SRCCLK_SCLK,
+			ARRAY_SIZE(spi2_csi));
+	}
+	for (gpio = EXYNOS4_GPC1(1); gpio < EXYNOS4_GPC1(5); gpio++)
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV3);
+
+	spi_register_board_info(spi2_board_info, ARRAY_SIZE(spi2_board_info));
+#endif
+
+#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE)
+	tdmb_dev_init();
+#endif
+#endif
+
+#ifdef CONFIG_BUSFREQ_OPP
+	dev_add(&busfreq, &exynos4_busfreq.dev);
+
+	/* PPMUs using for cpufreq get clk from clk_list */
+	ppmu_clk = clk_get(NULL, "ppmudmc0");
+	if (IS_ERR(ppmu_clk))
+		printk(KERN_ERR "failed to get ppmu_dmc0\n");
+	clk_enable(ppmu_clk);
+	clk_put(ppmu_clk);
+
+	ppmu_clk = clk_get(NULL, "ppmudmc1");
+	if (IS_ERR(ppmu_clk))
+		printk(KERN_ERR "failed to get ppmu_dmc1\n");
+	clk_enable(ppmu_clk);
+	clk_put(ppmu_clk);
+
+	ppmu_clk = clk_get(NULL, "ppmucpu");
+	if (IS_ERR(ppmu_clk))
+		printk(KERN_ERR "failed to get ppmu_cpu\n");
+	clk_enable(ppmu_clk);
+	clk_put(ppmu_clk);
+
+	ppmu_init(&exynos_ppmu[PPMU_DMC0], &exynos4_busfreq.dev);
+	ppmu_init(&exynos_ppmu[PPMU_DMC1], &exynos4_busfreq.dev);
+	ppmu_init(&exynos_ppmu[PPMU_CPU], &exynos4_busfreq.dev);
+#endif
+
+
+	/* 400 kHz for initialization of MMC Card  */
+	__raw_writel((__raw_readl(EXYNOS4_CLKDIV_FSYS3) & 0xfffffff0)
+		     | 0x9, EXYNOS4_CLKDIV_FSYS3);
+#if defined(CONFIG_MACH_M0) && defined(CONFIG_TARGET_LOCALE_EUR)
+	__raw_writel((__raw_readl(EXYNOS4_CLKDIV_FSYS2) & 0x00f0fff0)
+		     | 0x10008, EXYNOS4_CLKDIV_FSYS2);
+#else
+	__raw_writel((__raw_readl(EXYNOS4_CLKDIV_FSYS2) & 0xfff0fff0)
+		     | 0x80008, EXYNOS4_CLKDIV_FSYS2);
+#endif
+	__raw_writel((__raw_readl(EXYNOS4_CLKDIV_FSYS1) & 0xfff0fff0)
+		     | 0x80008, EXYNOS4_CLKDIV_FSYS1);
+}
+
+#ifdef CONFIG_EXYNOS_C2C
+static void __init exynos_c2c_reserve(void)
+{
+	static struct cma_region region = {
+			.name = "c2c_shdmem",
+			.size = 64 * SZ_1M,
+			{ .alignment	= 64 * SZ_1M },
+			.start = C2C_SHAREDMEM_BASE
+	};
+
+	BUG_ON(cma_early_region_register(&region));
+	BUG_ON(cma_early_region_reserve(&region));
+
+	pr_info("%s %10s %8x %8x\n", __func__,
+		region.name, region.start, region.size);
+}
+#endif
+
+static void __init exynos_init_reserve(void)
+{
+	sec_debug_magic_init();
+}
+
+MACHINE_START(SMDK4412, "SMDK4x12")
+	.boot_params	= S5P_PA_SDRAM + 0x100,
+	.init_irq	= exynos4_init_irq,
+	.map_io		= midas_map_io,
+	.init_machine	= midas_machine_init,
+	.timer		= &exynos4_timer,
+#ifdef CONFIG_EXYNOS_C2C
+	.reserve	= &exynos_c2c_reserve,
+#endif
+	.init_early	= &exynos_init_reserve,
+MACHINE_END
+
+MACHINE_START(SMDK4212, "SMDK4x12")
+	.boot_params	= S5P_PA_SDRAM + 0x100,
+	.init_irq	= exynos4_init_irq,
+	.map_io		= midas_map_io,
+	.init_machine	= midas_machine_init,
+	.timer		= &exynos4_timer,
+#ifdef CONFIG_EXYNOS_C2C
+	.reserve	= &exynos_c2c_reserve,
+#endif
+	.init_early	= &exynos_init_reserve,
+MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
new file mode 100644
index 0000000..efa5921
--- /dev/null
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -0,0 +1,410 @@
+/*
+ * linux/arch/arm/mach-exynos/mach-nuri.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/serial_core.h>
+#include <linux/input.h>
+#include <linux/i2c.h>
+#include <linux/i2c/atmel_mxt_ts.h>
+#include <linux/gpio_keys.h>
+#include <linux/gpio.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+#include <linux/mmc/host.h>
+#include <linux/fb.h>
+#include <linux/pwm_backlight.h>
+
+#include <video/platform_lcd.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <plat/regs-serial.h>
+#include <plat/exynos4.h>
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/sdhci.h>
+#include <plat/ehci.h>
+#include <plat/clock.h>
+#include <plat/gpio-cfg.h>
+#include <plat/iic.h>
+
+#include <mach/map.h>
+
+/* Following are default values for UCON, ULCON and UFCON UART registers */
+#define NURI_UCON_DEFAULT	(S3C2410_UCON_TXILEVEL |	\
+				 S3C2410_UCON_RXILEVEL |	\
+				 S3C2410_UCON_TXIRQMODE |	\
+				 S3C2410_UCON_RXIRQMODE |	\
+				 S3C2410_UCON_RXFIFO_TOI |	\
+				 S3C2443_UCON_RXERR_IRQEN)
+
+#define NURI_ULCON_DEFAULT	S3C2410_LCON_CS8
+
+#define NURI_UFCON_DEFAULT	(S3C2410_UFCON_FIFOMODE |	\
+				 S5PV210_UFCON_TXTRIG256 |	\
+				 S5PV210_UFCON_RXTRIG256)
+
+enum fixed_regulator_id {
+	FIXED_REG_ID_MMC = 0,
+};
+
+static struct s3c2410_uartcfg nuri_uartcfgs[] __initdata = {
+	{
+		.hwport		= 0,
+		.ucon		= NURI_UCON_DEFAULT,
+		.ulcon		= NURI_ULCON_DEFAULT,
+		.ufcon		= NURI_UFCON_DEFAULT,
+	},
+	{
+		.hwport		= 1,
+		.ucon		= NURI_UCON_DEFAULT,
+		.ulcon		= NURI_ULCON_DEFAULT,
+		.ufcon		= NURI_UFCON_DEFAULT,
+	},
+	{
+		.hwport		= 2,
+		.ucon		= NURI_UCON_DEFAULT,
+		.ulcon		= NURI_ULCON_DEFAULT,
+		.ufcon		= NURI_UFCON_DEFAULT,
+	},
+	{
+		.hwport		= 3,
+		.ucon		= NURI_UCON_DEFAULT,
+		.ulcon		= NURI_ULCON_DEFAULT,
+		.ufcon		= NURI_UFCON_DEFAULT,
+	},
+};
+
+/* eMMC */
+static struct s3c_sdhci_platdata nuri_hsmmc0_data __initdata = {
+	.max_width		= 8,
+	.host_caps		= (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
+				MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
+				MMC_CAP_DISABLE | MMC_CAP_ERASE),
+	.cd_type		= S3C_SDHCI_CD_PERMANENT,
+	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+
+static struct regulator_consumer_supply emmc_supplies[] = {
+	REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
+	REGULATOR_SUPPLY("vmmc", "dw_mmc"),
+};
+
+static struct regulator_init_data emmc_fixed_voltage_init_data = {
+	.constraints		= {
+		.name		= "VMEM_VDD_2.8V",
+		.valid_ops_mask	= REGULATOR_CHANGE_STATUS,
+	},
+	.num_consumer_supplies	= ARRAY_SIZE(emmc_supplies),
+	.consumer_supplies	= emmc_supplies,
+};
+
+static struct fixed_voltage_config emmc_fixed_voltage_config = {
+	.supply_name		= "MASSMEMORY_EN (inverted)",
+	.microvolts		= 2800000,
+	.gpio			= EXYNOS4_GPL1(1),
+	.enable_high		= false,
+	.init_data		= &emmc_fixed_voltage_init_data,
+};
+
+static struct platform_device emmc_fixed_voltage = {
+	.name			= "reg-fixed-voltage",
+	.id			= FIXED_REG_ID_MMC,
+	.dev			= {
+		.platform_data	= &emmc_fixed_voltage_config,
+	},
+};
+
+/* SD */
+static struct s3c_sdhci_platdata nuri_hsmmc2_data __initdata = {
+	.max_width		= 4,
+	.host_caps		= MMC_CAP_4_BIT_DATA |
+				MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
+				MMC_CAP_DISABLE,
+	.ext_cd_gpio		= EXYNOS4_GPX3(3),	/* XEINT_27 */
+	.ext_cd_gpio_invert	= 1,
+	.cd_type		= S3C_SDHCI_CD_GPIO,
+	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+
+/* WLAN */
+static struct s3c_sdhci_platdata nuri_hsmmc3_data __initdata = {
+	.max_width		= 4,
+	.host_caps		= MMC_CAP_4_BIT_DATA |
+				MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
+	.cd_type		= S3C_SDHCI_CD_EXTERNAL,
+	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+
+static void __init nuri_sdhci_init(void)
+{
+	s3c_sdhci0_set_platdata(&nuri_hsmmc0_data);
+	s3c_sdhci2_set_platdata(&nuri_hsmmc2_data);
+	s3c_sdhci3_set_platdata(&nuri_hsmmc3_data);
+}
+
+/* GPIO KEYS */
+static struct gpio_keys_button nuri_gpio_keys_tables[] = {
+	{
+		.code			= KEY_VOLUMEUP,
+		.gpio			= EXYNOS4_GPX2(0),	/* XEINT16 */
+		.desc			= "gpio-keys: KEY_VOLUMEUP",
+		.type			= EV_KEY,
+		.active_low		= 1,
+		.debounce_interval	= 1,
+	}, {
+		.code			= KEY_VOLUMEDOWN,
+		.gpio			= EXYNOS4_GPX2(1),	/* XEINT17 */
+		.desc			= "gpio-keys: KEY_VOLUMEDOWN",
+		.type			= EV_KEY,
+		.active_low		= 1,
+		.debounce_interval	= 1,
+	}, {
+		.code			= KEY_POWER,
+		.gpio			= EXYNOS4_GPX2(7),	/* XEINT23 */
+		.desc			= "gpio-keys: KEY_POWER",
+		.type			= EV_KEY,
+		.active_low		= 1,
+		.wakeup			= 1,
+		.debounce_interval	= 1,
+	},
+};
+
+static struct gpio_keys_platform_data nuri_gpio_keys_data = {
+	.buttons		= nuri_gpio_keys_tables,
+	.nbuttons		= ARRAY_SIZE(nuri_gpio_keys_tables),
+};
+
+static struct platform_device nuri_gpio_keys = {
+	.name			= "gpio-keys",
+	.dev			= {
+		.platform_data	= &nuri_gpio_keys_data,
+	},
+};
+
+static void nuri_lcd_power_on(struct plat_lcd_data *pd, unsigned int power)
+{
+	int gpio = EXYNOS4_GPE1(5);
+
+	gpio_request(gpio, "LVDS_nSHDN");
+	gpio_direction_output(gpio, power);
+	gpio_free(gpio);
+}
+
+static int nuri_bl_init(struct device *dev)
+{
+	int ret, gpio = EXYNOS4_GPE2(3);
+
+	ret = gpio_request(gpio, "LCD_LDO_EN");
+	if (!ret)
+		gpio_direction_output(gpio, 0);
+
+	return ret;
+}
+
+static int nuri_bl_notify(struct device *dev, int brightness)
+{
+	if (brightness < 1)
+		brightness = 0;
+
+	gpio_set_value(EXYNOS4_GPE2(3), 1);
+
+	return brightness;
+}
+
+static void nuri_bl_exit(struct device *dev)
+{
+	gpio_free(EXYNOS4_GPE2(3));
+}
+
+/* nuri pwm backlight */
+static struct platform_pwm_backlight_data nuri_backlight_data = {
+	.pwm_id			= 0,
+	.pwm_period_ns		= 30000,
+	.max_brightness		= 100,
+	.dft_brightness		= 50,
+	.init			= nuri_bl_init,
+	.notify			= nuri_bl_notify,
+	.exit			= nuri_bl_exit,
+};
+
+static struct platform_device nuri_backlight_device = {
+	.name			= "pwm-backlight",
+	.id			= -1,
+	.dev			= {
+		.parent		= &s3c_device_timer[0].dev,
+		.platform_data	= &nuri_backlight_data,
+	},
+};
+
+static struct plat_lcd_data nuri_lcd_platform_data = {
+	.set_power		= nuri_lcd_power_on,
+};
+
+static struct platform_device nuri_lcd_device = {
+	.name			= "platform-lcd",
+	.id			= -1,
+	.dev			= {
+		.platform_data	= &nuri_lcd_platform_data,
+	},
+};
+
+/* I2C1 */
+static struct i2c_board_info i2c1_devs[] __initdata = {
+	/* Gyro, To be updated */
+};
+
+/* TSP */
+static u8 mxt_init_vals[] = {
+	/* MXT_GEN_COMMAND(6) */
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	/* MXT_GEN_POWER(7) */
+	0x20, 0xff, 0x32,
+	/* MXT_GEN_ACQUIRE(8) */
+	0x0a, 0x00, 0x05, 0x00, 0x00, 0x00, 0x09, 0x23,
+	/* MXT_TOUCH_MULTI(9) */
+	0x00, 0x00, 0x00, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x02, 0x00,
+	0x00, 0x01, 0x01, 0x0e, 0x0a, 0x0a, 0x0a, 0x0a, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00,
+	/* MXT_TOUCH_KEYARRAY(15) */
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
+	0x00,
+	/* MXT_SPT_GPIOPWM(19) */
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	/* MXT_PROCI_GRIPFACE(20) */
+	0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x28, 0x04,
+	0x0f, 0x0a,
+	/* MXT_PROCG_NOISE(22) */
+	0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x23, 0x00,
+	0x00, 0x05, 0x0f, 0x19, 0x23, 0x2d, 0x03,
+	/* MXT_TOUCH_PROXIMITY(23) */
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00,
+	/* MXT_PROCI_ONETOUCH(24) */
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	/* MXT_SPT_SELFTEST(25) */
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00,
+	/* MXT_PROCI_TWOTOUCH(27) */
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	/* MXT_SPT_CTECONFIG(28) */
+	0x00, 0x00, 0x02, 0x08, 0x10, 0x00,
+};
+
+static struct mxt_platform_data mxt_platform_data = {
+	.config			= mxt_init_vals,
+	.config_length		= ARRAY_SIZE(mxt_init_vals),
+
+	.x_line			= 18,
+	.y_line			= 11,
+	.x_size			= 1024,
+	.y_size			= 600,
+	.blen			= 0x1,
+	.threshold		= 0x28,
+	.voltage		= 2800000,		/* 2.8V */
+	.orient			= MXT_DIAGONAL_COUNTER,
+	.irqflags		= IRQF_TRIGGER_FALLING,
+};
+
+static struct s3c2410_platform_i2c i2c3_data __initdata = {
+	.flags		= 0,
+	.bus_num	= 3,
+	.slave_addr	= 0x10,
+	.frequency	= 400 * 1000,
+	.sda_delay	= 100,
+};
+
+static struct i2c_board_info i2c3_devs[] __initdata = {
+	{
+		I2C_BOARD_INFO("atmel_mxt_ts", 0x4a),
+		.platform_data	= &mxt_platform_data,
+		.irq		= IRQ_EINT(4),
+	},
+};
+
+static void __init nuri_tsp_init(void)
+{
+	int gpio;
+
+	/* TOUCH_INT: XEINT_4 */
+	gpio = EXYNOS4_GPX0(4);
+	gpio_request(gpio, "TOUCH_INT");
+	s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
+	s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+}
+
+/* GPIO I2C 5 (PMIC) */
+static struct i2c_board_info i2c5_devs[] __initdata = {
+	/* max8997, To be updated */
+};
+
+/* USB EHCI */
+static struct s5p_ehci_platdata nuri_ehci_pdata;
+
+static void __init nuri_ehci_init(void)
+{
+	struct s5p_ehci_platdata *pdata = &nuri_ehci_pdata;
+
+	s5p_ehci_set_platdata(pdata);
+}
+
+static struct platform_device *nuri_devices[] __initdata = {
+	/* Samsung Platform Devices */
+	&emmc_fixed_voltage,
+	&s3c_device_hsmmc0,
+	&s3c_device_hsmmc2,
+	&s3c_device_hsmmc3,
+	&s3c_device_wdt,
+	&s3c_device_timer[0],
+	&s5p_device_ehci,
+	&s3c_device_i2c3,
+
+	/* NURI Devices */
+	&nuri_gpio_keys,
+	&nuri_lcd_device,
+	&nuri_backlight_device,
+};
+
+static void __init nuri_map_io(void)
+{
+	s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+	s3c24xx_init_clocks(24000000);
+	s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs));
+}
+
+static void __init nuri_machine_init(void)
+{
+	nuri_sdhci_init();
+	nuri_tsp_init();
+
+	i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
+	s3c_i2c3_set_platdata(&i2c3_data);
+	i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs));
+	i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
+
+	nuri_ehci_init();
+	clk_xusbxti.rate = 24000000;
+
+	/* Last */
+	platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices));
+}
+
+MACHINE_START(NURI, "NURI")
+	/* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
+	.boot_params	= S5P_PA_SDRAM + 0x100,
+	.init_irq	= exynos4_init_irq,
+	.map_io		= nuri_map_io,
+	.init_machine	= nuri_machine_init,
+	.timer		= &exynos4_timer,
+MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-p10.c b/arch/arm/mach-exynos/mach-p10.c
new file mode 100644
index 0000000..5ee8289
--- /dev/null
+++ b/arch/arm/mach-exynos/mach-p10.c
@@ -0,0 +1,3091 @@
+/* linux/arch/arm/mach-exynos/mach-p10.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/platform_device.h>
+#include <linux/serial_core.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi_gpio.h>
+#include <linux/clk.h>
+#include <linux/gpio.h>
+#include <linux/gpio_event.h>
+#include <linux/gpio_keys.h>
+#include <linux/i2c.h>
+#include <linux/i2c-gpio.h>
+#include <linux/pwm_backlight.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+#include <linux/mmc/host.h>
+#include <linux/memblock.h>
+#include <linux/fb.h>
+#include <linux/delay.h>
+#include <linux/notifier.h>
+#include <linux/reboot.h>
+
+#include <video/platform_lcd.h>
+#include <video/s5p-dp.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <media/exynos_gscaler.h>
+#include <media/exynos_flite.h>
+#include <media/exynos_fimc_is.h>
+#include <plat/gpio-cfg.h>
+#include <plat/adc.h>
+#include <plat/regs-serial.h>
+#include <plat/exynos5.h>
+#include <plat/cpu.h>
+#include <plat/clock.h>
+#include <plat/hwmon.h>
+#include <plat/devs.h>
+#include <plat/sdhci.h>
+
+#include <plat/fb.h>
+#include <plat/fb-s5p.h>
+#include <plat/fb-core.h>
+#include <plat/regs-fb-v4.h>
+#include <plat/iic.h>
+#include <plat/pd.h>
+#include <plat/ehci.h>
+#include <plat/s5p-mfc.h>
+#include <plat/dp.h>
+#include <plat/backlight.h>
+#include <plat/usbgadget.h>
+#include <plat/fimg2d.h>
+#include <plat/tv-core.h>
+#include <plat/s3c64xx-spi.h>
+
+#include <plat/mipi_csis.h>
+#include <mach/map.h>
+#include <mach/exynos-ion.h>
+#include <mach/sysmmu.h>
+#include <mach/spi-clocks.h>
+#include <mach/ppmu.h>
+#include <mach/dev.h>
+#include <mach/pmu.h>
+#include <mach/regs-pmu.h>
+#include <mach/dwmci.h>
+#ifdef CONFIG_VIDEO_JPEG_V2X
+#include <plat/jpeg.h>
+#endif
+
+#ifdef CONFIG_EXYNOS_C2C
+#include <mach/c2c.h>
+#endif
+
+#ifdef CONFIG_VIDEO_EXYNOS_TV
+#include <plat/tvout.h>
+#endif
+
+#ifdef CONFIG_MFD_MAX77686
+#include <linux/mfd/max77686.h>
+#endif
+
+#ifdef CONFIG_SENSORS_BH1721FVC
+#include <linux/bh1721fvc.h>
+#endif
+
+#include <mach/gpio-p10.h>
+#include <mach/regs-clock.h>
+#include <mach/regs-pmu5.h>
+#include <mach/midas-sound.h>
+
+#if defined(CONFIG_SEC_DEBUG)
+#include <mach/sec_debug.h>
+#endif
+
+#ifdef CONFIG_MPU_SENSORS_MPU6050
+#include <linux/mpu_411.h>
+#endif
+
+#ifdef CONFIG_EXYNOS4_SETUP_THERMAL
+#include <plat/s5p-tmu.h>
+#include <mach/regs-tmu.h>
+#endif
+#include <plat/media.h>
+
+#ifdef CONFIG_BATTERY_SAMSUNG_P1X
+#include <mach/p10-battery.h>
+#endif
+
+#ifdef CONFIG_STMPE811_ADC
+#include <linux/stmpe811-adc.h>
+struct stmpe811_platform_data stmpe811_pdata;
+#endif
+
+#include <mach/p10-input.h>
+#ifdef CONFIG_LEDS_SPFCW043
+#include <linux/leds-spfcw043.h>
+#endif
+
+#include "p10-wlan.h"
+
+#ifdef CONFIG_FB_S5P_EXTDSP
+struct s3cfb_extdsp_lcd {
+	int	width;
+	int	height;
+	int	bpp;
+};
+#endif
+
+#ifdef CONFIG_MPU_SENSORS_MPU6050
+	struct mpu_platform_data mpu6050_data = {
+	.int_config = 0x10,
+	.orientation = {0, 1, 0,
+			1, 0, 0,
+			0, 0, -1},
+	.enable_irq_handler = NULL,
+	};
+
+static struct ext_slave_platform_data mpu_ak8975_data = {
+	.bus		= EXT_SLAVE_BUS_PRIMARY,
+	.adapt_num	= 11,
+	.orientation = {1, 0, 0,
+			0, 1, 0,
+			0, 0, 1},
+	.address = 0x0C,
+	.irq = IRQ_EINT(18),
+	};
+
+static struct i2c_gpio_platform_data gpio_i2c_data11 = {
+	.sda_pin = GPIO_MSENSE_SDA,
+	.scl_pin = GPIO_MSENSE_SCL,
+};
+
+struct platform_device s3c_device_i2c11 = {
+	.name = "i2c-gpio",
+	.id = 11,
+	.dev.platform_data = &gpio_i2c_data11,
+};
+
+static struct i2c_board_info i2c_devs11[] __initdata = {
+	{
+		I2C_BOARD_INFO("ak8975_mod", 0x0C),
+		.irq = IRQ_EINT(18),
+		.platform_data = &mpu_ak8975_data,
+	},
+};
+
+static struct i2c_board_info i2c_devs1[] __initdata = {
+	{
+		I2C_BOARD_INFO("mpu6050",0x68),
+		.irq = IRQ_EINT(12),
+		.platform_data = &mpu6050_data,
+	},
+/*
+	{
+		I2C_BOARD_INFO("ak8975_mod",0x0C),
+		.irq = IRQ_EINT(18),
+		.platform_data = &mpu_ak8975_data,
+	},
+*/
+};
+
+void magnetic_init()
+{
+	pr_info("%s : AK8963C Init", __func__);
+	s3c_gpio_cfgpin(GPIO_MSENSE_RST, S3C_GPIO_SFN(S3C_GPIO_OUTPUT));
+	s3c_gpio_setpull(GPIO_MSENSE_RST, S3C_GPIO_PULL_UP);
+	gpio_set_value(GPIO_MSENSE_RST, 0);
+	usleep_range(20, 20);
+	gpio_set_value(GPIO_MSENSE_RST, 1);
+}
+
+#else
+static struct i2c_board_info i2c_devs1[] __initdata = {
+	{
+		I2C_BOARD_INFO("dummy", (0x10)),
+	}
+};
+#endif /* CONFIG_MPU_SENSORS_MPU6050 */
+
+
+#define REG_INFORM4	       (S5P_INFORM4)
+
+/* Following are default values for UCON, ULCON and UFCON UART registers */
+#define SMDK5250_UCON_DEFAULT	(S3C2410_UCON_TXILEVEL |	\
+				 S3C2410_UCON_RXILEVEL |	\
+				 S3C2410_UCON_TXIRQMODE |	\
+				 S3C2410_UCON_RXIRQMODE |	\
+				 S3C2410_UCON_RXFIFO_TOI |	\
+				 S3C2443_UCON_RXERR_IRQEN)
+
+#define SMDK5250_ULCON_DEFAULT	S3C2410_LCON_CS8
+
+#define SMDK5250_UFCON_DEFAULT	(S3C2410_UFCON_FIFOMODE |	\
+				 S5PV210_UFCON_TXTRIG4 |	\
+				 S5PV210_UFCON_RXTRIG4)
+
+#ifdef CONFIG_30PIN_CONN
+#include <linux/30pin_con.h>
+#endif
+
+#ifdef CONFIG_MOTOR_DRV_ISA1200
+#include <linux/isa1200_vibrator.h>
+#endif
+
+static struct s3c2410_uartcfg smdk5250_uartcfgs[] __initdata = {
+	[0] = {
+		.hwport		= 0,
+		.flags		= 0,
+		.ucon		= SMDK5250_UCON_DEFAULT,
+		.ulcon		= SMDK5250_ULCON_DEFAULT,
+		.ufcon		= SMDK5250_UFCON_DEFAULT,
+	},
+	[1] = {
+		.hwport		= 1,
+		.flags		= 0,
+		.ucon		= SMDK5250_UCON_DEFAULT,
+		.ulcon		= SMDK5250_ULCON_DEFAULT,
+		.ufcon		= SMDK5250_UFCON_DEFAULT,
+	},
+	[2] = {
+		.hwport		= 2,
+		.flags		= 0,
+		.ucon		= SMDK5250_UCON_DEFAULT,
+		.ulcon		= SMDK5250_ULCON_DEFAULT,
+		.ufcon		= SMDK5250_UFCON_DEFAULT,
+	},
+	[3] = {
+		.hwport		= 3,
+		.flags		= 0,
+		.ucon		= SMDK5250_UCON_DEFAULT,
+		.ulcon		= SMDK5250_ULCON_DEFAULT,
+		.ufcon		= SMDK5250_UFCON_DEFAULT,
+	},
+};
+
+#ifdef CONFIG_EXYNOS_MEDIA_DEVICE
+struct platform_device exynos_device_md0 = {
+	.name = "exynos-mdev",
+	.id = 0,
+};
+
+struct platform_device exynos_device_md1 = {
+	.name = "exynos-mdev",
+	.id = 1,
+};
+struct platform_device exynos_device_md2 = {
+	.name = "exynos-mdev",
+	.id = 2,
+};
+#endif
+
+#if defined(CONFIG_DP_40HZ_P10)
+#define FPS 40
+#elif defined(CONFIG_DP_60HZ_P10)
+#define FPS 60
+#endif
+#ifdef CONFIG_FB_S3C
+#if defined(CONFIG_MACH_P10_DP_01)
+
+static struct s3c_fb_pd_win p10_fb_win0 = {
+	.win_mode = {
+		.refresh	= FPS,
+		.left_margin	= 80,
+		.right_margin	= 48,
+		.upper_margin	= 37,
+		.lower_margin	= 3,
+		.hsync_len	= 32,
+		.vsync_len	= 6,
+		.xres		= 2560,
+		.yres		= 1600,
+	},
+	.virtual_x		= 2560,
+	.virtual_y		= 1640 * 2,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+};
+
+static struct s3c_fb_pd_win p10_fb_win1 = {
+	.win_mode = {
+		.refresh	= FPS,
+		.left_margin	= 80,
+		.right_margin	= 48,
+		.upper_margin	= 37,
+		.lower_margin	= 3,
+		.hsync_len	= 32,
+		.vsync_len	= 6,
+		.xres		= 2560,
+		.yres		= 1600,
+	},
+
+	.virtual_x		= 2560,
+	.virtual_y		= 1640 * 2,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+
+};
+
+static struct s3c_fb_pd_win p10_fb_win2 = {
+	.win_mode = {
+		.refresh	= FPS,
+		.left_margin	= 80,
+		.right_margin	= 48,
+		.upper_margin	= 37,
+		.lower_margin	= 3,
+		.hsync_len	= 32,
+		.vsync_len	= 6,
+		.xres		= 2560,
+		.yres		= 1600,
+	},
+
+	.virtual_x		= 2560,
+	.virtual_y		= 1640 * 2,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+
+};
+
+static struct s3c_fb_pd_win p10_fb_win3 = {
+	.win_mode = {
+		.refresh	= FPS,
+		.left_margin	= 80,
+		.right_margin	= 48,
+		.upper_margin	= 37,
+		.lower_margin	= 3,
+		.hsync_len	= 32,
+		.vsync_len	= 6,
+		.xres		= 2560,
+		.yres		= 1600,
+	},
+
+	.virtual_x		= 2560,
+	.virtual_y		= 1640 * 2,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+
+};
+
+static struct s3c_fb_pd_win p10_fb_win4 = {
+	.win_mode = {
+		.refresh	= FPS,
+		.left_margin	= 80,
+		.right_margin	= 48,
+		.upper_margin	= 37,
+		.lower_margin	= 3,
+		.hsync_len	= 32,
+		.vsync_len	= 6,
+		.xres		= 2560,
+		.yres		= 1600,
+	},
+
+	.virtual_x		= 2560,
+	.virtual_y		= 1640 * 2,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+
+};
+
+#elif defined(CONFIG_MACH_P10_DP_00)
+
+static struct s3c_fb_pd_win p10_fb_win0 = {
+	.win_mode = {
+		.refresh	= 20,
+		.left_margin	= 40,
+		.right_margin	= 24,
+		.upper_margin	= 20,
+		.lower_margin	= 3,
+		.hsync_len	= 16,
+		.vsync_len	= 6,
+		.xres		= 2560,
+		.yres		= 1600,
+	},
+	.virtual_x		= 2560,
+	.virtual_y		= 1640 * 2,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+};
+
+static struct s3c_fb_pd_win p10_fb_win1 = {
+	.win_mode = {
+		.refresh	= 20,
+		.left_margin	= 40,
+		.right_margin	= 24,
+		.upper_margin	= 20,
+		.lower_margin	= 3,
+		.hsync_len	= 16,
+		.vsync_len	= 6,
+		.xres		= 2560,
+		.yres		= 1600,
+
+	},
+	.virtual_x		= 2560,
+	.virtual_y		= 1640 * 2,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+
+};
+
+static struct s3c_fb_pd_win p10_fb_win2 = {
+	.win_mode = {
+		.refresh	= 20,
+		.left_margin	= 40,
+		.right_margin	= 24,
+		.upper_margin	= 20,
+		.lower_margin	= 3,
+		.hsync_len	= 16,
+		.vsync_len	= 6,
+		.xres		= 2560,
+		.yres		= 1600,
+
+	},
+	.virtual_x		= 2560,
+	.virtual_y		= 1640 * 2,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+
+};
+#endif
+static void exynos_fimd_gpio_setup_24bpp(void)
+{
+	unsigned int reg = 0;
+	unsigned int uRead = 0;
+
+#if defined(CONFIG_S5P_DP)
+		/* Set Hotplug detect for DP */
+		s3c_gpio_cfgpin(GPIO_DP_HPD, S3C_GPIO_SFN(3));
+#endif
+	/*
+	 * Set DISP1BLK_CFG register for Display path selection
+	 *
+	 * FIMD of DISP1_BLK Bypass selection : DISP1BLK_CFG[15]
+	 * ---------------------
+	 *  0 | MIE/MDNIE
+	 *  1 | FIMD : selected
+	 */
+	reg = __raw_readl(S3C_VA_SYS + 0x0214);
+	reg &= ~(1 << 15);	/* To save other reset values */
+	reg |= (1 << 15);
+	__raw_writel(reg, S3C_VA_SYS + 0x0214);
+#if defined(CONFIG_S5P_DP)
+#if defined(CONFIG_MACH_P10_DP_01)
+	// MPLL => FIMD Bus clock
+	uRead = __raw_readl(EXYNOS5_CLKSRC_TOP0);
+	uRead = (uRead & ~(0x3<<14)) | (0x0<<14);
+	__raw_writel(uRead, EXYNOS5_CLKSRC_TOP0);
+
+	uRead = __raw_readl(EXYNOS5_CLKDIV_TOP0);
+	uRead = (uRead & ~(0x7<<28)) | (0x2<<28);
+	__raw_writel(uRead,EXYNOS5_CLKDIV_TOP0);
+
+	/* Reference clcok selection for DPTX_PHY: pad_osc_clk_24M */
+	reg = __raw_readl(S3C_VA_SYS + 0x04d4);
+	reg = (reg & ~(0x1 << 0)) | (0x0 << 0);
+	__raw_writel(reg, S3C_VA_SYS + 0x04d4);
+
+	/* DPTX_PHY: XXTI */
+	reg = __raw_readl(S3C_VA_SYS + 0x04d8);
+	reg = (reg & ~(0x1 << 3)) | (0x0 << 3);
+	__raw_writel(reg, S3C_VA_SYS + 0x04d8);
+#elif defined(CONFIG_MACH_P10_DP_00)
+
+	reg = __raw_readl(S3C_VA_SYS + 0x04d4);
+	reg |= (1 << 0);
+	__raw_writel(reg, S3C_VA_SYS + 0x04d4);
+
+	/* DPTX_PHY: XXTI */
+	reg = __raw_readl(S3C_VA_SYS + 0x04d8);
+	reg &= ~(1 << 3);
+	__raw_writel(reg, S3C_VA_SYS + 0x04d8);
+#endif
+#endif
+}
+
+static struct s3c_fb_platdata p10_lcd1_pdata __initdata = {
+	.win[0]		= &p10_fb_win0,
+	.win[1]		= &p10_fb_win1,
+	.win[2]		= &p10_fb_win2,
+	.win[3]		= &p10_fb_win3,
+	.win[4]		= &p10_fb_win4,
+	.default_win	= 2,
+	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+	.vidcon1	= 0,
+	.setup_gpio	= exynos_fimd_gpio_setup_24bpp,
+};
+#endif
+
+#if defined CONFIG_VIDEO_EXYNOS5_FIMC_IS
+static struct exynos5_platform_fimc_is exynos5_fimc_is_data;
+
+#if defined CONFIG_VIDEO_S5K4E5
+static struct exynos5_fimc_is_sensor_info s5k4e5= {
+	.sensor_name = "S5K4E5",
+	.sensor_id = SENSOR_NAME_S5K4E5,
+#if defined CONFIG_S5K4E5_POSITION_FRONT
+	.sensor_position = SENSOR_POSITION_FRONT,
+#elif  defined CONFIG_S5K4E5_POSITION_REAR
+	.sensor_position = SENSOR_POSITION_REAR,
+#endif
+#if defined CONFIG_S5K4E5_CSI_C
+	.csi_id = CSI_ID_A,
+	.flite_id = FLITE_ID_A,
+	.i2c_channel = SENSOR_CONTROL_I2C0,
+#elif  defined CONFIG_S5K4E5_CSI_D
+	.csi_id = CSI_ID_B,
+	.flite_id = FLITE_ID_B,
+	.i2c_channel = SENSOR_CONTROL_I2C1,
+#endif
+
+	.max_width = 2560,
+	.max_height = 1920,
+	.max_frame_rate = 30,
+
+	.mipi_lanes = 2,
+	.mipi_settle = 12,
+	.mipi_align = 24,
+};
+#endif
+
+#if defined CONFIG_VIDEO_S5K6A3
+static struct exynos5_fimc_is_sensor_info s5k6a3= {
+	.sensor_name = "S5K6A3",
+	.sensor_id = SENSOR_NAME_S5K6A3,
+#if defined CONFIG_S5K6A3_POSITION_FRONT
+	.sensor_position = SENSOR_POSITION_FRONT,
+#elif  defined CONFIG_S5K6A3_POSITION_REAR
+	.sensor_position = SENSOR_POSITION_REAR,
+#endif
+#if defined CONFIG_S5K6A3_CSI_C
+	.csi_id = CSI_ID_A,
+	.flite_id = FLITE_ID_A,
+	.i2c_channel = SENSOR_CONTROL_I2C0,
+#elif  defined CONFIG_S5K6A3_CSI_D
+	.csi_id = CSI_ID_B,
+	.flite_id = FLITE_ID_B,
+	.i2c_channel = SENSOR_CONTROL_I2C1,
+#endif
+
+	.max_width = 1280,
+	.max_height = 720,
+	.max_frame_rate = 30,
+
+	.mipi_lanes = 1,
+	.mipi_settle = 12,
+	.mipi_align = 24,
+};
+#endif
+#endif
+
+#ifdef CONFIG_S5P_DP
+static void dp_lcd_set_power(struct plat_lcd_data *pd,
+				unsigned int power)
+{
+	if (power) {
+
+		/* LCD_PWM_IN_2.8V, AH21, XPWMOUT_0 => LCD_B_PWM */
+#ifndef CONFIG_BACKLIGHT_PWM
+		gpio_request_one(GPIO_LCD_PWM_IN_18V, GPIOF_OUT_INIT_LOW, "GPB2");
+#endif
+
+#ifdef CONFIG_MACH_P10_00_BD
+		/* LCD_APS_EN_2.8V, R6, XCI1RGB_2 => GPG0_2 */
+		gpio_request_one(GPIO_LCD_APS_EN_18V, GPIOF_OUT_INIT_LOW, "GPG0");
+#endif
+		/* LCD_EN , XMMC2CDN => GPC2_2 */
+		gpio_request_one(GPIO_LCD_EN, GPIOF_OUT_INIT_LOW, "GPC2");
+
+		/* LCD_EN , XMMC2CDN => GPC2_2 */
+		gpio_set_value(GPIO_LCD_EN, 1);
+
+#ifdef CONFIG_MACH_P10_00_BD
+		/* LCD_APS_EN_2.8V, R6, XCI1RGB_2 => GPG0_2 */
+		gpio_set_value(GPIO_LCD_APS_EN_18V, 1);
+#endif
+
+		udelay(1000);
+
+		/* LCD_PWM_IN_2.8V, AH21, XPWMOUT_0=> LCD_B_PWM */
+#ifndef CONFIG_BACKLIGHT_PWM
+		gpio_set_value(GPIO_LCD_PWM_IN_18V, 1);
+#endif
+	} else {
+		/* LCD_PWM_IN_2.8V, AH21, XPWMOUT_0=> LCD_B_PWM */
+#ifndef CONFIG_BACKLIGHT_PWM
+		gpio_set_value(GPIO_LCD_PWM_IN_18V, 0);
+#endif
+
+#ifdef CONFIG_MACH_P10_00_BD
+		/* LCD_APS_EN_2.8V, R6, XCI1RGB_2 => GPG0_2 */
+		gpio_set_value(GPIO_LCD_APS_EN_18V, 0);
+#endif
+
+		/* LCD_EN , XMMC2CDN => GPC2_2 */
+		gpio_set_value(GPIO_LCD_EN, 0);
+
+#ifdef CONFIG_MACH_P10_00_BD
+		/* LCD_APS_EN_2.8V, R6, XCI1RGB_2 => GPG0_2 */
+		gpio_free(GPIO_LCD_APS_EN_18V);
+#endif
+
+		/* LCD_EN , XMMC2CDN => GPC2_2 */
+		gpio_free(GPIO_LCD_EN);
+
+#ifndef CONFIG_BACKLIGHT_PWM
+		gpio_free(GPIO_LCD_PWM_IN_18V);
+#endif
+	}
+}
+
+static struct plat_lcd_data p10_dp_lcd_data = {
+	.set_power	= dp_lcd_set_power,
+};
+
+static struct platform_device p10_dp_lcd = {
+	.name		   = "platform-lcd",
+	.dev.parent	   = &s5p_device_fimd1.dev,
+	.dev.platform_data = &p10_dp_lcd_data,
+};
+
+static struct video_info p10_dp_config = {
+	.name			= "for p10 TEST",
+#if defined(CONFIG_MACH_P10_DP_01)
+	.h_sync_polarity	= 0,
+	.v_sync_polarity	= 0,
+	.interlaced		= 0,
+
+	.color_space		= COLOR_RGB,
+	.dynamic_range		= VESA,
+	.ycbcr_coeff		= COLOR_YCBCR601,
+	.color_depth		= COLOR_8,
+
+	.link_rate		= LINK_RATE_2_70GBPS,
+	.lane_count		= LANE_COUNT4,
+
+#elif defined(CONFIG_MACH_P10_DP_00)
+
+	.h_sync_polarity	= 0,
+	.v_sync_polarity	= 0,
+	.interlaced		= 0,
+
+	.color_space		= COLOR_RGB,
+	.dynamic_range		= VESA,
+	.ycbcr_coeff		= COLOR_YCBCR601,
+	.color_depth		= COLOR_8,
+
+	.link_rate		= LINK_RATE_1_62GBPS,
+	.lane_count		= LANE_COUNT4,
+#endif
+};
+
+static void s5p_dp_backlight_on(void)
+{
+	/* LED_BACKLIGHT_RESET: XCI1RGB_5 => GPG0_5 */
+	gpio_request_one(GPIO_LED_BACKLIGHT_RESET, GPIOF_OUT_INIT_LOW, "GPG0");
+
+	gpio_set_value(GPIO_LED_BACKLIGHT_RESET, 1);
+}
+
+static void s5p_dp_backlight_off(void)
+{
+	/* LED_BACKLIGHT_RESET: XCI1RGB_5 => GPG0_5 */
+	gpio_set_value(GPIO_LED_BACKLIGHT_RESET, 0);
+
+	gpio_free(GPIO_LED_BACKLIGHT_RESET);
+
+}
+
+static struct s5p_dp_platdata p10_dp_data __initdata = {
+	.video_info = &p10_dp_config,
+	.phy_init	= s5p_dp_phy_init,
+	.phy_exit	= s5p_dp_phy_exit,
+	.backlight_on	= s5p_dp_backlight_on,
+	.backlight_off	= s5p_dp_backlight_off,
+};
+#endif
+
+/* LCD Backlight data */
+#ifdef CONFIG_BACKLIGHT_PWM
+static struct samsung_bl_gpio_info p10_bl_gpio_info = {
+	.no = GPIO_LCD_PWM_IN_18V,
+	.func = S3C_GPIO_SFN(2),
+};
+
+static struct platform_pwm_backlight_data p10_bl_data = {
+	.pwm_id = 0,
+	.pwm_period_ns	= 10000,
+};
+#endif
+
+#if defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC)
+static struct s5p_mfc_platdata smdk5250_mfc_pd = {
+	.clock_rate = 333000000,
+};
+#endif
+
+#ifdef CONFIG_EXYNOS_C2C
+struct exynos_c2c_platdata smdk5250_c2c_pdata = {
+	.setup_gpio	= NULL,
+	.shdmem_addr	= C2C_SHAREDMEM_BASE,
+	.shdmem_size	= C2C_MEMSIZE_64,
+	.ap_sscm_addr	= NULL,
+	.cp_sscm_addr	= NULL,
+	.rx_width	= C2C_BUSWIDTH_16,
+	.tx_width	= C2C_BUSWIDTH_16,
+	.clk_opp100	= 400,
+	.clk_opp50	= 200,
+	.clk_opp25	= 100,
+	.default_opp_mode	= C2C_OPP25,
+	.get_c2c_state	= NULL,
+	.c2c_sysreg	= S3C_VA_SYS + 0x0360,
+};
+#endif
+
+static int exynos5_notifier_call(struct notifier_block *this,
+					unsigned long code, void *_cmd)
+{
+	int mode = 0;
+
+	if ((code == SYS_RESTART) && _cmd)
+		if (!strcmp((char *)_cmd, "recovery"))
+			mode = 0xf;
+
+	__raw_writel(mode, REG_INFORM4);
+
+	return NOTIFY_DONE;
+}
+
+static struct notifier_block exynos5_reboot_notifier = {
+	.notifier_call = exynos5_notifier_call,
+};
+
+#ifdef CONFIG_EXYNOS4_DEV_DWMCI
+static void exynos_dwmci_cfg_gpio(int width)
+{
+	unsigned int gpio;
+
+	for (gpio = EXYNOS5_GPC0(0); gpio < EXYNOS5_GPC0(2); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV2);
+	}
+
+	switch (width) {
+	case MMC_BUS_WIDTH_8:
+		for (gpio = EXYNOS5_GPC1(3); gpio <= EXYNOS5_GPC1(6); gpio++) {
+			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
+			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+			s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV2);
+		}
+	case MMC_BUS_WIDTH_4:
+		for (gpio = EXYNOS5_GPC0(3); gpio <= EXYNOS5_GPC0(6); gpio++) {
+			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+			s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV2);
+		}
+		break;
+	case MMC_BUS_WIDTH_1:
+		gpio = EXYNOS5_GPC0(3);
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV2);
+	default:
+		break;
+	}
+}
+
+static struct dw_mci_board exynos_dwmci_pdata __initdata = {
+	.num_slots		= 1,
+	.quirks			= DW_MCI_QUIRK_BROKEN_CARD_DETECTION | DW_MCI_QUIRK_HIGHSPEED,
+	.bus_hz			= 66 * 1000 * 1000,
+	.caps			= MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR |
+				  MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
+	.fifo_depth             = 0x80,
+	.detect_delay_ms	= 200,
+	.hclk_name		= "dwmci",
+	.cclk_name		= "sclk_dwmci",
+	.cfg_gpio		= exynos_dwmci_cfg_gpio,
+};
+#endif
+
+static void exynos_dwmci0_cfg_gpio(int width)
+{
+	unsigned int gpio;
+
+	for (gpio = EXYNOS5_GPC0(0); gpio < EXYNOS5_GPC0(2); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+	}
+
+	switch (width) {
+	case MMC_BUS_WIDTH_8:
+		for (gpio = EXYNOS5_GPC1(0); gpio <= EXYNOS5_GPC1(3); gpio++) {
+			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+			s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+		}
+	case MMC_BUS_WIDTH_4:
+		for (gpio = EXYNOS5_GPC0(3); gpio <= EXYNOS5_GPC0(6); gpio++) {
+			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+			s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+		}
+		break;
+	case MMC_BUS_WIDTH_1:
+		gpio = EXYNOS5_GPC0(3);
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+	default:
+		break;
+	}
+}
+
+static struct dw_mci_board exynos5_dwmci0_pdata __initdata = {
+	.num_slots		= 1,
+	.quirks			= DW_MCI_QUIRK_BROKEN_CARD_DETECTION | DW_MCI_QUIRK_HIGHSPEED,
+	.bus_hz			= 100 * 1000 * 1000,
+	.caps			= MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR |
+				  MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
+	.fifo_depth             = 0x80,
+	.detect_delay_ms	= 200,
+	.hclk_name		= "dwmci",
+	.cclk_name		= "sclk_dwmci",
+	.cfg_gpio		= exynos_dwmci0_cfg_gpio,
+};
+
+static void exynos_dwmci1_cfg_gpio(int width)
+{
+	unsigned int gpio;
+	for (gpio = EXYNOS5_GPC2(0); gpio < EXYNOS5_GPC2(2); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV3);
+	}
+
+	switch (width) {
+	case MMC_BUS_WIDTH_4:
+		for (gpio = EXYNOS5_GPC2(3); gpio <= EXYNOS5_GPC2(6); gpio++) {
+			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+			s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV3);
+		}
+		break;
+	case MMC_BUS_WIDTH_1:
+		gpio = EXYNOS5_GPC2(3);
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV3);
+	default:
+		break;
+	}
+}
+
+static void (*wlan_notify_func)(struct platform_device *dev, int state);
+static DEFINE_MUTEX(wlan_mutex_lock);
+
+static int ext_cd_init_wlan(void (*notify_func)(struct platform_device *dev, int state))
+{
+	mutex_lock(&wlan_mutex_lock);
+	WARN_ON(wlan_notify_func);
+
+	wlan_notify_func = notify_func;
+
+	if (wlan_notify_func) {
+		if (samsung_rev() >= EXYNOS5250_REV_1_0)
+			wlan_notify_func(&exynos_device_dwmci1, 1);
+		else
+			wlan_notify_func(&s3c_device_hsmmc3, 1);
+	}
+
+	mutex_unlock(&wlan_mutex_lock);
+
+	return 0;
+}
+
+static int ext_cd_cleanup_wlan(void (*notify_func)(struct platform_device *dev, int state))
+{
+	mutex_lock(&wlan_mutex_lock);
+	WARN_ON(wlan_notify_func);
+
+	if (wlan_notify_func) {
+		if (samsung_rev() >= EXYNOS5250_REV_1_0)
+			wlan_notify_func(&exynos_device_dwmci1, 0);
+		else
+			wlan_notify_func(&s3c_device_hsmmc3, 0);
+	}
+
+	wlan_notify_func = NULL;
+
+	mutex_unlock(&wlan_mutex_lock);
+
+	return 0;
+}
+
+static struct dw_mci_board exynos5_dwmci1_pdata __initdata = {
+	.num_slots              = 1,
+	.quirks                 = DW_MCI_QUIRK_BROKEN_CARD_DETECTION | DW_MCI_QUIRK_HIGHSPEED,
+	.bus_hz                 = 50 * 1000 * 1000,
+	.caps                   = MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR |
+				  MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
+	.fifo_depth             = 0x80,
+	.detect_delay_ms        = 200,
+	.hclk_name              = "dwmci",
+	.cclk_name              = "sclk_dwmci",
+	.cfg_gpio               = exynos_dwmci1_cfg_gpio,
+	.ext_cd_init 		= ext_cd_init_wlan,
+	.ext_cd_cleanup 	= ext_cd_cleanup_wlan,
+	.cd_type 		= DW_MCI_CD_EXTERNAL,
+};
+
+void mmc_force_presence_change(struct platform_device *pdev)
+{
+	void (*notify_func)(struct platform_device *, int state) = NULL;
+	mutex_lock(&wlan_mutex_lock);
+	if (samsung_rev() >= EXYNOS5250_REV_1_0) {
+		if (pdev == &exynos_device_dwmci1)
+			notify_func = wlan_notify_func;
+	} else {
+		if (pdev == &s3c_device_hsmmc3)
+			notify_func = wlan_notify_func;
+	}
+
+	if (notify_func)
+		notify_func(pdev, 1);
+	else
+		pr_warn("%s: called for device with no notifier\n", __func__);
+	mutex_unlock(&wlan_mutex_lock);
+}
+EXPORT_SYMBOL_GPL(mmc_force_presence_change);
+
+static int smdk5250_dwmci_get_ro(u32 slot_id)
+{
+	/* smdk5250 rev1.0 did not support SD/MMC card write pritect. */
+	return 0;
+}
+
+static void exynos_dwmci2_cfg_gpio(int width)
+{
+	unsigned int gpio;
+
+	for (gpio = EXYNOS5_GPC3(0); gpio <= EXYNOS5_GPC3(2); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV2);
+	}
+
+	switch (width) {
+	case MMC_BUS_WIDTH_4:
+		for (gpio = EXYNOS5_GPC3(3); gpio <= EXYNOS5_GPC3(6); gpio++) {
+			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+			s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV2);
+		}
+		break;
+	case MMC_BUS_WIDTH_1:
+		gpio = EXYNOS5_GPC3(3);
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV2);
+	default:
+		break;
+	}
+}
+
+static struct dw_mci_board exynos5_dwmci2_pdata __initdata = {
+	.num_slots		= 1,
+	.quirks			= DW_MCI_QUIRK_HIGHSPEED,
+	.bus_hz			= 22 * 1000 * 1000,
+	.caps			= MMC_CAP_CMD23,
+	.fifo_depth             = 0x80,
+	.detect_delay_ms	= 200,
+	.hclk_name		= "dwmci",
+	.cclk_name		= "sclk_dwmci",
+	.cfg_gpio		= exynos_dwmci2_cfg_gpio,
+	.get_ro		= smdk5250_dwmci_get_ro,
+};
+
+#ifdef CONFIG_VIDEO_FIMG2D
+static struct fimg2d_platdata fimg2d_data __initdata = {
+	.hw_ver		= 0x42,
+	.gate_clkname	= "fimg2d",
+};
+#endif
+
+#ifdef CONFIG_S3C_DEV_HSMMC
+static struct s3c_sdhci_platdata smdk5250_hsmmc0_pdata __initdata = {
+	.cd_type		= S3C_SDHCI_CD_PERMANENT,
+	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
+#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
+	.max_width		= 8,
+	.host_caps		= MMC_CAP_8_BIT_DATA,
+#endif
+};
+#endif
+
+#ifdef CONFIG_S3C_DEV_HSMMC1
+static struct s3c_sdhci_platdata smdk5250_hsmmc1_pdata __initdata = {
+	.cd_type		= S3C_SDHCI_CD_INTERNAL,
+	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+#endif
+
+#ifdef CONFIG_S3C_DEV_HSMMC2
+static struct s3c_sdhci_platdata smdk5250_hsmmc2_pdata __initdata = {
+	.cd_type		= S3C_SDHCI_CD_GPIO,
+	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
+	.ext_cd_gpio		= GPIO_T_FLASH_DETECT,
+	.ext_cd_gpio_invert	= true,
+#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
+	.max_width		= 8,
+	.host_caps		= MMC_CAP_8_BIT_DATA,
+#endif
+};
+#endif
+
+struct class *camera_class;
+EXPORT_SYMBOL(camera_class);
+
+#ifdef CONFIG_S3C_DEV_HSMMC3
+static struct s3c_sdhci_platdata smdk5250_hsmmc3_pdata __initdata = {
+	.cd_type		= S3C_SDHCI_CD_EXTERNAL,
+	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
+	.pm_flags		= S3C_SDHCI_PM_IGNORE_SUSPEND_RESUME,
+	/* ext_cd_xxx should be used in only .cd_type = S3C_SDHCI_CD_EXTERNAL */
+	.ext_cd_init		= ext_cd_init_wlan,
+	.ext_cd_cleanup		= ext_cd_cleanup_wlan,
+};
+#endif
+
+#ifdef CONFIG_S3C64XX_DEV_SPI
+static struct s3c64xx_spi_csinfo spi1_csi[] = {
+	[0] = {
+		.line = GPIO_5M_SPI_CS,
+		.set_level = gpio_set_value,
+		.fb_delay = 0x2,
+	},
+};
+
+static struct spi_board_info spi1_board_info[] __initdata = {
+	{
+		.modalias = "spidev",
+		.platform_data = NULL,
+		.max_speed_hz = 10*1000*1000,
+		.bus_num = 1,
+		.chip_select = 0,
+		.mode = SPI_MODE_0,
+		.controller_data = &spi1_csi[0],
+	}
+};
+#endif
+
+#ifdef CONFIG_LEDS_SPFCW043
+static int spfcw043_setGpio(void)
+{
+	int err;
+
+	err = gpio_request(GPIO_CAM_FLASH_EN, "TORCH_EN");
+	if (err) {
+		printk(KERN_ERR "failed to request TORCH_EN\n");
+		return -EPERM;
+	}
+	gpio_direction_output(GPIO_CAM_FLASH_EN, 1);
+	err = gpio_request(GPIO_CAM_FLASH_SET, "TORCH_SET");
+	if (err) {
+		printk(KERN_ERR "failed to request TORCH_SET\n");
+		gpio_free(GPIO_CAM_FLASH_EN);
+		return -EPERM;
+	}
+	gpio_direction_output(GPIO_CAM_FLASH_SET, 1);
+	gpio_set_value(GPIO_CAM_FLASH_EN, 0);
+	gpio_set_value(GPIO_CAM_FLASH_SET, 0);
+
+	return 0;
+}
+
+static int spfcw043_freeGpio(void)
+{
+	gpio_free(GPIO_CAM_FLASH_EN);
+	gpio_free(GPIO_CAM_FLASH_SET);
+
+	return 0;
+}
+
+static void spfcw043_torch_en(int onoff)
+{
+	gpio_set_value(GPIO_CAM_FLASH_EN, onoff);
+}
+
+static void spfcw043_torch_set(int onoff)
+{
+	gpio_set_value(GPIO_CAM_FLASH_SET, onoff);
+}
+
+static struct spfcw043_led_platform_data spfcw043_led_data = {
+	.brightness = TORCH_BRIGHTNESS_50,
+	.status	= STATUS_UNAVAILABLE,
+	.setGpio = spfcw043_setGpio,
+	.freeGpio = spfcw043_freeGpio,
+	.torch_en = spfcw043_torch_en,
+	.torch_set = spfcw043_torch_set,
+};
+
+static struct platform_device s3c_device_spfcw043_led = {
+	.name	= "spfcw043-led",
+	.id	= -1,
+	.dev	= {
+		.platform_data	= &spfcw043_led_data,
+	},
+};
+#endif
+
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_LITE
+#if defined(CONFIG_ITU_A)
+static int smdk5250_cam0_reset(int dummy)
+{
+	int err;
+	/* Camera A */
+	err = gpio_request(EXYNOS5_GPX1(2), "GPX1");
+	if (err)
+		printk(KERN_ERR "#### failed to request GPX1_2 ####\n");
+
+	s3c_gpio_setpull(EXYNOS5_GPX1(2), S3C_GPIO_PULL_NONE);
+	gpio_direction_output(EXYNOS5_GPX1(2), 0);
+	gpio_direction_output(EXYNOS5_GPX1(2), 1);
+	gpio_free(EXYNOS5_GPX1(2));
+
+	return 0;
+}
+#endif
+#if defined(CONFIG_ITU_B)
+static int smdk5250_cam1_reset(int dummy)
+{
+	int err;
+	/* Camera A */
+	err = gpio_request(EXYNOS5_GPX1(0), "GPX1");
+	if (err)
+		printk(KERN_ERR "#### failed to request GPX1_2 ####\n");
+
+	s3c_gpio_setpull(EXYNOS5_GPX1(0), S3C_GPIO_PULL_NONE);
+	gpio_direction_output(EXYNOS5_GPX1(0), 0);
+	gpio_direction_output(EXYNOS5_GPX1(0), 1);
+	gpio_free(EXYNOS5_GPX1(0));
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_VIDEO_S5K4BA
+static struct s5k4ba_mbus_platform_data s5k4ba_mbus_plat = {
+	.id		= 0,
+	.fmt = {
+		.width	= 1600,
+		.height	= 1200,
+		/* .code	= V4L2_MBUS_FMT_UYVY8_2X8, */
+		.code	= V4L2_MBUS_FMT_VYUY8_2X8,
+	},
+	.clk_rate	= 24000000UL,
+#ifdef CONFIG_ITU_A
+	.set_power	= smdk5250_cam0_reset,
+#endif
+#ifdef CONFIG_ITU_B
+	.set_power	= smdk5250_cam1_reset,
+#endif
+};
+
+static struct i2c_board_info s5k4ba_info = {
+	I2C_BOARD_INFO("S5K4BA", 0x2d),
+	.platform_data = &s5k4ba_mbus_plat,
+};
+#endif
+
+/* 1 MIPI Cameras */
+#ifdef CONFIG_VIDEO_M5MOLS
+static struct m5mols_platform_data m5mols_platdata = {
+#ifdef CONFIG_CSI_C
+	.gpio_rst = EXYNOS5_GPX1(2), /* ISP_RESET */
+#endif
+#ifdef CONFIG_CSI_D
+	.gpio_rst = EXYNOS5_GPX1(0), /* ISP_RESET */
+#endif
+	.enable_rst = true, /* positive reset */
+	.irq = IRQ_EINT(22),
+};
+
+static struct i2c_board_info m5mols_board_info = {
+	I2C_BOARD_INFO("M5MOLS", 0x1F),
+	.platform_data = &m5mols_platdata,
+};
+#endif
+#endif /* CONFIG_VIDEO_EXYNOS_FIMC_LITE */
+
+#ifdef CONFIG_VIDEO_EXYNOS_MIPI_CSIS
+static struct regulator_consumer_supply mipi_csi_fixed_voltage_supplies[] = {
+	REGULATOR_SUPPLY("mipi_csi", "s5p-mipi-csis.0"),
+	REGULATOR_SUPPLY("mipi_csi", "s5p-mipi-csis.1"),
+};
+
+static struct regulator_init_data mipi_csi_fixed_voltage_init_data = {
+	.constraints = {
+		.always_on = 1,
+	},
+	.num_consumer_supplies	= ARRAY_SIZE(mipi_csi_fixed_voltage_supplies),
+	.consumer_supplies	= mipi_csi_fixed_voltage_supplies,
+};
+
+static struct fixed_voltage_config mipi_csi_fixed_voltage_config = {
+	.supply_name	= "DC_5V",
+	.microvolts	= 5000000,
+	.gpio		= -EINVAL,
+	.init_data	= &mipi_csi_fixed_voltage_init_data,
+};
+
+static struct platform_device mipi_csi_fixed_voltage = {
+	.name		= "reg-fixed-voltage",
+	.id		= 3,
+	.dev		= {
+		.platform_data	= &mipi_csi_fixed_voltage_config,
+	},
+};
+#endif
+
+#ifdef CONFIG_VIDEO_M5MOLS
+static struct regulator_consumer_supply m5mols_fixed_voltage_supplies[] = {
+	REGULATOR_SUPPLY("core", NULL),
+	REGULATOR_SUPPLY("dig_18", NULL),
+	REGULATOR_SUPPLY("d_sensor", NULL),
+	REGULATOR_SUPPLY("dig_28", NULL),
+	REGULATOR_SUPPLY("a_sensor", NULL),
+	REGULATOR_SUPPLY("dig_12", NULL),
+};
+
+static struct regulator_init_data m5mols_fixed_voltage_init_data = {
+	.constraints = {
+		.always_on = 1,
+	},
+	.num_consumer_supplies	= ARRAY_SIZE(m5mols_fixed_voltage_supplies),
+	.consumer_supplies	= m5mols_fixed_voltage_supplies,
+};
+
+static struct fixed_voltage_config m5mols_fixed_voltage_config = {
+	.supply_name	= "CAM_SENSOR",
+	.microvolts	= 1800000,
+	.gpio		= -EINVAL,
+	.init_data	= &m5mols_fixed_voltage_init_data,
+};
+
+static struct platform_device m5mols_fixed_voltage = {
+	.name		= "reg-fixed-voltage",
+	.id		= 4,
+	.dev		= {
+		.platform_data	= &m5mols_fixed_voltage_config,
+	},
+};
+#endif
+
+#if defined(CONFIG_REGULATOR_MAX77686)
+/* max77686 */
+#ifdef CONFIG_SND_SOC_WM8994
+static struct regulator_consumer_supply ldo3_supply[] = {
+	REGULATOR_SUPPLY("vcc_1.8v", NULL),
+	REGULATOR_SUPPLY("AVDD2", NULL),
+	REGULATOR_SUPPLY("CPVDD", NULL),
+	REGULATOR_SUPPLY("DBVDD1", NULL),
+	REGULATOR_SUPPLY("DBVDD2", NULL),
+	REGULATOR_SUPPLY("DBVDD3", NULL)
+};
+#else
+static struct regulator_consumer_supply ldo3_supply[] = {
+	REGULATOR_SUPPLY("vcc_1.8v", NULL),
+};
+#endif
+
+static struct regulator_consumer_supply ldo4_supply[] = {
+	REGULATOR_SUPPLY("vcc_2.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo5_supply[] = {
+	REGULATOR_SUPPLY("cam_isp_mipi_1.2v", NULL),
+};
+
+static struct regulator_consumer_supply ldo8_supply[] = {
+	REGULATOR_SUPPLY("vmipi_1.0v", NULL),
+};
+
+static struct regulator_consumer_supply ldo9_supply[] = {
+	REGULATOR_SUPPLY("touch_vdd_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo10_supply[] = {
+	REGULATOR_SUPPLY("vmipi_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo11_supply[] = {
+	REGULATOR_SUPPLY("vabb1_1.9v", NULL),
+};
+
+static struct regulator_consumer_supply ldo12_supply[] = {
+	REGULATOR_SUPPLY("votg_3.0v", NULL),
+};
+
+static struct regulator_consumer_supply ldo14_supply[] = {
+	REGULATOR_SUPPLY("vabb02_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo15_supply[] = {
+	REGULATOR_SUPPLY("vhsic_1.0v", NULL),
+};
+
+static struct regulator_consumer_supply ldo16_supply[] = {
+	REGULATOR_SUPPLY("vhsic_1.8v", NULL),
+};
+
+#if defined(CONFIG_MACH_P10_LUNGO_01_BD) || \
+	defined(CONFIG_MACH_P10_LUNGO_WIFI_01_BD)
+static struct regulator_consumer_supply ldo17_supply[] = {
+	REGULATOR_SUPPLY("cam_core_1.8v", NULL),
+};
+#endif
+static struct regulator_consumer_supply ldo18_supply[] = {
+	REGULATOR_SUPPLY("cam_io_from_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo19_supply[] = {
+	REGULATOR_SUPPLY("vt_cam_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo20_supply[] = {
+	REGULATOR_SUPPLY("vmem_vdd_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo21_supply[] = {
+	REGULATOR_SUPPLY("vtf_2.8v", NULL),
+};
+
+#if defined(CONFIG_MACH_P10_LUNGO_01_BD) || \
+	defined(CONFIG_MACH_P10_LUNGO_WIFI_01_BD)
+static struct regulator_consumer_supply ldo22_supply[] = {
+	REGULATOR_SUPPLY("vcc_mmc_2.8v", NULL),
+};
+#else
+static struct regulator_consumer_supply ldo22_supply[] = {
+	REGULATOR_SUPPLY("cam_core_1.8v", NULL),
+};
+#endif
+static struct regulator_consumer_supply ldo23_supply[] = {
+	REGULATOR_SUPPLY("touch_avdd", NULL),
+};
+
+static struct regulator_consumer_supply ldo24_supply[] = {
+	REGULATOR_SUPPLY("cam_af_2.8v", NULL),
+};
+static struct regulator_consumer_supply ldo25_supply[] = {
+	REGULATOR_SUPPLY("vadc_3.3v", NULL),
+};
+
+static struct regulator_consumer_supply ldo26_supply[] = {
+	REGULATOR_SUPPLY("irda_3.3v", NULL),
+};
+
+static struct regulator_consumer_supply max77686_buck1 =
+	REGULATOR_SUPPLY("vdd_mif", NULL);
+static struct regulator_consumer_supply max77686_buck2 =
+	REGULATOR_SUPPLY("vdd_arm", NULL);
+
+static struct regulator_consumer_supply max77686_buck3 =
+	REGULATOR_SUPPLY("vdd_int", NULL);
+
+static struct regulator_consumer_supply max77686_buck4 =
+	REGULATOR_SUPPLY("vdd_g3d", NULL);
+
+static struct regulator_consumer_supply max77686_buck9 =
+	REGULATOR_SUPPLY("cam_isp_core", NULL);
+
+static struct regulator_consumer_supply max77686_enp32khz[] = {
+	REGULATOR_SUPPLY("lpo_in", "bcm47511"),
+	REGULATOR_SUPPLY("lpo", "bcm43241_bluetooth"),
+};
+
+#define REGULATOR_INIT(_ldo, _name, _min_uV, _max_uV, _always_on, _ops_mask,\
+	_disabled) \
+static struct regulator_init_data _ldo##_init_data = {		\
+	.constraints = {					\
+		.name	= _name,				\
+		.min_uV = _min_uV,				\
+		.max_uV = _max_uV,				\
+		.always_on	= _always_on,			\
+		.boot_on	= _always_on,			\
+		.apply_uV	= 1,				\
+		.valid_ops_mask = _ops_mask,			\
+		.state_mem	= {				\
+		.disabled	= _disabled,		\
+		.enabled	= !(_disabled),		\
+		}						\
+	    },							    \
+	    .num_consumer_supplies = ARRAY_SIZE(_ldo##_supply),	    \
+	    .consumer_supplies = &_ldo##_supply[0],		    \
+	       };
+
+REGULATOR_INIT(ldo3, "VCC_1.8V_AP", 1800000, 1800000, 1,
+	0, 0);
+REGULATOR_INIT(ldo4, "VCC_2.8V_AP", 2800000, 2800000, 1,
+	0, 0);
+REGULATOR_INIT(ldo5, "CAM_ISP_MIPI_1.2V", 1200000, 1200000, 0,
+	REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo8, "VMIPI_1.0V", 1000000, 1000000, 1,
+	REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo9, "TOUCH_VDD_1.8V", 1800000, 1800000, 0,
+	REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo10, "VMIPI_1.8V", 1800000, 1800000, 1,
+	REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo11, "VABB1_1.8V", 1800000, 1800000, 1,
+	REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo12, "VUOTG_3.0V", 3000000, 3000000, 1,
+	REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo14, "VABB02_1.8V", 1800000, 1800000, 0,
+	REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo15, "VHSIC_1.0V", 1000000, 1000000, 1,
+	REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo16, "VHSIC_1.8V", 1800000, 1800000, 0,
+	REGULATOR_CHANGE_STATUS, 1);
+#if defined(CONFIG_MACH_P10_LUNGO_01_BD) || \
+	defined(CONFIG_MACH_P10_LUNGO_WIFI_01_BD)
+REGULATOR_INIT(ldo17, "CAM_CORE_1.8v", 1800000, 1800000, 0,
+	REGULATOR_CHANGE_STATUS, 1);
+#endif
+REGULATOR_INIT(ldo18, "CAM_IO_FROM_1.8V", 1800000, 1800000, 0,
+	REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo19, "VT_CAM_1.8V", 1800000, 1800000, 0,
+	REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo20, "VMEM_VDD_1.8V", 1800000, 1800000, 0,
+	REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo21, "VTF_2.8V", 2800000, 2800000, 0,
+	REGULATOR_CHANGE_STATUS, 1);
+#if defined(CONFIG_MACH_P10_LUNGO_01_BD) || \
+	defined(CONFIG_MACH_P10_LUNGO_WIFI_01_BD)
+REGULATOR_INIT(ldo22, "VCC_MMC_2.8v", 2800000, 2800000, 0,
+	REGULATOR_CHANGE_STATUS, 1);
+#else
+REGULATOR_INIT(ldo22, "CAM_CORE_1.8v", 1800000, 1800000, 0,
+	REGULATOR_CHANGE_STATUS, 1);
+#endif
+REGULATOR_INIT(ldo23, "TSP_AVDD_2.8V", 2800000, 2800000, 0,
+	REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo24, "CAM_AF_2.8V", 2800000, 2800000, 0,
+	REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo25, "VADC_3.3V", 3300000, 3300000, 1,
+	REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo26, "IRDA_3.3V", 3300000, 3300000, 0,
+	REGULATOR_CHANGE_STATUS, 1);
+
+static struct regulator_init_data max77686_buck1_data = {
+	.constraints = {
+		.name = "vdd_mif range",
+		.min_uV = 900000,
+		.max_uV = 1300000,
+		.always_on = 1,
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &max77686_buck1,
+};
+
+static struct regulator_init_data max77686_buck2_data = {
+	.constraints = {
+		.name = "vdd_arm range",
+		.min_uV = 800000,
+		.max_uV = 1500000,
+		.always_on = 1,
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &max77686_buck2,
+};
+
+static struct regulator_init_data max77686_buck3_data = {
+	.constraints = {
+		.name = "vdd_int range",
+		.min_uV = 900000,
+		.max_uV = 1300000,
+		.always_on = 1,
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &max77686_buck3,
+};
+
+static struct regulator_init_data max77686_buck4_data = {
+	 .constraints = {
+		 .name = "vdd_g3d range",
+		 .min_uV = 700000,
+		 .max_uV = 1300000,
+		 .boot_on = 1,
+		 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+		 REGULATOR_CHANGE_STATUS,
+	 },
+	 .num_consumer_supplies = 1,
+	 .consumer_supplies = &max77686_buck4,
+};
+
+static struct regulator_init_data max77686_buck9_data = {
+	  .constraints = {
+		.name = "cam_isp_core",
+		.min_uV = 1000000,
+		.max_uV = 1200000,
+		.apply_uV = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+			 REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+		.disabled = 1,
+		},
+	 },
+	 .num_consumer_supplies = 1,
+	 .consumer_supplies = &max77686_buck9,
+};
+
+static struct regulator_init_data max77686_enp32khz_data = {
+	.constraints = {
+		.name = "32KHZ_PMIC",
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.enabled	= 1,
+			.disabled	= 0,
+		},
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_enp32khz),
+	.consumer_supplies = max77686_enp32khz,
+};
+
+static struct max77686_regulator_data max77686_regulators[] = {
+		{MAX77686_BUCK1, &max77686_buck1_data,},
+		{MAX77686_BUCK2, &max77686_buck2_data,},
+		{MAX77686_BUCK3, &max77686_buck3_data,},
+		{MAX77686_BUCK4, &max77686_buck4_data,},
+		{MAX77686_BUCK9, &max77686_buck9_data,},
+		{MAX77686_LDO3, &ldo3_init_data,},
+		{MAX77686_LDO4, &ldo4_init_data,},
+		{MAX77686_LDO5, &ldo5_init_data,},
+		{MAX77686_LDO8, &ldo8_init_data,},
+		{MAX77686_LDO9, &ldo9_init_data,},
+		{MAX77686_LDO10, &ldo10_init_data,},
+		{MAX77686_LDO11, &ldo11_init_data,},
+		{MAX77686_LDO12, &ldo12_init_data,},
+		{MAX77686_LDO14, &ldo14_init_data,},
+		{MAX77686_LDO15, &ldo15_init_data,},
+		{MAX77686_LDO16, &ldo16_init_data,},
+#if defined(CONFIG_MACH_P10_LUNGO_01_BD) || \
+	defined(CONFIG_MACH_P10_LUNGO_WIFI_01_BD)
+		{MAX77686_LDO17, &ldo17_init_data,},
+#endif
+		{MAX77686_LDO18, &ldo18_init_data,},
+		{MAX77686_LDO19, &ldo19_init_data,},
+		{MAX77686_LDO20, &ldo20_init_data,},
+		{MAX77686_LDO21, &ldo21_init_data,},
+		{MAX77686_LDO22, &ldo22_init_data,},
+		{MAX77686_LDO23, &ldo23_init_data,},
+		{MAX77686_LDO24, &ldo24_init_data,},
+		{MAX77686_LDO25, &ldo25_init_data,},
+		{MAX77686_LDO26, &ldo26_init_data,},
+		{MAX77686_P32KH, &max77686_enp32khz_data,},
+};
+
+struct max77686_opmode_data max77686_opmode_data[MAX77686_REG_MAX] = {
+		[MAX77686_LDO3] = {MAX77686_LDO3, MAX77686_OPMODE_NORMAL},
+		[MAX77686_LDO8] = {MAX77686_LDO8, MAX77686_OPMODE_STANDBY},
+		[MAX77686_LDO10] = {MAX77686_LDO10, MAX77686_OPMODE_STANDBY},
+		[MAX77686_LDO11] = {MAX77686_LDO11, MAX77686_OPMODE_STANDBY},
+		[MAX77686_LDO12] = {MAX77686_LDO12, MAX77686_OPMODE_STANDBY},
+		[MAX77686_LDO14] = {MAX77686_LDO14, MAX77686_OPMODE_STANDBY},
+		[MAX77686_LDO15] = {MAX77686_LDO15, MAX77686_OPMODE_STANDBY},
+		[MAX77686_LDO16] = {MAX77686_LDO16, MAX77686_OPMODE_STANDBY},
+		[MAX77686_BUCK1] = {MAX77686_BUCK1, MAX77686_OPMODE_STANDBY},
+		[MAX77686_BUCK2] = {MAX77686_BUCK2, MAX77686_OPMODE_STANDBY},
+		[MAX77686_BUCK3] = {MAX77686_BUCK3, MAX77686_OPMODE_STANDBY},
+		[MAX77686_BUCK4] = {MAX77686_BUCK4, MAX77686_OPMODE_STANDBY},
+};
+
+static struct max77686_platform_data exynos4_max77686_info = {
+		.num_regulators = ARRAY_SIZE(max77686_regulators),
+		.regulators = max77686_regulators,
+		.irq_gpio	= GPIO_PMIC_IRQ,
+		.irq_base	= IRQ_BOARD_PMIC_START,
+		.wakeup = 1,
+
+		.opmode_data = max77686_opmode_data,
+		.ramp_rate = MAX77686_RAMP_RATE_27MV,
+		.has_full_constraints = 1,
+
+		.buck234_gpio_dvs = {
+			GPIO_PMIC_DVS1,
+			GPIO_PMIC_DVS2,
+			GPIO_PMIC_DVS3,
+		},
+		.buck234_gpio_selb = {
+			GPIO_BUCK2_SEL,
+			GPIO_BUCK3_SEL,
+			GPIO_BUCK4_SEL,
+		},
+
+		/*for future work after DVS Table */
+		.buck2_voltage[0] = 1100000,	/* 1.1V */
+		.buck2_voltage[1] = 1100000,	/* 1.1V */
+		.buck2_voltage[2] = 1100000,	/* 1.1V */
+		.buck2_voltage[3] = 1100000,	/* 1.1V */
+		.buck2_voltage[4] = 1100000,	/* 1.1V */
+		.buck2_voltage[5] = 1100000,	/* 1.1V */
+		.buck2_voltage[6] = 1100000,	/* 1.1V */
+		.buck2_voltage[7] = 1100000,	/* 1.1V */
+
+		.buck3_voltage[0] = 1100000,	/* 1.1V */
+		.buck3_voltage[1] = 1100000,	/* 1.1V */
+		.buck3_voltage[2] = 1100000,	/* 1.1V */
+		.buck3_voltage[3] = 1100000,	/* 1.1V */
+		.buck3_voltage[4] = 1100000,	/* 1.1V */
+		.buck3_voltage[5] = 1100000,	/* 1.1V */
+		.buck3_voltage[6] = 1100000,	/* 1.1V */
+		.buck3_voltage[7] = 1100000,	/* 1.1V */
+
+		.buck4_voltage[0] = 1100000,	/* 1.1V */
+		.buck4_voltage[1] = 1100000,	/* 1.1V */
+		.buck4_voltage[2] = 1100000,	/* 1.1V */
+		.buck4_voltage[3] = 1100000,	/* 1.1V */
+		.buck4_voltage[4] = 1100000,	/* 1.1V */
+		.buck4_voltage[5] = 1100000,	/* 1.1V */
+		.buck4_voltage[6] = 1100000,	/* 1.1V */
+		.buck4_voltage[7] = 1100000,	/* 1.1V */
+};
+#endif /* CONFIG_REGULATOR_MAX77686 */
+
+static struct i2c_board_info i2c_devs0[] __initdata = {
+#ifdef CONFIG_VIDEO_EXYNOS_TV
+	{
+		I2C_BOARD_INFO("exynos_hdcp", (0x74 >> 1)),
+	}
+#endif
+};
+
+#ifdef CONFIG_S3C_DEV_HWMON
+static struct s3c_hwmon_pdata smdk5250_hwmon_pdata __initdata = {
+	/* Reference voltage (1.2V) */
+	.in[0] = &(struct s3c_hwmon_chcfg) {
+		.name		= "smdk:reference-voltage",
+		.mult		= 3300,
+		.div		= 4096,
+	},
+};
+#endif
+
+#if defined(CONFIG_REGULATOR_MAX77686)
+static struct i2c_board_info i2c_devs5[] __initdata = {
+	{
+		I2C_BOARD_INFO("max77686", (0x12 >> 1)),
+		.platform_data	= &exynos4_max77686_info,
+	}
+};
+#endif
+
+#ifdef CONFIG_SENSORS_BH1721FVC
+
+static struct i2c_gpio_platform_data gpio_i2c_data12 = {
+	.sda_pin = GPIO_PS_ALS_SDA,
+	.scl_pin = GPIO_PS_ALS_SCL,
+};
+
+struct platform_device s3c_device_i2c12 = {
+	.name = "i2c-gpio",
+	.id = 12,
+	.dev.platform_data = &gpio_i2c_data12,
+};
+
+static int light_sensor_init(void)
+{
+	int err;
+
+	printk(KERN_INFO"==============================\n");
+	printk(KERN_INFO"== BH1721 Light Sensor Init ==\n");
+	printk(KERN_INFO"==============================\n");
+	printk("%d %d\n", GPIO_PS_ALS_SDA, GPIO_PS_ALS_SCL);
+	err = gpio_request(GPIO_PS_VOUT, "LIGHT_SENSOR_RESET");
+	if (err) {
+		printk(KERN_INFO" bh1721fvc Failed to request the light "
+			" sensor gpio (%d)\n", err);
+		return err;
+	}
+
+	s3c_gpio_cfgpin(GPIO_PS_VOUT, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_PS_VOUT, S3C_GPIO_PULL_NONE);
+
+	err = gpio_direction_output(GPIO_PS_VOUT, 0);
+	udelay(2);
+	err = gpio_direction_output(GPIO_PS_VOUT, 1);
+	if (err) {
+		printk(KERN_INFO" bh1721fvc Failed to make the light sensor gpio(reset)"
+			" high (%d)\n", err);
+		return err;
+	}
+
+	return 0;
+}
+
+static int  bh1721fvc_light_sensor_reset(void)
+{
+	int err;
+
+	printk(KERN_INFO" bh1721fvc_light_sensor_reset\n");
+	err = gpio_direction_output(GPIO_PS_VOUT, 0);
+	if (err) {
+		printk(KERN_INFO" bh1721fvc Failed to make the light sensor gpio(reset)"
+			" low (%d)\n", err);
+		return err;
+	}
+
+	udelay(2);
+
+	err = gpio_direction_output(GPIO_PS_VOUT, 1);
+	if (err) {
+		printk(KERN_INFO" bh1721fvc Failed to make the light sensor gpio(reset)"
+			" high (%d)\n", err);
+		return err;
+	}
+	return 0;
+}
+
+static int  bh1721fvc_light_sensor_output(int value)
+{
+	int err;
+	int gpio_vout = GPIO_PS_VOUT;
+
+	err = gpio_direction_output(GPIO_PS_VOUT, value);
+	if (err) {
+		printk(KERN_INFO" bh1721fvc Failed to make the light sensor gpio(dvi)"
+			" low (%d)\n", err);
+		return err;
+	}
+	return 0;
+}
+
+static struct bh1721fvc_platform_data bh1721fvc_pdata = {
+	.reset = bh1721fvc_light_sensor_reset,
+	/* .output = bh1721fvc_light_sensor_output, */
+};
+
+static struct i2c_board_info i2c_bh1721_emul[] __initdata = {
+	{
+		I2C_BOARD_INFO("bh1721fvc", 0x23),
+		.platform_data = &bh1721fvc_pdata,
+	},
+};
+#endif
+
+#ifdef CONFIG_SENSORS_SHT21
+
+static struct i2c_gpio_platform_data gpio_i2c_data13 = {
+	.sda_pin = GPIO_HUM_SDA,
+	.scl_pin = GPIO_HUM_SCL,
+};
+
+struct platform_device s3c_device_i2c13 = {
+	.name = "i2c-gpio",
+	.id = 13,
+	.dev.platform_data = &gpio_i2c_data13,
+};
+
+static struct i2c_board_info i2c_devs13[] __initdata = {
+	{
+		I2C_BOARD_INFO("sht21", 0x40),
+	},
+};
+
+#endif
+
+#if defined(CONFIG_SAMSUNG_MHL)
+static struct i2c_board_info i2c_devs15_emul[] __initdata = {
+};
+
+/* i2c-gpio emulation platform_data */
+static struct i2c_gpio_platform_data i2c15_platdata = {
+	.sda_pin		= GPIO_MHL_SDA_18V,
+	.scl_pin		= GPIO_MHL_SCL_18V,
+	.udelay			= 2,	/* 250 kHz*/
+	.sda_is_open_drain	= 0,
+	.scl_is_open_drain	= 0,
+	.scl_is_output_only	= 0,
+};
+
+static struct platform_device s3c_device_i2c15 = {
+	.name			= "i2c-gpio",
+	.id			= 15,
+	.dev.platform_data	= &i2c15_platdata,
+};
+
+#endif
+
+#ifdef CONFIG_MOTOR_DRV_ISA1200
+
+static int isa1200_vdd_en(bool en)
+{
+	return gpio_direction_output(GPIO_MOTOR_EN, en);
+}
+
+static struct i2c_gpio_platform_data gpio_i2c_data17 = {
+	.sda_pin = GPIO_MOTOR_SDA_18V,
+	.scl_pin = GPIO_MOTOR_SCL_18V,
+};
+
+struct platform_device s3c_device_i2c17 = {
+	.name = "i2c-gpio",
+	.id = 17,
+	.dev.platform_data = &gpio_i2c_data17,
+};
+
+static struct isa1200_vibrator_platform_data isa1200_vibrator_pdata = {
+	.gpio_en = isa1200_vdd_en,
+	.max_timeout = 10000,
+	.ctrl0 = CTL0_DIVIDER128 | CTL0_PWM_INPUT,
+	.ctrl1 = CTL1_DEFAULT,
+	.ctrl2 = 0,
+	.ctrl4 = 0,
+	.pll = 0,
+	.duty = 0,
+	.period = 0,
+	.get_clk = NULL,
+	.pwm_id = 1,
+	.pwm_duty = 37000,
+	.pwm_period = 38675,/*38109*/
+};
+static struct i2c_board_info i2c_devs17[] = {
+	{
+		I2C_BOARD_INFO("isa1200_vibrator",  0x48),
+		.platform_data = &isa1200_vibrator_pdata,
+	},
+};
+
+static void isa1200_init(void)
+{
+	int gpio, ret;
+
+	gpio = GPIO_MOTOR_EN;
+	gpio_request(gpio, "MOTOR_EN");
+	gpio_direction_output(gpio, 1);
+	gpio_export(gpio, 0);
+}
+#endif	/* CONFIG_MOTOR_DRV_ISA1200 */
+
+#ifdef CONFIG_30PIN_CONN
+
+static void __init acc_con_gpio_init(void)
+{
+	s3c_gpio_cfgpin(GPIO_DOCK_INT, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_DOCK_INT, S3C_GPIO_PULL_NONE);
+
+	s3c_gpio_cfgpin(GPIO_ACCESSORY_INT, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_ACCESSORY_INT, S3C_GPIO_PULL_NONE);
+}
+
+static int acc_dock_con_state(void)
+{
+	/* From ACCESSROY_INT like desktop dock */
+
+	return gpio_get_value(GPIO_ACCESSORY_INT);
+}
+
+static int acc_accessory_con_state(void)
+{
+
+	/* From ACCESSORY_ID pin */
+	return gpio_get_value(GPIO_DOCK_INT);
+}
+
+struct acc_con_platform_data acc_con_pdata = {
+    /*
+	.otg_en =
+	.acc_power =
+	.usb_ldo_en =
+    */
+	.get_dock_state = acc_dock_con_state,
+	.get_acc_state = acc_accessory_con_state,
+	.accessory_irq_gpio = GPIO_ACCESSORY_INT,
+	.dock_irq_gpio = GPIO_DOCK_INT,
+	.mhl_irq_gpio = GPIO_MHL_INT,
+	.hdmi_hpd_gpio = GPIO_HDMI_HPD,
+};
+struct platform_device sec_device_connector = {
+	.name = "acc_con",
+	.id = -1,
+	.dev.platform_data = &acc_con_pdata,
+};
+#endif
+
+#ifdef CONFIG_USB_EHCI_S5P
+static struct s5p_ehci_platdata smdk5250_ehci_pdata;
+
+static void __init smdk5250_ehci_init(void)
+{
+	struct s5p_ehci_platdata *pdata = &smdk5250_ehci_pdata;
+
+#ifndef CONFIG_USB_EXYNOS_SWITCH
+	if (samsung_rev() >= EXYNOS5250_REV_1_0) {
+		if (gpio_request_one(EXYNOS5_GPX2(6), GPIOF_OUT_INIT_HIGH,
+			"HOST_VBUS_CONTROL"))
+			printk(KERN_ERR "failed to request gpio_host_vbus\n");
+		else {
+			s3c_gpio_setpull(EXYNOS5_GPX2(6), S3C_GPIO_PULL_NONE);
+			gpio_free(EXYNOS5_GPX2(6));
+		}
+	}
+#endif
+
+	s5p_ehci_set_platdata(pdata);
+}
+#endif
+
+#ifdef CONFIG_USB_OHCI_S5P
+static struct s5p_ohci_platdata smdk5250_ohci_pdata;
+
+static void __init smdk5250_ohci_init(void)
+{
+	struct s5p_ohci_platdata *pdata = &smdk5250_ohci_pdata;
+
+	s5p_ohci_set_platdata(pdata);
+}
+#endif
+
+#if defined(CONFIG_CPU_EXYNOS5250)
+static void set_usb3_en(int enable)
+{
+	int err;
+	/* XMMC2CDN(USB3.0_EN) for P10 H/W */
+	err = gpio_request(EXYNOS5_GPC2(2), "USB3_EN");
+	if (err)
+		printk(KERN_ERR "usb: failed to request XMMC2CDN GPIO ####\n");
+
+	s3c_gpio_setpull(EXYNOS5_GPC2(2), S3C_GPIO_PULL_NONE);
+	gpio_direction_output(EXYNOS5_GPC2(2), enable);
+	gpio_free(EXYNOS5_GPC2(2));
+	printk(KERN_INFO "usb: set usb3_en gpio (%d)\n", enable);
+}
+#endif
+
+/* USB GADGET */
+#ifdef CONFIG_USB_S3C_OTGD
+static struct s5p_usbgadget_platdata smdk5250_usbgadget_pdata;
+
+static void __init smdk5250_usbgadget_init(void)
+{
+	struct s5p_usbgadget_platdata *pdata = &smdk5250_usbgadget_pdata;
+
+	s5p_usbgadget_set_platdata(pdata);
+}
+#endif
+
+#ifdef CONFIG_EXYNOS_DEV_SS_UDC
+static struct exynos_usb3_drd_pdata smdk5250_ss_udc_pdata;
+
+static void __init smdk5250_ss_udc_init(void)
+{
+	struct exynos_usb3_drd_pdata *pdata = &smdk5250_ss_udc_pdata;
+
+	exynos_ss_udc_set_platdata(pdata);
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_EXYNOS
+static struct exynos_usb3_drd_pdata smdk5250_xhci_pdata;
+
+static void __init smdk5250_xhci_init(void)
+{
+	struct exynos_usb3_drd_pdata *pdata = &smdk5250_xhci_pdata;
+
+	exynos_xhci_set_platdata(pdata);
+}
+#endif
+
+#ifdef CONFIG_BATTERY_SAMSUNG
+static struct platform_device samsung_device_battery = {
+	.name	= "samsung-fake-battery",
+	.id	= -1,
+};
+#endif
+
+#if defined(CONFIG_STMPE811_ADC)
+static struct i2c_gpio_platform_data gpio_i2c_data19 = {
+	.sda_pin = GPIO_ADC_SDA_18V,
+	.scl_pin = GPIO_ADC_SCL_18V,
+};
+
+struct platform_device s3c_device_i2c19 = {
+	.name = "i2c-gpio",
+	.id = 19,
+	.dev.platform_data = &gpio_i2c_data19,
+};
+
+
+/* I2C19 */
+static struct i2c_board_info i2c_devs19_emul[] __initdata = {
+	{
+		I2C_BOARD_INFO("stmpe811-adc", (0x82 >> 1)),
+		.platform_data	= &stmpe811_pdata,
+	},
+};
+#endif
+
+#ifdef CONFIG_BUSFREQ_OPP
+/* BUSFREQ to control memory/bus*/
+static struct device_domain busfreq;
+
+static struct platform_device exynos5_busfreq = {
+	.id = -1,
+	.name = "exynos-busfreq",
+};
+#endif
+
+/* Bluetooth */
+#ifdef CONFIG_BT_BCM43241
+static struct platform_device bcm43241_bluetooth_device = {
+	.name = "bcm43241_bluetooth",
+	.id = -1,
+};
+#endif
+
+static struct platform_device *p10_devices[] __initdata = {
+	/* Samsung Power Domain */
+#ifdef CONFIG_EXYNOS_DEV_PD
+	&exynos5_device_pd[PD_MFC],
+	&exynos5_device_pd[PD_G3D],
+	&exynos5_device_pd[PD_ISP],
+	&exynos5_device_pd[PD_GSCL],
+	&exynos5_device_pd[PD_DISP1],
+#endif
+
+#ifdef CONFIG_S5P_DP
+	&s5p_device_dp,
+#endif
+
+#ifdef CONFIG_FB_S3C
+	&s5p_device_fimd1,
+#endif
+
+#ifdef CONFIG_S5P_DP
+	&p10_dp_lcd,
+#endif
+
+#ifdef CONFIG_FB_S5P_EXTDSP
+	&s3c_device_extdsp,
+#endif
+
+	&s3c_device_wdt,
+
+#ifdef CONFIG_S3C_DEV_HSMMC
+	&s3c_device_hsmmc0,
+#endif
+
+#ifdef CONFIG_S3C_DEV_HSMMC1
+	&s3c_device_hsmmc1,
+#endif
+
+#ifdef CONFIG_S3C_DEV_HSMMC2
+	&s3c_device_hsmmc2,
+#endif
+
+#ifdef CONFIG_S3C_DEV_HSMMC3
+	&s3c_device_hsmmc3,
+#endif
+
+#ifdef CONFIG_VIDEO_SAMSUNG_S5P_MFC
+	&s5p_device_mfc,
+#endif
+
+#ifdef CONFIG_VIDEO_JPEG_V2X
+	&s5p_device_jpeg,
+#endif
+
+#ifdef CONFIG_EXYNOS4_DEV_DWMCI
+	&exynos_device_dwmci,
+#endif
+	&exynos_device_dwmci0,
+	&exynos_device_dwmci1,
+	&exynos_device_dwmci2,
+#ifdef CONFIG_ION_EXYNOS
+	&exynos_device_ion,
+#endif
+
+#ifdef CONFIG_VIDEO_FIMG2D
+	&s5p_device_fimg2d,
+#endif
+
+#ifdef CONFIG_EXYNOS_MEDIA_DEVICE
+	&exynos_device_md0,
+	&exynos_device_md1,
+	&exynos_device_md2,
+#endif
+
+#ifdef CONFIG_VIDEO_EXYNOS5_FIMC_IS
+	&exynos5_device_fimc_is,
+#endif
+
+#ifdef CONFIG_VIDEO_EXYNOS_GSCALER
+	&exynos5_device_gsc0,
+	&exynos5_device_gsc1,
+	&exynos5_device_gsc2,
+	&exynos5_device_gsc3,
+#endif
+
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_LITE
+	&exynos_device_flite0,
+	&exynos_device_flite1,
+	&exynos_device_flite2,
+#endif
+
+#ifdef CONFIG_VIDEO_EXYNOS_MIPI_CSIS
+	&s5p_device_mipi_csis0,
+	&s5p_device_mipi_csis1,
+	&mipi_csi_fixed_voltage,
+#endif
+
+#ifdef CONFIG_VIDEO_M5MOLS
+	&m5mols_fixed_voltage,
+#endif
+
+	&s3c_device_rtc,
+
+#ifdef CONFIG_HAVE_PWM
+	&s3c_device_timer[1],
+#endif
+
+#ifdef CONFIG_VIDEO_EXYNOS_TV
+#ifdef CONFIG_VIDEO_EXYNOS_HDMI
+	&s5p_device_hdmi,
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS_HDMIPHY
+	&s5p_device_i2c_hdmiphy,
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS_MIXER
+	&s5p_device_mixer,
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS_HDMI_CEC
+	&s5p_device_cec,
+#endif
+#endif
+	&s3c_device_i2c0,
+#ifdef CONFIG_MPU_SENSORS_MPU6050
+	&s3c_device_i2c1,
+#endif
+	&s3c_device_i2c3,
+	&s3c_device_i2c4,
+	&s3c_device_i2c5,
+	&s3c_device_i2c7,
+
+#ifdef CONFIG_USB_EHCI_S5P
+	&s5p_device_ehci,
+#endif
+
+#ifdef CONFIG_USB_OHCI_S5P
+	&s5p_device_ohci,
+#endif
+
+#ifdef CONFIG_USB_S3C_OTGD
+	&s3c_device_usbgadget,
+#endif
+
+#ifdef CONFIG_EXYNOS_DEV_SS_UDC
+	&exynos_device_ss_udc,
+#endif
+
+#ifdef CONFIG_USB_XHCI_EXYNOS
+	&exynos_device_xhci,
+#endif
+
+#ifdef CONFIG_BATTERY_SAMSUNG
+	&samsung_device_battery,
+#endif
+#ifdef CONFIG_MOTOR_DRV_ISA1200
+	&s3c_device_i2c17,
+#endif
+#if defined(CONFIG_STMPE811_ADC)
+	&s3c_device_i2c19,
+#endif
+#ifdef CONFIG_SND_SAMSUNG_I2S
+	&exynos_device_i2s0,
+#endif
+
+	&samsung_asoc_dma,
+	&samsung_asoc_idma,
+
+#ifdef CONFIG_SND_SAMSUNG_PCM
+	&exynos_device_pcm0,
+#endif
+
+#if defined(CONFIG_SND_SAMSUNG_RP) || defined(CONFIG_SND_SAMSUNG_ALP)
+	&exynos_device_srp,
+#endif
+
+#ifdef CONFIG_EXYNOS4_SETUP_THERMAL
+	&s5p_device_tmu,
+#endif
+
+#ifdef CONFIG_S5P_DEV_ACE
+	&s5p_device_ace,
+#endif
+
+#ifdef CONFIG_EXYNOS_C2C
+	&exynos_device_c2c,
+#endif
+
+#ifdef CONFIG_S3C64XX_DEV_SPI
+	&exynos_device_spi1,
+#endif
+
+#ifdef CONFIG_BUSFREQ_OPP
+	&exynos5_busfreq,
+#endif
+
+#ifdef CONFIG_MPU_SENSORS_MPU6050
+	&s3c_device_i2c11,
+#endif
+#ifdef CONFIG_SENSORS_BH1721FVC
+	&s3c_device_i2c12,
+#endif
+
+#ifdef CONFIG_SENSORS_SHT21
+	&s3c_device_i2c13,
+#endif
+
+#if defined(CONFIG_SAMSUNG_MHL)
+	&s3c_device_i2c15,	/* MHL */
+#endif
+
+#ifdef CONFIG_30PIN_CONN
+	&sec_device_connector,
+#endif
+
+#ifdef CONFIG_VIDEO_EXYNOS_ROTATOR
+	&exynos_device_rotator,
+#endif
+#ifdef CONFIG_BT_BCM43241
+	&bcm43241_bluetooth_device,
+#endif
+};
+
+#ifdef CONFIG_EXYNOS4_SETUP_THERMAL
+/* below temperature base on the celcius degree */
+struct s5p_platform_tmu exynos_tmu_data __initdata = {
+	.ts = {
+		.stop_1st_throttle  = 78,
+		.start_1st_throttle = 80,
+		.stop_2nd_throttle  = 87,
+		.start_2nd_throttle = 103,
+		.start_tripping = 110, /* temp to do tripping */
+		.start_emergency    = 120, /* To protect chip,forcely kernel panic */
+		.stop_mem_throttle  = 80,
+		.start_mem_throttle = 85,
+	},
+	.cpufreq = {
+		.limit_1st_throttle  = 800000, /* 800MHz in KHz order */
+		.limit_2nd_throttle  = 200000, /* 200MHz in KHz order */
+	},
+};
+
+#endif
+
+#ifdef CONFIG_VIDEO_EXYNOS_HDMI_CEC
+static struct s5p_platform_cec hdmi_cec_data __initdata = {
+
+};
+#endif
+
+#if defined(CONFIG_CMA)
+static void __init exynos_reserve_mem(void)
+{
+	static struct cma_region regions[] = {
+		{
+			.name = "ion",
+			.size = 256 * SZ_1M,
+			.start = 0
+		},
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_GSC0
+		{
+			.name = "gsc0",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_GSC0 * SZ_1K,
+			.start = 0
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_GSC1
+		{
+			.name = "gsc1",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_GSC1 * SZ_1K,
+			.start = 0
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_GSC2
+		{
+			.name = "gsc2",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_GSC2 * SZ_1K,
+			.start = 0
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_GSC3
+		{
+			.name = "gsc3",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_GSC3 * SZ_1K,
+			.start = 0
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FLITE0
+	       {
+		       .name = "flite0",
+		       .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FLITE0 * SZ_1K,
+		       .start = 0
+	       },
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FLITE1
+	       {
+		       .name = "flite1",
+		       .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FLITE1 * SZ_1K,
+		       .start = 0
+	       },
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMD
+		{
+			.name = "fimd",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMD * SZ_1K,
+			.start = 0
+		},
+#endif
+#ifdef CONFIG_AUDIO_SAMSUNG_MEMSIZE_SRP
+		{
+			.name = "srp",
+			.size = CONFIG_AUDIO_SAMSUNG_MEMSIZE_SRP * SZ_1K,
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_S5P_MFC
+		{
+			.name		= "fw",
+			.size		= 2 << 20,
+			{ .alignment	= 128 << 10 },
+			.start		= 0x44000000,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_TV
+		{
+			.name = "tv",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_TV * SZ_1K,
+			.start = 0
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_ROT
+		{
+			.name = "rot",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_ROT * SZ_1K,
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS5_FIMC_IS
+		{
+			.name = "fimc_is",
+			.size = CONFIG_VIDEO_EXYNOS_MEMSIZE_FIMC_IS * SZ_1K,
+			{
+				.alignment = 1 << 26,
+			},
+			.start = 0
+		},
+#endif
+		{
+			.size = 0
+		},
+	};
+	static const char map[] __initconst =
+#ifdef CONFIG_EXYNOS_C2C
+		"samsung-c2c=c2c_shdmem;"
+#endif
+		"s3cfb.0=fimd;"
+#ifdef CONFIG_AUDIO_SAMSUNG_MEMSIZE_SRP
+		"samsung-rp=srp;"
+#endif
+		"exynos-gsc.0=gsc0;exynos-gsc.1=gsc1;exynos-gsc.2=gsc2;exynos-gsc.3=gsc3;"
+		"exynos-fimc-lite.0=flite0;exynos-fimc-lite.1=flite1;"
+		"ion-exynos=ion,gsc0,gsc1,gsc2,gsc3,flite0,flite1,fimd,fw,rot;"
+		"exynos-rot=rot;"
+		"s5p-mfc-v6/f=fw;"
+		"s5p-mixer=tv;"
+		"exynos5-fimc-is=fimc_is;";
+
+    s5p_cma_region_reserve(regions, NULL, 0, map);
+}
+#else /* !CONFIG_CMA */
+static inline void exynos_reserve_mem(void)
+{
+}
+#endif
+
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_LITE
+static void __init smdk5250_camera_gpio_cfg(void)
+{
+	/* CAM A port(b0010) : PCLK, VSYNC, HREF, CLK_OUT */
+	s3c_gpio_cfgrange_nopull(EXYNOS5_GPH0(0), 4, S3C_GPIO_SFN(2));
+	/* CAM A port(b0010) : DATA[0-7] */
+	s3c_gpio_cfgrange_nopull(EXYNOS5_GPH1(0), 8, S3C_GPIO_SFN(2));
+	/* CAM B port(b0010) : PCLK, BAY_RGB[0-6] */
+	s3c_gpio_cfgrange_nopull(EXYNOS5_GPG0(0), 8, S3C_GPIO_SFN(2));
+	/* CAM B port(b0010) : BAY_Vsync, BAY_RGB[7-13] */
+	s3c_gpio_cfgrange_nopull(EXYNOS5_GPG1(0), 8, S3C_GPIO_SFN(2));
+	/* CAM B port(b0010) : BAY_Hsync, BAY_MCLK */
+	s3c_gpio_cfgrange_nopull(EXYNOS5_GPG2(0), 2, S3C_GPIO_SFN(2));
+	/* This is externel interrupt for m5mo */
+#ifdef CONFIG_VIDEO_M5MOLS
+	s3c_gpio_cfgpin(EXYNOS5_GPX2(6), S3C_GPIO_SFN(0xF));
+	s3c_gpio_setpull(EXYNOS5_GPX2(6), S3C_GPIO_PULL_NONE);
+#endif
+}
+#endif
+
+#if defined(CONFIG_VIDEO_EXYNOS_GSCALER) && defined(CONFIG_VIDEO_EXYNOS_FIMC_LITE)
+#if defined(CONFIG_VIDEO_S5K4BA)
+static struct exynos_isp_info s5k4ba = {
+	.board_info	= &s5k4ba_info,
+	.cam_srclk_name	= "xxti",
+	.clk_frequency	= 24000000UL,
+	.bus_type	= CAM_TYPE_ITU,
+#ifdef CONFIG_ITU_A
+	.cam_clk_name	= "sclk_cam0",
+	.i2c_bus_num	= 4,
+	.cam_port	= CAM_PORT_A, /* A-Port : 0, B-Port : 1 */
+#endif
+#ifdef CONFIG_ITU_B
+	.cam_clk_name	= "sclk_cam1",
+	.i2c_bus_num	= 5,
+	.cam_port	= CAM_PORT_B, /* A-Port : 0, B-Port : 1 */
+#endif
+	.flags		= CAM_CLK_INV_VSYNC,
+};
+/* This is for platdata of fimc-lite */
+static struct s3c_platform_camera flite_s5k4ba = {
+	.type		= CAM_TYPE_MIPI,
+	.use_isp	= true,
+	.inv_pclk	= 1,
+	.inv_vsync	= 1,
+	.inv_href	= 0,
+	.inv_hsync	= 0,
+};
+#endif
+#if defined(CONFIG_VIDEO_M5MOLS)
+static struct exynos_isp_info m5mols = {
+	.board_info	= &m5mols_board_info,
+	.cam_srclk_name	= "xxti",
+	.clk_frequency	= 24000000UL,
+	.bus_type	= CAM_TYPE_MIPI,
+#ifdef CONFIG_CSI_C
+	.cam_clk_name	= "sclk_cam0",
+	.i2c_bus_num	= 4,
+	.cam_port	= CAM_PORT_A, /* A-Port : 0, B-Port : 1 */
+#endif
+#ifdef CONFIG_CSI_D
+	.cam_clk_name	= "sclk_cam1",
+	.i2c_bus_num	= 5,
+	.cam_port	= CAM_PORT_B, /* A-Port : 0, B-Port : 1 */
+#endif
+	.flags		= CAM_CLK_INV_PCLK | CAM_CLK_INV_VSYNC,
+	.csi_data_align = 32,
+};
+/* This is for platdata of fimc-lite */
+static struct s3c_platform_camera flite_m5mo = {
+	.type		= CAM_TYPE_MIPI,
+	.use_isp	= true,
+	.inv_pclk	= 1,
+	.inv_vsync	= 1,
+	.inv_href	= 0,
+	.inv_hsync	= 0,
+};
+#endif
+
+static void __set_gsc_camera_config(struct exynos_platform_gscaler *data,
+					u32 active_index, u32 preview,
+					u32 camcording, u32 max_cam)
+{
+	data->active_cam_index = active_index;
+	data->cam_preview = preview;
+	data->cam_camcording = camcording;
+	data->num_clients = max_cam;
+}
+
+static void __set_flite_camera_config(struct exynos_platform_flite *data,
+					u32 active_index, u32 max_cam)
+{
+	data->active_cam_index = active_index;
+	data->num_clients = max_cam;
+}
+
+static void __init smdk5250_set_camera_platdata(void)
+{
+	int gsc_cam_index = 0;
+	int flite0_cam_index = 0;
+	int flite1_cam_index = 0;
+#if defined(CONFIG_VIDEO_M5MOLS)
+	exynos_gsc0_default_data.isp_info[gsc_cam_index++] = &m5mols;
+#if defined(CONFIG_CSI_C)
+	exynos_flite0_default_data.cam[flite0_cam_index] = &flite_m5mo;
+	exynos_flite0_default_data.isp_info[flite0_cam_index] = &m5mols;
+	flite0_cam_index++;
+#endif
+#if defined(CONFIG_CSI_D)
+	exynos_flite1_default_data.cam[flite1_cam_index] = &flite_m5mo;
+	exynos_flite1_default_data.isp_info[flite1_cam_index] = &m5mols;
+	flite1_cam_index++;
+#endif
+#endif
+	/* flite platdata register */
+	__set_flite_camera_config(&exynos_flite0_default_data, 0, flite0_cam_index);
+	__set_flite_camera_config(&exynos_flite1_default_data, 0, flite1_cam_index);
+
+	/* gscaler platdata register */
+	/* GSC-0 */
+	__set_gsc_camera_config(&exynos_gsc0_default_data, 0, 1, 0, gsc_cam_index);
+
+	/* GSC-1 */
+	/* GSC-2 */
+	/* GSC-3 */
+}
+#endif /* CONFIG_VIDEO_EXYNOS_GSCALER */
+
+static void __init p10_map_io(void)
+{
+	s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+	s3c24xx_init_clocks(24000000);
+	s3c24xx_init_uarts(smdk5250_uartcfgs, ARRAY_SIZE(smdk5250_uartcfgs));
+	exynos_reserve_mem();
+
+#if defined(CONFIG_SEC_DEBUG)
+	/* as soon as INFORM6 is visible, sec_debug is ready to run */
+	sec_debug_init();
+#endif
+}
+
+#ifdef CONFIG_EXYNOS_DEV_SYSMMU
+static void __init exynos_sysmmu_init(void)
+{
+#ifdef CONFIG_VIDEO_JPEG_V2X
+	platform_set_sysmmu(&SYSMMU_PLATDEV(jpeg).dev, &s5p_device_jpeg.dev);
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_S5P_MFC
+	platform_set_sysmmu(&SYSMMU_PLATDEV(mfc_lr).dev, &s5p_device_mfc.dev);
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS_TV
+	platform_set_sysmmu(&SYSMMU_PLATDEV(tv).dev, &s5p_device_mixer.dev);
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS_GSCALER
+	platform_set_sysmmu(&SYSMMU_PLATDEV(gsc0).dev,
+						&exynos5_device_gsc0.dev);
+	platform_set_sysmmu(&SYSMMU_PLATDEV(gsc1).dev,
+						&exynos5_device_gsc1.dev);
+	platform_set_sysmmu(&SYSMMU_PLATDEV(gsc2).dev,
+						&exynos5_device_gsc2.dev);
+	platform_set_sysmmu(&SYSMMU_PLATDEV(gsc3).dev,
+						&exynos5_device_gsc3.dev);
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_LITE
+	platform_set_sysmmu(&SYSMMU_PLATDEV(camif0).dev,
+					   &exynos_device_flite0.dev);
+	platform_set_sysmmu(&SYSMMU_PLATDEV(camif1).dev,
+					   &exynos_device_flite1.dev);
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS_ROTATOR
+	platform_set_sysmmu(&SYSMMU_PLATDEV(rot).dev,
+						&exynos_device_rotator.dev);
+#endif
+#ifdef CONFIG_VIDEO_FIMG2D
+	platform_set_sysmmu(&SYSMMU_PLATDEV(2d).dev, &s5p_device_fimg2d.dev);
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS5_FIMC_IS
+	platform_set_sysmmu(&SYSMMU_PLATDEV(isp).dev,
+						&exynos5_device_fimc_is.dev);
+#endif
+}
+#else /* !CONFIG_EXYNOS_DEV_SYSMMU */
+static inline void exynos_sysmmu_init(void)
+{
+}
+#endif
+
+static void p10_power_off(void)
+{
+	printk(KERN_EMERG "%s: set PS_HOLD low\n", __func__);
+
+	writel(readl(EXYNOS5_PS_HOLD_CONTROL) & 0xFFFFFEFF, EXYNOS5_PS_HOLD_CONTROL);
+	printk(KERN_EMERG "%s: Should not reach here\n", __func__);
+}
+
+#ifdef CONFIG_FB_S5P_EXTDSP
+struct platform_device s3c_device_extdsp = {
+	.name		= "s3cfb_extdsp",
+	.id		= 0,
+};
+
+static struct s3cfb_extdsp_lcd dummy_buffer = {
+	.width = 1920,
+	.height = 1080,
+	.bpp = 16,
+};
+
+static struct s3c_platform_fb default_extdsp_data __initdata = {
+	.hw_ver		= 0x70,
+	.nr_wins	= 1,
+	.default_win	= 0,
+	.swap		= FB_SWAP_WORD | FB_SWAP_HWORD,
+	.lcd		= &dummy_buffer
+};
+
+void __init s3cfb_extdsp_set_platdata(struct s3c_platform_fb *pd)
+{
+	struct s3c_platform_fb *npd;
+	int i;
+
+	if (!pd)
+		pd = &default_extdsp_data;
+
+	npd = kmemdup(pd, sizeof(struct s3c_platform_fb), GFP_KERNEL);
+	if (!npd)
+		printk(KERN_ERR "%s: no memory for platform data\n", __func__);
+	else {
+		for (i = 0; i < npd->nr_wins; i++)
+			npd->nr_buffers[i] = 1;
+		s3c_device_extdsp.dev.platform_data = npd;
+	}
+}
+#endif
+
+static void camera_init(void)
+{
+	camera_class = class_create(THIS_MODULE, "camera");
+
+	if (IS_ERR(camera_class))
+		pr_err("Failed to create class(camera)!\n");
+}
+
+static void __init p10_machine_init(void)
+{
+#ifdef CONFIG_S3C64XX_DEV_SPI
+	struct clk *sclk = NULL;
+	struct clk *prnt = NULL;
+	struct device *spi1_dev = &exynos_device_spi1.dev;
+#endif
+	pm_power_off = p10_power_off;
+
+	if (samsung_rev() >= EXYNOS5250_REV_1_0) {
+		exynos_dwmci_set_platdata(&exynos5_dwmci0_pdata, 0);
+		dev_set_name(&exynos_device_dwmci0.dev, "s3c-sdhci.0");
+		clk_add_alias("dwmci", "dw_mmc.0", "hsmmc",
+			&exynos_device_dwmci0.dev);
+		clk_add_alias("sclk_dwmci", "dw_mmc.0", "sclk_mmc",
+			&exynos_device_dwmci0.dev);
+
+		exynos_dwmci_set_platdata(&exynos5_dwmci1_pdata, 1);
+		dev_set_name(&exynos_device_dwmci1.dev, "s3c-sdhci.1");
+		clk_add_alias("dwmci", "dw_mmc.1", "hsmmc",
+			&exynos_device_dwmci1.dev);
+		clk_add_alias("sclk_dwmci", "dw_mmc.1", "sclk_mmc",
+			&exynos_device_dwmci1.dev);
+
+		exynos_dwmci_set_platdata(&exynos5_dwmci2_pdata, 2);
+		dev_set_name(&exynos_device_dwmci2.dev, "s3c-sdhci.2");
+		clk_add_alias("dwmci", "dw_mmc.2", "hsmmc",
+			&exynos_device_dwmci2.dev);
+		clk_add_alias("sclk_dwmci", "dw_mmc.2", "sclk_mmc",
+			&exynos_device_dwmci2.dev);
+	} else {
+#ifdef CONFIG_EXYNOS4_DEV_DWMCI
+	exynos_dwmci_set_platdata(&exynos_dwmci_pdata, 0);
+#endif
+
+#ifdef CONFIG_S3C_DEV_HSMMC
+	s3c_sdhci0_set_platdata(&smdk5250_hsmmc0_pdata);
+#endif
+
+#ifdef CONFIG_S3C_DEV_HSMMC1
+	s3c_sdhci1_set_platdata(&smdk5250_hsmmc1_pdata);
+#endif
+
+#ifdef CONFIG_S3C_DEV_HSMMC2
+	s3c_sdhci2_set_platdata(&smdk5250_hsmmc2_pdata);
+#endif
+
+#ifdef CONFIG_S3C_DEV_HSMMC3
+	s3c_sdhci3_set_platdata(&smdk5250_hsmmc3_pdata);
+#endif
+    }
+#ifdef CONFIG_ION_EXYNOS
+	exynos_ion_set_platdata();
+#endif
+
+#ifdef CONFIG_LEDS_SPFCW043
+	platform_device_register(&s3c_device_spfcw043_led);
+#endif
+
+#ifdef CONFIG_FB_S3C
+	dev_set_name(&s5p_device_fimd1.dev, "s3cfb.1");
+	clk_add_alias("lcd", "exynos5-fb.1", "lcd", &s5p_device_fimd1.dev);
+	clk_add_alias("sclk_fimd", "exynos5-fb.1", "sclk_fimd",
+			&s5p_device_fimd1.dev);
+	s5p_fb_setname(1, "exynos5-fb");
+
+	s5p_fimd1_set_platdata(&p10_lcd1_pdata);
+#endif
+
+#ifdef CONFIG_FB_S5P_EXTDSP
+	s3cfb_extdsp_set_platdata(&default_extdsp_data);
+#endif
+
+#ifdef CONFIG_BACKLIGHT_PWM
+	samsung_bl_set(&p10_bl_gpio_info, &p10_bl_data);
+#endif
+
+#ifdef CONFIG_USB_EHCI_S5P
+	smdk5250_ehci_init();
+#endif
+
+#ifdef CONFIG_USB_OHCI_S5P
+	smdk5250_ohci_init();
+#endif
+
+#if defined(CONFIG_CPU_EXYNOS5250)
+	set_usb3_en(1);
+#endif
+
+#ifdef CONFIG_USB_S3C_OTGD
+	smdk5250_usbgadget_init();
+#endif
+
+#ifdef CONFIG_EXYNOS_DEV_SS_UDC
+	smdk5250_ss_udc_init();
+#endif
+
+#ifdef CONFIG_USB_XHCI_EXYNOS
+	smdk5250_xhci_init();
+#endif
+
+#if defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC)
+#if defined(CONFIG_EXYNOS_DEV_PD)
+	s5p_device_mfc.dev.parent = &exynos5_device_pd[PD_MFC].dev;
+#endif
+	s5p_mfc_set_platdata(&smdk5250_mfc_pd);
+
+	dev_set_name(&s5p_device_mfc.dev, "s3c-mfc");
+	clk_add_alias("mfc", "s5p-mfc-v6", "mfc", &s5p_device_mfc.dev);
+	s5p_mfc_setname(&s5p_device_mfc, "s5p-mfc-v6");
+#endif
+
+#ifdef CONFIG_FB_S3C
+	s5p_device_fimd1.dev.parent = &exynos5_device_pd[PD_DISP1].dev;
+#endif
+
+#ifdef CONFIG_S5P_DP
+	s5p_dp_set_platdata(&p10_dp_data);
+#endif
+
+#ifdef CONFIG_S3C_ADC
+	if (samsung_rev() >= EXYNOS5250_REV_1_0) {
+		platform_device_register(&s3c_device_adc);
+#ifdef CONFIG_S3C_DEV_HWMON
+		platform_device_register(&s3c_device_hwmon);
+#endif
+	}
+#endif
+
+#ifdef CONFIG_S3C_DEV_HWMON
+	if (samsung_rev() >= EXYNOS5250_REV_1_0)
+		s3c_hwmon_set_platdata(&smdk5250_hwmon_pdata);
+#endif
+
+#ifdef CONFIG_VIDEO_FIMG2D
+	s5p_fimg2d_set_platdata(&fimg2d_data);
+#endif
+
+	exynos_sysmmu_init();
+
+	p10_config_gpio_table();
+
+	exynos5_sleep_gpio_table_set = p10_config_sleep_gpio_table;
+
+	s3c_i2c0_set_platdata(NULL);
+	i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
+
+#ifdef CONFIG_MPU_SENSORS_MPU6050
+	pr_info("MPU6050 I2C-1 Init\n");
+	//magnetic_init();
+	s3c_i2c1_set_platdata(NULL);
+	i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
+#endif
+
+	p10_tsp_init();
+	p10_key_init();
+
+	s3c_i2c5_set_platdata(NULL);
+	i2c_register_board_info(5, i2c_devs5, ARRAY_SIZE(i2c_devs5));
+
+	midas_sound_init();
+
+#ifdef CONFIG_MPU_SENSORS_MPU6050
+	magnetic_init();
+	i2c_register_board_info(11, i2c_devs11, ARRAY_SIZE(i2c_devs11));
+#endif
+
+#ifdef CONFIG_SENSORS_BH1721FVC
+	light_sensor_init();
+	i2c_register_board_info(12, i2c_bh1721_emul, ARRAY_SIZE(i2c_bh1721_emul));
+#endif
+
+#ifdef CONFIG_SENSORS_SHT21
+	i2c_register_board_info(13, i2c_devs13, ARRAY_SIZE(i2c_devs13));
+#endif
+
+#if defined(CONFIG_SAMSUNG_MHL)
+	i2c_register_board_info(15, i2c_devs15_emul,
+			ARRAY_SIZE(i2c_devs15_emul));
+#endif
+
+#ifdef CONFIG_MOTOR_DRV_ISA1200
+	isa1200_init();
+	i2c_register_board_info(17, i2c_devs17,
+				ARRAY_SIZE(i2c_devs17));
+#endif
+
+#if defined(CONFIG_STMPE811_ADC)
+	i2c_register_board_info(19, i2c_devs19_emul,
+		ARRAY_SIZE(i2c_devs19_emul));
+#endif
+#if defined(CONFIG_BATTERY_SAMSUNG_P1X)
+	p10_battery_init();
+#endif
+
+	platform_device_register(&vbatt_device);
+
+	platform_add_devices(p10_devices, ARRAY_SIZE(p10_devices));
+
+#ifdef CONFIG_FB_S3C
+#if defined(CONFIG_MACH_P10_DP_01)
+#if defined(CONFIG_DP_40HZ_P10)
+	exynos4_fimd_setup_clock(&s5p_device_fimd1.dev, "sclk_fimd", "sclk_vpll",
+			180 * MHZ);
+#elif defined(CONFIG_DP_60HZ_P10)
+	exynos4_fimd_setup_clock(&s5p_device_fimd1.dev, "sclk_fimd", "sclk_vpll",
+		270 * MHZ);
+#endif
+#endif
+#endif
+
+#ifdef CONFIG_VIDEO_EXYNOS_MIPI_CSIS
+#if defined(CONFIG_EXYNOS_DEV_PD)
+	s5p_device_mipi_csis0.dev.parent = &exynos5_device_pd[PD_GSCL].dev;
+	s5p_device_mipi_csis1.dev.parent = &exynos5_device_pd[PD_GSCL].dev;
+#endif
+	s3c_set_platdata(&s5p_mipi_csis0_default_data,
+			sizeof(s5p_mipi_csis0_default_data), &s5p_device_mipi_csis0);
+	s3c_set_platdata(&s5p_mipi_csis1_default_data,
+			sizeof(s5p_mipi_csis1_default_data), &s5p_device_mipi_csis1);
+#endif
+
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_LITE
+#if defined(CONFIG_EXYNOS_DEV_PD)
+	exynos_device_flite0.dev.parent = &exynos5_device_pd[PD_GSCL].dev;
+	exynos_device_flite1.dev.parent = &exynos5_device_pd[PD_GSCL].dev;
+	exynos_device_flite2.dev.parent = &exynos5_device_pd[PD_GSCL].dev;
+#endif
+	smdk5250_camera_gpio_cfg();
+	smdk5250_set_camera_platdata();
+	s3c_set_platdata(&exynos_flite0_default_data,
+			sizeof(exynos_flite0_default_data), &exynos_device_flite0);
+	s3c_set_platdata(&exynos_flite1_default_data,
+			sizeof(exynos_flite1_default_data), &exynos_device_flite1);
+	s3c_set_platdata(&exynos_flite2_default_data,
+			sizeof(exynos_flite2_default_data), &exynos_device_flite2);
+
+/* In EVT0, for using camclk, gscaler clock should be enabled */
+	if (samsung_rev() < EXYNOS5250_REV_1_0) {
+		dev_set_name(&exynos_device_flite0.dev, "exynos-gsc.0");
+		clk_add_alias("gscl", "exynos-fimc-lite.0", "gscl",
+				&exynos_device_flite0.dev);
+		dev_set_name(&exynos_device_flite0.dev, "exynos-fimc-lite.0");
+
+		dev_set_name(&exynos_device_flite1.dev, "exynos-gsc.0");
+		clk_add_alias("gscl", "exynos-fimc-lite.1", "gscl",
+				&exynos_device_flite1.dev);
+		dev_set_name(&exynos_device_flite1.dev, "exynos-fimc-lite.1");
+	}
+#endif
+
+#if defined CONFIG_VIDEO_EXYNOS5_FIMC_IS
+	dev_set_name(&exynos5_device_fimc_is.dev, "s5p-mipi-csis.0");
+	clk_add_alias("gscl_wrap0", "exynos5-fimc-is", "gscl_wrap0", &exynos5_device_fimc_is.dev);
+	clk_add_alias("sclk_gscl_wrap0", "exynos5-fimc-is", "sclk_gscl_wrap0", &exynos5_device_fimc_is.dev);
+	dev_set_name(&exynos5_device_fimc_is.dev, "s5p-mipi-csis.1");
+	clk_add_alias("gscl_wrap1", "exynos5-fimc-is", "gscl_wrap1", &exynos5_device_fimc_is.dev);
+	clk_add_alias("sclk_gscl_wrap1", "exynos5-fimc-is", "sclk_gscl_wrap1", &exynos5_device_fimc_is.dev);
+	dev_set_name(&exynos5_device_fimc_is.dev, "exynos-gsc.0");
+	clk_add_alias("gscl", "exynos5-fimc-is", "gscl", &exynos5_device_fimc_is.dev);
+	dev_set_name(&exynos5_device_fimc_is.dev, "exynos5-fimc-is");
+
+#if defined CONFIG_VIDEO_S5K6A3
+	exynos5_fimc_is_data.sensor_info[s5k6a3.sensor_position] = &s5k6a3;
+	printk("add s5k6a3 sensor info(pos : %d)\n", s5k6a3.sensor_position);
+#endif
+#if defined CONFIG_VIDEO_S5K4E5
+	exynos5_fimc_is_data.sensor_info[s5k4e5.sensor_position] = &s5k4e5;
+	printk("add s5k4e5 sensor info(pos : %d)\n", s5k4e5.sensor_position);
+#endif
+
+	exynos5_fimc_is_set_platdata(&exynos5_fimc_is_data);
+#if defined(CONFIG_EXYNOS_DEV_PD)
+	exynos5_device_pd[PD_ISP].dev.parent = &exynos5_device_pd[PD_GSCL].dev;
+	exynos5_device_fimc_is.dev.parent = &exynos5_device_pd[PD_ISP].dev;
+#endif
+#endif
+#ifdef CONFIG_EXYNOS4_SETUP_THERMAL
+	s5p_tmu_set_platdata(&exynos_tmu_data);
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS_GSCALER
+#if defined(CONFIG_EXYNOS_DEV_PD)
+	exynos5_device_gsc0.dev.parent = &exynos5_device_pd[PD_GSCL].dev;
+	exynos5_device_gsc1.dev.parent = &exynos5_device_pd[PD_GSCL].dev;
+	exynos5_device_gsc2.dev.parent = &exynos5_device_pd[PD_GSCL].dev;
+	exynos5_device_gsc3.dev.parent = &exynos5_device_pd[PD_GSCL].dev;
+#endif
+
+	if (samsung_rev() >= EXYNOS5250_REV_1_0) {
+		exynos5_gsc_set_pdev_name(0, "exynos5250-gsc");
+		exynos5_gsc_set_pdev_name(1, "exynos5250-gsc");
+		exynos5_gsc_set_pdev_name(2, "exynos5250-gsc");
+		exynos5_gsc_set_pdev_name(3, "exynos5250-gsc");
+	}
+
+	s3c_set_platdata(&exynos_gsc0_default_data, sizeof(exynos_gsc0_default_data),
+			&exynos5_device_gsc0);
+	s3c_set_platdata(&exynos_gsc1_default_data, sizeof(exynos_gsc1_default_data),
+			&exynos5_device_gsc1);
+	s3c_set_platdata(&exynos_gsc2_default_data, sizeof(exynos_gsc2_default_data),
+			&exynos5_device_gsc2);
+	s3c_set_platdata(&exynos_gsc3_default_data, sizeof(exynos_gsc3_default_data),
+			&exynos5_device_gsc3);
+	/* Gscaler can use MPLL(266MHz) or VPLL(300MHz).
+	In case of P10, Gscaler should use MPLL(266MHz) because FIMD uses VPLL(86MHz).
+	So mout_aclk_300_gscl_mid selects mout_mpll_user and then
+	mout_aclk_300_gscl_mid is set to 267MHz
+	even though the clock name(dout_aclk_300_gscl) implies and requires around 300MHz
+	*/
+	exynos5_gsc_set_parent_clock("mout_aclk_300_gscl_mid", "mout_mpll_user");
+	exynos5_gsc_set_parent_clock("mout_aclk_300_gscl", "mout_aclk_300_gscl_mid");
+	exynos5_gsc_set_parent_clock("aclk_300_gscl", "dout_aclk_300_gscl");
+	exynos5_gsc_set_clock_rate("dout_aclk_300_gscl", 267000000);
+#endif
+
+#ifdef CONFIG_EXYNOS_C2C
+	exynos_c2c_set_platdata(&smdk5250_c2c_pdata);
+#endif
+
+#ifdef CONFIG_VIDEO_JPEG_V2X
+	exynos5_jpeg_setup_clock(&s5p_device_jpeg.dev, 150000000);
+#endif
+
+#if defined(CONFIG_VIDEO_EXYNOS_TV) && defined(CONFIG_VIDEO_EXYNOS_HDMI)
+	dev_set_name(&s5p_device_hdmi.dev, "exynos5-hdmi");
+	clk_add_alias("hdmi", "s5p-hdmi", "hdmi", &s5p_device_hdmi.dev);
+	clk_add_alias("hdmiphy", "s5p-hdmi", "hdmiphy", &s5p_device_hdmi.dev);
+
+	s5p_tv_setup();
+
+/* setup dependencies between TV devices */
+	/* This will be added after power domain for exynos5 is developed */
+	s5p_device_hdmi.dev.parent = &exynos5_device_pd[PD_DISP1].dev;
+	s5p_device_mixer.dev.parent = &exynos5_device_pd[PD_DISP1].dev;
+
+	s5p_i2c_hdmiphy_set_platdata(NULL);
+#ifdef CONFIG_VIDEO_EXYNOS_HDMI_CEC
+	s5p_hdmi_cec_set_platdata(&hdmi_cec_data);
+#endif
+#endif
+
+#ifdef CONFIG_S3C64XX_DEV_SPI
+	sclk = clk_get(spi1_dev, "sclk_spi1");
+	if (IS_ERR(sclk))
+		dev_err(spi1_dev, "failed to get sclk for SPI-1\n");
+	prnt = clk_get(spi1_dev, "mout_mpll_user");
+	if (IS_ERR(prnt))
+		dev_err(spi1_dev, "failed to get prnt\n");
+	if (clk_set_parent(sclk, prnt))
+		printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
+				prnt->name, sclk->name);
+
+	clk_set_rate(sclk, 800 * 1000 * 1000);
+	clk_put(sclk);
+	clk_put(prnt);
+
+	if (!gpio_request(GPIO_5M_SPI_CS, "SPI_CS1")) {
+		gpio_direction_output(GPIO_5M_SPI_CS, 1);
+		s3c_gpio_cfgpin(GPIO_5M_SPI_CS, S3C_GPIO_SFN(1));
+		s3c_gpio_setpull(GPIO_5M_SPI_CS, S3C_GPIO_PULL_UP);
+		exynos_spi_set_info(1, EXYNOS_SPI_SRCCLK_SCLK,
+			ARRAY_SIZE(spi1_csi));
+	}
+
+	spi_register_board_info(spi1_board_info, ARRAY_SIZE(spi1_board_info));
+#endif
+
+#ifdef CONFIG_BUSFREQ_OPP
+	dev_add(&busfreq, &exynos5_busfreq.dev);
+	ppmu_init(&exynos_ppmu[PPMU_CPU], &exynos5_busfreq.dev);
+	ppmu_init(&exynos_ppmu[PPMU_DDR_C], &exynos5_busfreq.dev);
+	ppmu_init(&exynos_ppmu[PPMU_DDR_R1], &exynos5_busfreq.dev);
+	ppmu_init(&exynos_ppmu[PPMU_DDR_L], &exynos5_busfreq.dev);
+	ppmu_init(&exynos_ppmu[PPMU_RIGHT0_BUS], &exynos5_busfreq.dev);
+#endif
+#ifdef CONFIG_30PIN_CONN
+	acc_con_gpio_init();
+#endif
+
+	/* for BRCM Wi-Fi */
+	brcm_wlan_init();
+
+	/* for camera*/
+	camera_init();
+
+	register_reboot_notifier(&exynos5_reboot_notifier);
+}
+
+#ifdef CONFIG_EXYNOS_C2C
+static void __init exynos_c2c_reserve(void)
+{
+	static struct cma_region regions[] = {
+		{
+			.name = "c2c_shdmem",
+			.size = 64 * SZ_1M,
+			{ .alignment	= 64 * SZ_1M },
+			.start = C2C_SHAREDMEM_BASE
+		}, {
+			.size = 0,
+		}
+	};
+
+	s5p_cma_region_reserve(regions, NULL, 0, map);
+}
+#endif
+
+#if defined(CONFIG_SEC_DEBUG)
+static void __init exynos_init_reserve(void)
+{
+	sec_debug_magic_init();
+}
+#endif
+
+MACHINE_START(SMDK5250, "SMDK5250")
+	.boot_params	= S5P_PA_SDRAM + 0x100,
+	.init_irq	= exynos5_init_irq,
+	.map_io		= p10_map_io,
+	.init_machine	= p10_machine_init,
+	.timer		= &exynos4_timer,
+#ifdef CONFIG_EXYNOS_C2C
+	.reserve	= &exynos_c2c_reserve,
+#endif
+#if defined(CONFIG_SEC_DEBUG)
+	.init_early	= &exynos_init_reserve,
+#endif
+MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-p4notepq.c b/arch/arm/mach-exynos/mach-p4notepq.c
new file mode 100644
index 0000000..fc349c1
--- /dev/null
+++ b/arch/arm/mach-exynos/mach-p4notepq.c
@@ -0,0 +1,2561 @@
+/* linux/arch/arm/mach-exynos/mach-smdk4212.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/serial_core.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi_gpio.h>
+#include <linux/clk.h>
+#include <linux/gpio.h>
+#include <linux/gpio_event.h>
+#include <linux/i2c.h>
+#include <linux/i2c-gpio.h>
+#include <linux/pwm_backlight.h>
+#include <linux/input.h>
+#include <linux/mmc/host.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/max8649.h>
+#include <linux/regulator/fixed.h>
+#ifdef CONFIG_LEDS_AAT1290A
+#include <linux/leds-aat1290a.h>
+#endif
+
+#ifdef CONFIG_MFD_MAX77693
+#include <linux/mfd/max77693.h>
+#include <linux/mfd/max77693-private.h>
+#include <linux/leds-max77693.h>
+#endif
+
+#ifdef CONFIG_BATTERY_MAX17042_FUELGAUGE_PX
+#include <linux/power/max17042_fuelgauge_px.h>
+#endif
+#ifdef CONFIG_SMB347_CHARGER
+#include <linux/power/smb347_charger.h>
+#endif
+#ifdef CONFIG_BATTERY_SEC_PX
+#include <linux/power/sec_battery_px.h>
+#endif
+#include <linux/power_supply.h>
+#ifdef CONFIG_STMPE811_ADC
+#include <linux/stmpe811-adc.h>
+#endif
+#include <linux/v4l2-mediabus.h>
+#include <linux/memblock.h>
+#include <linux/delay.h>
+#include <linux/bootmem.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <plat/regs-serial.h>
+#include <plat/exynos4.h>
+#include <plat/cpu.h>
+#include <plat/clock.h>
+#include <plat/keypad.h>
+#include <plat/devs.h>
+#include <plat/fb-s5p.h>
+#include <plat/fb-core.h>
+#include <plat/regs-fb-v4.h>
+#include <plat/backlight.h>
+#include <plat/gpio-cfg.h>
+#include <plat/iic.h>
+#include <plat/pd.h>
+#include <plat/sdhci.h>
+#include <plat/mshci.h>
+#include <plat/ehci.h>
+#include <plat/usbgadget.h>
+#include <plat/s3c64xx-spi.h>
+#include <plat/tvout.h>
+#include <plat/csis.h>
+#include <plat/media.h>
+#include <plat/adc.h>
+#include <media/exynos_fimc_is.h>
+#include <mach/exynos-ion.h>
+
+#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE)
+#include <mach/tdmb_pdata.h>
+#endif
+
+#include <mach/map.h>
+#include <mach/spi-clocks.h>
+
+#include <mach/dev.h>
+#include <mach/ppmu.h>
+
+#ifdef CONFIG_EXYNOS4_SETUP_THERMAL
+#include <plat/s5p-tmu.h>
+#include <mach/regs-tmu.h>
+#endif
+
+#ifdef CONFIG_EXYNOS_C2C
+#include <mach/c2c.h>
+#endif
+#if defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC) || defined(CONFIG_VIDEO_MFC5X)
+#include <plat/s5p-mfc.h>
+#endif
+
+#include <plat/fb-s5p.h>
+
+#ifdef CONFIG_FB_S5P_EXTDSP
+struct s3cfb_extdsp_lcd {
+	int	width;
+	int	height;
+	int	bpp;
+};
+#endif
+#include <mach/dev-sysmmu.h>
+
+#ifdef CONFIG_VIDEO_JPEG_V2X
+#include <plat/jpeg.h>
+#endif
+
+#include <plat/fimg2d.h>
+#include <plat/s5p-sysmmu.h>
+
+#include <mach/sec_debug.h>
+
+#include <mach/p4-input.h>
+
+#include <mach/midas-power.h>
+#ifdef CONFIG_SEC_THERMISTOR
+#include <mach/sec_thermistor.h>
+#endif
+#include <mach/midas-thermistor.h>
+#include <mach/midas-tsp.h>
+#include <mach/regs-clock.h>
+
+#include <mach/midas-lcd.h>
+#include <mach/midas-sound.h>
+#if defined(CONFIG_SEC_DEV_JACK)
+#include <mach/p4note-jack.h>
+#endif
+#ifdef CONFIG_USB_HOST_NOTIFY
+#include <linux/host_notify.h>
+#include <linux/pm_runtime.h>
+#include <linux/usb.h>
+#include <linux/usb/hcd.h>
+#include <mach/usb_switch.h>
+#endif
+
+#if defined(CONFIG_PHONE_IPC_SPI)
+#include <linux/phone_svn/ipc_spi.h>
+#include <linux/irq.h>
+#endif
+
+#ifdef CONFIG_30PIN_CONN
+#include <linux/30pin_con.h>
+#endif
+
+#ifdef CONFIG_MOTOR_DRV_ISA1200
+#include <linux/isa1200_vibrator.h>
+#endif
+
+#include "board-mobile.h"
+
+extern int s6c1372_panel_gpio_init(void);
+
+/* cable state */
+bool is_cable_attached;
+bool is_usb_lpm_enter;
+
+/* Following are default values for UCON, ULCON and UFCON UART registers */
+#define SMDK4212_UCON_DEFAULT	(S3C2410_UCON_TXILEVEL |	\
+				 S3C2410_UCON_RXILEVEL |	\
+				 S3C2410_UCON_TXIRQMODE |	\
+				 S3C2410_UCON_RXIRQMODE |	\
+				 S3C2410_UCON_RXFIFO_TOI |	\
+				 S3C2443_UCON_RXERR_IRQEN)
+
+#define SMDK4212_ULCON_DEFAULT	S3C2410_LCON_CS8
+
+#define SMDK4212_UFCON_DEFAULT	(S3C2410_UFCON_FIFOMODE |	\
+				 S5PV210_UFCON_TXTRIG4 |	\
+				 S5PV210_UFCON_RXTRIG4)
+
+#define SMDK4212_UFCON_GPS	(S3C2410_UFCON_FIFOMODE |	\
+				S5PV210_UFCON_TXTRIG8 |  \
+				S5PV210_UFCON_RXTRIG32)
+
+static struct s3c2410_uartcfg smdk4212_uartcfgs[] __initdata = {
+	[0] = {
+		.hwport		= 0,
+		.flags		= 0,
+		.ucon		= SMDK4212_UCON_DEFAULT,
+		.ulcon		= SMDK4212_ULCON_DEFAULT,
+		.ufcon		= SMDK4212_UFCON_DEFAULT,
+	},
+	[1] = {
+		.hwport		= 1,
+		.flags		= 0,
+		.ucon		= SMDK4212_UCON_DEFAULT,
+		.ulcon		= SMDK4212_ULCON_DEFAULT,
+		.ufcon		= SMDK4212_UFCON_GPS,
+		.set_runstate	= set_gps_uart_op,
+	},
+	[2] = {
+		.hwport		= 2,
+		.flags		= 0,
+		.ucon		= SMDK4212_UCON_DEFAULT,
+		.ulcon		= SMDK4212_ULCON_DEFAULT,
+		.ufcon		= SMDK4212_UFCON_DEFAULT,
+	},
+	[3] = {
+		.hwport		= 3,
+		.flags		= 0,
+		.ucon		= SMDK4212_UCON_DEFAULT,
+		.ulcon		= SMDK4212_ULCON_DEFAULT,
+		.ufcon		= SMDK4212_UFCON_DEFAULT,
+	},
+};
+
+#if defined(CONFIG_S3C64XX_DEV_SPI)
+#if defined(CONFIG_VIDEO_S5C73M3_SPI)
+
+static struct s3c64xx_spi_csinfo spi1_csi[] = {
+	[0] = {
+		.line = EXYNOS4_GPB(5),
+		.set_level = gpio_set_value,
+		.fb_delay = 0x2,
+	},
+};
+
+static struct spi_board_info spi1_board_info[] __initdata = {
+	{
+		.modalias = "s5c73m3_spi",
+		.platform_data = NULL,
+		.max_speed_hz = 50000000,
+		.bus_num = 1,
+		.chip_select = 0,
+		.mode = SPI_MODE_0,
+		.controller_data = &spi1_csi[0],
+	}
+};
+#endif
+
+#if defined(CONFIG_PHONE_IPC_SPI) \
+	|| defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE)
+static struct s3c64xx_spi_csinfo spi2_csi[] = {
+	[0] = {
+		.line = EXYNOS4_GPC1(2),
+		.set_level = gpio_set_value,
+	},
+};
+
+static struct spi_board_info spi2_board_info[] __initdata = {
+#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE)
+	{
+		.modalias = "tdmbspi",
+		.platform_data = NULL,
+		.max_speed_hz = 5000000,
+		.bus_num = 2,
+		.chip_select = 0,
+		.mode = SPI_MODE_0,
+		.controller_data = &spi2_csi[0],
+	},
+#else
+	{
+		.modalias = "ipc_spi",
+		.platform_data = NULL,
+		.bus_num = 2,
+		.chip_select = 0,
+		.max_speed_hz = 12*1000*1000,
+		.mode = SPI_MODE_1,
+		.controller_data = &spi2_csi[0],
+	}
+#endif
+};
+#endif
+#endif
+
+
+#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE)
+static void tdmb_set_config_poweron(void)
+{
+	s3c_gpio_cfgpin(GPIO_TDMB_EN, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TDMB_EN, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TDMB_EN, GPIO_LEVEL_LOW);
+
+	s3c_gpio_cfgpin(GPIO_TDMB_INT, S3C_GPIO_SFN(GPIO_TDMB_INT_AF));
+	s3c_gpio_setpull(GPIO_TDMB_INT, S3C_GPIO_PULL_NONE);
+}
+static void tdmb_set_config_poweroff(void)
+{
+	s3c_gpio_cfgpin(GPIO_TDMB_EN, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TDMB_EN, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TDMB_EN, GPIO_LEVEL_LOW);
+
+	s3c_gpio_cfgpin(GPIO_TDMB_INT, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TDMB_INT, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TDMB_INT, GPIO_LEVEL_LOW);
+}
+
+static void tdmb_gpio_on(void)
+{
+	printk(KERN_DEBUG "tdmb_gpio_on\n");
+
+	tdmb_set_config_poweron();
+
+	gpio_set_value(GPIO_TDMB_EN, GPIO_LEVEL_LOW);
+	usleep_range(1000, 1000);
+	gpio_set_value(GPIO_TDMB_EN, GPIO_LEVEL_HIGH);
+}
+
+static void tdmb_gpio_off(void)
+{
+	printk(KERN_DEBUG "tdmb_gpio_off\n");
+
+	tdmb_set_config_poweroff();
+
+	gpio_set_value(GPIO_TDMB_EN, GPIO_LEVEL_LOW);
+}
+
+static struct tdmb_platform_data tdmb_pdata = {
+	.gpio_on = tdmb_gpio_on,
+	.gpio_off = tdmb_gpio_off,
+};
+
+static struct platform_device tdmb_device = {
+	.name			= "tdmb",
+	.id				= -1,
+	.dev			= {
+		.platform_data = &tdmb_pdata,
+	},
+};
+
+static int __init tdmb_dev_init(void)
+{
+	tdmb_set_config_poweroff();
+	s5p_register_gpio_interrupt(GPIO_TDMB_INT);
+	tdmb_pdata.irq = GPIO_TDMB_IRQ;
+	platform_device_register(&tdmb_device);
+
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_PHONE_IPC_SPI)
+static void ipc_spi_cfg_gpio(void);
+
+static struct ipc_spi_platform_data ipc_spi_data = {
+	.gpio_ipc_mrdy = GPIO_IPC_MRDY,
+	.gpio_ipc_srdy = GPIO_IPC_SRDY,
+	.gpio_ipc_sub_mrdy = GPIO_IPC_SUB_MRDY,
+	.gpio_ipc_sub_srdy = GPIO_IPC_SUB_SRDY,
+
+	.cfg_gpio = ipc_spi_cfg_gpio,
+};
+
+static struct resource ipc_spi_res[] = {
+	[0] = {
+		.start = IRQ_IPC_SRDY,
+		.end = IRQ_IPC_SRDY,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device ipc_spi_device = {
+	.name = "onedram",
+	.id = -1,
+	.num_resources = ARRAY_SIZE(ipc_spi_res),
+	.resource = ipc_spi_res,
+	.dev = {
+		.platform_data = &ipc_spi_data,
+	},
+};
+
+static void ipc_spi_cfg_gpio(void)
+{
+	int err = 0;
+
+	unsigned gpio_ipc_mrdy = ipc_spi_data.gpio_ipc_mrdy;
+	unsigned gpio_ipc_srdy = ipc_spi_data.gpio_ipc_srdy;
+	unsigned gpio_ipc_sub_mrdy = ipc_spi_data.gpio_ipc_sub_mrdy;
+	unsigned gpio_ipc_sub_srdy = ipc_spi_data.gpio_ipc_sub_srdy;
+
+	err = gpio_request(gpio_ipc_mrdy, "IPC_MRDY");
+	if (err) {
+		printk(KERN_ERR "ipc_spi_cfg_gpio - fail to request gpio %s : %d\n",
+			"IPC_MRDY", err);
+	} else {
+		gpio_direction_output(gpio_ipc_mrdy, 0);
+		s3c_gpio_setpull(gpio_ipc_mrdy, S3C_GPIO_PULL_DOWN);
+	}
+
+	err = gpio_request(gpio_ipc_srdy, "IPC_SRDY");
+	if (err) {
+		printk(KERN_ERR "ipc_spi_cfg_gpio - fail to request gpio %s : %d\n",
+			"IPC_SRDY", err);
+	} else {
+		gpio_direction_input(gpio_ipc_srdy);
+		s3c_gpio_cfgpin(gpio_ipc_srdy, S3C_GPIO_SFN(0xF));
+		s3c_gpio_setpull(gpio_ipc_srdy, S3C_GPIO_PULL_NONE);
+	}
+
+	err = gpio_request(gpio_ipc_sub_mrdy, "IPC_SUB_MRDY");
+	if (err) {
+		printk(KERN_ERR "ipc_spi_cfg_gpio - fail to request gpio %s : %d\n",
+			"IPC_SUB_MRDY", err);
+	} else {
+		gpio_direction_output(gpio_ipc_sub_mrdy, 0);
+		s3c_gpio_setpull(gpio_ipc_sub_mrdy, S3C_GPIO_PULL_DOWN);
+	}
+
+	err = gpio_request(gpio_ipc_sub_srdy, "IPC_SUB_SRDY");
+	if (err) {
+		printk(KERN_ERR "ipc_spi_cfg_gpio - fail to request gpio %s : %d\n",
+			"IPC_SUB_SRDY", err);
+	} else {
+		gpio_direction_input(gpio_ipc_sub_srdy);
+		s3c_gpio_cfgpin(gpio_ipc_sub_srdy, S3C_GPIO_SFN(0xF));
+		s3c_gpio_setpull(gpio_ipc_sub_srdy, S3C_GPIO_PULL_NONE);
+	}
+
+	irq_set_irq_type(gpio_to_irq(GPIO_IPC_SRDY), IRQ_TYPE_EDGE_RISING);
+	irq_set_irq_type(gpio_to_irq(GPIO_IPC_SUB_SRDY), IRQ_TYPE_EDGE_RISING);
+}
+#endif
+
+#ifdef CONFIG_LEDS_AAT1290A
+static int aat1290a_initGpio(void)
+{
+	int err;
+
+	err = gpio_request(GPIO_CAM_SW_EN, "CAM_SW_EN");
+	if (err) {
+		printk(KERN_ERR "failed to request CAM_SW_EN\n");
+		return -EPERM;
+	}
+	gpio_direction_output(GPIO_CAM_SW_EN, 1);
+	gpio_set_value(GPIO_CAM_SW_EN, 1);
+
+	return 0;
+}
+
+static void aat1290a_switch(int enable)
+{
+	gpio_set_value(GPIO_CAM_SW_EN, enable);
+}
+
+static int aat1290a_setGpio(void)
+{
+	int err;
+
+	err = gpio_request(GPIO_TORCH_EN, "TORCH_EN");
+	if (err) {
+		printk(KERN_ERR "failed to request TORCH_EN\n");
+		return -EPERM;
+	}
+	gpio_direction_output(GPIO_TORCH_EN, 1);
+	err = gpio_request(GPIO_TORCH_SET, "TORCH_SET");
+	if (err) {
+		printk(KERN_ERR "failed to request TORCH_SET\n");
+		gpio_free(GPIO_TORCH_EN);
+		return -EPERM;
+	}
+	gpio_direction_output(GPIO_TORCH_SET, 1);
+	gpio_set_value(GPIO_TORCH_EN, 0);
+	gpio_set_value(GPIO_TORCH_SET, 0);
+
+	return 0;
+}
+
+static int aat1290a_freeGpio(void)
+{
+	gpio_free(GPIO_TORCH_EN);
+	gpio_free(GPIO_TORCH_SET);
+
+	return 0;
+}
+
+static void aat1290a_torch_en(int onoff)
+{
+	gpio_set_value(GPIO_TORCH_EN, onoff);
+}
+
+static void aat1290a_torch_set(int onoff)
+{
+	gpio_set_value(GPIO_TORCH_SET, onoff);
+}
+
+static struct aat1290a_led_platform_data aat1290a_led_data = {
+	.brightness = TORCH_BRIGHTNESS_50,
+	.status	= STATUS_UNAVAILABLE,
+	.switch_sel = aat1290a_switch,
+	.initGpio = aat1290a_initGpio,
+	.setGpio = aat1290a_setGpio,
+	.freeGpio = aat1290a_freeGpio,
+	.torch_en = aat1290a_torch_en,
+	.torch_set = aat1290a_torch_set,
+};
+
+static struct platform_device s3c_device_aat1290a_led = {
+	.name	= "aat1290a-led",
+	.id	= -1,
+	.dev	= {
+		.platform_data	= &aat1290a_led_data,
+	},
+};
+#endif
+
+static DEFINE_MUTEX(notify_lock);
+
+#define DEFINE_MMC_CARD_NOTIFIER(num) \
+static void (*hsmmc##num##_notify_func)(struct platform_device *, int state); \
+static int ext_cd_init_hsmmc##num(void (*notify_func)( \
+			struct platform_device *, int state)) \
+{ \
+	mutex_lock(&notify_lock); \
+	WARN_ON(hsmmc##num##_notify_func); \
+	hsmmc##num##_notify_func = notify_func; \
+	mutex_unlock(&notify_lock); \
+	return 0; \
+} \
+static int ext_cd_cleanup_hsmmc##num(void (*notify_func)( \
+			struct platform_device *, int state)) \
+{ \
+	mutex_lock(&notify_lock); \
+	WARN_ON(hsmmc##num##_notify_func != notify_func); \
+	hsmmc##num##_notify_func = NULL; \
+	mutex_unlock(&notify_lock); \
+	return 0; \
+}
+
+#ifdef CONFIG_S3C_DEV_HSMMC3
+	DEFINE_MMC_CARD_NOTIFIER(3)
+#endif
+
+/*
+ * call this when you need sd stack to recognize insertion or removal of card
+ * that can't be told by SDHCI regs
+ */
+void mmc_force_presence_change(struct platform_device *pdev)
+{
+	void (*notify_func)(struct platform_device *, int state) = NULL;
+	mutex_lock(&notify_lock);
+#ifdef CONFIG_S3C_DEV_HSMMC3
+	if (pdev == &s3c_device_hsmmc3)
+		notify_func = hsmmc3_notify_func;
+#endif
+
+	if (notify_func)
+		notify_func(pdev, 1);
+	else
+		pr_warn("%s: called for device with no notifier\n", __func__);
+	mutex_unlock(&notify_lock);
+}
+EXPORT_SYMBOL_GPL(mmc_force_presence_change);
+
+#ifdef CONFIG_S3C_DEV_HSMMC
+static struct s3c_sdhci_platdata smdk4212_hsmmc0_pdata __initdata = {
+	.cd_type		= S3C_MSHCI_CD_PERMANENT,
+	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
+#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
+	.max_width		= 8,
+	.host_caps		= MMC_CAP_8_BIT_DATA,
+#endif
+};
+#endif
+
+#ifdef CONFIG_S3C_DEV_HSMMC1
+static struct s3c_sdhci_platdata smdk4212_hsmmc1_pdata __initdata = {
+	.cd_type		= S3C_SDHCI_CD_INTERNAL,
+	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+#endif
+
+#ifdef CONFIG_S3C_DEV_HSMMC2
+static struct s3c_sdhci_platdata smdk4212_hsmmc2_pdata __initdata = {
+	.cd_type		= S3C_SDHCI_CD_GPIO,
+	.ext_cd_gpio		= EXYNOS4_GPX3(4),
+	.ext_cd_gpio_invert	= true,
+	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
+	.vmmc_name		= "vtf_2.8v"
+#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
+	.max_width		= 8,
+	.host_caps		= MMC_CAP_8_BIT_DATA,
+#endif
+};
+#endif
+
+#ifdef CONFIG_S3C_DEV_HSMMC3
+static struct s3c_sdhci_platdata smdk4212_hsmmc3_pdata __initdata = {
+/* new code for brm4334 */
+	.cd_type		= S3C_SDHCI_CD_EXTERNAL,
+
+	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
+	.pm_flags = S3C_SDHCI_PM_IGNORE_SUSPEND_RESUME,
+	.ext_cd_init = ext_cd_init_hsmmc3,
+	.ext_cd_cleanup = ext_cd_cleanup_hsmmc3,
+};
+#endif
+
+#ifdef CONFIG_EXYNOS4_DEV_MSHC
+static struct s3c_mshci_platdata exynos4_mshc_pdata __initdata = {
+	.cd_type		= S3C_MSHCI_CD_PERMANENT,
+	.fifo_depth		= 0x80,
+#if defined(CONFIG_EXYNOS4_MSHC_8BIT) && \
+	defined(CONFIG_EXYNOS4_MSHC_DDR)
+	.max_width		= 8,
+	.host_caps		= MMC_CAP_8_BIT_DATA | MMC_CAP_1_8V_DDR |
+				  MMC_CAP_UHS_DDR50 | MMC_CAP_CMD23,
+	.host_caps2		= MMC_CAP2_PACKED_CMD,
+#elif defined(CONFIG_EXYNOS4_MSHC_8BIT)
+	.max_width		= 8,
+	.host_caps		= MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
+#elif defined(CONFIG_EXYNOS4_MSHC_DDR)
+	.host_caps		= MMC_CAP_1_8V_DDR | MMC_CAP_UHS_DDR50 |
+				  MMC_CAP_CMD23,
+#endif
+	.int_power_gpio		= GPIO_eMMC_EN,
+};
+#endif
+
+#ifdef CONFIG_USB_EHCI_S5P
+static struct s5p_ehci_platdata smdk4212_ehci_pdata;
+
+static void __init smdk4212_ehci_init(void)
+{
+	struct s5p_ehci_platdata *pdata = &smdk4212_ehci_pdata;
+
+	s5p_ehci_set_platdata(pdata);
+}
+#endif
+
+#ifdef CONFIG_USB_OHCI_S5P
+static struct s5p_ohci_platdata smdk4212_ohci_pdata;
+
+static void __init smdk4212_ohci_init(void)
+{
+	struct s5p_ohci_platdata *pdata = &smdk4212_ohci_pdata;
+
+	s5p_ohci_set_platdata(pdata);
+}
+#endif
+
+/* USB GADGET */
+#ifdef CONFIG_USB_GADGET
+static struct s5p_usbgadget_platdata smdk4212_usbgadget_pdata;
+
+#include <linux/usb/android_composite.h>
+static void __init smdk4212_usbgadget_init(void)
+{
+	struct s5p_usbgadget_platdata *pdata = &smdk4212_usbgadget_pdata;
+	struct android_usb_platform_data *android_pdata =
+		s3c_device_android_usb.dev.platform_data;
+	if (android_pdata) {
+		unsigned int newluns = 2;
+		printk(KERN_DEBUG "usb: %s: default luns=%d, new luns=%d\n",
+				__func__, android_pdata->nluns, newluns);
+		android_pdata->nluns = newluns;
+	} else {
+		printk(KERN_DEBUG "usb: %s android_pdata is not available\n",
+				__func__);
+	}
+
+	s5p_usbgadget_set_platdata(pdata);
+
+#if defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT) || \
+	defined(CONFIG_MACH_C1_KOR_LGT)
+	pdata = s3c_device_usbgadget.dev.platform_data;
+	if (pdata) {
+		/* Squelch Threshold Tune [13:11] (111 : -20%) */
+		pdata->phy_tune_mask |= (0x7 << 11);
+		pdata->phy_tune |= (0x7 << 11);
+		printk(KERN_DEBUG "usb: %s tune_mask=0x%x, tune=0x%x\n",
+			__func__, pdata->phy_tune_mask, pdata->phy_tune);
+	}
+#endif
+
+}
+#endif
+
+/* I2C0 */
+static struct i2c_board_info i2c_devs0[] __initdata = {
+};
+
+/* I2C1 */
+static struct i2c_board_info i2c_devs1[] __initdata = {
+};
+
+#ifdef CONFIG_S3C_DEV_I2C5
+static struct i2c_board_info i2c_devs5[] __initdata = {
+#ifdef CONFIG_REGULATOR_MAX8997
+	{
+		I2C_BOARD_INFO("max8997", (0xcc >> 1)),
+		.platform_data = &exynos4_max8997_info,
+	},
+#endif
+#if defined(CONFIG_REGULATOR_MAX77686)
+	/* max77686 on i2c5 other than M1 board */
+	{
+		I2C_BOARD_INFO("max77686", (0x12 >> 1)),
+		.platform_data	= &exynos4_max77686_info,
+	},
+#endif
+};
+#endif
+
+static struct i2c_board_info i2c_devs7[] __initdata = {
+#if defined(CONFIG_REGULATOR_MAX77686) /* max77686 on i2c7 with M1 board */
+	{
+		I2C_BOARD_INFO("max77686", (0x12 >> 1)),
+		.platform_data	= &exynos4_max77686_info,
+	},
+#endif
+
+#if defined(CONFIG_REGULATOR_S5M8767)
+	{
+		I2C_BOARD_INFO("s5m87xx", 0xCC >> 1),
+		.platform_data = &exynos4_s5m8767_info,
+		.irq	= IRQ_EINT(7),
+	},
+#endif
+};
+
+/* Bluetooth */
+#ifdef CONFIG_BT_BCM4334
+static struct platform_device bcm4334_bluetooth_device = {
+	.name = "bcm4334_bluetooth",
+	.id = -1,
+};
+#endif
+
+/* I2C9 */
+static struct i2c_board_info i2c_devs9_emul[] __initdata = {
+};
+
+/* I2C10 */
+static struct i2c_board_info i2c_devs10_emul[] __initdata = {
+};
+
+/* I2C11 */
+static struct i2c_board_info i2c_devs11_emul[] __initdata = {
+};
+
+#ifdef CONFIG_SMB347_CHARGER
+struct smb_charger_callbacks *smb_callbacks;
+
+static void smb_charger_register_callbacks(struct smb_charger_callbacks *ptr)
+{
+	smb_callbacks = ptr;
+}
+
+static void smb_charger_unregister_callbacks(void)
+{
+	smb_callbacks = NULL;
+}
+
+static struct smb_charger_data smb_charger_pdata = {
+	.register_callbacks = smb_charger_register_callbacks,
+	.unregister_callbacks = smb_charger_unregister_callbacks,
+	.enable = GPIO_TA_EN,
+	.stat = GPIO_TA_nCHG,
+	.ta_nconnected = GPIO_TA_nCONNECTED,
+};
+
+/* I2C13 */
+static struct i2c_board_info i2c_devs13_emul[] __initdata = {
+	{
+		I2C_BOARD_INFO("smb347-charger", 0x0C >> 1),
+		.platform_data = &smb_charger_pdata,
+	},
+};
+
+static void __init smb_gpio_init(void)
+{
+	s3c_gpio_cfgpin(GPIO_TA_nCHG, S3C_GPIO_SFN(0xf));
+	/* external pull up */
+	s3c_gpio_setpull(GPIO_TA_nCHG, S3C_GPIO_PULL_NONE);
+	i2c_devs13_emul[0].irq = gpio_to_irq(GPIO_TA_nCHG);
+}
+
+static struct i2c_gpio_platform_data gpio_i2c_data13 = {
+	.sda_pin = GPIO_CHG_SDA,
+	.scl_pin = GPIO_CHG_SCL,
+};
+
+struct platform_device s3c_device_i2c13 = {
+	.name = "i2c-gpio",
+	.id = 13,
+	.dev.platform_data = &gpio_i2c_data13,
+};
+
+static void sec_bat_set_charging_state(int enable, int cable_status)
+{
+	if (smb_callbacks && smb_callbacks->set_charging_state)
+		smb_callbacks->set_charging_state(enable, cable_status);
+}
+
+static int sec_bat_get_charging_state(void)
+{
+	if (smb_callbacks && smb_callbacks->get_charging_state)
+		return smb_callbacks->get_charging_state();
+	else
+		return 0;
+}
+
+static void sec_bat_set_charging_current(int set_current)
+{
+	if (smb_callbacks && smb_callbacks->set_charging_current)
+		smb_callbacks->set_charging_current(set_current);
+}
+
+static int sec_bat_get_charging_current(void)
+{
+	if (smb_callbacks && smb_callbacks->get_charging_current)
+		return smb_callbacks->get_charging_current();
+	else
+		return 0;
+}
+
+static int sec_bat_get_charger_is_full(void)
+{
+	if (smb_callbacks && smb_callbacks->get_charger_is_full)
+		return smb_callbacks->get_charger_is_full();
+	else
+		return 0;
+}
+#endif
+
+static int check_bootmode(void)
+{
+	int inform2;
+
+	inform2 = __raw_readl(S5P_INFORM2);
+	if (inform2 == 0x1)
+		return 1;
+	else
+		return 0;
+}
+
+static int check_jig_on(void)
+{
+	/* check GPIO_IF_CON_SENSE pin */
+	if (system_rev >= 1)
+		return !gpio_get_value(GPIO_IF_CON_SENSE);
+	else
+		return 0;
+}
+
+/* I2C14 */
+#ifdef CONFIG_BATTERY_MAX17042_FUELGAUGE_PX
+static struct i2c_gpio_platform_data gpio_i2c_data14 = {
+	.sda_pin = GPIO_FUEL_SDA,
+	.scl_pin = GPIO_FUEL_SCL,
+};
+
+struct platform_device s3c_device_i2c14 = {
+	.name = "i2c-gpio",
+	.id = 14,
+	.dev.platform_data = &gpio_i2c_data14,
+};
+
+static struct max17042_platform_data max17042_pdata = {
+	.sdi_capacity = 0x3730,
+	.sdi_vfcapacity = 0x4996,
+	.atl_capacity = 0x3022,
+	.atl_vfcapacity = 0x4024,
+	.sdi_low_bat_comp_start_vol = 3600,
+	.atl_low_bat_comp_start_vol = 3450,
+	.fuel_alert_line = GPIO_FUEL_ALERT,
+	.check_jig_status = check_jig_on
+};
+
+static struct i2c_board_info i2c_devs14_emul[] __initdata = {
+	{
+		I2C_BOARD_INFO("fuelgauge", 0x36),
+		.platform_data = &max17042_pdata,
+	},
+};
+#endif
+
+/* I2C15 */
+static struct i2c_gpio_platform_data gpio_i2c_data15 = {
+	.sda_pin = GPIO_MHL_SDA_1_8V,
+	.scl_pin = GPIO_MHL_SCL_1_8V,
+	.udelay = 3,
+	.timeout = 0,
+};
+
+struct platform_device s3c_device_i2c15 = {
+	.name = "i2c-gpio",
+	.id = 15,
+	.dev = {
+		.platform_data = &gpio_i2c_data15,
+	}
+};
+
+static struct i2c_board_info i2c_devs15_emul[] __initdata = {
+};
+
+/* I2C16 */
+static struct i2c_gpio_platform_data gpio_i2c_data16 = {
+	.sda_pin = GPIO_MHL_DSDA_2_8V,
+	.scl_pin = GPIO_MHL_DSCL_2_8V,
+};
+
+struct platform_device s3c_device_i2c16 = {
+	.name = "i2c-gpio",
+	.id = 16,
+	.dev.platform_data = &gpio_i2c_data16,
+};
+
+static struct i2c_board_info i2c_devs16_emul[] __initdata = {
+};
+
+#if 0
+static struct i2c_gpio_platform_data i2c18_platdata = {
+	.sda_pin		= GPIO_8M_CAM_SDA_18V,
+	.scl_pin		= GPIO_8M_CAM_SCL_18V,
+	.udelay			= 2, /* 250 kHz */
+	.sda_is_open_drain	= 0,
+	.scl_is_open_drain	= 0,
+	.scl_is_output_only = 0,
+};
+
+static struct platform_device s3c_device_i2c18 = {
+	.name	= "i2c-gpio",
+	.id	= 18,
+	.dev.platform_data	= &i2c18_platdata,
+};
+
+/* I2C18 */
+/* No explicit i2c client array here. The channel number 18 is passed
+   to camera driver from midas-camera.c instead. */
+#endif
+
+#if defined(CONFIG_STMPE811_ADC) || defined(CONFIG_FM_SI4709_MODULE) \
+	|| defined(CONFIG_FM_SI4705_MODULE)
+static struct i2c_gpio_platform_data gpio_i2c_data19 = {
+	.sda_pin = GPIO_ADC_SDA,
+	.scl_pin = GPIO_ADC_SCL,
+};
+
+struct platform_device s3c_device_i2c19 = {
+	.name = "i2c-gpio",
+	.id = 19,
+	.dev.platform_data = &gpio_i2c_data19,
+};
+
+
+/* I2C19 */
+static struct i2c_board_info i2c_devs19_emul[] __initdata = {
+#if defined(CONFIG_STMPE811_ADC)
+	{
+		I2C_BOARD_INFO("stmpe811-adc", (0x82 >> 1)),
+		.platform_data	= &stmpe811_pdata,
+	},
+#endif
+#ifdef CONFIG_FM_SI4705_MODULE
+	{
+		I2C_BOARD_INFO("Si4709", (0x22 >> 1)),
+	},
+#endif
+#ifdef CONFIG_FM_SI4709_MODULE
+	{
+		I2C_BOARD_INFO("Si4709", (0x20 >> 1)),
+	},
+#endif
+
+};
+#endif
+
+/* I2C21 */
+#ifdef CONFIG_LEDS_AN30259A
+static struct i2c_gpio_platform_data gpio_i2c_data21 = {
+	.scl_pin = GPIO_S_LED_I2C_SCL,
+	.sda_pin = GPIO_S_LED_I2C_SDA,
+};
+
+struct platform_device s3c_device_i2c21 = {
+	.name = "i2c-gpio",
+	.id = 21,
+	.dev.platform_data = &gpio_i2c_data21,
+};
+#endif
+
+/* I2C21 */
+static struct i2c_board_info i2c_devs21_emul[] __initdata = {
+#ifdef CONFIG_LEDS_AN30259A
+	{
+		I2C_BOARD_INFO("an30259a", 0x30),
+	},
+#endif
+};
+
+#ifdef CONFIG_I2C_GPIO
+#ifdef CONFIG_MOTOR_DRV_ISA1200
+static void isa1200_init(void)
+{
+	int gpio;
+	gpio = GPIO_MOTOR_EN;
+	gpio_request(gpio, "MOTOR_EN");
+	gpio_direction_output(gpio, 1);
+	gpio_export(gpio, 0);
+}
+static int isa1200_vdd_en(bool en)
+{
+	return gpio_direction_output(GPIO_MOTOR_EN, en);
+}
+
+static struct i2c_gpio_platform_data gpio_i2c_data17 = {
+	.sda_pin = GPIO_MOTOR_SDA,
+	.scl_pin = GPIO_MOTOR_SCL,
+};
+
+struct platform_device s3c_device_i2c17 = {
+	.name = "i2c-gpio",
+	.id = 17,
+	.dev.platform_data = &gpio_i2c_data17,
+};
+
+static struct isa1200_vibrator_platform_data isa1200_vibrator_pdata = {
+	.gpio_en = isa1200_vdd_en,
+	.max_timeout = 10000,
+	.ctrl0 = CTL0_DIVIDER128 | CTL0_PWM_INPUT,
+	.ctrl1 = CTL1_DEFAULT,
+	.ctrl2 = 0,
+	.ctrl4 = 0,
+	. pll = 0x23,
+	.duty = 0x71,
+	.period = 0x74,
+	.get_clk = NULL,
+	.pwm_id = 0,
+	.pwm_duty = 37000,
+	.pwm_period = 38675,
+};
+static struct i2c_board_info i2c_devs17_emul[] = {
+	{
+		I2C_BOARD_INFO("isa1200_vibrator",  0x48),
+		.platform_data = &isa1200_vibrator_pdata,
+	},
+};
+#endif	/* CONFIG_MOTOR_DRV_ISA1200 */
+#endif
+
+#ifdef CONFIG_ANDROID_RAM_CONSOLE
+static struct resource ram_console_resource[] = {
+	{
+		.flags = IORESOURCE_MEM,
+	}
+};
+
+static struct platform_device ram_console_device = {
+	.name = "ram_console",
+	.id = -1,
+	.num_resources = ARRAY_SIZE(ram_console_resource),
+	.resource = ram_console_resource,
+};
+
+static int __init setup_ram_console_mem(char *str)
+{
+	unsigned size = memparse(str, &str);
+
+	if (size && (*str == '@')) {
+		unsigned long long base = 0;
+
+		base = simple_strtoul(++str, &str, 0);
+		if (reserve_bootmem(base, size, BOOTMEM_EXCLUSIVE)) {
+			pr_err("%s: failed reserving size %d "
+			       "at base 0x%llx\n", __func__, size, base);
+			return -1;
+		}
+
+		ram_console_resource[0].start = base;
+		ram_console_resource[0].end = base + size - 1;
+		pr_err("%s: %x at %llx\n", __func__, size, base);
+	}
+	return 0;
+}
+
+__setup("ram_console=", setup_ram_console_mem);
+#endif
+
+#ifdef CONFIG_BATTERY_SEC_PX
+void sec_bat_gpio_init(void)
+{
+
+	s3c_gpio_cfgpin(GPIO_TA_nCONNECTED, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_TA_nCONNECTED, S3C_GPIO_PULL_NONE);
+
+	s3c_gpio_cfgpin(GPIO_TA_nCHG, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_TA_nCHG, S3C_GPIO_PULL_UP);
+
+	s3c_gpio_cfgpin(GPIO_TA_EN, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TA_EN, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TA_EN, 0);
+
+	gpio_request(GPIO_TA_nCHG, "TA_nCHG");
+	s5p_register_gpio_interrupt(GPIO_TA_nCHG);
+
+	pr_info("BAT : Battery GPIO initialized.\n");
+}
+
+static void  sec_charger_cb(int set_cable_type)
+{
+	struct usb_gadget *gadget = platform_get_drvdata(&s3c_device_usbgadget);
+	bool cable_state_to_tsp;
+	bool cable_state_to_usb;
+
+	switch (set_cable_type) {
+	case CHARGER_USB:
+		cable_state_to_tsp = true;
+		cable_state_to_usb = true;
+		is_cable_attached = true;
+		is_usb_lpm_enter = false;
+		break;
+	case CHARGER_AC:
+	case CHARGER_DOCK:
+	case CHARGER_MISC:
+		cable_state_to_tsp = true;
+		cable_state_to_usb = false;
+		is_cable_attached = true;
+		is_usb_lpm_enter = true;
+		break;
+	case CHARGER_BATTERY:
+	case CHARGER_DISCHARGE:
+	default:
+		cable_state_to_tsp = false;
+		cable_state_to_usb = false;
+		is_cable_attached = false;
+		is_usb_lpm_enter = true;
+		break;
+	}
+	pr_info("%s:cable_type=%d,tsp(%d),usb(%d),attached(%d),usblpm(%d)\n",
+		__func__, set_cable_type, cable_state_to_tsp,
+		cable_state_to_usb, is_cable_attached, is_usb_lpm_enter);
+
+#if defined(CONFIG_TOUCHSCREEN_SYNAPTICS_S7301)
+	synaptics_ts_charger_infom(is_cable_attached);
+#endif
+
+/* Send charger state to px-switch. px-switch needs cable type what USB or not */
+	set_usb_connection_state(!is_usb_lpm_enter);
+
+/* Send charger state to USB. USB needs cable type what USB data or not */
+	if (gadget) {
+		if (cable_state_to_usb)
+			usb_gadget_vbus_connect(gadget);
+		else
+			usb_gadget_vbus_disconnect(gadget);
+	}
+
+	pr_info("%s\n", __func__);
+}
+
+static struct sec_battery_platform_data sec_battery_platform = {
+	.charger = {
+		.enable_line = GPIO_TA_EN,
+		.connect_line = GPIO_TA_nCONNECTED,
+		.fullcharge_line = GPIO_TA_nCHG,
+		.accessory_line = GPIO_ACCESSORY_INT,
+	},
+#if defined(CONFIG_SMB347_CHARGER)
+	.set_charging_state = sec_bat_set_charging_state,
+	.get_charging_state = sec_bat_get_charging_state,
+	.set_charging_current = sec_bat_set_charging_current,
+	.get_charging_current = sec_bat_get_charging_current,
+	.get_charger_is_full = sec_bat_get_charger_is_full,
+#endif
+	.init_charger_gpio = sec_bat_gpio_init,
+	.inform_charger_connection = sec_charger_cb,
+
+#if defined(CONFIG_TARGET_LOCALE_USA)
+	.temp_high_threshold = 50000,	/* 50c */
+	.temp_high_recovery = 42000,	/* 42c */
+	.temp_low_recovery = 0,			/* 0c */
+	.temp_low_threshold = -5000,	/* -5c */
+#else
+	.temp_high_threshold = 50000,	/* 50c */
+	.temp_high_recovery = 42000,	/* 42c */
+	.temp_low_recovery = 0,			/* 0c */
+	.temp_low_threshold = -5000,	/* -5c */
+#endif
+	.recharge_voltage = 4150,	/*4.15V */
+
+	.charge_duration = 10*60*60,	/* 10 hour */
+	.recharge_duration = 1.5*60*60,	/* 1.5 hour */
+	.check_lp_charging_boot = check_bootmode,
+	.check_jig_status = check_jig_on
+};
+
+static struct platform_device sec_battery_device = {
+	.name = "sec-battery",
+	.id = -1,
+	.dev = {
+		.platform_data = &sec_battery_platform,
+	},
+};
+#endif /* CONFIG_BATTERY_SEC_PX */
+
+#ifdef CONFIG_USB_HOST_NOTIFY
+static void px_usb_otg_power(int active);
+#define HOST_NOTIFIER_BOOSTER	px_usb_otg_power
+#define HOST_NOTIFIER_GPIO		GPIO_ACCESSORY_OUT_5V
+#define RETRY_CNT_LIMIT 100
+
+struct host_notifier_platform_data host_notifier_pdata = {
+	.ndev.name	= "usb_otg",
+	.gpio		= HOST_NOTIFIER_GPIO,
+	.booster	= HOST_NOTIFIER_BOOSTER,
+	.irq_enable = 1,
+};
+
+struct platform_device host_notifier_device = {
+	.name = "host_notifier",
+	.dev.platform_data = &host_notifier_pdata,
+};
+
+static void __init acc_chk_gpio_init(void)
+{
+	gpio_request(GPIO_ACCESSORY_EN, "GPIO_USB_OTG_EN");
+	s3c_gpio_cfgpin(GPIO_ACCESSORY_EN, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_ACCESSORY_EN, S3C_GPIO_PULL_NONE);
+	gpio_direction_output(GPIO_ACCESSORY_EN, false);
+
+	gpio_request(GPIO_ACCESSORY_OUT_5V, "gpio_acc_5v");
+	s3c_gpio_cfgpin(GPIO_ACCESSORY_OUT_5V, S3C_GPIO_SFN(0xf));
+	s3c_gpio_setpull(GPIO_ACCESSORY_OUT_5V, S3C_GPIO_PULL_NONE);
+	gpio_direction_input(GPIO_ACCESSORY_OUT_5V);
+}
+#endif
+
+#ifdef CONFIG_30PIN_CONN
+static void smdk_accessory_gpio_init(void)
+{
+	gpio_request(GPIO_ACCESSORY_INT, "accessory");
+	s3c_gpio_cfgpin(GPIO_ACCESSORY_INT, S3C_GPIO_SFN(0xf));
+	s3c_gpio_setpull(GPIO_ACCESSORY_INT, S3C_GPIO_PULL_NONE);
+	gpio_direction_input(GPIO_ACCESSORY_INT);
+
+	gpio_request(GPIO_DOCK_INT, "dock");
+	s3c_gpio_cfgpin(GPIO_DOCK_INT, S3C_GPIO_SFN(0xf));
+	s3c_gpio_setpull(GPIO_DOCK_INT, S3C_GPIO_PULL_NONE);
+	gpio_direction_input(GPIO_DOCK_INT);
+}
+
+void smdk_accessory_power(u8 token, bool active)
+{
+	int gpio_acc_en = 0;
+	int try_cnt = 0;
+	int gpio_acc_5v = 0;
+	static bool enable;
+	static u8 acc_en_token;
+
+	/*
+		token info
+		0 : power off,
+		1 : Keyboard dock
+		2 : USB
+	*/
+	gpio_acc_en = GPIO_ACCESSORY_EN;
+	gpio_acc_5v = GPIO_ACCESSORY_OUT_5V;
+
+	gpio_request(gpio_acc_en, "GPIO_ACCESSORY_EN");
+	s3c_gpio_cfgpin(gpio_acc_en, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(gpio_acc_en, S3C_GPIO_PULL_NONE);
+
+	if (active) {
+		if (acc_en_token) {
+			pr_info("Board : Keyboard dock is connected.\n");
+			gpio_direction_output(gpio_acc_en, 0);
+			msleep(100);
+		}
+
+		acc_en_token |= (1 << token);
+		enable = true;
+		gpio_direction_output(gpio_acc_en, 1);
+
+		if (0 != gpio_acc_5v) {
+			/* prevent the overcurrent */
+			while (!gpio_get_value(gpio_acc_5v)) {
+				gpio_direction_output(gpio_acc_en, 0);
+				msleep(20);
+				gpio_direction_output(gpio_acc_en, 1);
+				if (try_cnt > 10) {
+					pr_err("[acc] failed to enable the accessory_en");
+					break;
+				} else
+					try_cnt++;
+			}
+
+		} else
+			pr_info("[ACC] gpio_acc_5v is not set\n");
+
+	} else {
+		if (0 == token) {
+			gpio_direction_output(gpio_acc_en, 0);
+			enable = false;
+		} else {
+			acc_en_token &= ~(1 << token);
+			if (0 == acc_en_token) {
+				gpio_direction_output(gpio_acc_en, 0);
+				enable = false;
+			}
+		}
+	}
+	gpio_free(gpio_acc_en);
+	pr_info("Board : %s (%d,%d) %s\n", __func__,
+		token, active, enable ? "on" : "off");
+}
+
+static int smdk_get_acc_state(void)
+{
+	return gpio_get_value(GPIO_DOCK_INT);
+}
+
+static int smdk_get_dock_state(void)
+{
+	return gpio_get_value(GPIO_ACCESSORY_INT);
+}
+
+#ifdef CONFIG_SEC_KEYBOARD_DOCK
+static struct sec_keyboard_callbacks *keyboard_callbacks;
+static int check_sec_keyboard_dock(bool attached)
+{
+	if (keyboard_callbacks && keyboard_callbacks->check_keyboard_dock)
+		return keyboard_callbacks->
+			check_keyboard_dock(keyboard_callbacks, attached);
+	return 0;
+}
+
+static void check_uart_path(bool en)
+{
+	int gpio_uart_sel;
+#ifdef CONFIG_MACH_P8LTE
+	int gpio_uart_sel2;
+
+	gpio_uart_sel = GPIO_UART_SEL1;
+	gpio_uart_sel2 = GPIO_UART_SEL2;
+	if (en)
+		gpio_direction_output(gpio_uart_sel2, 1);
+	else
+		gpio_direction_output(gpio_uart_sel2, 0);
+	printk(KERN_DEBUG "[Keyboard] uart_sel2 : %d\n",
+		gpio_get_value(gpio_uart_sel2));
+#else
+	gpio_uart_sel = GPIO_UART_SEL;
+#endif
+
+	if (en)
+		gpio_direction_output(gpio_uart_sel, 1);
+	else
+		gpio_direction_output(gpio_uart_sel, 0);
+
+	printk(KERN_DEBUG "[Keyboard] uart_sel : %d\n",
+		gpio_get_value(gpio_uart_sel));
+}
+
+static void sec_keyboard_register_cb(struct sec_keyboard_callbacks *cb)
+{
+	keyboard_callbacks = cb;
+}
+
+static struct sec_keyboard_platform_data kbd_pdata = {
+	.accessory_irq_gpio = GPIO_ACCESSORY_INT,
+	.acc_power = smdk_accessory_power,
+	.check_uart_path = check_uart_path,
+	.register_cb = sec_keyboard_register_cb,
+	.wakeup_key = NULL,
+};
+
+static struct platform_device sec_keyboard = {
+	.name	= "sec_keyboard",
+	.id	= -1,
+	.dev = {
+		.platform_data = &kbd_pdata,
+	}
+};
+#endif
+
+#ifdef CONFIG_USB_HOST_NOTIFY
+static void px_usb_otg_power(int active)
+{
+	smdk_accessory_power(2, active);
+}
+
+static void px_usb_otg_en(int active)
+{
+	pr_info("otg %s : %d\n", __func__, active);
+
+	usb_switch_lock();
+
+	if (active) {
+
+#ifdef CONFIG_USB_EHCI_S5P
+		pm_runtime_get_sync(&s5p_device_ehci.dev);
+#endif
+#ifdef CONFIG_USB_OHCI_S5P
+		pm_runtime_get_sync(&s5p_device_ohci.dev);
+#endif
+		usb_switch_set_path(USB_PATH_AP);
+		px_usb_otg_power(1);
+
+		host_notifier_pdata.ndev.mode = NOTIFY_HOST_MODE;
+		if (host_notifier_pdata.usbhostd_start)
+			host_notifier_pdata.usbhostd_start();
+	} else {
+
+#ifdef CONFIG_USB_OHCI_S5P
+		pm_runtime_put_sync(&s5p_device_ohci.dev);
+#endif
+#ifdef CONFIG_USB_EHCI_S5P
+		pm_runtime_put_sync(&s5p_device_ehci.dev);
+#endif
+
+		usb_switch_clr_path(USB_PATH_AP);
+		host_notifier_pdata.ndev.mode = NOTIFY_NONE_MODE;
+		if (host_notifier_pdata.usbhostd_stop)
+			host_notifier_pdata.usbhostd_stop();
+		px_usb_otg_power(0);
+	}
+
+	usb_switch_unlock();
+}
+#endif
+
+struct acc_con_platform_data acc_con_pdata = {
+	.otg_en = px_usb_otg_en,
+	.acc_power = smdk_accessory_power,
+	.usb_ldo_en = NULL,
+	.get_acc_state = smdk_get_acc_state,
+	.get_dock_state = smdk_get_dock_state,
+#ifdef CONFIG_SEC_KEYBOARD_DOCK
+	.check_keyboard = check_sec_keyboard_dock,
+#endif
+	.accessory_irq_gpio = GPIO_ACCESSORY_INT,
+	.dock_irq_gpio = GPIO_DOCK_INT,
+#if defined(CONFIG_SAMSUNG_MHL_9290)
+	.mhl_irq_gpio = GPIO_MHL_INT,
+	.hdmi_hpd_gpio = GPIO_HDMI_HPD,
+#endif
+};
+struct platform_device sec_device_connector = {
+	.name = "acc_con",
+	.id = -1,
+	.dev.platform_data = &acc_con_pdata,
+};
+#endif
+
+#ifdef CONFIG_VIDEO_FIMG2D
+static struct fimg2d_platdata fimg2d_data __initdata = {
+	.hw_ver = 0x41,
+	.parent_clkname = "mout_g2d0",
+	.clkname = "sclk_fimg2d",
+	.gate_clkname = "fimg2d",
+	.clkrate = 199 * 1000000,	/* 160 Mhz */
+};
+#endif
+
+#ifdef CONFIG_EXYNOS_C2C
+struct exynos_c2c_platdata smdk4212_c2c_pdata = {
+	.setup_gpio	= NULL,
+	.shdmem_addr	= C2C_SHAREDMEM_BASE,
+	.shdmem_size	= C2C_MEMSIZE_64,
+	.ap_sscm_addr	= NULL,
+	.cp_sscm_addr	= NULL,
+	.rx_width	= C2C_BUSWIDTH_16,
+	.tx_width	= C2C_BUSWIDTH_16,
+	.clk_opp100	= 400,
+	.clk_opp50	= 266,
+	.clk_opp25	= 0,
+	.default_opp_mode	= C2C_OPP50,
+	.get_c2c_state	= NULL,
+};
+#endif
+/* BUSFREQ to control memory/bus */
+static struct device_domain busfreq;
+
+static struct platform_device exynos4_busfreq = {
+	.id = -1,
+	.name = "exynos-busfreq",
+};
+
+#if defined(CONFIG_SENSORS_BH1721)
+static struct i2c_gpio_platform_data i2c9_platdata = {
+	.sda_pin	= GPIO_PS_ALS_SDA_28V,
+	.scl_pin	= GPIO_PS_ALS_SCL_28V,
+	.udelay	= 2, /* 250KHz */
+	.sda_is_open_drain	= 0,
+	.scl_is_open_drain	= 0,
+	.scl_is_output_only = 0,
+};
+
+static struct platform_device s3c_device_i2c9 = {
+	.name	= "i2c-gpio",
+	.id	= 9,
+	.dev.platform_data	= &i2c9_platdata,
+};
+#endif
+
+#ifdef CONFIG_SENSORS_AK8975C
+static struct i2c_gpio_platform_data i2c10_platdata = {
+	.sda_pin	= GPIO_MSENSOR_SDA_18V,
+	.scl_pin	= GPIO_MSENSOR_SCL_18V,
+	.udelay	= 2, /* 250KHz */
+	.sda_is_open_drain	= 0,
+	.scl_is_open_drain	= 0,
+	.scl_is_output_only = 0,
+};
+
+static struct platform_device s3c_device_i2c10 = {
+	.name	= "i2c-gpio",
+	.id	= 10,
+	.dev.platform_data	= &i2c10_platdata,
+};
+#endif
+
+#ifdef CONFIG_SENSORS_LPS331
+static struct i2c_gpio_platform_data i2c11_platdata = {
+	.sda_pin	= GPIO_BSENSE_SDA_18V,
+	.scl_pin	= GPIO_BENSE_SCL_18V,
+	.udelay	= 2, /* 250KHz */
+	.sda_is_open_drain	= 0,
+	.scl_is_open_drain	= 0,
+	.scl_is_output_only = 0,
+};
+
+static struct platform_device s3c_device_i2c11 = {
+	.name			= "i2c-gpio",
+	.id	= 11,
+	.dev.platform_data	= &i2c11_platdata,
+};
+#endif
+
+/* IR_LED */
+#ifdef CONFIG_IR_REMOCON
+
+static struct platform_device ir_remote_device = {
+	.name = "ir_rc",
+	.id = 0,
+	.dev = {
+	},
+};
+
+static void ir_rc_init_hw(void)
+{
+	s3c_gpio_cfgpin(GPIO_IRDA_CONTROL, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_IRDA_CONTROL, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_IRDA_CONTROL, 0);
+}
+
+#endif
+/* IR_LED */
+
+static struct platform_device *midas_devices[] __initdata = {
+#ifdef CONFIG_ANDROID_RAM_CONSOLE
+	&ram_console_device,
+#endif
+	/* Samsung Power Domain */
+	&exynos4_device_pd[PD_MFC],
+	&exynos4_device_pd[PD_G3D],
+	&exynos4_device_pd[PD_LCD0],
+	&exynos4_device_pd[PD_CAM],
+	&exynos4_device_pd[PD_TV],
+	&exynos4_device_pd[PD_GPS],
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_IS
+	&exynos4_device_pd[PD_ISP],
+#endif
+	&exynos4_device_pd[PD_GPS_ALIVE],
+	/* legacy fimd */
+#ifdef CONFIG_FB_S5P
+	&s3c_device_fb,
+#ifdef CONFIG_FB_S5P_LMS501KF03
+	&s3c_device_spi_gpio,
+#endif
+#endif
+
+#ifdef CONFIG_FB_S5P_MDNIE
+	&mdnie_device,
+#endif
+
+#ifdef CONFIG_HAVE_PWM
+	&s3c_device_timer[0],
+	&s3c_device_timer[1],
+	&s3c_device_timer[2],
+	&s3c_device_timer[3],
+#endif
+
+#ifdef CONFIG_BATTERY_SEC_PX
+	&sec_battery_device,
+#endif
+
+#ifdef CONFIG_SND_SOC_WM8994
+	&vbatt_device,
+#endif
+
+	&s3c_device_wdt,
+	&s3c_device_rtc,
+
+	&s3c_device_i2c0,
+	&s3c_device_i2c1,
+#ifdef CONFIG_S3C_DEV_I2C3
+	&s3c_device_i2c3,
+#endif
+#ifdef CONFIG_S3C_DEV_I2C4
+	&s3c_device_i2c4,
+#endif
+	/* &s3c_device_i2c5, */
+#ifdef CONFIG_S3C_DEV_I2C6
+	&s3c_device_i2c6,
+#endif
+	&s3c_device_i2c7,
+#ifdef CONFIG_S3C_DEV_I2C8
+	&s3c_device_i2c8,
+#endif
+	/* &s3c_device_i2c9, */
+#ifdef CONFIG_SENSORS_AK8975C
+	&s3c_device_i2c10,
+#endif
+#ifdef CONFIG_SENSORS_LPS331
+	&s3c_device_i2c11,
+#endif
+	/* &s3c_device_i2c12, */
+#ifdef CONFIG_SMB347_CHARGER
+	&s3c_device_i2c13,
+#endif
+#ifdef CONFIG_BATTERY_MAX17042_FUELGAUGE_PX
+	&s3c_device_i2c14,
+#endif
+
+#ifdef CONFIG_SAMSUNG_MHL
+	&s3c_device_i2c15,
+	&s3c_device_i2c16,
+#endif
+
+#ifdef CONFIG_MOTOR_DRV_ISA1200
+	&s3c_device_i2c17,
+#endif
+
+#ifdef CONFIG_LEDS_AN30259A
+	&s3c_device_i2c21,
+#endif
+#if defined CONFIG_USB_EHCI_S5P && !defined CONFIG_LINK_DEVICE_HSIC
+	&s5p_device_ehci,
+#endif
+#if defined CONFIG_USB_OHCI_S5P && !defined CONFIG_LINK_DEVICE_HSIC
+	&s5p_device_ohci,
+#endif
+#ifdef CONFIG_USB_GADGET
+	&s3c_device_usbgadget,
+#endif
+#ifdef CONFIG_USB_ANDROID_RNDIS
+	&s3c_device_rndis,
+#endif
+#if defined(CONFIG_USB_ANDROID) || defined(CONFIG_USB_G_ANDROID)
+	&s3c_device_android_usb,
+	&s3c_device_usb_mass_storage,
+#endif
+#ifdef CONFIG_EXYNOS4_DEV_MSHC
+	&s3c_device_mshci,
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC
+	&s3c_device_hsmmc0,
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC1
+	&s3c_device_hsmmc1,
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC2
+	&s3c_device_hsmmc2,
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC3
+	&s3c_device_hsmmc3,
+#endif
+
+#ifdef CONFIG_SND_SAMSUNG_AC97
+	&exynos_device_ac97,
+#endif
+#ifdef CONFIG_SND_SAMSUNG_I2S
+	&exynos_device_i2s0,
+#endif
+#ifdef CONFIG_SND_SAMSUNG_PCM
+	&exynos_device_pcm0,
+#endif
+#ifdef CONFIG_SND_SAMSUNG_SPDIF
+	&exynos_device_spdif,
+#endif
+#if defined(CONFIG_SND_SAMSUNG_RP) || defined(CONFIG_SND_SAMSUNG_ALP)
+	&exynos_device_srp,
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_IS
+	&exynos4_device_fimc_is,
+#endif
+#ifdef CONFIG_FB_S5P_LD9040
+	&ld9040_spi_gpio,
+#endif
+#ifdef CONFIG_FB_S5P_S6C1372
+	&lcd_s6c1372,
+#endif
+#ifdef CONFIG_VIDEO_TVOUT
+	&s5p_device_tvout,
+	&s5p_device_cec,
+	&s5p_device_hpd,
+#endif
+#ifdef CONFIG_FB_S5P_EXTDSP
+	&s3c_device_extdsp,
+#endif
+#ifdef CONFIG_VIDEO_FIMC
+	&s3c_device_fimc0,
+	&s3c_device_fimc1,
+	&s3c_device_fimc2,
+	&s3c_device_fimc3,
+/* CONFIG_VIDEO_SAMSUNG_S5P_FIMC is the feature for mainline */
+#elif defined(CONFIG_VIDEO_SAMSUNG_S5P_FIMC)
+	&s5p_device_fimc0,
+	&s5p_device_fimc1,
+	&s5p_device_fimc2,
+	&s5p_device_fimc3,
+#endif
+#if defined(CONFIG_VIDEO_FIMC_MIPI)
+	&s3c_device_csis0,
+	&s3c_device_csis1,
+#endif
+#if defined(CONFIG_VIDEO_MFC5X) || defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC)
+	&s5p_device_mfc,
+#endif
+#ifdef CONFIG_S5P_SYSTEM_MMU
+	&SYSMMU_PLATDEV(g2d_acp),
+	&SYSMMU_PLATDEV(fimc0),
+	&SYSMMU_PLATDEV(fimc1),
+	&SYSMMU_PLATDEV(fimc2),
+	&SYSMMU_PLATDEV(fimc3),
+	&SYSMMU_PLATDEV(jpeg),
+	&SYSMMU_PLATDEV(mfc_l),
+	&SYSMMU_PLATDEV(mfc_r),
+	&SYSMMU_PLATDEV(tv),
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_IS
+	&SYSMMU_PLATDEV(is_isp),
+	&SYSMMU_PLATDEV(is_drc),
+	&SYSMMU_PLATDEV(is_fd),
+	&SYSMMU_PLATDEV(is_cpu),
+#endif
+#endif
+#ifdef CONFIG_ION_EXYNOS
+	&exynos_device_ion,
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_LITE
+	&exynos_device_flite0,
+	&exynos_device_flite1,
+#endif
+#ifdef CONFIG_VIDEO_FIMG2D
+	&s5p_device_fimg2d,
+#endif
+
+#ifdef CONFIG_VIDEO_JPEG_V2X
+	&s5p_device_jpeg,
+#endif
+	&samsung_asoc_dma,
+#ifndef CONFIG_SND_SOC_SAMSUNG_USE_DMA_WRAPPER
+	&samsung_asoc_idma,
+#endif
+#ifdef CONFIG_EXYNOS_C2C
+	&exynos_device_c2c,
+#endif
+#if defined(CONFIG_S3C64XX_DEV_SPI)
+#if defined(CONFIG_VIDEO_S5C73M3_SPI)
+	&exynos_device_spi1,
+#endif
+#if defined(CONFIG_PHONE_IPC_SPI)
+	&exynos_device_spi2,
+	&ipc_spi_device,
+#elif defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE)
+	&exynos_device_spi2,
+#endif
+#endif
+
+#ifdef CONFIG_BT_BCM4334
+	&bcm4334_bluetooth_device,
+#endif
+#ifdef CONFIG_S5P_DEV_ACE
+	&s5p_device_ace,
+#endif
+	&exynos4_busfreq,
+#ifdef CONFIG_USB_HOST_NOTIFY
+	&host_notifier_device,
+#endif
+#ifdef CONFIG_EXYNOS4_SETUP_THERMAL
+	&s5p_device_tmu,
+#endif
+#ifdef CONFIG_30PIN_CONN
+	&sec_device_connector,
+#ifdef CONFIG_SEC_KEYBOARD_DOCK
+	&sec_keyboard,
+#endif
+#endif
+#if defined(CONFIG_IR_REMOCON)
+/* IR_LED */
+	&ir_remote_device,
+/* IR_LED */
+#endif
+
+};
+
+#ifdef CONFIG_EXYNOS4_SETUP_THERMAL
+/* below temperature base on the celcius degree */
+struct s5p_platform_tmu midas_tmu_data __initdata = {
+	.ts = {
+		.stop_1st_throttle  = 78,
+		.start_1st_throttle = 80,
+		.stop_2nd_throttle  = 87,
+		.start_2nd_throttle = 103,
+		.start_tripping	    = 110, /* temp to do tripping */
+		.start_emergency    = 120, /* To protect chip,forcely kernel panic */
+		.stop_mem_throttle  = 80,
+		.start_mem_throttle = 85,
+		.stop_tc  = 13,
+		.start_tc = 10,
+	},
+	.cpufreq = {
+		.limit_1st_throttle  = 800000, /* 800MHz in KHz order */
+		.limit_2nd_throttle  = 200000, /* 200MHz in KHz order */
+	},
+	.temp_compensate = {
+		.arm_volt = 900000, /* vdd_arm in uV for temp compensation */
+		.bus_volt = 900000, /* vdd_bus in uV for temp compensation */
+		.g3d_volt = 900000, /* vdd_g3d in uV for temp compensation */
+	},
+};
+#endif
+
+#if defined CONFIG_USB_OHCI_S5P && defined CONFIG_LINK_DEVICE_HSIC
+static int __init s5p_ohci_device_initcall(void)
+{
+	return platform_device_register(&s5p_device_ohci);
+}
+late_initcall(s5p_ohci_device_initcall);
+#endif
+#if defined CONFIG_USB_EHCI_S5P && defined CONFIG_LINK_DEVICE_HSIC
+static int __init s5p_ehci_device_initcall(void)
+{
+	return platform_device_register(&s5p_device_ehci);
+}
+late_initcall(s5p_ehci_device_initcall);
+#endif
+
+#if defined(CONFIG_VIDEO_TVOUT)
+static struct s5p_platform_hpd hdmi_hpd_data __initdata = {
+
+};
+static struct s5p_platform_cec hdmi_cec_data __initdata = {
+
+};
+#endif
+
+#if defined(CONFIG_CMA)
+static void __init exynos4_reserve_mem(void)
+{
+	static struct cma_region regions[] = {
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_IS
+		{
+			.name = "fimc_is",
+			.size = CONFIG_VIDEO_EXYNOS_MEMSIZE_FIMC_IS * SZ_1K,
+			{
+				.alignment = 1 << 26,
+			},
+			.start = 0
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMD
+		{
+			.name = "fimd",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMD * SZ_1K,
+			.start = 0
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC0
+		{
+			.name = "fimc0",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC0 * SZ_1K,
+			.start = 0
+		},
+#endif
+#if !defined(CONFIG_EXYNOS_CONTENT_PATH_PROTECTION) && \
+	defined(CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC0)
+		{
+			.name = "mfc0",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC0 * SZ_1K,
+			{
+				.alignment = 1 << 17,
+			},
+			.start = 0,
+		},
+#endif
+#if !defined(CONFIG_EXYNOS_CONTENT_PATH_PROTECTION) && \
+	defined(CONFIG_ION_EXYNOS_CONTIGHEAP_SIZE)
+		{
+			.name	= "ion",
+			.size	= CONFIG_ION_EXYNOS_CONTIGHEAP_SIZE * SZ_1K,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC
+		{
+			.name = "mfc",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC * SZ_1K,
+			{
+				.alignment = 1 << 17,
+			},
+			.start = 0
+		},
+#endif
+#if !defined(CONFIG_EXYNOS_CONTENT_PATH_PROTECTION) && \
+	defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC)
+		{
+			.name		= "b2",
+			.size		= 32 << 20,
+			{ .alignment	= 128 << 10 },
+		},
+		{
+			.name		= "b1",
+			.size		= 32 << 20,
+			{ .alignment	= 128 << 10 },
+		},
+		{
+			.name		= "fw",
+			.size		= 1 << 20,
+			{ .alignment	= 128 << 10 },
+		},
+#endif
+#if (CONFIG_VIDEO_SAMSUNG_MEMSIZE_JPEG > 0)
+		{
+			.name = "jpeg",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_JPEG * SZ_1K,
+			.start = 0
+		},
+#endif
+#ifdef CONFIG_AUDIO_SAMSUNG_MEMSIZE_SRP
+		{
+			.name = "srp",
+			.size = CONFIG_AUDIO_SAMSUNG_MEMSIZE_SRP * SZ_1K,
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMG2D
+		{
+			.name = "fimg2d",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMG2D * SZ_1K,
+			.start = 0
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC1
+		{
+			.name = "fimc1",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC1 * SZ_1K,
+			.start = 0x65c00000,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC1
+		{
+			.name = "mfc1",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC1 * SZ_1K,
+			{
+				.alignment = 1 << 26,
+			},
+			.start = 0x64000000,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC_NORMAL
+		{
+			.name = "mfc-normal",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC_NORMAL * SZ_1K,
+			.start = 0x64000000,
+		},
+#endif
+		{
+			.size = 0
+		},
+	};
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+	static struct cma_region regions_secure[] = {
+#ifdef CONFIG_ION_EXYNOS_CONTIGHEAP_SIZE
+		{
+			.name	= "ion",
+			.size	= CONFIG_ION_EXYNOS_CONTIGHEAP_SIZE * SZ_1K,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC_SECURE
+		{
+			.name = "mfc-secure",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC_SECURE * SZ_1K,
+		},
+#endif
+		{
+			.name = "sectbl",
+			.size = SZ_1M,
+		},
+		{
+			.size = 0
+		},
+	};
+#else /* !CONFIG_EXYNOS_CONTENT_PATH_PROTECTION */
+	struct cma_region *regions_secure = NULL;
+#endif
+
+	static const char map[] __initconst =
+#ifdef CONFIG_EXYNOS_C2C
+		"samsung-c2c=c2c_shdmem;"
+#endif
+		"s3cfb.0=fimd;exynos4-fb.0=fimd;"
+		"s3c-fimc.0=fimc0;s3c-fimc.1=fimc1;s3c-fimc.2=fimc2;s3c-fimc.3=fimc3;"
+		"exynos4210-fimc.0=fimc0;exynos4210-fimc.1=fimc1;exynos4210-fimc.2=fimc2;exynos4210-fimc.3=fimc3;"
+#ifdef CONFIG_ION_EXYNOS
+		"ion-exynos=ion;"
+#endif
+#ifdef CONFIG_VIDEO_MFC5X
+		"s3c-mfc/A=mfc0,mfc-secure;"
+		"s3c-mfc/B=mfc1,mfc-normal;"
+		"s3c-mfc/AB=mfc;"
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_S5P_MFC
+		"s5p-mfc/f=fw;"
+		"s5p-mfc/a=b1;"
+		"s5p-mfc/b=b2;"
+#endif
+		"samsung-rp=srp;"
+#if (CONFIG_VIDEO_SAMSUNG_MEMSIZE_JPEG > 0)
+		"s5p-jpeg=jpeg;"
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_IS
+		"exynos4-fimc-is=fimc_is;"
+#endif
+		"s5p-fimg2d=fimg2d;"
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+		"s5p-smem/sectbl=sectbl;"
+#endif
+		"s5p-smem/mfc=mfc-secure;"
+		"s5p-smem/fimc=ion;"
+		"s5p-smem/mfc-shm=mfc-normal;"
+		"s5p-smem/fimd=fimd;";
+
+		s5p_cma_region_reserve(regions, regions_secure, 0, map);
+}
+#else
+static inline void exynos4_reserve_mem(void)
+{
+}
+#endif
+
+#ifdef CONFIG_BACKLIGHT_PWM
+/* LCD Backlight data */
+static struct samsung_bl_gpio_info smdk4212_bl_gpio_info = {
+	.no = EXYNOS4_GPD0(1),
+	.func = S3C_GPIO_SFN(2),
+};
+
+static struct platform_pwm_backlight_data smdk4212_bl_data = {
+	.pwm_id = 1,
+#ifdef CONFIG_FB_S5P_LMS501KF03
+	.pwm_period_ns = 1000,
+#endif
+};
+#endif
+
+static void __init midas_map_io(void)
+{
+	clk_xusbxti.rate = 24000000;
+	s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+	s3c24xx_init_clocks(24000000);
+	s3c24xx_init_uarts(smdk4212_uartcfgs, ARRAY_SIZE(smdk4212_uartcfgs));
+
+#if defined(CONFIG_S5P_MEM_CMA)
+	exynos4_reserve_mem();
+#endif
+
+	/* as soon as INFORM6 is visible, sec_debug is ready to run */
+	sec_debug_init();
+}
+
+static void __init exynos_sysmmu_init(void)
+{
+	ASSIGN_SYSMMU_POWERDOMAIN(fimc0, &exynos4_device_pd[PD_CAM].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(fimc1, &exynos4_device_pd[PD_CAM].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(fimc2, &exynos4_device_pd[PD_CAM].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(fimc3, &exynos4_device_pd[PD_CAM].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(jpeg, &exynos4_device_pd[PD_CAM].dev);
+
+#if defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC) || defined(CONFIG_VIDEO_MFC5X)
+	ASSIGN_SYSMMU_POWERDOMAIN(mfc_l, &exynos4_device_pd[PD_MFC].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(mfc_r, &exynos4_device_pd[PD_MFC].dev);
+#endif
+	ASSIGN_SYSMMU_POWERDOMAIN(tv, &exynos4_device_pd[PD_TV].dev);
+#ifdef CONFIG_VIDEO_FIMG2D
+	sysmmu_set_owner(&SYSMMU_PLATDEV(g2d_acp).dev, &s5p_device_fimg2d.dev);
+#endif
+#ifdef CONFIG_VIDEO_MFC5X
+	sysmmu_set_owner(&SYSMMU_PLATDEV(mfc_l).dev, &s5p_device_mfc.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(mfc_r).dev, &s5p_device_mfc.dev);
+#endif
+#ifdef CONFIG_VIDEO_FIMC
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc0).dev, &s3c_device_fimc0.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc1).dev, &s3c_device_fimc1.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc2).dev, &s3c_device_fimc2.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc3).dev, &s3c_device_fimc3.dev);
+#endif
+#ifdef CONFIG_VIDEO_TVOUT
+	sysmmu_set_owner(&SYSMMU_PLATDEV(tv).dev, &s5p_device_tvout.dev);
+#endif
+#ifdef CONFIG_VIDEO_JPEG_V2X
+	sysmmu_set_owner(&SYSMMU_PLATDEV(jpeg).dev, &s5p_device_jpeg.dev);
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_IS
+	ASSIGN_SYSMMU_POWERDOMAIN(is_isp, &exynos4_device_pd[PD_ISP].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(is_drc, &exynos4_device_pd[PD_ISP].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(is_fd, &exynos4_device_pd[PD_ISP].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(is_cpu, &exynos4_device_pd[PD_ISP].dev);
+
+	sysmmu_set_owner(&SYSMMU_PLATDEV(is_isp).dev,
+		&exynos4_device_fimc_is.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(is_drc).dev,
+		&exynos4_device_fimc_is.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(is_fd).dev,
+		&exynos4_device_fimc_is.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(is_cpu).dev,
+		&exynos4_device_fimc_is.dev);
+#endif
+}
+
+#ifdef CONFIG_FB_S5P_EXTDSP
+struct platform_device s3c_device_extdsp = {
+	.name		= "s3cfb_extdsp",
+	.id		= 0,
+};
+
+static struct s3cfb_extdsp_lcd dummy_buffer = {
+	.width = 1920,
+	.height = 1080,
+	.bpp = 16,
+};
+
+static struct s3c_platform_fb default_extdsp_data __initdata = {
+	.hw_ver		= 0x70,
+	.nr_wins	= 1,
+	.default_win	= 0,
+	.swap		= FB_SWAP_WORD | FB_SWAP_HWORD,
+	.lcd		= &dummy_buffer
+};
+
+void __init s3cfb_extdsp_set_platdata(struct s3c_platform_fb *pd)
+{
+	struct s3c_platform_fb *npd;
+	int i;
+
+	if (!pd)
+		pd = &default_extdsp_data;
+
+	npd = kmemdup(pd, sizeof(struct s3c_platform_fb), GFP_KERNEL);
+	if (!npd)
+		printk(KERN_ERR "%s: no memory for platform data\n", __func__);
+	else {
+		for (i = 0; i < npd->nr_wins; i++)
+			npd->nr_buffers[i] = 1;
+		s3c_device_extdsp.dev.platform_data = npd;
+	}
+}
+#endif
+
+static inline int need_i2c5(void)
+{
+	return 1; /* orig: system_rev != 3; */
+}
+
+static void __init midas_machine_init(void)
+{
+	struct clk *ppmu_clk = NULL;
+
+#if defined(CONFIG_S3C64XX_DEV_SPI)
+#if defined(CONFIG_VIDEO_S5C73M3_SPI)
+	unsigned int gpio;
+	struct clk *sclk = NULL;
+	struct clk *prnt = NULL;
+	struct device *spi1_dev = &exynos_device_spi1.dev;
+#endif
+#if defined(CONFIG_PHONE_IPC_SPI) \
+	|| defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE)
+	struct device *spi2_dev = &exynos_device_spi2.dev;
+#endif
+#endif
+
+	/*
+	  * prevent 4x12 ISP power off problem
+	  * ISP_SYS Register has to be 0 before ISP block power off.
+	  */
+	__raw_writel(0x0, S5P_CMU_RESET_ISP_SYS);
+
+	/* initialise the gpios */
+	midas_config_gpio_table();
+	exynos4_sleep_gpio_table_set = midas_config_sleep_gpio_table;
+
+	midas_power_init();
+
+	s3c_i2c0_set_platdata(NULL);
+	i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
+
+	s3c_i2c1_set_platdata(NULL);
+	i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
+
+	p4_tsp_init(system_rev);
+	p4_key_init();
+#if defined(CONFIG_EPEN_WACOM_G5SP)
+	p4_wacom_init();
+#endif	/* CONFIG_EPEN_WACOM_G5SP */
+
+#ifdef CONFIG_LEDS_AAT1290A
+	platform_device_register(&s3c_device_aat1290a_led);
+#endif
+	midas_sound_init();
+
+#ifdef CONFIG_S3C_DEV_I2C5
+	if (need_i2c5()) {
+		s3c_i2c5_set_platdata(NULL);
+		i2c_register_board_info(5, i2c_devs5,
+			ARRAY_SIZE(i2c_devs5));
+	}
+#endif
+
+	s3c_i2c7_set_platdata(NULL);
+	i2c_register_board_info(7, i2c_devs7, ARRAY_SIZE(i2c_devs7));
+
+	i2c_register_board_info(9, i2c_devs9_emul, ARRAY_SIZE(i2c_devs9_emul));
+
+	i2c_register_board_info(10, i2c_devs10_emul,
+				ARRAY_SIZE(i2c_devs10_emul));
+
+	i2c_register_board_info(11, i2c_devs11_emul,
+				ARRAY_SIZE(i2c_devs11_emul));
+
+#ifdef CONFIG_SMB347_CHARGER
+	/* smb347 charger */
+	i2c_register_board_info(13, i2c_devs13_emul,
+				ARRAY_SIZE(i2c_devs13_emul));
+#endif
+
+#ifdef CONFIG_BATTERY_MAX17042_FUELGAUGE_PX
+	/* max17042 fuelgauge */
+	i2c_register_board_info(14, i2c_devs14_emul,
+				ARRAY_SIZE(i2c_devs14_emul));
+#endif
+#ifdef CONFIG_SAMSUNG_MHL
+	printk(KERN_INFO "%s() register sii9234 driver\n", __func__);
+
+	i2c_register_board_info(15, i2c_devs15_emul,
+				ARRAY_SIZE(i2c_devs15_emul));
+	i2c_register_board_info(16, i2c_devs16_emul,
+				ARRAY_SIZE(i2c_devs16_emul));
+#endif
+
+#ifdef CONFIG_MOTOR_DRV_ISA1200
+	isa1200_init();
+	i2c_register_board_info(17, i2c_devs17_emul,
+				ARRAY_SIZE(i2c_devs17_emul));
+#endif
+
+#if defined(CONFIG_STMPE811_ADC) || defined(CONFIG_FM_SI4709_MODULE) \
+	|| defined(CONFIG_FM_SI4705_MODULE)
+	i2c_register_board_info(19, i2c_devs19_emul,
+				ARRAY_SIZE(i2c_devs19_emul));
+#endif
+
+#ifdef CONFIG_LEDS_AN30259A
+	i2c_register_board_info(21, i2c_devs21_emul,
+				ARRAY_SIZE(i2c_devs21_emul));
+#endif
+
+#if defined(GPIO_OLED_DET)
+	gpio_request(GPIO_OLED_DET, "OLED_DET");
+	s5p_register_gpio_interrupt(GPIO_OLED_DET);
+	gpio_free(GPIO_OLED_DET);
+#endif
+#ifdef CONFIG_FB_S5P
+#ifdef CONFIG_FB_S5P_LMS501KF03
+	spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
+	s3cfb_set_platdata(&lms501kf03_data);
+#endif
+#if defined(CONFIG_BACKLIGHT_PWM)
+	samsung_bl_set(&smdk4212_bl_gpio_info, &smdk4212_bl_data);
+#elif defined(CONFIG_FB_S5P_S6C1372)
+	s6c1372_panel_gpio_init();
+#endif
+	s3cfb_set_platdata(&fb_platform_data);
+#ifdef CONFIG_EXYNOS_DEV_PD
+	s3c_device_fb.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
+#endif
+#endif
+#ifdef CONFIG_USB_EHCI_S5P
+	smdk4212_ehci_init();
+#endif
+#ifdef CONFIG_USB_OHCI_S5P
+	smdk4212_ohci_init();
+#endif
+#ifdef CONFIG_USB_GADGET
+	smdk4212_usbgadget_init();
+#endif
+
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_IS
+	exynos4_fimc_is_set_platdata(NULL);
+#ifdef CONFIG_EXYNOS_DEV_PD
+	exynos4_device_fimc_is.dev.parent = &exynos4_device_pd[PD_ISP].dev;
+#endif
+#endif
+#ifdef CONFIG_EXYNOS4_DEV_MSHC
+	s3c_mshci_set_platdata(&exynos4_mshc_pdata);
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC
+	s3c_sdhci0_set_platdata(&smdk4212_hsmmc0_pdata);
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC1
+	s3c_sdhci1_set_platdata(&smdk4212_hsmmc1_pdata);
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC2
+	s3c_sdhci2_set_platdata(&smdk4212_hsmmc2_pdata);
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC3
+	s3c_sdhci3_set_platdata(&smdk4212_hsmmc3_pdata);
+#endif
+
+	midas_camera_init();
+
+#ifdef CONFIG_FB_S5P_EXTDSP
+	s3cfb_extdsp_set_platdata(&default_extdsp_data);
+#endif
+
+#if defined(CONFIG_VIDEO_TVOUT)
+	s5p_hdmi_hpd_set_platdata(&hdmi_hpd_data);
+	s5p_hdmi_cec_set_platdata(&hdmi_cec_data);
+#ifdef CONFIG_EXYNOS_DEV_PD
+	s5p_device_tvout.dev.parent = &exynos4_device_pd[PD_TV].dev;
+	exynos4_device_pd[PD_TV].dev.parent = &exynos4_device_pd[PD_LCD0].dev;
+#endif
+#endif
+
+#ifdef CONFIG_VIDEO_JPEG_V2X
+#ifdef CONFIG_EXYNOS_DEV_PD
+	s5p_device_jpeg.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+	exynos4_jpeg_setup_clock(&s5p_device_jpeg.dev, 160000000);
+#endif
+#endif
+
+#ifdef CONFIG_ION_EXYNOS
+	exynos_ion_set_platdata();
+#endif
+
+#if defined(CONFIG_VIDEO_MFC5X) || defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC)
+#ifdef CONFIG_EXYNOS_DEV_PD
+	s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
+#endif
+	exynos4_mfc_setup_clock(&s5p_device_mfc.dev, 200 * MHZ);
+#endif
+
+#if defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC)
+	dev_set_name(&s5p_device_mfc.dev, "s3c-mfc");
+	clk_add_alias("mfc", "s5p-mfc", "mfc", &s5p_device_mfc.dev);
+	s5p_mfc_setname(&s5p_device_mfc, "s5p-mfc");
+#endif
+#ifdef CONFIG_VIDEO_FIMG2D
+	s5p_fimg2d_set_platdata(&fimg2d_data);
+#endif
+#ifdef CONFIG_EXYNOS_C2C
+	exynos_c2c_set_platdata(&smdk4212_c2c_pdata);
+#endif
+
+	brcm_wlan_init();
+
+#ifdef CONFIG_EXYNOS4_SETUP_THERMAL
+	s5p_tmu_set_platdata(&midas_tmu_data);
+#endif
+
+	exynos_sysmmu_init();
+
+	platform_add_devices(midas_devices, ARRAY_SIZE(midas_devices));
+
+#ifdef CONFIG_S3C_ADC
+	platform_device_register(&s3c_device_adc);
+#endif
+#if defined(CONFIG_STMPE811_ADC) || defined(CONFIG_FM_SI4709_MODULE) \
+	|| defined(CONFIG_FM_SI4705_MODULE)
+	platform_device_register(&s3c_device_i2c19);
+#endif
+#ifdef CONFIG_SEC_THERMISTOR
+	platform_device_register(&sec_device_thermistor);
+#endif
+
+#if defined(CONFIG_S3C_DEV_I2C5)
+	if (need_i2c5())
+		platform_device_register(&s3c_device_i2c5);
+#endif
+
+#if defined(CONFIG_SENSORS_BH1721)
+	platform_device_register(&s3c_device_i2c9);
+#endif
+
+#ifdef CONFIG_30PIN_CONN
+	smdk_accessory_gpio_init();
+#endif
+#ifdef CONFIG_USB_HOST_NOTIFY
+	acc_chk_gpio_init();
+#endif
+
+#if defined(CONFIG_SEC_DEV_JACK)
+	p4note_jack_init();
+#endif
+
+#if defined(CONFIG_S3C64XX_DEV_SPI)
+#if defined(CONFIG_VIDEO_S5C73M3_SPI)
+	sclk = clk_get(spi1_dev, "dout_spi1");
+	if (IS_ERR(sclk))
+		dev_err(spi1_dev, "failed to get sclk for SPI-1\n");
+	prnt = clk_get(spi1_dev, "mout_mpll_user");
+	if (IS_ERR(prnt))
+		dev_err(spi1_dev, "failed to get prnt\n");
+	if (clk_set_parent(sclk, prnt))
+		printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
+		       prnt->name, sclk->name);
+
+	clk_set_rate(sclk, 800 * 1000 * 1000);
+	clk_put(sclk);
+	clk_put(prnt);
+
+	if (!gpio_request(EXYNOS4_GPB(5), "SPI_CS1")) {
+		gpio_direction_output(EXYNOS4_GPB(5), 1);
+		s3c_gpio_cfgpin(EXYNOS4_GPB(5), S3C_GPIO_SFN(1));
+		s3c_gpio_setpull(EXYNOS4_GPB(5), S3C_GPIO_PULL_UP);
+		exynos_spi_set_info(1, EXYNOS_SPI_SRCCLK_SCLK,
+				    ARRAY_SIZE(spi1_csi));
+	}
+
+	for (gpio = EXYNOS4_GPB(4); gpio < EXYNOS4_GPB(8); gpio++)
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV3);
+
+	spi_register_board_info(spi1_board_info, ARRAY_SIZE(spi1_board_info));
+#endif
+
+#if defined(CONFIG_PHONE_IPC_SPI) \
+	|| defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE)
+	sclk = NULL;
+	prnt = NULL;
+
+	sclk = clk_get(spi2_dev, "dout_spi2");
+	if (IS_ERR(sclk))
+		dev_err(spi2_dev, "failed to get sclk for SPI-2\n");
+	prnt = clk_get(spi2_dev, "mout_mpll_user");
+	if (IS_ERR(prnt))
+		dev_err(spi2_dev, "failed to get prnt\n");
+	if (clk_set_parent(sclk, prnt))
+		printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
+		       prnt->name, sclk->name);
+
+	clk_put(sclk);
+	clk_put(prnt);
+
+	if (!gpio_request(EXYNOS4_GPC1(2), "SPI_CS2")) {
+		gpio_direction_output(EXYNOS4_GPC1(2), 1);
+		s3c_gpio_cfgpin(EXYNOS4_GPC1(2), S3C_GPIO_SFN(1));
+		s3c_gpio_setpull(EXYNOS4_GPC1(2), S3C_GPIO_PULL_UP);
+		exynos_spi_set_info(2, EXYNOS_SPI_SRCCLK_SCLK,
+			ARRAY_SIZE(spi2_csi));
+	}
+	for (gpio = EXYNOS4_GPC1(1); gpio < EXYNOS4_GPC1(5); gpio++)
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV3);
+
+	spi_register_board_info(spi2_board_info, ARRAY_SIZE(spi2_board_info));
+#endif
+
+#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE)
+	tdmb_dev_init();
+#endif
+#endif
+
+#ifdef CONFIG_BUSFREQ_OPP
+	dev_add(&busfreq, &exynos4_busfreq.dev);
+
+	/* PPMUs using for cpufreq get clk from clk_list */
+	ppmu_clk = clk_get(NULL, "ppmudmc0");
+	if (IS_ERR(ppmu_clk))
+		printk(KERN_ERR "failed to get ppmu_dmc0\n");
+	clk_enable(ppmu_clk);
+	clk_put(ppmu_clk);
+
+	ppmu_clk = clk_get(NULL, "ppmudmc1");
+	if (IS_ERR(ppmu_clk))
+		printk(KERN_ERR "failed to get ppmu_dmc1\n");
+	clk_enable(ppmu_clk);
+	clk_put(ppmu_clk);
+
+	ppmu_clk = clk_get(NULL, "ppmucpu");
+	if (IS_ERR(ppmu_clk))
+		printk(KERN_ERR "failed to get ppmu_cpu\n");
+	clk_enable(ppmu_clk);
+	clk_put(ppmu_clk);
+
+	ppmu_init(&exynos_ppmu[PPMU_DMC0], &exynos4_busfreq.dev);
+	ppmu_init(&exynos_ppmu[PPMU_DMC1], &exynos4_busfreq.dev);
+	ppmu_init(&exynos_ppmu[PPMU_CPU], &exynos4_busfreq.dev);
+#endif
+
+
+	/* 400 kHz for initialization of MMC Card  */
+	__raw_writel((__raw_readl(EXYNOS4_CLKDIV_FSYS3) & 0xfffffff0)
+		     | 0x9, EXYNOS4_CLKDIV_FSYS3);
+	__raw_writel((__raw_readl(EXYNOS4_CLKDIV_FSYS2) & 0xfff0fff0)
+		     | 0x80008, EXYNOS4_CLKDIV_FSYS2);
+	__raw_writel((__raw_readl(EXYNOS4_CLKDIV_FSYS1) & 0xfff0fff0)
+		     | 0x80008, EXYNOS4_CLKDIV_FSYS1);
+
+#if defined(CONFIG_IR_REMOCON)
+/* IR_LED */
+	ir_rc_init_hw();
+/* IR_LED */
+#endif
+}
+
+#ifdef CONFIG_EXYNOS_C2C
+static void __init exynos_c2c_reserve(void)
+{
+	static struct cma_region region = {
+			.name = "c2c_shdmem",
+			.size = 64 * SZ_1M,
+			{ .alignment	= 64 * SZ_1M },
+			.start = C2C_SHAREDMEM_BASE
+	};
+
+	BUG_ON(cma_early_region_register(&region));
+	BUG_ON(cma_early_region_reserve(&region));
+
+	pr_info("%s %10s %8x %8x\n", __func__,
+		region.name, region.start, region.size);
+}
+#endif
+
+static void __init exynos_init_reserve(void)
+{
+	sec_debug_magic_init();
+}
+
+MACHINE_START(SMDK4412, "SMDK4x12")
+	.boot_params	= S5P_PA_SDRAM + 0x100,
+	.init_irq	= exynos4_init_irq,
+	.map_io		= midas_map_io,
+	.init_machine	= midas_machine_init,
+	.timer		= &exynos4_timer,
+#ifdef CONFIG_EXYNOS_C2C
+	.reserve	= &exynos_c2c_reserve,
+#endif
+	.init_early	= &exynos_init_reserve,
+MACHINE_END
+
+MACHINE_START(SMDK4212, "SMDK4x12")
+	.boot_params	= S5P_PA_SDRAM + 0x100,
+	.init_irq	= exynos4_init_irq,
+	.map_io		= midas_map_io,
+	.init_machine	= midas_machine_init,
+	.timer		= &exynos4_timer,
+#ifdef CONFIG_EXYNOS_C2C
+	.reserve	= &exynos_c2c_reserve,
+#endif
+	.init_early	= &exynos_init_reserve,
+MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-px.c b/arch/arm/mach-exynos/mach-px.c
new file mode 100644
index 0000000..8ab8c7a
--- /dev/null
+++ b/arch/arm/mach-exynos/mach-px.c
@@ -0,0 +1,7558 @@
+/* linux/arch/arm/mach-exynos4/mach-smdkc210.c
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/serial_core.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/gpio_keys.h>
+#include <linux/gpio_event.h>
+#include <linux/lcd.h>
+#include <linux/mmc/host.h>
+#include <linux/platform_device.h>
+#include <linux/smsc911x.h>
+#include <linux/io.h>
+#include <linux/i2c.h>
+#include <linux/i2c-gpio.h>
+#include <linux/input.h>
+#include <linux/switch.h>
+#include <linux/spi/spi.h>
+#include <linux/pwm_backlight.h>
+#include <linux/spi/spi_gpio.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+#include <linux/mfd/max8997.h>
+#include <linux/mfd/max8997-private.h>
+#include <linux/sensor/k3g.h>
+#include <linux/sensor/k3dh.h>
+#include <linux/sensor/ak8975.h>
+#include <linux/sensor/cm3663.h>
+#include <linux/pn544.h>
+#ifdef CONFIG_SND_SOC_U1_MC1N2
+#include <linux/mfd/mc1n2_pdata.h>
+#endif
+#if defined(CONFIG_TOUCHSCREEN_MXT540E)
+#include <linux/i2c/mxt540e.h>
+#elif defined(CONFIG_TOUCHSCREEN_MXT768E)
+#include <linux/i2c/mxt768e.h>
+#elif defined(CONFIG_TOUCHSCREEN_MMS152)
+#include <linux/mms152.h>
+#else
+#include <linux/i2c/mxt224_u1.h>
+#endif
+#ifdef CONFIG_TOUCHSCREEN_MXT1386
+#include <linux/atmel_mxt1386.h>
+#endif
+#include <linux/memblock.h>
+#include <linux/power_supply.h>
+#if defined(CONFIG_S5P_MEM_CMA)
+#include <linux/cma.h>
+#endif
+#ifdef CONFIG_ANDROID_PMEM
+#include <linux/android_pmem.h>
+#endif
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <video/platform_lcd.h>
+
+#include <plat/regs-serial.h>
+#include <plat/regs-srom.h>
+#include <plat/exynos4.h>
+#include <plat/clock.h>
+#include <plat/hwmon.h>
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/fb-s5p.h>
+#include <plat/fimc.h>
+#include <plat/csis.h>
+#include <plat/gpio-cfg.h>
+#include <plat/adc.h>
+#include <plat/ts.h>
+#include <plat/keypad.h>
+#include <plat/sdhci.h>
+#include <plat/mshci.h>
+#include <plat/iic.h>
+#include <plat/sysmmu.h>
+#include <plat/pd.h>
+#include <plat/regs-fb-v4.h>
+#include <plat/media.h>
+#include <plat/udc-hs.h>
+#include <plat/s5p-clock.h>
+#include <plat/tvout.h>
+#include <plat/fimg2d.h>
+#include <plat/ehci.h>
+#include <plat/usbgadget.h>
+#include <plat/regs-otg.h>
+
+#ifdef CONFIG_S3C64XX_DEV_SPI0
+#include <plat/s3c64xx-spi.h>
+#include <mach/spi-clocks.h>
+#endif
+
+#include <mach/map.h>
+#include <mach/exynos-clock.h>
+#include <mach/media.h>
+#include <plat/regs-fb.h>
+
+#include <mach/dev-sysmmu.h>
+#include <mach/dev.h>
+#include <mach/regs-clock.h>
+#include <mach/exynos-ion.h>
+
+#ifdef CONFIG_FB_S5P_MIPI_DSIM
+#include <mach/mipi_ddi.h>
+#include <mach/dsim.h>
+#include <plat/fb-s5p.h>
+#endif
+
+#if defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC) || defined(CONFIG_VIDEO_MFC5X)
+#include <plat/s5p-mfc.h>
+#endif
+
+#ifdef CONFIG_VIDEO_M5MO
+#include <media/m5mo_platform.h>
+#endif
+#ifdef CONFIG_VIDEO_S5K5CCGX_COMMON
+#include <media/s5k5ccgx_platform.h>
+#endif
+#ifdef CONFIG_VIDEO_S5K5BAFX
+#include <media/s5k5bafx_platform.h>
+#endif
+#ifdef CONFIG_VIDEO_SR200PC20
+#include <media/sr200pc20_platform.h>
+#endif
+
+#if defined(CONFIG_EXYNOS4_SETUP_THERMAL)
+#include <plat/s5p-tmu.h>
+#include <mach/regs-tmu.h>
+#endif
+
+#ifdef CONFIG_SEC_DEV_JACK
+#include <linux/sec_jack.h>
+#endif
+
+#ifdef CONFIG_SENSORS_AK8975
+#include <linux/i2c/ak8975.h>
+#endif
+
+#ifdef CONFIG_MPU_SENSORS_MPU3050
+#include <linux/mpu.h>
+#endif
+
+#ifdef CONFIG_OPTICAL_GP2A
+#include <linux/gp2a.h>
+#endif
+
+#ifdef CONFIG_SENSORS_BH1721FVC
+#include <linux/bh1721fvc.h>
+#endif
+
+#ifdef CONFIG_BT_BCM4330
+#include <mach/board-bluetooth-bcm.h>
+#endif
+
+#ifdef CONFIG_BT_CSR8811
+#include <mach/board-bluetooth-csr.h>
+#endif
+
+#ifdef CONFIG_FB_S5P_LD9040
+#include <linux/ld9040.h>
+#endif
+
+#ifdef CONFIG_FB_S5P_MDNIE
+#include <linux/mdnie.h>
+#endif
+
+#include <../../../drivers/video/samsung/s3cfb.h>
+#include "px.h"
+
+#include <mach/sec_debug.h>
+
+#if defined(CONFIG_MHL_SII9234)
+#include <linux/mhd9234.h>
+#endif
+
+#ifdef CONFIG_BATTERY_SEC_PX
+#include <linux/power/sec_battery_px.h>
+#endif
+
+#ifdef CONFIG_SEC_THERMISTOR
+#include <mach/sec_thermistor.h>
+#include "px_thermistor.h"
+#endif
+
+#ifdef CONFIG_BATTERY_MAX17042_FUELGAUGE_PX
+#include <linux/power/max17042_fuelgauge_px.h>
+#endif
+
+#ifdef CONFIG_USB_HOST_NOTIFY
+#include <linux/host_notify.h>
+#endif
+#include <linux/pm_runtime.h>
+
+#ifdef CONFIG_SMB136_CHARGER
+#include <linux/power/smb136_charger.h>
+#endif
+
+#ifdef CONFIG_SMB347_CHARGER
+#include <linux/power/smb347_charger.h>
+#endif
+
+#ifdef CONFIG_30PIN_CONN
+#include <linux/30pin_con.h>
+#include <mach/usb_switch.h>
+#endif
+
+#ifdef CONFIG_EPEN_WACOM_G5SP
+#include <linux/wacom_i2c.h>
+static struct wacom_g5_callbacks *wacom_callbacks;
+#endif /* CONFIG_EPEN_WACOM_G5SP */
+
+static struct charging_status_callbacks {
+	void (*tsp_set_charging_cable) (int type);
+} charging_cbs;
+
+bool is_cable_attached;
+bool is_usb_lpm_enter;
+
+unsigned int lcdtype;
+static int __init lcdtype_setup(char *str)
+{
+	get_option(&str, &lcdtype);
+	return 1;
+}
+__setup("lcdtype=", lcdtype_setup);
+
+/* Following are default values for UCON, ULCON and UFCON UART registers */
+#define SMDKC210_UCON_DEFAULT	(S3C2410_UCON_TXILEVEL |	\
+				 S3C2410_UCON_RXILEVEL |	\
+				 S3C2410_UCON_TXIRQMODE |	\
+				 S3C2410_UCON_RXIRQMODE |	\
+				 S3C2410_UCON_RXFIFO_TOI |	\
+				 S3C2443_UCON_RXERR_IRQEN)
+
+#define SMDKC210_ULCON_DEFAULT	S3C2410_LCON_CS8
+
+#define SMDKC210_UFCON_DEFAULT	(S3C2410_UFCON_FIFOMODE |	\
+				 S5PV210_UFCON_TXTRIG4 |	\
+				 S5PV210_UFCON_RXTRIG4)
+
+static struct s3c2410_uartcfg smdkc210_uartcfgs[] __initdata = {
+	[0] = {
+		.hwport = 0,
+		.flags = 0,
+		.ucon = SMDKC210_UCON_DEFAULT,
+		.ulcon = SMDKC210_ULCON_DEFAULT,
+		.ufcon = SMDKC210_UFCON_DEFAULT,
+#if defined(CONFIG_BT_BCM4330)
+		.wake_peer = bcm_bt_lpm_exit_lpm_locked,
+#elif defined(CONFIG_BT_CSR8811)
+		.wake_peer = csr_bt_lpm_exit_lpm_locked,
+#endif
+	},
+	[1] = {
+		.hwport = 1,
+		.flags = 0,
+		.ucon = SMDKC210_UCON_DEFAULT,
+		.ulcon = SMDKC210_ULCON_DEFAULT,
+		.ufcon = SMDKC210_UFCON_DEFAULT,
+		.set_runstate = set_gps_uart_op,
+	},
+	[2] = {
+		.hwport = 2,
+		.flags = 0,
+		.ucon = SMDKC210_UCON_DEFAULT,
+		.ulcon = SMDKC210_ULCON_DEFAULT,
+		.ufcon = SMDKC210_UFCON_DEFAULT,
+	},
+	[3] = {
+		.hwport = 3,
+		.flags = 0,
+		.ucon = SMDKC210_UCON_DEFAULT,
+		.ulcon = SMDKC210_ULCON_DEFAULT,
+		.ufcon = SMDKC210_UFCON_DEFAULT,
+	},
+};
+
+#define WRITEBACK_ENABLED
+
+#ifdef CONFIG_MACH_PX
+
+static struct platform_device p4w_wlan_ar6000_pm_device = {
+	.name				= "wlan_ar6000_pm_dev",
+	.id					= 1,
+	.num_resources		= 0,
+	.resource			= NULL,
+};
+
+static void
+(*wlan_status_notify_cb)(struct platform_device *dev_id, int card_present);
+struct platform_device *wlan_devid;
+
+static int register_wlan_status_notify
+(void (*callback)(struct platform_device *dev_id, int card_present))
+{
+	wlan_status_notify_cb = callback;
+	return 0;
+}
+
+static int register_wlan_pdev(struct platform_device *pdev)
+{
+	wlan_devid = pdev;
+	printk(KERN_ERR "ATHR register_wlan_pdev pdev->id = %d\n", pdev->id);
+	return 0;
+}
+
+#define WLAN_HOST_WAKE
+#ifdef WLAN_HOST_WAKE
+struct wlansleep_info {
+	unsigned host_wake;
+	unsigned host_wake_irq;
+	struct wake_lock wake_lock;
+};
+
+static struct wlansleep_info *wsi;
+static struct tasklet_struct hostwake_task;
+
+static void wlan_hostwake_task(unsigned long data)
+{
+	printk(KERN_INFO "WLAN: wake lock timeout 0.5 sec...\n");
+
+	wake_lock_timeout(&wsi->wake_lock, HZ / 2);
+}
+
+static irqreturn_t wlan_hostwake_isr(int irq, void *dev_id)
+{
+	tasklet_schedule(&hostwake_task);
+	return IRQ_HANDLED;
+}
+
+static int wlan_host_wake_init(void)
+{
+	int ret;
+
+	wsi = kzalloc(sizeof(struct wlansleep_info), GFP_KERNEL);
+	if (!wsi)
+		return -ENOMEM;
+
+	wake_lock_init(&wsi->wake_lock, WAKE_LOCK_SUSPEND, "bluesleep");
+	tasklet_init(&hostwake_task, wlan_hostwake_task, 0);
+
+	wsi->host_wake = GPIO_WLAN_HOST_WAKE;
+	wsi->host_wake_irq = gpio_to_irq(GPIO_WLAN_HOST_WAKE);
+
+	ret = request_irq(wsi->host_wake_irq, wlan_hostwake_isr,
+				IRQF_DISABLED | IRQF_TRIGGER_RISING,
+				"wlan hostwake", NULL);
+	if (ret	< 0) {
+		printk(KERN_ERR "WLAN: Couldn't acquire WLAN_HOST_WAKE IRQ");
+		return -1;
+	}
+
+	ret = enable_irq_wake(wsi->host_wake_irq);
+	if (ret < 0) {
+		printk(KERN_ERR "WLAN: Couldn't enable WLAN_HOST_WAKE as wakeup interrupt");
+		free_irq(wsi->host_wake_irq, NULL);
+		return -1;
+	}
+
+	return 0;
+}
+
+static void wlan_host_wake_exit(void)
+{
+	if (disable_irq_wake(wsi->host_wake_irq))
+		printk(KERN_ERR "WLAN: Couldn't disable hostwake IRQ wakeup mode\n");
+	free_irq(wsi->host_wake_irq, NULL);
+	tasklet_kill(&hostwake_task);
+	wake_lock_destroy(&wsi->wake_lock);
+	kfree(wsi);
+}
+#endif /* WLAN_HOST_WAKE */
+
+static void config_wlan_gpio(void)
+{
+	int ret = 0;
+	unsigned int gpio;
+
+	printk(KERN_ERR "ATHR - %s\n", __func__);
+	ret = gpio_request(GPIO_WLAN_HOST_WAKE, "wifi_irq");
+	if (ret < 0) {
+		printk(KERN_ERR "cannot reserve GPIO_WLAN_HOST_WAKE: %s - %d\n"\
+				, __func__, GPIO_WLAN_HOST_WAKE);
+		gpio_free(GPIO_WLAN_HOST_WAKE);
+		return;
+	}
+
+	ret = gpio_request(GPIO_WLAN_EN, "wifi_pwr_33");
+
+	if (ret < 0) {
+		printk(KERN_ERR "cannot reserve GPIO_WLAN_EN: %s - %d\n"\
+				, __func__, GPIO_WLAN_EN);
+		gpio_free(GPIO_WLAN_EN);
+		return;
+	}
+
+	if (system_rev >= 4) {
+		ret = gpio_request(GPIO_WLAN_EN2, "wifi_pwr_18");
+
+		if (ret < 0) {
+			printk(KERN_ERR "cannot reserve GPIO_WLAN_EN2: "\
+					"%s - %d\n", __func__, GPIO_WLAN_EN2);
+			gpio_free(GPIO_WLAN_EN2);
+			return;
+		}
+	}
+
+	ret = gpio_request(GPIO_WLAN_nRST, "wifi_rst");
+
+	if (ret < 0) {
+		printk(KERN_ERR "cannot reserve GPIO_WLAN_nRST: %s - %d\n"\
+				, __func__, GPIO_WLAN_nRST);
+		gpio_free(GPIO_WLAN_nRST);
+		return;
+	}
+
+	gpio_direction_output(GPIO_WLAN_nRST, 0);
+	gpio_direction_output(GPIO_WLAN_EN, 1);
+
+	if (system_rev >= 4)
+		gpio_direction_output(GPIO_WLAN_EN2, 0);
+}
+
+void
+wlan_setup_power(int on, int detect)
+{
+	printk(KERN_ERR "ATHR - %s %s --enter\n", __func__, on ? "on" : "off");
+
+	if (on) {
+		/* WAR for nRST is high */
+
+
+		if (system_rev >= 4) {
+			gpio_direction_output(GPIO_WLAN_EN2, 1);
+			udelay(10);
+		}
+		gpio_direction_output(GPIO_WLAN_nRST, 0);
+		mdelay(30);
+		gpio_direction_output(GPIO_WLAN_nRST, 1);
+
+#ifdef WLAN_HOST_WAKE
+		wlan_host_wake_init();
+#endif /* WLAN_HOST_WAKE */
+
+	} else {
+#ifdef WLAN_HOST_WAKE
+		wlan_host_wake_exit();
+#endif /* WLAN_HOST_WAKE */
+
+		gpio_direction_output(GPIO_WLAN_nRST, 0);
+		if (system_rev >= 4)
+			gpio_direction_output(GPIO_WLAN_EN2, 0);
+	}
+
+	mdelay(100);
+
+	printk(KERN_ERR "ATHR - rev : %02d\n", system_rev);
+
+	if (system_rev >= 4) {
+		printk(KERN_ERR "ATHR - GPIO_WLAN_EN1(%d: %d), "\
+			"GPIO_WLAN_EN2(%d: %d), GPIO_WALN_nRST(%d: %d)\n"\
+			, GPIO_WLAN_EN, gpio_get_value(GPIO_WLAN_EN)
+			, GPIO_WLAN_EN2, gpio_get_value(GPIO_WLAN_EN2)
+			, GPIO_WLAN_nRST, gpio_get_value(GPIO_WLAN_nRST));
+	} else {
+		printk(KERN_ERR "ATHR - GPIO_WLAN_EN(%d: %d), "\
+			" GPIO_WALN_nRST(%d: %d)\n"\
+			, GPIO_WLAN_EN, gpio_get_value(GPIO_WLAN_EN)
+			, GPIO_WLAN_nRST, gpio_get_value(GPIO_WLAN_nRST));
+	}
+
+	if (detect) {
+		if (wlan_status_notify_cb)
+			wlan_status_notify_cb(wlan_devid, on);
+		else
+			printk(KERN_ERR "ATHR - WLAN: No notify available\n");
+	}
+}
+EXPORT_SYMBOL(wlan_setup_power);
+
+#endif
+
+#ifdef CONFIG_VIDEO_FIMC
+/*
+ * External camera reset
+ * Because the most of cameras take i2c bus signal, so that
+ * you have to reset at the boot time for other i2c slave devices.
+ * This function also called at fimc_init_camera()
+ * Do optimization for cameras on your platform.
+ */
+
+#define CAM_CHECK_ERR_RET(x, msg)	\
+	if (unlikely((x) < 0)) { \
+		printk(KERN_ERR "\nfail to %s: err = %d\n", msg, x); \
+		return x; \
+	}
+#define CAM_CHECK_ERR(x, msg)	\
+	if (unlikely((x) < 0)) { \
+		printk(KERN_ERR "\nfail to %s: err = %d\n", msg, x); \
+	}
+
+#define CAM_CHECK_ERR_GOTO(x, out, fmt, ...) \
+	if (unlikely((x) < 0)) { \
+		printk(KERN_ERR fmt, ##__VA_ARGS__); \
+		goto out; \
+	}
+
+#ifdef CONFIG_VIDEO_FIMC_MIPI
+int s3c_csis_power(int enable)
+{
+	struct regulator *regulator;
+	int ret = -ENODEV;
+
+	/* mipi_1.1v ,mipi_1.8v are always powered-on.
+	* If they are off, we then power them on.
+	*/
+	if (enable) {
+		/* VMIPI_1.1V */
+		regulator = regulator_get(NULL, "vmipi_1.1v");
+		if (IS_ERR(regulator))
+			goto error_out;
+		if (!regulator_is_enabled(regulator)) {
+			printk(KERN_WARNING "%s: vmipi_1.1v is off. so ON\n",
+				__func__);
+			ret = regulator_enable(regulator);
+			if (unlikely(ret < 0)) {
+				pr_err("%s: error, vmipi_1.1v\n", __func__);
+				return ret;
+			}
+		}
+		regulator_put(regulator);
+
+		/* VMIPI_1.8V */
+		regulator = regulator_get(NULL, "vmipi_1.8v");
+		if (IS_ERR(regulator))
+			goto error_out;
+		if (!regulator_is_enabled(regulator)) {
+			printk(KERN_WARNING "%s: vmipi_1.8v is off. so ON\n",
+				__func__);
+			ret = regulator_enable(regulator);
+			if (unlikely(ret < 0)) {
+				pr_err("%s: error, vmipi_1.8v\n", __func__);
+				return ret;
+			}
+		}
+		regulator_put(regulator);
+	}
+
+	return 0;
+
+error_out:
+	printk(KERN_ERR "%s: ERROR: failed to check mipi-power\n", __func__);
+	return ret;
+}
+
+#endif
+
+
+#ifdef CONFIG_VIDEO_S5K5CCGX_COMMON
+static int s5k5ccgx_get_i2c_busnum(void)
+{
+	return 0;
+}
+
+#ifdef CONFIG_VIDEO_S5K5CCGX_P8
+static int s5k5ccgx_power_on(void)
+{
+	struct regulator *regulator;
+	int ret = 0;
+
+	printk(KERN_DEBUG "%s in P8\n", __func__);
+
+#ifndef USE_CAM_GPIO_CFG
+#if !defined(CONFIG_MACH_P8LTE)
+	ret = gpio_request(GPIO_CAM_AVDD_EN, "GPJ1");
+	if (ret) {
+		printk(KERN_ERR "Error: fail to request gpio(CAM_AVDD)\n");
+		return ret;
+	}
+#endif
+	ret = gpio_request(GPIO_2M_nSTBY, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "Error: fail to request gpio(2M_nSTBY)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_2M_nRST, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "Error: fail to request gpio(2M_nRST)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_3M_nSTBY, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "Error: fail to request gpio(3M_nSTBY)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_3M_nRST, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "Error: fail to request gpio(3M_nRST)\n");
+		return ret;
+	}
+#endif
+
+	/* 2M_nSTBY low */
+	ret = gpio_direction_output(GPIO_2M_nSTBY, 0);
+	CAM_CHECK_ERR_RET(ret, "2M_nSTBY");
+
+	/* 2M_nRST low */
+	ret = gpio_direction_output(GPIO_2M_nRST, 0);
+	CAM_CHECK_ERR_RET(ret, "2M_nRST");
+
+	/* CAM_A2.8V */
+#if defined(CONFIG_MACH_P8LTE)
+	regulator = regulator_get(NULL, "cam_analog_2.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "CAM_A2.8V");
+#else
+	ret = gpio_direction_output(GPIO_CAM_AVDD_EN, 1);
+	CAM_CHECK_ERR_RET(ret, "CAM_AVDD");
+	udelay(1);
+#endif
+
+	/* 3MP_CORE_1.2V */
+	regulator = regulator_get(NULL, "3mp_core");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "3mp_core");
+	udelay(1);
+
+	/* VT_CORE_1.8V */
+	regulator = regulator_get(NULL, "vt_core_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "vt_core_1.8v");
+	udelay(1);
+
+	/* CAM_IO_1.8V */
+	regulator = regulator_get(NULL, "cam_io_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "cam_io_1.8v");
+	udelay(70);
+
+	/* CAM_MCLK */
+	ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_SFN(2));
+	CAM_CHECK_ERR_RET(ret, "cfg mclk");
+	s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_NONE);
+	udelay(10);
+
+	/* 3M_nSTBY */
+	ret = gpio_direction_output(GPIO_3M_nSTBY, 1);
+	CAM_CHECK_ERR_RET(ret, "3M_nSTBY");
+	udelay(16);
+
+	/* 3M_nRST */
+	ret = gpio_direction_output(GPIO_3M_nRST, 1);
+	CAM_CHECK_ERR_RET(ret, "3M_nRST");
+
+	/* 3MP_AF_2.8V */
+	regulator = regulator_get(NULL, "3m_af_2.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "3m_af_2.8v");
+	msleep(10);
+
+#ifndef USE_CAM_GPIO_CFG
+#if !defined(CONFIG_MACH_P8LTE)
+	gpio_free(GPIO_CAM_AVDD_EN);
+#endif
+	gpio_free(GPIO_2M_nSTBY);
+	gpio_free(GPIO_2M_nRST);
+	gpio_free(GPIO_3M_nSTBY);
+	gpio_free(GPIO_3M_nRST);
+#endif
+	return ret;
+}
+
+static int s5k5ccgx_power_down(void)
+{
+	struct regulator *regulator;
+	int ret = 0;
+
+	printk(KERN_DEBUG "%s in P8\n", __func__);
+
+#ifndef USE_CAM_GPIO_CFG
+#if !defined(CONFIG_MACH_P8LTE)
+	ret = gpio_request(GPIO_CAM_AVDD_EN, "GPJ1");
+	if (ret) {
+		printk(KERN_ERR "Error: fail to request gpio(CAM_AVDD)\n");
+		return ret;
+	}
+#endif
+	ret = gpio_request(GPIO_3M_nRST, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "Error: fail to request gpio(3M_nRST)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_3M_nSTBY, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "Error: fail to request gpio(3M_nSTBY)\n");
+		return ret;
+	}
+#endif
+	/* 3MP_AF_2.8V */
+	regulator = regulator_get(NULL, "3m_af_2.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "3m_af_2.8v");
+
+	/* 3M_nRST Low*/
+	ret = gpio_direction_output(GPIO_3M_nRST, 0);
+	CAM_CHECK_ERR(ret, "3M_nSTBY");
+	udelay(50);
+
+	/* CAM_MCLK */
+	ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_DOWN);
+	CAM_CHECK_ERR(ret, "cfg mclk");
+	udelay(5);
+
+	/* 3M_nSTBY */
+	ret = gpio_direction_output(GPIO_3M_nSTBY, 0);
+	CAM_CHECK_ERR(ret, "3M_nSTBY");
+	udelay(1);
+
+	/* CAM_IO_1.8V */
+	regulator = regulator_get(NULL, "cam_io_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "cam_io_1.8v");
+	udelay(1);
+
+	/* VT_CORE_1.8V */
+	regulator = regulator_get(NULL, "vt_core_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "vt_core_1.8v");
+	udelay(1);
+
+	/* 3MP_CORE_1.2V */
+	regulator = regulator_get(NULL, "3mp_core");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "3mp_core");
+	udelay(1);
+
+	/* CAM_A2.8V */
+#if defined(CONFIG_MACH_P8LTE)
+	regulator = regulator_get(NULL, "cam_analog_2.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "CAM_A2.8V");
+#else
+	ret = gpio_direction_output(GPIO_CAM_AVDD_EN, 0);
+	CAM_CHECK_ERR_RET(ret, "CAM_AVDD");
+#endif
+
+#ifndef USE_CAM_GPIO_CFG
+#if !defined(CONFIG_MACH_P8LTE)
+	gpio_free(GPIO_CAM_AVDD_EN);
+#endif
+	gpio_free(GPIO_3M_nSTBY);
+	gpio_free(GPIO_3M_nRST);
+#endif
+	return ret;
+}
+
+#else /* CONFIG_VIDEO_S5K5CCGX_P8 */
+
+/* Power up/down func for P4C, P2. */
+static int s5k5ccgx_power_on(void)
+{
+	struct regulator *regulator;
+	int ret = 0;
+
+	printk(KERN_DEBUG "%s in P4C,P2\n", __func__);
+
+#ifndef USE_CAM_GPIO_CFG
+	ret = gpio_request(GPIO_2M_nSTBY, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "Error: fail to request gpio(2M_nSTBY)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_2M_nRST, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "Error: fail to request gpio(2M_nRST)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_3M_nSTBY, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "Error: fail to request gpio(3M_nSTBY)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_3M_nRST, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "Error: fail to request gpio(3M_nRST)\n");
+		return ret;
+	}
+#endif
+
+	/* 2M_nSTBY low */
+	ret = gpio_direction_output(GPIO_2M_nSTBY, 0);
+	CAM_CHECK_ERR_RET(ret, "2M_nSTBY");
+
+	/* 2M_nRST low */
+	ret = gpio_direction_output(GPIO_2M_nRST, 0);
+	CAM_CHECK_ERR_RET(ret, "2M_nRST");
+
+	/* 3MP_CORE_1.2V */
+	regulator = regulator_get(NULL, "3mp_core");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "3mp_core");
+
+	/* CAM_IO_1.8V */
+	regulator = regulator_get(NULL, "cam_io_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "cam_io_1.8v");
+
+	/* CAM_A2.8V, LDO13 */
+	regulator = regulator_get(NULL, "cam_analog_2.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "cam_analog_2.8v");
+
+	/* VT_CORE_1.8V */
+	regulator = regulator_get(NULL, "vt_core_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "vt_core_1.8v");
+	udelay(20);
+
+	/* 2M_nSTBY High */
+	ret = gpio_direction_output(GPIO_2M_nSTBY, 1);
+	CAM_CHECK_ERR_RET(ret, "2M_nSTBY");
+	udelay(3);
+
+	/* CAM_MCLK */
+	ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_SFN(2));
+	CAM_CHECK_ERR_RET(ret, "cfg mclk");
+	s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_NONE);
+	msleep(5); /* >=5ms */
+
+	/* 2M_nSTBY Low */
+	ret = gpio_direction_output(GPIO_2M_nSTBY, 0);
+	CAM_CHECK_ERR_RET(ret, "2M_nSTBY");
+	msleep(10); /* >=10ms */
+
+	/* 2M_nRST High */
+	ret = gpio_direction_output(GPIO_2M_nRST, 1);
+	CAM_CHECK_ERR_RET(ret, "2M_nRST");
+	msleep(5);
+
+	/* 2M_nSTBY High */
+	ret = gpio_direction_output(GPIO_2M_nSTBY, 1);
+	CAM_CHECK_ERR_RET(ret, "2M_nSTBY");
+	udelay(2);
+
+	/* 3M_nSTBY */
+	ret = gpio_direction_output(GPIO_3M_nSTBY, 1);
+	CAM_CHECK_ERR_RET(ret, "3M_nSTBY");
+	udelay(16);
+
+	/* 3M_nRST */
+	ret = gpio_direction_output(GPIO_3M_nRST, 1);
+	CAM_CHECK_ERR_RET(ret, "3M_nRST");
+	/* udelay(10); */
+
+	/* 3MP_AF_2.8V */
+	regulator = regulator_get(NULL, "3m_af_2.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "3m_af_2.8v");
+	msleep(10);
+
+#ifndef USE_CAM_GPIO_CFG
+	gpio_free(GPIO_2M_nSTBY);
+	gpio_free(GPIO_2M_nRST);
+	gpio_free(GPIO_3M_nSTBY);
+	gpio_free(GPIO_3M_nRST);
+#endif
+
+	return ret;
+}
+
+static int s5k5ccgx_power_down(void)
+{
+	struct regulator *regulator;
+	int ret = 0;
+
+	printk(KERN_DEBUG "%s in P4C,P2\n", __func__);
+
+#ifndef USE_CAM_GPIO_CFG
+	ret = gpio_request(GPIO_2M_nSTBY, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "Error: fail to request gpio(2M_nSTBY)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_2M_nRST, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "Error: fail to request gpio(2M_nRST)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_3M_nRST, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "Error: fail to request gpio(3M_nRST)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_3M_nSTBY, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "Error: fail to request gpio(3M_nSTBY)\n");
+		return ret;
+	}
+#endif
+	/* 3MP_AF_2.8V */
+	regulator = regulator_get(NULL, "3m_af_2.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "3m_af_2.8v");
+
+	/* 3M_nRST Low*/
+	ret = gpio_direction_output(GPIO_3M_nRST, 0);
+	CAM_CHECK_ERR(ret, "3M_nSTBY");
+	udelay(50);
+
+	/* CAM_MCLK */
+	ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_DOWN);
+	CAM_CHECK_ERR(ret, "cfg mclk");
+	udelay(5);
+
+	/* 3M_nSTBY */
+	ret = gpio_direction_output(GPIO_3M_nSTBY, 0);
+	CAM_CHECK_ERR(ret, "3M_nSTBY");
+	udelay(1);
+
+	/* 2M_nRST Low */
+	ret = gpio_direction_output(GPIO_2M_nRST, 0);
+	CAM_CHECK_ERR_RET(ret, "2M_nRST");
+
+	/* 2M_nSTBY Low */
+	ret = gpio_direction_output(GPIO_2M_nSTBY, 0);
+	CAM_CHECK_ERR_RET(ret, "2M_nSTBY");
+
+	/* VT_CORE_1.8V */
+	regulator = regulator_get(NULL, "vt_core_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "vt_core_1.8v");
+
+	/* CAM_A2.8V */
+	regulator = regulator_get(NULL, "cam_analog_2.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "cam_analog_2.8v");
+	/* udelay(50); */
+
+	/* CAM_IO_1.8V */
+	regulator = regulator_get(NULL, "cam_io_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "cam_io_1.8v");
+	/*udelay(50); */
+
+	/* 3MP_CORE_1.2V */
+	regulator = regulator_get(NULL, "3mp_core");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "3mp_core");
+
+#ifndef USE_CAM_GPIO_CFG
+	gpio_free(GPIO_2M_nSTBY);
+	gpio_free(GPIO_2M_nRST);
+	gpio_free(GPIO_3M_nSTBY);
+	gpio_free(GPIO_3M_nRST);
+#endif
+	return ret;
+}
+#endif /* CONFIG_VIDEO_S5K5CCGX_P8 */
+
+static int s5k5ccgx_power(int enable)
+{
+	int ret = 0;
+
+	printk(KERN_DEBUG "%s %s\n", __func__, enable ? "on" : "down");
+	if (enable) {
+#ifdef USE_CAM_GPIO_CFG
+		if (cfg_gpio_err) {
+			printk(KERN_ERR "%s: ERROR: gpio configuration",
+				__func__);
+			return cfg_gpio_err;
+		}
+#endif
+		ret = s5k5ccgx_power_on();
+	} else
+		ret = s5k5ccgx_power_down();
+
+	s3c_csis_power(enable);
+
+	return ret;
+}
+
+static void s5k5ccgx_flashtimer_handler(unsigned long data)
+{
+	int ret = -ENODEV;
+	atomic_t *flash_status = (atomic_t *)data;
+
+	pr_info("********** flashtimer_handler **********\n");
+
+	ret = gpio_direction_output(GPIO_CAM_FLASH_EN, 0);
+	atomic_set(flash_status, S5K5CCGX_FLASH_OFF);
+	if (unlikely(ret))
+		pr_err("flash_timer: ERROR, failed to oneshot flash off\n");
+}
+
+static atomic_t flash_status = ATOMIC_INIT(S5K5CCGX_FLASH_OFF);
+static int s5k5ccgx_flash_en(u32 mode, u32 onoff)
+{
+	static int flash_mode = S5K5CCGX_FLASH_MODE_NORMAL;
+	static DEFINE_MUTEX(flash_lock);
+	static DEFINE_TIMER(flash_timer, s5k5ccgx_flashtimer_handler,
+			0, (unsigned long)&flash_status);
+	int ret = 0;
+
+	printk(KERN_DEBUG "flash_en: mode=%d, on=%d\n", mode, onoff);
+
+	if (unlikely((u32)mode >= S5K5CCGX_FLASH_MODE_MAX)) {
+		pr_err("flash_en: ERROR, invalid flash mode(%d)\n", mode);
+		return -EINVAL;
+	}
+
+	/* We could not use spin lock because of gpio kernel API.*/
+	mutex_lock(&flash_lock);
+	if (atomic_read(&flash_status) == onoff) {
+		mutex_unlock(&flash_lock);
+		pr_warn("flash_en: WARNING, already flash %s\n",
+			onoff ? "On" : "Off");
+		return 0;
+	}
+
+	switch (onoff) {
+	case S5K5CCGX_FLASH_ON:
+		if (mode == S5K5CCGX_FLASH_MODE_MOVIE)
+			ret = gpio_direction_output(GPIO_CAM_MOVIE_EN, 1);
+		else {
+			ret = gpio_direction_output(GPIO_CAM_FLASH_EN, 1);
+			flash_timer.expires = get_jiffies_64() + HZ / 2;
+			add_timer(&flash_timer);
+		}
+		CAM_CHECK_ERR_GOTO(ret, out,
+			"flash_en: ERROR, fail to turn flash on (mode:%d)\n",
+			mode);
+		flash_mode = mode;
+		break;
+
+	case S5K5CCGX_FLASH_OFF:
+		if (unlikely(flash_mode != mode)) {
+			pr_err("flash_en: ERROR, unmatched flash mode(%d, %d)\n",
+				flash_mode, mode);
+			WARN_ON(1);
+			goto out;
+		}
+
+		if (mode == S5K5CCGX_FLASH_MODE_MOVIE)
+			ret = gpio_direction_output(GPIO_CAM_MOVIE_EN, 0);
+		else {
+			if (del_timer_sync(&flash_timer)) {
+				pr_info("flash_en: terminate flash timer...\n");
+				ret = gpio_direction_output(GPIO_CAM_FLASH_EN,
+							0);
+			}
+		}
+		CAM_CHECK_ERR_GOTO(ret, out,
+			"flash_en: ERROR, flash off (mode:%d)\n", mode);
+		break;
+
+	default:
+		pr_err("flash_en: ERROR, invalid flash cmd(%d)\n", onoff);
+		goto out;
+		break;
+	}
+
+	atomic_set(&flash_status, onoff);
+
+out:
+	mutex_unlock(&flash_lock);
+	return 0;
+}
+
+static int s5k5ccgx_is_flash_on(void)
+{
+	return atomic_read(&flash_status);
+}
+
+static int px_cam_cfg_init(void)
+{
+	int ret = -ENODEV;
+
+	/* pr_info("%s\n", __func__); */
+
+	ret = gpio_request(GPIO_CAM_MOVIE_EN, "GPL0");
+	if (unlikely(ret)) {
+		pr_err("cam_cfg_init: fail to get gpio(MOVIE_EN), "
+			"err=%d\n", ret);
+		goto out;
+	}
+
+	ret = gpio_request(GPIO_CAM_FLASH_EN, "GPL0");
+	if (unlikely(ret)) {
+		pr_err("cam_cfg_init: fail to get gpio(FLASH_EN), "
+			"err=%d\n", ret);
+		goto out_free;
+	}
+
+	return 0;
+
+out_free:
+	gpio_free(GPIO_CAM_MOVIE_EN);
+out:
+	return ret;
+}
+
+static struct s5k5ccgx_platform_data s5k5ccgx_plat = {
+	.default_width = 1024,
+	.default_height = 768,
+	.pixelformat = V4L2_PIX_FMT_UYVY,
+	.freq = 24000000,
+	.is_mipi = 1,
+	.streamoff_delay = S5K5CCGX_STREAMOFF_DELAY,
+	.flash_en = s5k5ccgx_flash_en,
+	.is_flash_on = s5k5ccgx_is_flash_on,
+	.dbg_level = CAMDBG_LEVEL_DEFAULT,
+};
+#define REAR_CAM_PLAT		(s5k5ccgx_plat)
+
+static struct i2c_board_info  s5k5ccgx_i2c_info = {
+	I2C_BOARD_INFO("S5K5CCGX", 0x78>>1),
+	.platform_data = &s5k5ccgx_plat,
+};
+
+static struct s3c_platform_camera s5k5ccgx = {
+	.id		= CAMERA_CSI_C,
+	.clk_name	= "sclk_cam0",
+	.get_i2c_busnum	= s5k5ccgx_get_i2c_busnum,
+	.cam_power	= s5k5ccgx_power, /*smdkv310_mipi_cam0_reset,*/
+	.type		= CAM_TYPE_MIPI,
+	.fmt		= ITU_601_YCBCR422_8BIT, /*MIPI_CSI_YCBCR422_8BIT*/
+	.order422	= CAM_ORDER422_8BIT_CBYCRY,
+	.info		= &s5k5ccgx_i2c_info,
+	.pixelformat	= V4L2_PIX_FMT_UYVY,
+	.srclk_name	= "xusbxti", /* "mout_mpll" */
+	.clk_rate	= 24000000, /* 48000000 */
+	.line_length	= 640,
+	.width		= 640,
+	.height		= 480,
+	.window		= {
+		.left	= 0,
+		.top	= 0,
+		.width	= 640,
+		.height	= 480,
+	},
+
+	.mipi_lanes	= 1,
+	.mipi_settle	= 6,
+	.mipi_align	= 32,
+
+	/* Polarity */
+	.inv_pclk	= 0,
+	.inv_vsync	= 1,
+	.inv_href	= 0,
+	.inv_hsync	= 0,
+	.reset_camera	= 0,
+	.initialized	= 0,
+};
+#endif /* #ifdef CONFIG_VIDEO_S5K5CCGX_COMMON */
+
+
+#ifdef CONFIG_VIDEO_S5K5BAFX
+static int s5k5bafx_get_i2c_busnum(void)
+{
+	return 0;
+}
+
+static int s5k5bafx_power_on(void)
+{
+	struct regulator *regulator;
+	int ret = 0;
+
+	printk(KERN_DEBUG "%s: in\n", __func__);
+#if !defined(CONFIG_MACH_P8LTE)
+	ret = gpio_request(GPIO_CAM_AVDD_EN, "GPJ1");
+	if (ret) {
+		printk(KERN_ERR "Error: fail to request gpio(CAM_AVDD)\n");
+		return ret;
+	}
+#endif
+	ret = gpio_request(GPIO_2M_nSTBY, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "Error: fail to request gpio(2M_nSTBY)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_2M_nRST, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "Error: fail to request gpio(2M_nRST)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_3M_nSTBY, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "Error: fail to request gpio(3M_nSTBY)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_3M_nRST, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "Error: fail to request gpio(3M_nRST)\n");
+		return ret;
+	}
+
+	/* 3M_nSTBY low */
+	ret = gpio_direction_output(GPIO_3M_nSTBY, 0);
+	CAM_CHECK_ERR_RET(ret, "3M_nSTBY");
+
+	/* 3M_nRST low */
+	ret = gpio_direction_output(GPIO_3M_nRST, 0);
+	CAM_CHECK_ERR_RET(ret, "3M_nRST");
+
+	/* CAM_A2.8V */
+#if defined(CONFIG_MACH_P8LTE)
+	regulator = regulator_get(NULL, "cam_analog_2.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "CAM_A2.8V");
+#else
+
+	ret = gpio_direction_output(GPIO_CAM_AVDD_EN, 1);
+	CAM_CHECK_ERR_RET(ret, "CAM_AVDD");
+	/* udelay(1); */
+#endif
+
+	/* 3MP_CORE_1.2V */
+	regulator = regulator_get(NULL, "3mp_core");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "3mp_core");
+	/* udelay(1); */
+
+	/* VT_CORE_1.8V */
+	regulator = regulator_get(NULL, "vt_core_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "vt_core_1.8v");
+	/* udelay(1); */
+
+	/* CAM_IO_1.8V */
+	regulator = regulator_get(NULL, "cam_io_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "cam_io_1.8v");
+	udelay(70);
+
+	/* 2M_nSTBY High */
+	ret = gpio_direction_output(GPIO_2M_nSTBY, 1);
+	CAM_CHECK_ERR_RET(ret, "2M_nSTBY");
+	udelay(10);
+
+	/* Mclk */
+	ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_SFN(2));
+	s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_NONE);
+	CAM_CHECK_ERR_RET(ret, "cfg mclk");
+	udelay(50);
+
+	/* 2M_nRST High */
+	ret = gpio_direction_output(GPIO_2M_nRST, 1);
+	CAM_CHECK_ERR_RET(ret, "2M_nRST");
+	udelay(50);
+
+#if !defined(CONFIG_MACH_P8LTE)
+	gpio_free(GPIO_CAM_AVDD_EN);
+#endif
+	gpio_free(GPIO_2M_nSTBY);
+	gpio_free(GPIO_2M_nRST);
+	gpio_free(GPIO_3M_nSTBY);
+	gpio_free(GPIO_3M_nRST);
+
+	return 0;
+}
+
+static int s5k5bafx_power_off(void)
+{
+	struct regulator *regulator;
+	int ret = 0;
+
+	printk(KERN_DEBUG "%s: in\n", __func__);
+
+#if !defined(CONFIG_MACH_P8LTE)
+	ret = gpio_request(GPIO_CAM_AVDD_EN, "GPJ1");
+	if (ret) {
+		printk(KERN_ERR "Error: fail to request gpio(CAM_AVDD)\n");
+		return ret;
+	}
+#endif
+	ret = gpio_request(GPIO_2M_nRST, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "Error: fail to request gpio(3M_nRST)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_2M_nSTBY, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "Error: fail to request gpio(3M_nSTBY)\n");
+		return ret;
+	}
+
+	/* 2M_nRST Low*/
+	ret = gpio_direction_output(GPIO_2M_nRST, 0);
+	CAM_CHECK_ERR(ret, "3M_nSTBY");
+	udelay(55);
+
+	/* CAM_MCLK */
+	ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_DOWN);
+	CAM_CHECK_ERR(ret, "cfg mclk");
+	udelay(10);
+
+	/* 2M_nSTBY */
+	ret = gpio_direction_output(GPIO_2M_nSTBY, 0);
+	CAM_CHECK_ERR(ret, "3M_nSTBY");
+	udelay(1);
+
+	/* CAM_IO_1.8V */
+	regulator = regulator_get(NULL, "cam_io_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "cam_io_1.8v");
+	/* udelay(1); */
+
+	/* VT_CORE_1.8V */
+	regulator = regulator_get(NULL, "vt_core_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "vt_core_1.8v");
+	/* udelay(1); */
+
+	/* 3MP_CORE_1.2V */
+	regulator = regulator_get(NULL, "3mp_core");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "3mp_core");
+
+	/* CAM_A2.8V */
+#if defined(CONFIG_MACH_P8LTE)
+	regulator = regulator_get(NULL, "cam_analog_2.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "CAM_A2.8V");
+#else
+	ret = gpio_direction_output(GPIO_CAM_AVDD_EN, 0);
+	CAM_CHECK_ERR_RET(ret, "CAM_AVDD");
+#endif
+
+#if !defined(CONFIG_MACH_P8LTE)
+	gpio_free(GPIO_CAM_AVDD_EN);
+#endif
+	gpio_free(GPIO_2M_nRST);
+	gpio_free(GPIO_2M_nSTBY);
+
+	return 0;
+}
+
+static int s5k5bafx_power(int onoff)
+{
+	int ret = 0;
+
+	printk(KERN_INFO "%s(): %s\n", __func__, onoff ? "on" : "down");
+	if (onoff) {
+		ret = s5k5bafx_power_on();
+		if (unlikely(ret))
+			goto error_out;
+	} else {
+		ret = s5k5bafx_power_off();
+		/* s3c_i2c0_force_stop();*//* DSLIM. Should be implemented */
+	}
+
+	ret = s3c_csis_power(onoff);
+
+error_out:
+	return ret;
+}
+
+static struct s5k5bafx_platform_data s5k5bafx_plat = {
+	.default_width = 800,
+	.default_height = 600,
+	.pixelformat = V4L2_PIX_FMT_UYVY,
+	.freq = 24000000,
+	.is_mipi = 1,
+	.streamoff_delay = S5K5BAFX_STREAMOFF_DELAY,
+	.dbg_level = CAMDBG_LEVEL_DEFAULT,
+};
+#define FRONT_CAM_PLAT		(s5k5bafx_plat)
+
+static struct i2c_board_info  s5k5bafx_i2c_info = {
+	I2C_BOARD_INFO("S5K5BAFX", 0x5A >> 1),
+	.platform_data = &s5k5bafx_plat,
+};
+
+static struct s3c_platform_camera s5k5bafx = {
+	.id		= CAMERA_CSI_D,
+	.type		= CAM_TYPE_MIPI,
+	.fmt		= ITU_601_YCBCR422_8BIT,
+	.order422	= CAM_ORDER422_8BIT_CBYCRY,
+	.mipi_lanes	= 1,
+	.mipi_settle	= 6,
+	.mipi_align	= 32,
+
+	.get_i2c_busnum	= s5k5bafx_get_i2c_busnum,
+	.info		= &s5k5bafx_i2c_info,
+	.pixelformat	= V4L2_PIX_FMT_UYVY,
+	.srclk_name	= "xusbxti",
+	.clk_name	= "sclk_cam0",
+	.clk_rate	= 24000000,
+	.line_length	= 800,
+	.width		= 800,
+	.height		= 600,
+	.window		= {
+		.left	= 0,
+		.top	= 0,
+		.width	= 800,
+		.height	= 600,
+	},
+
+	/* Polarity */
+	.inv_pclk	= 0,
+	.inv_vsync	= 1,
+	.inv_href	= 0,
+	.inv_hsync	= 0,
+	.reset_camera	= 0,
+	.initialized	= 0,
+	.cam_power	= s5k5bafx_power,
+};
+#endif
+
+
+#ifdef CONFIG_VIDEO_SR200PC20
+static int sr200pc20_get_i2c_busnum(void)
+{
+#ifdef CONFIG_MACH_P4
+	if (system_rev >= 2)
+		return 0;
+	else
+#endif
+		return 13;
+}
+
+static int sr200pc20_power_on(void)
+{
+	struct regulator *regulator;
+	int ret = 0;
+
+#ifndef USE_CAM_GPIO_CFG
+	ret = gpio_request(GPIO_2M_nSTBY, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "Error: fail to request gpio(2M_nSTBY)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_2M_nRST, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "Error: fail to request gpio(2M_nRST)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_3M_nSTBY, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "Error: fail to request gpio(3M_nSTBY)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_3M_nRST, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "Error: fail to request gpio(3M_nRST)\n");
+		return ret;
+	}
+#endif
+
+	/* 3M_nSTBY low */
+	ret = gpio_direction_output(GPIO_3M_nSTBY, 0);
+	CAM_CHECK_ERR_RET(ret, "3M_nSTBY");
+
+	/* 3M_nRST low */
+	ret = gpio_direction_output(GPIO_3M_nRST, 0);
+	CAM_CHECK_ERR_RET(ret, "3M_nRST");
+
+	/* 2M_nSTBY low */
+	ret = gpio_direction_output(GPIO_2M_nSTBY, 0);
+	CAM_CHECK_ERR_RET(ret, "2M_nSTBY");
+
+	/* 2M_nRST low */
+	ret = gpio_direction_output(GPIO_2M_nRST, 0);
+	CAM_CHECK_ERR_RET(ret, "2M_nRST");
+
+	/* 3MP_CORE_1.2V */
+	regulator = regulator_get(NULL, "3mp_core");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "3mp_core");
+	/* udelay(5); */
+
+	/* CAM_IO_1.8V */
+	regulator = regulator_get(NULL, "cam_io_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "cam_io_1.8v");
+	/*udelay(5); */
+
+	/* CAM_A2.8V */
+	regulator = regulator_get(NULL, "cam_analog_2.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "cam_analog_2.8v");
+	/* udelay(5); */
+
+	/* VT_CORE_1.8V */
+	regulator = regulator_get(NULL, "vt_core_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "vt_core_1.8v");
+	udelay(20);
+
+	/* ENB High */
+	ret = gpio_direction_output(GPIO_2M_nSTBY, 1);
+	CAM_CHECK_ERR_RET(ret, "2M_nSTBY");
+	udelay(3); /* 30 -> 3 */
+
+	/* CAM_MCLK */
+	ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_SFN(2));
+	CAM_CHECK_ERR_RET(ret, "cfg mclk");
+	s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_NONE);
+	msleep(5); /* >= 5ms */
+
+	/* ENB Low */
+	ret = gpio_direction_output(GPIO_2M_nSTBY, 0);
+	CAM_CHECK_ERR_RET(ret, "2M_nSTBY");
+	msleep(10); /* >= 10ms */
+
+	/* 2M_nRST High*/
+	ret = gpio_direction_output(GPIO_2M_nRST, 1);
+	CAM_CHECK_ERR_RET(ret, "2M_nRST");
+	/*msleep(7);*/ /* >= 7ms */
+
+#if 0
+	/* ENB High */
+	ret = gpio_direction_output(GPIO_2M_nSTBY, 1);
+	CAM_CHECK_ERR_RET(ret, "2M_nSTBY");
+	msleep(12); /* >= 10ms */
+
+	/* ENB Low */
+	ret = gpio_direction_output(GPIO_2M_nSTBY, 0);
+	CAM_CHECK_ERR_RET(ret, "2M_nSTBY");
+	msleep(12); /* >= 10ms */
+
+	/* 2M_nRST Low*/
+	ret = gpio_direction_output(GPIO_2M_nRST, 0);
+	CAM_CHECK_ERR_RET(ret, "2M_nRST");
+	udelay(10); /* >= 16 cycle */
+
+	/* 2M_nRST High */
+	ret = gpio_direction_output(GPIO_2M_nRST, 1);
+	CAM_CHECK_ERR_RET(ret, "2M_nRST");
+#endif
+	udelay(10); /* >= 16 cycle */
+
+#ifndef USE_CAM_GPIO_CFG
+	gpio_free(GPIO_2M_nSTBY);
+	gpio_free(GPIO_2M_nRST);
+	gpio_free(GPIO_3M_nSTBY);
+	gpio_free(GPIO_3M_nRST);
+#endif
+	return 0;
+}
+
+static int sr200pc20_power_off(void)
+{
+	struct regulator *regulator;
+	int ret = 0;
+
+	printk(KERN_DEBUG "%s in\n", __func__);
+
+#ifndef USE_CAM_GPIO_CFG
+	ret = gpio_request(GPIO_2M_nSTBY, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "Error: fail to request gpio(2M_nSTBY)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_2M_nRST, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "Error: fail to request gpio(2M_nRST)\n");
+		return ret;
+	}
+#endif
+
+#if 0
+	/* 2M_nRST */
+	ret = gpio_direction_output(GPIO_2M_nRST, 0);
+	CAM_CHECK_ERR_RET(ret, "2M_nRST");
+	udelay(100);
+
+	/* 2M_nSTBY */
+	ret = gpio_direction_output(GPIO_2M_nSTBY, 0);
+	CAM_CHECK_ERR_RET(ret, "2M_nSTBY");
+	udelay(100);
+#endif
+	/* Sleep command */
+	mdelay(1);
+
+	/* 2M_nRST Low*/
+	ret = gpio_direction_output(GPIO_2M_nRST, 0);
+	CAM_CHECK_ERR_RET(ret, "2M_nRST");
+	udelay(3);
+
+	/* CAM_MCLK */
+	ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_DOWN);
+	CAM_CHECK_ERR(ret, "cfg mclk");
+	udelay(10);
+
+	/* ENB High*/
+	ret = gpio_direction_output(GPIO_2M_nSTBY, 1);
+	CAM_CHECK_ERR_RET(ret, "2M_nSTBY");
+	mdelay(5);
+
+	/* ENB Low */
+	ret = gpio_direction_output(GPIO_2M_nSTBY, 0);
+	CAM_CHECK_ERR_RET(ret, "2M_spnSTBY");
+	/* udelay(1); */
+
+	/* VT_CORE_1.8V */
+	regulator = regulator_get(NULL, "vt_core_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "vt_core_1.8v");
+	/* udelay(10); */
+
+	/* CAM_A2.8V */
+	regulator = regulator_get(NULL, "cam_analog_2.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "cam_analog_2.8v");
+	/* udelay(10); */
+
+	/* CAM_IO_1.8V */
+	regulator = regulator_get(NULL, "cam_io_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "cam_io_1.8v");
+	/*udelay(10); */
+
+	/* 3MP_CORE_1.2V */
+	regulator = regulator_get(NULL, "3mp_core");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+
+#ifndef USE_CAM_GPIO_CFG
+	gpio_free(GPIO_2M_nSTBY);
+	gpio_free(GPIO_2M_nRST);
+#endif
+	return 0;
+}
+
+static int sr200pc20_power(int onoff)
+{
+	int ret = 0;
+
+	printk(KERN_DEBUG "%s(): %s\n", __func__, onoff ? "on" : "down");
+
+	if (onoff) {
+#ifdef USE_CAM_GPIO_CFG
+		if (cfg_gpio_err) {
+			printk(KERN_ERR "%s: ERROR: gpio configuration",
+				__func__);
+			return cfg_gpio_err;
+		}
+#endif
+		ret = sr200pc20_power_on();
+	} else {
+		ret = sr200pc20_power_off();
+		/* s3c_i2c0_force_stop();*/ /* DSLIM. Should be implemented */
+	}
+
+	return ret;
+}
+
+static struct sr200pc20_platform_data sr200pc20_plat = {
+	.default_width = 800,
+	.default_height = 600,
+	.pixelformat = V4L2_PIX_FMT_UYVY,
+	.is_mipi = 0,
+	.streamoff_delay = 0,
+	.dbg_level = CAMDBG_LEVEL_DEFAULT,
+};
+#define FRONT_CAM_PLAT		(sr200pc20_plat)
+
+static struct i2c_board_info  sr200pc20_i2c_info = {
+	I2C_BOARD_INFO("SR200PC20", 0x40 >> 1),
+	.platform_data = &sr200pc20_plat,
+};
+
+static struct s3c_platform_camera sr200pc20 = {
+	.id		= CAMERA_PAR_A,
+	.type		= CAM_TYPE_ITU,
+	.fmt		= ITU_601_YCBCR422_8BIT,
+	.order422	= CAM_ORDER422_8BIT_YCBYCR,
+	.get_i2c_busnum	= sr200pc20_get_i2c_busnum,
+	.info		= &sr200pc20_i2c_info,
+	.pixelformat	= V4L2_PIX_FMT_UYVY,
+	.srclk_name	= "xusbxti",
+	.clk_name	= "sclk_cam0",
+	.clk_rate	= 24000000,
+	.line_length	= 800,
+	.width		= 800,
+	.height		= 600,
+	.window		= {
+		.left	= 0,
+		.top	= 0,
+		.width	= 800,
+		.height	= 600,
+	},
+
+	/* Polarity */
+#if 0 /*def CONFIG_VIDEO_SR200PC20_P4W */
+	.inv_pclk	= 0,
+	.inv_vsync	= 1,
+#else
+	.inv_pclk	= 1,
+	.inv_vsync	= 0,
+#endif
+	.inv_href	= 0,
+	.inv_hsync	= 0,
+	.reset_camera	= 0,
+	.initialized	= 0,
+	.cam_power	= sr200pc20_power,
+};
+#endif /* CONFIG_VIDEO_SR200PC20 */
+
+
+
+#ifdef WRITEBACK_ENABLED
+static int get_i2c_busnum_writeback(void)
+{
+	return 0;
+}
+
+static struct i2c_board_info writeback_i2c_info = {
+	I2C_BOARD_INFO("WriteBack", 0x0),
+};
+
+static struct s3c_platform_camera writeback = {
+	.id = CAMERA_WB,
+	.fmt = ITU_601_YCBCR422_8BIT,
+	.order422 = CAM_ORDER422_8BIT_CBYCRY,
+	.get_i2c_busnum = get_i2c_busnum_writeback,
+	.info = &writeback_i2c_info,
+	.pixelformat = V4L2_PIX_FMT_YUV444,
+	.line_length = 800,
+	.width = 480,
+	.height = 800,
+	.window = {
+		.left = 0,
+		.top = 0,
+		.width = 480,
+		.height = 800,
+	},
+
+	.initialized = 0,
+};
+#endif
+
+/* Interface setting */
+static struct s3c_platform_fimc fimc_plat = {
+#ifdef CONFIG_ITU_A
+	.default_cam = CAMERA_PAR_A,
+#endif
+#ifdef CONFIG_ITU_B
+	.default_cam = CAMERA_PAR_B,
+#endif
+#ifdef CONFIG_CSI_C
+	.default_cam = CAMERA_CSI_C,
+#endif
+#ifdef CONFIG_CSI_D
+	.default_cam = CAMERA_CSI_D,
+#endif
+	.camera = {
+#ifdef CONFIG_VIDEO_S5K5CCGX_COMMON
+		&s5k5ccgx,
+#endif
+#ifdef CONFIG_VIDEO_S5K5BAFX
+		&s5k5bafx,
+#endif
+#ifdef CONFIG_VIDEO_SR200PC20
+		&sr200pc20,
+#endif
+#ifdef WRITEBACK_ENABLED
+		&writeback,
+#endif
+	},
+	.hw_ver = 0x51,
+};
+
+#if defined(CONFIG_VIDEO_S5K5CCGX_COMMON) || defined(CONFIG_VIDEO_S5K5BAFX) \
+	|| defined(CONFIG_VIDEO_SR200PC20)
+ssize_t cam_loglevel_show(struct device *dev, struct device_attribute *attr,
+			char *buf)
+{
+	char temp_buf[60] = {0,};
+
+	sprintf(buf, "Log Level(Rear): ");
+	if (REAR_CAM_PLAT.dbg_level & CAMDBG_LEVEL_TRACE) {
+		sprintf(temp_buf, "trace ");
+		strcat(buf, temp_buf);
+	}
+
+	if (REAR_CAM_PLAT.dbg_level & CAMDBG_LEVEL_DEBUG) {
+		sprintf(temp_buf, "debug ");
+		strcat(buf, temp_buf);
+	}
+
+	if (REAR_CAM_PLAT.dbg_level & CAMDBG_LEVEL_INFO) {
+		sprintf(temp_buf, "info ");
+		strcat(buf, temp_buf);
+	}
+
+	sprintf(temp_buf, "\nLog Level(Front): ");
+	strcat(buf, temp_buf);
+	if (FRONT_CAM_PLAT.dbg_level & CAMDBG_LEVEL_TRACE) {
+		sprintf(temp_buf, "trace ");
+		strcat(buf, temp_buf);
+	}
+
+	if (FRONT_CAM_PLAT.dbg_level & CAMDBG_LEVEL_DEBUG) {
+		sprintf(temp_buf, "debug ");
+		strcat(buf, temp_buf);
+	}
+
+	if (FRONT_CAM_PLAT.dbg_level & CAMDBG_LEVEL_INFO) {
+		sprintf(temp_buf, "info ");
+		strcat(buf, temp_buf);
+	}
+
+	sprintf(temp_buf, "\n - Warn and Error level is always on\n\n");
+	strcat(buf, temp_buf);
+
+	return strlen(buf);
+}
+
+ssize_t cam_loglevel_store(struct device *dev, struct device_attribute *attr,
+			 const char *buf, size_t count)
+{
+	printk(KERN_DEBUG "CAM buf=%s, count=%d\n", buf, count);
+
+	if (strstr(buf, "trace")) {
+		REAR_CAM_PLAT.dbg_level |= CAMDBG_LEVEL_TRACE;
+		FRONT_CAM_PLAT.dbg_level |= CAMDBG_LEVEL_TRACE;
+	}
+
+	if (strstr(buf, "debug")) {
+		REAR_CAM_PLAT.dbg_level |= CAMDBG_LEVEL_DEBUG;
+		FRONT_CAM_PLAT.dbg_level |= CAMDBG_LEVEL_DEBUG;
+	}
+
+	if (strstr(buf, "info")) {
+		REAR_CAM_PLAT.dbg_level |= CAMDBG_LEVEL_INFO;
+		FRONT_CAM_PLAT.dbg_level |= CAMDBG_LEVEL_INFO;
+	}
+
+	return count;
+}
+static DEVICE_ATTR(loglevel, 0664, cam_loglevel_show, cam_loglevel_store);
+#endif
+
+ssize_t rear_camera_type_show(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	/* Change camera type properly */
+	char cam_type[] = "SLSI_S5K5CCGX";
+
+	pr_info("%s\n", __func__);
+	return sprintf(buf, "%s\n", cam_type);
+}
+
+ssize_t front_camera_type_show(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	/* Change camera type properly */
+#ifdef CONFIG_MACH_P8
+	char cam_type[] = "SLSI_S5K5BAFX";
+#else
+	char cam_type[] = "SILICONFILE_SR200PC20";
+#endif
+
+	pr_info("%s\n", __func__);
+	return sprintf(buf, "%s\n", cam_type);
+}
+static DEVICE_ATTR(rear_camtype, 0664, rear_camera_type_show, NULL);
+static DEVICE_ATTR(front_camtype, 0664, front_camera_type_show, NULL);
+
+#ifdef CONFIG_VIDEO_S5K5CCGX_COMMON
+ssize_t flash_show(struct device *dev, struct device_attribute *attr,
+			char *buf)
+{
+	return sprintf(buf, "%s\n", s5k5ccgx_is_flash_on() ? "on" : "off");
+}
+
+ssize_t flash_store(struct device *dev, struct device_attribute *attr,
+			 const char *buf, size_t count)
+{
+	switch (*buf) {
+	case '0':
+		s5k5ccgx_flash_en(S5K5CCGX_FLASH_MODE_MOVIE,
+				S5K5CCGX_FLASH_OFF);
+		break;
+	case '1':
+		s5k5ccgx_flash_en(S5K5CCGX_FLASH_MODE_MOVIE,
+				S5K5CCGX_FLASH_ON);
+		break;
+	default:
+		pr_err("flash: invalid data=%c(0x%X)\n", *buf, *buf);
+		break;
+	}
+
+	return count;
+}
+static DEVICE_ATTR(rear_flash, 0664, flash_show, flash_store);
+#endif
+
+
+static inline int cam_cfg_init(void)
+{
+#ifdef CONFIG_VIDEO_S5K5CCGX_COMMON
+	return px_cam_cfg_init();
+#else
+	return 0;
+#endif
+}
+
+static int cam_create_file(struct class *cls)
+{
+	struct device *dev_rear = NULL;
+	struct device *dev_front = NULL;
+	int ret = -ENODEV;
+
+#if defined(CONFIG_VIDEO_S5K5CCGX_COMMON) || defined(CONFIG_VIDEO_S5K5BAFX) \
+	|| defined(CONFIG_VIDEO_SR200PC20)
+
+	dev_rear = device_create(cls, NULL, 0, NULL, "rear");
+	if (IS_ERR(dev_rear)) {
+		pr_err("cam_init: failed to create device(rearcam_dev)\n");
+		dev_rear = NULL;
+		goto front;
+	}
+
+	ret = device_create_file(dev_rear, &dev_attr_rear_camtype);
+	if (unlikely(ret < 0)) {
+		pr_err("cam_init: failed to create device file, %s\n",
+			dev_attr_rear_camtype.attr.name);
+	}
+
+	ret = device_create_file(dev_rear, &dev_attr_rear_flash);
+	if (unlikely(ret < 0)) {
+		pr_err("cam_init: failed to create device file, %s\n",
+			dev_attr_rear_flash.attr.name);
+	}
+
+	ret = device_create_file(dev_rear, &dev_attr_loglevel);
+	if (unlikely(ret < 0)) {
+		pr_err("cam_init: failed to create device file, %s\n",
+			dev_attr_loglevel.attr.name);
+	}
+
+front:
+	dev_front = device_create(cls, NULL, 0, NULL, "front");
+	if (IS_ERR(dev_front)) {
+		pr_err("cam_init: failed to create device(frontcam_dev)\n");
+		goto out_unreg_class;
+	}
+
+	ret = device_create_file(dev_front, &dev_attr_front_camtype);
+	if (unlikely(ret < 0)) {
+		pr_err("cam_init: failed to create device file, %s\n",
+			dev_attr_front_camtype.attr.name);
+		goto out_unreg_dev_front;
+	}
+#endif
+	return 0;
+
+out_unreg_dev_front:
+	device_destroy(cls, 0);
+out_unreg_class:
+	if (!dev_rear)
+		class_destroy(cls);
+
+	return -ENODEV;
+}
+
+static struct class *camera_class;
+
+/**
+ * cam_init - Intialize something concerning camera device if needed.
+ *
+ * And excute codes about camera needed on boot-up time
+ */
+static void cam_init(void)
+{
+	/* pr_info("%s: E\n", __func__); */
+
+	cam_cfg_init();
+
+	camera_class = class_create(THIS_MODULE, "camera");
+	if (IS_ERR(camera_class)) {
+		pr_err("cam_init: failed to create class\n");
+		return;
+	}
+
+	/* create device and device file for supporting camera sysfs.*/
+	cam_create_file(camera_class);
+
+	pr_info("%s: X\n", __func__);
+}
+
+#endif				/* CONFIG_VIDEO_FIMC */
+
+#ifdef CONFIG_S3C_DEV_HSMMC
+static struct s3c_sdhci_platdata exynos4_hsmmc0_pdata __initdata = {
+	.cd_type = S3C_SDHCI_CD_PERMANENT,
+	.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
+#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
+	.max_width = 8,
+	.host_caps = MMC_CAP_8_BIT_DATA,
+#endif
+};
+#endif
+
+#ifdef CONFIG_S3C_DEV_HSMMC2
+static struct s3c_sdhci_platdata exynos4_hsmmc2_pdata __initdata = {
+	.cd_type = S3C_SDHCI_CD_GPIO,
+	.ext_cd_gpio = EXYNOS4_GPX3(4),
+	.ext_cd_gpio_invert = 1,
+	.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
+	.vmmc_name = "vtf_2.8v",
+};
+#endif
+
+#ifdef CONFIG_S3C_DEV_HSMMC3
+static struct s3c_sdhci_platdata exynos4_hsmmc3_pdata __initdata = {
+/* For Wi-Fi */
+	.cd_type = S3C_SDHCI_CD_EXTERNAL,
+	.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
+	.host_caps = MMC_CAP_4_BIT_DATA,
+	.pm_flags = S3C_SDHCI_PM_IGNORE_SUSPEND_RESUME,
+#ifdef CONFIG_MACH_PX
+	.ext_cd_init = register_wlan_status_notify,
+	.ext_pdev = register_wlan_pdev
+#endif
+};
+#endif
+
+#ifdef CONFIG_EXYNOS4_DEV_MSHC
+static struct s3c_mshci_platdata exynos4_mshc_pdata __initdata = {
+	.cd_type = S3C_MSHCI_CD_PERMANENT,
+#if defined(CONFIG_EXYNOS4_MSHC_8BIT) &&	\
+	defined(CONFIG_EXYNOS4_MSHC_DDR)
+	.max_width = 8,
+	.host_caps = MMC_CAP_8_BIT_DATA | MMC_CAP_1_8V_DDR | MMC_CAP_UHS_DDR50,
+#elif defined(CONFIG_EXYNOS4_MSHC_8BIT)
+	.max_width = 8,
+	.host_caps = MMC_CAP_8_BIT_DATA,
+#elif defined(CONFIG_EXYNOS4_MSHC_DDR)
+	.host_caps = MMC_CAP_1_8V_DDR | MMC_CAP_UHS_DDR50,
+#endif
+	.int_power_gpio = GPIO_XMMC0_CDn,
+};
+#endif
+
+#ifdef CONFIG_VIDEO_FIMG2D
+static struct fimg2d_platdata fimg2d_data __initdata = {
+	.hw_ver = 30,
+	.parent_clkname = "mout_g2d0",
+	.clkname = "sclk_fimg2d",
+	.gate_clkname = "fimg2d",
+	.clkrate = 267 * 1000000,	/* 266 Mhz */
+};
+#endif
+
+#ifdef CONFIG_FB_S3C
+#if defined(CONFIG_LCD_AMS369FG06)
+static int lcd_power_on(struct lcd_device *ld, int enable)
+{
+	return 1;
+}
+
+static int reset_lcd(struct lcd_device *ld)
+{
+	int err = 0;
+
+	err = gpio_request(EXYNOS4_GPX0(6), "GPX0");
+	if (err) {
+		printk(KERN_ERR "failed to request GPX0 for "
+		       "lcd reset control\n");
+		return err;
+	}
+
+	gpio_direction_output(EXYNOS4_GPX0(6), 1);
+	msleep(100);
+
+	gpio_set_value(EXYNOS4_GPX0(6), 1);
+	msleep(100);
+
+	gpio_free(EXYNOS4_GPX0(6));
+
+	return 1;
+}
+
+static struct lcd_platform_data ams369fg06_platform_data = {
+	.reset = reset_lcd,
+	.power_on = lcd_power_on,
+	.lcd_enabled = 0,
+	.reset_delay = 100,	/* 100ms */
+};
+
+#define		LCD_BUS_NUM	3
+#define		DISPLAY_CS	EXYNOS4_GPB(5)
+#define		DISPLAY_CLK	EXYNOS4_GPB(4)
+#define		DISPLAY_SI	EXYNOS4_GPB(7)
+
+static struct spi_board_info spi_board_info[] __initdata = {
+	{
+		.modalias = "ams369fg06",
+		.platform_data = (void *)&ams369fg06_platform_data,
+		.max_speed_hz = 1200000,
+		.bus_num = LCD_BUS_NUM,
+		.chip_select = 0,
+		.mode = SPI_MODE_3,
+		.controller_data = (void *)DISPLAY_CS,
+	}
+};
+
+static struct spi_gpio_platform_data ams369fg06_spi_gpio_data = {
+	.sck = DISPLAY_CLK,
+	.mosi = DISPLAY_SI,
+	.miso = -1,
+	.num_chipselect = 1,
+};
+
+static struct platform_device s3c_device_spi_gpio = {
+	.name = "spi_gpio",
+	.id = LCD_BUS_NUM,
+	.dev = {
+		.parent = &s5p_device_fimd0.dev,
+		.platform_data = &ams369fg06_spi_gpio_data,
+	},
+};
+
+static struct s3c_fb_pd_win smdkc210_fb_win0 = {
+	.win_mode = {
+		.left_margin = 9,
+		.right_margin = 9,
+		.upper_margin = 5,
+		.lower_margin = 5,
+		.hsync_len = 2,
+		.vsync_len = 2,
+		.xres = 480,
+		.yres = 800,
+	},
+	.virtual_x = 480,
+	.virtual_y = 1600,
+	.width = 48,
+	.height = 80,
+	.max_bpp = 32,
+	.default_bpp = 24,
+};
+
+static struct s3c_fb_pd_win smdkc210_fb_win1 = {
+	.win_mode = {
+		.left_margin = 9,
+		.right_margin = 9,
+		.upper_margin = 5,
+		.lower_margin = 5,
+		.hsync_len = 2,
+		.vsync_len = 2,
+		.xres = 480,
+		.yres = 800,
+	},
+	.virtual_x = 480,
+	.virtual_y = 1600,
+	.width = 48,
+	.height = 80,
+	.max_bpp = 32,
+	.default_bpp = 24,
+};
+
+static struct s3c_fb_pd_win smdkc210_fb_win2 = {
+	.win_mode = {
+		.left_margin = 9,
+		.right_margin = 9,
+		.upper_margin = 5,
+		.lower_margin = 5,
+		.hsync_len = 2,
+		.vsync_len = 2,
+		.xres = 480,
+		.yres = 800,
+	},
+	.virtual_x = 480,
+	.virtual_y = 1600,
+	.width = 48,
+	.height = 80,
+	.max_bpp = 32,
+	.default_bpp = 24,
+};
+
+#elif defined(CONFIG_LCD_WA101S)
+static void lcd_wa101s_set_power(struct plat_lcd_data *pd, unsigned int power)
+{
+	if (power) {
+#if !defined(CONFIG_BACKLIGHT_PWM)
+		gpio_request(EXYNOS4_GPD0(1), "GPD0");
+		gpio_direction_output(EXYNOS4_GPD0(1), 1);
+		gpio_free(EXYNOS4_GPD0(1));
+#endif
+	} else {
+#if !defined(CONFIG_BACKLIGHT_PWM)
+		gpio_request(EXYNOS4_GPD0(1), "GPD0");
+		gpio_direction_output(EXYNOS4_GPD0(1), 0);
+		gpio_free(EXYNOS4_GPD0(1));
+#endif
+	}
+}
+
+static struct plat_lcd_data smdkc210_lcd_wa101s_data = {
+	.set_power = lcd_wa101s_set_power,
+};
+
+static struct platform_device smdkc210_lcd_wa101s = {
+	.name = "platform-lcd",
+	.dev.parent = &s5p_device_fimd0.dev,
+	.dev.platform_data = &smdkc210_lcd_wa101s_data,
+};
+
+static struct s3c_fb_pd_win smdkc210_fb_win0 = {
+	.win_mode = {
+		.left_margin = 80,
+		.right_margin = 48,
+		.upper_margin = 14,
+		.lower_margin = 3,
+		.hsync_len = 32,
+		.vsync_len = 5,
+		.xres = 1366,
+		.yres = 768,
+	},
+	.virtual_x = 1366,
+	.virtual_y = 768 * 2,
+	.width = 223,
+	.height = 125,
+	.max_bpp = 32,
+	.default_bpp = 24,
+};
+
+#ifndef CONFIG_LCD_WA101S	/* temporarily disables window1 */
+static struct s3c_fb_pd_win smdkc210_fb_win1 = {
+	.win_mode = {
+		.left_margin = 80,
+		.right_margin = 48,
+		.upper_margin = 14,
+		.lower_margin = 3,
+		.hsync_len = 32,
+		.vsync_len = 5,
+		.xres = 1366,
+		.yres = 768,
+	},
+	.virtual_x = 1366,
+	.virtual_y = 768 * 2,
+	.max_bpp = 32,
+	.default_bpp = 24,
+};
+#endif
+
+#elif defined(CONFIG_LCD_LTE480WV)
+static void lcd_lte480wv_set_power(struct plat_lcd_data *pd, unsigned int power)
+{
+	if (power) {
+#if !defined(CONFIG_BACKLIGHT_PWM)
+		gpio_request(EXYNOS4_GPD0(1), "GPD0");
+		gpio_direction_output(EXYNOS4_GPD0(1), 1);
+		gpio_free(EXYNOS4_GPD0(1));
+#endif
+		/* fire nRESET on power up */
+		gpio_request(EXYNOS4_GPX0(6), "GPX0");
+
+		gpio_direction_output(EXYNOS4_GPX0(6), 1);
+		msleep(100);
+
+		gpio_set_value(EXYNOS4_GPX0(6), 0);
+		mdelay(10);
+
+		gpio_set_value(EXYNOS4_GPX0(6), 1);
+		mdelay(10);
+
+		gpio_free(EXYNOS4_GPX0(6));
+	} else {
+#if !defined(CONFIG_BACKLIGHT_PWM)
+		gpio_request(EXYNOS4_GPD0(1), "GPD0");
+		gpio_direction_output(EXYNOS4_GPD0(1), 0);
+		gpio_free(EXYNOS4_GPD0(1));
+#endif
+	}
+}
+
+static struct plat_lcd_data smdkc210_lcd_lte480wv_data = {
+	.set_power = lcd_lte480wv_set_power,
+};
+
+static struct platform_device smdkc210_lcd_lte480wv = {
+	.name = "platform-lcd",
+	.dev.parent = &s5p_device_fimd0.dev,
+	.dev.platform_data = &smdkc210_lcd_lte480wv_data,
+};
+
+static struct s3c_fb_pd_win smdkc210_fb_win0 = {
+	.win_mode = {
+		.left_margin = 13,
+		.right_margin = 8,
+		.upper_margin = 7,
+		.lower_margin = 5,
+		.hsync_len = 3,
+		.vsync_len = 1,
+		.xres = 800,
+		.yres = 480,
+	},
+	.virtual_x = 800,
+	.virtual_y = 960,
+	.max_bpp = 32,
+	.default_bpp = 24,
+};
+
+static struct s3c_fb_pd_win smdkc210_fb_win1 = {
+	.win_mode = {
+		.left_margin = 13,
+		.right_margin = 8,
+		.upper_margin = 7,
+		.lower_margin = 5,
+		.hsync_len = 3,
+		.vsync_len = 1,
+		.xres = 800,
+		.yres = 480,
+	},
+	.virtual_x = 800,
+	.virtual_y = 960,
+	.max_bpp = 32,
+	.default_bpp = 24,
+};
+#endif
+
+static struct s3c_fb_platdata smdkc210_lcd0_pdata __initdata = {
+#if defined(CONFIG_LCD_AMS369FG06) || defined(CONFIG_LCD_WA101S) ||	\
+	defined(CONFIG_LCD_LTE480WV)
+	.win[0] = &smdkc210_fb_win0,
+#ifndef CONFIG_LCD_WA101S	/* temporarily disables window1 */
+	.win[1] = &smdkc210_fb_win1,
+#endif
+#endif
+	.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+#if defined(CONFIG_LCD_AMS369FG06)
+	.vidcon1 = VIDCON1_INV_VCLK | VIDCON1_INV_VDEN |
+	VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+#elif defined(CONFIG_LCD_WA101S)
+	.vidcon1 = VIDCON1_INV_VCLK | VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+#elif defined(CONFIG_LCD_LTE480WV)
+	.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+#endif
+	.setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
+};
+#endif
+
+#ifdef CONFIG_S3C64XX_DEV_SPI0
+static struct s3c64xx_spi_csinfo spi0_csi[] = {
+	[0] = {
+		.line = EXYNOS4_GPB(1),
+		.set_level = gpio_set_value,
+		.fb_delay = 0x0,
+	},
+};
+
+static struct spi_board_info spi0_board_info[] __initdata = {
+	{
+		.modalias = "spidev",
+		.platform_data = NULL,
+		.max_speed_hz = 10 * 1000 * 1000,
+		.bus_num = 0,
+		.chip_select = 0,
+		.mode = SPI_MODE_0,
+		.controller_data = &spi0_csi[0],
+	}
+};
+#endif
+
+#ifdef CONFIG_FB_S5P
+
+#ifdef CONFIG_FB_S5P_AMS369FG06
+static struct s3c_platform_fb ams369fg06_data __initdata = {
+	.hw_ver = 0x70,
+	.clk_name = "sclk_lcd",
+	.nr_wins = 5,
+	.default_win = CONFIG_FB_S5P_DEFAULT_WINDOW,
+	.swap = FB_SWAP_HWORD | FB_SWAP_WORD,
+};
+
+#define		LCD_BUS_NUM	3
+#define		DISPLAY_CS	EXYNOS4_GPB(5)
+#define		DISPLAY_CLK	EXYNOS4_GPB(4)
+#define		DISPLAY_SI	EXYNOS4_GPB(7)
+
+static struct spi_board_info spi_board_info[] __initdata = {
+	{
+		.modalias = "ams369fg06",
+		.platform_data = NULL,
+		.max_speed_hz = 1200000,
+		.bus_num = LCD_BUS_NUM,
+		.chip_select = 0,
+		.mode = SPI_MODE_3,
+		.controller_data = (void *)DISPLAY_CS,
+	}
+};
+
+static struct spi_gpio_platform_data ams369fg06_spi_gpio_data = {
+	.sck = DISPLAY_CLK,
+	.mosi = DISPLAY_SI,
+	.miso = -1,
+	.num_chipselect = 1,
+};
+
+static struct platform_device s3c_device_spi_gpio = {
+	.name = "spi_gpio",
+	.id = LCD_BUS_NUM,
+	.dev = {
+		.parent = &s3c_device_fb.dev,
+		.platform_data = &ams369fg06_spi_gpio_data,
+	},
+};
+#endif
+#endif
+
+static struct resource smdkc210_smsc911x_resources[] = {
+	[0] = {
+		.start = EXYNOS4_PA_SROM_BANK(1),
+		.end = EXYNOS4_PA_SROM_BANK(1) + SZ_64K - 1,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = IRQ_EINT(5),
+		.end = IRQ_EINT(5),
+		.flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
+	},
+};
+
+static struct smsc911x_platform_config smsc9215_config = {
+	.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+	.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
+	.flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
+	.phy_interface = PHY_INTERFACE_MODE_MII,
+	.mac = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
+};
+
+static struct platform_device smdkc210_smsc911x = {
+	.name = "smsc911x",
+	.id = -1,
+	.num_resources = ARRAY_SIZE(smdkc210_smsc911x_resources),
+	.resource = smdkc210_smsc911x_resources,
+	.dev = {
+		.platform_data = &smsc9215_config,
+	},
+};
+
+static struct platform_device u1_regulator_consumer = {
+	.name = "u1-regulator-consumer",
+	.id = -1,
+};
+
+#ifdef CONFIG_REGULATOR_MAX8997
+static struct regulator_consumer_supply ldo1_supply[] = {
+	REGULATOR_SUPPLY("vadc_3.3v", NULL),
+};
+
+static struct regulator_consumer_supply ldo3_supply[] = {
+	REGULATOR_SUPPLY("vusb_1.1v", "s5p-ehci"),
+	REGULATOR_SUPPLY("vusb_1.1v", "usb_otg"),
+	REGULATOR_SUPPLY("vmipi_1.1v", "m5mo"),
+	REGULATOR_SUPPLY("vmipi_1.1v", NULL),
+};
+
+static struct regulator_consumer_supply ldo4_supply[] = {
+	REGULATOR_SUPPLY("vmipi_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo5_supply[] = {
+	REGULATOR_SUPPLY("vhsic", NULL),
+};
+
+static struct regulator_consumer_supply ldo7_supply[] = {
+	REGULATOR_SUPPLY("vt_core_1.5v", NULL),
+	REGULATOR_SUPPLY("vt_core_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo8_supply[] = {
+	REGULATOR_SUPPLY("vusb_3.3v", NULL),
+};
+
+static struct regulator_consumer_supply ldo10_supply[] = {
+	REGULATOR_SUPPLY("vpll_1.1v", NULL),
+};
+
+static struct regulator_consumer_supply ldo11_supply[] = {
+	REGULATOR_SUPPLY("hdp_2.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo12_supply[] = {
+	REGULATOR_SUPPLY("cam_io_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo13_supply[] = {
+	REGULATOR_SUPPLY("cam_analog_2.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo14_supply[] = {
+	REGULATOR_SUPPLY("vmotor", NULL),
+};
+
+static struct regulator_consumer_supply ldo15_supply[] = {
+	REGULATOR_SUPPLY("vled_3.3v", NULL),
+};
+
+static struct regulator_consumer_supply ldo16_supply[] = {
+	REGULATOR_SUPPLY("irda_2.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo17_supply[] = {
+	REGULATOR_SUPPLY("3m_af_2.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo18_supply[] = {
+	REGULATOR_SUPPLY("vtf_2.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo21_supply[] = {
+	REGULATOR_SUPPLY("vddq_m1m2", NULL),
+};
+
+static struct regulator_consumer_supply buck1_supply[] = {
+	REGULATOR_SUPPLY("vdd_arm", NULL),
+};
+
+static struct regulator_consumer_supply buck2_supply[] = {
+	REGULATOR_SUPPLY("vdd_int", NULL),
+};
+
+static struct regulator_consumer_supply buck3_supply[] = {
+	REGULATOR_SUPPLY("vdd_g3d", NULL),
+};
+
+static struct regulator_consumer_supply buck4_supply[] = {
+	REGULATOR_SUPPLY("3mp_core", NULL),
+};
+
+static struct regulator_consumer_supply buck7_supply[] = {
+	REGULATOR_SUPPLY("vcc_sub", NULL),
+};
+
+static struct regulator_consumer_supply safeout1_supply[] = {
+	REGULATOR_SUPPLY("safeout1", NULL),
+};
+
+static struct regulator_consumer_supply safeout2_supply[] = {
+	REGULATOR_SUPPLY("safeout2", NULL),
+};
+
+#define REGULATOR_INIT(_ldo, _name, _min_uV, _max_uV, _always_on, _ops_mask, \
+		       _disabled)					\
+	static struct regulator_init_data _ldo##_init_data = {		\
+		.constraints = {					\
+			.name	= _name,				\
+			.min_uV = _min_uV,				\
+			.max_uV = _max_uV,				\
+			.always_on	= _always_on,			\
+			.boot_on	= _always_on,			\
+			.apply_uV	= 1,				\
+			.valid_ops_mask = _ops_mask,			\
+			.state_mem	= {				\
+				.disabled =				\
+					(_disabled == -1 ? 0 : _disabled),\
+				.enabled =				\
+					(_disabled == -1 ? 0 : !(_disabled)),\
+			}						\
+		},							\
+		.num_consumer_supplies = ARRAY_SIZE(_ldo##_supply),	\
+		.consumer_supplies = &_ldo##_supply[0],			\
+	};
+
+REGULATOR_INIT(ldo1, "VADC_3.3V_C210", 3300000, 3300000, 1,
+		REGULATOR_CHANGE_STATUS, 0);
+REGULATOR_INIT(ldo3, "VUSB_1.1V", 1100000, 1100000, 1,
+		REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo4, "VMIPI_1.8V", 1800000, 1800000, 1,
+		REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo5, "VHSIC_1.2V", 1200000, 1200000, 1,
+		REGULATOR_CHANGE_STATUS, 1);
+
+#if defined(CONFIG_MACH_P8) || defined(CONFIG_MACH_P8LTE)
+REGULATOR_INIT(ldo7, "VT_CORE_1.5V", 1500000, 1500000, 0,
+		REGULATOR_CHANGE_STATUS, 1);
+#else
+REGULATOR_INIT(ldo7, "VT_CORE_1.8V", 1800000, 1800000, 0,
+		REGULATOR_CHANGE_STATUS, 1);
+#endif
+
+REGULATOR_INIT(ldo8, "VUSB_3.3V", 3300000, 3300000, 1,
+		REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo10, "VPLL_1.2V", 1200000, 1200000, 1,
+		REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo11, "VCC_2.8V_HPD", 2800000, 2800000, 0,
+		REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo12, "CAM_IO_1.8V", 1800000, 1800000, 0,
+		REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo13, "CAM_ANALOG_2.8V", 2800000, 2800000, 0,
+		REGULATOR_CHANGE_STATUS, 1);
+
+#if defined(CONFIG_MACH_P2)
+REGULATOR_INIT(ldo14, "VCC_3.0V_MOTOR", 2400000, 2400000, 0,
+		REGULATOR_CHANGE_STATUS, 1);
+#elif defined(CONFIG_MACH_P8) || defined(CONFIG_MACH_P8LTE)
+REGULATOR_INIT(ldo14, "VCC_3.0V_MOTOR", 3100000, 3100000, 0,
+		REGULATOR_CHANGE_STATUS, 1);
+#else
+REGULATOR_INIT(ldo14, "VCC_3.0V_MOTOR", 3000000, 3000000, 0,
+		REGULATOR_CHANGE_STATUS, 1);
+#endif
+
+#if defined(CONFIG_MACH_P8)
+REGULATOR_INIT(ldo15, "VLED_3.3V", 3200000, 3200000, 1,
+		REGULATOR_CHANGE_STATUS, -1);
+#else
+REGULATOR_INIT(ldo15, "VLED_3.3V", 3300000, 3300000, 0,
+		REGULATOR_CHANGE_STATUS, 1);
+#endif
+
+REGULATOR_INIT(ldo16, "IRDA_2.8V", 2800000, 2800000, 0,
+		REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo17, "3M_AF_2.8V", 2800000, 2800000, 0,
+		REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo18, "VTF_2.8V", 2800000, 2800000, 0,
+		REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo21, "VDDQ_M1M2_1.2V", 1200000, 1200000, 1,
+		REGULATOR_CHANGE_STATUS, 1);
+
+static struct regulator_init_data buck1_init_data = {
+	.constraints	= {
+		.name		= "vdd_arm range",
+		.min_uV		= 650000,
+		.max_uV		= 2225000,
+		.always_on	= 1,
+		.boot_on	= 1,
+		.apply_uV	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE |
+				  REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.uV		= 1250000,
+			.mode		= REGULATOR_MODE_NORMAL,
+			.disabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &buck1_supply[0],
+};
+
+static struct regulator_init_data buck2_init_data = {
+	.constraints	= {
+		.name		= "vdd_int range",
+		.min_uV		= 650000,
+		.max_uV		= 2225000,
+		.always_on	= 1,
+		.boot_on	= 1,
+		.apply_uV	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE |
+				  REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.uV		= 1100000,
+			.mode		= REGULATOR_MODE_NORMAL,
+			.disabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &buck2_supply[0],
+};
+
+static struct regulator_init_data buck3_init_data = {
+	.constraints	= {
+		.name		= "G3D_1.1V",
+		.min_uV		= 900000,
+		.max_uV		= 1200000,
+		.always_on	= 0,
+		.boot_on	= 1,
+		.apply_uV	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE |
+				  REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.uV		= 1100000,
+			.mode		= REGULATOR_MODE_NORMAL,
+			.disabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &buck3_supply[0],
+};
+
+static struct regulator_init_data buck4_init_data = {
+	.constraints	= {
+		.name		= "3MP_CORE_1.2V",
+		.min_uV		= 1200000,
+		.max_uV		= 1200000,
+		.apply_uV	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.disabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &buck4_supply[0],
+};
+
+static struct regulator_init_data buck5_init_data = {
+	.constraints	= {
+		.name		= "VMEM_1.2V",
+		.min_uV		= 1200000,
+		.max_uV		= 1200000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.state_mem	= {
+			.uV		= 1200000,
+			.mode		= REGULATOR_MODE_NORMAL,
+			.enabled = 1,
+		},
+	},
+};
+
+static struct regulator_init_data buck7_init_data = {
+	.constraints	= {
+		.name		= "VCC_SUB_2.0V",
+		.min_uV		= 2000000,
+		.max_uV		= 2000000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.enabled = 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &buck7_supply[0],
+};
+
+static struct regulator_init_data safeout1_init_data = {
+	.constraints	= {
+		.name		= "safeout1 range",
+		.valid_ops_mask	= REGULATOR_CHANGE_STATUS,
+		.always_on	= 1,
+		.boot_on	= 1,
+		.state_mem      = {
+			.enabled = 1,
+			},
+	},
+	.num_consumer_supplies	= ARRAY_SIZE(safeout1_supply),
+	.consumer_supplies	= safeout1_supply,
+};
+
+static struct regulator_init_data safeout2_init_data = {
+	.constraints	= {
+		.name		= "safeout2 range",
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.always_on	= 0,
+		.boot_on	= 0,
+		.state_mem	= {
+			.enabled = 1,
+		},
+	},
+	.num_consumer_supplies	= ARRAY_SIZE(safeout2_supply),
+	.consumer_supplies	= safeout2_supply,
+};
+
+static struct max8997_regulator_data max8997_regulators[] = {
+	{ MAX8997_LDO1,	 &ldo1_init_data, NULL, },
+	{ MAX8997_LDO3,  &ldo3_init_data, NULL, },
+	{ MAX8997_LDO4,  &ldo4_init_data, NULL, },
+	{ MAX8997_LDO5,  &ldo5_init_data, NULL, },
+	{ MAX8997_LDO7,  &ldo7_init_data, NULL, },
+	{ MAX8997_LDO8,  &ldo8_init_data, NULL, },
+	{ MAX8997_LDO10, &ldo10_init_data, NULL, },
+	{ MAX8997_LDO11, &ldo11_init_data, NULL, },
+	{ MAX8997_LDO12, &ldo12_init_data, NULL, },
+	{ MAX8997_LDO13, &ldo13_init_data, NULL, },
+	{ MAX8997_LDO14, &ldo14_init_data, NULL, },
+	{ MAX8997_LDO15, &ldo15_init_data, NULL, },
+	{ MAX8997_LDO16, &ldo16_init_data, NULL, },
+	{ MAX8997_LDO17, &ldo17_init_data, NULL, },
+	{ MAX8997_LDO18, &ldo18_init_data, NULL, },
+	{ MAX8997_LDO21, &ldo21_init_data, NULL, },
+	{ MAX8997_BUCK1, &buck1_init_data, NULL, },
+	{ MAX8997_BUCK2, &buck2_init_data, NULL, },
+	{ MAX8997_BUCK3, &buck3_init_data, NULL, },
+	{ MAX8997_BUCK4, &buck4_init_data, NULL, },
+	{ MAX8997_BUCK5, &buck5_init_data, NULL, },
+	{ MAX8997_BUCK7, &buck7_init_data, NULL, },
+	{ MAX8997_ESAFEOUT1, &safeout1_init_data, NULL, },
+	{ MAX8997_ESAFEOUT2, &safeout2_init_data, NULL, },
+};
+
+static struct max8997_power_data max8997_power = {
+	.batt_detect = 1,
+};
+
+#ifdef CONFIG_VIBETONZ
+static struct max8997_motor_data max8997_motor = {
+#if defined(CONFIG_MACH_P8) || defined(CONFIG_MACH_P8LTE)
+	.reg2 = MOTOR_LRA | EXT_PWM | DIVIDER_256,
+#else
+	.reg2 = MOTOR_LRA | EXT_PWM | DIVIDER_128,
+#endif
+	.max_timeout = 10000,
+#if defined(CONFIG_MACH_P4)
+	.duty = 37000,
+	.period = 38675,
+#elif defined(CONFIG_MACH_P2)
+	.duty = 44707,
+	.period = 45159,
+#elif defined(CONFIG_MACH_P8) || defined(CONFIG_MACH_P8LTE)
+	.duty = 38288,
+	.period = 38676,
+#else
+	.duty = 37641,
+	.period = 38022,
+#endif
+	.init_hw = NULL,
+	.motor_en = NULL,
+	.pwm_id = 1,
+};
+#endif
+
+static struct max8997_buck1_dvs_funcs *buck1_dvs_funcs;
+
+void max8997_set_arm_voltage_table(int *voltage_table, int arr_size)
+{
+	pr_info("%s\n", __func__);
+	if (buck1_dvs_funcs && buck1_dvs_funcs->set_buck1_dvs_table)
+		buck1_dvs_funcs->set_buck1_dvs_table(buck1_dvs_funcs,
+			 voltage_table, arr_size);
+}
+
+static void max8997_register_buck1dvs_funcs(struct max8997_buck1_dvs_funcs *ptr)
+{
+	buck1_dvs_funcs = ptr;
+}
+
+static struct max8997_platform_data exynos4_max8997_info = {
+	.num_regulators = ARRAY_SIZE(max8997_regulators),
+	.regulators	= &max8997_regulators[0],
+	.irq_base	= IRQ_BOARD_START,
+	.wakeup		= 1,
+	.buck1_gpiodvs	= false,
+	.buck1_max_vol	= 1350000,
+	.buck2_max_vol	= 1150000,
+	.buck5_max_vol	= 1200000,
+	.buck_set1 = GPIO_BUCK1_EN_A,
+	.buck_set2 = GPIO_BUCK1_EN_B,
+	.buck_set3 = GPIO_BUCK2_EN,
+	.buck_ramp_en = true,
+	.buck_ramp_delay = 10,		/* 10.00mV /us (default) */
+	.flash_cntl_val = 0x5F,	/* Flash safety timer duration: 800msec,
+					   Maximum timer mode */
+	.mr_debounce_time = 8,	/* 8sec */
+	.power = &max8997_power,
+#ifdef CONFIG_VIBETONZ
+	.motor = &max8997_motor,
+#endif
+	.register_buck1_dvs_funcs = max8997_register_buck1dvs_funcs,
+};
+#endif /* CONFIG_REGULATOR_MAX8997 */
+
+
+#ifdef CONFIG_MPU_SENSORS_MPU3050
+
+extern struct class *sec_class;
+
+/* we use a skeleton to provide some information needed by MPL
+ * but we don't use the suspend/resume/read functions so we
+ * don't initialize them so that mldl_cfg.c doesn't try to
+ * control it directly.  we have a separate mag driver instead.
+ */
+static struct mpu3050_platform_data mpu3050_pdata = {
+	.int_config  = 0x12,
+	/* Orientation for MPU.  Part is mounted rotated
+	 * 90 degrees counter-clockwise from natural orientation.
+	 * So X & Y are swapped and Y is negated.
+	 */
+#if defined(CONFIG_MACH_P8)
+	.orientation = {0, 1, 0,
+			1, 0, 0,
+			0, 0, -1},
+#elif defined(CONFIG_MACH_P8LTE)
+	.orientation = {0, -1, 0,
+			1, 0, 0,
+			0, 0, 1},
+#elif defined(CONFIG_MACH_P2)
+	.orientation = {0, 1, 0,
+			1, 0, 0,
+			0, 0, -1},
+#elif defined(CONFIG_MACH_P4)
+	.orientation = {1 , 0, 0,
+			0, -1, 0,
+			0, 0, -1},
+#else
+	.orientation = {0, -1, 0,
+			-1, 0, 0,
+			0, 0, -1},
+#endif
+	.level_shifter = 0,
+	.accel = {
+		.get_slave_descr = kxtf9_get_slave_descr,
+		.irq		= 0,	/* not used */
+		.adapt_num	= 1,
+		.bus		= EXT_SLAVE_BUS_SECONDARY,
+		.address	= 0x0F,
+		/* Orientation for the Acc.  Part is mounted rotated
+		 * 180 degrees from natural orientation.
+		 * So X & Y are both negated.
+		 */
+#if defined(CONFIG_MACH_P8)
+		.orientation = {0, 1, 0,
+				1, 0, 0,
+				0, 0, -1},
+#elif defined(CONFIG_MACH_P8LTE)
+		.orientation = {0, 1, 0,
+				-1, 0, 0,
+				0, 0, 1},
+#elif defined(CONFIG_MACH_P2)
+		.orientation = {0, 1, 0,
+				1, 0, 0,
+				0, 0, -1},
+#elif defined(CONFIG_MACH_P4)
+		.orientation = {0, -1, 0,
+				-1, 0, 0,
+				0, 0, -1},
+#else
+		/* Rotate Accel Orientation for CL339008 */
+		.orientation = {0, -1, 0,
+				-1, 0, 0,
+				0, 0, -1},
+#endif
+	},
+
+	.compass = {
+		.get_slave_descr = NULL,
+		.adapt_num	= 7,	/*bus number 7*/
+		.bus		= EXT_SLAVE_BUS_PRIMARY,
+		.address	= 0x0C,
+		/* Orientation for the Mag.  Part is mounted rotated
+		 * 90 degrees clockwise from natural orientation.
+		 * So X & Y are swapped and Y & Z are negated.
+		 */
+		.orientation = {0, -1, 0,
+				1, 0, 0,
+				0, 0, 1},
+	},
+
+};
+
+
+static void ak8975_init(void)
+{
+	gpio_request(GPIO_MSENSE_INT, "ak8975_int");
+	gpio_direction_input(GPIO_MSENSE_INT);
+}
+
+static void mpu3050_init(void)
+{
+	gpio_request(GPIO_GYRO_INT, "mpu3050_int");
+	gpio_direction_input(GPIO_GYRO_INT);
+	/* mpu3050_pdata.sec_class = sec_class; */
+}
+
+static const struct i2c_board_info i2c_mpu_sensor_board_info[] = {
+	{
+		I2C_BOARD_INFO("mpu3050", 0x68),
+		.irq = IRQ_EINT(0),
+		.platform_data = &mpu3050_pdata,
+	},
+#if 0
+	{
+		I2C_BOARD_INFO("kxtf9", 0x0F),
+	},
+#endif
+};
+#endif   /* CONFIG_MPU_SENSORS_MPU3050 */
+
+static int check_bootmode(void)
+{
+	return __raw_readl(S5P_INFORM2);
+}
+
+static int check_jig_on(void)
+{
+	return !gpio_get_value(GPIO_IF_CON_SENSE);
+}
+
+/* Bluetooth */
+#ifdef CONFIG_BT_BCM4330
+static struct platform_device bcm4330_bluetooth_device = {
+	.name = "bcm4330_bluetooth",
+	.id = -1,
+};
+#endif				/* CONFIG_BT_BCM4330 */
+
+#ifdef CONFIG_BT_CSR8811
+static struct platform_device csr8811_bluetooth_device = {
+	.name = "csr8811_bluetooth",
+	.id = -1,
+};
+#endif				/* CONFIG_BT_CSR8811 */
+
+#define SYSTEM_REV_SND 0x09
+
+#ifdef CONFIG_SND_SOC_U1_MC1N2
+static DEFINE_SPINLOCK(mic_bias_lock);
+#ifndef CONFIG_MACH_P8
+static bool mc1n2_mainmic_bias;
+static bool mc1n2_submic_bias;
+static void set_shared_mic_bias(void)
+{
+	if (system_rev >= 0x03)
+		gpio_set_value(GPIO_MIC_BIAS_EN, mc1n2_mainmic_bias
+			       || mc1n2_submic_bias);
+	else
+		gpio_set_value(GPIO_EAR_MIC_BIAS_EN, mc1n2_mainmic_bias
+			       || mc1n2_submic_bias);
+}
+#endif
+void sec_set_sub_mic_bias(bool on)
+{
+#ifdef CONFIG_MACH_P4
+	return;
+#else
+#ifdef CONFIG_SND_SOC_USE_EXTERNAL_MIC_BIAS
+#ifdef CONFIG_MACH_P8
+		gpio_set_value(GPIO_SUB_MIC_BIAS_EN, on);
+#else
+		unsigned long flags;
+		spin_lock_irqsave(&mic_bias_lock, flags);
+		mc1n2_submic_bias = on;
+		set_shared_mic_bias();
+		spin_unlock_irqrestore(&mic_bias_lock, flags);
+#endif
+#endif
+#endif
+}
+
+void sec_set_main_mic_bias(bool on)
+{
+#ifdef CONFIG_SND_SOC_USE_EXTERNAL_MIC_BIAS
+
+#ifdef CONFIG_MACH_P8
+		gpio_set_value(GPIO_MAIN_MIC_BIAS_EN, on);
+#else
+		unsigned long flags;
+		spin_lock_irqsave(&mic_bias_lock, flags);
+		mc1n2_mainmic_bias = on;
+		set_shared_mic_bias();
+		spin_unlock_irqrestore(&mic_bias_lock, flags);
+#endif
+#endif
+}
+
+int sec_set_ldo1_constraints(int disabled)
+{
+#if 0 /* VADC_3.3V_C210 is always on */
+	struct regulator *regulator;
+
+	if (!disabled) {
+		regulator = regulator_get(NULL, "vadc_3.3v");
+		if (IS_ERR(regulator))
+			return -1;
+		regulator_enable(regulator);
+		regulator_put(regulator);
+	} else {
+		regulator = regulator_get(NULL, "vadc_3.3v");
+		if (IS_ERR(regulator))
+			return -1;
+		if (regulator_is_enabled(regulator))
+			regulator_force_disable(regulator);
+		regulator_put(regulator);
+	}
+#endif
+	return 0;
+}
+
+static struct mc1n2_platform_data mc1n2_pdata = {
+	.set_main_mic_bias = sec_set_main_mic_bias,
+	.set_sub_mic_bias = sec_set_sub_mic_bias,
+	.set_adc_power_constraints = sec_set_ldo1_constraints,
+};
+
+static void u1_sound_init(void)
+{
+#ifdef CONFIG_SND_SOC_USE_EXTERNAL_MIC_BIAS
+	int err;
+
+#ifdef CONFIG_MACH_P8
+	err = gpio_request(GPIO_MAIN_MIC_BIAS_EN, "GPC0");
+	if (err) {
+		pr_err(KERN_ERR "MAIN_MIC_BIAS_EN GPIO set error!\n");
+		return;
+	}
+
+	gpio_direction_output(GPIO_MAIN_MIC_BIAS_EN, 1);
+	gpio_set_value(GPIO_MAIN_MIC_BIAS_EN, 0);
+	gpio_free(GPIO_MAIN_MIC_BIAS_EN);
+
+	err = gpio_request(GPIO_SUB_MIC_BIAS_EN, "GPE1");
+	if (err) {
+		pr_err(KERN_ERR "GPIO_SUB_MIC_BIAS_EN GPIO set error!\n");
+		return;
+	}
+	gpio_direction_output(GPIO_SUB_MIC_BIAS_EN, 1);
+	gpio_set_value(GPIO_SUB_MIC_BIAS_EN, 0);
+	gpio_free(GPIO_SUB_MIC_BIAS_EN);
+
+#else
+	err = gpio_request(GPIO_MIC_BIAS_EN, "GPE1");
+	if (err) {
+		pr_err(KERN_ERR "MIC_BIAS_EN GPIO set error!\n");
+		return;
+	}
+	gpio_direction_output(GPIO_MIC_BIAS_EN, 1);
+	gpio_set_value(GPIO_MIC_BIAS_EN, 0);
+	gpio_free(GPIO_MIC_BIAS_EN);
+
+#endif
+
+	err = gpio_request(GPIO_EAR_MIC_BIAS_EN, "GPE2");
+	if (err) {
+		pr_err(KERN_ERR "EAR_MIC_BIAS_EN GPIO set error!\n");
+		return;
+	}
+	gpio_direction_output(GPIO_EAR_MIC_BIAS_EN, 1);
+	gpio_set_value(GPIO_EAR_MIC_BIAS_EN, 0);
+	gpio_free(GPIO_EAR_MIC_BIAS_EN);
+#ifndef CONFIG_MACH_PX
+	if (system_rev >= SYSTEM_REV_SND) {
+		err = gpio_request(GPIO_SUB_MIC_BIAS_EN, "submic_bias");
+		if (err) {
+			pr_err(KERN_ERR "SUB_MIC_BIAS_EN GPIO set error!\n");
+			return;
+		}
+		gpio_direction_output(GPIO_SUB_MIC_BIAS_EN, 0);
+		gpio_free(GPIO_SUB_MIC_BIAS_EN);
+	}
+#endif
+#endif
+}
+#endif
+
+/* IR_LED */
+#ifdef CONFIG_IR_REMOCON
+
+static struct platform_device ir_remote_device = {
+	.name = "ir_rc",
+	.id = 0,
+	.dev = {
+	},
+};
+
+#if defined(CONFIG_MACH_P2) || defined(CONFIG_MACH_P4)
+static void ir_rc_init_hw(void)
+{
+	s3c_gpio_cfgpin(GPIO_IRDA_CONTROL, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_IRDA_CONTROL, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_IRDA_CONTROL, 0);
+}
+#endif
+
+#if defined(CONFIG_MACH_P8LTE) || defined(CONFIG_MACH_P8)
+static void ir_rc_init_hw(void)
+{
+	s3c_gpio_cfgpin(GPIO_IRDA_nINT, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_IRDA_nINT, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_IRDA_nINT, 0);
+
+	s3c_gpio_cfgpin(GPIO_IRDA_EN, S3C_GPIO_OUTPUT);
+	S3C_gpio_setpull(GPIO_IRDA_EN, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_IRDA_EN, 0);
+}
+#endif
+
+#endif
+/* IR_LED */
+
+#ifdef CONFIG_BATTERY_SAMSUNG
+static struct platform_device samsung_device_battery = {
+	.name = "samsung-fake-battery",
+	.id = -1,
+};
+#endif
+
+
+
+#if defined(CONFIG_SEC_THERMISTOR)
+static struct sec_therm_platform_data sec_therm_pdata = {
+	.adc_channel	= 7,
+	.adc_arr_size	= ARRAY_SIZE(adc_temp_table),
+	.adc_table	= adc_temp_table,
+	.polling_interval = 60 * 1000, /* msecs */
+};
+
+static struct platform_device sec_device_thermistor = {
+	.name = "sec-thermistor",
+	.id = -1,
+	.dev.platform_data = &sec_therm_pdata,
+};
+#endif /* CONFIG_SEC_THERMISTOR */
+
+#ifdef CONFIG_KEYBOARD_GPIO
+#define GPIO_KEYS(_code, _gpio, _active_low, _iswake, _hook)		\
+{					\
+	.code = _code,			\
+	.gpio = _gpio,	\
+	.active_low = _active_low,		\
+	.type = EV_KEY,			\
+	.wakeup = _iswake,		\
+	.debounce_interval = 10,	\
+	.isr_hook = _hook			\
+}
+
+struct gpio_keys_button px_buttons[] = {
+	GPIO_KEYS(KEY_VOLUMEUP, GPIO_VOL_UP,
+		1, 0, sec_debug_check_crash_key),
+	GPIO_KEYS(KEY_VOLUMEDOWN, GPIO_VOL_DOWN,
+		1, 0, sec_debug_check_crash_key),
+	GPIO_KEYS(KEY_POWER, GPIO_nPOWER,
+		1, 1, sec_debug_check_crash_key),
+};
+
+struct gpio_keys_platform_data px_keys_platform_data = {
+	.buttons	= px_buttons,
+	.nbuttons	 = ARRAY_SIZE(px_buttons),
+};
+
+struct platform_device px_gpio_keys = {
+	.name	= "gpio-keys",
+	.dev.platform_data = &px_keys_platform_data,
+};
+#endif
+
+#ifdef CONFIG_SEC_DEV_JACK
+static void sec_set_jack_micbias(bool on)
+{
+#ifdef CONFIG_MACH_P8
+		gpio_set_value(GPIO_EAR_MIC_BIAS_EN, on);
+#else
+	if (system_rev >= 3)
+		gpio_set_value(GPIO_EAR_MIC_BIAS_EN, on);
+	else
+		gpio_set_value(GPIO_MIC_BIAS_EN, on);
+#endif
+}
+
+static struct sec_jack_zone sec_jack_zones[] = {
+	{
+		/* adc == 0, unstable zone, default to 3pole if it stays
+		 * in this range for 300ms (15ms delays, 20 samples)
+		 */
+		.adc_high = 0,
+		.delay_ms = 15,
+		.check_count = 20,
+		.jack_type = SEC_HEADSET_3POLE,
+	},
+	{
+		/* 0 < adc <= 1200, unstable zone, default to 3pole if it stays
+		 * in this range for 300ms (15ms delays, 20 samples)
+		 */
+		.adc_high = 1200,
+		.delay_ms = 10,
+		.check_count = 80,
+		.jack_type = SEC_HEADSET_3POLE,
+	},
+	{
+		/* 950 < adc <= 2600, unstable zone, default to 4pole if it
+		 * stays in this range for 800ms (10ms delays, 80 samples)
+		 */
+		.adc_high = 2600,
+		.delay_ms = 10,
+		.check_count = 10,
+		.jack_type = SEC_HEADSET_4POLE,
+	},
+	{
+		/* 2600 < adc <= 3400, 3 pole zone, default to 3pole if it
+		 * stays in this range for 100ms (10ms delays, 10 samples)
+		 */
+		.adc_high = 3800,
+		.delay_ms = 10,
+		.check_count = 5,
+		.jack_type = SEC_HEADSET_4POLE,
+	},
+	{
+		/* adc > 3400, unstable zone, default to 3pole if it stays
+		 * in this range for two seconds (10ms delays, 200 samples)
+		 */
+		.adc_high = 0x7fffffff,
+		.delay_ms = 10,
+		.check_count = 200,
+		.jack_type = SEC_HEADSET_3POLE,
+	},
+};
+
+/* To support 3-buttons earjack */
+static struct sec_jack_buttons_zone sec_jack_buttons_zones[] = {
+	{
+		/* 0 <= adc <=170, stable zone */
+		.code = KEY_MEDIA,
+		.adc_low = 0,
+		.adc_high = 170,
+	},
+	{
+		/* 171 <= adc <= 370, stable zone */
+		.code = KEY_VOLUMEUP,
+		.adc_low = 171,
+		.adc_high = 370,
+	},
+	{
+		/* 371 <= adc <= 850, stable zone */
+		.code = KEY_VOLUMEDOWN,
+		.adc_low = 371,
+		.adc_high = 850,
+	},
+};
+
+static struct sec_jack_platform_data sec_jack_data = {
+	.set_micbias_state = sec_set_jack_micbias,
+	.zones = sec_jack_zones,
+	.num_zones = ARRAY_SIZE(sec_jack_zones),
+	.buttons_zones = sec_jack_buttons_zones,
+	.num_buttons_zones = ARRAY_SIZE(sec_jack_buttons_zones),
+	.det_gpio = GPIO_DET_35,
+	.send_end_gpio = GPIO_EAR_SEND_END,
+};
+
+static struct platform_device sec_device_jack = {
+	.name = "sec_jack",
+	.id = 1,		/* will be used also for gpio_event id */
+	.dev.platform_data = &sec_jack_data,
+};
+#endif
+
+#ifdef CONFIG_TOUCHSCREEN_MMS152
+static struct tsp_callbacks *charger_cbs;
+
+static void sec_charger_melfas_cb(bool en)
+{
+	if (charger_cbs && charger_cbs->inform_charger)
+		charger_cbs->inform_charger(charger_cbs, en);
+
+	printk(KERN_DEBUG "[TSP] %s - %s\n", __func__,
+		en ? "on" : "off");
+}
+static void register_tsp_callbacks(struct tsp_callbacks *cb)
+{
+	charger_cbs = cb;
+}
+
+static void ts_power_on(void)
+{
+/*	s3c_gpio_cfgpin(GPIO_TSP_RST, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TSP_RST, S3C_GPIO_PULL_NONE);
+*/
+	gpio_set_value(GPIO_TSP_RST, GPIO_LEVEL_HIGH);
+	msleep(70);
+	s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_NONE);
+	s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_SFN(0xf));
+	pr_info("[TSP] TSP POWER ON\n");
+}
+
+static void ts_power_off(void)
+{
+	s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_NONE);
+
+/*	s3c_gpio_cfgpin(GPIO_TSP_RST, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TSP_RST, S3C_GPIO_PULL_NONE);
+*/
+	gpio_set_value(GPIO_TSP_RST, GPIO_LEVEL_LOW);
+	pr_info("[TSP] TSP POWER OFF");
+}
+
+static void ts_read_ta_status(bool *ta_status)
+{
+	*ta_status = is_cable_attached;
+}
+
+static void ts_set_touch_i2c(void)
+{
+	s3c_gpio_cfgpin(GPIO_TSP_SDA, S3C_GPIO_SFN(3));
+	s3c_gpio_setpull(GPIO_TSP_SDA, S3C_GPIO_PULL_UP);
+	s3c_gpio_cfgpin(GPIO_TSP_SCL, S3C_GPIO_SFN(3));
+	s3c_gpio_setpull(GPIO_TSP_SCL, S3C_GPIO_PULL_UP);
+	gpio_free(GPIO_TSP_SDA);
+	gpio_free(GPIO_TSP_SCL);
+}
+
+static void ts_set_touch_i2c_to_gpio(void)
+{
+
+	s3c_gpio_cfgpin(GPIO_TSP_SDA, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TSP_SDA, S3C_GPIO_PULL_UP);
+	s3c_gpio_cfgpin(GPIO_TSP_SCL, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TSP_SCL, S3C_GPIO_PULL_UP);
+	gpio_request(GPIO_TSP_SDA, "GPIO_TSP_SDA");
+	gpio_request(GPIO_TSP_SCL, "GPIO_TSP_SCL");
+
+}
+
+static struct ts_platform_data ts_data = {
+	.gpio_read_done = GPIO_TSP_INT,
+	.gpio_int = GPIO_TSP_INT,
+	.power_on = ts_power_on,
+	.power_off = ts_power_off,
+	.register_cb = register_tsp_callbacks,
+	.read_ta_status = ts_read_ta_status,
+	.set_touch_i2c = ts_set_touch_i2c,
+	.set_touch_i2c_to_gpio = ts_set_touch_i2c_to_gpio,
+};
+
+#endif /* ifdef CONFIG_TOUCHSCREEN_MMS152 */
+
+#ifdef CONFIG_TOUCHSCREEN_ATMEL_MXT224_U1
+static void mxt224_power_on(void)
+{
+	s3c_gpio_cfgpin(GPIO_TSP_LDO_ON, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TSP_LDO_ON, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TSP_LDO_ON, 1);
+	mdelay(70);
+	s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_NONE);
+	s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_SFN(0xf));
+	mdelay(40);
+	/* printk("mxt224_power_on is finished\n"); */
+}
+
+static void mxt224_power_off(void)
+{
+	s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_DOWN);
+
+	s3c_gpio_cfgpin(GPIO_TSP_LDO_ON, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TSP_LDO_ON, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TSP_LDO_ON, 0);
+	/* printk("mxt224_power_off is finished\n"); */
+}
+
+#if defined(CONFIG_MACH_U1Q1_REV02)
+|| defined(CONFIG_MACH_Q1_REV00) || defined(CONFIG_MACH_Q1_REV02)
+static u8 t7_config[] = { GEN_POWERCONFIG_T7,
+	64, 255, 20
+};
+
+static u8 t8_config[] = { GEN_ACQUISITIONCONFIG_T8,
+	36, 0, 20, 20, 0, 0, 10, 10, 50, 25
+};
+
+static u8 t9_config[] = { TOUCH_MULTITOUCHSCREEN_T9,
+	139, 0, 0, 18, 11, 0, 16, MXT224_THRESHOLD, 2, 1, 0, 3, 1,
+	0, MXT224_MAX_MT_FINGERS, 10, 10, 10, 31, 3,
+	223, 1, 0, 0, 0, 0, 0, 0, 0, 0, 10, 5, 5, 5
+};
+
+static u8 t15_config[] = { TOUCH_KEYARRAY_T15,
+	131, 16, 11, 2, 1, 0, 0, 40, 3, 0, 0
+};
+
+static u8 t18_config[] = { SPT_COMCONFIG_T18,
+	0, 0
+};
+
+static u8 t48_config[] = { PROCG_NOISESUPPRESSION_T48,
+	3, 0, 2, 10, 6, 12, 18, 24, 20, 30, 0, 0, 0, 0,
+	0, 0, 0
+};
+
+static u8 t46_config[] = { SPT_CTECONFIG_T46,
+	0, 2, 0, 0, 0, 0, 0
+};
+static u8 end_config[] = { RESERVED_T255 };
+
+static const u8 *mxt224_config[] = {
+	t7_config,
+	t8_config,
+	t9_config,
+	t15_config,
+	t18_config,
+	t46_config,
+	t48_config,
+	end_config,
+};
+#else
+/*
+  Configuration for MXT224
+*/
+static u8 t7_config[] = { GEN_POWERCONFIG_T7,
+	48,			/* IDLEACQINT */
+	255,			/* ACTVACQINT */
+	25			/* ACTV2IDLETO: 25 * 200ms = 5s */
+};
+
+static u8 t8_config[] = { GEN_ACQUISITIONCONFIG_T8,
+	10, 0, 5, 1, 0, 0, 9, 30
+};				/*byte 3: 0 */
+
+static u8 t9_config[] = { TOUCH_MULTITOUCHSCREEN_T9,
+	131, 0, 0, 19, 11, 0, 32, MXT224_THRESHOLD, 2, 1,
+	0,
+	15,			/* MOVHYSTI */
+	1, 11, MXT224_MAX_MT_FINGERS, 5, 40, 10, 31, 3,
+	223, 1, 0, 0, 0, 0, 143, 55, 143, 90, 18
+};
+
+static u8 t18_config[] = { SPT_COMCONFIG_T18,
+	0, 1
+};
+
+static u8 t20_config[] = { PROCI_GRIPFACESUPPRESSION_T20,
+	7, 0, 0, 0, 0, 0, 0, 30, 20, 4, 15, 10
+};
+
+static u8 t22_config[] = { PROCG_NOISESUPPRESSION_T22,
+	143, 0, 0, 0, 0, 0, 0, 3, 30, 0, 0, 29, 34, 39,
+	49, 58, 3
+};
+
+static u8 t28_config[] = { SPT_CTECONFIG_T28,
+			   0, 0, 3, 16, 19, 60
+};
+static u8 end_config[] = { RESERVED_T255 };
+
+static const u8 *mxt224_config[] = {
+	t7_config,
+	t8_config,
+	t9_config,
+	t18_config,
+	t20_config,
+	t22_config,
+	t28_config,
+	end_config,
+};
+
+/*
+  Configuration for MXT224-E
+*/
+#if defined(CONFIG_TARGET_LOCALE_NAATT)
+static u8 t7_config_e[] = { GEN_POWERCONFIG_T7,
+	48, 255, 25
+};
+
+static u8 t8_config_e[] = { GEN_ACQUISITIONCONFIG_T8,
+	27, 0, 5, 1, 0, 0, 8, 8, 8, 180
+};
+
+/* MXT224E_0V5_CONFIG */
+/* NEXTTCHDI added */
+static u8 t9_config_e[] = { TOUCH_MULTITOUCHSCREEN_T9,
+	139, 0, 0, 19, 11, 0, 32, 50, 2, 1,
+	10, 3, 1, 11, MXT224_MAX_MT_FINGERS, 5, 40, 10, 31, 3,
+	223, 1, 10, 10, 10, 10, 143, 40, 143, 80,
+	18, 15, 50, 50, 2
+};
+
+static u8 t15_config_e[] = { TOUCH_KEYARRAY_T15,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t18_config_e[] = { SPT_COMCONFIG_T18,
+	0, 0
+};
+
+static u8 t23_config_e[] = { TOUCH_PROXIMITY_T23,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t25_config_e[] = { SPT_SELFTEST_T25,
+	0, 0, 188, 52, 124, 21, 188, 52, 124, 21, 0, 0, 0, 0
+};
+
+static u8 t40_config_e[] = { PROCI_GRIPSUPPRESSION_T40,
+	0, 0, 0, 0, 0
+};
+
+static u8 t42_config_e[] = { PROCI_TOUCHSUPPRESSION_T42,
+	0, 32, 120, 100, 0, 0, 0, 0
+};
+
+static u8 t46_config_e[] = { SPT_CTECONFIG_T46,
+	0, 3, 16, 35, 0, 0, 1, 0
+};
+
+static u8 t47_config_e[] = { PROCI_STYLUS_T47,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*MXT224E_0V5_CONFIG */
+static u8 t48_config_e[] = { PROCG_NOISESUPPRESSION_T48,
+	3, 4, 72, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	6, 6, 0, 0, 100, 4, 64, 10, 0, 20, 5, 0, 38, 0, 5,
+	0, 0, 0, 0, 0, 0, 32, 50, 2, 3, 1, 11, 10, 5, 40, 10, 10,
+	10, 10, 143, 40, 143, 80, 18, 15, 2
+};
+
+static u8 t48_config_e_ta[] = { PROCG_NOISESUPPRESSION_T48,
+	1, 4, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	6, 6, 0, 0, 100, 4, 64, 10, 0, 20, 5, 0, 38, 0, 20,
+	0, 0, 0, 0, 0, 0, 16, 70, 2, 5, 2, 46, 10, 5, 40, 10, 0,
+	10, 10, 143, 40, 143, 80, 18, 15, 2
+};
+
+#elif defined(CONFIG_MACH_U1_NA_SPR_EPIC2_REV00)
+static u8 t7_config_e[] = { GEN_POWERCONFIG_T7,
+	48, 255, 15
+};
+
+static u8 t8_config_e[] = { GEN_ACQUISITIONCONFIG_T8,
+	27, 0, 5, 1, 0, 0, 4, 35, 40, 55
+};
+
+static u8 t9_config_e[] = { TOUCH_MULTITOUCHSCREEN_T9,
+	131, 0, 0, 19, 11, 0, 32, 50, 2, 7,
+	10, 3, 1, 46, MXT224_MAX_MT_FINGERS, 5, 40, 10, 31, 3,
+	223, 1, 10, 10, 10, 10, 143, 40, 143, 80,
+	18, 15, 50, 50, 2
+};
+
+static u8 t15_config_e[] = { TOUCH_KEYARRAY_T15,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t18_config_e[] = { SPT_COMCONFIG_T18,
+	0, 0
+};
+
+static u8 t23_config_e[] = { TOUCH_PROXIMITY_T23,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t25_config_e[] = { SPT_SELFTEST_T25,
+	0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t40_config_e[] = { PROCI_GRIPSUPPRESSION_T40,
+	0, 0, 0, 0, 0
+};
+
+static u8 t42_config_e[] = { PROCI_TOUCHSUPPRESSION_T42,
+	0, 32, 120, 100, 0, 0, 0, 0
+};
+
+static u8 t46_config_e[] = { SPT_CTECONFIG_T46,
+	0, 3, 16, 48, 0, 0, 1, 0, 0
+};
+
+static u8 t47_config_e[] = { PROCI_STYLUS_T47,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t48_config_e[] = { PROCG_NOISESUPPRESSION_T48,
+	3, 4, 64, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 6, 6, 0, 0, 100, 4, 64,
+	10, 0, 20, 5, 0, 38, 0, 5, 0, 0,
+	0, 0, 0, 0, 32, 50, 2, 3, 1, 46,
+	10, 5, 40, 10, 10, 10, 10, 143, 40, 143,
+	80, 18, 15, 2
+};
+
+static u8 t48_config_e_ta[] = { PROCG_NOISESUPPRESSION_T48,
+	1, 4, 80, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 6, 6, 0, 0, 100, 4, 64,
+	10, 0, 20, 5, 0, 38, 0, 20, 0, 0,
+	0, 0, 0, 0, 16, 70, 2, 5, 2, 46,
+	10, 5, 40, 10, 0, 10, 10, 143, 40, 143,
+	80, 18, 15, 2
+};
+#else
+
+static u8 t7_config_e[] = { GEN_POWERCONFIG_T7,
+	48,			/* IDLEACQINT */
+	255,			/* ACTVACQINT */
+	25			/* ACTV2IDLETO: 25 * 200ms = 5s */
+};
+
+static u8 t8_config_e[] = { GEN_ACQUISITIONCONFIG_T8,
+	27, 0, 5, 1, 0, 0, 4, 35, 40, 55
+};
+
+#if 1				/* MXT224E_0V5_CONFIG */
+/* NEXTTCHDI added */
+#ifdef CONFIG_TARGET_LOCALE_NA
+#ifdef CONFIG_MACH_U1_NA_USCC_REV05
+static u8 t9_config_e[] = { TOUCH_MULTITOUCHSCREEN_T9,
+	139, 0, 0, 19, 11, 0, 32, 50, 2, 1,
+	10,
+	10,			/* MOVHYSTI */
+	1, 46, MXT224_MAX_MT_FINGERS, 5, 40, 10, 31, 3,
+	223, 1, 10, 10, 10, 10, 143, 40, 143, 80,
+	18, 15, 50, 50, 0
+};
+
+#else
+static u8 t9_config_e[] = { TOUCH_MULTITOUCHSCREEN_T9,
+	139, 0, 0, 19, 11, 0, 32, 50, 2, 1,
+	10,
+	10,			/* MOVHYSTI */
+	1, 46, MXT224_MAX_MT_FINGERS, 5, 40, 10, 31, 3,
+	223, 1, 10, 10, 10, 10, 143, 40, 143, 80,
+	18, 15, 50, 50, 2
+};
+#endif
+#else
+static u8 t9_config_e[] = { TOUCH_MULTITOUCHSCREEN_T9,
+	139, 0, 0, 19, 11, 0, 32, 50, 2, 1,
+	10,
+	15,			/* MOVHYSTI */
+	1, 46, MXT224_MAX_MT_FINGERS, 5, 40, 10, 31, 3,
+	223, 1, 10, 10, 10, 10, 143, 40, 143, 80,
+	18, 15, 50, 50, 0
+};
+#endif
+#else
+static u8 t9_config_e[] = { TOUCH_MULTITOUCHSCREEN_T9,
+	139, 0, 0, 19, 11, 0, 16, MXT224_THRESHOLD, 2, 1, 10, 3, 1,
+	0, MXT224_MAX_MT_FINGERS, 10, 40, 10, 31, 3,
+	223, 1, 10, 10, 10, 10, 143, 40, 143, 80, 18, 15, 50, 50
+};
+#endif
+
+static u8 t15_config_e[] = { TOUCH_KEYARRAY_T15,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t18_config_e[] = { SPT_COMCONFIG_T18,
+	0, 0
+};
+
+static u8 t23_config_e[] = { TOUCH_PROXIMITY_T23,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t25_config_e[] = { SPT_SELFTEST_T25,
+	0, 0, 0, 0, 0, 0, 0, 0
+};
+
+#ifdef CONFIG_MACH_U1_NA_USCC_REV05
+static u8 t38_config_e[] = { SPT_USERDATA_T38,
+	0, 1, 13, 19, 44, 0, 0, 0
+};
+#else
+static u8 t38_config_e[] = { SPT_USERDATA_T38,
+	0, 1, 14, 23, 44, 0, 0, 0
+};
+#endif
+
+static u8 t40_config_e[] = { PROCI_GRIPSUPPRESSION_T40,
+	0, 0, 0, 0, 0
+};
+
+static u8 t42_config_e[] = { PROCI_TOUCHSUPPRESSION_T42,
+	0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t46_config_e[] = { SPT_CTECONFIG_T46,
+	0, 3, 16, 40, 0, 0, 1, 0, 0
+};
+
+static u8 t47_config_e[] = { PROCI_STYLUS_T47,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*MXT224E_0V5_CONFIG */
+#ifdef CONFIG_TARGET_LOCALE_NA
+#ifdef CONFIG_MACH_U1_NA_USCC_REV05
+static u8 t48_config_e_ta[] = { PROCG_NOISESUPPRESSION_T48,
+	3, 132, 0x52, 0, 0, 0, 0, 0, 10, 15,
+	0, 0, 0, 6, 6, 0, 0, 64, 4, 64,
+	10, 0, 10, 5, 0, 19, 0, 20, 0, 0,
+	0, 0, 0, 0, 0, 40, 2,	/*blen=0,threshold=50 */
+	10,			/* MOVHYSTI */
+	1, 47,
+	10, 5, 40, 240, 245, 10, 10, 148, 50, 143,
+	80, 18, 10, 0
+};
+
+static u8 t48_config_e[] = { PROCG_NOISESUPPRESSION_T48,
+	3, 132, 0x40, 0, 0, 0, 0, 0, 10, 15,
+	0, 0, 0, 6, 6, 0, 0, 64, 4, 64,
+	10, 0, 20, 5, 0, 38, 0, 5, 0, 0,	/*byte 27 original value 20 */
+	0, 0, 0, 0, 32, MXT224E_THRESHOLD, 2,
+	10,
+	1, 46,
+	MXT224_MAX_MT_FINGERS, 5, 40, 10, 0, 10, 10, 143, 40, 143,
+	80, 18, 15, 0
+};
+#else
+static u8 t48_config_e_ta[] = { PROCG_NOISESUPPRESSION_T48,
+	1, 4, 0x50, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 6, 6, 0, 0, 100, 4, 64,
+	10, 0, 20, 5, 0, 38, 0, 20, 0, 0,
+	0, 0, 0, 0, 0, 40, 2,	/*blen=0,threshold=50 */
+	10,			/* MOVHYSTI */
+	1, 15,
+	10, 5, 40, 240, 245, 10, 10, 148, 50, 143,
+	80, 18, 10, 2
+};
+
+static u8 t48_config_e[] = { PROCG_NOISESUPPRESSION_T48,
+	1, 4, 0x40, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 6, 6, 0, 0, 100, 4, 64,
+	10, 0, 20, 5, 0, 38, 0, 5, 0, 0,	/*byte 27 original value 20 */
+	0, 0, 0, 0, 32, 50, 2,
+	10,
+	1, 46,
+	MXT224_MAX_MT_FINGERS, 5, 40, 10, 0, 10, 10, 143, 40, 143,
+	80, 18, 15, 2
+};
+#endif				/*CONFIG_MACH_U1_NA_USCC_REV05 */
+#else
+static u8 t48_config_e_ta[] = { PROCG_NOISESUPPRESSION_T48,
+	3, 132, 0x52, 0, 0, 0, 0, 0, 10, 15,
+	0, 0, 0, 6, 6, 0, 0, 64, 4, 64,
+	10, 0, 9, 5, 0, 15, 0, 20, 0, 0,
+	0, 0, 0, 0, 0, 40, 2,	/*blen=0,threshold=50 */
+	15,			/* MOVHYSTI */
+	1, 47,
+	10, 5, 40, 235, 235, 10, 10, 160, 50, 143,
+	80, 18, 10, 0
+};
+
+static u8 t48_config_e[] = { PROCG_NOISESUPPRESSION_T48,
+	3, 132, 0x40, 0, 0, 0, 0, 0, 10, 15,
+	0, 0, 0, 6, 6, 0, 0, 64, 4, 64,
+	10, 0, 20, 5, 0, 38, 0, 5, 0, 0,	/*byte 27 original value 20 */
+	0, 0, 0, 0, 32, MXT224E_THRESHOLD, 2,
+	15,
+	1, 46,
+	MXT224_MAX_MT_FINGERS, 5, 40, 10, 10, 10, 10, 143, 40, 143,
+	80, 18, 15, 0
+};
+#endif				/*CONFIG_TARGET_LOCALE_NA */
+#endif				/*CONFIG_TARGET_LOCALE_NAATT */
+
+static u8 end_config_e[] = { RESERVED_T255 };
+
+static const u8 *mxt224e_config[] = {
+	t7_config_e,
+	t8_config_e,
+	t9_config_e,
+	t15_config_e,
+	t18_config_e,
+	t23_config_e,
+	t25_config_e,
+	t38_config_e,
+	t40_config_e,
+	t42_config_e,
+	t46_config_e,
+	t47_config_e,
+	t48_config_e,
+	end_config_e,
+};
+#endif
+
+static struct mxt224_platform_data mxt224_data = {
+	.max_finger_touches = MXT224_MAX_MT_FINGERS,
+	.gpio_read_done = GPIO_TSP_INT,
+#if defined(CONFIG_MACH_U1Q1_REV02)
+|| defined(CONFIG_MACH_Q1_REV00) || defined(CONFIG_MACH_Q1_REV02)
+	.config = mxt224_config,
+#else
+	.config = mxt224_config,
+	.config_e = mxt224e_config,
+	.t48_ta_cfg = t48_config_e_ta,
+#endif
+	.min_x = 0,
+	.max_x = 479,
+	.min_y = 0,
+	.max_y = 799,
+	.min_z = 0,
+	.max_z = 255,
+	.min_w = 0,
+	.max_w = 30,
+	.power_on = mxt224_power_on,
+	.power_off = mxt224_power_off,
+};
+
+#endif				/*CONFIG_TOUCHSCREEN_ATMEL_MXT224_U1 */
+
+#if defined(CONFIG_TOUCHSCREEN_MXT540E)
+
+void tsp_register_callback(void *function)
+{
+	charging_cbs.tsp_set_charging_cable = function;
+}
+
+void tsp_read_ta_status(bool *ta_status)
+{
+	*ta_status = is_cable_attached;
+}
+
+static void mxt540e_power_on(void)
+{
+	s3c_gpio_cfgpin(GPIO_TSP_LDO_ON, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TSP_LDO_ON, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TSP_LDO_ON, GPIO_LEVEL_HIGH);
+	msleep(MXT540E_HW_RESET_TIME);
+	s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_NONE);
+	s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_SFN(0xf));
+}
+
+static void mxt540e_power_off(void)
+{
+	s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_DOWN);
+
+	s3c_gpio_cfgpin(GPIO_TSP_LDO_ON, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TSP_LDO_ON, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TSP_LDO_ON, GPIO_LEVEL_LOW);
+}
+
+/*
+  Configuration for MXT540E
+*/
+#define MXT540E_MAX_MT_FINGERS		10
+#define MXT540E_CHRGTIME_BATT		68
+#define MXT540E_CHRGTIME_CHRG		60
+#define MXT540E_THRESHOLD_BATT		50
+#define MXT540E_THRESHOLD_CHRG		60
+#define MXT540E_ACTVSYNCSPERX_BATT		36
+#define MXT540E_ACTVSYNCSPERX_CHRG		24
+#define MXT540E_CALCFG_BATT		64
+#define MXT540E_CALCFG_CHRG		80
+#define MXT540E_ATCHFRCCALTHR_WAKEUP		8
+#define MXT540E_ATCHFRCCALRATIO_WAKEUP		180
+#define MXT540E_ATCHFRCCALTHR_NORMAL		40
+#define MXT540E_ATCHFRCCALRATIO_NORMAL		55
+
+static u8 t7_config_e[] = { GEN_POWERCONFIG_T7,
+	48, 255, 50
+};
+
+static u8 t8_config_e[] = { GEN_ACQUISITIONCONFIG_T8,
+	MXT540E_CHRGTIME_BATT, 0, 5, 1, 0, 0, 4, 30,
+	MXT540E_ATCHFRCCALTHR_WAKEUP, MXT540E_ATCHFRCCALRATIO_WAKEUP
+};
+
+static u8 t9_config_e[] = { TOUCH_MULTITOUCHSCREEN_T9,
+	131, 0, 0, 16, 26, 0, 176, MXT540E_THRESHOLD_BATT, 2, 6, 10, 10, 1,
+	47, MXT540E_MAX_MT_FINGERS, 5, 20, 20, 31, 3,
+	255, 4, 253, 3, 254, 2, 136, 60, 136, 40, 18, 12, 0, 0, 2
+};
+
+static u8 t15_config_e[] = { TOUCH_KEYARRAY_T15,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t18_config_e[] = { SPT_COMCONFIG_T18,
+	0, 0
+};
+
+static u8 t19_config_e[] = { SPT_GPIOPWM_T19,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t24_config_e[] = { PROCI_ONETOUCHGESTUREPROCESSOR_T24,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t25_config_e[] = { SPT_SELFTEST_T25,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t27_config_e[] = { PROCI_TWOTOUCHGESTUREPROCESSOR_T27,
+	0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t40_config_e[] = { PROCI_GRIPSUPPRESSION_T40,
+	0, 0, 0, 0, 0
+};
+
+static u8 t42_config_e[] = { PROCI_TOUCHSUPPRESSION_T42,
+	0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t43_config_e[] = { SPT_DIGITIZER_T43,
+	0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t46_config_e[] = { SPT_CTECONFIG_T46,
+	0, 0, 24, MXT540E_ACTVSYNCSPERX_BATT, 0, 0, 1, 0
+};
+
+static u8 t47_config_e[] = { PROCI_STYLUS_T47,
+	0, 30, 60, 15, 2, 20, 20, 150, 0, 32
+};
+
+static u8 t48_config_e[] = { PROCG_NOISESUPPRESSION_T48,
+	1, 132, MXT540E_CALCFG_BATT, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	6, 6, 0, 0, 100, 4, 64, 10, 0, 20, 6, 0, 46, 0, 1,
+	0, 0, 0, 0, 0, 0, 176, MXT540E_THRESHOLD_BATT, 2, 10, 1, 47,
+	MXT540E_MAX_MT_FINGERS, 5, 20, 253, 3,
+	254, 2, 136, 60, 136, 40, 18, 12, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t48_config_chrg_e[] = { PROCG_NOISESUPPRESSION_T48,
+	1, 132, MXT540E_CALCFG_CHRG, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	6, 6, 0, 0, 100, 4, 64, 10, 0, 20, 10, 0, 46, 0, 10,
+	0, 0, 0, 0, 0, 0, 128, MXT540E_THRESHOLD_CHRG, 2, 10, 1, 0,
+	MXT540E_MAX_MT_FINGERS, 5, 20, 240, 240,
+	10, 10, 138, 70, 132, 0, 18, 15, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t52_config_e[] = { TOUCH_PROXKEY_T52,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 end_config_e[] = { RESERVED_T255 };
+
+static const u8 *mxt540e_config[] = {
+	t7_config_e,
+	t8_config_e,
+	t9_config_e,
+	t15_config_e,
+	t18_config_e,
+	t19_config_e,
+	t24_config_e,
+	t25_config_e,
+	t27_config_e,
+	t40_config_e,
+	t42_config_e,
+	t43_config_e,
+	t46_config_e,
+	t47_config_e,
+	t48_config_e,
+	t52_config_e,
+	end_config_e,
+};
+
+struct mxt540e_platform_data mxt540e_data = {
+	.max_finger_touches = MXT540E_MAX_MT_FINGERS,
+	.gpio_read_done = GPIO_TSP_INT,
+	.config_e = mxt540e_config,
+	.min_x = 0,
+	.max_x = 799,
+	.min_y = 0,
+	.max_y = 1279,
+	.min_z = 0,
+	.max_z = 255,
+	.min_w = 0,
+	.max_w = 30,
+	.chrgtime_batt = MXT540E_CHRGTIME_BATT,
+	.chrgtime_charging = MXT540E_CHRGTIME_CHRG,
+	.tchthr_batt = MXT540E_THRESHOLD_BATT,
+	.tchthr_charging = MXT540E_THRESHOLD_CHRG,
+	.actvsyncsperx_batt = MXT540E_ACTVSYNCSPERX_BATT,
+	.actvsyncsperx_charging = MXT540E_ACTVSYNCSPERX_CHRG,
+	.calcfg_batt_e = MXT540E_CALCFG_BATT,
+	.calcfg_charging_e = MXT540E_CALCFG_CHRG,
+	.atchfrccalthr_e = MXT540E_ATCHFRCCALTHR_NORMAL,
+	.atchfrccalratio_e = MXT540E_ATCHFRCCALRATIO_NORMAL,
+	.t48_config_batt_e = t48_config_e,
+	.t48_config_chrg_e = t48_config_chrg_e,
+	.power_on = mxt540e_power_on,
+	.power_off = mxt540e_power_off,
+	.register_cb = tsp_register_callback,
+	.read_ta_status = tsp_read_ta_status,
+};
+#endif
+
+#if defined(CONFIG_TOUCHSCREEN_MXT768E)
+
+static void ts_power_on(void)
+{
+	s3c_gpio_cfgpin(GPIO_TSP_LDO_ON, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TSP_LDO_ON, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TSP_LDO_ON, GPIO_LEVEL_HIGH);
+	msleep(70);
+	s3c_gpio_setpull(GPIO_TSP_INT_18V, S3C_GPIO_PULL_NONE);
+	s3c_gpio_cfgpin(GPIO_TSP_INT_18V, S3C_GPIO_SFN(0xf));
+	msleep(40);
+	printk(KERN_DEBUG"mxt_power_on is finished\n");
+
+}
+
+static void ts_power_off(void)
+{
+	s3c_gpio_cfgpin(GPIO_TSP_INT_18V, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_TSP_INT_18V, S3C_GPIO_PULL_DOWN);
+
+	s3c_gpio_cfgpin(GPIO_TSP_LDO_ON, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TSP_LDO_ON, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TSP_LDO_ON, GPIO_LEVEL_LOW);
+	printk(KERN_DEBUG"mxt_power_off is finished\n");
+}
+
+static void ts_register_callback(void *function)
+{
+	printk(KERN_DEBUG"mxt_register_callback\n");
+	charging_cbs.tsp_set_charging_cable = function;
+}
+
+static void ts_read_ta_status(bool *ta_status)
+{
+	*ta_status = is_cable_attached;
+}
+/*
+	Configuration for MXT768-E
+*/
+#define MXT768E_MAX_MT_FINGERS		10
+#define MXT768E_CHRGTIME_BATT		64
+#define MXT768E_CHRGTIME_CHRG		64
+#define MXT768E_THRESHOLD_BATT		50
+#define MXT768E_THRESHOLD_CHRG		48
+#define MXT768E_CALCFG_BATT		210
+#define MXT768E_CALCFG_CHRG		242
+
+#define MXT768E_ATCHCALSTHR_NORMAL			50
+#define MXT768E_ATCHFRCCALTHR_NORMAL		50
+#define MXT768E_ATCHFRCCALRATIO_NORMAL		0
+#define MXT768E_ATCHFRCCALTHR_WAKEUP		8
+#define MXT768E_ATCHFRCCALRATIO_WAKEUP		136
+
+#define MXT768E_IDLESYNCSPERX_BATT		38
+#define MXT768E_IDLESYNCSPERX_CHRG		40
+#define MXT768E_ACTVSYNCSPERX_BATT		38
+#define MXT768E_ACTVSYNCSPERX_CHRG		40
+
+#define MXT768E_IDLEACQINT_BATT			24
+#define MXT768E_IDLEACQINT_CHRG			24
+#define MXT768E_ACTACQINT_BATT			255
+#define MXT768E_ACTACQINT_CHRG			255
+
+#define MXT768E_XLOCLIP_BATT		0
+#define MXT768E_XLOCLIP_CHRG		12
+#define MXT768E_XHICLIP_BATT		0
+#define MXT768E_XHICLIP_CHRG		12
+#define MXT768E_YLOCLIP_BATT		0
+#define MXT768E_YLOCLIP_CHRG		5
+#define MXT768E_YHICLIP_BATT		0
+#define MXT768E_YHICLIP_CHRG		5
+#define MXT768E_XEDGECTRL_BATT		136
+#define MXT768E_XEDGECTRL_CHRG		128
+#define MXT768E_XEDGEDIST_BATT		50
+#define MXT768E_XEDGEDIST_CHRG		0
+#define MXT768E_YEDGECTRL_BATT		136
+#define MXT768E_YEDGECTRL_CHRG		136
+#define MXT768E_YEDGEDIST_BATT		40
+#define MXT768E_YEDGEDIST_CHRG		30
+#define MXT768E_TCHHYST_BATT			15
+#define MXT768E_TCHHYST_CHRG			15
+
+
+static u8 t7_config_e[] = { GEN_POWERCONFIG_T7,
+	MXT768E_IDLEACQINT_BATT, MXT768E_ACTACQINT_BATT, 7
+};
+
+static u8 t8_config_e[] = { GEN_ACQUISITIONCONFIG_T8,
+	MXT768E_CHRGTIME_BATT, 0, 5, 1, 0, 0, 4,
+	MXT768E_ATCHCALSTHR_NORMAL,
+	MXT768E_ATCHFRCCALTHR_WAKEUP,
+	MXT768E_ATCHFRCCALRATIO_WAKEUP
+};
+
+static u8 t9_config_e[] = { TOUCH_MULTITOUCHSCREEN_T9,
+	139, 0, 0, 24, 32, 0, 176, MXT768E_THRESHOLD_BATT, 2, 1,
+	10, 10, 1, 13, MXT768E_MAX_MT_FINGERS, 20, 40, 20, 31, 3,
+	255, 4, MXT768E_XLOCLIP_BATT, MXT768E_XHICLIP_BATT,
+	MXT768E_YLOCLIP_BATT, MXT768E_YHICLIP_BATT,
+	MXT768E_XEDGECTRL_BATT, MXT768E_XEDGEDIST_BATT,
+	MXT768E_YEDGECTRL_BATT, MXT768E_YEDGEDIST_BATT,
+	12, MXT768E_TCHHYST_BATT, 43, 51, 0
+};
+
+static u8 t15_config_e[] = { TOUCH_KEYARRAY_T15,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t18_config_e[] = { SPT_COMCONFIG_T18,
+	0, 0
+};
+
+static u8 t19_config_e[] = { SPT_GPIOPWM_T19,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t25_config_e[] = { SPT_SELFTEST_T25,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t40_config_e[] = { PROCI_GRIPSUPPRESSION_T40,
+	0, 0, 0, 0, 0
+};
+
+static u8 t42_config_e[] = { PROCI_TOUCHSUPPRESSION_T42,
+	3/*51*/, 15, 100, 64, 224, 2, 0, 0, 200, 200
+};
+
+static u8 t43_config_e[] = { SPT_DIGITIZER_T43,
+	0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t46_config_e[] = { SPT_CTECONFIG_T46,
+	0, 0, MXT768E_IDLESYNCSPERX_BATT,
+	MXT768E_ACTVSYNCSPERX_BATT, 0, 0, 2, 0, 0
+};
+
+static u8 t47_config_e[] = { PROCI_STYLUS_T47,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t48_config_e[] = {PROCG_NOISESUPPRESSION_T48,
+	3, 0, MXT768E_CALCFG_BATT, 0, 0, 0, 0, 0, 0, 0,
+	176, 15, 0, 6, 6, 0, 0, 48, 4, 64,
+	0, 0, 20, 0, 0, 0, 0, 15, 0, 0,
+	0, 0, 0, 0, 112, MXT768E_THRESHOLD_CHRG, 2, 16, 2, 80,
+	MXT768E_MAX_MT_FINGERS, 20, 40, 250, 250, 5, 5, 143, 50, 136,
+	30, 12, MXT768E_TCHHYST_CHRG, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 0
+};
+
+static u8 t48_config_chrg_e[] = {PROCG_NOISESUPPRESSION_T48,
+	3, 0, MXT768E_CALCFG_CHRG, 0, 0, 0, 0, 0, 0, 0,
+	112, 15, 0, 6, 6, 0, 0, 44, 4, 64,
+	0, 0, 20, 0, 0, 0, 0, 15, 0, 0,
+	0, 0, 0, 0, 112, MXT768E_THRESHOLD_CHRG, 2, 16, 8, 80,
+	MXT768E_MAX_MT_FINGERS, 20, 40, 251, 251, 6, 6, 144, 50, 136,
+	30, 12, MXT768E_TCHHYST_CHRG, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 0
+};
+
+static u8 t52_config_e[] = { TOUCH_PROXIMITY_KEY_T52,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t55_config_e[] = {ADAPTIVE_T55,
+	0, 0, 0, 0, 0
+};
+
+/* T56 used from 2.0 firmware */
+static u8 t56_config_e[] = {PROCI_SHIELDLESS_T56,
+	1,  0,  1,  47,  14,  15,  15,  16,  15,  17,
+	16,  16,  16,  16,  17,  16,  16,  16,  16,  16,
+	16,  16,  15,  15,  14,  13,  12,  14,  0,  48,
+	1,  1, 27, 4
+};
+
+static u8 t57_config_e[] = {SPT_GENERICDATA_T57,
+	131/*0*/, 15, 0
+};
+
+
+static u8 end_config_e[] = { RESERVED_T255 };
+
+static const u8 *mxt768e_config[] = {
+	t7_config_e,
+	t8_config_e,
+	t9_config_e,
+	t15_config_e,
+	t18_config_e,
+	t19_config_e,
+	t25_config_e,
+	t40_config_e,
+	t42_config_e,
+	t43_config_e,
+	t46_config_e,
+	t47_config_e,
+	t48_config_e,
+	t52_config_e,
+	t55_config_e,
+	t56_config_e,
+	t57_config_e,
+	end_config_e,
+};
+
+static struct mxt_platform_data mxt_data = {
+	.max_finger_touches = MXT768E_MAX_MT_FINGERS,
+	.gpio_read_done = GPIO_TSP_INT_18V,
+	.config = mxt768e_config,
+	.min_x = 0,
+	.max_x = 1279,
+	.min_y = 0,
+	.max_y = 799,
+	.min_z = 0,
+	.max_z = 255,
+	.min_w = 0,
+	.max_w = 30,
+	.tchthr_batt = MXT768E_THRESHOLD_BATT,
+	.tchthr_charging = MXT768E_THRESHOLD_CHRG,
+	.calcfg_batt = MXT768E_CALCFG_BATT,
+	.calcfg_charging = MXT768E_CALCFG_CHRG,
+	.idlesyncsperx_batt = MXT768E_IDLESYNCSPERX_BATT,
+	.idlesyncsperx_charging = MXT768E_IDLESYNCSPERX_CHRG,
+	.actvsyncsperx_batt = MXT768E_ACTVSYNCSPERX_BATT,
+	.actvsyncsperx_charging = MXT768E_ACTVSYNCSPERX_CHRG,
+	.xloclip_batt = MXT768E_XLOCLIP_BATT,
+	.xloclip_charging = MXT768E_XLOCLIP_CHRG,
+	.xhiclip_batt = MXT768E_XHICLIP_BATT,
+	.xhiclip_charging = MXT768E_XHICLIP_CHRG,
+	.yloclip_batt = MXT768E_YLOCLIP_BATT,
+	.yloclip_charging = MXT768E_YLOCLIP_CHRG,
+	.yhiclip_batt = MXT768E_YHICLIP_BATT,
+	.yhiclip_charging = MXT768E_YHICLIP_CHRG,
+	.xedgectrl_batt = MXT768E_XEDGECTRL_BATT,
+	.xedgectrl_charging = MXT768E_XEDGECTRL_CHRG,
+	.xedgedist_batt = MXT768E_XEDGEDIST_BATT,
+	.xedgedist_charging = MXT768E_XEDGEDIST_CHRG,
+	.yedgectrl_batt = MXT768E_YEDGECTRL_BATT,
+	.yedgectrl_charging = MXT768E_YEDGECTRL_CHRG,
+	.yedgedist_batt = MXT768E_YEDGEDIST_BATT,
+	.yedgedist_charging = MXT768E_YEDGEDIST_CHRG,
+	.t48_config_batt = t48_config_e,
+	.t48_config_chrg = t48_config_chrg_e,
+	.power_on = ts_power_on,
+	.power_off = ts_power_off,
+	.register_cb = ts_register_callback,
+	.read_ta_status = ts_read_ta_status,
+};
+#endif
+
+#if defined(CONFIG_TOUCHSCREEN_MXT1386)
+static struct mxt_callbacks *charger_callbacks;
+static void  sec_mxt1386_charger_infom(bool en)
+{
+	if (charger_callbacks && charger_callbacks->inform_charger)
+		charger_callbacks->inform_charger(charger_callbacks, en);
+
+	printk(KERN_DEBUG "[TSP] %s - %s\n", __func__,
+		en ? "on" : "off");
+}
+static void p3_register_touch_callbacks(struct mxt_callbacks *cb)
+{
+	charger_callbacks = cb;
+}
+
+static void mxt1386_power_on(void)
+{
+	s3c_gpio_cfgpin(GPIO_TSP_LDO_ON, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TSP_LDO_ON, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TSP_LDO_ON, 1);
+	s3c_gpio_cfgpin(GPIO_TSP_RST, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TSP_RST, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TSP_RST, 1);
+	mdelay(70);
+	s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_NONE);
+	s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_SFN(0xf));
+	mdelay(40);
+	printk(KERN_ERR "[TSP]mxt1386_power_on is finished\n");
+}
+
+static void mxt1386_power_off(void)
+{
+	s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_NONE);
+
+	s3c_gpio_cfgpin(GPIO_TSP_RST, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TSP_RST, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TSP_RST, 0);
+
+	s3c_gpio_cfgpin(GPIO_TSP_LDO_ON, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TSP_LDO_ON, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TSP_LDO_ON, 0);
+	/* printk("mxt224_power_off is finished\n"); */
+}
+
+static struct mxt_platform_data p4w_touch_platform_data = {
+	.numtouch = 10,
+	.max_x  = 1280,
+	.max_y  = 800,
+	.init_platform_hw  = mxt1386_power_on,
+	.exit_platform_hw  = mxt1386_power_off,
+	.suspend_platform_hw = mxt1386_power_off,
+	.resume_platform_hw = mxt1386_power_on,
+	.register_cb = p3_register_touch_callbacks,
+	/*mxt_power_config*/
+	/* Set Idle Acquisition Interval to 32 ms. */
+	.power_config.idleacqint = 32,
+	.power_config.actvacqint = 255,
+	/* Set Active to Idle Timeout to 4 s (one unit = 200ms). */
+	.power_config.actv2idleto = 50,
+	/*acquisition_config*/
+	/* Atmel: 8 -> 10*/
+	.acquisition_config.chrgtime = 10,
+	.acquisition_config.reserved = 0,
+	.acquisition_config.tchdrift = 5,
+	/* Atmel: 0 -> 10*/
+	.acquisition_config.driftst = 10,
+	/* infinite*/
+	.acquisition_config.tchautocal = 0,
+	/* disabled*/
+	.acquisition_config.sync = 0,
+#ifdef MXT_CALIBRATE_WORKAROUND
+	/*autocal config at wakeup status*/
+	.acquisition_config.atchcalst = 9,
+	.acquisition_config.atchcalsthr = 48,
+	/* Atmel: 50 => 10 : avoid wakeup lockup : 2 or 3 finger*/
+	.acquisition_config.atchcalfrcthr = 10,
+	.acquisition_config.atchcalfrcratio = 215,
+#else
+	/* Atmel: 5 -> 0 -> 9  (to avoid ghost touch problem)*/
+	.acquisition_config.atchcalst = 9,
+	/* Atmel: 50 -> 55 -> 48 ->10 (to avoid ghost touch problem)*/
+	.acquisition_config.atchcalsthr = 10,
+	/* 50-> 20 (To avoid  wakeup touch lockup)  */
+	.acquisition_config.atchcalfrcthr = 20,
+	/* 25-> 0  (To avoid  wakeup touch lockup */
+	.acquisition_config.atchcalfrcratio = 0,
+#endif
+	/*multitouch_config*/
+	/* enable + message-enable*/
+	.touchscreen_config.ctrl = 0x8b,
+	.touchscreen_config.xorigin = 0,
+	.touchscreen_config.yorigin = 0,
+	.touchscreen_config.xsize = 27,
+	.touchscreen_config.ysize = 42,
+	.touchscreen_config.akscfg = 0,
+	/* Atmel: 0x11 -> 0x21 -> 0x11*/
+	.touchscreen_config.blen = 0x11,
+	/* Atmel: 50 -> 55 -> 48,*/
+	.touchscreen_config.tchthr = 48,
+	.touchscreen_config.tchdi = 2,
+	/* orient : Horizontal flip */
+	.touchscreen_config.orient = 1,
+	.touchscreen_config.mrgtimeout = 0,
+	.touchscreen_config.movhysti = 10,
+	.touchscreen_config.movhystn = 1,
+	 /* Atmel  0x20 ->0x21 -> 0x2e(-2)*/
+	.touchscreen_config.movfilter = 0x50,
+	.touchscreen_config.numtouch = MXT_MAX_NUM_TOUCHES,
+	.touchscreen_config.mrghyst = 5, /*Atmel 10 -> 5*/
+	 /* Atmel 20 -> 5 -> 50 (To avoid One finger Pinch Zoom) */
+	.touchscreen_config.mrgthr = 50,
+	.touchscreen_config.amphyst = 10,
+	.touchscreen_config.xrange = 799,
+	.touchscreen_config.yrange = 1279,
+	.touchscreen_config.xloclip = 0,
+	.touchscreen_config.xhiclip = 0,
+	.touchscreen_config.yloclip = 0,
+	.touchscreen_config.yhiclip = 0,
+	.touchscreen_config.xedgectrl = 0,
+	.touchscreen_config.xedgedist = 0,
+	.touchscreen_config.yedgectrl = 0,
+	.touchscreen_config.yedgedist = 0,
+	.touchscreen_config.jumplimit = 18,
+	.touchscreen_config.tchhyst = 10,
+	.touchscreen_config.xpitch = 1,
+	.touchscreen_config.ypitch = 3,
+	/*noise_suppression_config*/
+	.noise_suppression_config.ctrl = 0x87,
+	.noise_suppression_config.reserved = 0,
+	.noise_suppression_config.reserved1 = 0,
+	.noise_suppression_config.reserved2 = 0,
+	.noise_suppression_config.reserved3 = 0,
+	.noise_suppression_config.reserved4 = 0,
+	.noise_suppression_config.reserved5 = 0,
+	.noise_suppression_config.reserved6 = 0,
+	.noise_suppression_config.noisethr = 30,
+	.noise_suppression_config.reserved7 = 0,/*1;*/
+	.noise_suppression_config.freqhopscale = 0,
+	.noise_suppression_config.freq[0] = 10,
+	.noise_suppression_config.freq[1] = 18,
+	.noise_suppression_config.freq[2] = 23,
+	.noise_suppression_config.freq[3] = 30,
+	.noise_suppression_config.freq[4] = 36,
+	.noise_suppression_config.reserved8 = 0, /* 3 -> 0*/
+	/*cte_config*/
+	.cte_config.ctrl = 0,
+	.cte_config.cmd = 0,
+	.cte_config.mode = 0,
+	/*16 -> 4 -> 8*/
+	.cte_config.idlegcafdepth = 8,
+	/*63 -> 16 -> 54(16ms sampling)*/
+	.cte_config.actvgcafdepth = 54,
+	.cte_config.voltage = 0x3c,
+	/* (enable + non-locking mode)*/
+	.gripsupression_config.ctrl = 0,
+	.gripsupression_config.xlogrip = 0, /*10 -> 0*/
+	.gripsupression_config.xhigrip = 0, /*10 -> 0*/
+	.gripsupression_config.ylogrip = 0, /*10 -> 15*/
+	.gripsupression_config.yhigrip = 0,/*10 -> 15*/
+	.palmsupression_config.ctrl = 1,
+	.palmsupression_config.reserved1 = 0,
+	.palmsupression_config.reserved2 = 0,
+	/* 40 -> 20(For PalmSuppression detect) */
+	.palmsupression_config.largeobjthr = 10,
+	/* 5 -> 50(For PalmSuppression detect) */
+	.palmsupression_config.distancethr = 50,
+	.palmsupression_config.supextto = 5,
+	/*config change for ta connected*/
+	.idleacqint_for_ta_connect = 255,
+	.tchthr_for_ta_connect = 80,
+	.noisethr_for_ta_connect = 50,
+	.idlegcafdepth_ta_connect = 32,
+	.fherr_cnt = 0,
+	.fherr_chg_cnt = 10,
+	.tch_blen_for_fherr = 0x11,
+	.tchthr_for_fherr = 85,
+	.noisethr_for_fherr = 50,
+	.movefilter_for_fherr = 0x57,
+	.jumplimit_for_fherr = 30,
+	.freqhopscale_for_fherr = 1,
+	.freq_for_fherr1[0] = 10,
+	.freq_for_fherr1[1] = 12,
+	.freq_for_fherr1[2] = 18,
+	.freq_for_fherr1[3] = 40,
+	.freq_for_fherr1[4] = 72,
+	.freq_for_fherr2[0] = 45,
+	.freq_for_fherr2[1] = 49,
+	.freq_for_fherr2[2] = 55,
+	.freq_for_fherr2[3] = 59,
+	.freq_for_fherr2[4] = 63,
+	.freq_for_fherr3[0] = 7,
+	.freq_for_fherr3[1] = 33,
+	.freq_for_fherr3[2] = 39,
+	.freq_for_fherr3[3] = 52,
+	.freq_for_fherr3[4] = 64,
+	.fherr_cnt_no_ta = 0,
+	.fherr_chg_cnt_no_ta = 1,
+	.tch_blen_for_fherr_no_ta = 0,
+	.tchthr_for_fherr_no_ta = 45,
+	.movfilter_fherr_no_ta = 0,
+	.noisethr_for_fherr_no_ta = 40,
+#ifdef MXT_CALIBRATE_WORKAROUND
+	/*autocal config at idle status*/
+	.atchcalst_idle = 9,
+	.atchcalsthr_idle = 10,
+	.atchcalfrcthr_idle = 50,
+	/* Atmel: 25 => 55 : avoid idle palm on lockup*/
+	.atchcalfrcratio_idle = 55,
+#endif
+};
+#endif
+
+#if defined(CONFIG_RMI4_I2C)
+static int synaptics_tsp_pre_suspend(const void *pm_data)
+{
+	printk(KERN_DEBUG "[TSP] %s\n", __func__);
+	s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TSP_INT, 0);
+	s3c_gpio_cfgpin(GPIO_TSP_RST, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TSP_RST, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TSP_RST, 0);
+	s3c_gpio_cfgpin(GPIO_TSP_LDO_ON, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TSP_LDO_ON, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TSP_LDO_ON, 0);
+
+	return 0;
+}
+
+static int synaptics_tsp_post_resume(const void *pm_data)
+{
+	printk(KERN_DEBUG "[TSP] %s\n", __func__);
+	s3c_gpio_cfgpin(GPIO_TSP_LDO_ON, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TSP_LDO_ON, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TSP_LDO_ON, 1);
+	s3c_gpio_cfgpin(GPIO_TSP_RST, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TSP_RST, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TSP_RST, 1);
+	s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_NONE);
+	s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_SFN(0xf));
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_I2C_S3C2410
+/* I2C0 */
+static struct i2c_board_info i2c_devs0[] __initdata = {
+	{I2C_BOARD_INFO("24c128", 0x50),},	/* Samsung S524AD0XD1 */
+	{I2C_BOARD_INFO("24c128", 0x52),},	/* Samsung S524AD0XD1 */
+};
+
+#ifdef CONFIG_S3C_DEV_I2C1
+
+#ifndef CONFIG_MPU_SENSORS_MPU3050
+
+/* I2C1 */
+static struct i2c_board_info i2c_devs1[] __initdata = {
+	{
+		I2C_BOARD_INFO("k3g", 0x69),
+		.irq = IRQ_EINT(1),
+	},
+	{
+		I2C_BOARD_INFO("k3dh", 0x19),
+	},
+};
+
+#endif /* !CONFIG_MPU_SENSORS_MPU3050 */
+
+#endif /* CONFIG_S3C_DEV_I2C1 */
+
+#ifdef CONFIG_S3C_DEV_I2C2
+/* I2C2 */
+static struct i2c_board_info i2c_devs2[] __initdata = {
+};
+#endif
+#ifdef CONFIG_S3C_DEV_I2C3
+/* I2C3 */
+#if defined(CONFIG_TOUCHSCREEN_MXT1386)	\
+	|| defined(CONFIG_RMI4_I2C)
+#include <plat/regs-iic.h>
+static struct s3c2410_platform_i2c i2c3_data __initdata = {
+	.flags		= 0,
+	.bus_num	= 3,
+	.slave_addr	= 0x10,
+	.frequency	= 400 * 1000,
+	.sda_delay	= S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON,
+};
+#endif
+
+#if defined(CONFIG_RMI4_I2C)
+#include <linux/rmi.h>
+#define SYNAPTICS_RMI_NAME "rmi-i2c"
+#define SYNAPTICS_RMI_ADDR 0x20
+static struct rmi_device_platform_data synaptics_pdata = {
+	.driver_name = "rmi-generic",
+	.sensor_name = "s7301",
+	.attn_gpio = GPIO_TSP_INT,
+	.attn_polarity = RMI_ATTN_ACTIVE_LOW,
+	.axis_align = { },
+	.pm_data = NULL,
+	.pre_suspend = synaptics_tsp_pre_suspend,
+	.post_resume = synaptics_tsp_post_resume,
+};
+#endif	/* CONFIG_RMI4_I2C */
+
+#if defined(CONFIG_TOUCHSCREEN_MXT1386)	\
+	&& defined(CONFIG_RMI4_I2C)
+static struct i2c_board_info i2c_devs3_mxt[] __initdata = {
+	{
+		I2C_BOARD_INFO("sec_touchscreen", 0x4c),
+		.platform_data = &p4w_touch_platform_data,
+	},
+};
+static struct i2c_board_info i2c_devs3_syn[] __initdata = {
+	{
+		I2C_BOARD_INFO(SYNAPTICS_RMI_NAME,
+			SYNAPTICS_RMI_ADDR),
+		.platform_data = &synaptics_pdata,
+	},
+};
+
+#else	/* defined(CONFIG_TOUCHSCREEN_MXT1386)	\
+			&& defined(CONFIG_RMI4_I2C)*/
+
+static struct i2c_board_info i2c_devs3[] __initdata = {
+#ifdef CONFIG_TOUCHSCREEN_ATMEL_MXT224_U1
+	{
+		I2C_BOARD_INFO(MXT224_DEV_NAME, 0x4a),
+		.platform_data = &mxt224_data,
+	},
+#endif
+#if defined(CONFIG_TOUCHSCREEN_MXT540E)
+	{
+		I2C_BOARD_INFO(MXT540E_DEV_NAME, 0x4c),
+		.platform_data = &mxt540e_data,
+	},
+#endif
+#if defined(CONFIG_TOUCHSCREEN_MXT768E)
+	{
+		I2C_BOARD_INFO(MXT_DEV_NAME, 0x4c),
+		.platform_data = &mxt_data
+	},
+#endif
+#if defined(CONFIG_TOUCHSCREEN_MMS152)
+	{
+	    I2C_BOARD_INFO(TS_DEV_NAME, TS_DEV_ADDR),
+	    .platform_data	= &ts_data,
+	},
+#endif
+};
+
+#endif	/* defined(CONFIG_TOUCHSCREEN_MXT1386)	\
+			&& defined(CONFIG_RMI4_I2C)*/
+#endif	/* CONFIG_S3C_DEV_I2C3 */
+
+#ifdef CONFIG_S3C_DEV_I2C4
+#ifdef CONFIG_EPEN_WACOM_G5SP
+static int p4w_wacom_init_hw(void);
+static int p4w_wacom_suspend_hw(void);
+static int p4w_wacom_resume_hw(void);
+static int p4w_wacom_early_suspend_hw(void);
+static int p4w_wacom_late_resume_hw(void);
+static int p4w_wacom_reset_hw(void);
+static void p4w_wacom_register_callbacks(struct wacom_g5_callbacks *cb);
+
+static struct wacom_g5_platform_data p4w_wacom_platform_data = {
+	.x_invert = 0,
+	.y_invert = 0,
+	.xy_switch = 0,
+	.gpio_pendct = GPIO_PEN_PDCT_18V,
+	.init_platform_hw = p4w_wacom_init_hw,
+	.suspend_platform_hw = p4w_wacom_suspend_hw,
+	.resume_platform_hw = p4w_wacom_resume_hw,
+	.early_suspend_platform_hw = p4w_wacom_early_suspend_hw,
+	.late_resume_platform_hw = p4w_wacom_late_resume_hw,
+	.reset_platform_hw = p4w_wacom_reset_hw,
+	.register_cb = p4w_wacom_register_callbacks,
+};
+#endif /* CONFIG_EPEN_WACOM_G5SP */
+
+/* I2C4 */
+static struct i2c_board_info i2c_devs4[] __initdata = {
+#ifdef CONFIG_EPEN_WACOM_G5SP
+	{
+		I2C_BOARD_INFO("wacom_g5sp_i2c", 0x56),
+		.platform_data = &p4w_wacom_platform_data,
+	},
+#endif /* CONFIG_EPEN_WACOM_G5SP */
+};
+#endif
+
+#ifdef CONFIG_EPEN_WACOM_G5SP
+static void p4w_wacom_register_callbacks(struct wacom_g5_callbacks *cb)
+{
+	wacom_callbacks = cb;
+};
+
+static int __init p4w_wacom_init(void)
+{
+	p4w_wacom_init_hw();
+	gpio_set_value(GPIO_PEN_LDO_EN, 1);
+	printk(KERN_INFO "[E-PEN]: %s.\n", __func__);
+	return 0;
+}
+
+static int p4w_wacom_init_hw(void)
+{
+	int ret;
+	ret = gpio_request(GPIO_PEN_LDO_EN, "PEN_LDO_EN");
+	if (ret) {
+		printk(KERN_ERR "[E-PEN]: faile to request gpio(GPIO_PEN_LDO_EN)\n");
+		return ret;
+	}
+	s3c_gpio_cfgpin(GPIO_PEN_LDO_EN, S3C_GPIO_SFN(0x1));
+	s3c_gpio_setpull(GPIO_PEN_LDO_EN, S3C_GPIO_PULL_NONE);
+	gpio_direction_output(GPIO_PEN_LDO_EN, 0);
+
+	ret = gpio_request(GPIO_PEN_PDCT_18V, "PEN_PDCT");
+	if (ret) {
+		printk(KERN_ERR "[E-PEN]: faile to request gpio(GPIO_PEN_PDCT_18V)\n");
+		return ret;
+	}
+	s3c_gpio_cfgpin(GPIO_PEN_PDCT_18V, S3C_GPIO_SFN(0x0));
+	s3c_gpio_setpull(GPIO_PEN_PDCT_18V, S3C_GPIO_PULL_NONE);
+	gpio_direction_input(GPIO_PEN_PDCT_18V);
+
+	ret = gpio_request(GPIO_PEN_SLP_18V, "PEN_SLP");
+	if (ret) {
+		printk(KERN_ERR "[E-PEN]: faile to request gpio(GPIO_PEN_SLP_18V)\n");
+		return ret;
+	}
+	s3c_gpio_cfgpin(GPIO_PEN_SLP_18V, S3C_GPIO_SFN(0x1));
+	s3c_gpio_setpull(GPIO_PEN_SLP_18V, S3C_GPIO_PULL_NONE);
+	gpio_direction_output(GPIO_PEN_SLP_18V, 0);
+
+	ret = gpio_request(GPIO_PEN_IRQ_18V, "PEN_IRQ");
+	if (ret) {
+		printk(KERN_ERR "[E-PEN]: faile to request gpio(GPIO_PEN_IRQ_18V)\n");
+		return ret;
+	}
+	s3c_gpio_cfgpin(GPIO_PEN_IRQ_18V, S3C_GPIO_SFN(0xf));
+	s3c_gpio_setpull(GPIO_PEN_IRQ_18V, S3C_GPIO_PULL_DOWN);
+	s5p_register_gpio_interrupt(GPIO_PEN_IRQ_18V);
+	gpio_direction_input(GPIO_PEN_IRQ_18V);
+	i2c_devs4[0].irq = gpio_to_irq(GPIO_PEN_IRQ_18V);
+	return 0;
+}
+
+static int p4w_wacom_suspend_hw(void)
+{
+	return p4w_wacom_early_suspend_hw();
+}
+
+static int p4w_wacom_resume_hw(void)
+{
+	return p4w_wacom_late_resume_hw();
+}
+
+static int p4w_wacom_early_suspend_hw(void)
+{
+#if defined(WACOM_SLEEP_WITH_PEN_SLP)
+	gpio_set_value(GPIO_PEN_SLP_18V, 1);
+#elif defined(WACOM_SLEEP_WITH_PEN_LDO_EN)
+	gpio_set_value(GPIO_PEN_LDO_EN, 0);
+#endif
+	return 0;
+}
+
+static int p4w_wacom_late_resume_hw(void)
+{
+#if defined(WACOM_SLEEP_WITH_PEN_SLP)
+	gpio_set_value(GPIO_PEN_SLP_18V, 0);
+#elif defined(WACOM_SLEEP_WITH_PEN_LDO_EN)
+	gpio_set_value(GPIO_PEN_LDO_EN, 1);
+#endif
+
+#if (WACOM_HAVE_RESET_CONTROL == 1)
+	msleep(WACOM_DELAY_FOR_RST_RISING);
+	gpio_set_value(GPIO_PEN_SLP_18V, 1);
+#endif
+	return 0;
+}
+static int p4w_wacom_reset_hw(void)
+{
+
+#if (WACOM_HAVE_RESET_CONTROL == 1)
+	gpio_set_value(OMAP_GPIO_PEN_RST, 0);
+	msleep(200);
+	gpio_set_value(OMAP_GPIO_PEN_RST, 1);
+#endif
+	printk(KERN_INFO "[E-PEN] : wacom warm reset(%d).\n",
+		WACOM_HAVE_RESET_CONTROL);
+	return 0;
+}
+#endif /* CONFIG_EPEN_WACOM_G5SP */
+
+
+#ifdef CONFIG_S3C_DEV_I2C5
+/* I2C5 */
+static struct i2c_board_info i2c_devs5[] __initdata = {
+#ifdef CONFIG_MFD_MAX8998
+	{
+		I2C_BOARD_INFO("lp3974", 0x66),
+		.platform_data = &s5pv310_max8998_info,
+	},
+#endif
+#ifdef CONFIG_MFD_MAX8997
+	{
+		I2C_BOARD_INFO("max8997", (0xcc >> 1)),
+		.platform_data = &exynos4_max8997_info,
+	},
+#endif
+};
+#endif
+#ifdef CONFIG_S3C_DEV_I2C6
+/* I2C6 */
+static struct i2c_board_info i2c_devs6[] __initdata = {
+#ifdef CONFIG_SND_SOC_U1_MC1N2
+	{
+		I2C_BOARD_INFO("mc1n2", 0x3a),	/* MC1N2 */
+		.platform_data = &mc1n2_pdata,
+	},
+#endif
+};
+#endif
+#ifdef CONFIG_S3C_DEV_I2C7
+static struct akm8975_platform_data akm8975_pdata = {
+	.gpio_data_ready_int = GPIO_MSENSE_INT,
+};
+
+/* I2C7 */
+static struct i2c_board_info i2c_devs7[] __initdata = {
+	{
+		I2C_BOARD_INFO("ak8975", 0x0C),
+		.platform_data = &akm8975_pdata,
+	},
+#ifdef CONFIG_VIDEO_TVOUT
+	{
+		I2C_BOARD_INFO("s5p_ddc", (0x74 >> 1)),
+	},
+#endif
+};
+#endif
+static void s3c_i2c7_cfg_gpio_px(struct platform_device *dev)
+{
+	s3c_gpio_cfgall_range(EXYNOS4_GPD0(2), 2,
+		S3C_GPIO_SFN(3), S3C_GPIO_PULL_NONE);
+}
+
+struct s3c2410_platform_i2c default_i2c7_data __initdata = {
+	.bus_num	= 7,
+	.flags		= 0,
+	.slave_addr	= 0x10,
+	.frequency	= 100*1000,
+	.sda_delay	= 100,
+	.cfg_gpio	= s3c_i2c7_cfg_gpio_px,
+};
+#ifdef CONFIG_S3C_DEV_I2C8_EMUL
+static struct i2c_gpio_platform_data gpio_i2c_data8 = {
+	.sda_pin = GPIO_3_TOUCH_SDA,
+	.scl_pin = GPIO_3_TOUCH_SCL,
+};
+
+struct platform_device s3c_device_i2c8 = {
+	.name = "i2c-gpio",
+	.id = 8,
+	.dev.platform_data = &gpio_i2c_data8,
+};
+
+/* I2C8 */
+static struct i2c_board_info i2c_devs8_emul[] = {
+	{
+		I2C_BOARD_INFO("sec_touchkey", 0x20),
+	},
+};
+#endif
+
+#ifdef CONFIG_S3C_DEV_I2C9_EMUL
+static struct i2c_gpio_platform_data gpio_i2c_data9 = {
+	.sda_pin = GPIO_FUEL_SDA,
+	.scl_pin = GPIO_FUEL_SCL,
+};
+
+struct platform_device s3c_device_i2c9 = {
+	.name = "i2c-gpio",
+	.id = 9,
+	.dev.platform_data = &gpio_i2c_data9,
+};
+
+/* I2C9 */
+#ifdef CONFIG_BATTERY_MAX17042_FUELGAUGE_PX
+static struct max17042_platform_data max17042_pdata = {
+#if defined(CONFIG_MACH_P2)
+	.sdi_capacity = 0x1EC8,
+	.sdi_vfcapacity = 0x290A,
+	.atl_capacity = 0x1FBE,
+	.atl_vfcapacity = 0x2A54,
+	.sdi_low_bat_comp_start_vol = 3550,
+	.atl_low_bat_comp_start_vol = 3450,
+	.fuel_alert_line = GPIO_FUEL_ALERT,
+#elif defined(CONFIG_MACH_P4)
+	.sdi_capacity = 0x3730,
+	.sdi_vfcapacity = 0x4996,
+	.atl_capacity = 0x3022,
+	.atl_vfcapacity = 0x4024,
+	.sdi_low_bat_comp_start_vol = 3600,
+	.atl_low_bat_comp_start_vol = 3450,
+	.fuel_alert_line = GPIO_FUEL_ALERT,
+#elif defined(CONFIG_MACH_P8) || defined(CONFIG_MACH_P8LTE)
+	.sdi_capacity = 0x2B06,
+	.sdi_vfcapacity = 0x395E,
+	.atl_capacity = 0x2B06,
+	.atl_vfcapacity = 0x395E,
+	.sdi_low_bat_comp_start_vol = 3600,
+	.atl_low_bat_comp_start_vol = 3450,
+	.fuel_alert_line = GPIO_FUEL_ALERT,
+#else	/* default value */
+	.sdi_capacity = 0x1F40,
+	.sdi_vfcapacity = 0x29AC,
+	.atl_capacity = 0x1FBE,
+	.atl_vfcapacity = 0x2A54,
+	.sdi_low_bat_comp_start_vol = 3600,
+	.atl_low_bat_comp_start_vol = 3450,
+	.fuel_alert_line = GPIO_FUEL_ALERT,
+#endif
+	.check_jig_status = check_jig_on
+};
+
+static struct i2c_board_info i2c_devs9_emul[] __initdata = {
+	{
+		I2C_BOARD_INFO("fuelgauge", 0x36),
+		.platform_data = &max17042_pdata,
+	},
+};
+#else
+static struct i2c_board_info i2c_devs9_emul[] __initdata = {
+	{
+		I2C_BOARD_INFO("max17040", 0x36),
+	},
+};
+#endif
+#endif
+
+#ifdef CONFIG_S3C_DEV_I2C10_EMUL
+static struct i2c_gpio_platform_data gpio_i2c_data10 __initdata = {
+	.sda_pin = GPIO_USB_SDA,
+	.scl_pin = GPIO_USB_SCL,
+};
+
+struct platform_device s3c_device_i2c10 = {
+	.name = "i2c-gpio",
+	.id = 10,
+	.dev.platform_data = &gpio_i2c_data10,
+};
+
+/* I2C10 */
+static struct fsa9480_platform_data fsa9480_info = {
+};
+
+static struct i2c_board_info i2c_devs10_emul[] __initdata = {
+	{
+		I2C_BOARD_INFO("fsa9480", 0x25),
+		.platform_data = &fsa9480_info,
+	},
+};
+#endif
+
+#ifdef CONFIG_S3C_DEV_I2C11_EMUL
+static struct i2c_gpio_platform_data gpio_i2c_data11 = {
+	.sda_pin = GPIO_PS_ALS_SDA,
+	.scl_pin = GPIO_PS_ALS_SCL,
+};
+
+struct platform_device s3c_device_i2c11 = {
+	.name = "i2c-gpio",
+	.id = 11,
+	.dev.platform_data = &gpio_i2c_data11,
+};
+
+#ifdef CONFIG_SENSORS_BH1721FVC
+static int light_sensor_init(void)
+{
+	int err;
+	int gpio_vout = GPIO_PS_VOUT;
+
+	#if defined(CONFIG_OPTICAL_WAKE_ENABLE)
+	if (system_rev >= 0x03) {
+		printk(KERN_INFO" BH1721 Reset GPIO = GPX0(1) (rev%02d)\n", system_rev);
+		gpio_vout = GPIO_PS_VOUT_WAKE;
+	} else
+		printk(KERN_INFO" BH1721 Reset GPIO = GPL0(6) (rev%02d)\n", system_rev);
+	#endif
+
+	printk(KERN_INFO"============================\n");
+	printk(KERN_INFO"==    BH1721 Light Sensor Init         ==\n");
+	printk(KERN_INFO"============================\n");
+	printk("%d %d\n", GPIO_PS_ALS_SDA, GPIO_PS_ALS_SCL);
+	err = gpio_request(gpio_vout, "LIGHT_SENSOR_RESET");
+	if (err) {
+		printk(KERN_INFO" bh1721fvc Failed to request the light "
+			" sensor gpio (%d)\n", err);
+		return err;
+	}
+
+	s3c_gpio_cfgpin(gpio_vout, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(gpio_vout, S3C_GPIO_PULL_NONE);
+
+	err = gpio_direction_output(gpio_vout, 0);
+	udelay(2);
+	err = gpio_direction_output(gpio_vout, 1);
+	if (err) {
+		printk(KERN_INFO" bh1721fvc Failed to make the light sensor gpio(reset)"
+			" high (%d)\n", err);
+		return err;
+	}
+
+	return 0;
+}
+
+static int  bh1721fvc_light_sensor_reset(void)
+{
+	int err;
+	int gpio_vout = GPIO_PS_VOUT;
+
+	#if defined(CONFIG_OPTICAL_WAKE_ENABLE)
+	if (system_rev >= 0x03)
+		gpio_vout = GPIO_PS_VOUT_WAKE;
+	#endif
+
+	printk(KERN_INFO" bh1721fvc_light_sensor_reset\n");
+	err = gpio_direction_output(gpio_vout, 0);
+	if (err) {
+		printk(KERN_INFO" bh1721fvc Failed to make the light sensor gpio(reset)"
+			" low (%d)\n", err);
+		return err;
+	}
+
+	udelay(2);
+
+	err = gpio_direction_output(gpio_vout, 1);
+	if (err) {
+		printk(KERN_INFO" bh1721fvc Failed to make the light sensor gpio(reset)"
+			" high (%d)\n", err);
+		return err;
+	}
+	return 0;
+}
+
+static int  bh1721fvc_light_sensor_output(int value)
+{
+	int err;
+	int gpio_vout = GPIO_PS_VOUT;
+
+	#if defined(CONFIG_OPTICAL_WAKE_ENABLE)
+	if (system_rev >= 0x03)
+		gpio_vout = GPIO_PS_VOUT_WAKE;
+	#endif
+
+	err = gpio_direction_output(gpio_vout, value);
+	if (err) {
+		printk(KERN_INFO" bh1721fvc Failed to make the light sensor gpio(dvi)"
+			" low (%d)\n", err);
+		return err;
+	}
+	return 0;
+}
+
+static struct bh1721fvc_platform_data bh1721fvc_pdata = {
+	.reset = bh1721fvc_light_sensor_reset,
+	/* .output = bh1721fvc_light_sensor_output, */
+};
+
+static struct i2c_board_info i2c_bh1721_emul[] __initdata = {
+	{
+		I2C_BOARD_INFO("bh1721fvc", 0x23),
+		.platform_data = &bh1721fvc_pdata,
+	},
+#if defined(CONFIG_SENSORS_AL3201)
+	{
+		I2C_BOARD_INFO("AL3201", 0x1c),
+	},
+#endif
+};
+#endif
+
+#ifdef CONFIG_OPTICAL_GP2A
+static int gp2a_power(bool on)
+{
+	printk("%s : %d\n", __func__, on);
+	return 0;
+}
+
+
+#if defined(CONFIG_OPTICAL_WAKE_ENABLE)
+
+static struct gp2a_platform_data gp2a_wake_pdata = {
+	.power = gp2a_power,
+	.p_out = GPIO_PS_VOUT_WAKE,
+};
+
+static struct i2c_board_info i2c_wake_devs11[] __initdata = {
+	{
+		I2C_BOARD_INFO("gp2a", (0x88 >> 1)),
+		.platform_data = &gp2a_wake_pdata,
+	},
+};
+#endif
+
+static struct gp2a_platform_data gp2a_pdata = {
+	.power = gp2a_power,
+	.p_out = GPIO_PS_VOUT,
+};
+
+static struct i2c_board_info i2c_devs11[] __initdata = {
+	{
+		I2C_BOARD_INFO("gp2a", (0x88 >> 1)),
+		.platform_data = &gp2a_pdata,
+	},
+};
+
+#endif
+
+#endif /* CONFIG_S3C_DEV_I2C11_EMUL */
+
+/* I2C13 EMUL*/
+#ifdef CONFIG_VIDEO_SR200PC20_P2
+static struct i2c_gpio_platform_data  i2c13_platdata = {
+	.sda_pin		= VT_CAM_SDA_18V,
+	.scl_pin		= VT_CAM_SCL_18V,
+	.udelay			= 2,    /* 250KHz */
+	.sda_is_open_drain	= 0,
+	.scl_is_open_drain	= 0,
+	.scl_is_output_only	= 0,
+};
+
+static struct platform_device s3c_device_i2c13 = {
+	.name			= "i2c-gpio",
+	.id			= 13,
+	.dev.platform_data	= &i2c13_platdata,
+};
+#endif /* CONFIG_VIDEO_SR200PC20_P2 */
+
+#if defined(CONFIG_MHL_SII9234)
+static void sii9234_init(void)
+{
+	int ret = gpio_request(GPIO_HDMI_EN1, "hdmi_en1");
+	if (ret) {
+		pr_err("%s: gpio_request() for HDMI_EN1 failed\n", __func__);
+		return;
+	}
+	gpio_direction_output(GPIO_HDMI_EN1, 0);
+	if (ret) {
+		pr_err("%s: gpio_direction_output() for HDMI_EN1 failed\n",
+			__func__);
+		return;
+	}
+
+	ret = gpio_request(GPIO_MHL_RST, "mhl_rst");
+	if (ret) {
+		pr_err("%s: gpio_request() for MHL_RST failed\n", __func__);
+		return;
+	}
+	ret = gpio_direction_output(GPIO_MHL_RST, 0);
+	if (ret) {
+		pr_err("%s: gpio_direction_output() for MHL_RST failed\n",
+			__func__);
+		return;
+	}
+}
+
+static void sii9234_hw_reset(void)
+{
+#if defined(CONFIG_HPD_PULL)
+	struct regulator *reg;
+	reg = regulator_get(NULL, "hdp_2.8v");
+	if (IS_ERR_OR_NULL(reg)) {
+		pr_err("%s: failed to get LDO11 regulator\n", __func__);
+		return;
+	}
+#endif
+	gpio_set_value(GPIO_MHL_RST, 0);
+	gpio_set_value(GPIO_HDMI_EN1, 1);
+
+	usleep_range(5000, 10000);
+	gpio_set_value(GPIO_MHL_RST, 1);
+#if defined(CONFIG_HPD_PULL)
+	regulator_enable(reg);
+	regulator_put(reg);
+#endif
+	printk(KERN_ERR "[MHL]sii9234_hw_reset.\n");
+	msleep(30);
+}
+
+static void sii9234_hw_off(void)
+{
+#if defined(CONFIG_HPD_PULL)
+	struct regulator *reg;
+	reg = regulator_get(NULL, "hdp_2.8v");
+	if (IS_ERR_OR_NULL(reg)) {
+		pr_err("%s: failed to get LDO11 regulator\n", __func__);
+		return;
+	}
+	regulator_disable(reg);
+	regulator_put(reg);
+#endif
+	gpio_set_value(GPIO_HDMI_EN1, 0);
+	gpio_set_value(GPIO_MHL_RST, 0);
+	printk(KERN_ERR "[MHL]sii9234_hw_off.\n");
+}
+
+struct sii9234_platform_data sii9234_pdata = {
+	.hw_reset = sii9234_hw_reset,
+	.hw_off = sii9234_hw_off
+};
+static struct i2c_board_info i2c_devs15[] __initdata = {
+	{
+		I2C_BOARD_INFO("SII9234", 0x72>>1),
+		.platform_data = &sii9234_pdata,
+	},
+	{
+		I2C_BOARD_INFO("SII9234A", 0x7A>>1),
+	},
+	{
+		I2C_BOARD_INFO("SII9234B", 0x92>>1),
+	},
+	{
+		I2C_BOARD_INFO("SII9234C", 0xC8>>1),
+	},
+};
+/* i2c-gpio emulation platform_data */
+static struct i2c_gpio_platform_data i2c15_platdata = {
+	.sda_pin		= GPIO_AP_SDA_18V,
+	.scl_pin		= GPIO_AP_SCL_18V,
+	.udelay			= 2,	/* 250 kHz*/
+	.sda_is_open_drain	= 0,
+	.scl_is_open_drain	= 0,
+	.scl_is_output_only	= 0,
+};
+
+static struct platform_device s3c_device_i2c15 = {
+	.name			= "i2c-gpio",
+	.id			= 15,
+	.dev.platform_data	= &i2c15_platdata,
+};
+
+#endif
+
+
+#ifdef CONFIG_S3C_DEV_I2C16_EMUL
+static struct i2c_gpio_platform_data i2c16_platdata = {
+	.sda_pin		= GPIO_FM_SDA_28V,
+	.scl_pin		= GPIO_FM_SCL_28V,
+	.udelay			= 2,	/* 250KHz */
+	.sda_is_open_drain	= 0,
+	.scl_is_open_drain	= 0,
+	.scl_is_output_only	= 0,
+};
+
+static struct platform_device s3c_device_i2c16 = {
+	.name					= "i2c-gpio",
+	.id						= 16,
+	.dev.platform_data	= &i2c16_platdata,
+};
+
+static struct i2c_board_info i2c_devs16[] __initdata = {
+#ifdef CONFIG_FM_SI4709_MODULE
+	{
+		I2C_BOARD_INFO("Si4709", (0x20 >> 1)),
+	},
+#endif
+};
+#endif
+
+#endif
+
+#ifdef CONFIG_TOUCHSCREEN_S3C2410
+static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
+	.delay = 10000,
+	.presc = 49,
+	.oversampling_shift = 2,
+	.cal_x_max = 480,
+	.cal_y_max = 800,
+	.cal_param = {
+		33, -9156, 34720100, 14819, 57, -4234968, 65536,
+	},
+};
+#endif
+#if defined(CONFIG_FB_S5P_S6F1202A)
+static struct s3cfb_lcd s6f1202a = {
+	.width = 1024,
+	.height = 600,
+	.p_width = 161,
+	.p_height = 98,
+	.bpp = 24,
+	.freq = 59,
+	.timing = {
+		.h_fp = 142,
+		.h_bp = 210,
+		.h_sw = 50,
+		.v_fp = 10,
+		.v_fpe = 1,
+		.v_bp = 11,
+		.v_bpe = 1,
+		.v_sw = 10,
+	},
+	.polarity = {
+		.rise_vclk = 1,
+		.inv_hsync = 1,
+		.inv_vsync = 1,
+		.inv_vden = 0,
+	},
+};
+static int lcd_power_on(struct lcd_device *ld, int enable)
+{
+	if (enable) {
+		gpio_set_value(GPIO_LCD_EN, GPIO_LEVEL_HIGH);
+		mdelay(10);
+		gpio_set_value(GPIO_LCD_LDO_EN, GPIO_LEVEL_HIGH);
+		msleep(30);
+		/* LVDS_N_SHDN to high*/
+		gpio_set_value(GPIO_LVDS_NSHDN, GPIO_LEVEL_HIGH);
+		msleep(300);
+	} else {
+		/* For backlight hw spec timming(T4) */
+		msleep(220);
+		/* LVDS_nSHDN low*/
+		gpio_set_value(GPIO_LVDS_NSHDN, GPIO_LEVEL_LOW);
+		msleep(20);
+		/* Disable LVDS Panel Power, 1.2, 1.8, display 3.3V */
+		gpio_set_value(GPIO_LCD_LDO_EN, GPIO_LEVEL_LOW);
+		gpio_set_value(GPIO_LCD_EN, GPIO_LEVEL_LOW);
+		msleep(300);
+	}
+	return 0;
+}
+static struct lcd_platform_data p2_lcd_platform_data = {
+	.power_on		= lcd_power_on,
+};
+#endif
+
+#if defined(CONFIG_FB_S5P_S6C1372)
+static struct s3cfb_lcd s6c1372 = {
+	.width = 1280,
+	.height = 800,
+	.p_width = 217,
+	.p_height = 135,
+	.bpp = 24,
+
+	.freq = 60,
+	.timing = {
+		.h_fp = 18,
+		.h_bp = 36,
+		.h_sw = 16,
+		.v_fp = 4,
+		.v_fpe = 1,
+		.v_bp = 16,
+		.v_bpe = 1,
+		.v_sw = 3,
+	},
+
+	.polarity = {
+		.rise_vclk = 1,
+		.inv_hsync = 1,
+		.inv_vsync = 1,
+		.inv_vden = 0,
+	},
+};
+static int lcd_power_on(struct lcd_device *ld, int enable)
+{
+	if (enable) {
+		gpio_set_value(GPIO_LCD_EN, GPIO_LEVEL_HIGH);
+		msleep(40);
+
+		/* LVDS_N_SHDN to high*/
+		gpio_set_value(GPIO_LVDS_NSHDN, GPIO_LEVEL_HIGH);
+		msleep(300);
+
+		gpio_set_value(GPIO_LED_BACKLIGHT_RESET, GPIO_LEVEL_HIGH);
+		mdelay(2);
+
+	} else {
+		gpio_set_value(GPIO_LED_BACKLIGHT_RESET, GPIO_LEVEL_LOW);
+		msleep(200);
+
+		/* LVDS_nSHDN low*/
+		gpio_set_value(GPIO_LVDS_NSHDN, GPIO_LEVEL_LOW);
+		msleep(40);
+
+		/* Disable LVDS Panel Power, 1.2, 1.8, display 3.3V */
+		gpio_set_value(GPIO_LCD_EN, GPIO_LEVEL_LOW);
+		msleep(400);
+	}
+
+	return 0;
+}
+
+static struct lcd_platform_data p4_lcd_platform_data = {
+	.power_on		= lcd_power_on,
+};
+#endif
+
+#if defined(CONFIG_FB_S5P_S6C1372) || defined(CONFIG_FB_S5P_S6F1202A)
+static struct platform_device lcd_s6c1372 = {
+	.name   = "s6c1372",
+	.id	= -1,
+#if defined(CONFIG_FB_S5P_S6F1202A)
+	.dev.platform_data = &p2_lcd_platform_data,
+#else
+	.dev.platform_data = &p4_lcd_platform_data,
+#endif
+};
+static struct s3c_platform_fb fb_platform_data __initdata = {
+	.hw_ver		= 0x70,
+	.clk_name	= "fimd",
+	.nr_wins	= 5,
+#ifdef CONFIG_FB_S5P_DEFAULT_WINDOW
+	.default_win	= CONFIG_FB_S5P_DEFAULT_WINDOW,
+#else
+	.default_win	= 0,
+#endif
+	.swap		= FB_SWAP_HWORD | FB_SWAP_WORD,
+#if defined(CONFIG_FB_S5P_S6F1202A)
+	.lcd		= &s6f1202a
+#endif
+#if defined(CONFIG_FB_S5P_S6C1372)
+	.lcd		= &s6c1372
+#endif
+};
+#endif
+#if defined(CONFIG_BACKLIGHT_PWM)
+static struct platform_pwm_backlight_data smdk_backlight_data = {
+	.pwm_id  = 1,
+	.max_brightness = 255,
+	.dft_brightness = 30,
+	.pwm_period_ns  = 25000,
+};
+static struct platform_device smdk_backlight_device = {
+	.name      = "backlight",
+	.id        = -1,
+	.dev        = {
+		.parent = &s3c_device_timer[0].dev,
+		.platform_data = &smdk_backlight_data,
+	},
+};
+static void __init smdk_backlight_register(void)
+{
+	int ret;
+	if (system_rev < 3)
+		smdk_backlight_data.pwm_id = 0;
+	ret = platform_device_register(&smdk_backlight_device);
+	if (ret)
+		printk(KERN_ERR "failed to register backlight device: %d\n",
+				ret);
+}
+#endif
+#ifdef CONFIG_FB_S5P_MDNIE
+static struct platform_mdnie_data mdnie_data = {
+	.display_type	= -1,
+#if defined(CONFIG_FB_S5P_S6F1202A)
+	.lcd_pd		= &p2_lcd_platform_data,
+#elif defined(CONFIG_FB_S5P_S6C1372)
+	.lcd_pd		= &p4_lcd_platform_data,
+#endif
+};
+static struct platform_device mdnie_device = {
+	.name = "mdnie",
+	.id = -1,
+	.dev = {
+		.parent = &exynos4_device_pd[PD_LCD0].dev,
+		.platform_data = &mdnie_data,
+	},
+};
+static void __init mdnie_device_register(void)
+{
+	int ret;
+
+	mdnie_data.display_type = lcdtype;
+
+	ret = platform_device_register(&mdnie_device);
+	if (ret)
+		printk(KERN_ERR "failed to register mdnie device: %d\n",
+				ret);
+}
+#endif
+
+#if defined(CONFIG_FB_S5P_S6C1372) || defined(CONFIG_FB_S5P_S6F1202A)
+static int lcd_cfg_gpio(void)
+{
+	return 0;
+}
+
+int s6c1372_panel_gpio_init(void)
+{
+	int ret;
+
+	lcd_cfg_gpio();
+
+	/* GPIO Initialize  for S6C1372 LVDS panel */
+	ret = gpio_request(GPIO_LCD_EN, "GPIO_LCD_EN");
+	if (ret) {
+		pr_err("failed to request LCD_EN GPIO%d\n",
+				GPIO_LCD_EN);
+		return ret;
+	}
+	ret = gpio_request(GPIO_LVDS_NSHDN, "GPIO_LVDS_NSHDN");
+	if (ret) {
+		pr_err("failed to request LVDS GPIO%d\n",
+				GPIO_LVDS_NSHDN);
+		return ret;
+	}
+
+	gpio_direction_output(GPIO_LCD_EN, 1);
+	gpio_direction_output(GPIO_LVDS_NSHDN, 1);
+
+	gpio_free(GPIO_LCD_EN);
+	gpio_free(GPIO_LVDS_NSHDN);
+
+#ifdef GPIO_LED_BACKLIGHT_RESET
+	ret = gpio_request(GPIO_LED_BACKLIGHT_RESET,
+				"GPIO_LED_BACKLIGHT_RESET");
+	if (ret) {
+		pr_err("failed to request LVDS GPIO%d\n",
+				GPIO_LED_BACKLIGHT_RESET);
+		return ret;
+	}
+	gpio_direction_output(GPIO_LED_BACKLIGHT_RESET, 1);
+	gpio_free(GPIO_LED_BACKLIGHT_RESET);
+#endif
+	s3cfb_set_platdata(&fb_platform_data);
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_FB_S5P_MIPI_DSIM
+#ifdef CONFIG_FB_S5P_S6E8AB0
+/* for Geminus based on MIPI-DSI interface */
+static struct s3cfb_lcd s6e8ab0 = {
+	.name = "s6e8ab0",
+	.width = 1280,
+	.height = 800,
+	.p_width = 165,
+	.p_height = 103,
+	.bpp = 24,
+
+	.freq = 60,
+
+	/* minumun value is 0 except for wr_act time. */
+	.cpu_timing = {
+		.cs_setup = 0,
+		.wr_setup = 0,
+		.wr_act = 1,
+		.wr_hold = 0,
+	},
+
+	.timing = {
+		.h_fp = 128,
+		.h_bp = 128,
+		.h_sw = 94,
+		.v_fp = 13,
+		.v_fpe = 1,
+		.v_bp = 3,
+		.v_bpe = 1,
+		.v_sw = 2,
+		.cmd_allow_len = 11,    /*v_fp=stable_vfp + cmd_allow_len */
+		.stable_vfp = 2,
+	},
+
+	.polarity = {
+		.rise_vclk = 1,
+		.inv_hsync = 0,
+		.inv_vsync = 0,
+		.inv_vden = 0,
+	},
+};
+
+static int reset_lcd(void)
+{
+	int err;
+
+	printk(KERN_INFO "%s\n", __func__);
+
+	err = gpio_request(GPIO_LCD_RST, "MLCD_RST");
+	if (err) {
+		printk(KERN_ERR "failed to request GPF0[1] for "
+				"MLCD_RST control\n");
+		return -EPERM;
+	}
+	gpio_direction_output(GPIO_LCD_RST, 0);
+
+	/* Power Reset */
+	gpio_set_value(GPIO_LCD_RST, GPIO_LEVEL_HIGH);
+	msleep(5);
+	gpio_set_value(GPIO_LCD_RST, GPIO_LEVEL_LOW);
+	msleep(5);
+	gpio_set_value(GPIO_LCD_RST, GPIO_LEVEL_HIGH);
+
+
+	/* Release GPIO */
+	gpio_free(GPIO_LCD_RST);
+
+	return 0;
+}
+
+static void lcd_cfg_gpio(void)
+{
+	/* MLCD_RST */
+	s3c_gpio_cfgpin(GPIO_LCD_RST, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_LCD_RST, S3C_GPIO_PULL_NONE);
+
+	/* MLCD_ON */
+	s3c_gpio_cfgpin(GPIO_LCD_LDO_EN, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_LCD_LDO_EN, S3C_GPIO_PULL_NONE);
+
+	/* LCD_EN */
+	s3c_gpio_cfgpin(GPIO_LCD_EN, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_LCD_EN, S3C_GPIO_PULL_NONE);
+
+	return;
+}
+
+static int lcd_power_on(void *pdev, int enable)
+{
+	int err;
+
+	printk(KERN_INFO "%s : enable=%d\n", __func__, enable);
+
+	/* Request GPIO */
+	err = gpio_request(GPIO_LCD_LDO_EN, "MLCD_ON");
+	if (err) {
+		printk(KERN_ERR "failed to request GPK1[1] for "
+				"MLCD_ON control\n");
+		return -EPERM;
+	}
+
+	err = gpio_request(GPIO_LCD_EN, "LCD_EN");
+	if (err) {
+		printk(KERN_ERR "failed to request GPL0[7] for "
+				"LCD_EN control\n");
+		return -EPERM;
+	}
+
+	err = gpio_request(GPIO_LCD_RST, "LCD_RST");
+	if (err) {
+		printk(KERN_ERR "failed to request GPL0[7] for "
+				"LCD_EN control\n");
+		return -EPERM;
+	}
+
+	if (enable) {
+		gpio_set_value(GPIO_LCD_LDO_EN, GPIO_LEVEL_HIGH);
+		gpio_set_value(GPIO_LCD_EN, GPIO_LEVEL_HIGH);
+	} else {
+		gpio_set_value(GPIO_LCD_RST, GPIO_LEVEL_LOW);
+		gpio_set_value(GPIO_LCD_LDO_EN, GPIO_LEVEL_LOW);
+		gpio_set_value(GPIO_LCD_EN, GPIO_LEVEL_LOW);
+		mdelay(10);
+	}
+
+	gpio_free(GPIO_LCD_LDO_EN);
+	gpio_free(GPIO_LCD_EN);
+	gpio_free(GPIO_LCD_RST);
+
+	return 0;
+}
+#endif
+
+static struct s3c_platform_fb fb_platform_data __initdata = {
+	.hw_ver = 0x70,
+	.clk_name = "fimd",
+	.nr_wins = 5,
+#ifdef CONFIG_FB_S5P_DEFAULT_WINDOW
+	.default_win	= CONFIG_FB_S5P_DEFAULT_WINDOW,
+#else
+	.default_win = 0,
+#endif
+	.swap = FB_SWAP_HWORD | FB_SWAP_WORD,
+#ifdef CONFIG_FB_S5P_S6E8AB0
+	.lcd = &s6e8ab0
+#endif
+};
+
+static void __init mipi_fb_init(void)
+{
+	struct s5p_platform_dsim *dsim_pd = NULL;
+	struct mipi_ddi_platform_data *mipi_ddi_pd = NULL;
+	struct dsim_lcd_config *dsim_lcd_info = NULL;
+
+	/* set platform data */
+
+	/* gpio pad configuration for rgb and spi interface. */
+	lcd_cfg_gpio();
+
+	/*
+	 * register lcd panel data.
+	 */
+	printk(KERN_INFO "%s :: fb_platform_data.hw_ver = 0x%x\n",
+	       __func__, fb_platform_data.hw_ver);
+
+	fb_platform_data.mipi_is_enabled = 1;
+	fb_platform_data.interface_mode = FIMD_CPU_INTERFACE;
+
+	dsim_pd = (struct s5p_platform_dsim *)
+	    s5p_device_dsim.dev.platform_data;
+
+	dsim_pd->platform_rev = 1;
+
+	dsim_lcd_info = dsim_pd->dsim_lcd_info;
+
+#ifdef CONFIG_FB_S5P_S6E8AB0
+	dsim_lcd_info->lcd_panel_info = (void *)&s6e8ab0;
+
+	/* 500Mbps */
+	dsim_pd->dsim_info->p = 3;
+	dsim_pd->dsim_info->m = 125;
+	dsim_pd->dsim_info->s = 1;
+
+	dsim_pd->dsim_info->hs_toggle = msecs_to_jiffies(500);
+#endif
+
+	mipi_ddi_pd = (struct mipi_ddi_platform_data *)
+	    dsim_lcd_info->mipi_ddi_pd;
+	mipi_ddi_pd->lcd_reset = reset_lcd;
+	mipi_ddi_pd->lcd_power_on = lcd_power_on;
+
+	platform_device_register(&s5p_device_dsim);
+
+	s3cfb_set_platdata(&fb_platform_data);
+
+	printk(KERN_INFO
+	       "platform data of %s lcd panel has been registered.\n",
+	       dsim_pd->lcd_panel_name);
+}
+#endif
+
+#ifdef CONFIG_ANDROID_PMEM
+static struct android_pmem_platform_data pmem_pdata = {
+	.name = "pmem",
+	.no_allocator = 1,
+	.cached = 0,
+	.start = 0,
+	.size = 0
+};
+
+static struct android_pmem_platform_data pmem_gpu1_pdata = {
+	.name = "pmem_gpu1",
+	.no_allocator = 1,
+	.cached = 0,
+	.start = 0,
+	.size = 0,
+};
+
+static struct platform_device pmem_device = {
+	.name = "android_pmem",
+	.id = 0,
+	.dev = {
+		.platform_data = &pmem_pdata},
+};
+
+static struct platform_device pmem_gpu1_device = {
+	.name = "android_pmem",
+	.id = 1,
+	.dev = {
+		.platform_data = &pmem_gpu1_pdata},
+};
+
+static void __init android_pmem_set_platdata(void)
+{
+#if defined(CONFIG_S5P_MEM_CMA)
+	pmem_pdata.size = CONFIG_ANDROID_PMEM_MEMSIZE_PMEM * SZ_1K;
+	pmem_gpu1_pdata.size = CONFIG_ANDROID_PMEM_MEMSIZE_PMEM_GPU1 * SZ_1K;
+#else
+	pmem_pdata.start = (u32) s5p_get_media_memory_bank(S5P_MDEV_PMEM, 0);
+	pmem_pdata.size = (u32) s5p_get_media_memsize_bank(S5P_MDEV_PMEM, 0);
+	pmem_gpu1_pdata.start =
+		(u32) s5p_get_media_memory_bank(S5P_MDEV_PMEM_GPU1, 0);
+	pmem_gpu1_pdata.size =
+		(u32) s5p_get_media_memsize_bank(S5P_MDEV_PMEM_GPU1, 0);
+#endif
+}
+#endif
+
+/* USB EHCI */
+#ifdef CONFIG_USB_EHCI_S5P
+static struct s5p_ehci_platdata smdkc210_ehci_pdata;
+
+static void __init smdkc210_ehci_init(void)
+{
+	struct s5p_ehci_platdata *pdata = &smdkc210_ehci_pdata;
+
+	s5p_ehci_set_platdata(pdata);
+}
+#endif
+
+#ifdef CONFIG_USB_OHCI_S5P
+static struct s5p_ohci_platdata smdkc210_ohci_pdata;
+
+static void __init smdkc210_ohci_init(void)
+{
+	struct s5p_ohci_platdata *pdata = &smdkc210_ohci_pdata;
+
+	s5p_ohci_set_platdata(pdata);
+}
+#endif
+
+/* USB GADGET */
+#ifdef CONFIG_USB_GADGET
+static struct s5p_usbgadget_platdata smdkc210_usbgadget_pdata;
+
+#include <linux/usb/android_composite.h>
+static void __init smdkc210_usbgadget_init(void)
+{
+	struct s5p_usbgadget_platdata *pdata = &smdkc210_usbgadget_pdata;
+
+#if defined(CONFIG_USB_ANDROID) || defined(CONFIG_USB_G_ANDROID)
+	struct android_usb_platform_data *android_pdata =
+		s3c_device_android_usb.dev.platform_data;
+	if (android_pdata) {
+		unsigned int newluns = 2;
+		printk(KERN_DEBUG "usb: %s: default luns=%d, new luns=%d\n",
+				__func__, android_pdata->nluns, newluns);
+		android_pdata->nluns = newluns;
+	} else {
+		printk(KERN_DEBUG "usb: %s android_pdata is not available\n",
+				__func__);
+	}
+#endif
+
+	s5p_usbgadget_set_platdata(pdata);
+
+	pdata = s3c_device_usbgadget.dev.platform_data;
+	if (pdata) {
+		/* Enables HS Transmitter pre-emphasis [20] */
+		pdata->phy_tune_mask = 0;
+		pdata->phy_tune_mask |= (0x1 << 20);
+		pdata->phy_tune |= (0x1 << 20);
+
+		/* HS DC Voltage Level Adjustment [3:0] (1011 : +16%) */
+		pdata->phy_tune_mask |= 0xf;
+		pdata->phy_tune |= 0xb;
+
+		printk(KERN_DEBUG "usb: %s tune_mask=0x%x, tune=0x%x\n",
+			__func__, pdata->phy_tune_mask, pdata->phy_tune);
+	}
+
+#if defined(CONFIG_MACH_P8LTE)
+	/* squelch threshold tune [13:11] (001 : +10%) */
+	pdata->phy_tune_mask |= 0x7 << 11;
+	pdata->phy_tune |= 0x1 << 11;
+	printk(KERN_DEBUG "usb: %s apply squelch threshold tune tune_mask=0x%x, tune=0x%x\n",
+			__func__, pdata->phy_tune_mask, pdata->phy_tune);
+#endif
+}
+#endif
+
+#if defined(CONFIG_SMB136_CHARGER) || defined(CONFIG_SMB347_CHARGER)
+struct smb_charger_callbacks *smb_callbacks;
+
+static void smb_charger_register_callbacks(struct smb_charger_callbacks *ptr)
+{
+	smb_callbacks = ptr;
+}
+
+static void smb_charger_unregister_callbacks(void)
+{
+	smb_callbacks = NULL;
+}
+
+static struct smb_charger_data smb_charger_pdata = {
+	.register_callbacks = smb_charger_register_callbacks,
+	.unregister_callbacks = smb_charger_unregister_callbacks,
+	.enable = GPIO_TA_EN,
+	.stat = GPIO_TA_nCHG,
+#if defined(CONFIG_MACH_P4)
+	.ta_nconnected = GPIO_TA_nCONNECTED,
+#else
+	.ta_nconnected = 0,
+#endif
+};
+
+static struct i2c_board_info i2c_devs12_emul[] __initdata = {
+	{
+#if defined(CONFIG_SMB347_CHARGER)
+	 I2C_BOARD_INFO("smb347-charger", 0x0C >> 1),
+#else
+	 I2C_BOARD_INFO("smb136-charger", 0x9A >> 1),
+#endif
+	 .platform_data = &smb_charger_pdata,
+	 },
+};
+
+static void __init smb_gpio_init(void)
+{
+	s3c_gpio_cfgpin(GPIO_TA_nCHG, S3C_GPIO_SFN(0xf));
+	/* external pull up */
+	s3c_gpio_setpull(GPIO_TA_nCHG, S3C_GPIO_PULL_NONE);
+	i2c_devs12_emul[0].irq = gpio_to_irq(GPIO_TA_nCHG);
+}
+
+static struct i2c_gpio_platform_data gpio_i2c_data12 = {
+	.sda_pin = GPIO_CHG_SDA,
+	.scl_pin = GPIO_CHG_SCL,
+};
+
+static struct platform_device s3c_device_i2c12 = {
+	.name = "i2c-gpio",
+	.id = 12,
+	.dev.platform_data = &gpio_i2c_data12,
+};
+
+static void sec_bat_set_charging_state(int enable, int cable_status)
+{
+	if (smb_callbacks && smb_callbacks->set_charging_state)
+		smb_callbacks->set_charging_state(enable, cable_status);
+}
+
+static int sec_bat_get_charging_state(void)
+{
+	if (smb_callbacks && smb_callbacks->get_charging_state)
+		return smb_callbacks->get_charging_state();
+	else
+		return 0;
+}
+
+static void sec_bat_set_charging_current(int set_current)
+{
+	if (smb_callbacks && smb_callbacks->set_charging_current)
+		smb_callbacks->set_charging_current(set_current);
+}
+
+static int sec_bat_get_charging_current(void)
+{
+	if (smb_callbacks && smb_callbacks->get_charging_current)
+		return smb_callbacks->get_charging_current();
+	else
+		return 0;
+}
+#endif
+
+#if defined(CONFIG_SMB347_CHARGER)
+static int sec_bat_get_charger_is_full(void)
+{
+	if (smb_callbacks && smb_callbacks->get_charger_is_full)
+		return smb_callbacks->get_charger_is_full();
+	else
+		return 0;
+}
+#endif
+
+#ifdef CONFIG_BATTERY_SEC_PX
+void sec_bat_gpio_init(void)
+{
+
+	s3c_gpio_cfgpin(GPIO_TA_nCONNECTED, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_TA_nCONNECTED, S3C_GPIO_PULL_NONE);
+
+	s3c_gpio_cfgpin(GPIO_TA_nCHG, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_TA_nCHG, S3C_GPIO_PULL_UP);
+
+	s3c_gpio_cfgpin(GPIO_TA_EN, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TA_EN, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TA_EN, 0);
+
+#ifndef CONFIG_MACH_P2
+	s3c_gpio_cfgpin(GPIO_CURR_ADJ, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_CURR_ADJ, S3C_GPIO_PULL_NONE);
+#else
+	gpio_request(GPIO_TA_nCHG, "TA_nCHG");
+	s5p_register_gpio_interrupt(GPIO_TA_nCHG);
+#endif
+	pr_info("BAT : Battery GPIO initialized.\n");
+}
+
+static void  sec_charger_cb(int set_cable_type)
+{
+	struct usb_gadget *gadget = platform_get_drvdata(&s3c_device_usbgadget);
+	bool cable_state_to_tsp;
+	bool cable_state_to_usb;
+
+	switch (set_cable_type) {
+	case CHARGER_USB:
+		cable_state_to_tsp = true;
+		cable_state_to_usb = true;
+		is_cable_attached = true;
+		is_usb_lpm_enter = false;
+		break;
+	case CHARGER_AC:
+	case CHARGER_MISC:
+		cable_state_to_tsp = true;
+		cable_state_to_usb = false;
+		is_cable_attached = true;
+		is_usb_lpm_enter = true;
+		break;
+	case CHARGER_BATTERY:
+	case CHARGER_DISCHARGE:
+	default:
+		cable_state_to_tsp = false;
+		cable_state_to_usb = false;
+		is_cable_attached = false;
+		is_usb_lpm_enter = true;
+		break;
+	}
+	pr_info("%s:cable_type=%d,tsp(%d),usb(%d),attached(%d),usblpm(%d)\n",
+		__func__, set_cable_type, cable_state_to_tsp,
+		cable_state_to_usb, is_cable_attached, is_usb_lpm_enter);
+
+/* Send charger state to TSP. TSP needs cable type what charging or not */
+#if defined(CONFIG_TOUCHSCREEN_MMS152)
+	sec_charger_melfas_cb(is_cable_attached);
+#elif defined(CONFIG_TOUCHSCREEN_MXT1386)
+	if (system_rev < 13)
+		sec_mxt1386_charger_infom(is_cable_attached);
+#else
+	if (charging_cbs.tsp_set_charging_cable)
+		charging_cbs.tsp_set_charging_cable(is_cable_attached);
+
+#endif
+
+/* Send charger state to px-switch. px-switch needs cable type what USB or not */
+	set_usb_connection_state(!is_usb_lpm_enter);
+
+/* Send charger state to USB. USB needs cable type what USB data or not */
+	if (gadget) {
+		if (cable_state_to_usb)
+			usb_gadget_vbus_connect(gadget);
+		else
+			usb_gadget_vbus_disconnect(gadget);
+	}
+
+	pr_info("%s\n", __func__);
+}
+
+static struct sec_battery_platform_data sec_battery_platform = {
+	.charger = {
+		.enable_line = GPIO_TA_EN,
+		.connect_line = GPIO_TA_nCONNECTED,
+		.fullcharge_line = GPIO_TA_nCHG,
+#ifndef CONFIG_MACH_P2
+		.currentset_line = GPIO_CURR_ADJ,
+#endif
+#if defined(CONFIG_MACH_P4)
+		.accessory_line = GPIO_ACCESSORY_INT,
+#else
+		.accessory_line = 0,
+#endif
+	},
+#if defined(CONFIG_SMB136_CHARGER) || defined(CONFIG_SMB347_CHARGER)
+	.set_charging_state = sec_bat_set_charging_state,
+	.get_charging_state = sec_bat_get_charging_state,
+	.set_charging_current = sec_bat_set_charging_current,
+	.get_charging_current = sec_bat_get_charging_current,
+#endif
+#if defined(CONFIG_SMB347_CHARGER)
+	.get_charger_is_full = sec_bat_get_charger_is_full,
+#endif
+	.init_charger_gpio = sec_bat_gpio_init,
+	.inform_charger_connection = sec_charger_cb,
+
+#if defined(CONFIG_MACH_P8LTE)
+	.temp_high_threshold = 55800,	/* 55.8c */
+	.temp_high_recovery = 45700,	/* 45.7c */
+	.temp_low_recovery = 2200,		/* 2.2c  */
+	.temp_low_threshold = -2000,	/* -2c   */
+	.recharge_voltage = 4130,	    /*4.13V  */
+#else
+	.temp_high_threshold = 50000,	/* 50c */
+	.temp_high_recovery = 42000,	/* 42c */
+	.temp_low_recovery = 2000,		/* 2c */
+	.temp_low_threshold = 0,		/* 0c */
+	.recharge_voltage = 4150,	/*4.15V */
+#endif
+
+	.charge_duration = 10*60*60,	/* 10 hour */
+	.recharge_duration = 1.5*60*60,	/* 1.5 hour */
+	.check_lp_charging_boot = check_bootmode,
+	.check_jig_status = check_jig_on
+};
+
+static struct platform_device sec_battery_device = {
+	.name = "sec-battery",
+	.id = -1,
+	.dev = {
+		.platform_data = &sec_battery_platform,
+	},
+};
+#endif /* CONFIG_BATTERY_SEC_PX */
+
+#ifdef CONFIG_30PIN_CONN
+static void smdk_accessory_gpio_init(void)
+{
+	gpio_request(GPIO_ACCESSORY_INT, "accessory");
+	s3c_gpio_cfgpin(GPIO_ACCESSORY_INT, S3C_GPIO_SFN(0xf));
+	s3c_gpio_setpull(GPIO_ACCESSORY_INT, S3C_GPIO_PULL_UP);
+	gpio_direction_input(GPIO_ACCESSORY_INT);
+
+	gpio_request(GPIO_DOCK_INT, "dock");
+	s3c_gpio_cfgpin(GPIO_DOCK_INT, S3C_GPIO_SFN(0xf));
+	s3c_gpio_setpull(GPIO_DOCK_INT, S3C_GPIO_PULL_NONE);
+	gpio_direction_input(GPIO_DOCK_INT);
+
+	gpio_request(GPIO_USB_OTG_EN, "GPIO_USB_OTG_EN");
+	s3c_gpio_cfgpin(GPIO_USB_OTG_EN, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_USB_OTG_EN, S3C_GPIO_PULL_NONE);
+	gpio_direction_output(GPIO_USB_OTG_EN, false);
+	gpio_free(GPIO_USB_OTG_EN);
+
+	gpio_request(GPIO_ACCESSORY_EN, "GPIO_ACCESSORY_EN");
+	s3c_gpio_cfgpin(GPIO_ACCESSORY_EN, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_ACCESSORY_EN, S3C_GPIO_PULL_NONE);
+	gpio_direction_output(GPIO_ACCESSORY_EN, false);
+	gpio_free(GPIO_ACCESSORY_EN);
+}
+
+void smdk_accessory_power(u8 token, bool active)
+{
+	int gpio_acc_en;
+	int try_cnt = 0;
+	int gpio_acc_5v = 0;
+	static bool enable;
+	static u8 acc_en_token;
+
+	/*
+		token info
+		0 : power off,
+		1 : Keyboard dock
+		2 : USB
+	*/
+	gpio_acc_en = GPIO_ACCESSORY_EN;
+#ifdef CONFIG_MACH_P4
+	if (system_rev >= 2)
+		gpio_acc_5v = GPIO_ACCESSORY_OUT_5V;
+#elif defined(CONFIG_MACH_P2)	/* for checking p2 3g and wifi */
+	gpio_acc_5v = GPIO_ACCESSORY_OUT_5V;
+#elif defined(CONFIG_MACH_P8LTE)
+	if (system_rev >= 2)
+		gpio_acc_5v = GPIO_ACCESSORY_OUT_5V;
+#elif defined(CONFIG_MACH_P8)	/* for checking p8 3g and wifi */
+	if (system_rev >= 4)
+		gpio_acc_5v = GPIO_ACCESSORY_OUT_5V;
+#endif
+
+	gpio_request(gpio_acc_en, "GPIO_ACCESSORY_EN");
+	s3c_gpio_cfgpin(gpio_acc_en, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(gpio_acc_en, S3C_GPIO_PULL_NONE);
+
+	if (active) {
+		if (acc_en_token) {
+			pr_info("Board : Keyboard dock is connected.\n");
+			gpio_direction_output(gpio_acc_en, 0);
+			msleep(100);
+		}
+
+		acc_en_token |= (1 << token);
+		enable = true;
+		gpio_direction_output(gpio_acc_en, 1);
+
+		if (0 != gpio_acc_5v) {
+			gpio_request(gpio_acc_5v, "gpio_acc_5v");
+			s3c_gpio_cfgpin(gpio_acc_5v, S3C_GPIO_INPUT);
+			s3c_gpio_setpull(gpio_acc_5v, S3C_GPIO_PULL_NONE);
+			msleep(20);
+
+			/* prevent the overcurrent */
+			while (!gpio_get_value(gpio_acc_5v)) {
+				gpio_direction_output(gpio_acc_en, 0);
+				msleep(20);
+				gpio_direction_output(gpio_acc_en, 1);
+				if (try_cnt > 10) {
+					pr_err("[acc] failed to enable the accessory_en");
+					break;
+				} else
+					try_cnt++;
+			}
+			gpio_free(gpio_acc_5v);
+
+		} else
+			pr_info("[ACC] gpio_acc_5v is not set\n");
+
+	} else {
+		if (0 == token) {
+			gpio_direction_output(gpio_acc_en, 0);
+			enable = false;
+		} else {
+			acc_en_token &= ~(1 << token);
+			if (0 == acc_en_token) {
+				gpio_direction_output(gpio_acc_en, 0);
+				enable = false;
+			}
+		}
+	}
+	gpio_free(gpio_acc_en);
+	pr_info("Board : %s (%d,%d) %s\n", __func__,
+		token, active, enable ? "on" : "off");
+}
+
+static int smdk_get_acc_state(void)
+{
+	return gpio_get_value(GPIO_DOCK_INT);
+}
+
+static int smdk_get_dock_state(void)
+{
+	return gpio_get_value(GPIO_ACCESSORY_INT);
+}
+
+#ifdef CONFIG_SEC_KEYBOARD_DOCK
+static struct sec_keyboard_callbacks *keyboard_callbacks;
+static int check_sec_keyboard_dock(bool attached)
+{
+	if (keyboard_callbacks && keyboard_callbacks->check_keyboard_dock)
+		return keyboard_callbacks->
+			check_keyboard_dock(keyboard_callbacks, attached);
+	return 0;
+}
+
+static void check_uart_path(bool en)
+{
+	int gpio_uart_sel;
+#ifdef CONFIG_MACH_P8LTE
+	int gpio_uart_sel2;
+
+	gpio_uart_sel = GPIO_UART_SEL1;
+	gpio_uart_sel2 = GPIO_UART_SEL2;
+	if (en)
+		gpio_direction_output(gpio_uart_sel2, 1);
+	else
+		gpio_direction_output(gpio_uart_sel2, 0);
+	printk(KERN_DEBUG "[Keyboard] uart_sel2 : %d\n",
+		gpio_get_value(gpio_uart_sel2));
+#else
+	gpio_uart_sel = GPIO_UART_SEL;
+#endif
+
+	if (en)
+		gpio_direction_output(gpio_uart_sel, 1);
+	else
+		gpio_direction_output(gpio_uart_sel, 0);
+
+	printk(KERN_DEBUG "[Keyboard] uart_sel : %d\n",
+		gpio_get_value(gpio_uart_sel));
+}
+
+static void sec_keyboard_register_cb(struct sec_keyboard_callbacks *cb)
+{
+	keyboard_callbacks = cb;
+}
+
+static struct sec_keyboard_platform_data kbd_pdata = {
+	.accessory_irq_gpio = GPIO_ACCESSORY_INT,
+	.acc_power = smdk_accessory_power,
+	.check_uart_path = check_uart_path,
+	.register_cb = sec_keyboard_register_cb,
+	.wakeup_key = NULL,
+};
+
+static struct platform_device sec_keyboard = {
+	.name	= "sec_keyboard",
+	.id	= -1,
+	.dev = {
+		.platform_data = &kbd_pdata,
+	}
+};
+#endif
+
+#ifdef CONFIG_USB_HOST_NOTIFY
+#include <linux/host_notify.h>
+
+static void px_usb_otg_power(int active)
+{
+	smdk_accessory_power(2, active);
+}
+
+struct host_notifier_platform_data host_notifier_pdata = {
+	.ndev.name	= "usb_otg",
+	.gpio		= GPIO_ACCESSORY_OUT_5V,
+	.booster	= px_usb_otg_power,
+	.thread_enable = 1,
+};
+
+struct platform_device host_notifier_device = {
+	.name = "host_notifier",
+	.dev.platform_data = &host_notifier_pdata,
+};
+
+static void px_usb_otg_en(int active)
+{
+	pr_info("otg %s : %d\n", __func__, active);
+
+	usb_switch_lock();
+
+	if (active) {
+
+#ifdef CONFIG_USB_EHCI_S5P
+		pm_runtime_get_sync(&s5p_device_ehci.dev);
+#endif
+#ifdef CONFIG_USB_OHCI_S5P
+		pm_runtime_get_sync(&s5p_device_ohci.dev);
+#endif
+
+		usb_switch_set_path(USB_PATH_HOST);
+		smdk_accessory_power(2, 1);
+
+		host_notifier_pdata.ndev.mode = NOTIFY_HOST_MODE;
+		if (host_notifier_pdata.usbhostd_start)
+			host_notifier_pdata.usbhostd_start();
+	} else {
+
+#ifdef CONFIG_USB_OHCI_S5P
+		pm_runtime_put_sync(&s5p_device_ohci.dev);
+#endif
+#ifdef CONFIG_USB_EHCI_S5P
+		pm_runtime_put_sync(&s5p_device_ehci.dev);
+#endif
+
+		usb_switch_clr_path(USB_PATH_HOST);
+		if (host_notifier_pdata.usbhostd_stop)
+			host_notifier_pdata.usbhostd_stop();
+		smdk_accessory_power(2, 0);
+
+	}
+
+	usb_switch_unlock();
+}
+#endif
+
+struct acc_con_platform_data acc_con_pdata = {
+	.otg_en = px_usb_otg_en,
+	.acc_power = smdk_accessory_power,
+	.usb_ldo_en = NULL,
+	.get_acc_state = smdk_get_acc_state,
+	.get_dock_state = smdk_get_dock_state,
+#ifdef CONFIG_SEC_KEYBOARD_DOCK
+	.check_keyboard = check_sec_keyboard_dock,
+#endif
+	.accessory_irq_gpio = GPIO_ACCESSORY_INT,
+	.dock_irq_gpio = GPIO_DOCK_INT,
+#ifdef CONFIG_MHL_SII9234
+	.mhl_irq_gpio = GPIO_MHL_INT,
+	.hdmi_hpd_gpio = GPIO_HDMI_HPD,
+#endif
+};
+struct platform_device sec_device_connector = {
+	.name = "acc_con",
+	.id = -1,
+	.dev.platform_data = &acc_con_pdata,
+};
+#endif
+
+/* BUSFREQ to control memory/bus*/
+static struct device_domain busfreq;
+
+static struct platform_device exynos4_busfreq = {
+	.id = -1,
+	.name = "exynos-busfreq",
+};
+#ifdef CONFIG_SEC_WATCHDOG_RESET
+static struct platform_device watchdog_reset_device = {
+	.name = "watchdog-reset",
+	.id = -1,
+};
+#endif
+static struct platform_device *smdkc210_devices[] __initdata = {
+#ifdef CONFIG_SEC_WATCHDOG_RESET
+	&watchdog_reset_device,
+#endif
+	&exynos4_device_pd[PD_MFC],
+	&exynos4_device_pd[PD_G3D],
+	&exynos4_device_pd[PD_LCD0],
+	&exynos4_device_pd[PD_LCD1],
+	&exynos4_device_pd[PD_CAM],
+	&exynos4_device_pd[PD_TV],
+	&exynos4_device_pd[PD_GPS],
+
+	&smdkc210_smsc911x,
+#ifdef CONFIG_BATTERY_SAMSUNG
+	&samsung_device_battery,
+#endif
+#ifdef CONFIG_BATTERY_SEC_PX
+	&sec_battery_device,
+#endif
+#ifdef CONFIG_ANDROID_PMEM
+	&pmem_device,
+	&pmem_gpu1_device,
+#endif
+#ifdef CONFIG_FB_S5P
+	&s3c_device_fb,
+#endif
+
+#ifdef CONFIG_I2C_S3C2410
+	&s3c_device_i2c0,
+#if defined(CONFIG_S3C_DEV_I2C1)
+	&s3c_device_i2c1,
+#endif
+#if defined(CONFIG_S3C_DEV_I2C2)
+	&s3c_device_i2c2,
+#endif
+#if defined(CONFIG_S3C_DEV_I2C3)
+	&s3c_device_i2c3,
+#endif
+#if defined(CONFIG_S3C_DEV_I2C4)
+	&s3c_device_i2c4,
+#endif
+#if defined(CONFIG_S3C_DEV_I2C5)
+	&s3c_device_i2c5,
+#endif
+#if defined(CONFIG_S3C_DEV_I2C6)
+	&s3c_device_i2c6,
+#endif
+#if defined(CONFIG_S3C_DEV_I2C7)
+	&s3c_device_i2c7,
+#endif
+#if defined(CONFIG_S3C_DEV_I2C8_EMUL)
+	&s3c_device_i2c8,
+#endif
+#if defined(CONFIG_S3C_DEV_I2C9_EMUL)
+	&s3c_device_i2c9,
+#endif
+#if defined(CONFIG_S3C_DEV_I2C10_EMUL)
+	&s3c_device_i2c10,
+#endif
+#if defined(CONFIG_S3C_DEV_I2C11_EMUL)
+	&s3c_device_i2c11,
+#endif
+#if defined(CONFIG_VIDEO_SR200PC20_P2)
+	&s3c_device_i2c13,
+#endif
+#if defined(CONFIG_S3C_DEV_I2C14_EMUL)
+	&s3c_device_i2c14,
+#endif
+#if defined(CONFIG_SMB136_CHARGER)
+	&s3c_device_i2c12,
+#endif
+#if defined(CONFIG_MHL_SII9234)
+		&s3c_device_i2c15,
+#endif
+#ifdef CONFIG_S3C_DEV_I2C16_EMUL
+	&s3c_device_i2c16,
+#endif
+#endif
+
+	/* consumer driver should resume after resuming i2c drivers */
+	&u1_regulator_consumer,
+
+#ifdef CONFIG_EXYNOS4_DEV_MSHC
+	&s3c_device_mshci,
+#endif
+
+#ifdef CONFIG_S3C_DEV_HSMMC
+	&s3c_device_hsmmc0,
+#endif
+
+#ifdef CONFIG_S3C_DEV_HSMMC1
+	&s3c_device_hsmmc1,
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC2
+	&s3c_device_hsmmc2,
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC3
+	&s3c_device_hsmmc3,
+#endif
+
+#ifdef CONFIG_MACH_PX
+	&p4w_wlan_ar6000_pm_device,
+#endif
+
+#ifdef CONFIG_S3C_ADC
+	&s3c_device_adc,
+#endif
+#ifdef CONFIG_TOUCHSCREEN_S3C2410
+#ifdef CONFIG_S3C_DEV_ADC
+	&s3c_device_ts,
+#elif CONFIG_S3C_DEV_ADC1
+	&s3c_device_ts1,
+#endif
+#endif
+#ifdef CONFIG_KEYBOARD_GPIO
+	&px_gpio_keys,
+#endif
+	&s3c_device_rtc,
+	&s3c_device_wdt,
+#ifdef CONFIG_SND_SAMSUNG_AC97
+	&exynos_device_ac97,
+#endif
+#ifdef CONFIG_SND_SAMSUNG_I2S
+	&exynos_device_i2s0,
+#endif
+#ifdef CONFIG_SND_SAMSUNG_PCM
+	&exynos_device_pcm0,
+#endif
+#if defined(CONFIG_SND_SAMSUNG_RP) || defined(CONFIG_SND_SAMSUNG_ALP)
+	&exynos_device_srp,
+#endif
+#ifdef CONFIG_SND_SAMSUNG_SPDIF
+	&exynos_device_spdif,
+#endif
+#ifdef CONFIG_S5P_SYSTEM_MMU
+	&SYSMMU_PLATDEV(fimc0),
+	&SYSMMU_PLATDEV(fimc1),
+	&SYSMMU_PLATDEV(fimc2),
+	&SYSMMU_PLATDEV(fimc3),
+	&SYSMMU_PLATDEV(2d),
+	&SYSMMU_PLATDEV(tv),
+	&SYSMMU_PLATDEV(mfc_l),
+	&SYSMMU_PLATDEV(mfc_r),
+#endif
+#ifdef CONFIG_ION_EXYNOS
+	&exynos_device_ion,
+#endif
+
+	&samsung_asoc_dma,
+#ifndef CONFIG_SND_SOC_SAMSUNG_USE_DMA_WRAPPER
+	&samsung_asoc_idma,
+#endif
+
+#ifdef CONFIG_S3C64XX_DEV_SPI0
+	&exynos_device_spi0,
+#endif
+
+/* mainline fimd */
+#ifdef CONFIG_FB_S3C
+	&s5p_device_fimd0,
+#if defined(CONFIG_LCD_AMS369FG06)
+	&s3c_device_spi_gpio,
+#elif defined(CONFIG_LCD_WA101S)
+	&smdkc210_lcd_wa101s,
+#elif defined(CONFIG_LCD_LTE480WV)
+	&smdkc210_lcd_lte480wv,
+#endif
+#endif
+/* legacy fimd */
+#ifdef CONFIG_FB_S5P_AMS369FG06
+	&s3c_device_spi_gpio,
+#endif
+#ifdef CONFIG_FB_S5P_LD9040
+	&ld9040_spi_gpio,
+#endif
+#if defined(CONFIG_FB_S5P_S6C1372) || defined(CONFIG_FB_S5P_S6F1202A)
+	&lcd_s6c1372,
+#endif
+#ifdef CONFIG_FB_S5P_MDNIE
+/* &mdnie_device,*/
+#endif
+#ifdef CONFIG_VIDEO_TVOUT
+	&s5p_device_tvout,
+	&s5p_device_cec,
+	&s5p_device_hpd,
+#endif
+#ifdef CONFIG_VIDEO_FIMC
+	&s3c_device_fimc0,
+	&s3c_device_fimc1,
+	&s3c_device_fimc2,
+	&s3c_device_fimc3,
+#ifdef CONFIG_VIDEO_FIMC_MIPI
+	&s3c_device_csis0,
+	&s3c_device_csis1,
+#endif
+#endif
+#if defined(CONFIG_VIDEO_MFC5X) || defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC)
+	&s5p_device_mfc,
+#endif
+#ifdef CONFIG_VIDEO_FIMG2D
+	&s5p_device_fimg2d,
+#endif
+#ifdef CONFIG_VIDEO_JPEG
+	&s5p_device_jpeg,
+#endif
+#if defined CONFIG_USB_EHCI_S5P && !defined CONFIG_LINK_DEVICE_HSIC
+	&s5p_device_ehci,
+#endif
+#if defined CONFIG_USB_OHCI_S5P && !defined CONFIG_LINK_DEVICE_HSIC
+	&s5p_device_ohci,
+#endif
+#ifdef CONFIG_USB_GADGET
+	&s3c_device_usbgadget,
+#endif
+#ifdef CONFIG_USB_ANDROID_RNDIS
+	&s3c_device_rndis,
+#endif
+#if defined(CONFIG_USB_ANDROID) || defined(CONFIG_USB_G_ANDROID)
+	&s3c_device_android_usb,
+	&s3c_device_usb_mass_storage,
+#endif
+#ifdef CONFIG_HAVE_PWM
+	&s3c_device_timer[0],
+	&s3c_device_timer[1],
+	&s3c_device_timer[2],
+	&s3c_device_timer[3],
+#endif
+#ifdef CONFIG_EXYNOS4_SETUP_THERMAL
+	&s5p_device_tmu,
+#endif
+#ifdef CONFIG_BT_BCM4330
+	&bcm4330_bluetooth_device,
+#endif
+#ifdef CONFIG_BT_CSR8811
+	&csr8811_bluetooth_device,
+#endif
+#ifdef CONFIG_S5P_DEV_ACE
+	&s5p_device_ace,
+#endif
+	&exynos4_busfreq,
+#ifdef CONFIG_SEC_DEV_JACK
+	&sec_device_jack,
+#endif
+#if (defined(CONFIG_30PIN_CONN) && defined(CONFIG_USB_HOST_NOTIFY))
+	&host_notifier_device,
+#endif
+#if defined(CONFIG_IR_REMOCON)
+/* IR_LED */
+	&ir_remote_device,
+/* IR_LED */
+#endif
+#ifdef CONFIG_30PIN_CONN
+	&sec_device_connector,
+#ifdef CONFIG_SEC_KEYBOARD_DOCK
+	&sec_keyboard,
+#endif
+#endif
+};
+
+#ifdef CONFIG_EXYNOS4_SETUP_THERMAL
+/* below temperature base on the celcius degree */
+struct s5p_platform_tmu px_tmu_data __initdata = {
+	.ts = {
+		.stop_1st_throttle  = 61,
+		.start_1st_throttle = 64,
+		.stop_2nd_throttle  = 87,
+		.start_2nd_throttle = 103,
+		.start_tripping     = 110,
+		.start_emergency    = 120,
+		.stop_mem_throttle  = 80,
+		.start_mem_throttle = 85,
+	},
+	.cpufreq = {
+		.limit_1st_throttle  = 800000, /* 800MHz in KHz order */
+		.limit_2nd_throttle  = 200000, /* 200MHz in KHz order */
+	},
+};
+#endif
+
+#if defined CONFIG_USB_OHCI_S5P && defined CONFIG_LINK_DEVICE_HSIC
+static int __init s5p_ohci_device_initcall(void)
+{
+	return platform_device_register(&s5p_device_ohci);
+}
+late_initcall(s5p_ohci_device_initcall);
+#endif
+#if defined CONFIG_USB_EHCI_S5P && defined CONFIG_LINK_DEVICE_HSIC
+static int __init s5p_ehci_device_initcall(void)
+{
+	return platform_device_register(&s5p_device_ehci);
+}
+late_initcall(s5p_ehci_device_initcall);
+#endif
+
+#if defined(CONFIG_VIDEO_TVOUT)
+static struct s5p_platform_hpd hdmi_hpd_data __initdata = {
+
+};
+
+static struct s5p_platform_cec hdmi_cec_data __initdata = {
+
+};
+#endif
+
+static void __init smdkc210_smsc911x_init(void)
+{
+	u32 cs1;
+
+	/* configure nCS1 width to 16 bits */
+	cs1 = __raw_readl(S5P_SROM_BW) &
+		~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
+	cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
+		(1 << S5P_SROM_BW__WAITENABLE__SHIFT) |
+		(1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
+		S5P_SROM_BW__NCS1__SHIFT;
+	__raw_writel(cs1, S5P_SROM_BW);
+
+	/* set timing for nCS1 suitable for ethernet chip */
+	__raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
+		     (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
+		     (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
+		     (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
+		     (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
+		     (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
+		     (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
+}
+
+#if defined(CONFIG_S5P_MEM_CMA)
+static void __init exynos4_cma_region_reserve(struct cma_region *regions_normal,
+					      struct cma_region *regions_secure)
+{
+	struct cma_region *reg;
+	size_t size_secure = 0, align_secure = 0;
+	phys_addr_t paddr = 0;
+
+	for (reg = regions_normal; reg->size != 0; reg++) {
+		if (WARN_ON(cma_early_region_register(reg)))
+			continue;
+
+		if ((reg->alignment & (reg->alignment - 1)) || reg->reserved)
+			continue;
+
+		if (reg->start) {
+			if (!memblock_is_region_reserved(reg->start, reg->size)
+			    && memblock_reserve(reg->start, reg->size) >= 0)
+				reg->reserved = 1;
+		} else {
+			paddr = __memblock_alloc_base(reg->size, reg->alignment,
+						      MEMBLOCK_ALLOC_ACCESSIBLE);
+			if (paddr) {
+				reg->start = paddr;
+				reg->reserved = 1;
+			}
+		}
+	}
+
+	if (regions_secure && regions_secure->size) {
+		for (reg = regions_secure; reg->size != 0; reg++)
+			size_secure += reg->size;
+
+		reg--;
+
+		align_secure = reg->alignment;
+		BUG_ON(align_secure & (align_secure - 1));
+
+		paddr -= size_secure;
+		paddr &= ~(align_secure - 1);
+
+		if (!memblock_reserve(paddr, size_secure)) {
+			do {
+				reg->start = paddr;
+				reg->reserved = 1;
+				paddr += reg->size;
+
+				if (WARN_ON(cma_early_region_register(reg)))
+					memblock_free(reg->start, reg->size);
+			} while (reg-- != regions_secure);
+		}
+	}
+}
+
+static void __init exynos4_reserve_mem(void)
+{
+	static struct cma_region regions[] = {
+#ifdef CONFIG_ANDROID_PMEM_MEMSIZE_PMEM
+		{
+			.name = "pmem",
+			.size = CONFIG_ANDROID_PMEM_MEMSIZE_PMEM * SZ_1K,
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_ANDROID_PMEM_MEMSIZE_PMEM_GPU1
+		{
+			.name = "pmem_gpu1",
+			.size = CONFIG_ANDROID_PMEM_MEMSIZE_PMEM_GPU1 * SZ_1K,
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMD
+		{
+			.name = "fimd",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMD * SZ_1K,
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC0
+		{
+			.name = "fimc0",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC0 * SZ_1K,
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC1
+		{
+			.name = "fimc1",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC1 * SZ_1K,
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC2
+		{
+			.name = "fimc2",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC2 * SZ_1K,
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC3
+		{
+			.name = "fimc3",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC3 * SZ_1K,
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC1
+		{
+			.name = "mfc1",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC1 * SZ_1K,
+			{
+				.alignment = 1 << 17,
+			},
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC0
+		{
+			.name = "mfc0",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC0 * SZ_1K,
+			{
+				.alignment = 1 << 17,
+			},
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC
+		{
+			.name = "mfc",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC * SZ_1K,
+			{
+				.alignment = 1 << 17,
+			},
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_JPEG
+		{
+			.name = "jpeg",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_JPEG * SZ_1K,
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_AUDIO_SAMSUNG_MEMSIZE_SRP
+		{
+			.name = "srp",
+			.size = CONFIG_AUDIO_SAMSUNG_MEMSIZE_SRP * SZ_1K,
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMG2D
+		{
+			.name = "fimg2d",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMG2D * SZ_1K,
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_TVOUT
+		{
+			.name = "tvout",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_TVOUT * SZ_1K,
+			.start = 0,
+		},
+#endif
+		{
+			.size = 0,
+		},
+	};
+
+	static const char map[] __initconst =
+		"android_pmem.0=pmem;android_pmem.1=pmem_gpu1;"
+		"s3cfb.0=fimd;exynos4-fb.0=fimd;"
+		"s3c-fimc.0=fimc0;s3c-fimc.1=fimc1;s3c-fimc.2=fimc2;"
+		"exynos4210-fimc.0=fimc0;exynos4210-fimc.1=fimc1;exynos4210-fimc.2=fimc2;exynos4210-fimc3=fimc3;"
+#ifdef CONFIG_VIDEO_MFC5X
+		"s3c-mfc/A=mfc0,mfc-secure;"
+		"s3c-mfc/B=mfc1,mfc-normal;"
+		"s3c-mfc/AB=mfc;"
+#endif
+		"samsung-rp=srp;"
+		"s5p-jpeg=jpeg;"
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_IS
+		"exynos4-fimc-is=fimc_is;"
+#endif
+		"s5p-fimg2d=fimg2d;"
+		"s5p-tvout=tvout";
+
+	cma_set_defaults(regions, map);
+	exynos4_cma_region_reserve(regions, NULL);
+
+}
+#endif
+
+static void __init exynos_sysmmu_init(void)
+{
+	ASSIGN_SYSMMU_POWERDOMAIN(fimc0, &exynos4_device_pd[PD_CAM].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(fimc1, &exynos4_device_pd[PD_CAM].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(fimc2, &exynos4_device_pd[PD_CAM].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(fimc3, &exynos4_device_pd[PD_CAM].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(jpeg, &exynos4_device_pd[PD_CAM].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(fimd0, &exynos4_device_pd[PD_LCD0].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(2d, &exynos4_device_pd[PD_LCD0].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(rot, &exynos4_device_pd[PD_LCD0].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(tv, &exynos4_device_pd[PD_TV].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(mfc_l, &exynos4_device_pd[PD_MFC].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(mfc_r, &exynos4_device_pd[PD_MFC].dev);
+#if defined CONFIG_VIDEO_FIMC
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc0).dev, &s3c_device_fimc0.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc1).dev, &s3c_device_fimc1.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc2).dev, &s3c_device_fimc2.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc3).dev, &s3c_device_fimc3.dev);
+#elif defined CONFIG_VIDEO_SAMSUNG_S5P_FIMC
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc0).dev, &s5p_device_fimc0.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc1).dev, &s5p_device_fimc1.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc2).dev, &s5p_device_fimc2.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc3).dev, &s5p_device_fimc3.dev);
+#endif
+#ifdef CONFIG_VIDEO_JPEG
+	sysmmu_set_owner(&SYSMMU_PLATDEV(jpeg).dev, &s5p_device_jpeg.dev);
+#endif
+#ifdef CONFIG_FB_S3C
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimd0).dev, &s5p_device_fimd0.dev);
+#endif
+#ifdef CONFIG_VIDEO_FIMG2D
+	sysmmu_set_owner(&SYSMMU_PLATDEV(2d).dev, &s5p_device_fimg2d.dev);
+#endif
+#ifdef CONFIG_VIDEO_TVOUT
+	sysmmu_set_owner(&SYSMMU_PLATDEV(tv).dev, &s5p_device_tvout.dev);
+#endif
+#if defined(CONFIG_VIDEO_MFC5X) || defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC)
+	sysmmu_set_owner(&SYSMMU_PLATDEV(mfc_l).dev, &s5p_device_mfc.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(mfc_r).dev, &s5p_device_mfc.dev);
+#endif
+}
+
+static void __init smdkc210_map_io(void)
+{
+	clk_xusbxti.rate = 24000000;
+
+	s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+	s3c24xx_init_clocks(24000000);
+	s3c24xx_init_uarts(smdkc210_uartcfgs, ARRAY_SIZE(smdkc210_uartcfgs));
+
+#if defined(CONFIG_S5P_MEM_CMA)
+	exynos4_reserve_mem();
+#else
+	s5p_reserve_mem(S5P_RANGE_MFC);
+#endif
+
+	/* as soon as INFORM3 is visible, sec_debug is ready to run */
+	sec_debug_init();
+}
+
+static void __init universal_tsp_init(void)
+{
+	int gpio;
+	int gpio_touch_id = 0;
+
+#if !defined(CONFIG_TOUCHSCREEN_MMS152)
+	/* TSP_LDO_ON: XMDMADDR_11 */
+	gpio = GPIO_TSP_LDO_ON;
+	gpio_request(gpio, "TSP_LDO_ON");
+	gpio_direction_output(gpio, 1);
+	gpio_export(gpio, 0);
+#endif
+
+#if defined(CONFIG_TOUCHSCREEN_MXT1386) || defined(CONFIG_TOUCHSCREEN_MMS152) \
+	|| defined(CONFIG_RMI4_I2C)
+	gpio = GPIO_TSP_RST;
+	gpio_request(gpio, "TSP_RST");
+	gpio_direction_output(gpio, 1);
+	gpio_export(gpio, 0);
+#endif
+
+#if defined(CONFIG_MACH_P8)
+	/* TSP_INT: XMDMADDR_7 */
+	gpio = GPIO_TSP_INT_18V;
+	gpio_request(gpio, "TSP_INT_18V");
+#else
+	gpio = GPIO_TSP_INT;
+	gpio_request(gpio, "TSP_INT");
+#endif
+	s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
+	s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+#if defined(CONFIG_TOUCHSCREEN_MXT1386)	\
+	&& defined(CONFIG_RMI4_I2C)
+	i2c_devs3_mxt[0].irq = gpio_to_irq(gpio);
+	i2c_devs3_syn[0].irq = gpio_to_irq(gpio);
+#else
+	i2c_devs3[0].irq = gpio_to_irq(gpio);
+#endif
+
+	printk(KERN_INFO "%s touch irq : %d, system_rev : %d\n",
+		__func__, gpio_to_irq(gpio), system_rev);
+
+#if defined(CONFIG_TOUCHSCREEN_MMS152)
+
+	gpio = GPIO_TSP_VENDOR1;
+	gpio_request(gpio, "GPIO_TSP_VENDOR1");
+	s3c_gpio_cfgpin(gpio, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+
+	gpio = GPIO_TSP_VENDOR2;
+	gpio_request(gpio, "GPIO_TSP_VENDOR2");
+	s3c_gpio_cfgpin(gpio, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+
+
+	s3c_gpio_cfgpin(GPIO_TSP_RST, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TSP_RST, S3C_GPIO_PULL_NONE);
+
+	if (system_rev < 3) {
+		gpio_touch_id = gpio_get_value(GPIO_TSP_VENDOR1);
+	} else {
+		gpio_touch_id = gpio_get_value(GPIO_TSP_VENDOR1)
+					+ gpio_get_value(GPIO_TSP_VENDOR2)*2;
+	}
+	printk(KERN_ERR "[TSP] %s : gpio_touch_id = %d, system_rev = %d\n",
+			__func__, gpio_touch_id, system_rev);
+	ts_data.gpio_touch_id = gpio_touch_id;
+
+#endif
+
+}
+
+static void __init smdkc210_machine_init(void)
+{
+#ifdef CONFIG_S3C64XX_DEV_SPI0
+	struct clk *sclk = NULL;
+	struct clk *prnt = NULL;
+	struct device *spi0_dev = &exynos_device_spi0.dev;
+#endif
+
+	/* initialise the gpios */
+#if defined(CONFIG_MACH_P2)
+	p2_config_gpio_table();
+	exynos4_sleep_gpio_table_set = p2_config_sleep_gpio_table;
+#elif defined(CONFIG_MACH_P8)
+	p8_config_gpio_table();
+	exynos4_sleep_gpio_table_set = p8_config_sleep_gpio_table;
+#else /* CONFIG_MACH_P4 */
+	p4_config_gpio_table();
+	exynos4_sleep_gpio_table_set = p4_config_sleep_gpio_table;
+#endif
+
+#ifdef CONFIG_MACH_PX
+	config_wlan_gpio();
+#endif
+
+#if defined(CONFIG_EXYNOS4_DEV_PD) && defined(CONFIG_PM_RUNTIME)
+	exynos_pd_disable(&exynos4_device_pd[PD_MFC].dev);
+	exynos_pd_disable(&exynos4_device_pd[PD_G3D].dev);
+	exynos_pd_disable(&exynos4_device_pd[PD_LCD0].dev);
+	exynos_pd_disable(&exynos4_device_pd[PD_LCD1].dev);
+	exynos_pd_disable(&exynos4_device_pd[PD_CAM].dev);
+	exynos_pd_disable(&exynos4_device_pd[PD_TV].dev);
+	exynos_pd_disable(&exynos4_device_pd[PD_GPS].dev);
+
+#elif defined(CONFIG_EXYNOS_DEV_PD)
+	/*
+	 * These power domains should be always on
+	 * without runtime pm support.
+	 */
+	exynos_pd_enable(&exynos4_device_pd[PD_MFC].dev);
+	exynos_pd_enable(&exynos4_device_pd[PD_G3D].dev);
+	exynos_pd_enable(&exynos4_device_pd[PD_LCD0].dev);
+	exynos_pd_enable(&exynos4_device_pd[PD_LCD1].dev);
+	exynos_pd_enable(&exynos4_device_pd[PD_CAM].dev);
+	exynos_pd_enable(&exynos4_device_pd[PD_TV].dev);
+	exynos_pd_enable(&exynos4_device_pd[PD_GPS].dev);
+#endif
+#ifdef CONFIG_I2C_S3C2410
+	s3c_i2c0_set_platdata(NULL);
+	i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
+
+#ifdef CONFIG_S3C_DEV_I2C1
+
+#ifdef CONFIG_MPU_SENSORS_MPU3050
+	ak8975_init();
+	mpu3050_init();
+	s3c_i2c1_set_platdata(NULL);
+	i2c_register_board_info(1, i2c_mpu_sensor_board_info
+			, ARRAY_SIZE(i2c_mpu_sensor_board_info));
+#else
+	s3c_i2c1_set_platdata(NULL);
+	i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
+#endif
+#endif
+
+#ifdef CONFIG_S3C_DEV_I2C2
+	s3c_i2c2_set_platdata(NULL);
+	i2c_register_board_info(2, i2c_devs2, ARRAY_SIZE(i2c_devs2));
+#endif
+#ifdef CONFIG_S3C_DEV_I2C3
+	universal_tsp_init();
+#if defined(CONFIG_TOUCHSCREEN_MXT1386) \
+	&& defined(CONFIG_RMI4_I2C)
+	if (system_rev >= 13)
+		i2c_register_board_info(3, i2c_devs3_syn,
+			ARRAY_SIZE(i2c_devs3_syn));
+	else {
+		i2c_register_board_info(3, i2c_devs3_mxt,
+			ARRAY_SIZE(i2c_devs3_mxt));
+		i2c3_data.frequency = 100 * 1000;
+	}
+	s3c_i2c3_set_platdata(&i2c3_data);
+#else
+	s3c_i2c3_set_platdata(NULL);
+	i2c_register_board_info(3, i2c_devs3, ARRAY_SIZE(i2c_devs3));
+#endif
+#endif
+#ifdef CONFIG_S3C_DEV_I2C4
+#ifdef CONFIG_EPEN_WACOM_G5SP
+	p4w_wacom_init();
+#endif /* CONFIG_EPEN_WACOM_G5SP */
+	s3c_i2c4_set_platdata(NULL);
+	i2c_register_board_info(4, i2c_devs4, ARRAY_SIZE(i2c_devs4));
+#endif
+#ifdef CONFIG_S3C_DEV_I2C5
+	s3c_i2c5_set_platdata(NULL);
+	s3c_gpio_cfgpin(GPIO_PMIC_IRQ, S3C_GPIO_SFN(0xF));
+	s3c_gpio_setpull(GPIO_PMIC_IRQ, S3C_GPIO_PULL_NONE);
+	i2c_devs5[0].irq = gpio_to_irq(GPIO_PMIC_IRQ);
+	i2c_register_board_info(5, i2c_devs5, ARRAY_SIZE(i2c_devs5));
+#endif
+
+#if defined(CONFIG_MACH_P4) || defined(CONFIG_MACH_P2)
+#ifdef CONFIG_VIBETONZ
+	if (system_rev >= 3)
+		max8997_motor.pwm_id = 0;
+#endif
+#endif
+
+#ifdef CONFIG_S3C_DEV_I2C6
+	s3c_i2c6_set_platdata(NULL);
+	i2c_register_board_info(6, i2c_devs6, ARRAY_SIZE(i2c_devs6));
+#endif
+#ifdef CONFIG_S3C_DEV_I2C7
+#ifdef CONFIG_VIDEO_TVOUT
+	s3c_i2c7_set_platdata(&default_i2c7_data);
+#else
+	s3c_i2c7_set_platdata(NULL);
+#endif
+	i2c_register_board_info(7, i2c_devs7, ARRAY_SIZE(i2c_devs7));
+#endif
+#ifdef CONFIG_SAMSUNG_MHL
+	printk(KERN_INFO "%s() register sii9234 driver\n", __func__);
+
+	i2c_register_board_info(15, tuna_i2c15_boardinfo,
+			ARRAY_SIZE(tuna_i2c15_boardinfo));
+#endif
+#ifdef CONFIG_S3C_DEV_I2C8_EMUL
+	i2c_register_board_info(8, i2c_devs8_emul, ARRAY_SIZE(i2c_devs8_emul));
+	gpio_request(GPIO_3_TOUCH_INT, "sec_touchkey");
+	s5p_register_gpio_interrupt(GPIO_3_TOUCH_INT);
+
+#endif
+#ifdef CONFIG_S3C_DEV_I2C9_EMUL
+	i2c_register_board_info(9, i2c_devs9_emul, ARRAY_SIZE(i2c_devs9_emul));
+#endif
+#ifdef CONFIG_S3C_DEV_I2C10_EMUL
+	i2c_register_board_info(10, i2c_devs10_emul,
+				ARRAY_SIZE(i2c_devs10_emul));
+#endif
+#ifdef CONFIG_S3C_DEV_I2C11_EMUL
+
+#ifdef CONFIG_OPTICAL_GP2A
+	#if defined(CONFIG_OPTICAL_WAKE_ENABLE)
+	if (system_rev >= 0x03)
+		i2c_register_board_info(11, i2c_wake_devs11, ARRAY_SIZE(i2c_wake_devs11));
+	else
+		i2c_register_board_info(11, i2c_devs11, ARRAY_SIZE(i2c_devs11));
+	#else
+	/* optical sensor */
+	i2c_register_board_info(11, i2c_devs11, ARRAY_SIZE(i2c_devs11));
+	#endif
+#else
+	light_sensor_init();
+	i2c_register_board_info(11, i2c_bh1721_emul, ARRAY_SIZE(i2c_bh1721_emul));
+#endif
+#endif
+
+#ifdef CONFIG_S3C_DEV_I2C14_EMUL
+	nfc_setup_gpio();
+	i2c_register_board_info(14, i2c_devs14, ARRAY_SIZE(i2c_devs14));
+#endif
+
+#if defined(CONFIG_SMB136_CHARGER)
+	/* smb charger */
+	smb_gpio_init();
+	i2c_register_board_info(12, i2c_devs12_emul,
+				ARRAY_SIZE(i2c_devs12_emul));
+#endif
+#if defined(CONFIG_SMB347_CHARGER)
+	if (system_rev >= 02) {
+		printk(KERN_INFO "%s : Add smb347 charger.\n", __func__);
+		/* smb charger */
+		smb_gpio_init();
+		i2c_register_board_info(12, i2c_devs12_emul,
+					ARRAY_SIZE(i2c_devs12_emul));
+		platform_device_register(&s3c_device_i2c12);
+	}
+#endif
+
+	/* I2C13 EMUL */
+#if 0 /*defined(CONFIG_VIDEO_SR200PC20) && defined(CONFIG_MACH_P4W_REV01)*/
+	if (system_rev < 2)
+		platform_device_register(&s3c_device_i2c13);
+#endif
+
+#if defined(CONFIG_MHL_SII9234)
+	sii9234_init();
+	i2c_register_board_info(15, i2c_devs15, ARRAY_SIZE(i2c_devs15));
+#endif
+#ifdef CONFIG_S3C_DEV_I2C16_EMUL
+	i2c_register_board_info(16, i2c_devs16, ARRAY_SIZE(i2c_devs16));
+#endif
+#endif
+	smdkc210_smsc911x_init();
+
+	/* 400 kHz for initialization of MMC Card  */
+	__raw_writel((__raw_readl(EXYNOS4_CLKDIV_FSYS3) & 0xfffffff0)
+		     | 0x9, EXYNOS4_CLKDIV_FSYS3);
+	__raw_writel((__raw_readl(EXYNOS4_CLKDIV_FSYS2) & 0xfff0fff0)
+		     | 0x80008, EXYNOS4_CLKDIV_FSYS2);
+	__raw_writel((__raw_readl(EXYNOS4_CLKDIV_FSYS1) & 0xfff0fff0)
+		     | 0x90009, EXYNOS4_CLKDIV_FSYS1);
+
+#ifdef CONFIG_S3C_DEV_HSMMC
+	s3c_sdhci0_set_platdata(&exynos4_hsmmc0_pdata);
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC1
+	s3c_sdhci1_set_platdata(&exynos4_hsmmc1_pdata);
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC2
+	s3c_sdhci2_set_platdata(&exynos4_hsmmc2_pdata);
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC3
+	s3c_sdhci3_set_platdata(&exynos4_hsmmc3_pdata);
+#endif
+
+#ifdef CONFIG_EXYNOS4_DEV_MSHC
+	s3c_mshci_set_platdata(&exynos4_mshc_pdata);
+#endif
+
+#ifdef CONFIG_FB_S3C
+#ifdef CONFIG_LCD_AMS369FG06
+	spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
+#endif
+	s5p_fimd0_set_platdata(&smdkc210_lcd0_pdata);
+#ifdef CONFIG_EXYNOS_DEV_PD
+	s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
+#endif
+#endif
+
+#ifdef CONFIG_FB_S5P
+#ifdef CONFIG_FB_S5P_AMS369FG06
+	spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
+	s3cfb_set_platdata(&ams369fg06_data);
+#else
+	s3cfb_set_platdata(NULL);
+#endif
+#ifdef CONFIG_EXYNOS_DEV_PD
+	s3c_device_fb.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
+#endif
+#endif
+
+#ifdef CONFIG_EXYNOS_DEV_PD
+#ifdef CONFIG_VIDEO_JPEG
+	s5p_device_jpeg.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+#endif
+#endif
+#if defined(CONFIG_VIDEO_TVOUT)
+	s5p_hdmi_hpd_set_platdata(&hdmi_hpd_data);
+	s5p_hdmi_cec_set_platdata(&hdmi_cec_data);
+#ifdef CONFIG_EXYNOS_DEV_PD
+	s5p_device_tvout.dev.parent = &exynos4_device_pd[PD_TV].dev;
+#endif
+#endif
+#ifdef CONFIG_TOUCHSCREEN_S3C2410
+#ifdef CONFIG_S3C_DEV_ADC
+	s3c24xx_ts_set_platdata(&s3c_ts_platform);
+#endif
+#ifdef CONFIG_S3C_DEV_ADC1
+	s3c24xx_ts1_set_platdata(&s3c_ts_platform);
+#endif
+#endif
+#ifdef CONFIG_ANDROID_PMEM
+	android_pmem_set_platdata();
+#endif
+#ifdef CONFIG_VIDEO_FIMC
+	/* fimc */
+	s3c_fimc0_set_platdata(&fimc_plat);
+	s3c_fimc1_set_platdata(NULL);
+	s3c_fimc2_set_platdata(&fimc_plat);
+	s3c_fimc3_set_platdata(NULL);
+#ifdef CONFIG_VIDEO_FIMC_MIPI
+	s3c_csis0_set_platdata(NULL);
+	s3c_csis1_set_platdata(NULL);
+#endif
+#endif
+
+#ifdef CONFIG_EXYNOS_DEV_PD
+#ifdef CONFIG_VIDEO_FIMC
+	s3c_device_fimc0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+	s3c_device_fimc1.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+	s3c_device_fimc2.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+	s3c_device_fimc3.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+#endif
+#endif
+#ifdef CONFIG_ION_EXYNOS
+	exynos_ion_set_platdata();
+#endif
+
+#ifdef CONFIG_EXYNOS4_SETUP_THERMAL
+	s5p_tmu_set_platdata(&px_tmu_data);
+#endif
+#if defined(CONFIG_VIDEO_MFC5X) || defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC)
+#ifdef CONFIG_EXYNOS_DEV_PD
+	s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
+#endif
+#endif
+
+#if defined(CONFIG_VIDEO_MFC5X)
+	exynos4_mfc_setup_clock(&s5p_device_fimd0.dev, 200 * MHZ);
+#endif
+#if defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC)
+	dev_set_name(&s5p_device_mfc.dev, "s3c-mfc");
+	clk_add_alias("mfc", "s5p-mfc", "mfc", &s5p_device_mfc.dev);
+	s5p_mfc_setname(&s5p_device_mfc, "s5p-mfc");
+#endif
+
+#ifdef CONFIG_VIDEO_FIMG2D
+	s5p_fimg2d_set_platdata(&fimg2d_data);
+#ifdef CONFIG_EXYNOS_DEV_PD
+	s5p_device_fimg2d.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
+#endif
+#endif
+#ifdef CONFIG_USB_EHCI_S5P
+	smdkc210_ehci_init();
+#endif
+#ifdef CONFIG_USB_OHCI_S5P
+	smdkc210_ohci_init();
+#endif
+#ifdef CONFIG_USB_GADGET
+	smdkc210_usbgadget_init();
+#endif
+	platform_add_devices(smdkc210_devices, ARRAY_SIZE(smdkc210_devices));
+
+#ifdef CONFIG_BACKLIGHT_PWM
+	smdk_backlight_register();
+#endif
+#if defined(CONFIG_FB_S5P_MDNIE) && defined(CONFIG_MACH_PX)
+	mdnie_device_register();
+#endif
+#ifdef CONFIG_FB_S5P_LD9040
+	ld9040_fb_init();
+#endif
+#if defined(CONFIG_FB_S5P_S6C1372) || defined(CONFIG_FB_S5P_S6F1202A)
+	s6c1372_panel_gpio_init();
+#endif
+#if defined(CONFIG_FB_S5P_MIPI_DSIM)
+	mipi_fb_init();
+#endif
+
+#ifdef CONFIG_SND_SOC_U1_MC1N2
+	u1_sound_init();
+#endif
+
+#ifdef CONFIG_30PIN_CONN
+	smdk_accessory_gpio_init();
+#endif
+
+	exynos_sysmmu_init();
+
+
+#ifdef CONFIG_SEC_THERMISTOR
+	platform_device_register(&sec_device_thermistor);
+#endif
+
+#ifdef CONFIG_FB_S3C
+	exynos4_fimd0_setup_clock(&s5p_device_fimd0.dev, "mout_mpll",
+				  800 * MHZ);
+#endif
+
+#ifdef CONFIG_S3C64XX_DEV_SPI0
+	sclk = clk_get(spi0_dev, "sclk_spi");
+	if (IS_ERR(sclk))
+		dev_err(spi0_dev, "failed to get sclk for SPI-0\n");
+	prnt = clk_get(spi0_dev, "mout_mpll");
+	if (IS_ERR(prnt))
+		dev_err(spi0_dev, "failed to get prnt\n");
+	clk_set_parent(sclk, prnt);
+
+	clk_put(sclk);
+	clk_put(prnt);
+
+	if (!gpio_request(EXYNOS4_GPB(1), "SPI_CS0")) {
+		gpio_direction_output(EXYNOS4_GPB(1), 1);
+		s3c_gpio_cfgpin(EXYNOS4_GPB(1), S3C_GPIO_SFN(1));
+		s3c_gpio_setpull(EXYNOS4_GPB(1), S3C_GPIO_PULL_UP);
+		exynos_spi_set_info(0, EXYNOS_SPI_SRCCLK_SCLK,
+				    ARRAY_SIZE(spi0_csi));
+	}
+	spi_register_board_info(spi0_board_info, ARRAY_SIZE(spi0_board_info));
+#endif
+
+#ifdef CONFIG_BUSFREQ_OPP
+	dev_add(&busfreq, &exynos4_busfreq.dev);
+#endif
+
+	cam_init();
+#if defined(CONFIG_IR_REMOCON)
+/* IR_LED */
+	ir_rc_init_hw();
+/* IR_LED */
+#endif
+}
+
+static void __init exynos_init_reserve(void)
+{
+	sec_debug_magic_init();
+}
+
+MACHINE_START(SMDKC210, "SMDK4210")
+	/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
+	.boot_params	= S5P_PA_SDRAM + 0x100,
+	.init_irq	= exynos4_init_irq,
+	.map_io		= smdkc210_map_io,
+	.init_machine	= smdkc210_machine_init,
+	.timer		= &exynos4_timer,
+	.init_early	= &exynos_init_reserve,
+MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c b/arch/arm/mach-exynos/mach-smdk4x12.c
new file mode 100644
index 0000000..97daba2
--- /dev/null
+++ b/arch/arm/mach-exynos/mach-smdk4x12.c
@@ -0,0 +1,4388 @@
+/* linux/arch/arm/mach-exynos/mach-smdk4x12.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/platform_device.h>
+#include <linux/serial_core.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi_gpio.h>
+#include <linux/clk.h>
+#include <linux/lcd.h>
+#include <linux/gpio.h>
+#include <linux/gpio_event.h>
+#include <linux/i2c.h>
+#include <linux/pwm_backlight.h>
+#include <linux/input.h>
+#include <linux/mmc/host.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/max8649.h>
+#include <linux/regulator/fixed.h>
+#include <linux/mfd/wm8994/pdata.h>
+#include <linux/mfd/max8997.h>
+#include <linux/mfd/max77686.h>
+#include <linux/v4l2-mediabus.h>
+#include <linux/memblock.h>
+#include <linux/delay.h>
+#include <linux/smsc911x.h>
+#include <linux/notifier.h>
+#include <linux/reboot.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <plat/regs-serial.h>
+#include <plat/exynos4.h>
+#include <plat/cpu.h>
+#include <plat/clock.h>
+#include <plat/keypad.h>
+#include <plat/devs.h>
+#include <plat/fb.h>
+#include <plat/fb-s5p.h>
+#include <plat/fb-core.h>
+#include <plat/regs-fb-v4.h>
+#include <plat/backlight.h>
+#include <plat/gpio-cfg.h>
+#include <plat/regs-adc.h>
+#include <plat/adc.h>
+#include <plat/iic.h>
+#include <plat/pd.h>
+#include <plat/sdhci.h>
+#include <plat/mshci.h>
+#include <plat/ehci.h>
+#include <plat/usbgadget.h>
+#include <plat/usb-switch.h>
+#include <plat/s3c64xx-spi.h>
+#if defined(CONFIG_VIDEO_FIMC)
+#include <plat/fimc.h>
+#elif defined(CONFIG_VIDEO_SAMSUNG_S5P_FIMC)
+#include <plat/fimc-core.h>
+#include <media/s5p_fimc.h>
+#endif
+#if defined(CONFIG_VIDEO_FIMC_MIPI)
+#include <plat/csis.h>
+#elif defined(CONFIG_VIDEO_S5P_MIPI_CSIS)
+#include <plat/mipi_csis.h>
+#endif
+#include <plat/tvout.h>
+#include <plat/media.h>
+#include <plat/regs-srom.h>
+#include <plat/s5p-sysmmu.h>
+#include <plat/tv-core.h>
+#if defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC) || defined(CONFIG_VIDEO_MFC5X)
+#include <plat/s5p-mfc.h>
+#endif
+
+#include <media/s5k4ba_platform.h>
+#include <media/s5k4ea_platform.h>
+#include <media/exynos_flite.h>
+#include <media/exynos_fimc_is.h>
+#include <video/platform_lcd.h>
+#include <media/m5mo_platform.h>
+#include <media/m5mols.h>
+#include <mach/board_rev.h>
+#include <mach/map.h>
+#include <mach/spi-clocks.h>
+#include <mach/exynos-ion.h>
+#include <mach/regs-pmu.h>
+#ifdef CONFIG_EXYNOS4_DEV_DWMCI
+#include <mach/dwmci.h>
+#endif
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+#include <mach/secmem.h>
+#endif
+#include <mach/dev.h>
+#include <mach/ppmu.h>
+#ifdef CONFIG_EXYNOS_C2C
+#include <mach/c2c.h>
+#endif
+#ifdef CONFIG_FB_S5P_MIPI_DSIM
+#include <mach/mipi_ddi.h>
+#include <mach/dsim.h>
+#include <../../../drivers/video/samsung/s3cfb.h>
+#endif
+#ifdef CONFIG_FB_S5P_EXTDSP
+struct s3cfb_extdsp_lcd {
+	int	width;
+	int	height;
+	int	bpp;
+};
+#endif
+#include <plat/fimg2d.h>
+#include <mach/dev-sysmmu.h>
+
+#ifdef CONFIG_VIDEO_SAMSUNG_S5P_FIMC
+#include <plat/fimc-core.h>
+#include <media/s5p_fimc.h>
+#endif
+
+#ifdef CONFIG_VIDEO_JPEG_V2X
+#include <plat/jpeg.h>
+#endif
+
+#ifdef CONFIG_REGULATOR_S5M8767
+#include <linux/mfd/s5m87xx/s5m-core.h>
+#include <linux/mfd/s5m87xx/s5m-pmic.h>
+#endif
+
+#if defined(CONFIG_EXYNOS_SETUP_THERMAL)
+#include <plat/s5p-tmu.h>
+#endif
+
+#define REG_INFORM4            (S5P_INFORM4)
+
+/* Following are default values for UCON, ULCON and UFCON UART registers */
+#define SMDK4X12_UCON_DEFAULT	(S3C2410_UCON_TXILEVEL |	\
+				 S3C2410_UCON_RXILEVEL |	\
+				 S3C2410_UCON_TXIRQMODE |	\
+				 S3C2410_UCON_RXIRQMODE |	\
+				 S3C2410_UCON_RXFIFO_TOI |	\
+				 S3C2443_UCON_RXERR_IRQEN)
+
+#define SMDK4X12_ULCON_DEFAULT	S3C2410_LCON_CS8
+
+#define SMDK4X12_UFCON_DEFAULT	(S3C2410_UFCON_FIFOMODE |	\
+				 S5PV210_UFCON_TXTRIG4 |	\
+				 S5PV210_UFCON_RXTRIG4)
+
+static struct s3c2410_uartcfg smdk4x12_uartcfgs[] __initdata = {
+	[0] = {
+		.hwport		= 0,
+		.flags		= 0,
+		.ucon		= SMDK4X12_UCON_DEFAULT,
+		.ulcon		= SMDK4X12_ULCON_DEFAULT,
+		.ufcon		= SMDK4X12_UFCON_DEFAULT,
+	},
+	[1] = {
+		.hwport		= 1,
+		.flags		= 0,
+		.ucon		= SMDK4X12_UCON_DEFAULT,
+		.ulcon		= SMDK4X12_ULCON_DEFAULT,
+		.ufcon		= SMDK4X12_UFCON_DEFAULT,
+	},
+	[2] = {
+		.hwport		= 2,
+		.flags		= 0,
+		.ucon		= SMDK4X12_UCON_DEFAULT,
+		.ulcon		= SMDK4X12_ULCON_DEFAULT,
+		.ufcon		= SMDK4X12_UFCON_DEFAULT,
+	},
+	[3] = {
+		.hwport		= 3,
+		.flags		= 0,
+		.ucon		= SMDK4X12_UCON_DEFAULT,
+		.ulcon		= SMDK4X12_ULCON_DEFAULT,
+		.ufcon		= SMDK4X12_UFCON_DEFAULT,
+	},
+};
+
+static struct resource smdk4x12_smsc911x_resources[] = {
+	[0] = {
+		.start	= EXYNOS4_PA_SROM_BANK(1),
+		.end	= EXYNOS4_PA_SROM_BANK(1) + SZ_64K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= IRQ_EINT(5),
+		.end	= IRQ_EINT(5),
+		.flags	= IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
+	},
+};
+
+static struct smsc911x_platform_config smsc9215_config = {
+	.irq_polarity	= SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+	.irq_type	= SMSC911X_IRQ_TYPE_PUSH_PULL,
+	.flags		= SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
+	.phy_interface	= PHY_INTERFACE_MODE_MII,
+	.mac		= {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
+};
+
+static struct platform_device smdk4x12_smsc911x = {
+	.name		= "smsc911x",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(smdk4x12_smsc911x_resources),
+	.resource	= smdk4x12_smsc911x_resources,
+	.dev		= {
+		.platform_data	= &smsc9215_config,
+	},
+};
+
+#ifdef CONFIG_EXYNOS_MEDIA_DEVICE
+struct platform_device exynos_device_md0 = {
+	.name = "exynos-mdev",
+	.id = -1,
+};
+#endif
+
+#define WRITEBACK_ENABLED
+
+#if defined(CONFIG_VIDEO_FIMC) || defined(CONFIG_VIDEO_SAMSUNG_S5P_FIMC)
+/*
+ * External camera reset
+ * Because the most of cameras take i2c bus signal, so that
+ * you have to reset at the boot time for other i2c slave devices.
+ * This function also called at fimc_init_camera()
+ * Do optimization for cameras on your platform.
+*/
+#if defined(CONFIG_ITU_A) || defined(CONFIG_CSI_C) \
+	|| defined(CONFIG_S5K3H2_CSI_C) || defined(CONFIG_S5K3H7_CSI_C) \
+	|| defined(CONFIG_S5K4E5_CSI_C) || defined(CONFIG_S5K6A3_CSI_C)
+static int smdk4x12_cam0_reset(int dummy)
+{
+	int err;
+	/* Camera A */
+	err = gpio_request(EXYNOS4_GPX1(2), "GPX1");
+	if (err)
+		printk(KERN_ERR "#### failed to request GPX1_2 ####\n");
+
+	s3c_gpio_setpull(EXYNOS4_GPX1(2), S3C_GPIO_PULL_NONE);
+	gpio_direction_output(EXYNOS4_GPX1(2), 0);
+	gpio_direction_output(EXYNOS4_GPX1(2), 1);
+	gpio_free(EXYNOS4_GPX1(2));
+
+	return 0;
+}
+#endif
+#if defined(CONFIG_ITU_B) || defined(CONFIG_CSI_D) \
+	|| defined(CONFIG_S5K3H2_CSI_D) || defined(CONFIG_S5K3H7_CSI_D) \
+	|| defined(CONFIG_S5K4E5_CSI_D) || defined(CONFIG_S5K6A3_CSI_D)
+static int smdk4x12_cam1_reset(int dummy)
+{
+	int err;
+
+	/* Camera B */
+	err = gpio_request(EXYNOS4_GPX1(0), "GPX1");
+	if (err)
+		printk(KERN_ERR "#### failed to request GPX1_0 ####\n");
+
+	s3c_gpio_setpull(EXYNOS4_GPX1(0), S3C_GPIO_PULL_NONE);
+	gpio_direction_output(EXYNOS4_GPX1(0), 0);
+	gpio_direction_output(EXYNOS4_GPX1(0), 1);
+	gpio_free(EXYNOS4_GPX1(0));
+
+	return 0;
+}
+#endif
+#endif
+
+#ifdef CONFIG_VIDEO_FIMC
+#ifdef CONFIG_VIDEO_S5K4BA
+static struct s5k4ba_platform_data s5k4ba_plat = {
+	.default_width = 800,
+	.default_height = 600,
+	.pixelformat = V4L2_PIX_FMT_YUYV,
+	.freq = 24000000,
+	.is_mipi = 0,
+};
+
+static struct i2c_board_info s5k4ba_i2c_info = {
+	I2C_BOARD_INFO("S5K4BA", 0x2d),
+	.platform_data = &s5k4ba_plat,
+};
+
+static struct s3c_platform_camera s5k4ba = {
+#ifdef CONFIG_ITU_A
+	.id		= CAMERA_PAR_A,
+	.clk_name	= "sclk_cam0",
+	.i2c_busnum	= 4,
+	.cam_power	= smdk4x12_cam0_reset,
+#endif
+#ifdef CONFIG_ITU_B
+	.id		= CAMERA_PAR_B,
+	.clk_name	= "sclk_cam1",
+	.i2c_busnum	= 5,
+	.cam_power	= smdk4x12_cam1_reset,
+#endif
+	.type		= CAM_TYPE_ITU,
+	.fmt		= ITU_601_YCBCR422_8BIT,
+	.order422	= CAM_ORDER422_8BIT_CBYCRY,
+	.info		= &s5k4ba_i2c_info,
+	.pixelformat	= V4L2_PIX_FMT_YUYV,
+	.srclk_name	= "xusbxti",
+	.clk_rate	= 24000000,
+	.line_length	= 1920,
+	.width		= 1600,
+	.height		= 1200,
+	.window		= {
+		.left	= 0,
+		.top	= 0,
+		.width	= 1600,
+		.height	= 1200,
+	},
+
+	/* Polarity */
+	.inv_pclk	= 0,
+	.inv_vsync	= 1,
+	.inv_href	= 0,
+	.inv_hsync	= 0,
+	.reset_camera	= 1,
+	.initialized	= 0,
+};
+#endif
+
+/* 2 MIPI Cameras */
+#ifdef CONFIG_VIDEO_S5K4EA
+static struct s5k4ea_platform_data s5k4ea_plat = {
+	.default_width = 1920,
+	.default_height = 1080,
+	.pixelformat = V4L2_PIX_FMT_UYVY,
+	.freq = 24000000,
+	.is_mipi = 1,
+};
+
+static struct i2c_board_info s5k4ea_i2c_info = {
+	I2C_BOARD_INFO("S5K4EA", 0x2d),
+	.platform_data = &s5k4ea_plat,
+};
+
+static struct s3c_platform_camera s5k4ea = {
+#ifdef CONFIG_CSI_C
+	.id		= CAMERA_CSI_C,
+	.clk_name	= "sclk_cam0",
+	.i2c_busnum	= 4,
+	.cam_power	= smdk4x12_cam0_reset,
+#endif
+#ifdef CONFIG_CSI_D
+	.id		= CAMERA_CSI_D,
+	.clk_name	= "sclk_cam1",
+	.i2c_busnum	= 5,
+	.cam_power	= smdk4x12_cam1_reset,
+#endif
+	.type		= CAM_TYPE_MIPI,
+	.fmt		= MIPI_CSI_YCBCR422_8BIT,
+	.order422	= CAM_ORDER422_8BIT_YCBYCR,
+	.info		= &s5k4ea_i2c_info,
+	.pixelformat	= V4L2_PIX_FMT_UYVY,
+	.srclk_name	= "xusbxti",
+	.clk_rate	= 24000000,
+	.line_length	= 1920,
+	.width		= 1920,
+	.height		= 1080,
+	.window		= {
+		.left	= 0,
+		.top	= 0,
+		.width	= 1920,
+		.height	= 1080,
+	},
+
+	.mipi_lanes	= 2,
+	.mipi_settle	= 12,
+	.mipi_align	= 32,
+
+	/* Polarity */
+	.inv_pclk	= 0,
+	.inv_vsync	= 1,
+	.inv_href	= 0,
+	.inv_hsync	= 0,
+
+	.initialized	= 0,
+};
+#endif
+
+#ifdef WRITEBACK_ENABLED
+static struct i2c_board_info writeback_i2c_info = {
+	I2C_BOARD_INFO("WriteBack", 0x0),
+};
+
+static struct s3c_platform_camera writeback = {
+	.id		= CAMERA_WB,
+	.fmt		= ITU_601_YCBCR422_8BIT,
+	.order422	= CAM_ORDER422_8BIT_CBYCRY,
+	.i2c_busnum	= 0,
+	.info		= &writeback_i2c_info,
+	.pixelformat	= V4L2_PIX_FMT_YUV444,
+	.line_length	= 800,
+	.width		= 480,
+	.height		= 800,
+	.window		= {
+		.left	= 0,
+		.top	= 0,
+		.width	= 480,
+		.height	= 800,
+	},
+
+	.initialized	= 0,
+};
+#endif
+
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_IS
+#ifdef CONFIG_VIDEO_S5K3H2
+static struct i2c_board_info s5k3h2_sensor_info = {
+	.type = "S5K3H2",
+};
+
+static struct s3c_platform_camera s5k3h2 = {
+#ifdef CONFIG_S5K3H2_CSI_C
+	.id		= CAMERA_CSI_C,
+	.clk_name	= "sclk_cam0",
+	.cam_power	= smdk4x12_cam0_reset,
+#endif
+#ifdef CONFIG_S5K3H2_CSI_D
+	.id		= CAMERA_CSI_D,
+	.clk_name	= "sclk_cam1",
+	.cam_power	= smdk4x12_cam1_reset,
+#endif
+	.type		= CAM_TYPE_MIPI,
+	.fmt		= MIPI_CSI_RAW10,
+	.info		= &s5k3h2_sensor_info,
+	.order422	= CAM_ORDER422_8BIT_YCBYCR,
+	.pixelformat	= V4L2_PIX_FMT_UYVY,
+	.line_length	= 1920,
+	.width		= 1920,
+	.height		= 1080,
+	.window		= {
+		.left	= 0,
+		.top	= 0,
+		.width	= 1920,
+		.height	= 1080,
+	},
+	.srclk_name	= "xusbxti",
+	.clk_rate	= 24000000,
+	.mipi_lanes	= 2,
+	.mipi_settle	= 12,
+	.mipi_align	= 24,
+
+	.initialized	= 0,
+#ifdef CONFIG_S5K3H2_CSI_C
+	.flite_id	= FLITE_IDX_A,
+#endif
+#ifdef CONFIG_S5K3H2_CSI_D
+	.flite_id	= FLITE_IDX_B,
+#endif
+	.use_isp	= true,
+#ifdef CONFIG_S5K3H2_CSI_C
+	.sensor_index	= 1,
+#endif
+#ifdef CONFIG_S5K3H2_CSI_D
+	.sensor_index	= 101,
+#endif
+};
+#endif
+
+#ifdef CONFIG_VIDEO_S5K3H7
+static struct i2c_board_info s5k3h7_sensor_info = {
+	.type = "S5K3H7",
+};
+
+static struct s3c_platform_camera s5k3h7 = {
+#ifdef CONFIG_S5K3H7_CSI_C
+	.id		= CAMERA_CSI_C,
+	.clk_name	= "sclk_cam0",
+	.cam_power	= smdk4x12_cam0_reset,
+#endif
+#ifdef CONFIG_S5K3H7_CSI_D
+	.id		= CAMERA_CSI_D,
+	.clk_name	= "sclk_cam1",
+	.cam_power	= smdk4x12_cam1_reset,
+#endif
+	.type		= CAM_TYPE_MIPI,
+	.fmt		= MIPI_CSI_RAW10,
+	.info		= &s5k3h7_sensor_info,
+	.order422	= CAM_ORDER422_8BIT_YCBYCR,
+	.pixelformat	= V4L2_PIX_FMT_UYVY,
+	.line_length	= 1920,
+	.width		= 1920,
+	.height		= 1080,
+	.window		= {
+		.left	= 0,
+		.top	= 0,
+		.width	= 1920,
+		.height	= 1080,
+	},
+	.srclk_name	= "xusbxti",
+	.clk_rate	= 24000000,
+	.mipi_lanes	= 2,
+	.mipi_settle	= 12,
+	.mipi_align	= 24,
+
+	.initialized	= 0,
+#ifdef CONFIG_S5K3H7_CSI_C
+	.flite_id	= FLITE_IDX_A,
+#endif
+#ifdef CONFIG_S5K3H7_CSI_D
+	.flite_id	= FLITE_IDX_B,
+#endif
+	.use_isp	= true,
+#ifdef CONFIG_S5K3H7_CSI_C
+	.sensor_index	= 4,
+#endif
+#ifdef CONFIG_S5K3H7_CSI_D
+	.sensor_index	= 104,
+#endif
+};
+#endif
+
+#ifdef CONFIG_VIDEO_S5K4E5
+static struct i2c_board_info s5k4e5_sensor_info = {
+	.type = "S5K4E5",
+};
+
+static struct s3c_platform_camera s5k4e5 = {
+#ifdef CONFIG_S5K4E5_CSI_C
+	.id		= CAMERA_CSI_C,
+	.clk_name	= "sclk_cam0",
+	.cam_power	= smdk4x12_cam0_reset,
+#endif
+#ifdef CONFIG_S5K4E5_CSI_D
+	.id		= CAMERA_CSI_D,
+	.clk_name	= "sclk_cam1",
+	.cam_power	= smdk4x12_cam1_reset,
+#endif
+	.type		= CAM_TYPE_MIPI,
+	.fmt		= MIPI_CSI_RAW10,
+	.info		= &s5k4e5_sensor_info,
+	.order422	= CAM_ORDER422_8BIT_YCBYCR,
+	.pixelformat	= V4L2_PIX_FMT_UYVY,
+	.line_length	= 1920,
+	.width		= 1920,
+	.height		= 1080,
+	.window		= {
+		.left	= 0,
+		.top	= 0,
+		.width	= 1920,
+		.height	= 1080,
+	},
+	.srclk_name	= "xusbxti",
+	.clk_rate	= 24000000,
+	.mipi_lanes	= 2,
+	.mipi_settle	= 12,
+	.mipi_align	= 24,
+
+	.initialized	= 0,
+#ifdef CONFIG_S5K4E5_CSI_C
+	.flite_id	= FLITE_IDX_A,
+#endif
+#ifdef CONFIG_S5K4E5_CSI_D
+	.flite_id	= FLITE_IDX_B,
+#endif
+	.use_isp	= true,
+#ifdef CONFIG_S5K4E5_CSI_C
+	.sensor_index	= 3,
+#endif
+#ifdef CONFIG_S5K4E5_CSI_D
+	.sensor_index	= 103,
+#endif
+};
+#endif
+
+
+#ifdef CONFIG_VIDEO_S5K6A3
+static struct i2c_board_info s5k6a3_sensor_info = {
+	.type = "S5K6A3",
+};
+
+static struct s3c_platform_camera s5k6a3 = {
+#ifdef CONFIG_S5K6A3_CSI_C
+	.id		= CAMERA_CSI_C,
+	.clk_name	= "sclk_cam0",
+	.cam_power	= smdk4x12_cam0_reset,
+#endif
+#ifdef CONFIG_S5K6A3_CSI_D
+	.id		= CAMERA_CSI_D,
+	.clk_name	= "sclk_cam1",
+	.cam_power	= smdk4x12_cam1_reset,
+#endif
+	.type		= CAM_TYPE_MIPI,
+	.fmt		= MIPI_CSI_RAW10,
+	.info		= &s5k6a3_sensor_info,
+	.order422	= CAM_ORDER422_8BIT_YCBYCR,
+	.pixelformat	= V4L2_PIX_FMT_UYVY,
+	.line_length	= 1920,
+	.width		= 1920,
+	.height		= 1080,
+	.window		= {
+		.left	= 0,
+		.top	= 0,
+		.width	= 1920,
+		.height	= 1080,
+	},
+	.srclk_name	= "xusbxti",
+	.clk_rate	= 24000000,
+	.mipi_lanes	= 1,
+	.mipi_settle	= 18,
+	.mipi_align	= 24,
+
+	.initialized	= 0,
+#ifdef CONFIG_S5K6A3_CSI_C
+	.flite_id	= FLITE_IDX_A,
+#endif
+#ifdef CONFIG_S5K6A3_CSI_D
+	.flite_id	= FLITE_IDX_B,
+#endif
+	.use_isp	= true,
+#ifdef CONFIG_S5K6A3_CSI_C
+	.sensor_index	= 2,
+#endif
+#ifdef CONFIG_S5K6A3_CSI_D
+	.sensor_index	= 102,
+#endif
+};
+#endif
+
+#if defined(CONFIG_VIDEO_S5K6A3) && defined(CONFIG_S5K6A3_CSI_D)
+static struct i2c_board_info s5k6a3_fd_sensor_info = {
+	.type = "S5K6A3_FD",
+};
+
+static struct s3c_platform_camera s5k6a3_fd = {
+	.id		= CAMERA_CSI_D,
+	.clk_name	= "sclk_cam1",
+	.cam_power	= smdk4x12_cam1_reset,
+
+	.type		= CAM_TYPE_MIPI,
+	.fmt		= MIPI_CSI_RAW10,
+	.info		= &s5k6a3_fd_sensor_info,
+	.order422	= CAM_ORDER422_8BIT_YCBYCR,
+	.pixelformat	= V4L2_PIX_FMT_UYVY,
+	.line_length	= 1920,
+	.width		= 1920,
+	.height		= 1080,
+	.window		= {
+		.left	= 0,
+		.top	= 0,
+		.width	= 1920,
+		.height	= 1080,
+	},
+	.srclk_name	= "xusbxti",
+	.clk_rate	= 24000000,
+	.mipi_lanes	= 1,
+	.mipi_settle	= 18,
+	.mipi_align	= 24,
+
+	.initialized	= 0,
+	.flite_id	= FLITE_IDX_B,
+	.use_isp	= true,
+	.sensor_index	= 200
+};
+#endif
+
+#endif
+
+/* legacy M5MOLS Camera driver configuration */
+#ifdef CONFIG_VIDEO_M5MO
+#define CAM_CHECK_ERR_RET(x, msg)	\
+	if (unlikely((x) < 0)) { \
+		printk(KERN_ERR "\nfail to %s: err = %d\n", msg, x); \
+		return x; \
+	}
+#define CAM_CHECK_ERR(x, msg)	\
+		if (unlikely((x) < 0)) { \
+			printk(KERN_ERR "\nfail to %s: err = %d\n", msg, x); \
+		}
+
+static int m5mo_config_isp_irq(void)
+{
+	s3c_gpio_cfgpin(EXYNOS4_GPX3(3), S3C_GPIO_SFN(0xF));
+	s3c_gpio_setpull(EXYNOS4_GPX3(3), S3C_GPIO_PULL_NONE);
+	return 0;
+}
+
+static struct m5mo_platform_data m5mo_plat = {
+	.default_width = 640, /* 1920 */
+	.default_height = 480, /* 1080 */
+	.pixelformat = V4L2_PIX_FMT_UYVY,
+	.freq = 24000000,
+	.is_mipi = 1,
+	.config_isp_irq = m5mo_config_isp_irq,
+	.irq = IRQ_EINT(27),
+};
+
+static struct i2c_board_info m5mo_i2c_info = {
+	I2C_BOARD_INFO("M5MO", 0x1F),
+	.platform_data = &m5mo_plat,
+	.irq = IRQ_EINT(27),
+};
+
+static struct s3c_platform_camera m5mo = {
+#ifdef CONFIG_CSI_C
+	.id		= CAMERA_CSI_C,
+	.clk_name	= "sclk_cam0",
+	.i2c_busnum	= 4,
+	.cam_power	= smdk4x12_cam0_reset,
+#endif
+#ifdef CONFIG_CSI_D
+	.id		= CAMERA_CSI_D,
+	.clk_name	= "sclk_cam1",
+	.i2c_busnum	= 5,
+	.cam_power	= smdk4x12_cam1_reset,
+#endif
+	.type		= CAM_TYPE_MIPI,
+	.fmt		= MIPI_CSI_YCBCR422_8BIT,
+	.order422	= CAM_ORDER422_8BIT_YCBYCR,
+	.info		= &m5mo_i2c_info,
+	.pixelformat	= V4L2_PIX_FMT_UYVY,
+	.srclk_name	= "xusbxti", /* "mout_mpll" */
+	.clk_rate	= 24000000, /* 48000000 */
+	.line_length	= 1920,
+	.width		= 640,
+	.height		= 480,
+	.window		= {
+		.left	= 0,
+		.top	= 0,
+		.width	= 640,
+		.height	= 480,
+	},
+
+	.mipi_lanes	= 2,
+	.mipi_settle	= 12,
+	.mipi_align	= 32,
+
+	/* Polarity */
+	.inv_pclk	= 1,
+	.inv_vsync	= 1,
+	.inv_href	= 0,
+	.inv_hsync	= 0,
+	.reset_camera	= 0,
+	.initialized	= 0,
+};
+#endif
+
+/* Interface setting */
+static struct s3c_platform_fimc fimc_plat = {
+#ifdef CONFIG_ITU_A
+	.default_cam	= CAMERA_PAR_A,
+#endif
+#ifdef CONFIG_ITU_B
+	.default_cam	= CAMERA_PAR_B,
+#endif
+#ifdef CONFIG_CSI_C
+	.default_cam	= CAMERA_CSI_C,
+#endif
+#ifdef CONFIG_CSI_D
+	.default_cam	= CAMERA_CSI_D,
+#endif
+#ifdef WRITEBACK_ENABLED
+	.default_cam	= CAMERA_WB,
+#endif
+	.camera		= {
+#ifdef CONFIG_VIDEO_S5K4BA
+		&s5k4ba,
+#endif
+#ifdef CONFIG_VIDEO_S5K4EA
+		&s5k4ea,
+#endif
+#ifdef CONFIG_VIDEO_M5MO
+		&m5mo,
+#endif
+#ifdef CONFIG_VIDEO_S5K3H2
+		&s5k3h2,
+#endif
+#ifdef CONFIG_VIDEO_S5K3H7
+		&s5k3h7,
+#endif
+#ifdef CONFIG_VIDEO_S5K4E5
+		&s5k4e5,
+#endif
+#ifdef CONFIG_VIDEO_S5K6A3
+		&s5k6a3,
+#endif
+#ifdef WRITEBACK_ENABLED
+		&writeback,
+#endif
+#if defined(CONFIG_VIDEO_S5K6A3) && defined(CONFIG_S5K6A3_CSI_D)
+		&s5k6a3_fd,
+#endif
+	},
+	.hw_ver		= 0x51,
+};
+#endif /* CONFIG_VIDEO_FIMC */
+
+/* for mainline fimc interface */
+#ifdef CONFIG_VIDEO_SAMSUNG_S5P_FIMC
+#ifdef WRITEBACK_ENABLED
+struct writeback_mbus_platform_data {
+	int id;
+	struct v4l2_mbus_framefmt fmt;
+};
+
+static struct i2c_board_info __initdata writeback_info = {
+	I2C_BOARD_INFO("writeback", 0x0),
+};
+#endif
+
+#ifdef CONFIG_VIDEO_S5K4BA
+static struct s5k4ba_mbus_platform_data s5k4ba_mbus_plat = {
+	.id		= 0,
+	.fmt = {
+		.width	= 1600,
+		.height	= 1200,
+		/*.code	= V4L2_MBUS_FMT_UYVY8_2X8, */
+		.code	= V4L2_MBUS_FMT_VYUY8_2X8,
+	},
+	.clk_rate	= 24000000UL,
+#ifdef CONFIG_ITU_A
+	.set_power	= smdk4x12_cam0_reset,
+#endif
+#ifdef CONFIG_ITU_B
+	.set_power	= smdk4x12_cam1_reset,
+#endif
+};
+
+static struct i2c_board_info s5k4ba_info = {
+	I2C_BOARD_INFO("S5K4BA", 0x2d),
+	.platform_data = &s5k4ba_mbus_plat,
+};
+#endif
+
+/* 2 MIPI Cameras */
+#ifdef CONFIG_VIDEO_S5K4EA
+static struct s5k4ea_mbus_platform_data s5k4ea_mbus_plat = {
+#ifdef CONFIG_CSI_C
+	.id		= 0,
+	.set_power = smdk4x12_cam0_reset,
+#endif
+#ifdef CONFIG_CSI_D
+	.id		= 1,
+	.set_power = smdk4x12_cam1_reset,
+#endif
+	.fmt = {
+		.width	= 1920,
+		.height	= 1080,
+		.code	= V4L2_MBUS_FMT_VYUY8_2X8,
+	},
+	.clk_rate	= 24000000UL,
+};
+
+static struct i2c_board_info s5k4ea_info = {
+	I2C_BOARD_INFO("S5K4EA", 0x2d),
+	.platform_data = &s5k4ea_mbus_plat,
+};
+#endif
+
+#ifdef CONFIG_VIDEO_M5MOLS
+static struct m5mols_platform_data m5mols_platdata = {
+#ifdef CONFIG_CSI_C
+	.gpio_rst = EXYNOS4_GPX1(2), /* ISP_RESET */
+#endif
+#ifdef CONFIG_CSI_D
+	.gpio_rst = EXYNOS4_GPX1(0), /* ISP_RESET */
+#endif
+	.enable_rst = true, /* positive reset */
+	.irq = IRQ_EINT(27),
+};
+
+static struct i2c_board_info m5mols_board_info = {
+	I2C_BOARD_INFO("M5MOLS", 0x1F),
+	.platform_data = &m5mols_platdata,
+};
+
+#endif
+
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_IS
+#ifdef CONFIG_VIDEO_S5K3H2
+static struct i2c_board_info s5k3h2_sensor_info = {
+	.type = "S5K3H2",
+};
+#endif
+#ifdef CONFIG_VIDEO_S5K3H7
+static struct i2c_board_info s5k3h7_sensor_info = {
+	.type = "S5K3H7",
+};
+#endif
+#ifdef CONFIG_VIDEO_S5K4E5
+static struct i2c_board_info s5k4e5_sensor_info = {
+	.type = "S5K4E5",
+};
+#endif
+#ifdef CONFIG_VIDEO_S5K6A3
+static struct i2c_board_info s5k6a3_sensor_info = {
+	.type = "S5K6A3",
+};
+#endif
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_LITE
+/* This is for platdata of fimc-lite */
+#ifdef CONFIG_VIDEO_S5K3H2
+static struct s3c_platform_camera s5k3h2 = {
+	.type  = CAM_TYPE_MIPI,
+	.use_isp = true,
+	.inv_pclk = 0,
+	.inv_vsync = 0,
+	.inv_href = 0,
+	.inv_hsync = 0,
+};
+#endif
+
+#ifdef CONFIG_VIDEO_S5K3H7
+static struct s3c_platform_camera s5k3h7 = {
+	.type  = CAM_TYPE_MIPI,
+	.use_isp = true,
+	.inv_pclk = 0,
+	.inv_vsync = 0,
+	.inv_href = 0,
+	.inv_hsync = 0,
+};
+#endif
+
+#ifdef CONFIG_VIDEO_S5K4E5
+static struct s3c_platform_camera s5k4e5 = {
+	.type  = CAM_TYPE_MIPI,
+	.use_isp = true,
+	.inv_pclk = 0,
+	.inv_vsync = 0,
+	.inv_href = 0,
+	.inv_hsync = 0,
+};
+#endif
+
+
+#ifdef CONFIG_VIDEO_S5K6A3
+static struct s3c_platform_camera s5k6a3 = {
+	.type  = CAM_TYPE_MIPI,
+	.use_isp = true,
+	.inv_pclk = 0,
+	.inv_vsync = 0,
+	.inv_href = 0,
+	.inv_hsync = 0,
+};
+#endif
+#endif
+#endif /* CONFIG_VIDEO_SAMSUNG_S5P_FIMC */
+
+#ifdef CONFIG_S3C64XX_DEV_SPI
+static struct s3c64xx_spi_csinfo spi0_csi[] = {
+	[0] = {
+		.line = EXYNOS4_GPB(1),
+		.set_level = gpio_set_value,
+		.fb_delay = 0x2,
+	},
+};
+
+static struct spi_board_info spi0_board_info[] __initdata = {
+	{
+		.modalias = "spidev",
+		.platform_data = NULL,
+		.max_speed_hz = 10*1000*1000,
+		.bus_num = 0,
+		.chip_select = 0,
+		.mode = SPI_MODE_0,
+		.controller_data = &spi0_csi[0],
+	}
+};
+
+#ifndef CONFIG_FB_S5P_LMS501KF03
+static struct s3c64xx_spi_csinfo spi1_csi[] = {
+	[0] = {
+		.line = EXYNOS4_GPB(5),
+		.set_level = gpio_set_value,
+		.fb_delay = 0x2,
+	},
+};
+
+static struct spi_board_info spi1_board_info[] __initdata = {
+	{
+		.modalias = "spidev",
+		.platform_data = NULL,
+		.max_speed_hz = 10*1000*1000,
+		.bus_num = 1,
+		.chip_select = 0,
+		.mode = SPI_MODE_3,
+		.controller_data = &spi1_csi[0],
+	}
+};
+#endif
+
+static struct s3c64xx_spi_csinfo spi2_csi[] = {
+	[0] = {
+		.line = EXYNOS4_GPC1(2),
+		.set_level = gpio_set_value,
+		.fb_delay = 0x2,
+	},
+};
+
+static struct spi_board_info spi2_board_info[] __initdata = {
+	{
+		.modalias = "spidev",
+		.platform_data = NULL,
+		.max_speed_hz = 10*1000*1000,
+		.bus_num = 2,
+		.chip_select = 0,
+		.mode = SPI_MODE_0,
+		.controller_data = &spi2_csi[0],
+	}
+};
+#endif
+
+#ifdef CONFIG_FB_S3C
+#if defined(CONFIG_LCD_AMS369FG06)
+static int lcd_power_on(struct lcd_device *ld, int enable)
+{
+	return 1;
+}
+
+static int reset_lcd(struct lcd_device *ld)
+{
+	int err = 0;
+
+	err = gpio_request_one(EXYNOS4_GPX0(6), GPIOF_OUT_INIT_HIGH, "GPX0");
+	if (err) {
+		printk(KERN_ERR "failed to request GPX0 for "
+				"lcd reset control\n");
+		return err;
+	}
+	gpio_set_value(EXYNOS4_GPX0(6), 0);
+	mdelay(1);
+
+	gpio_set_value(EXYNOS4_GPX0(6), 1);
+
+	gpio_free(EXYNOS4_GPX0(6));
+
+	return 1;
+}
+
+static struct lcd_platform_data ams369fg06_platform_data = {
+	.reset			= reset_lcd,
+	.power_on		= lcd_power_on,
+	.lcd_enabled		= 0,
+	.reset_delay		= 100,	/* 100ms */
+};
+
+#define		LCD_BUS_NUM	3
+#define		DISPLAY_CS	EXYNOS4_GPB(5)
+#define		DISPLAY_CLK	EXYNOS4_GPB(4)
+#define		DISPLAY_SI	EXYNOS4_GPB(7)
+
+static struct spi_board_info spi_board_info[] __initdata = {
+	{
+		.modalias		= "ams369fg06",
+		.platform_data		= (void *)&ams369fg06_platform_data,
+		.max_speed_hz		= 1200000,
+		.bus_num		= LCD_BUS_NUM,
+		.chip_select		= 0,
+		.mode			= SPI_MODE_3,
+		.controller_data	= (void *)DISPLAY_CS,
+	}
+};
+
+static struct spi_gpio_platform_data ams369fg06_spi_gpio_data = {
+	.sck	= DISPLAY_CLK,
+	.mosi	= DISPLAY_SI,
+	.miso	= -1,
+	.num_chipselect = 1,
+};
+
+static struct platform_device s3c_device_spi_gpio = {
+	.name	= "spi_gpio",
+	.id	= LCD_BUS_NUM,
+	.dev	= {
+		.parent		= &s5p_device_fimd0.dev,
+		.platform_data	= &ams369fg06_spi_gpio_data,
+	},
+};
+
+static struct s3c_fb_pd_win smdk4x12_fb_win0 = {
+	.win_mode = {
+		.left_margin	= 9,
+		.right_margin	= 9,
+		.upper_margin	= 5,
+		.lower_margin	= 5,
+		.hsync_len	= 2,
+		.vsync_len	= 2,
+		.xres		= 480,
+		.yres		= 800,
+	},
+	.virtual_x		= 480,
+	.virtual_y		= 1600,
+	.width			= 48,
+	.height			= 80,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+};
+
+static struct s3c_fb_pd_win smdk4x12_fb_win1 = {
+	.win_mode = {
+		.left_margin	= 9,
+		.right_margin	= 9,
+		.upper_margin	= 5,
+		.lower_margin	= 5,
+		.hsync_len	= 2,
+		.vsync_len	= 2,
+		.xres		= 480,
+		.yres		= 800,
+	},
+	.virtual_x		= 480,
+	.virtual_y		= 1600,
+	.width			= 48,
+	.height			= 80,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+};
+
+static struct s3c_fb_pd_win smdk4x12_fb_win2 = {
+	.win_mode = {
+		.left_margin	= 9,
+		.right_margin	= 9,
+		.upper_margin	= 5,
+		.lower_margin	= 5,
+		.hsync_len	= 2,
+		.vsync_len	= 2,
+		.xres		= 480,
+		.yres		= 800,
+	},
+	.virtual_x		= 480,
+	.virtual_y		= 1600,
+	.width			= 48,
+	.height			= 80,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+};
+#elif defined(CONFIG_LCD_LMS501KF03)
+static int lcd_power_on(struct lcd_device *ld, int enable)
+{
+	return 1;
+}
+
+static int reset_lcd(struct lcd_device *ld)
+{
+	int err = 0;
+
+	if (samsung_board_rev_is_0_1()) {
+		err = gpio_request_one(EXYNOS4212_GPM3(6),
+				GPIOF_OUT_INIT_HIGH, "GPM3");
+		if (err) {
+			printk(KERN_ERR "failed to request GPM3 for "
+					"lcd reset control\n");
+			return err;
+		}
+		gpio_set_value(EXYNOS4212_GPM3(6), 0);
+		mdelay(1);
+
+		gpio_set_value(EXYNOS4212_GPM3(6), 1);
+
+		gpio_free(EXYNOS4212_GPM3(6));
+	} else {
+		err = gpio_request_one(EXYNOS4_GPX1(5),
+				GPIOF_OUT_INIT_HIGH, "GPX1");
+		if (err) {
+			printk(KERN_ERR "failed to request GPX1 for "
+					"lcd reset control\n");
+			return err;
+		}
+		gpio_set_value(EXYNOS4_GPX1(5), 0);
+		mdelay(1);
+
+		gpio_set_value(EXYNOS4_GPX1(5), 1);
+
+		gpio_free(EXYNOS4_GPX1(5));
+	}
+
+	return 1;
+}
+
+static struct lcd_platform_data lms501kf03_platform_data = {
+	.reset			= reset_lcd,
+	.power_on		= lcd_power_on,
+	.lcd_enabled		= 0,
+	.reset_delay		= 100,	/* 100ms */
+};
+
+#define		LCD_BUS_NUM	3
+#define		DISPLAY_CS	EXYNOS4_GPB(5)
+#define		DISPLAY_CLK	EXYNOS4_GPB(4)
+#define		DISPLAY_SI	EXYNOS4_GPB(7)
+
+static struct spi_board_info spi_board_info[] __initdata = {
+	{
+		.modalias		= "lms501kf03",
+		.platform_data		= (void *)&lms501kf03_platform_data,
+		.max_speed_hz		= 1200000,
+		.bus_num		= LCD_BUS_NUM,
+		.chip_select		= 0,
+		.mode			= SPI_MODE_3,
+		.controller_data	= (void *)DISPLAY_CS,
+	}
+};
+
+static struct spi_gpio_platform_data lms501kf03_spi_gpio_data = {
+	.sck	= DISPLAY_CLK,
+	.mosi	= DISPLAY_SI,
+	.miso	= -1,
+	.num_chipselect = 1,
+};
+
+static struct platform_device s3c_device_spi_gpio = {
+	.name	= "spi_gpio",
+	.id	= LCD_BUS_NUM,
+	.dev	= {
+		.parent		= &s5p_device_fimd0.dev,
+		.platform_data	= &lms501kf03_spi_gpio_data,
+	},
+};
+
+static struct s3c_fb_pd_win smdk4x12_fb_win0 = {
+	.win_mode = {
+		.left_margin	= 8,		/* HBPD */
+		.right_margin	= 8,		/* HFPD */
+		.upper_margin	= 6,	/* VBPD */
+		.lower_margin	= 6,		/* VFPD */
+		.hsync_len	= 6,		/* HSPW */
+		.vsync_len	= 4,		/* VSPW */
+		.xres		= 480,
+		.yres		= 800,
+	},
+	.virtual_x		= 480,
+	.virtual_y		= 1600,
+	.width			= 48,
+	.height			= 80,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+};
+
+static struct s3c_fb_pd_win smdk4x12_fb_win1 = {
+	.win_mode = {
+		.left_margin	= 8,		/* HBPD */
+		.right_margin	= 8,		/* HFPD */
+		.upper_margin	= 6,	/* VBPD */
+		.lower_margin	= 6,		/* VFPD */
+		.hsync_len	= 6,		/* HSPW */
+		.vsync_len	= 4,		/* VSPW */
+		.xres		= 480,
+		.yres		= 800,
+	},
+	.virtual_x		= 480,
+	.virtual_y		= 1600,
+	.width			= 48,
+	.height			= 80,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+};
+
+static struct s3c_fb_pd_win smdk4x12_fb_win2 = {
+	.win_mode = {
+		.left_margin	= 8,		/* HBPD */
+		.right_margin	= 8,		/* HFPD */
+		.upper_margin	= 6,	/* VBPD */
+		.lower_margin	= 6,		/* VFPD */
+		.hsync_len	= 6,		/* HSPW */
+		.vsync_len	= 4,		/* VSPW */
+		.xres		= 480,
+		.yres		= 800,
+	},
+	.virtual_x		= 480,
+	.virtual_y		= 1600,
+	.width			= 48,
+	.height			= 80,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+};
+#elif defined(CONFIG_LCD_WA101S)
+static void lcd_wa101s_set_power(struct plat_lcd_data *pd,
+				   unsigned int power)
+{
+	if (power) {
+#if !defined(CONFIG_BACKLIGHT_PWM)
+		gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_HIGH, "GPD0");
+		gpio_free(EXYNOS4_GPD0(1));
+#endif
+	} else {
+#if !defined(CONFIG_BACKLIGHT_PWM)
+		gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_LOW, "GPD0");
+		gpio_free(EXYNOS4_GPD0(1));
+#endif
+	}
+}
+
+static struct plat_lcd_data smdk4x12_lcd_wa101s_data = {
+	.set_power		= lcd_wa101s_set_power,
+};
+
+static struct platform_device smdk4x12_lcd_wa101s = {
+	.name			= "platform-lcd",
+	.dev.parent		= &s5p_device_fimd0.dev,
+	.dev.platform_data      = &smdk4x12_lcd_wa101s_data,
+};
+
+static struct s3c_fb_pd_win smdk4x12_fb_win0 = {
+	.win_mode = {
+		.left_margin	= 80,
+		.right_margin	= 48,
+		.upper_margin	= 14,
+		.lower_margin	= 3,
+		.hsync_len	= 32,
+		.vsync_len	= 5,
+		.xres		= 1360, /* real size : 1366 */
+		.yres		= 768,
+	},
+	.virtual_x		= 1360, /* real size : 1366 */
+	.virtual_y		= 768 * 2,
+	.width			= 223,
+	.height			= 125,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+};
+
+static struct s3c_fb_pd_win smdk4x12_fb_win1 = {
+	.win_mode = {
+		.left_margin	= 80,
+		.right_margin	= 48,
+		.upper_margin	= 14,
+		.lower_margin	= 3,
+		.hsync_len	= 32,
+		.vsync_len	= 5,
+		.xres		= 1360, /* real size : 1366 */
+		.yres		= 768,
+	},
+	.virtual_x		= 1360, /* real size : 1366 */
+	.virtual_y		= 768 * 2,
+	.width			= 223,
+	.height			= 125,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+};
+
+static struct s3c_fb_pd_win smdk4x12_fb_win2 = {
+	.win_mode = {
+		.left_margin	= 80,
+		.right_margin	= 48,
+		.upper_margin	= 14,
+		.lower_margin	= 3,
+		.hsync_len	= 32,
+		.vsync_len	= 5,
+		.xres		= 1360, /* real size : 1366 */
+		.yres		= 768,
+	},
+	.virtual_x		= 1360, /* real size : 1366 */
+	.virtual_y		= 768 * 2,
+	.width			= 223,
+	.height			= 125,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+};
+
+#elif defined(CONFIG_LCD_LTE480WV)
+static void lcd_lte480wv_set_power(struct plat_lcd_data *pd,
+				   unsigned int power)
+{
+	if (power) {
+#if !defined(CONFIG_BACKLIGHT_PWM)
+		gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_HIGH, "GPD0");
+		gpio_free(EXYNOS4_GPD0(1));
+#endif
+		/* fire nRESET on power up */
+		gpio_request_one(EXYNOS4_GPX0(6), GPIOF_OUT_INIT_HIGH, "GPX0");
+		mdelay(100);
+
+		gpio_set_value(EXYNOS4_GPX0(6), 0);
+		mdelay(10);
+
+		gpio_set_value(EXYNOS4_GPX0(6), 1);
+		mdelay(10);
+
+		gpio_free(EXYNOS4_GPX0(6));
+	} else {
+#if !defined(CONFIG_BACKLIGHT_PWM)
+		gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_LOW, "GPD0");
+		gpio_free(EXYNOS4_GPD0(1));
+#endif
+	}
+}
+
+static struct plat_lcd_data smdk4x12_lcd_lte480wv_data = {
+	.set_power		= lcd_lte480wv_set_power,
+};
+
+static struct platform_device smdk4x12_lcd_lte480wv = {
+	.name			= "platform-lcd",
+	.dev.parent		= &s5p_device_fimd0.dev,
+	.dev.platform_data      = &smdk4x12_lcd_lte480wv_data,
+};
+
+static struct s3c_fb_pd_win smdk4x12_fb_win0 = {
+	.win_mode = {
+		.left_margin	= 13,
+		.right_margin	= 8,
+		.upper_margin	= 7,
+		.lower_margin	= 5,
+		.hsync_len	= 3,
+		.vsync_len	= 1,
+		.xres		= 800,
+		.yres		= 480,
+	},
+	.virtual_x		= 800,
+	.virtual_y		= 960,
+	.width			= 104,
+	.height			= 62,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+};
+
+static struct s3c_fb_pd_win smdk4x12_fb_win1 = {
+	.win_mode = {
+		.left_margin	= 13,
+		.right_margin	= 8,
+		.upper_margin	= 7,
+		.lower_margin	= 5,
+		.hsync_len	= 3,
+		.vsync_len	= 1,
+		.xres		= 800,
+		.yres		= 480,
+	},
+	.virtual_x		= 800,
+	.virtual_y		= 960,
+	.width			= 104,
+	.height			= 62,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+};
+
+static struct s3c_fb_pd_win smdk4x12_fb_win2 = {
+	.win_mode = {
+		.left_margin	= 13,
+		.right_margin	= 8,
+		.upper_margin	= 7,
+		.lower_margin	= 5,
+		.hsync_len	= 3,
+		.vsync_len	= 1,
+		.xres		= 800,
+		.yres		= 480,
+	},
+	.virtual_x		= 800,
+	.virtual_y		= 960,
+	.width			= 104,
+	.height			= 62,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+};
+#elif defined(CONFIG_LCD_MIPI_S6E63M0)
+static void mipi_lcd_set_power(struct plat_lcd_data *pd,
+				unsigned int power)
+{
+	gpio_request_one(EXYNOS4_GPX2(7), GPIOF_OUT_INIT_HIGH, "GPX2");
+
+	mdelay(100);
+	if (power) {
+		/* fire nRESET on power up */
+		gpio_set_value(EXYNOS4_GPX2(7), 0);
+		mdelay(100);
+		gpio_set_value(EXYNOS4_GPX2(7), 1);
+		mdelay(100);
+		gpio_free(EXYNOS4_GPX2(7));
+	} else {
+		/* fire nRESET on power off */
+		gpio_set_value(EXYNOS4_GPX2(7), 0);
+		mdelay(100);
+		gpio_set_value(EXYNOS4_GPX2(7), 1);
+		mdelay(100);
+		gpio_free(EXYNOS4_GPX2(7));
+	}
+}
+
+static struct plat_lcd_data smdk4x12_mipi_lcd_data = {
+	.set_power	= mipi_lcd_set_power,
+};
+
+static struct platform_device smdk4x12_mipi_lcd = {
+	.name			= "platform-lcd",
+	.dev.parent		= &s5p_device_fimd0.dev,
+	.dev.platform_data	= &smdk4x12_mipi_lcd_data,
+};
+
+static struct s3c_fb_pd_win smdk4x12_fb_win0 = {
+	.win_mode = {
+		.left_margin	= 0x16,
+		.right_margin	= 0x16,
+		.upper_margin	= 0x1,
+		.lower_margin	= 0x28,
+		.hsync_len	= 0x2,
+		.vsync_len	= 0x3,
+		.xres		= 480,
+		.yres		= 800,
+	},
+	.virtual_x		= 480,
+	.virtual_y		= 1600,
+	.width			= 48,
+	.height			= 80,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+};
+
+static struct s3c_fb_pd_win smdk4x12_fb_win1 = {
+	.win_mode = {
+		.left_margin	= 0x16,
+		.right_margin	= 0x16,
+		.upper_margin	= 0x1,
+		.lower_margin	= 0x28,
+		.hsync_len	= 0x2,
+		.vsync_len	= 0x3,
+		.xres		= 480,
+		.yres		= 800,
+	},
+	.virtual_x		= 480,
+	.virtual_y		= 1600,
+	.width			= 48,
+	.height			= 80,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+};
+
+static struct s3c_fb_pd_win smdk4x12_fb_win2 = {
+	.win_mode = {
+		.left_margin	= 0x16,
+		.right_margin	= 0x16,
+		.upper_margin	= 0x1,
+		.lower_margin	= 0x28,
+		.hsync_len	= 0x2,
+		.vsync_len	= 0x3,
+		.xres		= 480,
+		.yres		= 800,
+	},
+	.virtual_x		= 480,
+	.virtual_y		= 1600,
+	.width			= 48,
+	.height			= 80,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+};
+#endif
+
+static struct s3c_fb_platdata smdk4x12_lcd0_pdata __initdata = {
+#if defined(CONFIG_LCD_AMS369FG06) || defined(CONFIG_LCD_WA101S) || \
+	defined(CONFIG_LCD_LTE480WV) || defined(CONFIG_LCD_LMS501KF03) || \
+	defined(CONFIG_LCD_MIPI_S6E63M0)
+	.win[0]		= &smdk4x12_fb_win0,
+	.win[1]		= &smdk4x12_fb_win1,
+	.win[2]		= &smdk4x12_fb_win2,
+#endif
+	.default_win	= 2,
+	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+#if defined(CONFIG_LCD_AMS369FG06)
+	.vidcon1	= VIDCON1_INV_VCLK | VIDCON1_INV_VDEN |
+			  VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+#elif defined(CONFIG_LCD_LMS501KF03)
+	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+#elif defined(CONFIG_LCD_WA101S)
+	.vidcon1	= VIDCON1_INV_VCLK | VIDCON1_INV_HSYNC |
+			  VIDCON1_INV_VSYNC,
+#elif defined(CONFIG_LCD_LTE480WV)
+	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+#endif
+	.setup_gpio	= exynos4_fimd0_gpio_setup_24bpp,
+};
+#endif
+
+#ifdef CONFIG_FB_S5P
+#ifdef CONFIG_FB_S5P_LMS501KF03
+static struct s3c_platform_fb lms501kf03_data __initdata = {
+	.hw_ver = 0x70,
+	.clk_name = "sclk_lcd",
+	.nr_wins = 5,
+	.default_win = CONFIG_FB_S5P_DEFAULT_WINDOW,
+	.swap = FB_SWAP_HWORD | FB_SWAP_WORD,
+};
+
+#define		LCD_BUS_NUM	3
+#define		DISPLAY_CS	EXYNOS4_GPB(5)
+#define		DISPLAY_CLK	EXYNOS4_GPB(4)
+#define		DISPLAY_SI	EXYNOS4_GPB(7)
+
+static struct spi_board_info spi_board_info[] __initdata = {
+	{
+		.modalias	= "lms501kf03",
+		.platform_data	= NULL,
+		.max_speed_hz	= 1200000,
+		.bus_num	= LCD_BUS_NUM,
+		.chip_select	= 0,
+		.mode		= SPI_MODE_3,
+		.controller_data = (void *)DISPLAY_CS,
+	}
+};
+static struct spi_gpio_platform_data lms501kf03_spi_gpio_data = {
+	.sck	= DISPLAY_CLK,
+	.mosi	= DISPLAY_SI,
+	.miso	= -1,
+	.num_chipselect = 1,
+};
+
+static struct platform_device s3c_device_spi_gpio = {
+	.name	= "spi_gpio",
+	.id	= LCD_BUS_NUM,
+	.dev	= {
+		.parent		= &s3c_device_fb.dev,
+		.platform_data	= &lms501kf03_spi_gpio_data,
+	},
+};
+#elif defined(CONFIG_FB_S5P_DUMMY_MIPI_LCD)
+#define		LCD_BUS_NUM	3
+#define		DISPLAY_CS	EXYNOS4_GPB(5)
+#define		DISPLAY_CLK	EXYNOS4_GPB(4)
+#define		DISPLAY_SI	EXYNOS4_GPB(7)
+
+static struct s3cfb_lcd dummy_mipi_lcd = {
+	.width = 480,
+	.height = 800,
+	.bpp = 24,
+
+	.freq = 60,
+
+	.timing = {
+		.h_fp = 0x16,
+		.h_bp = 0x16,
+		.h_sw = 0x2,
+		.v_fp = 0x28,
+		.v_fpe = 2,
+		.v_bp = 0x1,
+		.v_bpe = 1,
+		.v_sw = 3,
+		.cmd_allow_len = 0x4,
+	},
+
+	.polarity = {
+		.rise_vclk = 0,
+		.inv_hsync = 0,
+		.inv_vsync = 0,
+		.inv_vden = 0,
+	},
+};
+
+static struct s3c_platform_fb fb_platform_data __initdata = {
+	.hw_ver		= 0x70,
+	.clk_name	= "sclk_lcd",
+	.nr_wins	= 5,
+	.default_win	= CONFIG_FB_S5P_DEFAULT_WINDOW,
+	.swap		= FB_SWAP_HWORD | FB_SWAP_WORD,
+};
+
+static void lcd_cfg_gpio(void)
+{
+	return;
+}
+
+static int reset_lcd(void)
+{
+	int err = 0;
+
+	/* fire nRESET on power off */
+	err = gpio_request(EXYNOS4_GPX3(1), "GPX3");
+	if (err) {
+		printk(KERN_ERR "failed to request GPX0 for lcd reset control\n");
+		return err;
+	}
+
+#ifdef CONFIG_CPU_EXYNOS4212
+	gpio_direction_output(EXYNOS4_GPX2(7), 1);
+	mdelay(100);
+
+	gpio_set_value(EXYNOS4_GPX2(7), 0);
+	mdelay(100);
+	gpio_set_value(EXYNOS4_GPX2(7), 1);
+	mdelay(100);
+	gpio_free(EXYNOS4_GPX2(7));
+#else
+	gpio_direction_output(EXYNOS4_GPX3(1), 1);
+	mdelay(100);
+
+	gpio_set_value(EXYNOS4_GPX3(1), 0);
+	mdelay(100);
+	gpio_set_value(EXYNOS4_GPX3(1), 1);
+	mdelay(100);
+	gpio_free(EXYNOS4_GPX3(1));
+#endif
+	return 0;
+}
+
+static int lcd_power_on(void *pdev, int enable)
+{
+	return 1;
+}
+
+static void __init mipi_fb_init(void)
+{
+	struct s5p_platform_dsim *dsim_pd = NULL;
+	struct mipi_ddi_platform_data *mipi_ddi_pd = NULL;
+	struct dsim_lcd_config *dsim_lcd_info = NULL;
+
+	/* gpio pad configuration for rgb and spi interface. */
+	lcd_cfg_gpio();
+
+	/*
+	 * register lcd panel data.
+	 */
+	dsim_pd = (struct s5p_platform_dsim *)
+		s5p_device_dsim.dev.platform_data;
+
+	strcpy(dsim_pd->lcd_panel_name, "dummy_mipi_lcd");
+
+	dsim_lcd_info = dsim_pd->dsim_lcd_info;
+	dsim_lcd_info->lcd_panel_info = (void *)&dummy_mipi_lcd;
+
+	mipi_ddi_pd = (struct mipi_ddi_platform_data *)
+		dsim_lcd_info->mipi_ddi_pd;
+	mipi_ddi_pd->lcd_reset = reset_lcd;
+	mipi_ddi_pd->lcd_power_on = lcd_power_on;
+
+	platform_device_register(&s5p_device_dsim);
+
+	s3cfb_set_platdata(&fb_platform_data);
+
+	printk(KERN_INFO "platform data of %s lcd panel has been registered.\n",
+			dsim_pd->lcd_panel_name);
+}
+#endif
+#endif
+
+static int exynos4_notifier_call(struct notifier_block *this,
+					unsigned long code, void *_cmd)
+{
+	int mode = 0;
+
+	if ((code == SYS_RESTART) && _cmd)
+		if (!strcmp((char *)_cmd, "recovery"))
+			mode = 0xf;
+
+	__raw_writel(mode, REG_INFORM4);
+
+	return NOTIFY_DONE;
+}
+
+static struct notifier_block exynos4_reboot_notifier = {
+	.notifier_call = exynos4_notifier_call,
+};
+
+#ifdef CONFIG_EXYNOS4_DEV_DWMCI
+static void exynos_dwmci_cfg_gpio(int width)
+{
+	unsigned int gpio;
+
+	for (gpio = EXYNOS4_GPK0(0); gpio < EXYNOS4_GPK0(2); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV2);
+	}
+
+	switch (width) {
+	case MMC_BUS_WIDTH_8:
+		for (gpio = EXYNOS4_GPK1(3); gpio <= EXYNOS4_GPK1(6); gpio++) {
+			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
+			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+			s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV2);
+		}
+	case MMC_BUS_WIDTH_4:
+		for (gpio = EXYNOS4_GPK0(3); gpio <= EXYNOS4_GPK0(6); gpio++) {
+			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+			s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV2);
+		}
+		break;
+	case MMC_BUS_WIDTH_1:
+		gpio = EXYNOS4_GPK0(3);
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV2);
+	default:
+		break;
+	}
+}
+
+static struct dw_mci_board exynos_dwmci_pdata __initdata = {
+	.num_slots		= 1,
+	.quirks			= DW_MCI_QUIRK_BROKEN_CARD_DETECTION | DW_MCI_QUIRK_HIGHSPEED,
+	.bus_hz			= 100 * 1000 * 1000,
+	.caps			= MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR |
+				MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
+	.fifo_depth		= 0x80,
+	.detect_delay_ms	= 200,
+	.hclk_name		= "dwmci",
+	.cclk_name		= "sclk_dwmci",
+	.cfg_gpio		= exynos_dwmci_cfg_gpio,
+};
+#endif
+
+#ifdef CONFIG_S3C_DEV_HSMMC
+static struct s3c_sdhci_platdata smdk4x12_hsmmc0_pdata __initdata = {
+	.cd_type		= S3C_SDHCI_CD_INTERNAL,
+	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
+#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
+	.max_width		= 8,
+	.host_caps		= MMC_CAP_8_BIT_DATA,
+#endif
+};
+#endif
+
+#ifdef CONFIG_S3C_DEV_HSMMC1
+static struct s3c_sdhci_platdata smdk4x12_hsmmc1_pdata __initdata = {
+	.cd_type		= S3C_SDHCI_CD_INTERNAL,
+	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+#endif
+
+#ifdef CONFIG_S3C_DEV_HSMMC2
+static struct s3c_sdhci_platdata smdk4x12_hsmmc2_pdata __initdata = {
+	.cd_type		= S3C_SDHCI_CD_INTERNAL,
+	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
+#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
+	.max_width		= 8,
+	.host_caps		= MMC_CAP_8_BIT_DATA,
+#endif
+};
+#endif
+
+#ifdef CONFIG_S3C_DEV_HSMMC3
+static struct s3c_sdhci_platdata smdk4x12_hsmmc3_pdata __initdata = {
+	.cd_type		= S3C_SDHCI_CD_INTERNAL,
+	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+#endif
+
+#ifdef CONFIG_S5P_DEV_MSHC
+static struct s3c_mshci_platdata exynos4_mshc_pdata __initdata = {
+	.cd_type		= S3C_MSHCI_CD_PERMANENT,
+	.has_wp_gpio		= true,
+	.wp_gpio		= 0xffffffff,
+#if defined(CONFIG_EXYNOS4_MSHC_8BIT) && \
+	defined(CONFIG_EXYNOS4_MSHC_DDR)
+	.max_width		= 8,
+	.host_caps		= MMC_CAP_8_BIT_DATA | MMC_CAP_1_8V_DDR |
+				  MMC_CAP_UHS_DDR50,
+#elif defined(CONFIG_EXYNOS4_MSHC_8BIT)
+	.max_width		= 8,
+	.host_caps		= MMC_CAP_8_BIT_DATA,
+#elif defined(CONFIG_EXYNOS4_MSHC_DDR)
+	.host_caps		= MMC_CAP_1_8V_DDR | MMC_CAP_UHS_DDR50,
+#endif
+};
+#endif
+
+#ifdef CONFIG_USB_EHCI_S5P
+static struct s5p_ehci_platdata smdk4x12_ehci_pdata;
+
+static void __init smdk4x12_ehci_init(void)
+{
+	struct s5p_ehci_platdata *pdata = &smdk4x12_ehci_pdata;
+
+	s5p_ehci_set_platdata(pdata);
+}
+#endif
+
+#ifdef CONFIG_USB_OHCI_S5P
+static struct s5p_ohci_platdata smdk4x12_ohci_pdata;
+
+static void __init smdk4x12_ohci_init(void)
+{
+	struct s5p_ohci_platdata *pdata = &smdk4x12_ohci_pdata;
+
+	s5p_ohci_set_platdata(pdata);
+}
+#endif
+
+/* USB GADGET */
+#ifdef CONFIG_USB_GADGET
+static struct s5p_usbgadget_platdata smdk4x12_usbgadget_pdata;
+
+static void __init smdk4x12_usbgadget_init(void)
+{
+	struct s5p_usbgadget_platdata *pdata = &smdk4x12_usbgadget_pdata;
+
+	s5p_usbgadget_set_platdata(pdata);
+}
+#endif
+
+static struct regulator_consumer_supply max8952_supply =
+	REGULATOR_SUPPLY("vdd_mif", NULL);
+
+static struct regulator_init_data max8952_init_data = {
+	.constraints	= {
+		.name		= "vdd_mif range",
+		.min_uV		= 800000,
+		.max_uV		= 1100000,
+		.always_on	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE,
+		.state_mem	= {
+			.uV		= 1100000,
+			.disabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &max8952_supply,
+};
+
+static struct max8649_platform_data exynos4_max8952_info = {
+	.mode		= 1,	/* VID1 = 0, VID0 = 1 */
+	.extclk		= 0,
+	.ramp_timing	= MAX8649_RAMP_32MV,
+	.regulator	= &max8952_init_data,
+};
+
+/* max8997 */
+static struct regulator_consumer_supply max8997_buck1 =
+	REGULATOR_SUPPLY("vdd_arm", NULL);
+
+static struct regulator_consumer_supply max8997_buck2 =
+	REGULATOR_SUPPLY("vdd_int", NULL);
+
+static struct regulator_consumer_supply max8997_buck3 =
+	REGULATOR_SUPPLY("vdd_g3d", NULL);
+
+static struct regulator_consumer_supply __initdata ldo2_consumer =
+	REGULATOR_SUPPLY("vdd_ldo2", NULL);
+
+static struct regulator_consumer_supply __initdata ldo3_consumer =
+	REGULATOR_SUPPLY("vdd_ldo3", NULL);
+
+static struct regulator_consumer_supply __initdata ldo4_consumer =
+	REGULATOR_SUPPLY("vdd_ldo4", NULL);
+
+static struct regulator_consumer_supply __initdata ldo5_consumer =
+	REGULATOR_SUPPLY("vdd_ldo5", NULL);
+
+static struct regulator_consumer_supply __initdata ldo6_consumer =
+	REGULATOR_SUPPLY("vdd_ldo6", NULL);
+
+static struct regulator_consumer_supply __initdata ldo7_consumer =
+	REGULATOR_SUPPLY("vdd_ldo7", NULL);
+
+static struct regulator_consumer_supply __initdata ldo8_consumer =
+	REGULATOR_SUPPLY("vdd_ldo8", NULL);
+
+static struct regulator_consumer_supply __initdata ldo9_consumer =
+	REGULATOR_SUPPLY("vdd_ldo9", NULL);
+
+static struct regulator_consumer_supply __initdata ldo10_consumer =
+	REGULATOR_SUPPLY("vdd_ldo10", NULL);
+
+static struct regulator_consumer_supply __initdata ldo11_consumer =
+	REGULATOR_SUPPLY("vdd_ldo11", NULL);
+
+static struct regulator_consumer_supply __initdata ldo12_consumer =
+	REGULATOR_SUPPLY("vdd_adc", NULL);
+
+static struct regulator_consumer_supply __initdata ldo14_consumer =
+	REGULATOR_SUPPLY("vdd_ldo14", NULL);
+
+static struct regulator_consumer_supply __initdata ldo21_consumer =
+	REGULATOR_SUPPLY("vdd_ldo21", NULL);
+
+static struct regulator_init_data __initdata max8997_ldo2_data = {
+	.constraints	= {
+		.name		= "vdd_ldo2 range",
+		.min_uV		= 1000000,
+		.max_uV		= 1000000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.state_mem	= {
+			.enabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &ldo2_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_ldo3_data = {
+	.constraints	= {
+		.name		= "vdd_ldo3 range",
+		.min_uV		= 1000000,
+		.max_uV		= 1000000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.disabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &ldo3_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_ldo4_data = {
+	.constraints	= {
+		.name		= "vdd_ldo4 range",
+		.min_uV		= 1800000,
+		.max_uV		= 1800000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.disabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &ldo4_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_ldo5_data = {
+	.constraints	= {
+		.name		= "vdd_ldo5 range",
+		.min_uV		= 1000000,
+		.max_uV		= 1000000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.state_mem	= {
+			.enabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &ldo5_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_ldo6_data = {
+	.constraints	= {
+		.name		= "vdd_ldo6 range",
+		.min_uV		= 1800000,
+		.max_uV		= 1800000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.state_mem	= {
+			.enabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &ldo6_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_ldo7_data = {
+	.constraints	= {
+		.name		= "vdd_ldo7 range",
+		.min_uV		= 1800000,
+		.max_uV		= 1800000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.state_mem	= {
+			.enabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &ldo7_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_ldo8_data = {
+	.constraints	= {
+		.name		= "vdd_ldo8 range",
+		.min_uV		= 3300000,
+		.max_uV		= 3300000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.disabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &ldo8_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_ldo9_data = {
+	.constraints	= {
+		.name		= "vdd_ldo9 range",
+		.min_uV		= 2800000,
+		.max_uV		= 2800000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.state_mem	= {
+			.enabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &ldo9_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_ldo10_data = {
+	.constraints	= {
+		.name		= "vdd_ldo10 range",
+		.min_uV		= 1000000,
+		.max_uV		= 1000000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.disabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &ldo10_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_ldo11_data = {
+	.constraints	= {
+		.name		= "vdd_ldo11 range",
+		.min_uV		= 2800000,
+		.max_uV		= 2800000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.state_mem	= {
+			.enabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &ldo11_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_ldo12_data = {
+	.constraints	= {
+		.name		= "vdd_adc range",
+		.min_uV		= 1800000,
+		.max_uV		= 1800000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.state_mem	= {
+			.enabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &ldo12_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_ldo14_data = {
+	.constraints	= {
+		.name		= "vdd_ldo14 range",
+		.min_uV		= 1800000,
+		.max_uV		= 1800000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.state_mem	= {
+			.enabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &ldo14_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_ldo21_data = {
+	.constraints	= {
+		.name		= "vdd_ldo21 range",
+		.min_uV		= 1200000,
+		.max_uV		= 1200000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.state_mem	= {
+			.enabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &ldo21_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_buck1_data = {
+	.constraints	= {
+		.name		= "vdd_arm range",
+		.min_uV		= 800000,
+		.max_uV		= 1500000,
+		.always_on	= 1,
+		.boot_on	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE,
+		.state_mem	= {
+			.disabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &max8997_buck1,
+};
+
+static struct regulator_init_data __initdata max8997_buck2_data = {
+	.constraints	= {
+		.name		= "vdd_int range",
+		.min_uV		= 800000,
+		.max_uV		= 1150000,
+		.always_on	= 1,
+		.boot_on	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE,
+		.state_mem	= {
+			.disabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &max8997_buck2,
+};
+
+static struct regulator_init_data __initdata max8997_buck3_data = {
+	.constraints	= {
+		.name		= "vdd_g3d range",
+		.min_uV		= 800000,
+		.max_uV		= 1200000,
+		.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE |
+				  REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.disabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &max8997_buck3,
+};
+
+static struct max8997_regulator_data __initdata max8997_regulators[] = {
+	{ MAX8997_LDO2, &max8997_ldo2_data, },
+	{ MAX8997_LDO3, &max8997_ldo3_data, },
+	{ MAX8997_LDO4, &max8997_ldo4_data, },
+	{ MAX8997_LDO5, &max8997_ldo5_data, },
+	{ MAX8997_LDO6, &max8997_ldo6_data, },
+	{ MAX8997_LDO7, &max8997_ldo7_data, },
+	{ MAX8997_LDO8, &max8997_ldo8_data, },
+	{ MAX8997_LDO9, &max8997_ldo9_data, },
+	{ MAX8997_LDO10, &max8997_ldo10_data, },
+	{ MAX8997_LDO11, &max8997_ldo11_data, },
+	{ MAX8997_LDO12, &max8997_ldo12_data, },
+	{ MAX8997_LDO14, &max8997_ldo14_data, },
+	{ MAX8997_LDO21, &max8997_ldo21_data, },
+	{ MAX8997_BUCK1, &max8997_buck1_data, },
+	{ MAX8997_BUCK2, &max8997_buck2_data, },
+	{ MAX8997_BUCK3, &max8997_buck3_data, },
+};
+
+static struct max8997_platform_data __initdata exynos4_max8997_info = {
+	.num_regulators = ARRAY_SIZE(max8997_regulators),
+	.regulators     = max8997_regulators,
+
+	.buck1_voltage[0] = 1300000, /* 1.25V */
+	.buck1_voltage[1] = 1100000, /* 1.1V */
+	.buck1_voltage[2] = 1100000, /* 1.1V */
+	.buck1_voltage[3] = 1100000, /* 1.1V */
+	.buck1_voltage[4] = 1100000, /* 1.1V */
+	.buck1_voltage[5] = 1100000, /* 1.1V */
+	.buck1_voltage[6] = 1000000, /* 1.0V */
+	.buck1_voltage[7] = 950000, /* 0.95V */
+
+	.buck2_voltage[0] = 1037500, /* 1.0375V */
+	.buck2_voltage[1] = 1000000, /* 1.0V */
+	.buck2_voltage[2] = 950000, /* 0.95V */
+	.buck2_voltage[3] = 900000, /* 0.9V */
+	.buck2_voltage[4] = 1000000, /* 1.0V */
+	.buck2_voltage[5] = 1000000, /* 1.0V */
+	.buck2_voltage[6] = 950000, /* 0.95V */
+	.buck2_voltage[7] = 900000, /* 0.9V */
+
+	.buck5_voltage[0] = 1100000, /* 1.1V */
+	.buck5_voltage[1] = 1100000, /* 1.1V */
+	.buck5_voltage[2] = 1100000, /* 1.1V */
+	.buck5_voltage[3] = 1100000, /* 1.1V */
+	.buck5_voltage[4] = 1100000, /* 1.1V */
+	.buck5_voltage[5] = 1100000, /* 1.1V */
+	.buck5_voltage[6] = 1100000, /* 1.1V */
+	.buck5_voltage[7] = 1100000, /* 1.1V */
+};
+
+/* max77686 */
+static struct regulator_consumer_supply max77686_buck1 =
+REGULATOR_SUPPLY("vdd_mif", NULL);
+
+static struct regulator_consumer_supply max77686_buck2 =
+REGULATOR_SUPPLY("vdd_arm", NULL);
+
+static struct regulator_consumer_supply max77686_buck3 =
+REGULATOR_SUPPLY("vdd_int", NULL);
+
+static struct regulator_consumer_supply max77686_buck4 =
+REGULATOR_SUPPLY("vdd_g3d", NULL);
+
+static struct regulator_consumer_supply max77686_ldo11_consumer =
+REGULATOR_SUPPLY("vdd_ldo11", NULL);
+
+static struct regulator_consumer_supply max77686_ldo14_consumer =
+REGULATOR_SUPPLY("vdd_ldo14", NULL);
+
+static struct regulator_init_data max77686_buck1_data = {
+	.constraints = {
+		.name = "vdd_mif range",
+		.min_uV = 800000,
+		.max_uV = 1050000,
+		.always_on = 1,
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+				REGULATOR_CHANGE_STATUS,
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &max77686_buck1,
+};
+
+static struct regulator_init_data max77686_buck2_data = {
+	.constraints = {
+		.name = "vdd_arm range",
+		.min_uV = 800000,
+		.max_uV = 1350000,
+		.always_on = 1,
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &max77686_buck2,
+};
+
+static struct regulator_init_data max77686_buck3_data = {
+	.constraints = {
+		.name = "vdd_int range",
+		.min_uV = 800000,
+		.max_uV = 1150000,
+		.always_on = 1,
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &max77686_buck3,
+};
+
+static struct regulator_init_data max77686_buck4_data = {
+	.constraints = {
+		.name = "vdd_g3d range",
+		.min_uV = 850000,
+		.max_uV = 1200000,
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+				  REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.disabled = 1,
+		},
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &max77686_buck4,
+};
+
+static struct regulator_init_data max77686_ldo11_data = {
+	.constraints	= {
+		.name		= "vdd_ldo11 range",
+		.min_uV		= 1900000,
+		.max_uV		= 1900000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.state_mem	= {
+			.enabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &max77686_ldo11_consumer,
+};
+
+static struct regulator_init_data max77686_ldo14_data = {
+	.constraints	= {
+		.name		= "vdd_ldo14 range",
+		.min_uV		= 1900000,
+		.max_uV		= 1900000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.state_mem	= {
+			.enabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &max77686_ldo14_consumer,
+};
+
+static struct max77686_regulator_data max77686_regulators[] = {
+	{MAX77686_BUCK1, &max77686_buck1_data,},
+	{MAX77686_BUCK2, &max77686_buck2_data,},
+	{MAX77686_BUCK3, &max77686_buck3_data,},
+	{MAX77686_BUCK4, &max77686_buck4_data,},
+	{MAX77686_LDO11, &max77686_ldo11_data,},
+	{MAX77686_LDO14, &max77686_ldo14_data,},
+};
+
+struct max77686_opmode_data max77686_opmode_data[MAX77686_REG_MAX] = {
+	[MAX77686_LDO11] = {MAX77686_LDO11, MAX77686_OPMODE_STANDBY},
+	[MAX77686_LDO14] = {MAX77686_LDO14, MAX77686_OPMODE_STANDBY},
+	[MAX77686_BUCK1] = {MAX77686_BUCK1, MAX77686_OPMODE_STANDBY},
+	[MAX77686_BUCK2] = {MAX77686_BUCK2, MAX77686_OPMODE_STANDBY},
+	[MAX77686_BUCK3] = {MAX77686_BUCK3, MAX77686_OPMODE_STANDBY},
+	[MAX77686_BUCK4] = {MAX77686_BUCK4, MAX77686_OPMODE_STANDBY},
+};
+
+static struct max77686_platform_data exynos4_max77686_info = {
+	.num_regulators = ARRAY_SIZE(max77686_regulators),
+	.regulators = max77686_regulators,
+	.irq_gpio	= 0,
+	.irq_base	= 0,
+	.wakeup		= 0,
+
+	.opmode_data = max77686_opmode_data,
+	.ramp_rate = MAX77686_RAMP_RATE_27MV,
+
+	.buck2_voltage[0] = 1300000,	/* 1.3V */
+	.buck2_voltage[1] = 1000000,	/* 1.0V */
+	.buck2_voltage[2] = 950000,	/* 0.95V */
+	.buck2_voltage[3] = 900000,	/* 0.9V */
+	.buck2_voltage[4] = 1000000,	/* 1.0V */
+	.buck2_voltage[5] = 1000000,	/* 1.0V */
+	.buck2_voltage[6] = 950000,	/* 0.95V */
+	.buck2_voltage[7] = 900000,	/* 0.9V */
+
+	.buck3_voltage[0] = 1037500,	/* 1.0375V */
+	.buck3_voltage[1] = 1000000,	/* 1.0V */
+	.buck3_voltage[2] = 950000,	/* 0.95V */
+	.buck3_voltage[3] = 900000,	/* 0.9V */
+	.buck3_voltage[4] = 1000000,	/* 1.0V */
+	.buck3_voltage[5] = 1000000,	/* 1.0V */
+	.buck3_voltage[6] = 950000,	/* 0.95V */
+	.buck3_voltage[7] = 900000,	/* 0.9V */
+
+	.buck4_voltage[0] = 1100000,	/* 1.1V */
+	.buck4_voltage[1] = 1000000,	/* 1.0V */
+	.buck4_voltage[2] = 950000,	/* 0.95V */
+	.buck4_voltage[3] = 900000,	/* 0.9V */
+	.buck4_voltage[4] = 1000000,	/* 1.0V */
+	.buck4_voltage[5] = 1000000,	/* 1.0V */
+	.buck4_voltage[6] = 950000,	/* 0.95V */
+	.buck4_voltage[7] = 900000,	/* 0.9V */
+};
+#ifdef CONFIG_REGULATOR_S5M8767
+/* S5M8767 Regulator */
+static int s5m_cfg_irq(void)
+{
+	/* AP_PMIC_IRQ: EINT26 */
+	s3c_gpio_cfgpin(EXYNOS4_GPX3(2), S3C_GPIO_SFN(0xF));
+	s3c_gpio_setpull(EXYNOS4_GPX3(2), S3C_GPIO_PULL_UP);
+	return 0;
+}
+static struct regulator_consumer_supply s5m8767_buck1_consumer =
+	REGULATOR_SUPPLY("vdd_mif", NULL);
+
+static struct regulator_consumer_supply s5m8767_buck2_consumer =
+	REGULATOR_SUPPLY("vdd_arm", NULL);
+
+static struct regulator_consumer_supply s5m8767_buck3_consumer =
+	REGULATOR_SUPPLY("vdd_int", NULL);
+
+static struct regulator_consumer_supply s5m8767_buck4_consumer =
+	REGULATOR_SUPPLY("vdd_g3d", NULL);
+
+static struct regulator_init_data s5m8767_buck1_data = {
+	.constraints	= {
+		.name		= "vdd_mif range",
+		.min_uV		= 800000,
+		.max_uV		= 1100000,
+		.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE |
+				  REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.disabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &s5m8767_buck1_consumer,
+};
+
+static struct regulator_init_data s5m8767_buck2_data = {
+	.constraints	= {
+		.name		= "vdd_arm range",
+		.min_uV		=  800000,
+		.max_uV		= 1350000,
+		.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE |
+				  REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.disabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &s5m8767_buck2_consumer,
+};
+
+static struct regulator_init_data s5m8767_buck3_data = {
+	.constraints	= {
+		.name		= "vdd_int range",
+		.min_uV		=  800000,
+		.max_uV		= 1150000,
+		.apply_uV	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE |
+				REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.uV		= 1100000,
+			.mode		= REGULATOR_MODE_NORMAL,
+			.disabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &s5m8767_buck3_consumer,
+};
+
+static struct regulator_init_data s5m8767_buck4_data = {
+	.constraints	= {
+		.name		= "vdd_g3d range",
+		.min_uV		= 850000,
+		.max_uV		= 1200000,
+		.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE |
+				REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.disabled	= 1,
+		},
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &s5m8767_buck4_consumer,
+};
+
+static struct s5m_regulator_data pegasus_regulators[] = {
+	{ S5M8767_BUCK1, &s5m8767_buck1_data },
+	{ S5M8767_BUCK2, &s5m8767_buck2_data },
+	{ S5M8767_BUCK3, &s5m8767_buck3_data },
+	{ S5M8767_BUCK4, &s5m8767_buck4_data },
+};
+
+static struct s5m_platform_data exynos4_s5m8767_pdata = {
+	.device_type		= S5M8767X,
+	.irq_base		= IRQ_BOARD_START,
+	.num_regulators		= ARRAY_SIZE(pegasus_regulators),
+	.regulators		= pegasus_regulators,
+	.cfg_pmic_irq		= s5m_cfg_irq,
+	.wakeup			= 1,
+	.opmode_data		= s5m8767_opmode_data,
+	.wtsr_smpl		= 1,
+
+	.buck2_voltage[0]	= 1250000,
+	.buck2_voltage[1]	= 1200000,
+	.buck2_voltage[2]	= 1150000,
+	.buck2_voltage[3]	= 1100000,
+	.buck2_voltage[4]	= 1050000,
+	.buck2_voltage[5]	= 1000000,
+	.buck2_voltage[6]	=  950000,
+	.buck2_voltage[7]	=  900000,
+
+	.buck3_voltage[0]	= 1100000,
+	.buck3_voltage[1]	= 1000000,
+	.buck3_voltage[2]	= 950000,
+	.buck3_voltage[3]	= 900000,
+	.buck3_voltage[4]	= 1100000,
+	.buck3_voltage[5]	= 1000000,
+	.buck3_voltage[6]	= 950000,
+	.buck3_voltage[7]	= 900000,
+
+	.buck4_voltage[0]	= 1200000,
+	.buck4_voltage[1]	= 1150000,
+	.buck4_voltage[2]	= 1200000,
+	.buck4_voltage[3]	= 1100000,
+	.buck4_voltage[4]	= 1100000,
+	.buck4_voltage[5]	= 1100000,
+	.buck4_voltage[6]	= 1100000,
+	.buck4_voltage[7]	= 1100000,
+
+	.buck_default_idx	= 3,
+	.buck_gpios[0]		= EXYNOS4_GPX2(3),
+	.buck_gpios[1]		= EXYNOS4_GPX2(4),
+	.buck_gpios[2]		= EXYNOS4_GPX2(5),
+
+	.buck_ramp_delay        = 25,
+	.buck2_ramp_enable      = true,
+	.buck3_ramp_enable      = true,
+	.buck4_ramp_enable      = true,
+};
+/* End of S5M8767 */
+#endif
+
+#ifdef CONFIG_VIDEO_S5P_MIPI_CSIS
+static struct regulator_consumer_supply mipi_csi_fixed_voltage_supplies[] = {
+	REGULATOR_SUPPLY("mipi_csi", "s5p-mipi-csis.0"),
+	REGULATOR_SUPPLY("mipi_csi", "s5p-mipi-csis.1"),
+};
+
+static struct regulator_init_data mipi_csi_fixed_voltage_init_data = {
+	.constraints = {
+		.always_on = 1,
+	},
+	.num_consumer_supplies	= ARRAY_SIZE(mipi_csi_fixed_voltage_supplies),
+	.consumer_supplies	= mipi_csi_fixed_voltage_supplies,
+};
+
+static struct fixed_voltage_config mipi_csi_fixed_voltage_config = {
+	.supply_name	= "DC_5V",
+	.microvolts	= 5000000,
+	.gpio		= -EINVAL,
+	.init_data	= &mipi_csi_fixed_voltage_init_data,
+};
+
+static struct platform_device mipi_csi_fixed_voltage = {
+	.name		= "reg-fixed-voltage",
+	.id		= 3,
+	.dev		= {
+		.platform_data	= &mipi_csi_fixed_voltage_config,
+	},
+};
+#endif
+
+#ifdef CONFIG_VIDEO_M5MOLS
+static struct regulator_consumer_supply m5mols_fixed_voltage_supplies[] = {
+	REGULATOR_SUPPLY("core", NULL),
+	REGULATOR_SUPPLY("dig_18", NULL),
+	REGULATOR_SUPPLY("d_sensor", NULL),
+	REGULATOR_SUPPLY("dig_28", NULL),
+	REGULATOR_SUPPLY("a_sensor", NULL),
+	REGULATOR_SUPPLY("dig_12", NULL),
+};
+
+static struct regulator_init_data m5mols_fixed_voltage_init_data = {
+	.constraints = {
+		.always_on = 1,
+	},
+	.num_consumer_supplies	= ARRAY_SIZE(m5mols_fixed_voltage_supplies),
+	.consumer_supplies	= m5mols_fixed_voltage_supplies,
+};
+
+static struct fixed_voltage_config m5mols_fixed_voltage_config = {
+	.supply_name	= "CAM_SENSOR",
+	.microvolts	= 1800000,
+	.gpio		= -EINVAL,
+	.init_data	= &m5mols_fixed_voltage_init_data,
+};
+
+static struct platform_device m5mols_fixed_voltage = {
+	.name		= "reg-fixed-voltage",
+	.id		= 4,
+	.dev		= {
+		.platform_data	= &m5mols_fixed_voltage_config,
+	},
+};
+#endif
+
+static struct regulator_consumer_supply wm8994_fixed_voltage0_supplies[] = {
+	REGULATOR_SUPPLY("AVDD2", "1-001a"),
+	REGULATOR_SUPPLY("CPVDD", "1-001a"),
+};
+
+static struct regulator_consumer_supply wm8994_fixed_voltage1_supplies[] = {
+	REGULATOR_SUPPLY("SPKVDD1", "1-001a"),
+	REGULATOR_SUPPLY("SPKVDD2", "1-001a"),
+};
+
+static struct regulator_consumer_supply wm8994_fixed_voltage2_supplies =
+	REGULATOR_SUPPLY("DBVDD", "1-001a");
+
+static struct regulator_init_data wm8994_fixed_voltage0_init_data = {
+	.constraints = {
+		.always_on = 1,
+	},
+	.num_consumer_supplies	= ARRAY_SIZE(wm8994_fixed_voltage0_supplies),
+	.consumer_supplies	= wm8994_fixed_voltage0_supplies,
+};
+
+static struct regulator_init_data wm8994_fixed_voltage1_init_data = {
+	.constraints = {
+		.always_on = 1,
+	},
+	.num_consumer_supplies	= ARRAY_SIZE(wm8994_fixed_voltage1_supplies),
+	.consumer_supplies	= wm8994_fixed_voltage1_supplies,
+};
+
+static struct regulator_init_data wm8994_fixed_voltage2_init_data = {
+	.constraints = {
+		.always_on = 1,
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &wm8994_fixed_voltage2_supplies,
+};
+
+static struct fixed_voltage_config wm8994_fixed_voltage0_config = {
+	.supply_name	= "VDD_1.8V",
+	.microvolts	= 1800000,
+	.gpio		= -EINVAL,
+	.init_data	= &wm8994_fixed_voltage0_init_data,
+};
+
+static struct fixed_voltage_config wm8994_fixed_voltage1_config = {
+	.supply_name	= "DC_5V",
+	.microvolts	= 5000000,
+	.gpio		= -EINVAL,
+	.init_data	= &wm8994_fixed_voltage1_init_data,
+};
+
+static struct fixed_voltage_config wm8994_fixed_voltage2_config = {
+	.supply_name	= "VDD_3.3V",
+	.microvolts	= 3300000,
+	.gpio		= -EINVAL,
+	.init_data	= &wm8994_fixed_voltage2_init_data,
+};
+
+static struct platform_device wm8994_fixed_voltage0 = {
+	.name		= "reg-fixed-voltage",
+	.id		= 0,
+	.dev		= {
+		.platform_data	= &wm8994_fixed_voltage0_config,
+	},
+};
+
+static struct platform_device wm8994_fixed_voltage1 = {
+	.name		= "reg-fixed-voltage",
+	.id		= 1,
+	.dev		= {
+		.platform_data	= &wm8994_fixed_voltage1_config,
+	},
+};
+
+static struct platform_device wm8994_fixed_voltage2 = {
+	.name		= "reg-fixed-voltage",
+	.id		= 2,
+	.dev		= {
+		.platform_data	= &wm8994_fixed_voltage2_config,
+	},
+};
+
+static struct regulator_consumer_supply wm8994_avdd1_supply =
+	REGULATOR_SUPPLY("AVDD1", "1-001a");
+
+static struct regulator_consumer_supply wm8994_dcvdd_supply =
+	REGULATOR_SUPPLY("DCVDD", "1-001a");
+
+static struct regulator_init_data wm8994_ldo1_data = {
+	.constraints	= {
+		.name		= "AVDD1",
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &wm8994_avdd1_supply,
+};
+
+static struct regulator_init_data wm8994_ldo2_data = {
+	.constraints	= {
+		.name		= "DCVDD",
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &wm8994_dcvdd_supply,
+};
+
+static struct wm8994_pdata wm8994_platform_data = {
+	/* configure gpio1 function: 0x0001(Logic level input/output) */
+	.gpio_defaults[0] = 0x0001,
+	/* If the i2s0 and i2s2 is enabled simultaneously */
+	.gpio_defaults[7] = 0x8100, /* GPIO8  DACDAT3 in */
+	.gpio_defaults[8] = 0x0100, /* GPIO9  ADCDAT3 out */
+	.gpio_defaults[9] = 0x0100, /* GPIO10 LRCLK3  out */
+	.gpio_defaults[10] = 0x0100,/* GPIO11 BCLK3   out */
+	.ldo[0] = { 0, NULL, &wm8994_ldo1_data },
+	.ldo[1] = { 0, NULL, &wm8994_ldo2_data },
+};
+
+static struct i2c_board_info i2c_devs0[] __initdata = {
+#ifdef CONFIG_REGULATOR_S5M8767
+	{
+		I2C_BOARD_INFO("s5m87xx", 0xCC >> 1),
+		.platform_data = &exynos4_s5m8767_pdata,
+		.irq		= IRQ_EINT(26),
+	},
+#else
+	{
+		I2C_BOARD_INFO("max8997", 0x66),
+		.platform_data	= &exynos4_max8997_info,
+	}, {
+		I2C_BOARD_INFO("max77686", (0x12 >> 1)),
+		.platform_data	= &exynos4_max77686_info,
+	},
+#endif
+};
+
+static struct i2c_board_info i2c_devs1[] __initdata = {
+	{
+		I2C_BOARD_INFO("wm8994", 0x1a),
+		.platform_data	= &wm8994_platform_data,
+	},
+};
+
+static struct i2c_board_info i2c_devs2[] __initdata = {
+#ifdef CONFIG_VIDEO_TVOUT
+	{
+		I2C_BOARD_INFO("s5p_ddc", (0x74 >> 1)),
+	},
+#endif
+};
+
+static struct i2c_board_info i2c_devs3[] __initdata = {
+	{
+		I2C_BOARD_INFO("max8952", 0x60),
+		.platform_data	= &exynos4_max8952_info,
+	},
+};
+
+static struct i2c_board_info i2c_devs7[] __initdata = {
+	{
+		I2C_BOARD_INFO("pixcir-ts", 0x5C),
+	},
+};
+
+#ifdef CONFIG_BATTERY_SAMSUNG
+static struct platform_device samsung_device_battery = {
+	.name	= "samsung-fake-battery",
+	.id	= -1,
+};
+#endif
+
+static struct gpio_event_direct_entry smdk4x12_keypad_key_map[] = {
+	{
+		.gpio   = EXYNOS4_GPX0(0),
+		.code   = KEY_POWER,
+	}
+};
+
+static struct gpio_event_input_info smdk4x12_keypad_key_info = {
+	.info.func              = gpio_event_input_func,
+	.info.no_suspend        = true,
+	.debounce_time.tv64	= 5 * NSEC_PER_MSEC,
+	.type                   = EV_KEY,
+	.keymap                 = smdk4x12_keypad_key_map,
+	.keymap_size            = ARRAY_SIZE(smdk4x12_keypad_key_map)
+};
+
+static struct gpio_event_info *smdk4x12_input_info[] = {
+	&smdk4x12_keypad_key_info.info,
+};
+
+static struct gpio_event_platform_data smdk4x12_input_data = {
+	.names  = {
+		"smdk4x12-keypad",
+		NULL,
+	},
+	.info           = smdk4x12_input_info,
+	.info_count     = ARRAY_SIZE(smdk4x12_input_info),
+};
+
+static struct platform_device smdk4x12_input_device = {
+	.name   = GPIO_EVENT_DEV_NAME,
+	.id     = 0,
+	.dev    = {
+		.platform_data = &smdk4x12_input_data,
+	},
+};
+
+static void __init smdk4x12_gpio_power_init(void)
+{
+	int err = 0;
+
+	err = gpio_request_one(EXYNOS4_GPX0(0), 0, "GPX0");
+	if (err) {
+		printk(KERN_ERR "failed to request GPX0 for "
+				"suspend/resume control\n");
+		return;
+	}
+	s3c_gpio_setpull(EXYNOS4_GPX0(0), S3C_GPIO_PULL_NONE);
+
+	gpio_free(EXYNOS4_GPX0(0));
+}
+
+static uint32_t smdk4x12_keymap0[] __initdata = {
+	/* KEY(row, col, keycode) */
+	KEY(1, 0, KEY_D), KEY(1, 1, KEY_A), KEY(1, 2, KEY_B),
+	KEY(1, 3, KEY_E), KEY(1, 4, KEY_C)
+};
+
+static struct matrix_keymap_data smdk4x12_keymap_data0 __initdata = {
+	.keymap		= smdk4x12_keymap0,
+	.keymap_size	= ARRAY_SIZE(smdk4x12_keymap0),
+};
+
+static struct samsung_keypad_platdata smdk4x12_keypad_data0 __initdata = {
+	.keymap_data	= &smdk4x12_keymap_data0,
+	.rows		= 2,
+	.cols		= 5,
+};
+
+static uint32_t smdk4x12_keymap1[] __initdata = {
+	/* KEY(row, col, keycode) */
+	KEY(1, 3, KEY_1), KEY(1, 4, KEY_2), KEY(1, 5, KEY_3),
+	KEY(1, 6, KEY_4), KEY(1, 7, KEY_5),
+	KEY(2, 5, KEY_D), KEY(2, 6, KEY_A), KEY(2, 7, KEY_B),
+	KEY(0, 7, KEY_E), KEY(0, 5, KEY_C)
+};
+
+static struct matrix_keymap_data smdk4x12_keymap_data1 __initdata = {
+	.keymap		= smdk4x12_keymap1,
+	.keymap_size	= ARRAY_SIZE(smdk4x12_keymap1),
+};
+
+static struct samsung_keypad_platdata smdk4x12_keypad_data1 __initdata = {
+	.keymap_data	= &smdk4x12_keymap_data1,
+	.rows		= 3,
+	.cols		= 8,
+};
+
+#ifdef CONFIG_WAKEUP_ASSIST
+static struct platform_device wakeup_assist_device = {
+	.name   = "wakeup_assist",
+};
+#endif
+
+#ifdef CONFIG_VIDEO_FIMG2D
+static struct fimg2d_platdata fimg2d_data __initdata = {
+	.hw_ver = 0x41,
+	.parent_clkname = "mout_g2d0",
+	.clkname = "sclk_fimg2d",
+	.gate_clkname = "fimg2d",
+	.clkrate = 201 * 1000000,	/* 200 Mhz */
+};
+#endif
+
+#ifdef CONFIG_EXYNOS_C2C
+struct exynos_c2c_platdata smdk4x12_c2c_pdata = {
+	.setup_gpio	= NULL,
+	.shdmem_addr	= C2C_SHAREDMEM_BASE,
+	.shdmem_size	= C2C_MEMSIZE_64,
+	.ap_sscm_addr	= NULL,
+	.cp_sscm_addr	= NULL,
+	.rx_width	= C2C_BUSWIDTH_16,
+	.tx_width	= C2C_BUSWIDTH_16,
+	.clk_opp100	= 400,
+	.clk_opp50	= 266,
+	.clk_opp25	= 0,
+	.default_opp_mode	= C2C_OPP50,
+	.get_c2c_state	= NULL,
+	.c2c_sysreg	= S5P_VA_CMU + 0x12000,
+};
+#endif
+
+#ifdef CONFIG_USB_EXYNOS_SWITCH
+static struct s5p_usbswitch_platdata smdk4x12_usbswitch_pdata;
+
+static void __init smdk4x12_usbswitch_init(void)
+{
+	struct s5p_usbswitch_platdata *pdata = &smdk4x12_usbswitch_pdata;
+	int err;
+
+	pdata->gpio_host_detect = EXYNOS4_GPX3(5); /* low active */
+	err = gpio_request_one(pdata->gpio_host_detect, GPIOF_IN, "HOST_DETECT");
+	if (err) {
+		printk(KERN_ERR "failed to request gpio_host_detect\n");
+		return;
+	}
+
+	s3c_gpio_cfgpin(pdata->gpio_host_detect, S3C_GPIO_SFN(0xF));
+	s3c_gpio_setpull(pdata->gpio_host_detect, S3C_GPIO_PULL_NONE);
+	gpio_free(pdata->gpio_host_detect);
+
+	pdata->gpio_device_detect = EXYNOS4_GPX3(4); /* high active */
+	err = gpio_request_one(pdata->gpio_device_detect, GPIOF_IN, "DEVICE_DETECT");
+	if (err) {
+		printk(KERN_ERR "failed to request gpio_host_detect for\n");
+		return;
+	}
+
+	s3c_gpio_cfgpin(pdata->gpio_device_detect, S3C_GPIO_SFN(0xF));
+	s3c_gpio_setpull(pdata->gpio_device_detect, S3C_GPIO_PULL_NONE);
+	gpio_free(pdata->gpio_device_detect);
+
+	if (samsung_board_rev_is_0_0())
+		pdata->gpio_host_vbus = 0;
+	else {
+		pdata->gpio_host_vbus = EXYNOS4_GPL2(0);
+		err = gpio_request_one(pdata->gpio_host_vbus, GPIOF_OUT_INIT_LOW, "HOST_VBUS_CONTROL");
+		if (err) {
+			printk(KERN_ERR "failed to request gpio_host_vbus\n");
+			return;
+		}
+
+		s3c_gpio_setpull(pdata->gpio_host_vbus, S3C_GPIO_PULL_NONE);
+		gpio_free(pdata->gpio_host_vbus);
+	}
+
+	s5p_usbswitch_set_platdata(pdata);
+}
+#endif
+
+#ifdef CONFIG_BUSFREQ_OPP
+/* BUSFREQ to control memory/bus*/
+static struct device_domain busfreq;
+#endif
+
+static struct platform_device exynos4_busfreq = {
+	.id = -1,
+	.name = "exynos-busfreq",
+};
+
+static struct platform_device *smdk4412_devices[] __initdata = {
+	&s3c_device_adc,
+};
+
+static struct platform_device *smdk4x12_devices[] __initdata = {
+	/* Samsung Power Domain */
+	&exynos4_device_pd[PD_MFC],
+	&exynos4_device_pd[PD_G3D],
+	&exynos4_device_pd[PD_LCD0],
+	&exynos4_device_pd[PD_CAM],
+	&exynos4_device_pd[PD_TV],
+	&exynos4_device_pd[PD_GPS],
+	&exynos4_device_pd[PD_GPS_ALIVE],
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_IS
+	&exynos4_device_pd[PD_ISP],
+#endif
+#ifdef CONFIG_FB_MIPI_DSIM
+	&s5p_device_mipi_dsim,
+#endif
+/* mainline fimd */
+#ifdef CONFIG_FB_S3C
+	&s5p_device_fimd0,
+#if defined(CONFIG_LCD_AMS369FG06) || defined(CONFIG_LCD_LMS501KF03)
+	&s3c_device_spi_gpio,
+#elif defined(CONFIG_LCD_WA101S)
+	&smdk4x12_lcd_wa101s,
+#elif defined(CONFIG_LCD_LTE480WV)
+	&smdk4x12_lcd_lte480wv,
+#elif defined(CONFIG_LCD_MIPI_S6E63M0)
+	&smdk4x12_mipi_lcd,
+#endif
+#endif
+	/* legacy fimd */
+#ifdef CONFIG_FB_S5P
+	&s3c_device_fb,
+#ifdef CONFIG_FB_S5P_LMS501KF03
+	&s3c_device_spi_gpio,
+#endif
+#endif
+	&s3c_device_wdt,
+	&s3c_device_rtc,
+	&s3c_device_i2c0,
+	&s3c_device_i2c1,
+	&s3c_device_i2c2,
+	&s3c_device_i2c3,
+	&s3c_device_i2c4,
+	&s3c_device_i2c5,
+	&s3c_device_i2c7,
+#ifdef CONFIG_USB_EHCI_S5P
+	&s5p_device_ehci,
+#endif
+#ifdef CONFIG_USB_OHCI_S5P
+	&s5p_device_ohci,
+#endif
+#ifdef CONFIG_USB_GADGET
+	&s3c_device_usbgadget,
+#endif
+#ifdef CONFIG_USB_ANDROID_RNDIS
+	&s3c_device_rndis,
+#endif
+#ifdef CONFIG_USB_ANDROID
+	&s3c_device_android_usb,
+	&s3c_device_usb_mass_storage,
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC
+	&s3c_device_hsmmc0,
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC1
+	&s3c_device_hsmmc1,
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC2
+	&s3c_device_hsmmc2,
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC3
+	&s3c_device_hsmmc3,
+#endif
+#ifdef CONFIG_S5P_DEV_MSHC
+	&s3c_device_mshci,
+#endif
+#ifdef CONFIG_EXYNOS4_DEV_DWMCI
+	&exynos_device_dwmci,
+#endif
+#ifdef CONFIG_SND_SAMSUNG_AC97
+	&exynos_device_ac97,
+#endif
+#ifdef CONFIG_SND_SAMSUNG_I2S
+	&exynos_device_i2s0,
+#endif
+#ifdef CONFIG_SND_SAMSUNG_PCM
+	&exynos_device_pcm0,
+#endif
+#ifdef CONFIG_SND_SAMSUNG_SPDIF
+	&exynos_device_spdif,
+#endif
+#if defined(CONFIG_SND_SAMSUNG_RP) || defined(CONFIG_SND_SAMSUNG_ALP)
+	&exynos_device_srp,
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_IS
+	&exynos4_device_fimc_is,
+#endif
+#ifdef CONFIG_VIDEO_TVOUT
+	&s5p_device_tvout,
+	&s5p_device_cec,
+	&s5p_device_hpd,
+#endif
+#ifdef CONFIG_FB_S5P_EXTDSP
+	&s3c_device_extdsp,
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS_TV
+	&s5p_device_i2c_hdmiphy,
+	&s5p_device_hdmi,
+	&s5p_device_sdo,
+	&s5p_device_mixer,
+	&s5p_device_cec,
+#endif
+#if defined(CONFIG_VIDEO_FIMC)
+	&s3c_device_fimc0,
+	&s3c_device_fimc1,
+	&s3c_device_fimc2,
+	&s3c_device_fimc3,
+/* CONFIG_VIDEO_SAMSUNG_S5P_FIMC is the feature for mainline */
+#elif defined(CONFIG_VIDEO_SAMSUNG_S5P_FIMC)
+	&s5p_device_fimc0,
+	&s5p_device_fimc1,
+	&s5p_device_fimc2,
+	&s5p_device_fimc3,
+#endif
+#if defined(CONFIG_VIDEO_FIMC_MIPI)
+	&s3c_device_csis0,
+	&s3c_device_csis1,
+#elif defined(CONFIG_VIDEO_S5P_MIPI_CSIS)
+	&s5p_device_mipi_csis0,
+	&s5p_device_mipi_csis1,
+#endif
+#ifdef CONFIG_VIDEO_S5P_MIPI_CSIS
+	&mipi_csi_fixed_voltage,
+#endif
+#ifdef CONFIG_VIDEO_M5MOLS
+	&m5mols_fixed_voltage,
+#endif
+
+#if defined(CONFIG_VIDEO_MFC5X) || defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC)
+	&s5p_device_mfc,
+#endif
+#ifdef CONFIG_S5P_SYSTEM_MMU
+	&SYSMMU_PLATDEV(g2d_acp),
+	&SYSMMU_PLATDEV(fimc0),
+	&SYSMMU_PLATDEV(fimc1),
+	&SYSMMU_PLATDEV(fimc2),
+	&SYSMMU_PLATDEV(fimc3),
+	&SYSMMU_PLATDEV(jpeg),
+	&SYSMMU_PLATDEV(mfc_l),
+	&SYSMMU_PLATDEV(mfc_r),
+	&SYSMMU_PLATDEV(tv),
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_IS
+	&SYSMMU_PLATDEV(is_isp),
+	&SYSMMU_PLATDEV(is_drc),
+	&SYSMMU_PLATDEV(is_fd),
+	&SYSMMU_PLATDEV(is_cpu),
+#endif
+#endif /* CONFIG_S5P_SYSTEM_MMU */
+#ifdef CONFIG_ION_EXYNOS
+	&exynos_device_ion,
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_LITE
+	&exynos_device_flite0,
+	&exynos_device_flite1,
+#endif
+#ifdef CONFIG_VIDEO_FIMG2D
+	&s5p_device_fimg2d,
+#endif
+#ifdef CONFIG_EXYNOS_MEDIA_DEVICE
+	&exynos_device_md0,
+#endif
+#ifdef CONFIG_VIDEO_JPEG_V2X
+	&s5p_device_jpeg,
+#endif
+	&wm8994_fixed_voltage0,
+	&wm8994_fixed_voltage1,
+	&wm8994_fixed_voltage2,
+	&samsung_asoc_dma,
+	&samsung_asoc_idma,
+#ifdef CONFIG_BATTERY_SAMSUNG
+	&samsung_device_battery,
+#endif
+	&samsung_device_keypad,
+#ifdef CONFIG_WAKEUP_ASSIST
+	&wakeup_assist_device,
+#endif
+#ifdef CONFIG_EXYNOS_C2C
+	&exynos_device_c2c,
+#endif
+	&smdk4x12_input_device,
+	&smdk4x12_smsc911x,
+#ifdef CONFIG_S3C64XX_DEV_SPI
+	&exynos_device_spi0,
+#ifndef CONFIG_FB_S5P_LMS501KF03
+	&exynos_device_spi1,
+#endif
+	&exynos_device_spi2,
+#endif
+#ifdef CONFIG_EXYNOS_SETUP_THERMAL
+	&exynos_device_tmu,
+#endif
+#ifdef CONFIG_S5P_DEV_ACE
+	&s5p_device_ace,
+#endif
+	&exynos4_busfreq,
+};
+
+#ifdef CONFIG_EXYNOS_SETUP_THERMAL
+/* below temperature base on the celcius degree */
+struct tmu_data exynos_tmu_data __initdata = {
+	.ts = {
+		.stop_throttle  = 82,
+		.start_throttle = 85,
+		.stop_warning  = 95,
+		.start_warning = 103,
+		.start_tripping = 110, /* temp to do tripping */
+	},
+	.efuse_value = 55,
+	.slope = 0x10008802,
+	.mode = 0,
+};
+#endif
+
+#if defined(CONFIG_VIDEO_TVOUT)
+static struct s5p_platform_hpd hdmi_hpd_data __initdata = {
+
+};
+static struct s5p_platform_cec hdmi_cec_data __initdata = {
+
+};
+#endif
+
+#ifdef CONFIG_VIDEO_EXYNOS_HDMI_CEC
+static struct s5p_platform_cec hdmi_cec_data __initdata = {
+
+};
+#endif
+
+#ifdef CONFIG_VIDEO_SAMSUNG_S5P_FIMC
+static struct s5p_fimc_isp_info isp_info[] = {
+#if defined(CONFIG_VIDEO_S5K4BA)
+	{
+		.board_info	= &s5k4ba_info,
+		.clk_frequency  = 24000000UL,
+		.bus_type	= FIMC_ITU_601,
+#ifdef CONFIG_ITU_A
+		.i2c_bus_num	= 0,
+		.mux_id		= 0, /* A-Port : 0, B-Port : 1 */
+#endif
+#ifdef CONFIG_ITU_B
+		.i2c_bus_num	= 1,
+		.mux_id		= 1, /* A-Port : 0, B-Port : 1 */
+#endif
+		.flags		= FIMC_CLK_INV_VSYNC,
+	},
+#endif
+#if defined(CONFIG_VIDEO_S5K4EA)
+	{
+		.board_info	= &s5k4ea_info,
+		.clk_frequency  = 24000000UL,
+		.bus_type	= FIMC_MIPI_CSI2,
+#ifdef CONFIG_CSI_C
+		.i2c_bus_num	= 0,
+		.mux_id		= 0, /* A-Port : 0, B-Port : 1 */
+#endif
+#ifdef CONFIG_CSI_D
+		.i2c_bus_num	= 1,
+		.mux_id		= 1, /* A-Port : 0, B-Port : 1 */
+#endif
+		.flags		= FIMC_CLK_INV_VSYNC,
+		.csi_data_align = 32,
+	},
+#endif
+#if defined(CONFIG_VIDEO_M5MOLS)
+	{
+		.board_info	= &m5mols_board_info,
+		.clk_frequency  = 24000000UL,
+		.bus_type	= FIMC_MIPI_CSI2,
+#ifdef CONFIG_CSI_C
+		.i2c_bus_num	= 4,
+		.mux_id		= 0, /* A-Port : 0, B-Port : 1 */
+#endif
+#ifdef CONFIG_CSI_D
+		.i2c_bus_num	= 5,
+		.mux_id		= 1, /* A-Port : 0, B-Port : 1 */
+#endif
+		.flags		= FIMC_CLK_INV_PCLK | FIMC_CLK_INV_VSYNC,
+		.csi_data_align = 32,
+	},
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_IS
+#if defined(CONFIG_VIDEO_S5K3H2)
+	{
+		.board_info	= &s5k3h2_sensor_info,
+		.clk_frequency  = 24000000UL,
+		.bus_type	= FIMC_MIPI_CSI2,
+#ifdef CONFIG_S5K3H2_CSI_C
+		.i2c_bus_num	= 0,
+		.mux_id		= 0, /* A-Port : 0, B-Port : 1 */
+		.flite_id	= FLITE_IDX_A,
+		.cam_power	= smdk4x12_cam0_reset,
+#endif
+#ifdef CONFIG_S5K3H2_CSI_D
+		.i2c_bus_num	= 1,
+		.mux_id		= 1, /* A-Port : 0, B-Port : 1 */
+		.flite_id	= FLITE_IDX_B,
+		.cam_power	= smdk4x12_cam1_reset,
+#endif
+		.flags		= 0,
+		.csi_data_align = 24,
+		.use_isp	= true,
+	},
+#endif
+#if defined(CONFIG_VIDEO_S5K3H7)
+	{
+		.board_info	= &s5k3h7_sensor_info,
+		.clk_frequency  = 24000000UL,
+		.bus_type	= FIMC_MIPI_CSI2,
+#ifdef CONFIG_S5K3H7_CSI_C
+		.i2c_bus_num	= 0,
+		.mux_id		= 0, /* A-Port : 0, B-Port : 1 */
+		.flite_id	= FLITE_IDX_A,
+		.cam_power	= smdk4x12_cam0_reset,
+#endif
+#ifdef CONFIG_S5K3H7_CSI_D
+		.i2c_bus_num	= 1,
+		.mux_id		= 1, /* A-Port : 0, B-Port : 1 */
+		.flite_id	= FLITE_IDX_B,
+		.cam_power	= smdk4x12_cam1_reset,
+#endif
+		.csi_data_align = 24,
+		.use_isp	= true,
+	},
+#endif
+#if defined(CONFIG_VIDEO_S5K4E5)
+	{
+		.board_info	= &s5k4e5_sensor_info,
+		.clk_frequency  = 24000000UL,
+		.bus_type	= FIMC_MIPI_CSI2,
+#ifdef CONFIG_S5K4E5_CSI_C
+		.i2c_bus_num	= 0,
+		.mux_id		= 0, /* A-Port : 0, B-Port : 1 */
+		.flite_id	= FLITE_IDX_A,
+		.cam_power	= smdk4x12_cam0_reset,
+#endif
+#ifdef CONFIG_S5K4E5_CSI_D
+		.i2c_bus_num	= 1,
+		.mux_id		= 1, /* A-Port : 0, B-Port : 1 */
+		.flite_id	= FLITE_IDX_B,
+		.cam_power	= smdk4x12_cam1_reset,
+#endif
+		.csi_data_align = 24,
+		.use_isp	= true,
+	},
+#endif
+#if defined(CONFIG_VIDEO_S5K6A3)
+	{
+		.board_info	= &s5k6a3_sensor_info,
+		.clk_frequency  = 12000000UL,
+		.bus_type	= FIMC_MIPI_CSI2,
+#ifdef CONFIG_S5K6A3_CSI_C
+		.i2c_bus_num	= 0,
+		.mux_id		= 0, /* A-Port : 0, B-Port : 1 */
+		.flite_id	= FLITE_IDX_A,
+		.cam_power	= smdk4x12_cam0_reset,
+#endif
+#ifdef CONFIG_S5K6A3_CSI_D
+		.i2c_bus_num	= 1,
+		.mux_id		= 1, /* A-Port : 0, B-Port : 1 */
+		.flite_id	= FLITE_IDX_B,
+		.cam_power	= smdk4x12_cam1_reset,
+#endif
+		.flags		= 0,
+		.csi_data_align = 12,
+		.use_isp	= true,
+	},
+#endif
+#endif
+#if defined(WRITEBACK_ENABLED)
+	{
+		.board_info	= &writeback_info,
+		.bus_type	= FIMC_LCD_WB,
+		.i2c_bus_num	= 0,
+		.mux_id		= 0, /* A-Port : 0, B-Port : 1 */
+		.flags		= FIMC_CLK_INV_VSYNC,
+	},
+#endif
+};
+
+static void __init smdk4x12_subdev_config(void)
+{
+	s3c_fimc0_default_data.isp_info[0] = &isp_info[0];
+	s3c_fimc0_default_data.isp_info[0]->use_cam = true;
+	s3c_fimc0_default_data.isp_info[1] = &isp_info[1];
+	s3c_fimc0_default_data.isp_info[1]->use_cam = true;
+	/* support using two fimc as one sensore */
+	{
+		static struct s5p_fimc_isp_info camcording1;
+		static struct s5p_fimc_isp_info camcording2;
+		memcpy(&camcording1, &isp_info[0], sizeof(struct s5p_fimc_isp_info));
+		memcpy(&camcording2, &isp_info[1], sizeof(struct s5p_fimc_isp_info));
+		s3c_fimc1_default_data.isp_info[0] = &camcording1;
+		s3c_fimc1_default_data.isp_info[0]->use_cam = false;
+		s3c_fimc1_default_data.isp_info[1] = &camcording2;
+		s3c_fimc1_default_data.isp_info[1]->use_cam = false;
+	}
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_IS
+#ifdef CONFIG_VIDEO_S5K3H2
+#ifdef CONFIG_S5K3H2_CSI_C
+	s5p_mipi_csis0_default_data.clk_rate	= 160000000;
+	s5p_mipi_csis0_default_data.lanes	= 2;
+	s5p_mipi_csis0_default_data.alignment	= 24;
+	s5p_mipi_csis0_default_data.hs_settle	= 12;
+#endif
+#ifdef CONFIG_S5K3H2_CSI_D
+	s5p_mipi_csis1_default_data.clk_rate	= 160000000;
+	s5p_mipi_csis1_default_data.lanes	= 2;
+	s5p_mipi_csis1_default_data.alignment	= 24;
+	s5p_mipi_csis1_default_data.hs_settle	= 12;
+#endif
+#endif
+#ifdef CONFIG_VIDEO_S5K3H7
+#ifdef CONFIG_S5K3H7_CSI_C
+	s5p_mipi_csis0_default_data.clk_rate	= 160000000;
+	s5p_mipi_csis0_default_data.lanes	= 2;
+	s5p_mipi_csis0_default_data.alignment	= 24;
+	s5p_mipi_csis0_default_data.hs_settle	= 12;
+#endif
+#ifdef CONFIG_S5K3H7_CSI_D
+	s5p_mipi_csis1_default_data.clk_rate	= 160000000;
+	s5p_mipi_csis1_default_data.lanes	= 2;
+	s5p_mipi_csis1_default_data.alignment	= 24;
+	s5p_mipi_csis1_default_data.hs_settle	= 12;
+#endif
+#endif
+#ifdef CONFIG_VIDEO_S5K4E5
+#ifdef CONFIG_S5K4E5_CSI_C
+	s5p_mipi_csis0_default_data.clk_rate	= 160000000;
+	s5p_mipi_csis0_default_data.lanes	= 2;
+	s5p_mipi_csis0_default_data.alignment	= 24;
+	s5p_mipi_csis0_default_data.hs_settle	= 12;
+#endif
+#ifdef CONFIG_S5K4E5_CSI_D
+	s5p_mipi_csis1_default_data.clk_rate	= 160000000;
+	s5p_mipi_csis1_default_data.lanes	= 2;
+	s5p_mipi_csis1_default_data.alignment	= 24;
+	s5p_mipi_csis1_default_data.hs_settle	= 12;
+#endif
+#endif
+#ifdef CONFIG_VIDEO_S5K6A3
+#ifdef CONFIG_S5K6A3_CSI_C
+	s5p_mipi_csis0_default_data.clk_rate	= 160000000;
+	s5p_mipi_csis0_default_data.lanes 	= 1;
+	s5p_mipi_csis0_default_data.alignment	= 24;
+	s5p_mipi_csis0_default_data.hs_settle	= 12;
+#endif
+#ifdef CONFIG_S5K6A3_CSI_D
+	s5p_mipi_csis1_default_data.clk_rate	= 160000000;
+	s5p_mipi_csis1_default_data.lanes 	= 1;
+	s5p_mipi_csis1_default_data.alignment	= 24;
+	s5p_mipi_csis1_default_data.hs_settle	= 12;
+#endif
+#endif
+#endif
+}
+static void __init smdk4x12_camera_config(void)
+{
+	/* CAM A port(b0010) : PCLK, VSYNC, HREF, DATA[0-4] */
+	s3c_gpio_cfgrange_nopull(EXYNOS4212_GPJ0(0), 8, S3C_GPIO_SFN(2));
+	/* CAM A port(b0010) : DATA[5-7], CLKOUT(MIPI CAM also), FIELD */
+	s3c_gpio_cfgrange_nopull(EXYNOS4212_GPJ1(0), 5, S3C_GPIO_SFN(2));
+	/* CAM B port(b0011) : PCLK, DATA[0-6] */
+	s3c_gpio_cfgrange_nopull(EXYNOS4212_GPM0(0), 8, S3C_GPIO_SFN(3));
+	/* CAM B port(b0011) : FIELD, DATA[7]*/
+	s3c_gpio_cfgrange_nopull(EXYNOS4212_GPM1(0), 2, S3C_GPIO_SFN(3));
+	/* CAM B port(b0011) : VSYNC, HREF, CLKOUT*/
+	s3c_gpio_cfgrange_nopull(EXYNOS4212_GPM2(0), 3, S3C_GPIO_SFN(3));
+
+	/* note : driver strength to max is unnecessary */
+#ifdef CONFIG_VIDEO_M5MOLS
+	s3c_gpio_cfgpin(EXYNOS4_GPX2(6), S3C_GPIO_SFN(0xF));
+	s3c_gpio_setpull(EXYNOS4_GPX2(6), S3C_GPIO_PULL_NONE);
+#endif
+}
+#endif /* CONFIG_VIDEO_SAMSUNG_S5P_FIMC */
+
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_LITE
+static void __set_flite_camera_config(struct exynos_platform_flite *data,
+					u32 active_index, u32 max_cam)
+{
+	data->active_cam_index = active_index;
+	data->num_clients = max_cam;
+}
+
+static void __init smdk4x12_set_camera_flite_platdata(void)
+{
+	int flite0_cam_index = 0;
+	int flite1_cam_index = 0;
+#ifdef CONFIG_VIDEO_S5K3H2
+#ifdef CONFIG_S5K3H2_CSI_C
+	exynos_flite0_default_data.cam[flite0_cam_index++] = &s5k3h2;
+#endif
+#ifdef CONFIG_S5K3H2_CSI_D
+	exynos_flite1_default_data.cam[flite1_cam_index++] = &s5k3h2;
+#endif
+#endif
+#ifdef CONFIG_VIDEO_S5K3H7
+#ifdef CONFIG_S5K3H7_CSI_C
+	exynos_flite0_default_data.cam[flite0_cam_index++] = &s5k3h7;
+#endif
+#ifdef CONFIG_S5K3H7_CSI_D
+	exynos_flite1_default_data.cam[flite1_cam_index++] = &s5k3h7;
+#endif
+#endif
+#ifdef CONFIG_VIDEO_S5K4E5
+#ifdef CONFIG_S5K4E5_CSI_C
+	exynos_flite0_default_data.cam[flite0_cam_index++] = &s5k4e5;
+#endif
+#ifdef CONFIG_S5K4E5_CSI_D
+	exynos_flite1_default_data.cam[flite1_cam_index++] = &s5k4e5;
+#endif
+#endif
+
+#ifdef CONFIG_VIDEO_S5K6A3
+#ifdef CONFIG_S5K6A3_CSI_C
+	exynos_flite0_default_data.cam[flite0_cam_index++] = &s5k6a3;
+#endif
+#ifdef CONFIG_S5K6A3_CSI_D
+	exynos_flite1_default_data.cam[flite1_cam_index++] = &s5k6a3;
+#endif
+#endif
+	__set_flite_camera_config(&exynos_flite0_default_data, 0, flite0_cam_index);
+	__set_flite_camera_config(&exynos_flite1_default_data, 0, flite1_cam_index);
+}
+#endif
+
+#if defined(CONFIG_CMA)
+static void __init exynos4_reserve_mem(void)
+{
+	static struct cma_region regions[] = {
+#ifndef CONFIG_VIDEOBUF2_ION
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_TV
+		{
+			.name = "tv",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_TV * SZ_1K,
+			.start = 0
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_JPEG
+		{
+			.name = "jpeg",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_JPEG * SZ_1K,
+			.start = 0
+		},
+#endif
+#ifdef CONFIG_AUDIO_SAMSUNG_MEMSIZE_SRP
+		{
+			.name = "srp",
+			.size = CONFIG_AUDIO_SAMSUNG_MEMSIZE_SRP * SZ_1K,
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMG2D
+		{
+			.name = "fimg2d",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMG2D * SZ_1K,
+			.start = 0
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMD
+		{
+			.name = "fimd",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMD * SZ_1K,
+			.start = 0
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC0
+		{
+			.name = "fimc0",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC0 * SZ_1K,
+			.start = 0
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC2
+		{
+			.name = "fimc2",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC2 * SZ_1K,
+			.start = 0
+		},
+#endif
+#if !defined(CONFIG_EXYNOS_CONTENT_PATH_PROTECTION) && \
+	defined(CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC3)
+		{
+			.name = "fimc3",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC3 * SZ_1K,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC1
+		{
+			.name = "fimc1",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC1 * SZ_1K,
+			.start = 0
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC_NORMAL
+		{
+			.name = "mfc-normal",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC_NORMAL * SZ_1K,
+			{ .alignment = 1 << 17 },
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC1
+		{
+			.name = "mfc1",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC1 * SZ_1K,
+			{
+				.alignment = 1 << 17,
+			},
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC0
+		{
+			.name = "mfc0",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC0 * SZ_1K,
+			{
+				.alignment = 1 << 17,
+			}
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC
+		{
+			.name = "mfc",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC * SZ_1K,
+			{
+				.alignment = 1 << 17,
+			},
+			.start = 0
+		},
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_IS
+		{
+			.name = "fimc_is",
+			.size = CONFIG_VIDEO_EXYNOS_MEMSIZE_FIMC_IS * SZ_1K,
+			{
+				.alignment = 1 << 26,
+			},
+			.start = 0
+		},
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_IS_BAYER
+		{
+			.name = "fimc_is_isp",
+			.size = CONFIG_VIDEO_EXYNOS_MEMSIZE_FIMC_IS_ISP * SZ_1K,
+			.start = 0
+		},
+#endif
+#endif
+#if !defined(CONFIG_EXYNOS_CONTENT_PATH_PROTECTION) && \
+	defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC)
+		{
+			.name		= "b2",
+			.size		= 32 << 20,
+			{ .alignment	= 128 << 10 },
+		},
+		{
+			.name		= "b1",
+			.size		= 32 << 20,
+			{ .alignment	= 128 << 10 },
+		},
+		{
+			.name		= "fw",
+			.size		= 1 << 20,
+			{ .alignment	= 128 << 10 },
+		},
+#endif
+#else /* !CONFIG_VIDEOBUF2_ION */
+#ifdef CONFIG_FB_S5P
+#error CONFIG_FB_S5P is defined. Select CONFIG_FB_S3C, instead
+#endif
+		{
+			.name	= "ion",
+			.size	= CONFIG_ION_EXYNOS_CONTIGHEAP_SIZE * SZ_1K,
+		},
+#endif /* !CONFIG_VIDEOBUF2_ION */
+		{
+			.size = 0
+		},
+	};
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+	static struct cma_region regions_secure[] = {
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC3
+		{
+			.name = "fimc3",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC3 * SZ_1K,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMD_VIDEO
+		{
+			.name = "video",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMD_VIDEO * SZ_1K,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC_SECURE
+		{
+			.name = "mfc-secure",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC_SECURE * SZ_1K,
+		},
+#endif
+		{
+			.name = "sectbl",
+			.size = SZ_1M,
+		},
+		{
+			.size = 0
+		},
+	};
+#else /* !CONFIG_EXYNOS_CONTENT_PATH_PROTECTION */
+	struct cma_region *regions_secure = NULL;
+#endif
+	static const char map[] __initconst =
+#ifdef CONFIG_EXYNOS_C2C
+		"samsung-c2c=c2c_shdmem;"
+#endif
+		"s3cfb.0/fimd=fimd;exynos4-fb.0/fimd=fimd;"
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+		"s3cfb.0/video=video;exynos4-fb.0/video=video;"
+#endif
+		"s3c-fimc.0=fimc0;s3c-fimc.1=fimc1;s3c-fimc.2=fimc2;s3c-fimc.3=fimc3;"
+		"exynos4210-fimc.0=fimc0;exynos4210-fimc.1=fimc1;exynos4210-fimc.2=fimc2;exynos4210-fimc.3=fimc3;"
+#ifdef CONFIG_VIDEO_MFC5X
+		"s3c-mfc=mfc,mfc0,mfc1;"
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_S5P_MFC
+		"s5p-mfc/f=fw;"
+		"s5p-mfc/a=b1;"
+		"s5p-mfc/b=b2;"
+#endif
+		"samsung-rp=srp;"
+		"s5p-jpeg=jpeg;"
+		"exynos4-fimc-is/f=fimc_is;"
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_IS_BAYER
+		"exynos4-fimc-is/i=fimc_is_isp;"
+#endif
+		"s5p-mixer=tv;"
+		"s5p-fimg2d=fimg2d;"
+		"ion-exynos=ion,fimd,fimc0,fimc1,fimc2,fimc3,mfc,mfc0,mfc1,fw,b1,b2;"
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+		"s5p-smem/video=video;"
+		"s5p-smem/sectbl=sectbl;"
+#endif
+		"s5p-smem/mfc=mfc0;"
+		"s5p-smem/fimc=fimc3;"
+		"s5p-smem/mfc-shm=mfc1,mfc-normal;"
+		"s5p-smem/fimd=fimd;";
+
+	s5p_cma_region_reserve(regions, regions_secure, 0, map);
+}
+#else
+static inline void exynos4_reserve_mem(void)
+{
+}
+#endif /* CONFIG_CMA */
+
+/* LCD Backlight data */
+static struct samsung_bl_gpio_info smdk4x12_bl_gpio_info = {
+	.no = EXYNOS4_GPD0(1),
+	.func = S3C_GPIO_SFN(2),
+};
+
+static struct platform_pwm_backlight_data smdk4x12_bl_data = {
+	.pwm_id = 1,
+#ifdef CONFIG_FB_S5P_LMS501KF03
+	.pwm_period_ns  = 1000,
+#endif
+};
+
+static void __init smdk4x12_map_io(void)
+{
+	clk_xusbxti.rate = 24000000;
+	s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+	s3c24xx_init_clocks(24000000);
+	s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs));
+
+	exynos4_reserve_mem();
+}
+
+static void __init smdk4x12_smsc911x_init(void)
+{
+	u32 cs1;
+
+	/* configure nCS1 width to 16 bits */
+	cs1 = __raw_readl(S5P_SROM_BW) &
+		~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
+	cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
+		(1 << S5P_SROM_BW__WAITENABLE__SHIFT) |
+		(1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
+		S5P_SROM_BW__NCS1__SHIFT;
+	__raw_writel(cs1, S5P_SROM_BW);
+
+	/* set timing for nCS1 suitable for ethernet chip */
+	__raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
+		     (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
+		     (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
+		     (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
+		     (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
+		     (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
+		     (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
+}
+
+static void __init exynos_sysmmu_init(void)
+{
+	ASSIGN_SYSMMU_POWERDOMAIN(fimc0, &exynos4_device_pd[PD_CAM].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(fimc1, &exynos4_device_pd[PD_CAM].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(fimc2, &exynos4_device_pd[PD_CAM].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(fimc3, &exynos4_device_pd[PD_CAM].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(jpeg, &exynos4_device_pd[PD_CAM].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(mfc_l, &exynos4_device_pd[PD_MFC].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(mfc_r, &exynos4_device_pd[PD_MFC].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(tv, &exynos4_device_pd[PD_TV].dev);
+#ifdef CONFIG_VIDEO_FIMG2D
+	sysmmu_set_owner(&SYSMMU_PLATDEV(g2d_acp).dev, &s5p_device_fimg2d.dev);
+#endif
+#if defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC) || defined(CONFIG_VIDEO_MFC5X)
+	sysmmu_set_owner(&SYSMMU_PLATDEV(mfc_l).dev, &s5p_device_mfc.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(mfc_r).dev, &s5p_device_mfc.dev);
+#endif
+#if defined(CONFIG_VIDEO_FIMC)
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc0).dev, &s3c_device_fimc0.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc1).dev, &s3c_device_fimc1.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc2).dev, &s3c_device_fimc2.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc3).dev, &s3c_device_fimc3.dev);
+#elif defined(CONFIG_VIDEO_SAMSUNG_S5P_FIMC)
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc0).dev, &s5p_device_fimc0.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc1).dev, &s5p_device_fimc1.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc2).dev, &s5p_device_fimc2.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc3).dev, &s5p_device_fimc3.dev);
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS_TV
+	sysmmu_set_owner(&SYSMMU_PLATDEV(tv).dev, &s5p_device_mixer.dev);
+#endif
+#ifdef CONFIG_VIDEO_TVOUT
+	sysmmu_set_owner(&SYSMMU_PLATDEV(tv).dev, &s5p_device_tvout.dev);
+#endif
+#ifdef CONFIG_VIDEO_JPEG_V2X
+	sysmmu_set_owner(&SYSMMU_PLATDEV(jpeg).dev, &s5p_device_jpeg.dev);
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_IS
+	ASSIGN_SYSMMU_POWERDOMAIN(is_isp, &exynos4_device_pd[PD_ISP].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(is_drc, &exynos4_device_pd[PD_ISP].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(is_fd, &exynos4_device_pd[PD_ISP].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(is_cpu, &exynos4_device_pd[PD_ISP].dev);
+
+	sysmmu_set_owner(&SYSMMU_PLATDEV(is_isp).dev,
+						&exynos4_device_fimc_is.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(is_drc).dev,
+						&exynos4_device_fimc_is.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(is_fd).dev,
+						&exynos4_device_fimc_is.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(is_cpu).dev,
+						&exynos4_device_fimc_is.dev);
+#endif
+}
+
+#ifdef CONFIG_FB_S5P_EXTDSP
+struct platform_device s3c_device_extdsp = {
+	.name		= "s3cfb_extdsp",
+	.id		= 0,
+};
+
+static struct s3cfb_extdsp_lcd dummy_buffer = {
+	.width = 1280,
+	.height = 720,
+	.bpp = 16,
+};
+
+static struct s3c_platform_fb default_extdsp_data __initdata = {
+	.hw_ver		= 0x70,
+	.nr_wins	= 1,
+	.default_win	= 0,
+	.swap		= FB_SWAP_WORD | FB_SWAP_HWORD,
+	.lcd		= &dummy_buffer
+};
+
+void __init s3cfb_extdsp_set_platdata(struct s3c_platform_fb *pd)
+{
+	struct s3c_platform_fb *npd;
+	int i;
+
+	if (!pd)
+		pd = &default_extdsp_data;
+
+	npd = kmemdup(pd, sizeof(struct s3c_platform_fb), GFP_KERNEL);
+	if (!npd)
+		printk(KERN_ERR "%s: no memory for platform data\n", __func__);
+	else {
+		for (i = 0; i < npd->nr_wins; i++)
+			npd->nr_buffers[i] = 1;
+		s3c_device_extdsp.dev.platform_data = npd;
+	}
+}
+#endif
+
+#define SMDK4412_REV_0_0_ADC_VALUE 0
+#define SMDK4412_REV_0_1_ADC_VALUE 443
+int samsung_board_rev;
+
+static int get_samsung_board_rev(void)
+{
+	int 		adc_val = 0;
+	struct clk	*adc_clk;
+	struct resource	*res;
+	void __iomem	*adc_regs;
+	unsigned int	con;
+	int		ret;
+
+	if ((soc_is_exynos4412() && samsung_rev() < EXYNOS4412_REV_1_0) ||
+		(soc_is_exynos4212() && samsung_rev() < EXYNOS4212_REV_1_0))
+		return SAMSUNG_BOARD_REV_0_0;
+
+	adc_clk = clk_get(NULL, "adc");
+	if (unlikely(IS_ERR(adc_clk)))
+		return SAMSUNG_BOARD_REV_0_0;
+
+	clk_enable(adc_clk);
+
+	res = platform_get_resource(&s3c_device_adc, IORESOURCE_MEM, 0);
+	if (unlikely(!res))
+		goto err_clk;
+
+	adc_regs = ioremap(res->start, resource_size(res));
+	if (unlikely(!adc_regs))
+		goto err_clk;
+
+	writel(S5PV210_ADCCON_SELMUX(3), adc_regs + S5P_ADCMUX);
+
+	con = readl(adc_regs + S3C2410_ADCCON);
+	con &= ~S3C2410_ADCCON_MUXMASK;
+	con &= ~S3C2410_ADCCON_STDBM;
+	con &= ~S3C2410_ADCCON_STARTMASK;
+	con |=  S3C2410_ADCCON_PRSCEN;
+
+	con |= S3C2410_ADCCON_ENABLE_START;
+	writel(con, adc_regs + S3C2410_ADCCON);
+
+	udelay (50);
+
+	adc_val = readl(adc_regs + S3C2410_ADCDAT0) & 0xFFF;
+	writel(0, adc_regs + S3C64XX_ADCCLRINT);
+
+	iounmap(adc_regs);
+err_clk:
+	clk_disable(adc_clk);
+	clk_put(adc_clk);
+
+	ret = (adc_val < SMDK4412_REV_0_1_ADC_VALUE/2) ?
+			SAMSUNG_BOARD_REV_0_0 : SAMSUNG_BOARD_REV_0_1;
+
+	pr_info ("SMDK MAIN Board Rev 0.%d (ADC value:%d)\n", ret, adc_val);
+	return ret;
+}
+
+static void __init smdk4x12_machine_init(void)
+{
+#ifdef CONFIG_S3C64XX_DEV_SPI
+	struct clk *sclk = NULL;
+	struct clk *prnt = NULL;
+	struct device *spi0_dev = &exynos_device_spi0.dev;
+#ifndef CONFIG_FB_S5P_LMS501KF03
+	struct device *spi1_dev = &exynos_device_spi1.dev;
+#endif
+	struct device *spi2_dev = &exynos_device_spi2.dev;
+#endif
+	samsung_board_rev = get_samsung_board_rev();
+#if defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME)
+	exynos_pd_disable(&exynos4_device_pd[PD_MFC].dev);
+	exynos_pd_disable(&exynos4_device_pd[PD_G3D].dev);
+	exynos_pd_disable(&exynos4_device_pd[PD_LCD0].dev);
+	exynos_pd_disable(&exynos4_device_pd[PD_CAM].dev);
+	exynos_pd_disable(&exynos4_device_pd[PD_TV].dev);
+	exynos_pd_disable(&exynos4_device_pd[PD_GPS].dev);
+	exynos_pd_disable(&exynos4_device_pd[PD_GPS_ALIVE].dev);
+	exynos_pd_disable(&exynos4_device_pd[PD_ISP].dev);
+#elif defined(CONFIG_EXYNOS_DEV_PD)
+	/*
+	 * These power domains should be always on
+	 * without runtime pm support.
+	 */
+	exynos_pd_enable(&exynos4_device_pd[PD_MFC].dev);
+	exynos_pd_enable(&exynos4_device_pd[PD_G3D].dev);
+	exynos_pd_enable(&exynos4_device_pd[PD_LCD0].dev);
+	exynos_pd_enable(&exynos4_device_pd[PD_CAM].dev);
+	exynos_pd_enable(&exynos4_device_pd[PD_TV].dev);
+	exynos_pd_enable(&exynos4_device_pd[PD_GPS].dev);
+	exynos_pd_enable(&exynos4_device_pd[PD_GPS_ALIVE].dev);
+	exynos_pd_enable(&exynos4_device_pd[PD_ISP].dev);
+#endif
+	s3c_i2c0_set_platdata(NULL);
+	i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
+
+	s3c_i2c1_set_platdata(NULL);
+	i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
+
+	s3c_i2c2_set_platdata(NULL);
+	i2c_register_board_info(2, i2c_devs2, ARRAY_SIZE(i2c_devs2));
+
+	s3c_i2c3_set_platdata(NULL);
+	i2c_register_board_info(3, i2c_devs3, ARRAY_SIZE(i2c_devs3));
+
+	s3c_i2c4_set_platdata(NULL);
+	s3c_i2c5_set_platdata(NULL);
+
+	s3c_i2c7_set_platdata(NULL);
+	i2c_devs7[0].irq = samsung_board_rev_is_0_0() ? IRQ_EINT(15) : IRQ_EINT(22);
+	i2c_register_board_info(7, i2c_devs7, ARRAY_SIZE(i2c_devs7));
+
+#if defined(CONFIG_FB_S5P_MIPI_DSIM)
+	mipi_fb_init();
+#endif
+#ifdef CONFIG_FB_S3C
+	dev_set_name(&s5p_device_fimd0.dev, "s3cfb.0");
+	clk_add_alias("lcd", "exynos4-fb.0", "lcd", &s5p_device_fimd0.dev);
+	clk_add_alias("sclk_fimd", "exynos4-fb.0", "sclk_fimd", &s5p_device_fimd0.dev);
+	s5p_fb_setname(0, "exynos4-fb");
+#if defined(CONFIG_LCD_AMS369FG06) || defined(CONFIG_LCD_LMS501KF03)
+	spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
+#endif
+	s5p_fimd0_set_platdata(&smdk4x12_lcd0_pdata);
+#ifdef CONFIG_FB_MIPI_DSIM
+	s5p_device_mipi_dsim.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
+#endif
+#ifdef CONFIG_EXYNOS_DEV_PD
+	s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
+#endif
+#endif
+#ifdef CONFIG_FB_S5P
+#ifdef CONFIG_FB_S5P_LMS501KF03
+	spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
+	s3cfb_set_platdata(&lms501kf03_data);
+#else
+	s3cfb_set_platdata(NULL);
+#endif
+#ifdef CONFIG_FB_S5P_MIPI_DSIM
+	s5p_device_dsim.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
+#endif
+#ifdef CONFIG_EXYNOS_DEV_PD
+	s3c_device_fb.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
+#endif
+#endif
+#ifdef CONFIG_USB_EHCI_S5P
+	smdk4x12_ehci_init();
+#endif
+#ifdef CONFIG_USB_OHCI_S5P
+	smdk4x12_ohci_init();
+#endif
+#ifdef CONFIG_USB_GADGET
+	smdk4x12_usbgadget_init();
+#endif
+#ifdef CONFIG_USB_EXYNOS_SWITCH
+	smdk4x12_usbswitch_init();
+#endif
+
+	samsung_bl_set(&smdk4x12_bl_gpio_info, &smdk4x12_bl_data);
+
+#ifdef CONFIG_EXYNOS4_DEV_DWMCI
+	exynos_dwmci_set_platdata(&exynos_dwmci_pdata, 0);
+#endif
+
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_IS
+	exynos4_fimc_is_set_platdata(NULL);
+#ifdef CONFIG_EXYNOS_DEV_PD
+	exynos4_device_fimc_is.dev.parent = &exynos4_device_pd[PD_ISP].dev;
+#endif
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC
+	s3c_sdhci0_set_platdata(&smdk4x12_hsmmc0_pdata);
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC1
+	s3c_sdhci1_set_platdata(&smdk4x12_hsmmc1_pdata);
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC2
+	s3c_sdhci2_set_platdata(&smdk4x12_hsmmc2_pdata);
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC3
+	s3c_sdhci3_set_platdata(&smdk4x12_hsmmc3_pdata);
+#endif
+#ifdef CONFIG_S5P_DEV_MSHC
+	s3c_mshci_set_platdata(&exynos4_mshc_pdata);
+#endif
+#if defined(CONFIG_VIDEO_EXYNOS_TV) && defined(CONFIG_VIDEO_EXYNOS_HDMI)
+	dev_set_name(&s5p_device_hdmi.dev, "exynos4-hdmi");
+	clk_add_alias("hdmi", "s5p-hdmi", "hdmi", &s5p_device_hdmi.dev);
+	clk_add_alias("hdmiphy", "s5p-hdmi", "hdmiphy", &s5p_device_hdmi.dev);
+
+	s5p_tv_setup();
+       
+	/* setup dependencies between TV devices */
+	s5p_device_hdmi.dev.parent = &exynos4_device_pd[PD_TV].dev;
+	s5p_device_mixer.dev.parent = &exynos4_device_pd[PD_TV].dev;
+
+	s5p_i2c_hdmiphy_set_platdata(NULL);
+
+#ifdef CONFIG_VIDEO_EXYNOS_HDMI_CEC
+	s5p_hdmi_cec_set_platdata(&hdmi_cec_data);
+#endif
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_LITE
+	smdk4x12_set_camera_flite_platdata();
+	s3c_set_platdata(&exynos_flite0_default_data,
+			sizeof(exynos_flite0_default_data), &exynos_device_flite0);
+	s3c_set_platdata(&exynos_flite1_default_data,
+			sizeof(exynos_flite1_default_data), &exynos_device_flite1);
+#ifdef CONFIG_EXYNOS_DEV_PD
+	exynos_device_flite0.dev.parent = &exynos4_device_pd[PD_ISP].dev;
+	exynos_device_flite1.dev.parent = &exynos4_device_pd[PD_ISP].dev;
+#endif
+#endif
+#ifdef CONFIG_EXYNOS_SETUP_THERMAL
+	s5p_tmu_set_platdata(&exynos_tmu_data);
+#endif
+#ifdef CONFIG_VIDEO_FIMC
+	s3c_fimc0_set_platdata(&fimc_plat);
+	s3c_fimc1_set_platdata(&fimc_plat);
+	s3c_fimc2_set_platdata(&fimc_plat);
+	s3c_fimc3_set_platdata(NULL);
+#ifdef CONFIG_EXYNOS_DEV_PD
+	s3c_device_fimc0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+	s3c_device_fimc1.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+	s3c_device_fimc2.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+	s3c_device_fimc3.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+	secmem.parent = &exynos4_device_pd[PD_CAM].dev;
+#endif
+#endif
+#ifdef CONFIG_VIDEO_FIMC_MIPI
+	s3c_csis0_set_platdata(NULL);
+	s3c_csis1_set_platdata(NULL);
+#ifdef CONFIG_EXYNOS_DEV_PD
+	s3c_device_csis0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+	s3c_device_csis1.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+#endif
+#endif
+
+#if defined(CONFIG_ITU_A) || defined(CONFIG_CSI_C) \
+	|| defined(CONFIG_S5K3H1_CSI_C) || defined(CONFIG_S5K3H2_CSI_C) \
+	|| defined(CONFIG_S5K6A3_CSI_C)
+	smdk4x12_cam0_reset(1);
+#endif
+#if defined(CONFIG_ITU_B) || defined(CONFIG_CSI_D) \
+	|| defined(CONFIG_S5K3H1_CSI_D) || defined(CONFIG_S5K3H2_CSI_D) \
+	|| defined(CONFIG_S5K6A3_CSI_D)
+	smdk4x12_cam1_reset(1);
+#endif
+#endif /* CONFIG_VIDEO_FIMC */
+#ifdef CONFIG_FB_S5P_EXTDSP
+	s3cfb_extdsp_set_platdata(&default_extdsp_data);
+#endif
+
+
+#ifdef CONFIG_VIDEO_SAMSUNG_S5P_FIMC
+	smdk4x12_camera_config();
+	smdk4x12_subdev_config();
+
+	dev_set_name(&s5p_device_fimc0.dev, "s3c-fimc.0");
+	dev_set_name(&s5p_device_fimc1.dev, "s3c-fimc.1");
+	dev_set_name(&s5p_device_fimc2.dev, "s3c-fimc.2");
+	dev_set_name(&s5p_device_fimc3.dev, "s3c-fimc.3");
+
+	clk_add_alias("fimc", "exynos4210-fimc.0", "fimc", &s5p_device_fimc0.dev);
+	clk_add_alias("sclk_fimc", "exynos4210-fimc.0", "sclk_fimc",
+			&s5p_device_fimc0.dev);
+	clk_add_alias("fimc", "exynos4210-fimc.1", "fimc", &s5p_device_fimc1.dev);
+	clk_add_alias("sclk_fimc", "exynos4210-fimc.1", "sclk_fimc",
+			&s5p_device_fimc1.dev);
+	clk_add_alias("fimc", "exynos4210-fimc.2", "fimc", &s5p_device_fimc2.dev);
+	clk_add_alias("sclk_fimc", "exynos4210-fimc.2", "sclk_fimc",
+			&s5p_device_fimc2.dev);
+	clk_add_alias("fimc", "exynos4210-fimc.3", "fimc", &s5p_device_fimc3.dev);
+	clk_add_alias("sclk_fimc", "exynos4210-fimc.3", "sclk_fimc",
+			&s5p_device_fimc3.dev);
+
+	s3c_fimc_setname(0, "exynos4210-fimc");
+	s3c_fimc_setname(1, "exynos4210-fimc");
+	s3c_fimc_setname(2, "exynos4210-fimc");
+	s3c_fimc_setname(3, "exynos4210-fimc");
+	/* FIMC */
+	s3c_set_platdata(&s3c_fimc0_default_data,
+			 sizeof(s3c_fimc0_default_data), &s5p_device_fimc0);
+	s3c_set_platdata(&s3c_fimc1_default_data,
+			 sizeof(s3c_fimc1_default_data), &s5p_device_fimc1);
+	s3c_set_platdata(&s3c_fimc2_default_data,
+			 sizeof(s3c_fimc2_default_data), &s5p_device_fimc2);
+	s3c_set_platdata(&s3c_fimc3_default_data,
+			 sizeof(s3c_fimc3_default_data), &s5p_device_fimc3);
+#ifdef CONFIG_EXYNOS_DEV_PD
+	s5p_device_fimc0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+	s5p_device_fimc1.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+	s5p_device_fimc2.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+	s5p_device_fimc3.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+#endif
+#ifdef CONFIG_VIDEO_S5P_MIPI_CSIS
+	dev_set_name(&s5p_device_mipi_csis0.dev, "s3c-csis.0");
+	dev_set_name(&s5p_device_mipi_csis1.dev, "s3c-csis.1");
+	clk_add_alias("csis", "s5p-mipi-csis.0", "csis",
+			&s5p_device_mipi_csis0.dev);
+	clk_add_alias("sclk_csis", "s5p-mipi-csis.0", "sclk_csis",
+			&s5p_device_mipi_csis0.dev);
+	clk_add_alias("csis", "s5p-mipi-csis.1", "csis",
+			&s5p_device_mipi_csis1.dev);
+	clk_add_alias("sclk_csis", "s5p-mipi-csis.1", "sclk_csis",
+			&s5p_device_mipi_csis1.dev);
+	dev_set_name(&s5p_device_mipi_csis0.dev, "s5p-mipi-csis.0");
+	dev_set_name(&s5p_device_mipi_csis1.dev, "s5p-mipi-csis.1");
+
+	s3c_set_platdata(&s5p_mipi_csis0_default_data,
+			sizeof(s5p_mipi_csis0_default_data), &s5p_device_mipi_csis0);
+	s3c_set_platdata(&s5p_mipi_csis1_default_data,
+			sizeof(s5p_mipi_csis1_default_data), &s5p_device_mipi_csis1);
+#ifdef CONFIG_EXYNOS_DEV_PD
+	s5p_device_mipi_csis0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+	s5p_device_mipi_csis1.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+#endif
+#endif
+#if defined(CONFIG_ITU_A) || defined(CONFIG_CSI_C) \
+	|| defined(CONFIG_S5K3H1_CSI_C) || defined(CONFIG_S5K3H2_CSI_C) \
+	|| defined(CONFIG_S5K6A3_CSI_C)
+	smdk4x12_cam0_reset(1);
+#endif
+#if defined(CONFIG_ITU_B) || defined(CONFIG_CSI_D) \
+	|| defined(CONFIG_S5K3H1_CSI_D) || defined(CONFIG_S5K3H2_CSI_D) \
+	|| defined(CONFIG_S5K6A3_CSI_D)
+	smdk4x12_cam1_reset(1);
+#endif
+#endif
+
+#if defined(CONFIG_VIDEO_TVOUT)
+	s5p_hdmi_hpd_set_platdata(&hdmi_hpd_data);
+	s5p_hdmi_cec_set_platdata(&hdmi_cec_data);
+#ifdef CONFIG_EXYNOS_DEV_PD
+	s5p_device_tvout.dev.parent = &exynos4_device_pd[PD_TV].dev;
+	exynos4_device_pd[PD_TV].dev.parent = &exynos4_device_pd[PD_LCD0].dev;
+#endif
+#endif
+
+#ifdef CONFIG_VIDEO_JPEG_V2X
+#ifdef CONFIG_EXYNOS_DEV_PD
+	s5p_device_jpeg.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+	exynos4_jpeg_setup_clock(&s5p_device_jpeg.dev, 160000000);
+#endif
+#endif
+
+#ifdef CONFIG_ION_EXYNOS
+	exynos_ion_set_platdata();
+#endif
+
+#if defined(CONFIG_VIDEO_MFC5X) || defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC)
+#ifdef CONFIG_EXYNOS_DEV_PD
+	s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
+#endif
+	if (soc_is_exynos4412() && samsung_rev() >= EXYNOS4412_REV_1_0)
+		exynos4_mfc_setup_clock(&s5p_device_mfc.dev, 200 * MHZ);
+	else
+		exynos4_mfc_setup_clock(&s5p_device_mfc.dev, 267 * MHZ);
+#endif
+
+#if defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC)
+	dev_set_name(&s5p_device_mfc.dev, "s3c-mfc");
+	clk_add_alias("mfc", "s5p-mfc", "mfc", &s5p_device_mfc.dev);
+	s5p_mfc_setname(&s5p_device_mfc, "s5p-mfc");
+#endif
+#ifdef CONFIG_VIDEO_FIMG2D
+	s5p_fimg2d_set_platdata(&fimg2d_data);
+#endif
+	if (samsung_board_rev_is_0_0())
+		samsung_keypad_set_platdata(&smdk4x12_keypad_data0);
+	else
+		samsung_keypad_set_platdata(&smdk4x12_keypad_data1);
+	smdk4x12_smsc911x_init();
+#ifdef CONFIG_EXYNOS_C2C
+	exynos_c2c_set_platdata(&smdk4x12_c2c_pdata);
+#endif
+
+	exynos_sysmmu_init();
+
+	smdk4x12_gpio_power_init();
+
+	platform_add_devices(smdk4x12_devices, ARRAY_SIZE(smdk4x12_devices));
+	if (soc_is_exynos4412())
+		platform_add_devices(smdk4412_devices, ARRAY_SIZE(smdk4412_devices));
+
+#ifdef CONFIG_FB_S3C
+	exynos4_fimd0_setup_clock(&s5p_device_fimd0.dev, "mout_mpll_user",
+				800 * MHZ);
+#endif
+#ifdef CONFIG_S3C64XX_DEV_SPI
+	sclk = clk_get(spi0_dev, "dout_spi0");
+	if (IS_ERR(sclk))
+		dev_err(spi0_dev, "failed to get sclk for SPI-0\n");
+	prnt = clk_get(spi0_dev, "mout_mpll_user");
+	if (IS_ERR(prnt))
+		dev_err(spi0_dev, "failed to get prnt\n");
+	if (clk_set_parent(sclk, prnt))
+		printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
+				prnt->name, sclk->name);
+
+	clk_set_rate(sclk, 800 * 1000 * 1000);
+	clk_put(sclk);
+	clk_put(prnt);
+
+	if (!gpio_request(EXYNOS4_GPB(1), "SPI_CS0")) {
+		gpio_direction_output(EXYNOS4_GPB(1), 1);
+		s3c_gpio_cfgpin(EXYNOS4_GPB(1), S3C_GPIO_SFN(1));
+		s3c_gpio_setpull(EXYNOS4_GPB(1), S3C_GPIO_PULL_UP);
+		exynos_spi_set_info(0, EXYNOS_SPI_SRCCLK_SCLK,
+			ARRAY_SIZE(spi0_csi));
+	}
+
+	spi_register_board_info(spi0_board_info, ARRAY_SIZE(spi0_board_info));
+
+#ifndef CONFIG_FB_S5P_LMS501KF03
+	sclk = clk_get(spi1_dev, "dout_spi1");
+	if (IS_ERR(sclk))
+		dev_err(spi1_dev, "failed to get sclk for SPI-1\n");
+	prnt = clk_get(spi1_dev, "mout_mpll_user");
+	if (IS_ERR(prnt))
+		dev_err(spi1_dev, "failed to get prnt\n");
+	if (clk_set_parent(sclk, prnt))
+		printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
+				prnt->name, sclk->name);
+
+	clk_set_rate(sclk, 800 * 1000 * 1000);
+	clk_put(sclk);
+	clk_put(prnt);
+
+	if (!gpio_request(EXYNOS4_GPB(5), "SPI_CS1")) {
+		gpio_direction_output(EXYNOS4_GPB(5), 1);
+		s3c_gpio_cfgpin(EXYNOS4_GPB(5), S3C_GPIO_SFN(1));
+		s3c_gpio_setpull(EXYNOS4_GPB(5), S3C_GPIO_PULL_UP);
+		exynos_spi_set_info(1, EXYNOS_SPI_SRCCLK_SCLK,
+			ARRAY_SIZE(spi1_csi));
+	}
+
+	spi_register_board_info(spi1_board_info, ARRAY_SIZE(spi1_board_info));
+#endif
+
+	sclk = clk_get(spi2_dev, "dout_spi2");
+	if (IS_ERR(sclk))
+		dev_err(spi2_dev, "failed to get sclk for SPI-2\n");
+	prnt = clk_get(spi2_dev, "mout_mpll_user");
+	if (IS_ERR(prnt))
+		dev_err(spi2_dev, "failed to get prnt\n");
+	if (clk_set_parent(sclk, prnt))
+		printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
+				prnt->name, sclk->name);
+
+	clk_set_rate(sclk, 800 * 1000 * 1000);
+	clk_put(sclk);
+	clk_put(prnt);
+
+	if (!gpio_request(EXYNOS4_GPC1(2), "SPI_CS2")) {
+		gpio_direction_output(EXYNOS4_GPC1(2), 1);
+		s3c_gpio_cfgpin(EXYNOS4_GPC1(2), S3C_GPIO_SFN(1));
+		s3c_gpio_setpull(EXYNOS4_GPC1(2), S3C_GPIO_PULL_UP);
+		exynos_spi_set_info(2, EXYNOS_SPI_SRCCLK_SCLK,
+			ARRAY_SIZE(spi2_csi));
+	}
+
+	spi_register_board_info(spi2_board_info, ARRAY_SIZE(spi2_board_info));
+#endif
+#ifdef CONFIG_BUSFREQ_OPP
+	dev_add(&busfreq, &exynos4_busfreq.dev);
+	ppmu_init(&exynos_ppmu[PPMU_DMC0], &exynos4_busfreq.dev);
+	ppmu_init(&exynos_ppmu[PPMU_DMC1], &exynos4_busfreq.dev);
+	ppmu_init(&exynos_ppmu[PPMU_CPU], &exynos4_busfreq.dev);
+#endif
+	register_reboot_notifier(&exynos4_reboot_notifier);
+}
+
+#ifdef CONFIG_EXYNOS_C2C
+static void __init exynos_c2c_reserve(void)
+{
+	static struct cma_region region[] = {
+		{
+			.name = "c2c_shdmem",
+			.size = 64 * SZ_1M,
+			{ .alignment    = 64 * SZ_1M },
+			.start = C2C_SHAREDMEM_BASE
+		}, {
+		.size = 0,
+		}
+	};
+
+	s5p_cma_region_reserve(region, NULL, 0, NULL);
+}
+#endif
+
+MACHINE_START(SMDK4212, "SMDK4X12")
+	.boot_params	= S5P_PA_SDRAM + 0x100,
+	.init_irq	= exynos4_init_irq,
+	.map_io		= smdk4x12_map_io,
+	.init_machine	= smdk4x12_machine_init,
+	.timer		= &exynos4_timer,
+#ifdef CONFIG_EXYNOS_C2C
+	.reserve	= &exynos_c2c_reserve,
+#endif
+MACHINE_END
+
+MACHINE_START(SMDK4412, "SMDK4X12")
+	.boot_params	= S5P_PA_SDRAM + 0x100,
+	.init_irq	= exynos4_init_irq,
+	.map_io		= smdk4x12_map_io,
+	.init_machine	= smdk4x12_machine_init,
+	.timer		= &exynos4_timer,
+#ifdef CONFIG_EXYNOS_C2C
+	.reserve	= &exynos_c2c_reserve,
+#endif
+MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-smdk5210.c b/arch/arm/mach-exynos/mach-smdk5210.c
new file mode 100644
index 0000000..16ccba4
--- /dev/null
+++ b/arch/arm/mach-exynos/mach-smdk5210.c
@@ -0,0 +1,1174 @@
+/* linux/arch/arm/mach-exynos/mach-smdk5210.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/platform_device.h>
+#include <linux/serial_core.h>
+#include <linux/fb.h>
+#include <linux/lcd.h>
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+#include <linux/mfd/wm8994/pdata.h>
+#include <linux/delay.h>
+#include <linux/pwm_backlight.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi_gpio.h>
+#include <linux/cma.h>
+#include <linux/memblock.h>
+#include <linux/mmc/host.h>
+#include <linux/smsc911x.h>
+#include <linux/clk.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <plat/gpio-cfg.h>
+#include <plat/regs-serial.h>
+#include <plat/regs-fb-v4.h>
+#include <plat/exynos5.h>
+#include <plat/cpu.h>
+#include <plat/clock.h>
+#include <plat/devs.h>
+#include <plat/fb.h>
+#include <plat/fb-s5p.h>
+#include <plat/fb-core.h>
+#include <plat/regs-fb-v4.h>
+#include <plat/backlight.h>
+#include <plat/dp.h>
+#include <plat/iic.h>
+#include <plat/tv-core.h>
+#if defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC)
+#include <plat/s5p-mfc.h>
+#endif
+#include <plat/sdhci.h>
+#include <plat/regs-srom.h>
+#include <plat/ehci.h>
+#include <plat/udc-ss.h>
+
+#include <mach/map.h>
+#include <mach/exynos-ion.h>
+#ifdef CONFIG_EXYNOS4_DEV_DWMCI
+#include <mach/dwmci.h>
+#endif
+
+#include <video/platform_lcd.h>
+
+/* Following are default values for UCON, ULCON and UFCON UART registers */
+#define SMDK5210_UCON_DEFAULT	(S3C2410_UCON_TXILEVEL |	\
+				 S3C2410_UCON_RXILEVEL |	\
+				 S3C2410_UCON_TXIRQMODE |	\
+				 S3C2410_UCON_RXIRQMODE |	\
+				 S3C2410_UCON_RXFIFO_TOI |	\
+				 S3C2443_UCON_RXERR_IRQEN)
+
+#define SMDK5210_ULCON_DEFAULT	S3C2410_LCON_CS8
+
+#define SMDK5210_UFCON_DEFAULT	(S3C2410_UFCON_FIFOMODE |	\
+				 S5PV210_UFCON_TXTRIG4 |	\
+				 S5PV210_UFCON_RXTRIG4)
+
+static struct s3c2410_uartcfg smdk5210_uartcfgs[] __initdata = {
+	[0] = {
+		.hwport		= 0,
+		.flags		= 0,
+		.ucon		= SMDK5210_UCON_DEFAULT,
+		.ulcon		= SMDK5210_ULCON_DEFAULT,
+		.ufcon		= SMDK5210_UFCON_DEFAULT,
+	},
+	[1] = {
+		.hwport		= 1,
+		.flags		= 0,
+		.ucon		= SMDK5210_UCON_DEFAULT,
+		.ulcon		= SMDK5210_ULCON_DEFAULT,
+		.ufcon		= SMDK5210_UFCON_DEFAULT,
+	},
+	[2] = {
+		.hwport		= 2,
+		.flags		= 0,
+		.ucon		= SMDK5210_UCON_DEFAULT,
+		.ulcon		= SMDK5210_ULCON_DEFAULT,
+		.ufcon		= SMDK5210_UFCON_DEFAULT,
+	},
+	[3] = {
+		.hwport		= 3,
+		.flags		= 0,
+		.ucon		= SMDK5210_UCON_DEFAULT,
+		.ulcon		= SMDK5210_ULCON_DEFAULT,
+		.ufcon		= SMDK5210_UFCON_DEFAULT,
+	},
+};
+
+static struct resource smdk5210_smsc911x_resources[] = {
+	[0] = {
+		.start	= EXYNOS4_PA_SROM_BANK(1),
+		.end	= EXYNOS4_PA_SROM_BANK(1) + SZ_64K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= IRQ_EINT(5),
+		.end	= IRQ_EINT(5),
+		.flags	= IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
+	},
+};
+
+static struct smsc911x_platform_config smsc9215_config = {
+	.irq_polarity	= SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+	.irq_type	= SMSC911X_IRQ_TYPE_PUSH_PULL,
+	.flags		= SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
+	.phy_interface	= PHY_INTERFACE_MODE_MII,
+	.mac		= {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
+};
+
+static struct platform_device smdk5210_smsc911x = {
+	.name		= "smsc911x",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(smdk5210_smsc911x_resources),
+	.resource	= smdk5210_smsc911x_resources,
+	.dev		= {
+		.platform_data	= &smsc9215_config,
+	},
+};
+
+#ifdef CONFIG_EXYNOS_MEDIA_DEVICE
+struct platform_device exynos_device_md0 = {
+	.name = "exynos-mdev",
+	.id = 0,
+};
+
+struct platform_device exynos_device_md1 = {
+	.name = "exynos-mdev",
+	.id = 1,
+};
+#endif
+
+#ifdef CONFIG_FB_S3C
+#if defined(CONFIG_LCD_LMS501KF03)
+static int lcd_power_on(struct lcd_device *ld, int enable)
+{
+	return 1;
+}
+
+static int reset_lcd(struct lcd_device *ld)
+{
+	int err = 0;
+
+	err = gpio_request_one(EXYNOS5_GPX0(6), GPIOF_OUT_INIT_HIGH, "GPX0");
+	if (err) {
+		printk(KERN_ERR "failed to request GPX0 for "
+				"lcd reset control\n");
+		return err;
+	}
+	gpio_set_value(EXYNOS5_GPX0(6), 0);
+	mdelay(1);
+
+	gpio_set_value(EXYNOS5_GPX0(6), 1);
+
+	gpio_free(EXYNOS5_GPX0(6));
+
+#ifndef CONFIG_BACKLIGHT_PWM
+	gpio_request_one(EXYNOS5_GPB2(0), GPIOF_OUT_INIT_HIGH, "GPB2");
+	gpio_free(EXYNOS5_GPB2(0));
+#endif
+
+	return 1;
+}
+
+static struct lcd_platform_data lms501kf03_platform_data = {
+	.reset			= reset_lcd,
+	.power_on		= lcd_power_on,
+	.lcd_enabled		= 0,
+	.reset_delay		= 100,	/* 100ms */
+};
+
+#define	LCD_BUS_NUM	3
+#define	DISPLAY_CS	EXYNOS5_GPA2(5)		/*Chip select */
+#define	DISPLAY_CLK	EXYNOS5_GPA2(4)		/* SPI clock */
+#define	DISPLAY_SI	EXYNOS5_GPA2(7)		/* SPI MOSI */
+
+static struct spi_board_info spi_board_info[] __initdata = {
+	{
+		.modalias		= "lms501kf03",
+		.platform_data		= (void *)&lms501kf03_platform_data,
+		.max_speed_hz		= 1200000,
+		.bus_num		= LCD_BUS_NUM,
+		.chip_select		= 0,
+		.mode			= SPI_MODE_3,
+		.controller_data	= (void *)DISPLAY_CS,
+	}
+};
+
+static struct spi_gpio_platform_data lms501kf03_spi_gpio_data = {
+	.sck	= DISPLAY_CLK,
+	.mosi	= DISPLAY_SI,
+	.miso	= -1,
+	.num_chipselect = 1,
+};
+
+static struct platform_device s3c_device_spi_gpio = {
+	.name	= "spi_gpio",
+	.id	= LCD_BUS_NUM,
+	.dev	= {
+		.parent		= &s5p_device_fimd1.dev,
+		.platform_data	= &lms501kf03_spi_gpio_data,
+	},
+};
+
+static struct s3c_fb_pd_win smdk5210_fb_win0 = {
+	.win_mode = {
+		.left_margin	= 8,	/* HBPD */
+		.right_margin	= 8,	/* HFPD */
+		.upper_margin	= 6,	/* VBPD */
+		.lower_margin	= 6,	/* VFPD */
+		.hsync_len	= 6,	/* HSPW */
+		.vsync_len	= 4,	/* VSPW */
+		.xres		= 480,
+		.yres		= 800,
+	},
+	.virtual_x		= 480,
+	.virtual_y		= 1600,
+	.width			= 66,
+	.height			= 109,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+};
+
+static struct s3c_fb_pd_win smdk5210_fb_win1 = {
+	.win_mode = {
+		.left_margin	= 8,	/* HBPD */
+		.right_margin	= 8,	/* HFPD */
+		.upper_margin	= 6,	/* VBPD */
+		.lower_margin	= 6,	/* VFPD */
+		.hsync_len	= 6,	/* HSPW */
+		.vsync_len	= 4,	/* VSPW */
+		.xres		= 480,
+		.yres		= 800,
+	},
+	.virtual_x		= 480,
+	.virtual_y		= 1600,
+	.width			= 66,
+	.height			= 109,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+};
+
+static struct s3c_fb_pd_win smdk5210_fb_win2 = {
+	.win_mode = {
+		.left_margin	= 8,	/* HBPD */
+		.right_margin	= 8,	/* HFPD */
+		.upper_margin	= 6,	/* VBPD */
+		.lower_margin	= 6,	/* VFPD */
+		.hsync_len	= 6,	/* HSPW */
+		.vsync_len	= 4,	/* VSPW */
+		.xres		= 480,
+		.yres		= 800,
+	},
+	.virtual_x		= 480,
+	.virtual_y		= 1600,
+	.width			= 66,
+	.height			= 109,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+};
+
+#elif defined(CONFIG_LCD_WA101S)
+static void lcd_wa101s_set_power(struct plat_lcd_data *pd,
+				   unsigned int power)
+{
+	if (power) {
+#ifndef CONFIG_BACKLIGHT_PWM
+		gpio_request_one(EXYNOS5_GPB2(0), GPIOF_OUT_INIT_HIGH, "GPB2");
+		gpio_free(EXYNOS5_GPB2(0));
+#endif
+		/* fire nRESET on power up */
+		gpio_request_one(EXYNOS5_GPX0(6), GPIOF_OUT_INIT_HIGH, "GPX0");
+		mdelay(100);
+
+		gpio_set_value(EXYNOS5_GPX0(6), 0);
+		mdelay(10);
+
+		gpio_set_value(EXYNOS5_GPX0(6), 1);
+		mdelay(10);
+
+		gpio_free(EXYNOS5_GPX0(6));
+	} else {
+#ifndef CONFIG_BACKLIGHT_PWM
+		gpio_request_one(EXYNOS5_GPB2(0), GPIOF_OUT_INIT_LOW, "GPB2");
+		gpio_free(EXYNOS5_GPB2(0));
+#endif
+	}
+}
+
+static struct plat_lcd_data smdk5210_lcd_wa101s_data = {
+	.set_power		= lcd_wa101s_set_power,
+};
+
+static struct platform_device smdk5210_lcd_wa101s = {
+	.name			= "platform-lcd",
+	.dev.parent		= &s5p_device_fimd1.dev,
+	.dev.platform_data      = &smdk5210_lcd_wa101s_data,
+};
+
+static struct s3c_fb_pd_win smdk5210_fb_win0 = {
+	.win_mode = {
+		.left_margin	= 80,
+		.right_margin	= 48,
+		.upper_margin	= 14,
+		.lower_margin	= 3,
+		.hsync_len	= 32,
+		.vsync_len	= 5,
+		.xres		= 1360, /* real size : 1366 */
+		.yres		= 768,
+	},
+	.virtual_x		= 1360, /* real size : 1366 */
+	.virtual_y		= 768 * 2,
+	.width			= 223,
+	.height			= 125,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+};
+
+static struct s3c_fb_pd_win smdk5210_fb_win1 = {
+	.win_mode = {
+		.left_margin	= 80,
+		.right_margin	= 48,
+		.upper_margin	= 14,
+		.lower_margin	= 3,
+		.hsync_len	= 32,
+		.vsync_len	= 5,
+		.xres		= 1360, /* real size : 1366 */
+		.yres		= 768,
+	},
+	.virtual_x		= 1360, /* real size : 1366 */
+	.virtual_y		= 768 * 2,
+	.width			= 223,
+	.height			= 125,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+};
+
+static struct s3c_fb_pd_win smdk5210_fb_win2 = {
+	.win_mode = {
+		.left_margin	= 80,
+		.right_margin	= 48,
+		.upper_margin	= 14,
+		.lower_margin	= 3,
+		.hsync_len	= 32,
+		.vsync_len	= 5,
+		.xres		= 1360, /* real size : 1366 */
+		.yres		= 768,
+	},
+	.virtual_x		= 1360, /* real size : 1366 */
+	.virtual_y		= 768 * 2,
+	.width			= 223,
+	.height			= 125,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+};
+#elif defined(CONFIG_S5P_DP)
+static struct s3c_fb_pd_win smdk5210_fb_win0 = {
+	.win_mode = {
+		.refresh	= 39,
+		.left_margin	= 172,
+		.right_margin	= 60,
+		.upper_margin	= 25,
+		.lower_margin	= 10,
+		.hsync_len	= 80,
+		.vsync_len	= 10,
+		.xres		= 1920,
+		.yres		= 1080,
+	},
+	.virtual_x		= 1920,
+	.virtual_y		= 1080 * 2,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+};
+
+static struct s3c_fb_pd_win smdk5210_fb_win1 = {
+	.win_mode = {
+		.refresh	= 39,
+		.left_margin	= 172,
+		.right_margin	= 60,
+		.upper_margin	= 25,
+		.lower_margin	= 10,
+		.hsync_len	= 80,
+		.vsync_len	= 10,
+		.xres		= 1920,
+		.yres		= 1080,
+	},
+	.virtual_x		= 1920,
+	.virtual_y		= 1080 * 2,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+};
+
+static struct s3c_fb_pd_win smdk5210_fb_win2 = {
+	.win_mode = {
+		.refresh	= 39,
+		.left_margin	= 172,
+		.right_margin	= 60,
+		.upper_margin	= 25,
+		.lower_margin	= 10,
+		.hsync_len	= 80,
+		.vsync_len	= 10,
+		.xres		= 1920,
+		.yres		= 1080,
+	},
+	.virtual_x		= 1920,
+	.virtual_y		= 1080 * 2,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+};
+#endif
+
+static void exynos_fimd_gpio_setup_24bpp(void)
+{
+	unsigned int reg = 0;
+
+#if defined(CONFIG_LCD_WA101S)
+	exynos4_fimd_cfg_gpios(EXYNOS5210_GPJ0(0), 5, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV4);
+	exynos4_fimd_cfg_gpios(EXYNOS5210_GPJ1(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV4);
+	exynos4_fimd_cfg_gpios(EXYNOS5210_GPJ2(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV4);
+	exynos4_fimd_cfg_gpios(EXYNOS5210_GPJ3(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV4);
+	exynos4_fimd_cfg_gpios(EXYNOS5210_GPJ4(0), 2, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV4);
+#elif defined(CONFIG_LCD_LMS501KF03)
+	exynos4_fimd_cfg_gpios(EXYNOS5210_GPJ0(0), 5, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV4);
+	exynos4_fimd_cfg_gpios(EXYNOS5210_GPJ1(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV1);
+	exynos4_fimd_cfg_gpios(EXYNOS5210_GPJ2(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV1);
+	exynos4_fimd_cfg_gpios(EXYNOS5210_GPJ3(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV1);
+	exynos4_fimd_cfg_gpios(EXYNOS5210_GPJ4(0), 2, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV1);
+#endif
+
+#if defined(CONFIG_S5P_DP)
+	/* Set Hotplug detect for DP */
+	s3c_gpio_cfgpin(EXYNOS5_GPX0(7), S3C_GPIO_SFN(3));
+#endif
+
+	/*
+	 * Set DISP1BLK_CFG register for Display path selection
+	 * DISP1_BLK output source selection : DISP1BLK_CFG[28:27]
+	 *---------------------
+	 *  10 | From DISP0_BLK
+	 *  01 | From DISP1_BLK : selected
+	 *
+	 * FIMD of DISP1_BLK Bypass selection : DISP1BLK_CFG[15]
+	 * ---------------------
+	 *  0 | MIE/MDNIE
+	 *  1 | FIMD : selected
+	 */
+	  reg = __raw_readl(S3C_VA_SYS + 0x0214);
+	reg &= ~((1 << 28) | (1 << 27) | (1 << 15));	/* To save other reset values */
+	reg |=  (0 << 28) | (1 << 27) | (1 << 15);
+	__raw_writel(reg, S3C_VA_SYS + 0x0214);
+}
+
+static struct s3c_fb_platdata smdk5210_lcd1_pdata __initdata = {
+#if defined(CONFIG_LCD_WA101S) || defined(CONFIG_LCD_LMS501KF03) || \
+	defined(CONFIG_S5P_DP)
+	.win[0]		= &smdk5210_fb_win0,
+	.win[1]		= &smdk5210_fb_win1,
+	.win[2]		= &smdk5210_fb_win2,
+#endif
+	.default_win	= 2,
+	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+#if defined(CONFIG_LCD_LMS501KF03)
+	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+#elif defined(CONFIG_LCD_WA101S)
+	.vidcon1	= VIDCON1_INV_VCLK | VIDCON1_INV_HSYNC |
+			  VIDCON1_INV_VSYNC,
+#elif defined(CONFIG_S5P_DP)
+	.vidcon1	= 0,
+#endif
+	.setup_gpio	= exynos_fimd_gpio_setup_24bpp,
+};
+#endif
+
+#ifdef CONFIG_S5P_DP
+static struct video_info smdk5210_dp_config = {
+	.name			= "DELL U2410, for SMDK TEST",
+
+	.h_total		= 2222,
+	.h_active		= 1920,
+	.h_sync_width		= 80,
+	.h_back_porch		= 172,
+	.h_front_porch		= 60,
+
+	.v_total		= 1125,
+	.v_active		= 1080,
+	.v_sync_width		= 10,
+	.v_back_porch		= 25,
+	.v_front_porch		= 10,
+
+	.v_sync_rate		= 60,
+
+	.mvid			= 0,
+	.nvid			= 0,
+
+	.h_sync_polarity	= 0,
+	.v_sync_polarity	= 0,
+	.interlaced		= 0,
+
+	.color_space		= COLOR_RGB,
+	.dynamic_range		= VESA,
+	.ycbcr_coeff		= COLOR_YCBCR601,
+	.color_depth		= COLOR_8,
+
+	.sync_clock		= 0,
+	.even_field		= 0,
+
+	.refresh_denominator	= REFRESH_DENOMINATOR_1,
+
+	.test_pattern		= COLORBAR_32,
+	.link_rate		= LINK_RATE_1_62GBPS,
+	.lane_count		= LANE_COUNT2,
+
+	.video_mute_on		= 0,
+
+	.master_mode		= 0,
+	.bist_mode		= 0,
+};
+
+static struct s5p_dp_platdata smdk5210_dp_data __initdata = {
+	.video_info	= &smdk5210_dp_config,
+	.phy_init	= s5p_dp_phy_init,
+	.phy_exit	= s5p_dp_phy_exit,
+};
+#endif
+
+#ifdef CONFIG_EXYNOS4_DEV_DWMCI
+static void exynos_dwmci_cfg_gpio(int width)
+{
+	unsigned int gpio;
+
+	for (gpio = EXYNOS5_GPC0(0); gpio < EXYNOS5_GPC0(2); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV2);
+	}
+
+	switch (width) {
+	case 8:
+		for (gpio = EXYNOS5_GPC1(3); gpio <= EXYNOS5_GPC1(6); gpio++) {
+			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
+			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+			s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV2);
+		}
+	case 4:
+		for (gpio = EXYNOS5_GPC0(3); gpio <= EXYNOS5_GPC0(6); gpio++) {
+			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+			s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV2);
+		}
+		break;
+	case 1:
+		gpio = EXYNOS5_GPC0(3);
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV2);
+	default:
+		break;
+	}
+}
+
+static struct dw_mci_board exynos_dwmci_pdata __initdata = {
+	.num_slots		= 1,
+	.quirks			= DW_MCI_QUIRK_BROKEN_CARD_DETECTION | DW_MCI_QUIRK_HIGHSPEED,
+	.bus_hz			= 66 * 1000 * 1000,
+	.caps			= MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA,
+	.detect_delay_ms	= 200,
+	.hclk_name		= "dwmci",
+	.cclk_name		= "sclk_dwmci",
+	.cfg_gpio		= exynos_dwmci_cfg_gpio,
+};
+#endif
+
+#ifdef CONFIG_S3C_DEV_HSMMC
+static struct s3c_sdhci_platdata smdk5210_hsmmc0_pdata __initdata = {
+	.cd_type		= S3C_SDHCI_CD_INTERNAL,
+	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
+#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
+	.max_width		= 8,
+	.host_caps		= MMC_CAP_8_BIT_DATA,
+#endif
+};
+#endif
+
+#ifdef CONFIG_S3C_DEV_HSMMC1
+static struct s3c_sdhci_platdata smdk5210_hsmmc1_pdata __initdata = {
+	.cd_type		= S3C_SDHCI_CD_INTERNAL,
+	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+#endif
+
+#ifdef CONFIG_S3C_DEV_HSMMC2
+static struct s3c_sdhci_platdata smdk5210_hsmmc2_pdata __initdata = {
+	.cd_type		= S3C_SDHCI_CD_INTERNAL,
+	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
+#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
+	.max_width		= 8,
+	.host_caps		= MMC_CAP_8_BIT_DATA,
+#endif
+};
+#endif
+
+#ifdef CONFIG_S3C_DEV_HSMMC3
+static struct s3c_sdhci_platdata smdk5210_hsmmc3_pdata __initdata = {
+	.cd_type		= S3C_SDHCI_CD_INTERNAL,
+	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+#endif
+
+static struct regulator_consumer_supply wm8994_fixed_voltage0_supplies[] = {
+	REGULATOR_SUPPLY("AVDD2", "1-001a"),
+	REGULATOR_SUPPLY("CPVDD", "1-001a"),
+};
+
+static struct regulator_consumer_supply wm8994_fixed_voltage1_supplies[] = {
+	REGULATOR_SUPPLY("SPKVDD1", "1-001a"),
+	REGULATOR_SUPPLY("SPKVDD2", "1-001a"),
+};
+
+static struct regulator_consumer_supply wm8994_fixed_voltage2_supplies =
+	REGULATOR_SUPPLY("DBVDD", "1-001a");
+
+static struct regulator_init_data wm8994_fixed_voltage0_init_data = {
+	.constraints = {
+		.always_on = 1,
+	},
+	.num_consumer_supplies	= ARRAY_SIZE(wm8994_fixed_voltage0_supplies),
+	.consumer_supplies	= wm8994_fixed_voltage0_supplies,
+};
+
+static struct regulator_init_data wm8994_fixed_voltage1_init_data = {
+	.constraints = {
+		.always_on = 1,
+	},
+	.num_consumer_supplies	= ARRAY_SIZE(wm8994_fixed_voltage1_supplies),
+	.consumer_supplies	= wm8994_fixed_voltage1_supplies,
+};
+
+static struct regulator_init_data wm8994_fixed_voltage2_init_data = {
+	.constraints = {
+		.always_on = 1,
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &wm8994_fixed_voltage2_supplies,
+};
+
+static struct fixed_voltage_config wm8994_fixed_voltage0_config = {
+	.supply_name	= "VDD_1.8V",
+	.microvolts	= 1800000,
+	.gpio		= -EINVAL,
+	.init_data	= &wm8994_fixed_voltage0_init_data,
+};
+
+static struct fixed_voltage_config wm8994_fixed_voltage1_config = {
+	.supply_name	= "DC_5V",
+	.microvolts	= 5000000,
+	.gpio		= -EINVAL,
+	.init_data	= &wm8994_fixed_voltage1_init_data,
+};
+
+static struct fixed_voltage_config wm8994_fixed_voltage2_config = {
+	.supply_name	= "VDD_3.3V",
+	.microvolts	= 3300000,
+	.gpio		= -EINVAL,
+	.init_data	= &wm8994_fixed_voltage2_init_data,
+};
+
+static struct platform_device wm8994_fixed_voltage0 = {
+	.name		= "reg-fixed-voltage",
+	.id		= 0,
+	.dev		= {
+		.platform_data	= &wm8994_fixed_voltage0_config,
+	},
+};
+
+static struct platform_device wm8994_fixed_voltage1 = {
+	.name		= "reg-fixed-voltage",
+	.id		= 1,
+	.dev		= {
+		.platform_data	= &wm8994_fixed_voltage1_config,
+	},
+};
+
+static struct platform_device wm8994_fixed_voltage2 = {
+	.name		= "reg-fixed-voltage",
+	.id		= 2,
+	.dev		= {
+		.platform_data	= &wm8994_fixed_voltage2_config,
+	},
+};
+
+static struct regulator_consumer_supply wm8994_avdd1_supply =
+	REGULATOR_SUPPLY("AVDD1", "1-001a");
+
+static struct regulator_consumer_supply wm8994_dcvdd_supply =
+	REGULATOR_SUPPLY("DCVDD", "1-001a");
+
+static struct regulator_init_data wm8994_ldo1_data = {
+	.constraints	= {
+		.name		= "AVDD1",
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &wm8994_avdd1_supply,
+};
+
+static struct regulator_init_data wm8994_ldo2_data = {
+	.constraints	= {
+		.name		= "DCVDD",
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &wm8994_dcvdd_supply,
+};
+
+static struct wm8994_pdata wm8994_platform_data = {
+	/* configure gpio1 function: 0x0001(Logic level input/output) */
+	.gpio_defaults[0] = 0x0001,
+	/* If the i2s0 and i2s2 is enabled simultaneously */
+	.gpio_defaults[7] = 0x8100, /* GPIO8  DACDAT3 in */
+	.gpio_defaults[8] = 0x0100, /* GPIO9  ADCDAT3 out */
+	.gpio_defaults[9] = 0x0100, /* GPIO10 LRCLK3  out */
+	.gpio_defaults[10] = 0x0100,/* GPIO11 BCLK3   out */
+	.ldo[0] = { 0, NULL, &wm8994_ldo1_data },
+	.ldo[1] = { 0, NULL, &wm8994_ldo2_data },
+};
+
+static struct i2c_board_info i2c_devs1[] __initdata = {
+	{
+		I2C_BOARD_INFO("wm8994", 0x1a),
+		.platform_data	= &wm8994_platform_data,
+	},
+};
+
+static struct i2c_board_info i2c_devs2[] __initdata = {
+	{
+		I2C_BOARD_INFO("exynos_hdcp", (0x74 >> 1)),
+	},
+};
+
+#ifdef CONFIG_USB_EHCI_S5P
+static struct s5p_ehci_platdata smdk5210_ehci_pdata;
+
+static void __init smdk5210_ehci_init(void)
+{
+	struct s5p_ehci_platdata *pdata = &smdk5210_ehci_pdata;
+
+	s5p_ehci_set_platdata(pdata);
+}
+#endif
+
+#ifdef CONFIG_USB_OHCI_S5P
+static struct s5p_ohci_platdata smdk5210_ohci_pdata;
+
+static void __init smdk5210_ohci_init(void)
+{
+	struct s5p_ohci_platdata *pdata = &smdk5210_ohci_pdata;
+
+	s5p_ohci_set_platdata(pdata);
+}
+#endif
+
+#ifdef CONFIG_EXYNOS_DEV_SS_UDC
+static struct exynos_ss_udc_plat smdk5210_ss_udc_pdata;
+
+static void __init smdk5210_ss_udc_init(void)
+{
+	struct exynos_ss_udc_plat *pdata = &smdk5210_ss_udc_pdata;
+
+	exynos_ss_udc_set_platdata(pdata);
+}
+#endif
+
+static struct platform_device *smdk5210_devices[] __initdata = {
+#ifdef CONFIG_EXYNOS_MEDIA_DEVICE
+	&exynos_device_md0,
+	&exynos_device_md1,
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS_GSCALER
+	&exynos5_device_gsc0,
+	&exynos5_device_gsc1,
+	&exynos5_device_gsc2,
+	&exynos5_device_gsc3,
+#endif
+#ifdef CONFIG_S5P_DP
+	&s5p_device_dp,
+#endif
+#ifdef CONFIG_FB_S3C
+	&s5p_device_fimd1,
+#if defined(CONFIG_LCD_LMS501KF03)
+	&s3c_device_spi_gpio,
+#elif defined(CONFIG_LCD_WA101S)
+	&smdk5210_lcd_wa101s,
+#endif	
+#endif	
+#if defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC)
+	&s5p_device_mfc,
+#endif
+#ifdef CONFIG_ION_EXYNOS
+	&exynos_device_ion,
+#endif
+	&s3c_device_i2c1,
+	&s3c_device_i2c2,
+#ifdef CONFIG_S3C_DEV_HSMMC
+	&s3c_device_hsmmc0,
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC1
+	&s3c_device_hsmmc1,
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC2
+	&s3c_device_hsmmc2,
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC3
+	&s3c_device_hsmmc3,
+#endif
+#ifdef CONFIG_SND_SAMSUNG_AC97
+	&exynos_device_ac97,
+#endif
+#ifdef CONFIG_SND_SAMSUNG_I2S
+	&exynos_device_i2s0,
+#endif
+#ifdef CONFIG_SND_SAMSUNG_PCM
+	&exynos_device_pcm0,
+#endif
+#ifdef CONFIG_SND_SAMSUNG_SPDIF
+	&exynos_device_spdif,
+#endif
+#ifdef CONFIG_SND_SAMSUNG_RP
+	&exynos_device_srp,
+#endif
+	&wm8994_fixed_voltage0,
+	&wm8994_fixed_voltage1,
+	&wm8994_fixed_voltage2,
+	&samsung_asoc_dma,
+	&samsung_asoc_idma,
+#ifdef CONFIG_EXYNOS4_DEV_DWMCI
+	&exynos_device_dwmci,
+#endif
+	&smdk5210_smsc911x,
+
+#ifdef CONFIG_VIDEO_EXYNOS_TV
+#ifdef CONFIG_VIDEO_EXYNOS_HDMI
+	&s5p_device_hdmi,
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS_HDMIPHY
+	&s5p_device_i2c_hdmiphy,
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS_MIXER
+	&s5p_device_mixer,
+#endif
+#endif
+#ifdef CONFIG_USB_EHCI_S5P
+	&s5p_device_ehci,
+#endif
+#ifdef CONFIG_USB_OHCI_S5P
+	&s5p_device_ohci,
+#endif
+#ifdef CONFIG_EXYNOS_DEV_SS_UDC
+	&exynos_device_ss_udc,
+#endif
+};
+
+#ifdef CONFIG_SAMSUNG_DEV_BACKLIGHT
+/* LCD Backlight data */
+static struct samsung_bl_gpio_info smdk5210_bl_gpio_info = {
+	.no = EXYNOS5_GPB2(0),
+	.func = S3C_GPIO_SFN(2),
+};
+
+static struct platform_pwm_backlight_data smdk5210_bl_data = {
+	.pwm_id = 0,
+#if defined(CONFIG_LCD_LMS501KF03)
+	.pwm_period_ns  = 1000,
+#endif
+};
+#endif
+
+#if defined(CONFIG_S5P_MEM_CMA)
+static void __init exynos5_cma_region_reserve(
+			struct cma_region *regions_normal,
+			struct cma_region *regions_secure)
+{
+	struct cma_region *reg;
+	size_t size_secure = 0, align_secure = 0;
+	phys_addr_t paddr = 0;
+
+	for (reg = regions_normal; reg->size != 0; reg++) {
+		if ((reg->alignment & (reg->alignment - 1)) || reg->reserved)
+			continue;
+
+		if (reg->start) {
+			if (!memblock_is_region_reserved(reg->start, reg->size)
+			    && memblock_reserve(reg->start, reg->size) >= 0)
+				reg->reserved = 1;
+		} else {
+			paddr = __memblock_alloc_base(reg->size, reg->alignment,
+					MEMBLOCK_ALLOC_ACCESSIBLE);
+			if (paddr) {
+				reg->start = paddr;
+				reg->reserved = 1;
+				if (reg->size & (reg->alignment - 1))
+					memblock_free(paddr + reg->size,
+						ALIGN(reg->size, reg->alignment)
+						- reg->size);
+			}
+		}
+	}
+
+	if (regions_secure && regions_secure->size) {
+		for (reg = regions_secure; reg->size != 0; reg++)
+			size_secure += reg->size;
+
+		reg--;
+
+		align_secure = reg->alignment;
+		BUG_ON(align_secure & (align_secure - 1));
+
+		paddr -= size_secure;
+		paddr &= ~(align_secure - 1);
+
+		if (!memblock_reserve(paddr, size_secure)) {
+			do {
+				reg->start = paddr;
+				reg->reserved = 1;
+				paddr += reg->size;
+			} while (reg-- != regions_secure);
+		}
+	}
+}
+
+static void __init exynos5_reserve_mem(void)
+{
+	static struct cma_region regions[] = {
+#ifdef CONFIG_ANDROID_PMEM_MEMSIZE_PMEM
+		{
+			.name = "pmem",
+			.size = CONFIG_ANDROID_PMEM_MEMSIZE_PMEM * SZ_1K,
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_ANDROID_PMEM_MEMSIZE_PMEM_GPU1
+		{
+			.name = "pmem_gpu1",
+			.size = CONFIG_ANDROID_PMEM_MEMSIZE_PMEM_GPU1 * SZ_1K,
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMD
+		{
+			.name = "fimd",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMD * SZ_1K,
+			.start = 0
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_GSC0
+		{
+			.name = "gsc0",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_GSC0 * SZ_1K,
+			.start = 0
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_GSC1
+		{
+			.name = "gsc1",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_GSC1 * SZ_1K,
+			.start = 0
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_GSC2
+		{
+			.name = "gsc2",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_GSC2 * SZ_1K,
+			.start = 0
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_GSC3
+		{
+			.name = "gsc3",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_GSC3 * SZ_1K,
+			.start = 0
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_S5P_MFC
+		{
+			.name		= "fw",
+			.size		= 1 << 20,
+			{ .alignment	= 128 << 10 },
+			.start		= 0x44000000,
+		},
+		{
+			.name		= "b1",
+			.size		= 32 << 20,
+			.start		= 0x45000000,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_TV
+		{
+			.name = "tv",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_TV * SZ_1K,
+			.start = 0
+		},
+#endif
+		{
+			.size = 0
+		},
+	};
+	static const char map[] __initconst =
+		"android_pmem.0=pmem;android_pmem.1=pmem_gpu1;"
+		"s3cfb.0=fimd;"
+		"exynos-gsc.0=gsc0;exynos-gsc.1=gsc1;exynos-gsc.2=gsc2;exynos-gsc.3=gsc3;"
+		"ion-exynos=fimd,gsc0,gsc1,gsc2,gsc3;"
+		"s5p-mfc-v6/f=fw;"
+		"s5p-mfc-v6/a=b1;"
+		"s5p-mixer=tv;";
+
+	cma_set_defaults(regions, map);
+
+	exynos5_cma_region_reserve(regions, NULL);
+}
+#else /* !CONFIG_S5P_MEM_CMA */
+static inline void exynos5_reserve_mem(void)
+{
+}
+#endif
+
+static void __init smdk5210_map_io(void)
+{
+	clk_xusbxti.rate = 24000000;
+	s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+	s3c24xx_init_clocks(24000000);
+	s3c24xx_init_uarts(smdk5210_uartcfgs, ARRAY_SIZE(smdk5210_uartcfgs));
+	exynos5_reserve_mem();
+}
+
+static void __init smdk5210_smsc911x_init(void)
+{
+	u32 cs1;
+
+	/* configure nCS1 width to 16 bits */
+	cs1 = __raw_readl(S5P_SROM_BW) &
+		~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
+	cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
+		(1 << S5P_SROM_BW__WAITENABLE__SHIFT) |
+		(1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
+		S5P_SROM_BW__NCS1__SHIFT;
+	__raw_writel(cs1, S5P_SROM_BW);
+
+	/* set timing for nCS1 suitable for ethernet chip */
+	__raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
+		     (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
+		     (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
+		     (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
+		     (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
+		     (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
+		     (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
+}
+
+static void s5p_tv_setup(void)
+{
+	/* direct HPD to HDMI chip */
+	gpio_request(EXYNOS5_GPX3(7), "hpd-plug");
+
+	gpio_direction_input(EXYNOS5_GPX3(7));
+	s3c_gpio_cfgpin(EXYNOS5_GPX3(7), S3C_GPIO_SFN(0x3));
+	s3c_gpio_setpull(EXYNOS5_GPX3(7), S3C_GPIO_PULL_NONE);
+
+	/* setup dependencies between TV devices */
+	/* This will be added after power domain for exynos5 is developed */
+	/* s5p_device_hdmi.dev.parent = &exynos4_device_pd[PD_TV].dev; */
+	/* s5p_device_mixer.dev.parent = &exynos4_device_pd[PD_TV].dev; */
+}
+
+static void __init smdk5210_machine_init(void)
+{
+#if defined(CONFIG_VIDEO_EXYNOS_TV) && defined(CONFIG_VIDEO_EXYNOS_HDMI)
+	dev_set_name(&s5p_device_hdmi.dev, "exynos5-hdmi");
+	clk_add_alias("hdmi", "s5p-hdmi", "hdmi", &s5p_device_hdmi.dev);
+	clk_add_alias("hdmiphy", "s5p-hdmi", "hdmiphy", &s5p_device_hdmi.dev);
+#endif
+	s3c_i2c1_set_platdata(NULL);
+	i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
+	s3c_i2c2_set_platdata(NULL);
+	i2c_register_board_info(2, i2c_devs2, ARRAY_SIZE(i2c_devs2));
+
+#ifdef CONFIG_FB_S3C
+	dev_set_name(&s5p_device_fimd1.dev, "s3cfb.1");
+	clk_add_alias("lcd", "exynos5-fb.1", "lcd", &s5p_device_fimd1.dev);
+	clk_add_alias("sclk_fimd", "exynos5-fb.1", "sclk_fimd",
+			&s5p_device_fimd1.dev);
+	s5p_fb_setname(1, "exynos5-fb");
+
+#if defined(CONFIG_LCD_LMS501KF03)
+	spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
+#endif
+	s5p_fimd1_set_platdata(&smdk5210_lcd1_pdata);
+#endif
+
+#ifdef CONFIG_S5P_DP
+	s5p_dp_set_platdata(&smdk5210_dp_data);
+#endif
+
+#ifdef CONFIG_SAMSUNG_DEV_BACKLIGHT
+	samsung_bl_set(&smdk5210_bl_gpio_info, &smdk5210_bl_data);
+#endif
+
+#if defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC)
+	dev_set_name(&s5p_device_mfc.dev, "s3c-mfc");
+	clk_add_alias("mfc", "s5p-mfc-v6", "mfc", &s5p_device_mfc.dev);
+	s5p_mfc_setname(&s5p_device_mfc, "s5p-mfc-v6");
+#endif
+#ifdef CONFIG_ION_EXYNOS
+	exynos_ion_set_platdata();
+#endif
+
+#ifdef CONFIG_EXYNOS4_DEV_DWMCI
+	exynos_dwmci_set_platdata(&exynos_dwmci_pdata);
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC
+	s3c_sdhci0_set_platdata(&smdk5210_hsmmc0_pdata);
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC1
+	s3c_sdhci1_set_platdata(&smdk5210_hsmmc1_pdata);
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC2
+	s3c_sdhci2_set_platdata(&smdk5210_hsmmc2_pdata);
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC3
+	s3c_sdhci3_set_platdata(&smdk5210_hsmmc3_pdata);
+#endif
+#ifdef CONFIG_USB_EHCI_S5P
+	smdk5210_ehci_init();
+#endif
+#ifdef CONFIG_USB_OHCI_S5P
+	smdk5210_ohci_init();
+#endif
+#ifdef CONFIG_EXYNOS_DEV_SS_UDC
+	smdk5210_ss_udc_init();
+#endif
+	smdk5210_smsc911x_init();
+	platform_add_devices(smdk5210_devices, ARRAY_SIZE(smdk5210_devices));
+
+#ifdef CONFIG_FB_S3C
+	exynos4_fimd_setup_clock(&s5p_device_fimd1.dev, "sclk_fimd", "mout_mpll_user",
+				800 * MHZ);
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS_TV
+	s5p_tv_setup();
+	s5p_i2c_hdmiphy_set_platdata(NULL);
+#endif
+}
+
+MACHINE_START(SMDK5210, "SMDK5210")
+	.boot_params	= S5P_PA_SDRAM + 0x100,
+	.init_irq	= exynos5_init_irq,
+	.map_io		= smdk5210_map_io,
+	.init_machine	= smdk5210_machine_init,
+	.timer		= &exynos4_timer,
+MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-smdk5250.c b/arch/arm/mach-exynos/mach-smdk5250.c
new file mode 100644
index 0000000..4f68120
--- /dev/null
+++ b/arch/arm/mach-exynos/mach-smdk5250.c
@@ -0,0 +1,1316 @@
+/* linux/arch/arm/mach-exynos/mach-smdk5250.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/platform_device.h>
+#include <linux/serial_core.h>
+#include <linux/clk.h>
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+#include <linux/memblock.h>
+#include <linux/smsc911x.h>
+#include <linux/delay.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <media/s5k4ba_platform.h>
+#include <media/m5mols.h>
+#include <media/exynos_gscaler.h>
+#include <media/exynos_flite.h>
+#include <media/exynos_fimc_is.h>
+#include <plat/gpio-cfg.h>
+#include <plat/adc.h>
+#include <plat/regs-serial.h>
+#include <plat/exynos5.h>
+#include <plat/cpu.h>
+#include <plat/clock.h>
+#include <plat/hwmon.h>
+#include <plat/devs.h>
+#include <plat/regs-srom.h>
+#include <plat/iic.h>
+#include <plat/pd.h>
+#include <plat/backlight.h>
+#include <plat/ehci.h>
+#include <plat/usbgadget.h>
+#include <plat/usb-switch.h>
+#include <plat/s5p-mfc.h>
+#include <plat/fimg2d.h>
+#include <plat/tv-core.h>
+
+#include <plat/mipi_csis.h>
+#include <mach/map.h>
+#include <mach/exynos-ion.h>
+#include <mach/sysmmu.h>
+#include <mach/ppmu.h>
+#include <mach/dev.h>
+#include <mach/regs-pmu.h>
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+#include <mach/secmem.h>
+#endif
+#ifdef CONFIG_VIDEO_JPEG_V2X
+#include <plat/jpeg.h>
+#endif
+#ifdef CONFIG_EXYNOS_C2C
+#include <mach/c2c.h>
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS_TV
+#include <plat/tvout.h>
+#endif
+
+#include <plat/media.h>
+
+#include "board-smdk5250.h"
+
+#define REG_INFORM4            (S5P_INFORM4)
+
+/* Following are default values for UCON, ULCON and UFCON UART registers */
+#define SMDK5250_UCON_DEFAULT	(S3C2410_UCON_TXILEVEL |	\
+				 S3C2410_UCON_RXILEVEL |	\
+				 S3C2410_UCON_TXIRQMODE |	\
+				 S3C2410_UCON_RXIRQMODE |	\
+				 S3C2410_UCON_RXFIFO_TOI |	\
+				 S3C2443_UCON_RXERR_IRQEN)
+
+#define SMDK5250_ULCON_DEFAULT	S3C2410_LCON_CS8
+
+#define SMDK5250_UFCON_DEFAULT	(S3C2410_UFCON_FIFOMODE |	\
+				 S5PV210_UFCON_TXTRIG4 |	\
+				 S5PV210_UFCON_RXTRIG4)
+
+static struct s3c2410_uartcfg smdk5250_uartcfgs[] __initdata = {
+	[0] = {
+		.hwport		= 0,
+		.flags		= 0,
+		.ucon		= SMDK5250_UCON_DEFAULT,
+		.ulcon		= SMDK5250_ULCON_DEFAULT,
+		.ufcon		= SMDK5250_UFCON_DEFAULT,
+	},
+	[1] = {
+		.hwport		= 1,
+		.flags		= 0,
+		.ucon		= SMDK5250_UCON_DEFAULT,
+		.ulcon		= SMDK5250_ULCON_DEFAULT,
+		.ufcon		= SMDK5250_UFCON_DEFAULT,
+	},
+	[2] = {
+		.hwport		= 2,
+		.flags		= 0,
+		.ucon		= SMDK5250_UCON_DEFAULT,
+		.ulcon		= SMDK5250_ULCON_DEFAULT,
+		.ufcon		= SMDK5250_UFCON_DEFAULT,
+	},
+	[3] = {
+		.hwport		= 3,
+		.flags		= 0,
+		.ucon		= SMDK5250_UCON_DEFAULT,
+		.ulcon		= SMDK5250_ULCON_DEFAULT,
+		.ufcon		= SMDK5250_UFCON_DEFAULT,
+	},
+};
+
+static struct resource smdk5250_smsc911x_resources[] = {
+	[0] = {
+		.start	= EXYNOS4_PA_SROM_BANK(1),
+		.end	= EXYNOS4_PA_SROM_BANK(1) + SZ_64K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= IRQ_EINT(5),
+		.end	= IRQ_EINT(5),
+		.flags	= IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
+	},
+};
+
+static struct smsc911x_platform_config smsc9215_config = {
+	.irq_polarity	= SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+	.irq_type	= SMSC911X_IRQ_TYPE_PUSH_PULL,
+	.flags		= SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
+	.phy_interface	= PHY_INTERFACE_MODE_MII,
+	.mac		= {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
+};
+
+static struct platform_device smdk5250_smsc911x = {
+	.name		= "smsc911x",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(smdk5250_smsc911x_resources),
+	.resource	= smdk5250_smsc911x_resources,
+	.dev		= {
+		.platform_data	= &smsc9215_config,
+	},
+};
+
+#ifdef CONFIG_EXYNOS_MEDIA_DEVICE
+struct platform_device exynos_device_md0 = {
+	.name = "exynos-mdev",
+	.id = 0,
+};
+
+struct platform_device exynos_device_md1 = {
+	.name = "exynos-mdev",
+	.id = 1,
+};
+
+struct platform_device exynos_device_md2 = {
+	.name = "exynos-mdev",
+	.id = 2,
+};
+#endif
+
+#if defined CONFIG_VIDEO_EXYNOS5_FIMC_IS
+static struct exynos5_platform_fimc_is exynos5_fimc_is_data;
+
+#if defined CONFIG_VIDEO_S5K4E5
+static struct exynos5_fimc_is_sensor_info s5k4e5= {
+	.sensor_name = "S5K4E5",
+	.sensor_id = SENSOR_NAME_S5K4E5,
+#if defined CONFIG_S5K4E5_POSITION_FRONT
+	.sensor_position = SENSOR_POSITION_FRONT,
+#elif  defined CONFIG_S5K4E5_POSITION_REAR
+	.sensor_position = SENSOR_POSITION_REAR,
+#endif
+#if defined CONFIG_S5K4E5_CSI_C
+	.csi_id = CSI_ID_A,
+	.flite_id = FLITE_ID_A,
+	.i2c_channel = SENSOR_CONTROL_I2C0,
+#elif  defined CONFIG_S5K4E5_CSI_D
+	.csi_id = CSI_ID_B,
+	.flite_id = FLITE_ID_B,
+	.i2c_channel = SENSOR_CONTROL_I2C1,
+#endif
+
+	.max_width = 2560,
+	.max_height = 1920,
+	.max_frame_rate = 30,
+
+	.mipi_lanes = 2,
+	.mipi_settle = 12,
+	.mipi_align = 24,
+};
+#endif
+
+#if defined CONFIG_VIDEO_S5K6A3
+static struct exynos5_fimc_is_sensor_info s5k6a3= {
+	.sensor_name = "S5K6A3",
+	.sensor_id = SENSOR_NAME_S5K6A3,
+#if defined CONFIG_S5K6A3_POSITION_FRONT
+	.sensor_position = SENSOR_POSITION_FRONT,
+#elif  defined CONFIG_S5K6A3_POSITION_REAR
+	.sensor_position = SENSOR_POSITION_REAR,
+#endif
+#if defined CONFIG_S5K6A3_CSI_C
+	.csi_id = CSI_ID_A,
+	.flite_id = FLITE_ID_A,
+	.i2c_channel = SENSOR_CONTROL_I2C0,
+#elif  defined CONFIG_S5K6A3_CSI_D
+	.csi_id = CSI_ID_B,
+	.flite_id = FLITE_ID_B,
+	.i2c_channel = SENSOR_CONTROL_I2C1,
+#endif
+
+	.max_width = 1280,
+	.max_height = 720,
+	.max_frame_rate = 30,
+
+	.mipi_lanes = 1,
+	.mipi_settle = 12,
+	.mipi_align = 24,
+};
+#endif
+#endif
+
+#ifdef CONFIG_EXYNOS_C2C
+struct exynos_c2c_platdata smdk5250_c2c_pdata = {
+	.setup_gpio	= NULL,
+	.shdmem_addr	= C2C_SHAREDMEM_BASE,
+	.shdmem_size	= C2C_MEMSIZE_64,
+	.ap_sscm_addr	= NULL,
+	.cp_sscm_addr	= NULL,
+	.rx_width	= C2C_BUSWIDTH_16,
+	.tx_width	= C2C_BUSWIDTH_16,
+	.clk_opp100	= 400,
+	.clk_opp50	= 200,
+	.clk_opp25	= 100,
+	.default_opp_mode	= C2C_OPP50,
+	.get_c2c_state	= NULL,
+	.c2c_sysreg	= S5P_VA_CMU + 0x6000,
+};
+#endif
+
+#ifdef CONFIG_VIDEO_FIMG2D
+static struct fimg2d_platdata fimg2d_data __initdata = {
+	.hw_ver		= 0x42,
+	.gate_clkname	= "fimg2d",
+};
+#endif
+
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_LITE
+#if defined(CONFIG_ITU_A)
+static int smdk5250_cam0_reset(int dummy)
+{
+	int err;
+	/* Camera A */
+	err = gpio_request(EXYNOS5_GPX1(2), "GPX1");
+	if (err)
+		printk(KERN_ERR "#### failed to request GPX1_2 ####\n");
+
+	s3c_gpio_setpull(EXYNOS5_GPX1(2), S3C_GPIO_PULL_NONE);
+	gpio_direction_output(EXYNOS5_GPX1(2), 0);
+	gpio_direction_output(EXYNOS5_GPX1(2), 1);
+	gpio_free(EXYNOS5_GPX1(2));
+
+	return 0;
+}
+#endif
+#if defined(CONFIG_ITU_B)
+static int smdk5250_cam1_reset(int dummy)
+{
+	int err;
+	/* Camera A */
+	err = gpio_request(EXYNOS5_GPX1(0), "GPX1");
+	if (err)
+		printk(KERN_ERR "#### failed to request GPX1_2 ####\n");
+
+	s3c_gpio_setpull(EXYNOS5_GPX1(0), S3C_GPIO_PULL_NONE);
+	gpio_direction_output(EXYNOS5_GPX1(0), 0);
+	gpio_direction_output(EXYNOS5_GPX1(0), 1);
+	gpio_free(EXYNOS5_GPX1(0));
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_VIDEO_S5K4BA
+static struct s5k4ba_mbus_platform_data s5k4ba_mbus_plat = {
+	.id		= 0,
+	.fmt = {
+		.width	= 1600,
+		.height	= 1200,
+		/*.code	= V4L2_MBUS_FMT_UYVY8_2X8,*/
+		.code	= V4L2_MBUS_FMT_VYUY8_2X8,
+	},
+	.clk_rate	= 24000000UL,
+#ifdef CONFIG_ITU_A
+	.set_power	= smdk5250_cam0_reset,
+#endif
+#ifdef CONFIG_ITU_B
+	.set_power	= smdk5250_cam1_reset,
+#endif
+};
+
+static struct i2c_board_info s5k4ba_info = {
+	I2C_BOARD_INFO("S5K4BA", 0x2d),
+	.platform_data = &s5k4ba_mbus_plat,
+};
+#endif
+
+/* 1 MIPI Cameras */
+#ifdef CONFIG_VIDEO_M5MOLS
+static struct m5mols_platform_data m5mols_platdata = {
+#ifdef CONFIG_CSI_C
+	.gpio_rst = EXYNOS5_GPX1(2), /* ISP_RESET */
+#endif
+#ifdef CONFIG_CSI_D
+	.gpio_rst = EXYNOS5_GPX1(0), /* ISP_RESET */
+#endif
+	.enable_rst = true, /* positive reset */
+	.irq = IRQ_EINT(22),
+};
+
+static struct i2c_board_info m5mols_board_info = {
+	I2C_BOARD_INFO("M5MOLS", 0x1F),
+	.platform_data = &m5mols_platdata,
+};
+#endif
+#endif /* CONFIG_VIDEO_EXYNOS_FIMC_LITE */
+
+#ifdef CONFIG_VIDEO_EXYNOS_MIPI_CSIS
+static struct regulator_consumer_supply mipi_csi_fixed_voltage_supplies[] = {
+	REGULATOR_SUPPLY("mipi_csi", "s5p-mipi-csis.0"),
+	REGULATOR_SUPPLY("mipi_csi", "s5p-mipi-csis.1"),
+};
+
+static struct regulator_init_data mipi_csi_fixed_voltage_init_data = {
+	.constraints = {
+		.always_on = 1,
+	},
+	.num_consumer_supplies	= ARRAY_SIZE(mipi_csi_fixed_voltage_supplies),
+	.consumer_supplies	= mipi_csi_fixed_voltage_supplies,
+};
+
+static struct fixed_voltage_config mipi_csi_fixed_voltage_config = {
+	.supply_name	= "DC_5V",
+	.microvolts	= 5000000,
+	.gpio		= -EINVAL,
+	.init_data	= &mipi_csi_fixed_voltage_init_data,
+};
+
+static struct platform_device mipi_csi_fixed_voltage = {
+	.name		= "reg-fixed-voltage",
+	.id		= 3,
+	.dev		= {
+		.platform_data	= &mipi_csi_fixed_voltage_config,
+	},
+};
+#endif
+
+#ifdef CONFIG_VIDEO_M5MOLS
+static struct regulator_consumer_supply m5mols_fixed_voltage_supplies[] = {
+	REGULATOR_SUPPLY("core", NULL),
+	REGULATOR_SUPPLY("dig_18", NULL),
+	REGULATOR_SUPPLY("d_sensor", NULL),
+	REGULATOR_SUPPLY("dig_28", NULL),
+	REGULATOR_SUPPLY("a_sensor", NULL),
+	REGULATOR_SUPPLY("dig_12", NULL),
+};
+
+static struct regulator_init_data m5mols_fixed_voltage_init_data = {
+	.constraints = {
+		.always_on = 1,
+	},
+	.num_consumer_supplies	= ARRAY_SIZE(m5mols_fixed_voltage_supplies),
+	.consumer_supplies	= m5mols_fixed_voltage_supplies,
+};
+
+static struct fixed_voltage_config m5mols_fixed_voltage_config = {
+	.supply_name	= "CAM_SENSOR",
+	.microvolts	= 1800000,
+	.gpio		= -EINVAL,
+	.init_data	= &m5mols_fixed_voltage_init_data,
+};
+
+static struct platform_device m5mols_fixed_voltage = {
+	.name		= "reg-fixed-voltage",
+	.id		= 4,
+	.dev		= {
+		.platform_data	= &m5mols_fixed_voltage_config,
+	},
+};
+#endif
+
+static struct i2c_board_info i2c_devs2[] __initdata = {
+#ifdef CONFIG_VIDEO_EXYNOS_TV
+	{
+		I2C_BOARD_INFO("exynos_hdcp", (0x74 >> 1)),
+	},
+#endif
+};
+
+#ifdef CONFIG_S3C_DEV_HWMON
+static struct s3c_hwmon_pdata smdk5250_hwmon_pdata __initdata = {
+	/* Reference voltage (1.2V) */
+	.in[0] = &(struct s3c_hwmon_chcfg) {
+		.name		= "smdk:reference-voltage",
+		.mult		= 3300,
+		.div		= 4096,
+	},
+};
+#endif
+
+#ifdef CONFIG_USB_EHCI_S5P
+static struct s5p_ehci_platdata smdk5250_ehci_pdata;
+
+static void __init smdk5250_ehci_init(void)
+{
+	struct s5p_ehci_platdata *pdata = &smdk5250_ehci_pdata;
+
+#ifndef CONFIG_USB_EXYNOS_SWITCH
+	if (samsung_rev() >= EXYNOS5250_REV_1_0) {
+		if (gpio_request_one(EXYNOS5_GPX2(6), GPIOF_OUT_INIT_HIGH,
+			"HOST_VBUS_CONTROL"))
+			printk(KERN_ERR "failed to request gpio_host_vbus\n");
+		else {
+			s3c_gpio_setpull(EXYNOS5_GPX2(6), S3C_GPIO_PULL_NONE);
+			gpio_free(EXYNOS5_GPX2(6));
+		}
+	}
+#endif
+	s5p_ehci_set_platdata(pdata);
+}
+#endif
+
+#ifdef CONFIG_USB_OHCI_S5P
+static struct s5p_ohci_platdata smdk5250_ohci_pdata;
+
+static void __init smdk5250_ohci_init(void)
+{
+	struct s5p_ohci_platdata *pdata = &smdk5250_ohci_pdata;
+
+	s5p_ohci_set_platdata(pdata);
+}
+#endif
+
+/* USB GADGET */
+#ifdef CONFIG_USB_S3C_OTGD
+static struct s5p_usbgadget_platdata smdk5250_usbgadget_pdata;
+
+static void __init smdk5250_usbgadget_init(void)
+{
+	struct s5p_usbgadget_platdata *pdata = &smdk5250_usbgadget_pdata;
+
+	s5p_usbgadget_set_platdata(pdata);
+}
+#endif
+
+#ifdef CONFIG_EXYNOS_DEV_SS_UDC
+static struct exynos_usb3_drd_pdata smdk5250_ss_udc_pdata;
+
+static void __init smdk5250_ss_udc_init(void)
+{
+	struct exynos_usb3_drd_pdata *pdata = &smdk5250_ss_udc_pdata;
+
+	exynos_ss_udc_set_platdata(pdata);
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_EXYNOS
+static struct exynos_usb3_drd_pdata smdk5250_xhci_pdata;
+
+static void __init smdk5250_xhci_init(void)
+{
+	struct exynos_usb3_drd_pdata *pdata = &smdk5250_xhci_pdata;
+
+	exynos_xhci_set_platdata(pdata);
+}
+#endif
+
+static struct s5p_usbswitch_platdata smdk5250_usbswitch_pdata;
+
+static void __init smdk5250_usbswitch_init(void)
+{
+	struct s5p_usbswitch_platdata *pdata = &smdk5250_usbswitch_pdata;
+	int err;
+
+	/* USB 2.0 detect GPIO */
+	if (samsung_rev() < EXYNOS5250_REV_1_0) {
+		pdata->gpio_device_detect = 0;
+		pdata->gpio_host_vbus = 0;
+	} else {
+		pdata->gpio_host_detect = EXYNOS5_GPX1(6);
+		err = gpio_request_one(pdata->gpio_host_detect, GPIOF_IN,
+			"HOST_DETECT");
+		if (err) {
+			printk(KERN_ERR "failed to request host gpio\n");
+			return;
+		}
+
+		s3c_gpio_cfgpin(pdata->gpio_host_detect, S3C_GPIO_SFN(0xF));
+		s3c_gpio_setpull(pdata->gpio_host_detect, S3C_GPIO_PULL_NONE);
+		gpio_free(pdata->gpio_host_detect);
+
+		pdata->gpio_device_detect = EXYNOS5_GPX3(4);
+		err = gpio_request_one(pdata->gpio_device_detect, GPIOF_IN,
+			"DEVICE_DETECT");
+		if (err) {
+			printk(KERN_ERR "failed to request device gpio\n");
+			return;
+		}
+
+		s3c_gpio_cfgpin(pdata->gpio_device_detect, S3C_GPIO_SFN(0xF));
+		s3c_gpio_setpull(pdata->gpio_device_detect, S3C_GPIO_PULL_NONE);
+		gpio_free(pdata->gpio_device_detect);
+
+		pdata->gpio_host_vbus = EXYNOS5_GPX2(6);
+		err = gpio_request_one(pdata->gpio_host_vbus,
+			GPIOF_OUT_INIT_LOW,
+			"HOST_VBUS_CONTROL");
+		if (err) {
+			printk(KERN_ERR "failed to request host_vbus gpio\n");
+			return;
+		}
+
+		s3c_gpio_setpull(pdata->gpio_host_vbus, S3C_GPIO_PULL_NONE);
+		gpio_free(pdata->gpio_host_vbus);
+	}
+
+	/* USB 3.0 DRD detect GPIO */
+	if (samsung_rev() < EXYNOS5250_REV_1_0) {
+		pdata->gpio_drd_host_detect = 0;
+		pdata->gpio_drd_device_detect = 0;
+	} else {
+		pdata->gpio_drd_host_detect = EXYNOS5_GPX1(7);
+		err = gpio_request_one(pdata->gpio_drd_host_detect, GPIOF_IN,
+			"DRD_HOST_DETECT");
+		if (err) {
+			printk(KERN_ERR "failed to request drd_host gpio\n");
+			return;
+		}
+
+		s3c_gpio_cfgpin(pdata->gpio_drd_host_detect, S3C_GPIO_SFN(0xF));
+		s3c_gpio_setpull(pdata->gpio_drd_host_detect,
+			S3C_GPIO_PULL_NONE);
+		gpio_free(pdata->gpio_drd_host_detect);
+
+		pdata->gpio_drd_device_detect = EXYNOS5_GPX0(6);
+		err = gpio_request_one(pdata->gpio_drd_device_detect, GPIOF_IN,
+			"DRD_DEVICE_DETECT");
+		if (err) {
+			printk(KERN_ERR "failed to request drd_device\n");
+			return;
+		}
+
+		s3c_gpio_cfgpin(pdata->gpio_drd_device_detect,
+			S3C_GPIO_SFN(0xF));
+		s3c_gpio_setpull(pdata->gpio_drd_device_detect,
+			S3C_GPIO_PULL_NONE);
+		gpio_free(pdata->gpio_drd_device_detect);
+	}
+
+	s5p_usbswitch_set_platdata(pdata);
+}
+
+#ifdef CONFIG_BATTERY_SAMSUNG
+static struct platform_device samsung_device_battery = {
+	.name	= "samsung-fake-battery",
+	.id	= -1,
+};
+#endif
+
+static struct gpio_event_direct_entry smdk5250_keypad_key_map[] = {
+	{
+		.gpio   = EXYNOS5_GPX0(0),
+		.code   = KEY_POWER,
+	}
+};
+
+static struct gpio_event_input_info smdk5250_keypad_key_info = {
+	.info.func              = gpio_event_input_func,
+	.info.no_suspend        = true,
+	.debounce_time.tv64	= 5 * NSEC_PER_MSEC,
+	.type                   = EV_KEY,
+	.keymap                 = smdk5250_keypad_key_map,
+	.keymap_size            = ARRAY_SIZE(smdk5250_keypad_key_map)
+};
+
+static struct gpio_event_info *smdk5250_input_info[] = {
+	&smdk5250_keypad_key_info.info,
+};
+
+static struct gpio_event_platform_data smdk5250_input_data = {
+	.names  = {
+		"smdk5250-keypad",
+		NULL,
+	},
+	.info           = smdk5250_input_info,
+	.info_count     = ARRAY_SIZE(smdk5250_input_info),
+};
+
+static struct platform_device smdk5250_input_device = {
+	.name   = GPIO_EVENT_DEV_NAME,
+	.id     = 0,
+	.dev    = {
+		.platform_data = &smdk5250_input_data,
+	},
+};
+
+static void __init smdk5250_gpio_power_init(void)
+{
+	int err = 0;
+
+	err = gpio_request_one(EXYNOS5_GPX0(0), 0, "GPX0");
+	if (err) {
+		printk(KERN_ERR "failed to request GPX0 for "
+				"suspend/resume control\n");
+		return;
+	}
+	s3c_gpio_setpull(EXYNOS5_GPX0(0), S3C_GPIO_PULL_NONE);
+
+	gpio_free(EXYNOS5_GPX0(0));
+}
+
+#ifdef CONFIG_WAKEUP_ASSIST
+static struct platform_device wakeup_assist_device = {
+	.name = "wakeup_assist",
+};
+#endif
+
+static struct i2c_board_info i2c_devs7[] __initdata = {
+	{
+		I2C_BOARD_INFO("egalax_i2c", 0x04),
+		.irq		= IRQ_EINT(25),
+		.platform_data	= &exynos5_egalax_data,
+	},
+};
+
+#ifdef CONFIG_BUSFREQ_OPP
+/* BUSFREQ to control memory/bus*/
+static struct device_domain busfreq;
+#endif
+
+static struct platform_device exynos5_busfreq = {
+	.id = -1,
+	.name = "exynos-busfreq",
+};
+
+static struct platform_device *smdk5250_devices[] __initdata = {
+	&s3c_device_wdt,
+	&s3c_device_i2c2,
+	&s3c_device_i2c4,
+	&s3c_device_i2c5,
+#if defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC)
+	&s5p_device_mfc,
+#endif
+#ifdef CONFIG_VIDEO_JPEG_V2X
+	&s5p_device_jpeg,
+#endif
+#ifdef CONFIG_ION_EXYNOS
+	&exynos_device_ion,
+#endif
+#ifdef CONFIG_VIDEO_FIMG2D
+	&s5p_device_fimg2d,
+#endif
+#ifdef CONFIG_EXYNOS_MEDIA_DEVICE
+	&exynos_device_md0,
+	&exynos_device_md1,
+	&exynos_device_md2,
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS5_FIMC_IS
+	&exynos5_device_fimc_is,
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS_GSCALER
+	&exynos5_device_gsc0,
+	&exynos5_device_gsc1,
+	&exynos5_device_gsc2,
+	&exynos5_device_gsc3,
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_LITE
+	&exynos_device_flite0,
+	&exynos_device_flite1,
+	&exynos_device_flite2,
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS_MIPI_CSIS
+	&s5p_device_mipi_csis0,
+	&s5p_device_mipi_csis1,
+	&mipi_csi_fixed_voltage,
+#endif
+#ifdef CONFIG_VIDEO_M5MOLS
+	&m5mols_fixed_voltage,
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS_ROTATOR
+	&exynos_device_rotator,
+#endif
+	&s3c_device_rtc,
+	&smdk5250_smsc911x,
+#ifdef CONFIG_VIDEO_EXYNOS_TV
+#ifdef CONFIG_VIDEO_EXYNOS_HDMI
+	&s5p_device_hdmi,
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS_HDMIPHY
+	&s5p_device_i2c_hdmiphy,
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS_MIXER
+	&s5p_device_mixer,
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS_HDMI_CEC
+	&s5p_device_cec,
+#endif
+#endif
+#ifdef CONFIG_S5P_DEV_ACE
+	&s5p_device_ace,
+#endif
+#ifdef CONFIG_EXYNOS_C2C
+	&exynos_device_c2c,
+#endif
+	&exynos5_device_ahci,
+};
+
+#ifdef CONFIG_VIDEO_EXYNOS_HDMI_CEC
+static struct s5p_platform_cec hdmi_cec_data __initdata = {
+
+};
+#endif
+
+#if defined(CONFIG_CMA)
+static void __init exynos_reserve_mem(void)
+{
+	static struct cma_region regions[] = {
+		{
+			.name = "ion",
+			.size = 30 * SZ_1M,
+			.start = 0
+		},
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_GSC0
+		{
+			.name = "gsc0",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_GSC0 * SZ_1K,
+			.start = 0
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_GSC1
+		{
+			.name = "gsc1",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_GSC1 * SZ_1K,
+			.start = 0
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_GSC2
+		{
+			.name = "gsc2",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_GSC2 * SZ_1K,
+			.start = 0
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_GSC3
+		{
+			.name = "gsc3",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_GSC3 * SZ_1K,
+			.start = 0
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FLITE0
+		{
+			.name = "flite0",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FLITE0 * SZ_1K,
+			.start = 0
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FLITE1
+		{
+			.name = "flite1",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FLITE1 * SZ_1K,
+			.start = 0
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMD
+		{
+			.name = "fimd",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMD * SZ_1K,
+			.start = 0
+		},
+#endif
+#ifdef CONFIG_AUDIO_SAMSUNG_MEMSIZE_SRP
+		{
+			.name = "srp",
+			.size = CONFIG_AUDIO_SAMSUNG_MEMSIZE_SRP * SZ_1K,
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_S5P_MFC
+		{
+			.name		= "fw",
+			.size		= 2 << 20,
+			{ .alignment	= 128 << 10 },
+			.start		= 0x44000000,
+		},
+		{
+			.name		= "b1",
+			.size		= 64 << 20,
+			.start		= 0x45000000,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_TV
+		{
+			.name = "tv",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_TV * SZ_1K,
+			.start = 0
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_ROT
+		{
+			.name = "rot",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_ROT * SZ_1K,
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS5_FIMC_IS
+		{
+			.name = "fimc_is",
+			.size = CONFIG_VIDEO_EXYNOS_MEMSIZE_FIMC_IS * SZ_1K,
+			{
+                .alignment = 1 << 26,
+            },
+			.start = 0
+		},
+#endif
+		{
+			.size = 0
+		},
+	};
+	static const char map[] __initconst =
+#ifdef CONFIG_EXYNOS_C2C
+		"samsung-c2c=c2c_shdmem;"
+#endif
+		"s3cfb.0=fimd;exynos5-fb.1=fimd;"
+		"samsung-rp=srp;"
+		"exynos-gsc.0=gsc0;exynos-gsc.1=gsc1;exynos-gsc.2=gsc2;exynos-gsc.3=gsc3;"
+		"exynos-fimc-lite.0=flite0;exynos-fimc-lite.1=flite1;"
+		"ion-exynos=ion,gsc0,gsc1,gsc2,gsc3,flite0,flite1,fimd,fw,b1,rot;"
+		"exynos-rot=rot;"
+		"s5p-mfc-v6/f=fw;"
+		"s5p-mfc-v6/a=b1;"
+		"s5p-mixer=tv;"
+		"exynos5-fimc-is=fimc_is;"
+		"s5p-smem/mfc_sh=drm_mfc_sh;"
+		"s5p-smem/video=drm_video;"
+		"s5p-smem/mfc_fw=drm_mfc_fw;"
+		"s5p-smem/sectbl=drm_sectbl;";
+
+	s5p_cma_region_reserve(regions, NULL, 0, map);
+}
+#else /* !CONFIG_CMA*/
+static inline void exynos_reserve_mem(void)
+{
+}
+#endif
+
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_LITE
+static void __init smdk5250_camera_gpio_cfg(void)
+{
+	/* CAM A port(b0010) : PCLK, VSYNC, HREF, CLK_OUT */
+	s3c_gpio_cfgrange_nopull(EXYNOS5_GPH0(0), 4, S3C_GPIO_SFN(2));
+	/* CAM A port(b0010) : DATA[0-7] */
+	s3c_gpio_cfgrange_nopull(EXYNOS5_GPH1(0), 8, S3C_GPIO_SFN(2));
+	/* CAM B port(b0010) : PCLK, BAY_RGB[0-6] */
+	s3c_gpio_cfgrange_nopull(EXYNOS5_GPG0(0), 8, S3C_GPIO_SFN(2));
+	/* CAM B port(b0010) : BAY_Vsync, BAY_RGB[7-13] */
+	s3c_gpio_cfgrange_nopull(EXYNOS5_GPG1(0), 8, S3C_GPIO_SFN(2));
+	/* CAM B port(b0010) : BAY_Hsync, BAY_MCLK */
+	s3c_gpio_cfgrange_nopull(EXYNOS5_GPG2(0), 2, S3C_GPIO_SFN(2));
+	/* This is externel interrupt for m5mo */
+#ifdef CONFIG_VIDEO_M5MOLS
+	s3c_gpio_cfgpin(EXYNOS5_GPX2(6), S3C_GPIO_SFN(0xF));
+	s3c_gpio_setpull(EXYNOS5_GPX2(6), S3C_GPIO_PULL_NONE);
+#endif
+}
+#endif
+
+#if defined(CONFIG_VIDEO_EXYNOS_GSCALER) && defined(CONFIG_VIDEO_EXYNOS_FIMC_LITE)
+#if defined(CONFIG_VIDEO_S5K4BA)
+static struct exynos_isp_info s5k4ba = {
+	.board_info	= &s5k4ba_info,
+	.cam_srclk_name	= "xxti",
+	.clk_frequency  = 24000000UL,
+	.bus_type	= CAM_TYPE_ITU,
+#ifdef CONFIG_ITU_A
+	.cam_clk_name	= "sclk_cam0",
+	.i2c_bus_num	= 4,
+	.cam_port	= CAM_PORT_A, /* A-Port : 0, B-Port : 1 */
+#endif
+#ifdef CONFIG_ITU_B
+	.cam_clk_name	= "sclk_cam1",
+	.i2c_bus_num	= 5,
+	.cam_port	= CAM_PORT_B, /* A-Port : 0, B-Port : 1 */
+#endif
+	.flags		= CAM_CLK_INV_VSYNC,
+};
+/* This is for platdata of fimc-lite */
+static struct s3c_platform_camera flite_s5k4ba = {
+	.type		= CAM_TYPE_MIPI,
+	.use_isp	= true,
+	.inv_pclk	= 1,
+	.inv_vsync	= 1,
+	.inv_href	= 0,
+	.inv_hsync	= 0,
+};
+#endif
+#if defined(CONFIG_VIDEO_M5MOLS)
+static struct exynos_isp_info m5mols = {
+	.board_info	= &m5mols_board_info,
+	.cam_srclk_name	= "xxti",
+	.clk_frequency  = 24000000UL,
+	.bus_type	= CAM_TYPE_MIPI,
+#ifdef CONFIG_CSI_C
+	.cam_clk_name	= "sclk_cam0",
+	.i2c_bus_num	= 4,
+	.cam_port	= CAM_PORT_A, /* A-Port : 0, B-Port : 1 */
+#endif
+#ifdef CONFIG_CSI_D
+	.cam_clk_name	= "sclk_cam1",
+	.i2c_bus_num	= 5,
+	.cam_port	= CAM_PORT_B, /* A-Port : 0, B-Port : 1 */
+#endif
+	.flags		= CAM_CLK_INV_PCLK | CAM_CLK_INV_VSYNC,
+	.csi_data_align = 32,
+};
+/* This is for platdata of fimc-lite */
+static struct s3c_platform_camera flite_m5mo = {
+	.type		= CAM_TYPE_MIPI,
+	.use_isp	= true,
+	.inv_pclk	= 1,
+	.inv_vsync	= 1,
+	.inv_href	= 0,
+	.inv_hsync	= 0,
+};
+#endif
+
+static void __set_gsc_camera_config(struct exynos_platform_gscaler *data,
+					u32 active_index, u32 preview,
+					u32 camcording, u32 max_cam)
+{
+	data->active_cam_index = active_index;
+	data->cam_preview = preview;
+	data->cam_camcording = camcording;
+	data->num_clients = max_cam;
+}
+
+static void __set_flite_camera_config(struct exynos_platform_flite *data,
+					u32 active_index, u32 max_cam)
+{
+	data->active_cam_index = active_index;
+	data->num_clients = max_cam;
+}
+
+static void __init smdk5250_set_camera_platdata(void)
+{
+	int gsc_cam_index = 0;
+	int flite0_cam_index = 0;
+	int flite1_cam_index = 0;
+#if defined(CONFIG_VIDEO_M5MOLS)
+	exynos_gsc0_default_data.isp_info[gsc_cam_index++] = &m5mols;
+#if defined(CONFIG_CSI_C)
+	exynos_flite0_default_data.cam[flite0_cam_index] = &flite_m5mo;
+	exynos_flite0_default_data.isp_info[flite0_cam_index] = &m5mols;
+	flite0_cam_index++;
+#endif
+#if defined(CONFIG_CSI_D)
+	exynos_flite1_default_data.cam[flite1_cam_index] = &flite_m5mo;
+	exynos_flite1_default_data.isp_info[flite1_cam_index] = &m5mols;
+	flite1_cam_index++;
+#endif
+#endif
+	/* flite platdata register */
+	__set_flite_camera_config(&exynos_flite0_default_data, 0, flite0_cam_index);
+	__set_flite_camera_config(&exynos_flite1_default_data, 0, flite1_cam_index);
+
+	/* gscaler platdata register */
+	/* GSC-0 */
+	__set_gsc_camera_config(&exynos_gsc0_default_data, 0, 1, 0, gsc_cam_index);
+
+	/* GSC-1 */
+	/* GSC-2 */
+	/* GSC-3 */
+}
+#endif /* CONFIG_VIDEO_EXYNOS_GSCALER */
+
+static void __init smdk5250_smsc911x_init(void)
+{
+	u32 cs1;
+
+	/* configure nCS1 width to 16 bits */
+	cs1 = __raw_readl(S5P_SROM_BW) &
+		~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
+	cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
+		(1 << S5P_SROM_BW__WAITENABLE__SHIFT) |
+		(1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
+		S5P_SROM_BW__NCS1__SHIFT;
+	__raw_writel(cs1, S5P_SROM_BW);
+
+	/* set timing for nCS1 suitable for ethernet chip */
+	__raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
+		     (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
+		     (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
+		     (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
+		     (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
+		     (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
+		     (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
+}
+
+#if defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC)
+static struct s5p_mfc_platdata smdk5250_mfc_pd = {
+	.clock_rate = 333000000,
+};
+#endif
+
+static void __init smdk5250_map_io(void)
+{
+	clk_xxti.rate = 24000000;
+	s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+	s3c24xx_init_clocks(24000000);
+	s3c24xx_init_uarts(smdk5250_uartcfgs, ARRAY_SIZE(smdk5250_uartcfgs));
+	exynos_reserve_mem();
+}
+
+#ifdef CONFIG_EXYNOS_DEV_SYSMMU
+static void __init exynos_sysmmu_init(void)
+{
+#ifdef CONFIG_VIDEO_JPEG_V2X
+	platform_set_sysmmu(&SYSMMU_PLATDEV(jpeg).dev, &s5p_device_jpeg.dev);
+#endif
+#if defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC)
+	platform_set_sysmmu(&SYSMMU_PLATDEV(mfc_lr).dev, &s5p_device_mfc.dev);
+#endif
+#if defined(CONFIG_VIDEO_EXYNOS_TV)
+	platform_set_sysmmu(&SYSMMU_PLATDEV(tv).dev, &s5p_device_mixer.dev);
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS_GSCALER
+	platform_set_sysmmu(&SYSMMU_PLATDEV(gsc0).dev,
+						&exynos5_device_gsc0.dev);
+	platform_set_sysmmu(&SYSMMU_PLATDEV(gsc1).dev,
+						&exynos5_device_gsc1.dev);
+	platform_set_sysmmu(&SYSMMU_PLATDEV(gsc2).dev,
+						&exynos5_device_gsc2.dev);
+	platform_set_sysmmu(&SYSMMU_PLATDEV(gsc3).dev,
+						&exynos5_device_gsc3.dev);
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_LITE
+	platform_set_sysmmu(&SYSMMU_PLATDEV(camif0).dev,
+						&exynos_device_flite0.dev);
+	platform_set_sysmmu(&SYSMMU_PLATDEV(camif1).dev,
+						&exynos_device_flite1.dev);
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS_ROTATOR
+	platform_set_sysmmu(&SYSMMU_PLATDEV(rot).dev,
+						&exynos_device_rotator.dev);
+#endif
+#ifdef CONFIG_VIDEO_FIMG2D
+	platform_set_sysmmu(&SYSMMU_PLATDEV(2d).dev, &s5p_device_fimg2d.dev);
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS5_FIMC_IS
+	platform_set_sysmmu(&SYSMMU_PLATDEV(isp).dev,
+						&exynos5_device_fimc_is.dev);
+#endif
+}
+#else /* !CONFIG_EXYNOS_DEV_SYSMMU */
+static inline void exynos_sysmmu_init(void)
+{
+}
+#endif
+
+static void __init smdk5250_machine_init(void)
+{
+	exynos5_smdk5250_mmc_init();
+	exynos5_smdk5250_power_init();
+	exynos5_smdk5250_audio_init();
+	exynos5_smdk5250_usb_init();
+	exynos5_smdk5250_input_init();
+#if defined(CONFIG_S3C64XX_DEV_SPI)
+	exynos5_smdk5250_spi_init();
+#endif
+
+	s3c_i2c2_set_platdata(NULL);
+	i2c_register_board_info(2, i2c_devs2, ARRAY_SIZE(i2c_devs2));
+
+	s3c_i2c4_set_platdata(NULL);
+	s3c_i2c5_set_platdata(NULL);
+
+#ifdef CONFIG_ION_EXYNOS
+	exynos_ion_set_platdata();
+#endif
+
+	if (samsung_rev() >= EXYNOS5250_REV_1_0) {
+		platform_device_register(&s3c_device_adc);
+#ifdef CONFIG_S3C_DEV_HWMON
+		platform_device_register(&s3c_device_hwmon);
+#endif
+	}
+
+#ifdef CONFIG_S3C_DEV_HWMON
+	if (samsung_rev() >= EXYNOS5250_REV_1_0)
+		s3c_hwmon_set_platdata(&smdk5250_hwmon_pdata);
+#endif
+
+#ifdef CONFIG_SAMSUNG_DEV_BACKLIGHT
+	samsung_bl_set(&smdk5250_bl_gpio_info, &smdk5250_bl_data);
+#endif
+
+#ifdef CONFIG_FB_S3C
+	dev_set_name(&s5p_device_fimd1.dev, "s3cfb.1");
+	clk_add_alias("lcd", "exynos5-fb.1", "lcd", &s5p_device_fimd1.dev);
+	clk_add_alias("sclk_fimd", "exynos5-fb.1", "sclk_fimd",
+			&s5p_device_fimd1.dev);
+	s5p_fb_setname(1, "exynos5-fb");
+
+	s5p_fimd1_set_platdata(&smdk5250_lcd1_pdata);
+#endif
+#ifdef CONFIG_USB_EHCI_S5P
+	smdk5250_ehci_init();
+#endif
+#ifdef CONFIG_USB_OHCI_S5P
+	smdk5250_ohci_init();
+#endif
+#ifdef CONFIG_USB_S3C_OTGD
+	smdk5250_usbgadget_init();
+#endif
+#ifdef CONFIG_EXYNOS_DEV_SS_UDC
+	smdk5250_ss_udc_init();
+#endif
+#ifdef CONFIG_USB_XHCI_EXYNOS
+	smdk5250_xhci_init();
+#endif
+	smdk5250_usbswitch_init();
+#if defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC)
+#if defined(CONFIG_EXYNOS_DEV_PD)
+	s5p_device_mfc.dev.parent = &exynos5_device_pd[PD_MFC].dev;
+#endif
+	s5p_mfc_set_platdata(&smdk5250_mfc_pd);
+
+	dev_set_name(&s5p_device_mfc.dev, "s3c-mfc");
+	clk_add_alias("mfc", "s5p-mfc-v6", "mfc", &s5p_device_mfc.dev);
+	s5p_mfc_setname(&s5p_device_mfc, "s5p-mfc-v6");
+#endif
+
+#ifdef CONFIG_VIDEO_FIMG2D
+	s5p_fimg2d_set_platdata(&fimg2d_data);
+#endif
+	exynos_sysmmu_init();
+
+	platform_add_devices(smdk5250_devices, ARRAY_SIZE(smdk5250_devices));
+
+	exynos5_smdk5250_display_init();
+
+#ifdef CONFIG_VIDEO_EXYNOS_MIPI_CSIS
+#if defined(CONFIG_EXYNOS_DEV_PD)
+	s5p_device_mipi_csis0.dev.parent = &exynos5_device_pd[PD_GSCL].dev;
+	s5p_device_mipi_csis1.dev.parent = &exynos5_device_pd[PD_GSCL].dev;
+#endif
+	s3c_set_platdata(&s5p_mipi_csis0_default_data,
+			sizeof(s5p_mipi_csis0_default_data), &s5p_device_mipi_csis0);
+	s3c_set_platdata(&s5p_mipi_csis1_default_data,
+			sizeof(s5p_mipi_csis1_default_data), &s5p_device_mipi_csis1);
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_LITE
+#if defined(CONFIG_EXYNOS_DEV_PD)
+	exynos_device_flite0.dev.parent = &exynos5_device_pd[PD_GSCL].dev;
+	exynos_device_flite1.dev.parent = &exynos5_device_pd[PD_GSCL].dev;
+	exynos_device_flite2.dev.parent = &exynos5_device_pd[PD_GSCL].dev;
+#endif
+	smdk5250_camera_gpio_cfg();
+	smdk5250_set_camera_platdata();
+	s3c_set_platdata(&exynos_flite0_default_data,
+			sizeof(exynos_flite0_default_data), &exynos_device_flite0);
+	s3c_set_platdata(&exynos_flite1_default_data,
+			sizeof(exynos_flite1_default_data), &exynos_device_flite1);
+	s3c_set_platdata(&exynos_flite2_default_data,
+			sizeof(exynos_flite2_default_data), &exynos_device_flite2);
+/* In EVT0, for using camclk, gscaler clock should be enabled */
+	if (samsung_rev() < EXYNOS5250_REV_1_0) {
+		dev_set_name(&exynos_device_flite0.dev, "exynos-gsc.0");
+		clk_add_alias("gscl", "exynos-fimc-lite.0", "gscl",
+				&exynos_device_flite0.dev);
+		dev_set_name(&exynos_device_flite0.dev, "exynos-fimc-lite.0");
+
+		dev_set_name(&exynos_device_flite1.dev, "exynos-gsc.0");
+		clk_add_alias("gscl", "exynos-fimc-lite.1", "gscl",
+				&exynos_device_flite1.dev);
+		dev_set_name(&exynos_device_flite1.dev, "exynos-fimc-lite.1");
+	}
+#endif
+#if defined CONFIG_VIDEO_EXYNOS5_FIMC_IS
+	dev_set_name(&exynos5_device_fimc_is.dev, "s5p-mipi-csis.0");
+	clk_add_alias("gscl_wrap0", "exynos5-fimc-is", "gscl_wrap0", &exynos5_device_fimc_is.dev);
+	clk_add_alias("sclk_gscl_wrap0", "exynos5-fimc-is", "sclk_gscl_wrap0", &exynos5_device_fimc_is.dev);
+	dev_set_name(&exynos5_device_fimc_is.dev, "s5p-mipi-csis.1");
+	clk_add_alias("gscl_wrap1", "exynos5-fimc-is", "gscl_wrap1", &exynos5_device_fimc_is.dev);
+	clk_add_alias("sclk_gscl_wrap1", "exynos5-fimc-is", "sclk_gscl_wrap1", &exynos5_device_fimc_is.dev);
+	dev_set_name(&exynos5_device_fimc_is.dev, "exynos-gsc.0");
+	clk_add_alias("gscl", "exynos5-fimc-is", "gscl", &exynos5_device_fimc_is.dev);
+	dev_set_name(&exynos5_device_fimc_is.dev, "exynos5-fimc-is");
+
+#if defined CONFIG_VIDEO_S5K6A3
+	exynos5_fimc_is_data.sensor_info[s5k6a3.sensor_position] = &s5k6a3;
+	printk("add s5k6a3 sensor info(pos : %d)\n", s5k6a3.sensor_position);
+#endif
+#if defined CONFIG_VIDEO_S5K4E5
+	exynos5_fimc_is_data.sensor_info[s5k4e5.sensor_position] = &s5k4e5;
+	printk("add s5k4e5 sensor info(pos : %d)\n", s5k4e5.sensor_position);
+#endif
+
+	exynos5_fimc_is_set_platdata(&exynos5_fimc_is_data);
+#if defined(CONFIG_EXYNOS_DEV_PD)
+	exynos5_device_pd[PD_ISP].dev.parent = &exynos5_device_pd[PD_GSCL].dev;
+	exynos5_device_fimc_is.dev.parent = &exynos5_device_pd[PD_ISP].dev;
+#endif
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS_GSCALER
+#if defined(CONFIG_EXYNOS_DEV_PD)
+	exynos5_device_gsc0.dev.parent = &exynos5_device_pd[PD_GSCL].dev;
+	exynos5_device_gsc1.dev.parent = &exynos5_device_pd[PD_GSCL].dev;
+	exynos5_device_gsc2.dev.parent = &exynos5_device_pd[PD_GSCL].dev;
+	exynos5_device_gsc3.dev.parent = &exynos5_device_pd[PD_GSCL].dev;
+#endif
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+	secmem.parent = &exynos5_device_pd[PD_GSCL].dev;
+#endif
+	if (samsung_rev() >= EXYNOS5250_REV_1_0) {
+		exynos5_gsc_set_pdev_name(0, "exynos5250-gsc");
+		exynos5_gsc_set_pdev_name(1, "exynos5250-gsc");
+		exynos5_gsc_set_pdev_name(2, "exynos5250-gsc");
+		exynos5_gsc_set_pdev_name(3, "exynos5250-gsc");
+	}
+
+	s3c_set_platdata(&exynos_gsc0_default_data, sizeof(exynos_gsc0_default_data),
+			&exynos5_device_gsc0);
+	s3c_set_platdata(&exynos_gsc1_default_data, sizeof(exynos_gsc1_default_data),
+			&exynos5_device_gsc1);
+	s3c_set_platdata(&exynos_gsc2_default_data, sizeof(exynos_gsc2_default_data),
+			&exynos5_device_gsc2);
+	s3c_set_platdata(&exynos_gsc3_default_data, sizeof(exynos_gsc3_default_data),
+			&exynos5_device_gsc3);
+	exynos5_gsc_set_parent_clock("mout_aclk_300_gscl_mid", "mout_mpll_user");
+	exynos5_gsc_set_parent_clock("mout_aclk_300_gscl", "mout_aclk_300_gscl_mid");
+	exynos5_gsc_set_parent_clock("aclk_300_gscl", "dout_aclk_300_gscl");
+	exynos5_gsc_set_clock_rate("dout_aclk_300_gscl", 310000000);
+#endif
+#ifdef CONFIG_EXYNOS_C2C
+	exynos_c2c_set_platdata(&smdk5250_c2c_pdata);
+#endif
+#ifdef CONFIG_VIDEO_JPEG_V2X
+	exynos5_jpeg_setup_clock(&s5p_device_jpeg.dev, 150000000);
+#endif
+
+#if defined(CONFIG_VIDEO_EXYNOS_TV) && defined(CONFIG_VIDEO_EXYNOS_HDMI)
+	dev_set_name(&s5p_device_hdmi.dev, "exynos5-hdmi");
+	clk_add_alias("hdmi", "s5p-hdmi", "hdmi", &s5p_device_hdmi.dev);
+	clk_add_alias("hdmiphy", "s5p-hdmi", "hdmiphy", &s5p_device_hdmi.dev);
+
+	s5p_tv_setup();
+
+/* setup dependencies between TV devices */
+	/* This will be added after power domain for exynos5 is developed */
+	s5p_device_hdmi.dev.parent = &exynos5_device_pd[PD_DISP1].dev;
+	s5p_device_mixer.dev.parent = &exynos5_device_pd[PD_DISP1].dev;
+
+	s5p_i2c_hdmiphy_set_platdata(NULL);
+#ifdef CONFIG_VIDEO_EXYNOS_HDMI_CEC
+	s5p_hdmi_cec_set_platdata(&hdmi_cec_data);
+#endif
+#endif
+
+	smdk5250_smsc911x_init();
+#ifdef CONFIG_BUSFREQ_OPP
+	dev_add(&busfreq, &exynos5_busfreq.dev);
+	ppmu_init(&exynos_ppmu[PPMU_CPU], &exynos5_busfreq.dev);
+	ppmu_init(&exynos_ppmu[PPMU_DDR_C], &exynos5_busfreq.dev);
+	ppmu_init(&exynos_ppmu[PPMU_DDR_R1], &exynos5_busfreq.dev);
+	ppmu_init(&exynos_ppmu[PPMU_DDR_L], &exynos5_busfreq.dev);
+	ppmu_init(&exynos_ppmu[PPMU_RIGHT0_BUS], &exynos5_busfreq.dev
+#endif
+	register_reboot_notifier(&exynos5_reboot_notifier);
+}
+
+#ifdef CONFIG_EXYNOS_C2C
+static void __init exynos_c2c_reserve(void)
+{
+	static struct cma_region regions[] = {
+		{
+			.name = "c2c_shdmem",
+			.size = 64 * SZ_1M,
+			{ .alignment	= 64 * SZ_1M },
+			.start = C2C_SHAREDMEM_BASE
+		}, {
+			.size = 0,
+		}
+	};
+
+	s5p_cma_region_reserve(regions, NULL, 0, NULL);
+}
+#endif
+
+MACHINE_START(SMDK5250, "SMDK5250")
+	.boot_params	= S5P_PA_SDRAM + 0x100,
+	.init_irq	= exynos5_init_irq,
+	.map_io		= smdk5250_map_io,
+	.init_machine	= smdk5250_machine_init,
+	.timer		= &exynos4_timer,
+#ifdef CONFIG_EXYNOS_C2C
+	.reserve	= &exynos_c2c_reserve,
+#endif
+MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
new file mode 100644
index 0000000..3bb14d5
--- /dev/null
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -0,0 +1,2680 @@
+/* linux/arch/arm/mach-exynos/mach-smdkv310.c
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/serial_core.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/gpio_event.h>
+#include <linux/lcd.h>
+#include <linux/mmc/host.h>
+#include <linux/platform_device.h>
+#include <linux/smsc911x.h>
+#include <linux/io.h>
+#include <linux/i2c.h>
+#include <linux/pwm_backlight.h>
+#include <linux/input.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi_gpio.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/max8649.h>
+#include <linux/regulator/fixed.h>
+#include <linux/mfd/wm8994/pdata.h>
+#include <linux/mfd/max8997.h>
+#include <linux/v4l2-mediabus.h>
+#include <linux/memblock.h>
+#if defined(CONFIG_CMA)
+#include <linux/cma.h>
+#endif
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <video/platform_lcd.h>
+
+#include <plat/regs-serial.h>
+#include <plat/regs-srom.h>
+#include <plat/exynos4.h>
+#include <plat/clock.h>
+#include <plat/hwmon.h>
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/fb.h>
+#include <plat/fb-s5p.h>
+#ifdef CONFIG_VIDEO_FIMC
+#include <plat/fimc.h>
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_S5P_FIMC
+#include <media/s5p_fimc.h>
+#include <plat/fimc-core.h>
+#endif
+#ifdef CONFIG_VIDEO_FIMC_MIPI
+#include <plat/csis.h>
+#endif
+#ifdef CONFIG_VIDEO_S5P_MIPI_CSIS
+#include <plat/mipi_csis.h>
+#endif
+#if defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC) || defined(CONFIG_VIDEO_MFC5X)
+#include <plat/s5p-mfc.h>
+#endif
+#include <plat/gpio-cfg.h>
+#include <plat/adc.h>
+#include <plat/ts.h>
+#include <plat/keypad.h>
+#include <plat/sdhci.h>
+#include <plat/mshci.h>
+#include <plat/iic.h>
+#include <plat/sysmmu.h>
+#include <plat/pd.h>
+#include <plat/backlight.h>
+#include <plat/regs-fb-v4.h>
+#include <plat/media.h>
+#include <plat/s5p-clock.h>
+#include <plat/tvout.h>
+#include <plat/fimg2d.h>
+#include <plat/ehci.h>
+#include <plat/usbgadget.h>
+#ifdef CONFIG_S3C64XX_DEV_SPI
+#include <plat/s3c64xx-spi.h>
+#endif
+
+#include <mach/map.h>
+#include <mach/media.h>
+#include <mach/dev-sysmmu.h>
+#include <mach/regs-clock.h>
+#include <mach/exynos-ion.h>
+#ifdef CONFIG_S3C64XX_DEV_SPI
+#include <mach/spi-clocks.h>
+#endif
+#ifdef CONFIG_EXYNOS4_DEV_DWMCI
+#include <mach/dwmci.h>
+#endif
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+#include <mach/secmem.h>
+#endif
+#include <mach/dev.h>
+
+#include <media/s5k4ba_platform.h>
+#include <media/s5k4ea_platform.h>
+#include <media/m5mo_platform.h>
+#include <media/m5mols.h>
+
+#if defined(CONFIG_EXYNOS4_SETUP_THERMAL)
+#include <plat/s5p-tmu.h>
+#endif
+
+#if defined(CONFIG_FB_S5P_MIPI_DSIM)
+#include <mach/mipi_ddi.h>
+#include <mach/dsim.h>
+#include <../../../drivers/video/samsung/s3cfb.h>
+#endif
+
+/* Following are default values for UCON, ULCON and UFCON UART registers */
+#define SMDKV310_UCON_DEFAULT	(S3C2410_UCON_TXILEVEL |	\
+				 S3C2410_UCON_RXILEVEL |	\
+				 S3C2410_UCON_TXIRQMODE |	\
+				 S3C2410_UCON_RXIRQMODE |	\
+				 S3C2410_UCON_RXFIFO_TOI |	\
+				 S3C2443_UCON_RXERR_IRQEN)
+
+#define SMDKV310_ULCON_DEFAULT	S3C2410_LCON_CS8
+
+#define SMDKV310_UFCON_DEFAULT	(S3C2410_UFCON_FIFOMODE |	\
+				 S5PV210_UFCON_TXTRIG4 |	\
+				 S5PV210_UFCON_RXTRIG4)
+
+static struct s3c2410_uartcfg smdkv310_uartcfgs[] __initdata = {
+	[0] = {
+		.hwport		= 0,
+		.flags		= 0,
+		.ucon		= SMDKV310_UCON_DEFAULT,
+		.ulcon		= SMDKV310_ULCON_DEFAULT,
+		.ufcon		= SMDKV310_UFCON_DEFAULT,
+	},
+	[1] = {
+		.hwport		= 1,
+		.flags		= 0,
+		.ucon		= SMDKV310_UCON_DEFAULT,
+		.ulcon		= SMDKV310_ULCON_DEFAULT,
+		.ufcon		= SMDKV310_UFCON_DEFAULT,
+	},
+	[2] = {
+		.hwport		= 2,
+		.flags		= 0,
+		.ucon		= SMDKV310_UCON_DEFAULT,
+		.ulcon		= SMDKV310_ULCON_DEFAULT,
+		.ufcon		= SMDKV310_UFCON_DEFAULT,
+	},
+	[3] = {
+		.hwport		= 3,
+		.flags		= 0,
+		.ucon		= SMDKV310_UCON_DEFAULT,
+		.ulcon		= SMDKV310_ULCON_DEFAULT,
+		.ufcon		= SMDKV310_UFCON_DEFAULT,
+	},
+};
+
+#define WRITEBACK_ENABLED
+
+#if defined(CONFIG_VIDEO_FIMC) || defined(CONFIG_VIDEO_SAMSUNG_S5P_FIMC)
+/*
+ * External camera reset
+ * Because the most of cameras take i2c bus signal, so that
+ * you have to reset at the boot time for other i2c slave devices.
+ * This function also called at fimc_init_camera()
+ * Do optimization for cameras on your platform.
+*/
+#if defined(CONFIG_ITU_A) || defined(CONFIG_CSI_C)
+static int smdkv310_cam0_reset(int dummy)
+{
+	int err;
+	/* Camera A */
+	err = gpio_request(EXYNOS4_GPX1(2), "GPX1");
+	if (err)
+		printk(KERN_ERR "#### failed to request GPX1_2 ####\n");
+
+	s3c_gpio_setpull(EXYNOS4_GPX1(2), S3C_GPIO_PULL_NONE);
+	gpio_direction_output(EXYNOS4_GPX1(2), 0);
+	gpio_direction_output(EXYNOS4_GPX1(2), 1);
+	gpio_free(EXYNOS4_GPX1(2));
+
+	return 0;
+}
+#endif
+#if defined(CONFIG_ITU_B) || defined(CONFIG_CSI_D)
+static int smdkv310_cam1_reset(int dummy)
+{
+	int err;
+
+	/* Camera B */
+	err = gpio_request(EXYNOS4_GPX1(0), "GPX1");
+	if (err)
+		printk(KERN_ERR "#### failed to request GPX1_0 ####\n");
+
+	s3c_gpio_setpull(EXYNOS4_GPX1(0), S3C_GPIO_PULL_NONE);
+	gpio_direction_output(EXYNOS4_GPX1(0), 0);
+	gpio_direction_output(EXYNOS4_GPX1(0), 1);
+	gpio_free(EXYNOS4_GPX1(0));
+
+	return 0;
+}
+#endif
+/* for 12M camera */
+#ifdef CE143_MONACO
+static int smdkv310_cam0_standby(void)
+{
+	int err;
+	/* Camera A */
+	err = gpio_request(EXYNOS4_GPX3(3), "GPX3");
+	if (err)
+		printk(KERN_ERR "#### failed to request GPX3_3 ####\n");
+	s3c_gpio_setpull(EXYNOS4_GPX3(3), S3C_GPIO_PULL_NONE);
+	gpio_direction_output(EXYNOS4_GPX3(3), 0);
+	gpio_direction_output(EXYNOS4_GPX3(3), 1);
+	gpio_free(EXYNOS4_GPX3(3));
+
+	return 0;
+}
+
+static int smdkv310_cam1_standby(void)
+{
+	int err;
+
+	/* Camera B */
+	err = gpio_request(EXYNOS4_GPX1(1), "GPX1");
+	if (err)
+		printk(KERN_ERR "#### failed to request GPX1_1 ####\n");
+	s3c_gpio_setpull(EXYNOS4_GPX1(1), S3C_GPIO_PULL_NONE);
+	gpio_direction_output(EXYNOS4_GPX1(1), 0);
+	gpio_direction_output(EXYNOS4_GPX1(1), 1);
+	gpio_free(EXYNOS4_GPX1(1));
+
+	return 0;
+}
+#endif
+#endif
+
+#ifdef CONFIG_VIDEO_FIMC
+#ifdef CONFIG_VIDEO_S5K4BA
+static struct s5k4ba_platform_data s5k4ba_plat = {
+	.default_width = 800,
+	.default_height = 600,
+	.pixelformat = V4L2_PIX_FMT_YUYV,
+	.freq = 24000000,
+	.is_mipi = 0,
+};
+
+static struct i2c_board_info s5k4ba_i2c_info = {
+	I2C_BOARD_INFO("S5K4BA", 0x2d),
+	.platform_data = &s5k4ba_plat,
+};
+
+static struct s3c_platform_camera s5k4ba = {
+#ifdef CONFIG_ITU_A
+	.id		= CAMERA_PAR_A,
+	.clk_name	= "sclk_cam0",
+	.i2c_busnum	= 0,
+	.cam_power	= smdkv310_cam0_reset,
+#endif
+#ifdef CONFIG_ITU_B
+	.id		= CAMERA_PAR_B,
+	.clk_name	= "sclk_cam1",
+	.i2c_busnum	= 1,
+	.cam_power	= smdkv310_cam1_reset,
+#endif
+	.type		= CAM_TYPE_ITU,
+	.fmt		= ITU_601_YCBCR422_8BIT,
+	.order422	= CAM_ORDER422_8BIT_CBYCRY,
+	.info		= &s5k4ba_i2c_info,
+	.pixelformat	= V4L2_PIX_FMT_YUYV,
+	.srclk_name	= "xusbxti",
+	.clk_rate	= 24000000,
+	.line_length	= 1920,
+	.width		= 1600,
+	.height		= 1200,
+	.window		= {
+		.left	= 0,
+		.top	= 0,
+		.width	= 1600,
+		.height	= 1200,
+	},
+
+	/* Polarity */
+	.inv_pclk	= 0,
+	.inv_vsync	= 1,
+	.inv_href	= 0,
+	.inv_hsync	= 0,
+	.reset_camera	= 1,
+	.initialized	= 0,
+};
+#endif
+
+/* 2 MIPI Cameras */
+#ifdef CONFIG_VIDEO_S5K4EA
+static struct s5k4ea_platform_data s5k4ea_plat = {
+	.default_width = 1920,
+	.default_height = 1080,
+	.pixelformat = V4L2_PIX_FMT_UYVY,
+	.freq = 24000000,
+	.is_mipi = 1,
+};
+
+static struct i2c_board_info s5k4ea_i2c_info = {
+	I2C_BOARD_INFO("S5K4EA", 0x2d),
+	.platform_data = &s5k4ea_plat,
+};
+
+static struct s3c_platform_camera s5k4ea = {
+#ifdef CONFIG_CSI_C
+	.id		= CAMERA_CSI_C,
+	.clk_name	= "sclk_cam0",
+	.i2c_busnum	= 0,
+	.cam_power	= smdkv310_cam0_reset,
+#endif
+#ifdef CONFIG_CSI_D
+	.id		= CAMERA_CSI_D,
+	.clk_name	= "sclk_cam1",
+	.i2c_busnum	= 1,
+	.cam_power	= smdkv310_mipi_cam1_reset,
+#endif
+	.type		= CAM_TYPE_MIPI,
+	.fmt		= MIPI_CSI_YCBCR422_8BIT,
+	.order422	= CAM_ORDER422_8BIT_CBYCRY,
+	.info		= &s5k4ea_i2c_info,
+	.pixelformat	= V4L2_PIX_FMT_UYVY,
+	.srclk_name	= "mout_mpll",
+	.clk_rate	= 48000000,
+	.line_length	= 1920,
+	.width		= 1920,
+	.height		= 1080,
+	.window		= {
+		.left	= 0,
+		.top	= 0,
+		.width	= 1920,
+		.height	= 1080,
+	},
+
+	.mipi_lanes	= 2,
+	.mipi_settle	= 12,
+	.mipi_align	= 32,
+
+	/* Polarity */
+	.inv_pclk	= 0,
+	.inv_vsync	= 1,
+	.inv_href	= 0,
+	.inv_hsync	= 0,
+
+	.initialized	= 0,
+};
+#endif
+
+#ifdef WRITEBACK_ENABLED
+static struct i2c_board_info  __initdata writeback_i2c_info = {
+	I2C_BOARD_INFO("WriteBack", 0x0),
+};
+
+static struct s3c_platform_camera writeback = {
+	.id		= CAMERA_WB,
+	.fmt		= ITU_601_YCBCR422_8BIT,
+	.order422	= CAM_ORDER422_8BIT_CBYCRY,
+	.i2c_busnum	= 0,
+	.info		= &writeback_i2c_info,
+	.pixelformat	= V4L2_PIX_FMT_YUV444,
+	.line_length	= 800,
+	.width		= 480,
+	.height		= 800,
+	.window		= {
+		.left	= 0,
+		.top	= 0,
+		.width	= 480,
+		.height	= 800,
+	},
+
+	.initialized	= 0,
+};
+#endif
+
+/* legacy M5MOLS Camera driver configuration */
+#ifdef CONFIG_VIDEO_M5MO
+#define CAM_CHECK_ERR_RET(x, msg)	\
+	if (unlikely((x) < 0)) { \
+		printk(KERN_ERR "\nfail to %s: err = %d\n", msg, x); \
+		return x; \
+	}
+#define CAM_CHECK_ERR(x, msg)	\
+		if (unlikely((x) < 0)) { \
+			printk(KERN_ERR "\nfail to %s: err = %d\n", msg, x); \
+		}
+
+static int m5mo_config_isp_irq(void)
+{
+	s3c_gpio_cfgpin(EXYNOS4_GPX0(5), S3C_GPIO_SFN(0xF));
+	s3c_gpio_setpull(EXYNOS4_GPX0(5), S3C_GPIO_PULL_NONE);
+	return 0;
+}
+
+static struct m5mo_platform_data m5mo_plat = {
+	.default_width = 640, /* 1920 */
+	.default_height = 480, /* 1080 */
+	.pixelformat = V4L2_PIX_FMT_UYVY,
+	.freq = 24000000,
+	.is_mipi = 1,
+	.config_isp_irq = m5mo_config_isp_irq,
+	.irq = IRQ_EINT(5),
+};
+
+static struct i2c_board_info m5mo_i2c_info = {
+	I2C_BOARD_INFO("M5MO", 0x1F),
+	.platform_data = &m5mo_plat,
+	.irq = IRQ_EINT(5),
+};
+
+static struct s3c_platform_camera m5mo = {
+#ifdef CONFIG_CSI_C
+	.id		= CAMERA_CSI_C,
+	.clk_name	= "sclk_cam0",
+	.i2c_busnum	= 0,
+	.cam_power	= smdkv310_cam0_reset,
+#endif
+#ifdef CONFIG_CSI_D
+	.id		= CAMERA_CSI_D,
+	.clk_name	= "sclk_cam1",
+	.i2c_busnum	= 1,
+	.cam_power	= smdkv310_mipi_cam1_reset,
+#endif
+	.type		= CAM_TYPE_MIPI,
+	.fmt		= MIPI_CSI_YCBCR422_8BIT,
+	.order422	= CAM_ORDER422_8BIT_YCBYCR,
+	.info		= &m5mo_i2c_info,
+	.pixelformat	= V4L2_PIX_FMT_UYVY,
+	.srclk_name	= "xusbxti", /* "mout_mpll" */
+	.clk_rate	= 24000000, /* 48000000 */
+	.line_length	= 1920,
+	.width		= 640,
+	.height		= 480,
+	.window		= {
+		.left	= 0,
+		.top	= 0,
+		.width	= 640,
+		.height	= 480,
+	},
+
+	.mipi_lanes	= 2,
+	.mipi_settle	= 12,
+	.mipi_align	= 32,
+
+	/* Polarity */
+	.inv_pclk	= 1,
+	.inv_vsync	= 1,
+	.inv_href	= 0,
+	.inv_hsync	= 0,
+	.reset_camera	= 0,
+	.initialized	= 0,
+};
+#endif
+
+/* Interface setting */
+static struct s3c_platform_fimc fimc_plat = {
+#ifdef CONFIG_ITU_A
+	.default_cam	= CAMERA_PAR_A,
+#endif
+#ifdef CONFIG_ITU_B
+	.default_cam	= CAMERA_PAR_B,
+#endif
+#ifdef CONFIG_CSI_C
+	.default_cam	= CAMERA_CSI_C,
+#endif
+#ifdef CONFIG_CSI_D
+	.default_cam	= CAMERA_CSI_D,
+#endif
+#ifdef WRITEBACK_ENABLED
+	.default_cam	= CAMERA_WB,
+#endif
+	.camera		= {
+#ifdef CONFIG_VIDEO_S5K4BA
+		&s5k4ba,
+#endif
+#ifdef CONFIG_VIDEO_S5K4EA
+		&s5k4ea,
+#endif
+#ifdef CONFIG_VIDEO_M5MO
+		&m5mo,
+#endif
+#ifdef WRITEBACK_ENABLED
+		&writeback,
+#endif
+	},
+	.hw_ver		= 0x51,
+};
+#endif /* CONFIG_VIDEO_FIMC */
+
+/* for mainline fimc interface */
+#ifdef CONFIG_VIDEO_SAMSUNG_S5P_FIMC
+#ifdef WRITEBACK_ENABLED
+struct writeback_mbus_platform_data {
+	int id;
+	struct v4l2_mbus_framefmt fmt;
+};
+
+static struct i2c_board_info __initdata writeback_info = {
+	I2C_BOARD_INFO("writeback", 0x0),
+};
+#endif
+
+#ifdef CONFIG_VIDEO_S5K4BA
+static struct s5k4ba_mbus_platform_data s5k4ba_mbus_plat = {
+	.id		= 0,
+	.fmt = {
+		.width	= 1600,
+		.height	= 1200,
+		/*.code	= V4L2_MBUS_FMT_UYVY8_2X8,*/
+		.code	= V4L2_MBUS_FMT_VYUY8_2X8,
+	},
+	.clk_rate	= 24000000UL,
+#ifdef CONFIG_ITU_A
+	.set_power	= smdkv310_cam0_reset,
+#endif
+#ifdef CONFIG_ITU_B
+	.set_power	= smdkv310_cam1_reset,
+#endif
+};
+
+static struct i2c_board_info s5k4ba_info = {
+	I2C_BOARD_INFO("S5K4BA", 0x2d),
+	.platform_data = &s5k4ba_mbus_plat,
+};
+#endif
+
+/* 2 MIPI Cameras */
+#ifdef CONFIG_VIDEO_S5K4EA
+static struct s5k4ea_mbus_platform_data s5k4ea_mbus_plat = {
+#ifdef CONFIG_CSI_C
+	.id		= 0,
+	.set_power = smdkv310_cam0_reset,
+#endif
+#ifdef CONFIG_CSI_D
+	.id		= 1,
+	.set_power = smdkv310_cam1_reset,
+#endif
+	.fmt = {
+		.width	= 1920,
+		.height	= 1080,
+		.code	= V4L2_MBUS_FMT_VYUY8_2X8,
+	},
+	.clk_rate	= 24000000UL,
+};
+
+static struct i2c_board_info s5k4ea_info = {
+	I2C_BOARD_INFO("S5K4EA", 0x2d),
+	.platform_data = &s5k4ea_mbus_plat,
+};
+#endif
+
+#ifdef CONFIG_VIDEO_M5MOLS
+static struct m5mols_platform_data m5mols_platdata = {
+#ifdef CONFIG_CSI_C
+	.gpio_rst = EXYNOS4_GPX1(2), /* ISP_RESET */
+#endif
+#ifdef CONFIG_CSI_D
+	.gpio_rst = EXYNOS4_GPX1(0), /* ISP_RESET */
+#endif
+	.enable_rst = true, /* positive reset */
+	.irq = IRQ_EINT(5),
+};
+
+static struct i2c_board_info m5mols_board_info = {
+	I2C_BOARD_INFO("M5MOLS", 0x1F),
+	.platform_data = &m5mols_platdata,
+};
+
+#endif
+#endif /* CONFIG_VIDEO_SAMSUNG_S5P_FIMC */
+
+#ifdef CONFIG_EXYNOS4_DEV_DWMCI
+static void exynos_dwmci_cfg_gpio(int width)
+{
+	unsigned int gpio;
+
+	for (gpio = EXYNOS4_GPK0(0); gpio < EXYNOS4_GPK0(2); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV2);
+	}
+
+	switch (width) {
+	case MMC_BUS_WIDTH_8:
+		for (gpio = EXYNOS4_GPK1(3); gpio <= EXYNOS4_GPK1(6); gpio++) {
+			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
+			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+			s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV2);
+		}
+	case MMC_BUS_WIDTH_4:
+		for (gpio = EXYNOS4_GPK0(3); gpio <= EXYNOS4_GPK0(6); gpio++) {
+			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+			s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV2);
+		}
+		break;
+	case MMC_BUS_WIDTH_1:
+		gpio = EXYNOS4_GPK0(3);
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV2);
+	default:
+		break;
+	}
+}
+
+static struct dw_mci_board exynos_dwmci_pdata __initdata = {
+	.num_slots		= 1,
+	.quirks			= DW_MCI_QUIRK_BROKEN_CARD_DETECTION | DW_MCI_QUIRK_HIGHSPEED,
+	.bus_hz			= 80 * 1000 * 1000,
+	.caps			= MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR |
+				  MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
+	.fifo_depth		= 0x20,
+	.detect_delay_ms	= 200,
+	.hclk_name		= "dwmci",
+	.cclk_name		= "sclk_dwmci",
+	.cfg_gpio		= exynos_dwmci_cfg_gpio,
+};
+#endif
+
+#ifdef CONFIG_S3C_DEV_HSMMC
+static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = {
+	.cd_type		= S3C_SDHCI_CD_INTERNAL,
+	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
+#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
+	.max_width		= 8,
+	.host_caps		= MMC_CAP_8_BIT_DATA,
+#endif
+};
+#endif
+
+#ifdef CONFIG_S3C_DEV_HSMMC1
+static struct s3c_sdhci_platdata smdkv310_hsmmc1_pdata __initdata = {
+	.cd_type		= S3C_SDHCI_CD_INTERNAL,
+	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+#endif
+
+#ifdef CONFIG_S3C_DEV_HSMMC2
+static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = {
+	.cd_type		= S3C_SDHCI_CD_INTERNAL,
+	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
+#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
+	.max_width		= 8,
+	.host_caps		= MMC_CAP_8_BIT_DATA,
+#endif
+};
+#endif
+
+#ifdef CONFIG_S3C_DEV_HSMMC3
+static struct s3c_sdhci_platdata smdkv310_hsmmc3_pdata __initdata = {
+	.cd_type		= S3C_SDHCI_CD_INTERNAL,
+	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+#endif
+
+#ifdef CONFIG_S5P_DEV_MSHC
+static struct s3c_mshci_platdata exynos4_mshc_pdata __initdata = {
+	.cd_type		= S3C_MSHCI_CD_PERMANENT,
+	.has_wp_gpio		= true,
+	.wp_gpio		= 0xffffffff,
+#if defined(CONFIG_EXYNOS4_MSHC_8BIT) && \
+	defined(CONFIG_EXYNOS4_MSHC_DDR)
+	.max_width		= 8,
+	.host_caps		= MMC_CAP_8_BIT_DATA | MMC_CAP_1_8V_DDR |
+				  MMC_CAP_UHS_DDR50,
+#elif defined(CONFIG_EXYNOS4_MSHC_8BIT)
+	.max_width		= 8,
+	.host_caps		= MMC_CAP_8_BIT_DATA,
+#elif defined(CONFIG_EXYNOS4_MSHC_DDR)
+	.host_caps		= MMC_CAP_1_8V_DDR | MMC_CAP_UHS_DDR50,
+#endif
+};
+#endif
+
+#ifdef CONFIG_VIDEO_FIMG2D
+static struct fimg2d_platdata fimg2d_data __initdata = {
+	.hw_ver = 30,
+	.parent_clkname = "mout_g2d0",
+	.clkname = "sclk_fimg2d",
+	.gate_clkname = "fimg2d",
+	.clkrate = 267 * 1000000,	/* 266 Mhz */
+};
+#endif
+
+#ifdef CONFIG_FB_S3C
+#if defined(CONFIG_LCD_AMS369FG06)
+static int lcd_power_on(struct lcd_device *ld, int enable)
+{
+	return 1;
+}
+
+static int reset_lcd(struct lcd_device *ld)
+{
+	int err = 0;
+
+	err = gpio_request_one(EXYNOS4_GPX0(6), GPIOF_OUT_INIT_HIGH, "GPX0");
+	if (err) {
+		printk(KERN_ERR "failed to request GPX0 for "
+				"lcd reset control\n");
+		return err;
+	}
+	gpio_set_value(EXYNOS4_GPX0(6), 0);
+	mdelay(1);
+
+	gpio_set_value(EXYNOS4_GPX0(6), 1);
+
+	gpio_free(EXYNOS4_GPX0(6));
+
+	return 1;
+}
+
+static struct lcd_platform_data ams369fg06_platform_data = {
+	.reset			= reset_lcd,
+	.power_on		= lcd_power_on,
+	.lcd_enabled		= 0,
+	.reset_delay		= 100,	/* 100ms */
+};
+
+#define		LCD_BUS_NUM	3
+#define		DISPLAY_CS	EXYNOS4_GPB(5)
+#define		DISPLAY_CLK	EXYNOS4_GPB(4)
+#define		DISPLAY_SI	EXYNOS4_GPB(7)
+
+static struct spi_board_info spi_board_info[] __initdata = {
+	{
+		.modalias		= "ams369fg06",
+		.platform_data		= (void *)&ams369fg06_platform_data,
+		.max_speed_hz		= 1200000,
+		.bus_num		= LCD_BUS_NUM,
+		.chip_select		= 0,
+		.mode			= SPI_MODE_3,
+		.controller_data	= (void *)DISPLAY_CS,
+	}
+};
+
+static struct spi_gpio_platform_data ams369fg06_spi_gpio_data = {
+	.sck	= DISPLAY_CLK,
+	.mosi	= DISPLAY_SI,
+	.miso	= -1,
+	.num_chipselect = 1,
+};
+
+static struct platform_device s3c_device_spi_gpio = {
+	.name	= "spi_gpio",
+	.id	= LCD_BUS_NUM,
+	.dev	= {
+		.parent		= &s5p_device_fimd0.dev,
+		.platform_data	= &ams369fg06_spi_gpio_data,
+	},
+};
+
+static struct s3c_fb_pd_win smdkv310_fb_win0 = {
+	.win_mode = {
+		.left_margin	= 9,
+		.right_margin	= 9,
+		.upper_margin	= 5,
+		.lower_margin	= 5,
+		.hsync_len	= 2,
+		.vsync_len	= 2,
+		.xres		= 480,
+		.yres		= 800,
+	},
+	.virtual_x		= 480,
+	.virtual_y		= 1600,
+	.width			= 48,
+	.height			= 80,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+};
+
+static struct s3c_fb_pd_win smdkv310_fb_win1 = {
+	.win_mode = {
+		.left_margin	= 9,
+		.right_margin	= 9,
+		.upper_margin	= 5,
+		.lower_margin	= 5,
+		.hsync_len	= 2,
+		.vsync_len	= 2,
+		.xres		= 480,
+		.yres		= 800,
+	},
+	.virtual_x		= 480,
+	.virtual_y		= 1600,
+	.width			= 48,
+	.height			= 80,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+};
+
+static struct s3c_fb_pd_win smdkv310_fb_win2 = {
+	.win_mode = {
+		.left_margin	= 9,
+		.right_margin	= 9,
+		.upper_margin	= 5,
+		.lower_margin	= 5,
+		.hsync_len	= 2,
+		.vsync_len	= 2,
+		.xres		= 480,
+		.yres		= 800,
+	},
+	.virtual_x		= 480,
+	.virtual_y		= 1600,
+	.width			= 48,
+	.height			= 80,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+};
+
+#elif defined(CONFIG_LCD_WA101S)
+static void lcd_wa101s_set_power(struct plat_lcd_data *pd,
+				   unsigned int power)
+{
+	if (power) {
+#if !defined(CONFIG_BACKLIGHT_PWM)
+		gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_HIGH, "GPD0");
+		gpio_free(EXYNOS4_GPD0(1));
+#endif
+	} else {
+#if !defined(CONFIG_BACKLIGHT_PWM)
+		gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_LOW, "GPD0");
+		gpio_free(EXYNOS4_GPD0(1));
+#endif
+	}
+}
+
+static struct plat_lcd_data smdkv310_lcd_wa101s_data = {
+	.set_power		= lcd_wa101s_set_power,
+};
+
+static struct platform_device smdkv310_lcd_wa101s = {
+	.name			= "platform-lcd",
+	.dev.parent		= &s5p_device_fimd0.dev,
+	.dev.platform_data      = &smdkv310_lcd_wa101s_data,
+};
+
+static struct s3c_fb_pd_win smdkv310_fb_win0 = {
+	.win_mode = {
+		.left_margin	= 80,
+		.right_margin	= 48,
+		.upper_margin	= 14,
+		.lower_margin	= 3,
+		.hsync_len	= 32,
+		.vsync_len	= 5,
+		.xres		= 1360, /* real size : 1366 */
+		.yres		= 768,
+	},
+	.virtual_x		= 1360, /* real size : 1366 */
+	.virtual_y		= 768 * 2,
+	.width			= 223,
+	.height			= 125,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+};
+
+static struct s3c_fb_pd_win smdkv310_fb_win1 = {
+	.win_mode = {
+		.left_margin	= 80,
+		.right_margin	= 48,
+		.upper_margin	= 14,
+		.lower_margin	= 3,
+		.hsync_len	= 32,
+		.vsync_len	= 5,
+		.xres		= 1360, /* real size : 1366 */
+		.yres		= 768,
+	},
+	.virtual_x		= 1360, /* real size : 1366 */
+	.virtual_y		= 768 * 2,
+	.width			= 223,
+	.height			= 125,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+};
+
+static struct s3c_fb_pd_win smdkv310_fb_win2 = {
+	.win_mode = {
+		.left_margin	= 80,
+		.right_margin	= 48,
+		.upper_margin	= 14,
+		.lower_margin	= 3,
+		.hsync_len	= 32,
+		.vsync_len	= 5,
+		.xres		= 1360, /* real size : 1366 */
+		.yres		= 768,
+	},
+	.virtual_x		= 1360, /* real size : 1366 */
+	.virtual_y		= 768 * 2,
+	.width			= 223,
+	.height			= 125,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+};
+
+#elif defined(CONFIG_LCD_LTE480WV)
+static void lcd_lte480wv_set_power(struct plat_lcd_data *pd,
+				   unsigned int power)
+{
+	if (power) {
+#if !defined(CONFIG_BACKLIGHT_PWM)
+		gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_HIGH, "GPD0");
+		gpio_free(EXYNOS4_GPD0(1));
+#endif
+		/* fire nRESET on power up */
+		gpio_request_one(EXYNOS4_GPX0(6), GPIOF_OUT_INIT_HIGH, "GPX0");
+		mdelay(100);
+
+		gpio_set_value(EXYNOS4_GPX0(6), 0);
+		mdelay(10);
+
+		gpio_set_value(EXYNOS4_GPX0(6), 1);
+		mdelay(10);
+
+		gpio_free(EXYNOS4_GPX0(6));
+	} else {
+#if !defined(CONFIG_BACKLIGHT_PWM)
+		gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_LOW, "GPD0");
+		gpio_free(EXYNOS4_GPD0(1));
+#endif
+	}
+}
+
+static struct plat_lcd_data smdkv310_lcd_lte480wv_data = {
+	.set_power		= lcd_lte480wv_set_power,
+};
+
+static struct platform_device smdkv310_lcd_lte480wv = {
+	.name			= "platform-lcd",
+	.dev.parent		= &s5p_device_fimd0.dev,
+	.dev.platform_data      = &smdkv310_lcd_lte480wv_data,
+};
+
+static struct s3c_fb_pd_win smdkv310_fb_win0 = {
+	.win_mode = {
+		.left_margin	= 13,
+		.right_margin	= 8,
+		.upper_margin	= 7,
+		.lower_margin	= 5,
+		.hsync_len	= 3,
+		.vsync_len	= 1,
+		.xres		= 800,
+		.yres		= 480,
+	},
+	.virtual_x		= 800,
+	.virtual_y		= 960,
+	.width			= 104,
+	.height			= 62,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+};
+
+static struct s3c_fb_pd_win smdkv310_fb_win1 = {
+	.win_mode = {
+		.left_margin	= 13,
+		.right_margin	= 8,
+		.upper_margin	= 7,
+		.lower_margin	= 5,
+		.hsync_len	= 3,
+		.vsync_len	= 1,
+		.xres		= 800,
+		.yres		= 480,
+	},
+	.virtual_x		= 800,
+	.virtual_y		= 960,
+	.width			= 104,
+	.height			= 62,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+};
+
+static struct s3c_fb_pd_win smdkv310_fb_win2 = {
+	.win_mode = {
+		.left_margin	= 13,
+		.right_margin	= 8,
+		.upper_margin	= 7,
+		.lower_margin	= 5,
+		.hsync_len	= 3,
+		.vsync_len	= 1,
+		.xres		= 800,
+		.yres		= 480,
+	},
+	.virtual_x		= 800,
+	.virtual_y		= 960,
+	.width			= 104,
+	.height			= 62,
+	.max_bpp		= 32,
+	.default_bpp		= 24,
+};
+#endif
+
+static struct s3c_fb_platdata smdkv310_lcd0_pdata __initdata = {
+#if defined(CONFIG_LCD_AMS369FG06) || defined(CONFIG_LCD_WA101S) || \
+	defined(CONFIG_LCD_LTE480WV)
+	.win[0]		= &smdkv310_fb_win0,
+	.win[1]		= &smdkv310_fb_win1,
+	.win[2]		= &smdkv310_fb_win2,
+#endif
+	.default_win	= 2,
+	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+#if defined(CONFIG_LCD_AMS369FG06)
+	.vidcon1	= VIDCON1_INV_VCLK | VIDCON1_INV_VDEN |
+			  VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+#elif defined(CONFIG_LCD_WA101S)
+	.vidcon1	= VIDCON1_INV_VCLK | VIDCON1_INV_HSYNC |
+			  VIDCON1_INV_VSYNC,
+#elif defined(CONFIG_LCD_LTE480WV)
+	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+#endif
+	.setup_gpio	= exynos4_fimd0_gpio_setup_24bpp,
+};
+#endif
+
+#ifdef CONFIG_S3C64XX_DEV_SPI
+static struct s3c64xx_spi_csinfo spi0_csi[] = {
+	[0] = {
+		.line       = EXYNOS4_GPB(1),
+		.set_level  = gpio_set_value,
+		.fb_delay   = 0x0,
+	},
+};
+
+static struct spi_board_info spi0_board_info[] __initdata = {
+	{
+		.modalias   = "spidev",
+		.platform_data  = NULL,
+		.max_speed_hz   = 10*1000*1000,
+		.bus_num    = 0,
+		.chip_select    = 0,
+		.mode       = SPI_MODE_0,
+		.controller_data = &spi0_csi[0],
+	}
+};
+
+static struct s3c64xx_spi_csinfo spi2_csi[] = {
+	[0] = {
+		.line       = EXYNOS4_GPC1(2),
+		.set_level  = gpio_set_value,
+		.fb_delay   = 0x1,
+	},
+};
+
+static struct spi_board_info spi2_board_info[] __initdata = {
+	{
+		.modalias   = "spidev",
+		.platform_data  = NULL,
+		.max_speed_hz   = 10*1000*1000,
+		.bus_num    = 2,
+		.chip_select    = 0,
+		.mode       = SPI_MODE_0,
+		.controller_data = &spi2_csi[0],
+	}
+};
+#endif
+
+#ifdef CONFIG_FB_S5P
+#ifdef CONFIG_FB_S5P_AMS369FG06
+static struct s3c_platform_fb ams369fg06_data __initdata = {
+	.hw_ver = 0x70,
+	.clk_name = "sclk_lcd",
+	.nr_wins = 5,
+	.default_win = CONFIG_FB_S5P_DEFAULT_WINDOW,
+	.swap = FB_SWAP_HWORD | FB_SWAP_WORD,
+};
+
+#define		LCD_BUS_NUM	3
+#define		DISPLAY_CS	EXYNOS4_GPB(5)
+#define		DISPLAY_CLK	EXYNOS4_GPB(4)
+#define		DISPLAY_SI	EXYNOS4_GPB(7)
+
+static struct spi_board_info spi_board_info[] __initdata = {
+	{
+		.modalias	= "ams369fg06",
+		.platform_data	= NULL,
+		.max_speed_hz	= 1200000,
+		.bus_num	= LCD_BUS_NUM,
+		.chip_select	= 0,
+		.mode		= SPI_MODE_3,
+		.controller_data = (void *)DISPLAY_CS,
+	}
+};
+static struct spi_gpio_platform_data ams369fg06_spi_gpio_data = {
+	.sck	= DISPLAY_CLK,
+	.mosi	= DISPLAY_SI,
+	.miso	= -1,
+	.num_chipselect = 1,
+};
+
+static struct platform_device s3c_device_spi_gpio = {
+	.name	= "spi_gpio",
+	.id	= LCD_BUS_NUM,
+	.dev	= {
+		.parent		= &s3c_device_fb.dev,
+		.platform_data	= &ams369fg06_spi_gpio_data,
+	},
+};
+#elif defined(CONFIG_FB_S5P_DUMMY_MIPI_LCD)
+#define		LCD_BUS_NUM	3
+#define		DISPLAY_CS	EXYNOS4_GPB(5)
+#define		DISPLAY_CLK	EXYNOS4_GPB(4)
+#define		DISPLAY_SI	EXYNOS4_GPB(7)
+
+static struct s3cfb_lcd dummy_mipi_lcd = {
+	.width = 480,
+	.height = 800,
+	.bpp = 24,
+
+	.freq = 60,
+
+	.timing = {
+		.h_fp = 0x16,
+		.h_bp = 0x16,
+		.h_sw = 0x2,
+		.v_fp = 0x28,
+		.v_fpe = 2,
+		.v_bp = 0x1,
+		.v_bpe = 1,
+		.v_sw = 3,
+		.cmd_allow_len = 4,
+	},
+
+	.polarity = {
+		.rise_vclk = 0,
+		.inv_hsync = 0,
+		.inv_vsync = 0,
+		.inv_vden = 0,
+	},
+};
+
+static struct s3c_platform_fb fb_platform_data __initdata = {
+	.hw_ver		= 0x70,
+	.clk_name	= "fimd",
+	.nr_wins	= 5,
+#if defined(CONFIG_FB_S5P_DEFAULT_WINDOW)
+	.default_win	= CONFIG_FB_S5P_DEFAULT_WINDOW,
+#else
+	.default_win	= 0,
+#endif
+	.swap		= FB_SWAP_HWORD | FB_SWAP_WORD,
+};
+
+static void lcd_cfg_gpio(void)
+{
+	return;
+}
+
+static int reset_lcd(void)
+{
+	int err = 0;
+	/* fire nRESET on power off */
+	err = gpio_request_one(EXYNOS4_GPX3(1), GPIOF_OUT_INIT_HIGH, "GPX3");
+	if (err) {
+		printk(KERN_ERR "failed to request GPX0 for "
+				"lcd reset control\n");
+		return err;
+	}
+	mdelay(100);
+
+	gpio_set_value(EXYNOS4_GPX3(1), 0);
+	mdelay(100);
+	gpio_set_value(EXYNOS4_GPX3(1), 1);
+	mdelay(100);
+	gpio_free(EXYNOS4_GPX3(1));
+
+	return 0;
+}
+
+static int lcd_power_on(void *pdev, int enable)
+{
+	return 1;
+}
+
+static void __init mipi_fb_init(void)
+{
+	struct s5p_platform_dsim *dsim_pd = NULL;
+	struct mipi_ddi_platform_data *mipi_ddi_pd = NULL;
+	struct dsim_lcd_config *dsim_lcd_info = NULL;
+
+	/* gpio pad configuration for rgb and spi interface. */
+	lcd_cfg_gpio();
+
+	/* register lcd panel data. */
+	dsim_pd = (struct s5p_platform_dsim *)
+		s5p_device_dsim.dev.platform_data;
+
+	strcpy(dsim_pd->lcd_panel_name, "dummy_mipi_lcd");
+
+	dsim_lcd_info = dsim_pd->dsim_lcd_info;
+	dsim_lcd_info->lcd_panel_info = (void *)&dummy_mipi_lcd;
+
+	mipi_ddi_pd = (struct mipi_ddi_platform_data *)
+		dsim_lcd_info->mipi_ddi_pd;
+	mipi_ddi_pd->lcd_reset = reset_lcd;
+	mipi_ddi_pd->lcd_power_on = lcd_power_on;
+
+	platform_device_register(&s5p_device_dsim);
+
+	s3cfb_set_platdata(&fb_platform_data);
+
+	printk(KERN_INFO "platform data of %s lcd panel has been registered.\n",
+			dsim_pd->lcd_panel_name);
+}
+#endif
+#endif
+
+static struct resource smdkv310_smsc911x_resources[] = {
+	[0] = {
+		.start	= EXYNOS4_PA_SROM_BANK(1),
+		.end	= EXYNOS4_PA_SROM_BANK(1) + SZ_64K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= IRQ_EINT(5),
+		.end	= IRQ_EINT(5),
+		.flags	= IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
+	},
+};
+
+static struct smsc911x_platform_config smsc9215_config = {
+	.irq_polarity	= SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+	.irq_type	= SMSC911X_IRQ_TYPE_PUSH_PULL,
+	.flags		= SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
+	.phy_interface	= PHY_INTERFACE_MODE_MII,
+	.mac		= {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
+};
+
+static struct platform_device smdkv310_smsc911x = {
+	.name		= "smsc911x",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(smdkv310_smsc911x_resources),
+	.resource	= smdkv310_smsc911x_resources,
+	.dev		= {
+		.platform_data	= &smsc9215_config,
+	},
+};
+
+/* max8649 */
+static struct regulator_consumer_supply max8952_supply =
+	REGULATOR_SUPPLY("vdd_arm", NULL);
+
+static struct regulator_consumer_supply max8649_supply =
+	REGULATOR_SUPPLY("vdd_int", NULL);
+
+static struct regulator_consumer_supply max8649a_supply =
+	REGULATOR_SUPPLY("vdd_g3d", NULL);
+
+static struct regulator_init_data max8952_init_data = {
+	.constraints	= {
+		.name		= "vdd_arm range",
+		.min_uV		= 770000,
+		.max_uV		= 1400000,
+		.always_on	= 1,
+		.boot_on	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE,
+		.state_mem	= {
+			.uV		= 1200000,
+			.disabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &max8952_supply,
+};
+
+static struct regulator_init_data max8649_init_data = {
+	.constraints	= {
+		.name		= "vdd_int range",
+		.min_uV		= 750000,
+		.max_uV		= 1380000,
+		.always_on	= 1,
+		.boot_on	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE,
+		.state_mem	= {
+			.uV		= 1100000,
+			.disabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &max8649_supply,
+};
+
+static struct regulator_init_data max8649a_init_data = {
+	.constraints	= {
+		.name		= "vdd_g3d range",
+		.min_uV		= 750000,
+		.max_uV		= 1380000,
+		.always_on	= 0,
+		.boot_on	= 0,
+		.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE |
+				  REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.uV		= 1200000,
+			.disabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &max8649a_supply,
+};
+
+static struct max8649_platform_data exynos4_max8952_info = {
+	.mode		= 3,	/* VID1 = 1, VID0 = 1 */
+	.extclk		= 0,
+	.ramp_timing	= MAX8649_RAMP_32MV,
+	.regulator	= &max8952_init_data,
+};
+
+static struct max8649_platform_data exynos4_max8649_info = {
+	.mode		= 2,	/* VID1 = 1, VID0 = 0 */
+	.extclk		= 0,
+	.ramp_timing	= MAX8649_RAMP_32MV,
+	.regulator	= &max8649_init_data,
+};
+
+static struct max8649_platform_data exynos4_max8649a_info = {
+	.mode		= 2,	/* VID1 = 1, VID0 = 0 */
+	.extclk		= 0,
+	.ramp_timing	= MAX8649_RAMP_32MV,
+	.regulator	= &max8649a_init_data,
+};
+
+/* max8997 */
+static struct regulator_consumer_supply max8997_buck1 =
+	REGULATOR_SUPPLY("vdd_arm", NULL);
+
+static struct regulator_consumer_supply max8997_buck2 =
+	REGULATOR_SUPPLY("vdd_int", NULL);
+
+static struct regulator_consumer_supply max8997_buck3 =
+	REGULATOR_SUPPLY("vdd_g3d", NULL);
+
+static struct regulator_init_data max8997_buck1_data = {
+	.constraints	= {
+		.name		= "vdd_arm range",
+		.min_uV		= 925000,
+		.max_uV		= 1350000,
+		.always_on	= 1,
+		.boot_on	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE,
+		.state_mem	= {
+			.disabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &max8997_buck1,
+};
+
+static struct regulator_init_data max8997_buck2_data = {
+	.constraints	= {
+		.name		= "vdd_int range",
+		.min_uV		= 950000,
+		.max_uV		= 1150000,
+		.always_on	= 1,
+		.boot_on	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE,
+		.state_mem	= {
+			.disabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &max8997_buck2,
+};
+
+static struct regulator_init_data max8997_buck3_data = {
+	.constraints	= {
+		.name		= "vdd_g3d range",
+		.min_uV		= 950000,
+		.max_uV		= 1150000,
+		.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE |
+				  REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.disabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &max8997_buck3,
+};
+
+static struct max8997_regulator_data max8997_regulators[] = {
+	{ MAX8997_BUCK1, &max8997_buck1_data, },
+	{ MAX8997_BUCK2, &max8997_buck2_data, },
+	{ MAX8997_BUCK3, &max8997_buck3_data, },
+};
+
+static struct max8997_platform_data exynos4_max8997_info = {
+	.num_regulators = ARRAY_SIZE(max8997_regulators),
+	.regulators     = max8997_regulators,
+
+	.buck1_voltage[0] = 1350000, /* 1.35V */
+	.buck1_voltage[1] = 1300000, /* 1.3V */
+	.buck1_voltage[2] = 1250000, /* 1.25V */
+	.buck1_voltage[3] = 1200000, /* 1.2V */
+	.buck1_voltage[4] = 1150000, /* 1.15V */
+	.buck1_voltage[5] = 1100000, /* 1.1V */
+	.buck1_voltage[6] = 1000000, /* 1.0V */
+	.buck1_voltage[7] = 950000, /* 0.95V */
+
+	.buck2_voltage[0] = 1100000, /* 1.1V */
+	.buck2_voltage[1] = 1000000, /* 1.0V */
+	.buck2_voltage[2] = 950000, /* 0.95V */
+	.buck2_voltage[3] = 900000, /* 0.9V */
+	.buck2_voltage[4] = 1100000, /* 1.1V */
+	.buck2_voltage[5] = 1000000, /* 1.0V */
+	.buck2_voltage[6] = 950000, /* 0.95V */
+	.buck2_voltage[7] = 900000, /* 0.9V */
+
+	.buck5_voltage[0] = 1100000, /* 1.1V */
+	.buck5_voltage[1] = 1100000, /* 1.1V */
+	.buck5_voltage[2] = 1100000, /* 1.1V */
+	.buck5_voltage[3] = 1100000, /* 1.1V */
+	.buck5_voltage[4] = 1100000, /* 1.1V */
+	.buck5_voltage[5] = 1100000, /* 1.1V */
+	.buck5_voltage[6] = 1100000, /* 1.1V */
+	.buck5_voltage[7] = 1100000, /* 1.1V */
+};
+
+#ifdef CONFIG_VIDEO_S5P_MIPI_CSIS
+static struct regulator_consumer_supply mipi_csi_fixed_voltage_supplies[] = {
+	REGULATOR_SUPPLY("mipi_csi", "s5p-mipi-csis.0"),
+	REGULATOR_SUPPLY("mipi_csi", "s5p-mipi-csis.1"),
+};
+
+static struct regulator_init_data mipi_csi_fixed_voltage_init_data = {
+	.constraints = {
+		.always_on = 1,
+	},
+	.num_consumer_supplies	= ARRAY_SIZE(mipi_csi_fixed_voltage_supplies),
+	.consumer_supplies	= mipi_csi_fixed_voltage_supplies,
+};
+
+static struct fixed_voltage_config mipi_csi_fixed_voltage_config = {
+	.supply_name	= "DC_5V",
+	.microvolts	= 5000000,
+	.gpio		= -EINVAL,
+	.init_data	= &mipi_csi_fixed_voltage_init_data,
+};
+
+static struct platform_device mipi_csi_fixed_voltage = {
+	.name		= "reg-fixed-voltage",
+	.id		= 3,
+	.dev		= {
+		.platform_data	= &mipi_csi_fixed_voltage_config,
+	},
+};
+#endif
+
+#ifdef CONFIG_VIDEO_M5MOLS
+static struct regulator_consumer_supply m5mols_fixed_voltage_supplies[] = {
+	REGULATOR_SUPPLY("core", NULL),
+	REGULATOR_SUPPLY("dig_18", NULL),
+	REGULATOR_SUPPLY("d_sensor", NULL),
+	REGULATOR_SUPPLY("dig_28", NULL),
+	REGULATOR_SUPPLY("a_sensor", NULL),
+	REGULATOR_SUPPLY("dig_12", NULL),
+};
+
+static struct regulator_init_data m5mols_fixed_voltage_init_data = {
+	.constraints = {
+		.always_on = 1,
+	},
+	.num_consumer_supplies	= ARRAY_SIZE(m5mols_fixed_voltage_supplies),
+	.consumer_supplies	= m5mols_fixed_voltage_supplies,
+};
+
+static struct fixed_voltage_config m5mols_fixed_voltage_config = {
+	.supply_name	= "CAM_SENSOR",
+	.microvolts	= 1800000,
+	.gpio		= -EINVAL,
+	.init_data	= &m5mols_fixed_voltage_init_data,
+};
+
+static struct platform_device m5mols_fixed_voltage = {
+	.name		= "reg-fixed-voltage",
+	.id		= 4,
+	.dev		= {
+		.platform_data	= &m5mols_fixed_voltage_config,
+	},
+};
+#endif
+
+static struct gpio_event_direct_entry smdkv310_keypad_key_map[] = {
+	{
+		.gpio   = EXYNOS4_GPX0(0),
+		.code   = KEY_POWER,
+	}
+};
+
+static struct gpio_event_input_info smdkv310_keypad_key_info = {
+	.info.func              = gpio_event_input_func,
+	.info.no_suspend        = true,
+	.debounce_time.tv64	= 5 * NSEC_PER_MSEC,
+	.type                   = EV_KEY,
+	.keymap                 = smdkv310_keypad_key_map,
+	.keymap_size            = ARRAY_SIZE(smdkv310_keypad_key_map)
+};
+
+static struct gpio_event_info *smdkv310_input_info[] = {
+	&smdkv310_keypad_key_info.info,
+};
+
+static struct gpio_event_platform_data smdkv310_input_data = {
+	.names  = {
+		"smdkv310-keypad",
+		NULL,
+	},
+	.info           = smdkv310_input_info,
+	.info_count     = ARRAY_SIZE(smdkv310_input_info),
+};
+
+static struct platform_device smdkv310_input_device = {
+	.name   = GPIO_EVENT_DEV_NAME,
+	.id     = 0,
+	.dev    = {
+		.platform_data = &smdkv310_input_data,
+	},
+};
+
+#ifdef CONFIG_WAKEUP_ASSIST
+static struct platform_device wakeup_assist_device = {
+	.name   = "wakeup_assist",
+};
+#endif
+
+static struct regulator_consumer_supply wm8994_fixed_voltage0_supplies[] = {
+	REGULATOR_SUPPLY("AVDD2", "1-001a"),
+	REGULATOR_SUPPLY("CPVDD", "1-001a"),
+};
+
+static struct regulator_consumer_supply wm8994_fixed_voltage1_supplies[] = {
+	REGULATOR_SUPPLY("SPKVDD1", "1-001a"),
+	REGULATOR_SUPPLY("SPKVDD2", "1-001a"),
+};
+
+static struct regulator_consumer_supply wm8994_fixed_voltage2_supplies =
+	REGULATOR_SUPPLY("DBVDD", "1-001a");
+
+static struct regulator_init_data wm8994_fixed_voltage0_init_data = {
+	.constraints = {
+		.always_on = 1,
+	},
+	.num_consumer_supplies	= ARRAY_SIZE(wm8994_fixed_voltage0_supplies),
+	.consumer_supplies	= wm8994_fixed_voltage0_supplies,
+};
+
+static struct regulator_init_data wm8994_fixed_voltage1_init_data = {
+	.constraints = {
+		.always_on = 1,
+	},
+	.num_consumer_supplies	= ARRAY_SIZE(wm8994_fixed_voltage1_supplies),
+	.consumer_supplies	= wm8994_fixed_voltage1_supplies,
+};
+
+static struct regulator_init_data wm8994_fixed_voltage2_init_data = {
+	.constraints = {
+		.always_on = 1,
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &wm8994_fixed_voltage2_supplies,
+};
+
+static struct fixed_voltage_config wm8994_fixed_voltage0_config = {
+	.supply_name	= "VDD_1.8V",
+	.microvolts	= 1800000,
+	.gpio		= -EINVAL,
+	.init_data	= &wm8994_fixed_voltage0_init_data,
+};
+
+static struct fixed_voltage_config wm8994_fixed_voltage1_config = {
+	.supply_name	= "DC_5V",
+	.microvolts	= 5000000,
+	.gpio		= -EINVAL,
+	.init_data	= &wm8994_fixed_voltage1_init_data,
+};
+
+static struct fixed_voltage_config wm8994_fixed_voltage2_config = {
+	.supply_name	= "VDD_3.3V",
+	.microvolts	= 3300000,
+	.gpio		= -EINVAL,
+	.init_data	= &wm8994_fixed_voltage2_init_data,
+};
+
+static struct platform_device wm8994_fixed_voltage0 = {
+	.name		= "reg-fixed-voltage",
+	.id		= 0,
+	.dev		= {
+		.platform_data	= &wm8994_fixed_voltage0_config,
+	},
+};
+
+static struct platform_device wm8994_fixed_voltage1 = {
+	.name		= "reg-fixed-voltage",
+	.id		= 1,
+	.dev		= {
+		.platform_data	= &wm8994_fixed_voltage1_config,
+	},
+};
+
+static struct platform_device wm8994_fixed_voltage2 = {
+	.name		= "reg-fixed-voltage",
+	.id		= 2,
+	.dev		= {
+		.platform_data	= &wm8994_fixed_voltage2_config,
+	},
+};
+
+static struct regulator_consumer_supply wm8994_avdd1_supply =
+	REGULATOR_SUPPLY("AVDD1", "1-001a");
+
+static struct regulator_consumer_supply wm8994_dcvdd_supply =
+	REGULATOR_SUPPLY("DCVDD", "1-001a");
+
+static struct regulator_init_data wm8994_ldo1_data = {
+	.constraints	= {
+		.name		= "AVDD1",
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &wm8994_avdd1_supply,
+};
+
+static struct regulator_init_data wm8994_ldo2_data = {
+	.constraints	= {
+		.name		= "DCVDD",
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &wm8994_dcvdd_supply,
+};
+
+static struct wm8994_pdata wm8994_platform_data = {
+	/* configure gpio1 function: 0x0001(Logic level input/output) */
+	.gpio_defaults[0] = 0x0001,
+	/* configure gpio3/4/5/7 function for AIF2 voice */
+	.gpio_defaults[2] = 0x8100,/* BCLK2 in */
+	.gpio_defaults[3] = 0x8100,/* LRCLK2 in */
+	.gpio_defaults[4] = 0x8100,/* DACDAT2 in */
+	/* configure gpio6 function: 0x0001(Logic level input/output) */
+	.gpio_defaults[5] = 0x0001,
+	.gpio_defaults[6] = 0x0100,/* ADCDAT2 out */
+	.ldo[0] = { 0, NULL, &wm8994_ldo1_data },
+	.ldo[1] = { 0, NULL, &wm8994_ldo2_data },
+};
+
+static uint32_t smdkv310_keymap[] __initdata = {
+	/* KEY(row, col, keycode) */
+	KEY(0, 3, KEY_1), KEY(0, 4, KEY_2), KEY(0, 5, KEY_3),
+	KEY(0, 6, KEY_4), KEY(0, 7, KEY_5),
+	KEY(1, 3, KEY_A), KEY(1, 4, KEY_B), KEY(1, 5, KEY_C),
+	KEY(1, 6, KEY_D), KEY(1, 7, KEY_E)
+};
+
+static struct matrix_keymap_data smdkv310_keymap_data __initdata = {
+	.keymap		= smdkv310_keymap,
+	.keymap_size	= ARRAY_SIZE(smdkv310_keymap),
+};
+
+static struct samsung_keypad_platdata smdkv310_keypad_data __initdata = {
+	.keymap_data	= &smdkv310_keymap_data,
+	.rows		= 2,
+	.cols		= 8,
+};
+
+#ifdef CONFIG_BATTERY_SAMSUNG
+static struct platform_device samsung_device_battery = {
+	.name	= "samsung-fake-battery",
+	.id	= -1,
+};
+#endif
+
+static struct i2c_board_info i2c_devs0[] __initdata = {
+	{
+		I2C_BOARD_INFO("max8649", 0x62),
+		.platform_data	= &exynos4_max8649a_info,
+	}, {
+		I2C_BOARD_INFO("max8952", 0x60),
+		.platform_data	= &exynos4_max8952_info,
+	}, {
+		I2C_BOARD_INFO("max8997", 0x66),
+		.platform_data	= &exynos4_max8997_info,
+	}
+};
+
+static struct i2c_board_info i2c_devs1[] __initdata = {
+	{
+		I2C_BOARD_INFO("wm8994", 0x1a),
+		.platform_data	= &wm8994_platform_data,
+	}, {
+		I2C_BOARD_INFO("max8649", 0x60),
+		.platform_data	= &exynos4_max8649_info,
+	},
+#ifdef CONFIG_VIDEO_TVOUT
+	{
+		I2C_BOARD_INFO("s5p_ddc", (0x74 >> 1)),
+	},
+#endif
+};
+
+#ifdef CONFIG_TOUCHSCREEN_S3C2410
+static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
+	.delay			= 10000,
+	.presc			= 49,
+	.oversampling_shift	= 2,
+	.cal_x_max		= 480,
+	.cal_y_max		= 800,
+	.cal_param		= {
+		33, -9156, 34720100, 14819, 57, -4234968, 65536
+	},
+};
+#endif
+
+#ifdef CONFIG_S3C_DEV_HWMON
+static struct s3c_hwmon_pdata smdkv310_hwmon_pdata __initdata = {
+	/* Reference voltage (1.2V) */
+	.in[0] = &(struct s3c_hwmon_chcfg) {
+		.name		= "smdk:reference-voltage",
+		.mult		= 3300,
+		.div		= 4096,
+	},
+};
+#endif
+
+/* USB EHCI */
+#ifdef CONFIG_USB_EHCI_S5P
+static struct s5p_ehci_platdata smdkv310_ehci_pdata;
+
+static void __init smdkv310_ehci_init(void)
+{
+	struct s5p_ehci_platdata *pdata = &smdkv310_ehci_pdata;
+
+	s5p_ehci_set_platdata(pdata);
+}
+#endif
+
+#ifdef CONFIG_USB_OHCI_S5P
+static struct s5p_ohci_platdata smdkv310_ohci_pdata;
+
+static void __init smdkv310_ohci_init(void)
+{
+	struct s5p_ohci_platdata *pdata = &smdkv310_ohci_pdata;
+
+	s5p_ohci_set_platdata(pdata);
+}
+#endif
+/* USB GADGET */
+#ifdef CONFIG_USB_GADGET
+static struct s5p_usbgadget_platdata smdkv310_usbgadget_pdata;
+
+static void __init smdkv310_usbgadget_init(void)
+{
+	struct s5p_usbgadget_platdata *pdata = &smdkv310_usbgadget_pdata;
+
+	s5p_usbgadget_set_platdata(pdata);
+}
+#endif
+
+#ifdef CONFIG_BUSFREQ_OPP
+/* BUSFREQ to control memory/bus*/
+static struct device_domain busfreq;
+#endif
+
+static struct platform_device exynos4_busfreq = {
+	.id = -1,
+	.name = "exynos-busfreq",
+};
+
+static struct platform_device *smdkv310_devices[] __initdata = {
+#ifdef CONFIG_S3C_DEV_HSMMC
+	&s3c_device_hsmmc0,
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC1
+	&s3c_device_hsmmc1,
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC2
+	&s3c_device_hsmmc2,
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC3
+	&s3c_device_hsmmc3,
+#endif
+#ifdef CONFIG_S5P_DEV_MSHC
+	&s3c_device_mshci,
+#endif
+#ifdef CONFIG_EXYNOS4_DEV_DWMCI
+	&exynos_device_dwmci,
+#endif
+	&s3c_device_i2c0,
+	&s3c_device_i2c1,
+	&s3c_device_adc,
+#ifdef CONFIG_S3C_DEV_HWMON
+	&s3c_device_hwmon,
+#endif
+#ifdef CONFIG_TOUCHSCREEN_S3C2410
+#ifdef CONFIG_S3C_DEV_ADC
+	&s3c_device_ts,
+#elif CONFIG_S3C_DEV_ADC1
+	&s3c_device_ts1,
+#endif
+#endif
+	&s3c_device_rtc,
+	&s3c_device_wdt,
+	&exynos_device_ac97,
+	&exynos_device_i2s0,
+	&exynos_device_pcm0,
+	&exynos_device_spdif,
+#ifdef CONFIG_SND_SAMSUNG_RP
+	&exynos_device_srp,
+#endif
+	&samsung_device_keypad,
+#ifdef CONFIG_BATTERY_SAMSUNG
+	&samsung_device_battery,
+#endif
+	&exynos4_device_pd[PD_MFC],
+	&exynos4_device_pd[PD_G3D],
+	&exynos4_device_pd[PD_LCD0],
+	&exynos4_device_pd[PD_LCD1],
+	&exynos4_device_pd[PD_CAM],
+	&exynos4_device_pd[PD_TV],
+	&exynos4_device_pd[PD_GPS],
+#ifdef CONFIG_S5P_SYSTEM_MMU
+	&SYSMMU_PLATDEV(sss),
+	&SYSMMU_PLATDEV(fimc0),
+	&SYSMMU_PLATDEV(fimc1),
+	&SYSMMU_PLATDEV(fimc2),
+	&SYSMMU_PLATDEV(fimc3),
+	&SYSMMU_PLATDEV(jpeg),
+	&SYSMMU_PLATDEV(fimd0),
+	&SYSMMU_PLATDEV(fimd1),
+	&SYSMMU_PLATDEV(pcie),
+	&SYSMMU_PLATDEV(2d),
+	&SYSMMU_PLATDEV(rot),
+	&SYSMMU_PLATDEV(mdma),
+	&SYSMMU_PLATDEV(tv),
+	&SYSMMU_PLATDEV(mfc_l),
+	&SYSMMU_PLATDEV(mfc_r),
+#endif
+#ifdef CONFIG_ION_EXYNOS
+	&exynos_device_ion,
+#endif
+	&wm8994_fixed_voltage0,
+	&wm8994_fixed_voltage1,
+	&wm8994_fixed_voltage2,
+	&samsung_asoc_dma,
+	&samsung_asoc_idma,
+#ifdef CONFIG_S3C64XX_DEV_SPI
+	&exynos_device_spi0,
+	&exynos_device_spi2,
+#endif
+/* mainline fimd */
+#ifdef CONFIG_FB_S3C
+	&s5p_device_fimd0,
+#if defined(CONFIG_LCD_AMS369FG06)
+	&s3c_device_spi_gpio,
+#elif defined(CONFIG_LCD_WA101S)
+	&smdkv310_lcd_wa101s,
+#elif defined(CONFIG_LCD_LTE480WV)
+	&smdkv310_lcd_lte480wv,
+#endif
+#endif
+/* legacy fimd */
+#ifdef CONFIG_FB_S5P
+	&s3c_device_fb,
+#ifdef CONFIG_FB_S5P_AMS369FG06
+	&s3c_device_spi_gpio,
+#endif
+#endif
+#ifdef CONFIG_VIDEO_TVOUT
+	&s5p_device_tvout,
+	&s5p_device_cec,
+	&s5p_device_hpd,
+#endif
+	&smdkv310_smsc911x,
+	&smdkv310_input_device,
+#ifdef CONFIG_WAKEUP_ASSIST
+	&wakeup_assist_device,
+#endif
+#ifdef CONFIG_VIDEO_FIMC
+	&s3c_device_fimc0,
+	&s3c_device_fimc1,
+	&s3c_device_fimc2,
+	&s3c_device_fimc3,
+#endif
+#ifdef CONFIG_VIDEO_FIMC_MIPI
+	&s3c_device_csis0,
+	&s3c_device_csis1,
+#endif
+/* CONFIG_VIDEO_SAMSUNG_S5P_FIMC & CONFIG_VIDEO_SAMSUNG_S5P_FIMC are the
+ * feature for mainline */
+#ifdef CONFIG_VIDEO_SAMSUNG_S5P_FIMC
+	&s5p_device_fimc0,
+	&s5p_device_fimc1,
+	&s5p_device_fimc2,
+	&s5p_device_fimc3,
+#endif
+#ifdef CONFIG_VIDEO_S5P_MIPI_CSIS
+	&s5p_device_mipi_csis0,
+	&s5p_device_mipi_csis1,
+#endif
+
+#ifdef CONFIG_VIDEO_S5P_MIPI_CSIS
+	&mipi_csi_fixed_voltage,
+#endif
+#ifdef CONFIG_VIDEO_M5MOLS
+	&m5mols_fixed_voltage,
+#endif
+
+#if defined(CONFIG_VIDEO_MFC5X) || defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC)
+	&s5p_device_mfc,
+#endif
+#ifdef CONFIG_VIDEO_FIMG2D
+	&s5p_device_fimg2d,
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS_ROTATOR
+	&exynos_device_rotator,
+#endif
+#ifdef CONFIG_VIDEO_JPEG
+	&s5p_device_jpeg,
+#endif
+#ifdef CONFIG_USB_EHCI_S5P
+	&s5p_device_ehci,
+#endif
+#ifdef CONFIG_USB_OHCI_S5P
+	&s5p_device_ohci,
+#endif
+#ifdef CONFIG_USB_GADGET
+	&s3c_device_usbgadget,
+#endif
+#ifdef CONFIG_USB_ANDROID_RNDIS
+	&s3c_device_rndis,
+#endif
+#ifdef CONFIG_USB_ANDROID
+	&s3c_device_android_usb,
+	&s3c_device_usb_mass_storage,
+#endif
+#ifdef CONFIG_EXYNOS4_SETUP_THERMAL
+	&s5p_device_tmu,
+#endif
+#ifdef CONFIG_SATA_AHCI_PLATFORM
+	&exynos4_device_ahci,
+#endif
+#ifdef CONFIG_S5P_DEV_ACE
+	&s5p_device_ace,
+#endif
+	&exynos4_busfreq,
+};
+
+#if defined(CONFIG_VIDEO_TVOUT)
+static struct s5p_platform_hpd hdmi_hpd_data __initdata = {
+
+};
+static struct s5p_platform_cec hdmi_cec_data __initdata = {
+
+};
+#endif
+
+static void __init smdkv310_button_init(void)
+{
+	s3c_gpio_cfgpin(EXYNOS4_GPX0(0), (0xf << 0));
+	s3c_gpio_setpull(EXYNOS4_GPX0(0), S3C_GPIO_PULL_NONE);
+
+	s3c_gpio_cfgpin(EXYNOS4_GPX3(7), (0xf << 28));
+	s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
+}
+
+#ifdef CONFIG_VIDEO_SAMSUNG_S5P_FIMC
+static struct s5p_fimc_isp_info isp_info[] = {
+#if defined(CONFIG_VIDEO_S5K4BA)
+	{
+		.board_info	= &s5k4ba_info,
+		.clk_frequency  = 24000000UL,
+		.bus_type	= FIMC_ITU_601,
+#ifdef CONFIG_ITU_A
+		.i2c_bus_num	= 0,
+		.mux_id		= 0, /* A-Port : 0, B-Port : 1 */
+#endif
+#ifdef CONFIG_ITU_B
+		.i2c_bus_num	= 1,
+		.mux_id		= 1, /* A-Port : 0, B-Port : 1 */
+#endif
+		.flags		= FIMC_CLK_INV_VSYNC,
+	},
+#endif
+#if defined(CONFIG_VIDEO_S5K4EA)
+	{
+		.board_info	= &s5k4ea_info,
+		.clk_frequency  = 24000000UL,
+		.bus_type	= FIMC_MIPI_CSI2,
+#ifdef CONFIG_CSI_C
+		.i2c_bus_num	= 0,
+		.mux_id		= 0, /* A-Port : 0, B-Port : 1 */
+#endif
+#ifdef CONFIG_CSI_D
+		.i2c_bus_num	= 1,
+		.mux_id		= 1, /* A-Port : 0, B-Port : 1 */
+#endif
+		.flags		= FIMC_CLK_INV_VSYNC,
+		.csi_data_align = 32,
+	},
+#endif
+#if defined(CONFIG_VIDEO_M5MOLS)
+	{
+		.board_info	= &m5mols_board_info,
+		.clk_frequency  = 24000000UL,
+		.bus_type	= FIMC_MIPI_CSI2,
+#ifdef CONFIG_CSI_C
+		.i2c_bus_num	= 0,
+		.mux_id		= 0, /* A-Port : 0, B-Port : 1 */
+#endif
+#ifdef CONFIG_CSI_D
+		.i2c_bus_num	= 1,
+		.mux_id		= 1, /* A-Port : 0, B-Port : 1 */
+#endif
+		.flags		= FIMC_CLK_INV_PCLK | FIMC_CLK_INV_VSYNC,
+		.csi_data_align = 32,
+	},
+#endif
+
+#if defined(WRITEBACK_ENABLED)
+	{
+		.board_info	= &writeback_info,
+		.bus_type	= FIMC_LCD_WB,
+		.i2c_bus_num	= 0,
+		.mux_id		= 0, /* A-Port : 0, B-Port : 1 */
+		.flags		= FIMC_CLK_INV_VSYNC,
+	},
+#endif
+};
+
+static void __init smdkv310_subdev_config(void)
+{
+	s3c_fimc0_default_data.isp_info[0] = &isp_info[0];
+	s3c_fimc0_default_data.isp_info[0]->use_cam = true;
+	/* support using two fimc as one sensore */
+	{
+		static struct s5p_fimc_isp_info camcording;
+		memcpy(&camcording, &isp_info[0], sizeof(struct s5p_fimc_isp_info));
+		s3c_fimc2_default_data.isp_info[0] = &camcording;
+		s3c_fimc2_default_data.isp_info[0]->use_cam = false;
+	}
+}
+
+static void __init smdkv310_camera_config(void)
+{
+	int i = 0;
+
+	/* CAM A port(b0010) : PCLK, VSYNC, HREF, DATA[0-4] */
+	for (i = 0; i < 8; i++) {
+		s3c_gpio_cfgpin(EXYNOS4210_GPJ0(i), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(EXYNOS4210_GPJ0(i), S3C_GPIO_PULL_NONE);
+	}
+	/* CAM A port(b0010) : DATA[5-7], CLKOUT(MIPI CAM also), FIELD */
+	for (i = 0; i < 5; i++) {
+		s3c_gpio_cfgpin(EXYNOS4210_GPJ1(i), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(EXYNOS4210_GPJ1(i), S3C_GPIO_PULL_NONE);
+	}
+	/* CAM B port(b0011) : DATA[0-7] */
+	for (i = 0; i < 8; i++) {
+		s3c_gpio_cfgpin(EXYNOS4210_GPE1(i), S3C_GPIO_SFN(3));
+		s3c_gpio_setpull(EXYNOS4210_GPE1(i), S3C_GPIO_PULL_NONE);
+	}
+	/* CAM B port(b0011) : PCLK, VSYNC, HREF, FIELD, CLCKOUT */
+	for (i = 0; i < 5; i++) {
+		s3c_gpio_cfgpin(EXYNOS4210_GPE0(i), S3C_GPIO_SFN(3));
+		s3c_gpio_setpull(EXYNOS4210_GPE0(i), S3C_GPIO_PULL_NONE);
+	}
+	/* note : driver strength to max is unnecessary */
+#ifdef CONFIG_VIDEO_M5MOLS
+	s3c_gpio_cfgpin(EXYNOS4_GPX0(5), S3C_GPIO_SFN(0xF));
+	s3c_gpio_setpull(EXYNOS4_GPX0(5), S3C_GPIO_PULL_NONE);
+#endif
+}
+#endif
+
+static void __init smdkv310_smsc911x_init(void)
+{
+	u32 cs1;
+
+	/* configure nCS1 width to 16 bits */
+	cs1 = __raw_readl(S5P_SROM_BW) &
+		~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
+	cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
+		(1 << S5P_SROM_BW__WAITENABLE__SHIFT) |
+		(1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
+		S5P_SROM_BW__NCS1__SHIFT;
+	__raw_writel(cs1, S5P_SROM_BW);
+
+	/* set timing for nCS1 suitable for ethernet chip */
+	__raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
+		     (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
+		     (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
+		     (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
+		     (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
+		     (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
+		     (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
+}
+
+#if defined(CONFIG_CMA)
+static void __init exynos4_reserve_mem(void)
+{
+	static struct cma_region regions[] = {
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_JPEG
+		{
+			.name = "jpeg",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_JPEG * SZ_1K,
+			.start = 0
+		},
+#endif
+#ifdef CONFIG_AUDIO_SAMSUNG_MEMSIZE_SRP
+		{
+			.name = "srp",
+			.size = CONFIG_AUDIO_SAMSUNG_MEMSIZE_SRP * SZ_1K,
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMG2D
+		{
+			.name = "fimg2d",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMG2D * SZ_1K,
+			.start = 0
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMD
+		{
+			.name = "fimd",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMD * SZ_1K,
+			.start = 0
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC2
+		{
+			.name = "fimc2",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC2 * SZ_1K,
+			.start = 0
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC3
+		{
+			.name = "fimc3",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC3 * SZ_1K,
+			.start = 0
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC0
+		{
+			.name = "fimc0",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC0 * SZ_1K,
+			.start = 0
+		},
+#endif
+#if !defined(CONFIG_EXYNOS_CONTENT_PATH_PROTECTION) && \
+	defined(CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC1)
+		{
+			.name = "fimc1",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC1 * SZ_1K,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC_NORMAL
+		{
+			.name = "mfc-normal",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC_NORMAL * SZ_1K,
+			{ .alignment = 1 << 17 },
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC1
+		{
+			.name = "mfc1",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC1 * SZ_1K,
+			{ .alignment = 1 << 17 },
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC0
+		{
+			.name = "mfc0",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC0 * SZ_1K,
+			{ .alignment = 1 << 17 },
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC
+		{
+			.name = "mfc",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC * SZ_1K,
+			{ .alignment = 1 << 17 },
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_ROT
+		{
+			.name = "rot",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_ROT * SZ_1K,
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_S5P_MFC
+		{
+			.name		= "b2",
+			.size		= 32 << 20,
+			{ .alignment	= 128 << 10 },
+		},
+		{
+			.name		= "b1",
+			.size		= 32 << 20,
+			{ .alignment	= 128 << 10 },
+		},
+		{
+			.name		= "fw",
+			.size		= 1 << 20,
+			{ .alignment	= 128 << 10 },
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_TVOUT
+		{
+			.name = "tvout",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_TVOUT * SZ_1K,
+			.start = 0
+		},
+#endif
+		{
+			.size = 0
+		},
+	};
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+	static struct cma_region regions_secure[] = {
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC1
+		{
+			.name = "fimc1",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC1 * SZ_1K,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC_SECURE
+		{
+			.name = "mfc-secure",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC_SECURE * SZ_1K,
+			{
+				.alignment = SZ_64M,
+			},
+		},
+#endif
+		{
+			.size = 0
+		},
+	};
+#else /* !CONFIG_EXYNOS_CONTENT_PATH_PROTECTION */
+	struct cma_region *regions_secure = NULL;
+#endif
+	static const char map[] __initconst =
+		"s3cfb.0=fimd;exynos4-fb.0=fimd;"
+		"s3c-fimc.0=fimc0;s3c-fimc.1=fimc1;s3c-fimc.2=fimc2;s3c-fimc.3=fimc3;"
+		"exynos4210-fimc.0=fimc0;exynos4210-fimc.1=fimc1;exynos4210-fimc.2=fimc2;exynos4210-fimc.3=fimc3;"
+#ifdef CONFIG_VIDEO_EXYNOS_ROTATOR
+		"exynos-rot=rot;"
+#endif
+#ifdef CONFIG_VIDEO_MFC5X
+		"s3c-mfc/A=mfc0,mfc-secure;"
+		"s3c-mfc/B=mfc1,mfc-normal;"
+		"s3c-mfc/AB=mfc;"
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_S5P_MFC
+		"s5p-mfc/f=fw;"
+		"s5p-mfc/a=b1;"
+		"s5p-mfc/b=b2;"
+#endif
+		"samsung-rp=srp;"
+		"s5p-jpeg=jpeg;"
+		"s5p-fimg2d=fimg2d;"
+		"s5p-tvout=tvout;"
+		"s5p-smem/mfc=mfc0,mfc-secure;"
+		"s5p-smem/fimc=fimc1;"
+		"s5p-smem/mfc-shm=mfc1,mfc-normal;"
+		"ion-exynos=fimd,fimc0,fimc1,fimc2,fimc3,fw,b1,b2;";
+
+	s5p_cma_region_reserve(regions, regions_secure, SZ_64M, map);
+}
+#endif
+
+/* LCD Backlight data */
+static struct samsung_bl_gpio_info smdkv310_bl_gpio_info = {
+	.no = EXYNOS4_GPD0(1),
+	.func = S3C_GPIO_SFN(2),
+};
+
+static struct platform_pwm_backlight_data smdkv310_bl_data = {
+	.pwm_id = 1,
+#if defined(CONFIG_LCD_LTE480WV)
+	.pwm_period_ns  = 1000,
+#endif
+};
+
+static void __init smdkv310_map_io(void)
+{
+	clk_xusbxti.rate = 24000000;
+
+	s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+	s3c24xx_init_clocks(24000000);
+	s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
+
+#if defined(CONFIG_CMA)
+	exynos4_reserve_mem();
+#else
+	s5p_reserve_mem(S5P_RANGE_MFC);
+#endif
+}
+
+static void __init exynos_sysmmu_init(void)
+{
+	ASSIGN_SYSMMU_POWERDOMAIN(fimc0, &exynos4_device_pd[PD_CAM].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(fimc1, &exynos4_device_pd[PD_CAM].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(fimc2, &exynos4_device_pd[PD_CAM].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(fimc3, &exynos4_device_pd[PD_CAM].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(jpeg, &exynos4_device_pd[PD_CAM].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(fimd0, &exynos4_device_pd[PD_LCD0].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(2d, &exynos4_device_pd[PD_LCD0].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(rot, &exynos4_device_pd[PD_LCD0].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(tv, &exynos4_device_pd[PD_TV].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(mfc_l, &exynos4_device_pd[PD_MFC].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(mfc_r, &exynos4_device_pd[PD_MFC].dev);
+#if defined CONFIG_VIDEO_FIMC
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc0).dev, &s3c_device_fimc0.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc1).dev, &s3c_device_fimc1.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc2).dev, &s3c_device_fimc2.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc3).dev, &s3c_device_fimc3.dev);
+#elif defined CONFIG_VIDEO_SAMSUNG_S5P_FIMC
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc0).dev, &s5p_device_fimc0.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc1).dev, &s5p_device_fimc1.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc2).dev, &s5p_device_fimc2.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc3).dev, &s5p_device_fimc3.dev);
+#endif
+#ifdef CONFIG_VIDEO_JPEG
+	sysmmu_set_owner(&SYSMMU_PLATDEV(jpeg).dev, &s5p_device_jpeg.dev);
+#endif
+#ifdef CONFIG_FB_S3C
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimd0).dev, &s5p_device_fimd0.dev);
+#endif
+#ifdef CONFIG_VIDEO_FIMG2D
+	sysmmu_set_owner(&SYSMMU_PLATDEV(2d).dev, &s5p_device_fimg2d.dev);
+#endif
+#ifdef CONFIG_VIDEO_TVOUT
+	sysmmu_set_owner(&SYSMMU_PLATDEV(tv).dev, &s5p_device_tvout.dev);
+#endif
+#if defined(CONFIG_VIDEO_MFC5X) || defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC)
+	sysmmu_set_owner(&SYSMMU_PLATDEV(mfc_l).dev, &s5p_device_mfc.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(mfc_r).dev, &s5p_device_mfc.dev);
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS_ROTATOR
+	sysmmu_set_owner(&SYSMMU_PLATDEV(rot).dev, &exynos_device_rotator.dev);
+#endif
+}
+
+static void __init smdkv310_machine_init(void)
+{
+#ifdef CONFIG_S3C64XX_DEV_SPI
+	struct clk *sclk = NULL;
+	struct clk *prnt = NULL;
+	struct device *spi0_dev = &exynos_device_spi0.dev;
+	struct device *spi2_dev = &exynos_device_spi2.dev;
+#endif
+#if defined(CONFIG_FB_S5P_MIPI_DSIM)
+	mipi_fb_init();
+#endif
+
+#if defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME)
+	exynos_pd_disable(&exynos4_device_pd[PD_MFC].dev);
+	exynos_pd_disable(&exynos4_device_pd[PD_G3D].dev);
+	exynos_pd_disable(&exynos4_device_pd[PD_LCD0].dev);
+	exynos_pd_disable(&exynos4_device_pd[PD_LCD1].dev);
+	exynos_pd_disable(&exynos4_device_pd[PD_CAM].dev);
+	exynos_pd_disable(&exynos4_device_pd[PD_TV].dev);
+	exynos_pd_disable(&exynos4_device_pd[PD_GPS].dev);
+#elif defined(CONFIG_EXYNOS_DEV_PD)
+	/*
+	 * These power domains should be always on
+	 * without runtime pm support.
+	 */
+	exynos_pd_enable(&exynos4_device_pd[PD_MFC].dev);
+	exynos_pd_enable(&exynos4_device_pd[PD_G3D].dev);
+	exynos_pd_enable(&exynos4_device_pd[PD_LCD0].dev);
+	exynos_pd_enable(&exynos4_device_pd[PD_LCD1].dev);
+	exynos_pd_enable(&exynos4_device_pd[PD_CAM].dev);
+	exynos_pd_enable(&exynos4_device_pd[PD_TV].dev);
+	exynos_pd_enable(&exynos4_device_pd[PD_GPS].dev);
+#endif
+	s3c_i2c0_set_platdata(NULL);
+	i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
+
+	s3c_i2c1_set_platdata(NULL);
+	i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
+
+	smdkv310_button_init();
+	smdkv310_smsc911x_init();
+
+#ifdef CONFIG_EXYNOS4_DEV_DWMCI
+	if (samsung_rev() != EXYNOS4210_REV_1_1)
+		exynos_dwmci_pdata.caps &= ~(MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR);
+	exynos_dwmci_set_platdata(&exynos_dwmci_pdata. 0);
+#endif
+
+#ifdef CONFIG_S3C_DEV_HSMMC
+	s3c_sdhci0_set_platdata(&smdkv310_hsmmc0_pdata);
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC1
+	s3c_sdhci1_set_platdata(&smdkv310_hsmmc1_pdata);
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC2
+	s3c_sdhci2_set_platdata(&smdkv310_hsmmc2_pdata);
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC3
+	s3c_sdhci3_set_platdata(&smdkv310_hsmmc3_pdata);
+#endif
+#ifdef CONFIG_S5P_DEV_MSHC
+	s3c_mshci_set_platdata(&exynos4_mshc_pdata);
+#endif
+#ifdef CONFIG_S3C_DEV_HWMON
+	s3c_hwmon_set_platdata(&smdkv310_hwmon_pdata);
+#endif
+
+#ifdef CONFIG_FB_S3C
+	dev_set_name(&s5p_device_fimd0.dev, "s3cfb.0");
+	clk_add_alias("lcd", "exynos4-fb.0", "lcd", &s5p_device_fimd0.dev);
+	clk_add_alias("sclk_fimd", "exynos4-fb.0", "sclk_fimd", &s5p_device_fimd0.dev);
+#ifdef CONFIG_LCD_AMS369FG06
+	spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
+#endif
+	s5p_fimd0_set_platdata(&smdkv310_lcd0_pdata);
+#ifdef CONFIG_EXYNOS_DEV_PD
+	s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
+#endif
+#endif
+
+#ifdef CONFIG_FB_S5P
+#ifdef CONFIG_FB_S5P_AMS369FG06
+	spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
+	s3cfb_set_platdata(&ams369fg06_data);
+#elif defined(CONFIG_FB_S5P_DUMMY_MIPI_LCD)
+	exynos4_fimd0_gpio_setup_24bpp();
+#else
+	s3cfb_set_platdata(NULL);
+#endif
+#ifdef CONFIG_EXYNOS_DEV_PD
+	s3c_device_fb.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
+#endif
+#endif
+
+#ifdef CONFIG_EXYNOS_DEV_PD
+#ifdef CONFIG_VIDEO_JPEG
+	s5p_device_jpeg.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+#endif
+#ifdef CONFIG_FB_S5P_MIPI_DSIM
+	s5p_device_dsim.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
+#endif
+#endif
+#if defined(CONFIG_VIDEO_TVOUT)
+	s5p_hdmi_hpd_set_platdata(&hdmi_hpd_data);
+	s5p_hdmi_cec_set_platdata(&hdmi_cec_data);
+#ifdef CONFIG_EXYNOS_DEV_PD
+	s5p_device_tvout.dev.parent = &exynos4_device_pd[PD_TV].dev;
+#endif
+#endif
+	samsung_bl_set(&smdkv310_bl_gpio_info, &smdkv310_bl_data);
+
+	samsung_keypad_set_platdata(&smdkv310_keypad_data);
+
+#ifdef CONFIG_TOUCHSCREEN_S3C2410
+#ifdef CONFIG_S3C_DEV_ADC
+	s3c24xx_ts_set_platdata(&s3c_ts_platform);
+#endif
+#ifdef CONFIG_S3C_DEV_ADC1
+	s3c24xx_ts1_set_platdata(&s3c_ts_platform);
+#endif
+#endif
+#ifdef CONFIG_VIDEO_FIMC
+	s3c_fimc0_set_platdata(&fimc_plat);
+	s3c_fimc1_set_platdata(NULL);
+	s3c_fimc2_set_platdata(&fimc_plat);
+	s3c_fimc3_set_platdata(NULL);
+#ifdef CONFIG_EXYNOS_DEV_PD
+	s3c_device_fimc0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+	s3c_device_fimc1.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+	s3c_device_fimc2.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+	s3c_device_fimc3.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+	secmem.parent = &exynos4_device_pd[PD_CAM].dev;
+#endif
+#endif
+#ifdef CONFIG_VIDEO_FIMC_MIPI
+	s3c_csis0_set_platdata(NULL);
+	s3c_csis1_set_platdata(NULL);
+#ifdef CONFIG_EXYNOS_DEV_PD
+	s3c_device_csis0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+	s3c_device_csis1.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+#endif
+#endif
+#if defined(CONFIG_ITU_A) || defined(CONFIG_CSI_C)
+	smdkv310_cam0_reset(1);
+#endif
+#if defined(CONFIG_ITU_B) || defined(CONFIG_CSI_D)
+	smdkv310_cam1_reset(1);
+#endif
+#endif /* CONFIG_VIDEO_FIMC */
+
+#ifdef CONFIG_VIDEO_SAMSUNG_S5P_FIMC
+	smdkv310_camera_config();
+	smdkv310_subdev_config();
+
+	dev_set_name(&s5p_device_fimc0.dev, "s3c-fimc.0");
+	dev_set_name(&s5p_device_fimc1.dev, "s3c-fimc.1");
+	dev_set_name(&s5p_device_fimc2.dev, "s3c-fimc.2");
+	dev_set_name(&s5p_device_fimc3.dev, "s3c-fimc.3");
+
+	clk_add_alias("fimc", "exynos4210-fimc.0", "fimc", &s5p_device_fimc0.dev);
+	clk_add_alias("sclk_fimc", "exynos4210-fimc.0", "sclk_fimc",
+			&s5p_device_fimc0.dev);
+	clk_add_alias("fimc", "exynos4210-fimc.1", "fimc", &s5p_device_fimc1.dev);
+	clk_add_alias("sclk_fimc", "exynos4210-fimc.1", "sclk_fimc",
+			&s5p_device_fimc1.dev);
+	clk_add_alias("fimc", "exynos4210-fimc.2", "fimc", &s5p_device_fimc2.dev);
+	clk_add_alias("sclk_fimc", "exynos4210-fimc.2", "sclk_fimc",
+			&s5p_device_fimc2.dev);
+	clk_add_alias("fimc", "exynos4210-fimc.3", "fimc", &s5p_device_fimc3.dev);
+	clk_add_alias("sclk_fimc", "exynos4210-fimc.3", "sclk_fimc",
+			&s5p_device_fimc3.dev);
+
+	s3c_fimc_setname(0, "exynos4210-fimc");
+	s3c_fimc_setname(1, "exynos4210-fimc");
+	s3c_fimc_setname(2, "exynos4210-fimc");
+	s3c_fimc_setname(3, "exynos4210-fimc");
+	/* FIMC */
+	s3c_set_platdata(&s3c_fimc0_default_data,
+			 sizeof(s3c_fimc0_default_data), &s5p_device_fimc0);
+	s3c_set_platdata(&s3c_fimc1_default_data,
+			 sizeof(s3c_fimc1_default_data), &s5p_device_fimc1);
+	s3c_set_platdata(&s3c_fimc2_default_data,
+			 sizeof(s3c_fimc2_default_data), &s5p_device_fimc2);
+	s3c_set_platdata(&s3c_fimc3_default_data,
+			 sizeof(s3c_fimc3_default_data), &s5p_device_fimc3);
+#ifdef CONFIG_EXYNOS_DEV_PD
+	s5p_device_fimc0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+	s5p_device_fimc1.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+	s5p_device_fimc2.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+	s5p_device_fimc3.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+#endif
+#ifdef CONFIG_VIDEO_S5P_MIPI_CSIS
+	s3c_set_platdata(&s5p_mipi_csis0_default_data,
+			sizeof(s5p_mipi_csis0_default_data), &s5p_device_mipi_csis0);
+	s3c_set_platdata(&s5p_mipi_csis1_default_data,
+			sizeof(s5p_mipi_csis1_default_data), &s5p_device_mipi_csis1);
+#ifdef CONFIG_EXYNOS_DEV_PD
+	s5p_device_mipi_csis0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+	s5p_device_mipi_csis1.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+#endif
+#endif
+#if defined(CONFIG_ITU_A) || defined(CONFIG_CSI_C)
+	smdkv310_cam0_reset(1);
+#endif
+#if defined(CONFIG_ITU_B) || defined(CONFIG_CSI_D)
+	smdkv310_cam1_reset(1);
+#endif
+#endif
+
+#ifdef CONFIG_ION_EXYNOS
+	exynos_ion_set_platdata();
+#endif
+
+#ifdef CONFIG_EXYNOS4_SETUP_THERMAL
+	s5p_tmu_set_platdata(NULL);
+#endif
+
+#if defined(CONFIG_VIDEO_MFC5X) || defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC)
+#ifdef CONFIG_EXYNOS_DEV_PD
+	s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
+#endif
+#endif
+
+#if defined(CONFIG_VIDEO_MFC5X)
+	exynos4_mfc_setup_clock(&s5p_device_mfc.dev, 200 * MHZ);
+#endif
+#if defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC)
+	dev_set_name(&s5p_device_mfc.dev, "s3c-mfc");
+	clk_add_alias("mfc", "s5p-mfc", "mfc", &s5p_device_mfc.dev);
+	s5p_mfc_setname(&s5p_device_mfc, "s5p-mfc");
+#endif
+
+#ifdef CONFIG_VIDEO_FIMG2D
+	s5p_fimg2d_set_platdata(&fimg2d_data);
+#ifdef CONFIG_EXYNOS_DEV_PD
+	s5p_device_fimg2d.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
+#endif
+#endif
+
+#ifdef CONFIG_VIDEO_EXYNOS_ROTATOR
+	exynos_device_rotator.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
+#endif
+
+#ifdef CONFIG_USB_EHCI_S5P
+	smdkv310_ehci_init();
+#endif
+#ifdef CONFIG_USB_OHCI_S5P
+	smdkv310_ohci_init();
+#endif
+#ifdef CONFIG_USB_GADGET
+	smdkv310_usbgadget_init();
+#endif
+
+	exynos_sysmmu_init();
+
+	platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices));
+
+#ifdef CONFIG_FB_S3C
+	exynos4_fimd0_setup_clock(&s5p_device_fimd0.dev, "mout_mpll",
+				800 * MHZ);
+#endif
+
+#ifdef CONFIG_S3C64XX_DEV_SPI
+	sclk = clk_get(spi0_dev, "sclk_spi");
+	if (IS_ERR(sclk))
+		dev_err(spi0_dev, "failed to get sclk for SPI-0\n");
+
+	prnt = clk_get(spi0_dev, "mout_mpll");
+	if (IS_ERR(prnt))
+		dev_err(spi0_dev, "failed to get prnt\n");
+
+	if (!IS_ERR(sclk) && !IS_ERR(prnt))
+		if (clk_set_parent(sclk, prnt))
+			printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
+					prnt->name, sclk->name);
+	clk_put(sclk);
+	clk_put(prnt);
+
+	if (!gpio_request(EXYNOS4_GPB(1), "SPI_CS0")) {
+		gpio_direction_output(EXYNOS4_GPB(1), 1);
+		s3c_gpio_cfgpin(EXYNOS4_GPB(1), S3C_GPIO_SFN(1));
+		s3c_gpio_setpull(EXYNOS4_GPB(1), S3C_GPIO_PULL_UP);
+		exynos_spi_set_info(0, EXYNOS_SPI_SRCCLK_SCLK,
+				ARRAY_SIZE(spi0_csi));
+	}
+	spi_register_board_info(spi0_board_info, ARRAY_SIZE(spi0_board_info));
+
+	sclk = clk_get(spi2_dev, "sclk_spi");
+	if (IS_ERR(sclk))
+		dev_err(spi2_dev, "failed to get sclk for SPI-2\n");
+
+	prnt = clk_get(spi2_dev, "mout_mpll");
+	if (IS_ERR(prnt))
+		dev_err(spi2_dev, "failed to get prnt\n");
+
+	if (!IS_ERR(sclk) && !IS_ERR(prnt))
+		if (clk_set_parent(sclk, prnt))
+			printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
+					prnt->name, sclk->name);
+	clk_put(sclk);
+	clk_put(prnt);
+
+	if (!gpio_request(EXYNOS4_GPC1(2), "SPI_CS2")) {
+		gpio_direction_output(EXYNOS4_GPC1(2), 1);
+		s3c_gpio_cfgpin(EXYNOS4_GPC1(2), S3C_GPIO_SFN(1));
+		s3c_gpio_setpull(EXYNOS4_GPC1(2), S3C_GPIO_PULL_UP);
+		exynos_spi_set_info(2, EXYNOS_SPI_SRCCLK_SCLK,
+				ARRAY_SIZE(spi2_csi));
+	}
+	spi_register_board_info(spi2_board_info, ARRAY_SIZE(spi2_board_info));
+#endif
+#ifdef CONFIG_BUSFREQ_OPP
+	dev_add(&busfreq, &exynos4_busfreq.dev);
+#endif
+}
+
+MACHINE_START(SMDKC210, "SMDKC210")
+	/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
+	.boot_params	= S5P_PA_SDRAM + 0x100,
+	.init_irq	= exynos4_init_irq,
+	.map_io		= smdkv310_map_io,
+	.init_machine	= smdkv310_machine_init,
+	.timer		= &exynos4_timer,
+MACHINE_END
+
+MACHINE_START(SMDKV310, "SMDKV310")
+	/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
+	/* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */
+	.boot_params	= S5P_PA_SDRAM + 0x100,
+	.init_irq	= exynos4_init_irq,
+	.map_io		= smdkv310_map_io,
+	.init_machine	= smdkv310_machine_init,
+	.timer		= &exynos4_timer,
+MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-u1.c b/arch/arm/mach-exynos/mach-u1.c
new file mode 100644
index 0000000..9c026e0
--- /dev/null
+++ b/arch/arm/mach-exynos/mach-u1.c
@@ -0,0 +1,7497 @@
+/* linux/arch/arm/mach-exynos4/mach-smdkc210.c
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/serial_core.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/gpio_keys.h>
+#include <linux/gpio_event.h>
+#include <linux/lcd.h>
+#include <linux/mmc/host.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/i2c.h>
+#include <linux/i2c-gpio.h>
+#include <linux/input.h>
+#include <linux/switch.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi_gpio.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+#include <linux/mfd/max8997.h>
+#include <linux/mfd/max8997-private.h>
+#include <linux/sensor/k3g.h>
+#include <linux/sensor/k3dh.h>
+#include <linux/sensor/ak8975.h>
+#ifdef CONFIG_MACH_U1_BD
+#include <linux/sensor/cm3663.h>
+#include <linux/sensor/pas2m110.h>
+#endif
+#ifdef CONFIG_MACH_Q1_BD
+#include <linux/sensor/gp2a_analog.h>
+#endif
+#include <linux/pn544.h>
+#ifdef CONFIG_SND_SOC_U1_MC1N2
+#include <linux/mfd/mc1n2_pdata.h>
+#endif
+#if defined(CONFIG_TOUCHSCREEN_ATMEL_MXT540E)
+#include <linux/i2c/mxt540e.h>
+#else
+#ifdef CONFIG_TOUCHSCREEN_ATMEL_MXT224_GC
+#include <linux/i2c/mxt224_gc.h>
+#else
+#include <linux/i2c/mxt224_u1.h>
+#endif
+#endif
+#include <linux/memblock.h>
+#include <linux/power_supply.h>
+#if defined(CONFIG_S5P_MEM_CMA)
+#include <linux/cma.h>
+#endif
+#ifdef CONFIG_ANDROID_PMEM
+#include <linux/android_pmem.h>
+#endif
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <video/platform_lcd.h>
+
+#include <plat/regs-serial.h>
+#include <plat/regs-srom.h>
+#include <plat/exynos4.h>
+#include <plat/clock.h>
+#include <plat/hwmon.h>
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/fb-s5p.h>
+#include <plat/fimc.h>
+#include <plat/csis.h>
+#include <plat/gpio-cfg.h>
+#include <plat/adc.h>
+#include <plat/ts.h>
+#include <plat/keypad.h>
+#include <plat/sdhci.h>
+#include <plat/mshci.h>
+#include <plat/iic.h>
+#include <plat/sysmmu.h>
+#include <plat/pd.h>
+#include <plat/regs-fb-v4.h>
+#include <plat/media.h>
+#include <plat/udc-hs.h>
+#include <plat/s5p-clock.h>
+#include <plat/tvout.h>
+#include <plat/fimg2d.h>
+#include <plat/ehci.h>
+#include <plat/usbgadget.h>
+
+#ifdef CONFIG_S3C64XX_DEV_SPI
+#include <plat/s3c64xx-spi.h>
+#endif
+
+#include <mach/map.h>
+#include <mach/exynos-clock.h>
+#include <mach/media.h>
+#include <plat/regs-fb.h>
+
+#include <mach/dev-sysmmu.h>
+#include <mach/dev.h>
+#include <mach/regs-clock.h>
+#include <mach/exynos-ion.h>
+
+#ifdef CONFIG_FB_S5P_MIPI_DSIM
+#include <mach/mipi_ddi.h>
+#include <mach/dsim.h>
+#include <plat/fb-s5p.h>
+#endif
+
+#if defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC) || defined(CONFIG_VIDEO_MFC5X)
+#include <plat/s5p-mfc.h>
+#endif
+
+#ifdef CONFIG_S3C64XX_DEV_SPI
+#include <mach/spi-clocks.h>
+#endif
+
+#ifdef CONFIG_VIDEO_M5MO
+#include <media/m5mo_platform.h>
+#endif
+#ifdef CONFIG_VIDEO_S5K5BAFX
+#include <media/s5k5bafx_platform.h>
+#endif
+
+#if defined(CONFIG_EXYNOS4_SETUP_THERMAL)
+#include <plat/s5p-tmu.h>
+#include <mach/regs-tmu.h>
+#endif
+
+#ifdef CONFIG_SEC_DEV_JACK
+#include <linux/sec_jack.h>
+#endif
+
+#ifdef CONFIG_BT_BCM4330
+#include <mach/board-bluetooth-bcm.h>
+#endif
+
+#ifdef CONFIG_FB_S5P_LD9040
+#include <linux/ld9040.h>
+#endif
+
+#ifdef CONFIG_FB_S5P_MDNIE
+#include <linux/mdnie.h>
+#endif
+
+#include <../../../drivers/video/samsung/s3cfb.h>
+#include "u1.h"
+
+#include <mach/sec_debug.h>
+
+#ifdef	CONFIG_SAMSUNG_MHL
+#include <linux/irq.h>
+#include <linux/sii9234.h>
+#endif
+
+#ifdef CONFIG_BATTERY_SEC_U1
+#include <linux/power/sec_battery_u1.h>
+#endif
+
+#ifdef CONFIG_SEC_THERMISTOR
+#include <mach/sec_thermistor.h>
+#endif
+
+#ifdef CONFIG_BATTERY_MAX17042_FUELGAUGE_U1
+#include <linux/power/max17042_fuelgauge_u1.h>
+#endif
+
+#ifdef CONFIG_CHARGER_MAX8922_U1
+#include <linux/power/max8922_charger_u1.h>
+#endif
+
+#ifdef CONFIG_SMB136_CHARGER_Q1
+#include <linux/power/smb136_charger_q1.h>
+#endif
+
+#ifdef CONFIG_SMB328_CHARGER
+#include <linux/power/smb328_charger.h>
+#endif
+
+#ifdef CONFIG_USB_HOST_NOTIFY
+#include <linux/host_notify.h>
+#endif
+
+#ifdef CONFIG_EPEN_WACOM_G5SP
+#include <linux/wacom_i2c.h>
+static struct wacom_g5_callbacks *wacom_callbacks;
+#endif /* CONFIG_EPEN_WACOM_G5SP */
+
+#ifdef CONFIG_KEYBOARD_CYPRESS_TOUCH
+#include <linux/i2c/touchkey_i2c.h>
+#endif
+
+
+#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE)
+#include <mach/tdmb_pdata.h>
+#endif
+
+#ifdef CONFIG_LEDS_MAX8997
+#include <linux/leds-max8997.h>
+#endif
+
+#if defined(CONFIG_PHONE_IPC_SPI)
+#include <linux/phone_svn/ipc_spi.h>
+#include <linux/irq.h>
+#endif
+
+/* Following are default values for UCON, ULCON and UFCON UART registers */
+#define SMDKC210_UCON_DEFAULT	(S3C2410_UCON_TXILEVEL |	\
+				 S3C2410_UCON_RXILEVEL |	\
+				 S3C2410_UCON_TXIRQMODE |	\
+				 S3C2410_UCON_RXIRQMODE |	\
+				 S3C2410_UCON_RXFIFO_TOI |	\
+				 S3C2443_UCON_RXERR_IRQEN)
+
+#define SMDKC210_ULCON_DEFAULT	S3C2410_LCON_CS8
+
+#define SMDKC210_UFCON_DEFAULT	(S3C2410_UFCON_FIFOMODE |	\
+				 S5PV210_UFCON_TXTRIG4 |	\
+				 S5PV210_UFCON_RXTRIG4)
+
+static struct s3c2410_uartcfg smdkc210_uartcfgs[] __initdata = {
+	[0] = {
+		.hwport = 0,
+		.flags = 0,
+		.ucon = SMDKC210_UCON_DEFAULT,
+		.ulcon = SMDKC210_ULCON_DEFAULT,
+		.ufcon = SMDKC210_UFCON_DEFAULT,
+#ifdef CONFIG_BT_BCM4330
+		.wake_peer = bcm_bt_lpm_exit_lpm_locked,
+#endif
+	},
+	[1] = {
+		.hwport = 1,
+		.flags = 0,
+		.ucon = SMDKC210_UCON_DEFAULT,
+		.ulcon = SMDKC210_ULCON_DEFAULT,
+		.ufcon = SMDKC210_UFCON_DEFAULT,
+		.set_runstate = set_gps_uart_op,
+	},
+	[2] = {
+		.hwport = 2,
+		.flags = 0,
+		.ucon = SMDKC210_UCON_DEFAULT,
+		.ulcon = SMDKC210_ULCON_DEFAULT,
+		.ufcon = SMDKC210_UFCON_DEFAULT,
+	},
+	[3] = {
+		.hwport = 3,
+		.flags = 0,
+		.ucon = SMDKC210_UCON_DEFAULT,
+		.ulcon = SMDKC210_ULCON_DEFAULT,
+		.ufcon = SMDKC210_UFCON_DEFAULT,
+	},
+};
+
+#define WRITEBACK_ENABLED
+
+#ifdef CONFIG_VIDEO_FIMC
+/*
+ * External camera reset
+ * Because the most of cameras take i2c bus signal, so that
+ * you have to reset at the boot time for other i2c slave devices.
+ * This function also called at fimc_init_camera()
+ * Do optimization for cameras on your platform.
+ */
+
+#ifdef CONFIG_VIDEO_M5MO
+#define CAM_CHECK_ERR_RET(x, msg)					\
+	if (unlikely((x) < 0)) {					\
+		printk(KERN_ERR "\nfail to %s: err = %d\n", msg, x);	\
+		return x;						\
+	}
+#define CAM_CHECK_ERR(x, msg)						\
+	if (unlikely((x) < 0)) {					\
+		printk(KERN_ERR "\nfail to %s: err = %d\n", msg, x);	\
+	}
+
+static int m5mo_get_i2c_busnum(void)
+{
+#ifdef CONFIG_VIDEO_M5MO_USE_SWI2C
+	return 25;
+#else
+	return 0;
+#endif
+}
+
+static int m5mo_power_on(void)
+{
+	struct regulator *regulator;
+	int ret = 0;
+
+	printk(KERN_DEBUG "%s: in\n", __func__);
+
+	ret = gpio_request(GPIO_CAM_VGA_nSTBY, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "faile to request gpio(GPIO_CAM_VGA_nSTBY)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_CAM_VGA_nRST, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "faile to request gpio(GPIO_CAM_VGA_nRST)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_CAM_SENSOR_CORE, "GPE2");
+	if (ret) {
+		printk(KERN_ERR "fail to request gpio(CAM_SENSOR_CORE)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_CAM_IO_EN, "GPE2");
+	if (ret) {
+		printk(KERN_ERR "fail to request gpio(CAM_IO_EN)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_VT_CAM_15V, "GPE2");
+	if (ret) {
+		printk(KERN_ERR "faile to request gpio(GPIO_VT_CAM_15V)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_ISP_RESET, "ISP_RESET");
+	if (ret) {
+		printk(KERN_ERR "faile to request gpio(ISP_RESET)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_8M_AF_EN, "GPK1");
+	if (ret) {
+		printk(KERN_ERR "fail to request gpio(8M_AF_EN)\n");
+		return ret;
+	}
+
+	/* CAM_VT_nSTBY low */
+	ret = gpio_direction_output(GPIO_CAM_VGA_nSTBY, 0);
+	CAM_CHECK_ERR_RET(ret, "output VGA_nSTBY");
+
+	/* CAM_VT_nRST	low */
+	gpio_direction_output(GPIO_CAM_VGA_nRST, 0);
+	CAM_CHECK_ERR_RET(ret, "output VGA_nRST");
+	udelay(10);
+
+	/* CAM_ISP_CORE_1.2V */
+	regulator = regulator_get(NULL, "cam_isp_core");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "enable cam_isp_core");
+	/* No delay */
+
+	/* CAM_SENSOR_CORE_1.2V */
+	ret = gpio_direction_output(GPIO_CAM_SENSOR_CORE, 1);
+	CAM_CHECK_ERR_RET(ret, "output senser_core");
+
+#if defined(CONFIG_MACH_Q1_BD)
+	udelay(120);
+#else
+	udelay(10);
+#endif
+
+	/* CAM_SENSOR_A2.8V */
+	ret = gpio_direction_output(GPIO_CAM_IO_EN, 1);
+	CAM_CHECK_ERR_RET(ret, "output IO_EN");
+	/* it takes about 100us at least during level transition. */
+	udelay(160);		/* 130us -> 160us */
+
+	/* VT_CORE_1.5V */
+	ret = gpio_direction_output(GPIO_VT_CAM_15V, 1);
+	CAM_CHECK_ERR_RET(ret, "output VT_CAM_1.5V");
+	udelay(20);
+
+#if defined(CONFIG_MACH_Q1_BD)
+	udelay(120);
+#endif
+
+	/* CAM_AF_2.8V */
+	ret = gpio_direction_output(GPIO_8M_AF_EN, 1);
+	CAM_CHECK_ERR(ret, "output AF");
+	mdelay(7);
+
+	/* VT_CAM_1.8V */
+	regulator = regulator_get(NULL, "vt_cam_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "enable vt_1.8v");
+	udelay(10);
+
+	/* CAM_ISP_1.8V */
+	regulator = regulator_get(NULL, "cam_isp");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "enable cam_isp");
+	udelay(120);		/* at least */
+
+	/* CAM_SENSOR_IO_1.8V */
+	regulator = regulator_get(NULL, "cam_sensor_io");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "enable sensor_io");
+	udelay(30);
+
+	/* MCLK */
+	ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_SFN(2));
+	CAM_CHECK_ERR_RET(ret, "cfg mclk");
+	s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_NONE);
+	udelay(70);
+
+	/* ISP_RESET */
+	ret = gpio_direction_output(GPIO_ISP_RESET, 1);
+	CAM_CHECK_ERR_RET(ret, "output reset");
+	mdelay(4);
+
+	gpio_free(GPIO_CAM_VGA_nSTBY);
+	gpio_free(GPIO_CAM_VGA_nRST);
+	gpio_free(GPIO_CAM_SENSOR_CORE);
+	gpio_free(GPIO_CAM_IO_EN);
+	gpio_free(GPIO_VT_CAM_15V);
+	gpio_free(GPIO_ISP_RESET);
+	gpio_free(GPIO_8M_AF_EN);
+	printk(KERN_DEBUG "%s: out\n", __func__);
+
+	return ret;
+}
+#ifdef	CONFIG_SAMSUNG_MHL
+
+
+static void sii9234_cfg_gpio(void)
+{
+	printk(KERN_INFO "%s()\n", __func__);
+
+	s3c_gpio_cfgpin(GPIO_AP_SDA_18V, S3C_GPIO_SFN(0x0));
+	s3c_gpio_setpull(GPIO_AP_SDA_18V, S3C_GPIO_PULL_NONE);
+
+	s3c_gpio_cfgpin(GPIO_AP_SCL_18V, S3C_GPIO_SFN(0x1));
+	s3c_gpio_setpull(GPIO_AP_SCL_18V, S3C_GPIO_PULL_NONE);
+
+	s3c_gpio_cfgpin(GPIO_MHL_WAKE_UP, S3C_GPIO_INPUT);
+	irq_set_irq_type(MHL_WAKEUP_IRQ, IRQ_TYPE_EDGE_RISING);
+	s3c_gpio_setpull(GPIO_MHL_WAKE_UP, S3C_GPIO_PULL_DOWN);
+
+	gpio_request(GPIO_MHL_INT, "MHL_INT");
+	s5p_register_gpio_interrupt(GPIO_MHL_INT);
+	s3c_gpio_setpull(GPIO_MHL_INT, S3C_GPIO_PULL_DOWN);
+	irq_set_irq_type(MHL_INT_IRQ, IRQ_TYPE_EDGE_RISING);
+	s3c_gpio_cfgpin(GPIO_MHL_INT, GPIO_MHL_INT_AF);
+
+#ifdef CONFIG_TARGET_LOCALE_KOR
+	s3c_gpio_cfgpin(GPIO_HDMI_EN, S3C_GPIO_OUTPUT);
+	gpio_set_value(GPIO_HDMI_EN, GPIO_LEVEL_LOW);
+	s3c_gpio_setpull(GPIO_HDMI_EN, S3C_GPIO_PULL_NONE);
+#else
+	if (system_rev < 7) {
+		s3c_gpio_cfgpin(GPIO_HDMI_EN, S3C_GPIO_OUTPUT);
+		gpio_set_value(GPIO_HDMI_EN, GPIO_LEVEL_LOW);
+		s3c_gpio_setpull(GPIO_HDMI_EN, S3C_GPIO_PULL_NONE);
+	} else {
+		s3c_gpio_cfgpin(GPIO_HDMI_EN_REV07, S3C_GPIO_OUTPUT);
+		gpio_set_value(GPIO_HDMI_EN_REV07, GPIO_LEVEL_LOW);
+		s3c_gpio_setpull(GPIO_HDMI_EN_REV07, S3C_GPIO_PULL_NONE);
+	}
+#endif
+
+	s3c_gpio_cfgpin(GPIO_MHL_RST, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_MHL_RST, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_MHL_RST, GPIO_LEVEL_LOW);
+
+	s3c_gpio_cfgpin(GPIO_MHL_SEL, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_MHL_SEL, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_MHL_SEL, GPIO_LEVEL_LOW);
+
+}
+
+void sii9234_power_onoff(bool on)
+{
+	pr_info("%s(%d)\n", __func__, on);
+
+	if (on) {
+		/*s3c_gpio_cfgpin(GPIO_HDMI_EN,S3C_GPIO_OUTPUT);*/
+#ifdef CONFIG_TARGET_LOCALE_KOR
+		gpio_set_value(GPIO_HDMI_EN, GPIO_LEVEL_HIGH);
+#else
+		if (system_rev < 7)
+			gpio_set_value(GPIO_HDMI_EN, GPIO_LEVEL_HIGH);
+		else
+			gpio_set_value(GPIO_HDMI_EN_REV07, GPIO_LEVEL_HIGH);
+#endif
+
+		s3c_gpio_setpull(GPIO_AP_SCL_18V, S3C_GPIO_PULL_DOWN);
+		s3c_gpio_setpull(GPIO_AP_SCL_18V, S3C_GPIO_PULL_NONE);
+
+	} else {
+		gpio_set_value(GPIO_MHL_RST, GPIO_LEVEL_LOW);
+		usleep_range(10000, 20000);
+		gpio_set_value(GPIO_MHL_RST, GPIO_LEVEL_HIGH);
+#ifdef CONFIG_TARGET_LOCALE_KOR
+		gpio_set_value(GPIO_HDMI_EN, GPIO_LEVEL_HIGH);
+#else
+		if (system_rev < 7)
+			gpio_set_value(GPIO_HDMI_EN, GPIO_LEVEL_LOW);
+		else
+			gpio_set_value(GPIO_HDMI_EN_REV07, GPIO_LEVEL_LOW);
+#endif
+		gpio_set_value(GPIO_MHL_RST, GPIO_LEVEL_LOW);
+	}
+	pr_info("[MHL]%s : %d\n", __func__, on);
+}
+
+void sii9234_reset(void)
+{
+	s3c_gpio_cfgpin(GPIO_MHL_RST, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_MHL_RST, S3C_GPIO_PULL_NONE);
+
+	gpio_set_value(GPIO_MHL_RST, GPIO_LEVEL_LOW);
+	usleep_range(10000, 20000);
+	gpio_set_value(GPIO_MHL_RST, GPIO_LEVEL_HIGH);
+
+}
+
+void mhl_usb_switch_control(bool on)
+{
+	pr_info("%s() [MHL] USB path change : %s\n",
+			__func__, on ? "MHL" : "USB");
+	if (on == 1) {
+		if (gpio_get_value(GPIO_MHL_SEL))
+			pr_info("[MHL] GPIO_MHL_SEL :already 1\n");
+		else {
+			gpio_set_value(GPIO_MHL_SEL, GPIO_LEVEL_HIGH);
+			/* sii9234_cfg_power(1);	// onegun */
+			/* sii9234_init();		// onegun */
+		}
+	} else {
+		if (!gpio_get_value(GPIO_MHL_SEL))
+			pr_info("[MHL]	GPIO_MHL_SEL :already0\n");
+		else {
+			/* sii9234_cfg_power(0);	// onegun */
+			gpio_set_value(GPIO_MHL_SEL, GPIO_LEVEL_LOW);
+		}
+	}
+}
+
+static struct sii9234_platform_data sii9234_pdata = {
+	.init = sii9234_cfg_gpio,
+	.mhl_sel = mhl_usb_switch_control,
+	.hw_onoff = sii9234_power_onoff,
+	.hw_reset = sii9234_reset,
+	.enable_vbus = NULL,
+	.vbus_present = NULL,
+};
+
+static struct i2c_board_info __initdata tuna_i2c15_boardinfo[] = {
+	{
+		I2C_BOARD_INFO("sii9234_mhl_tx", 0x72>>1),
+		.platform_data = &sii9234_pdata,
+	},
+	{
+		I2C_BOARD_INFO("sii9234_tpi", 0x7A>>1),
+		.platform_data = &sii9234_pdata,
+	},
+	{
+		I2C_BOARD_INFO("sii9234_hdmi_rx", 0x92>>1),
+		.platform_data = &sii9234_pdata,
+	},
+	{
+		I2C_BOARD_INFO("sii9234_cbus", 0xC8>>1),
+		.platform_data = &sii9234_pdata,
+	},
+};
+
+#define I2C_BUS_ID_MHL	15
+static struct i2c_gpio_platform_data gpio_i2c_data15 = {
+	.sda_pin = GPIO_MHL_SDA_18V,
+	.scl_pin = GPIO_MHL_SCL_18V,
+	.udelay = 2,
+	.sda_is_open_drain	= 0,
+	.scl_is_open_drain	= 0,
+	.scl_is_output_only	= 0,
+};
+
+struct platform_device s3c_device_i2c15 = {
+	.name = "i2c-gpio",
+	.id = I2C_BUS_ID_MHL,
+	.dev = {
+		.platform_data = &gpio_i2c_data15,
+	}
+};
+
+#endif
+
+static int m5mo_power_down(void)
+{
+	struct regulator *regulator;
+	int ret = 0;
+
+	printk(KERN_DEBUG "%s: in\n", __func__);
+
+	ret = gpio_request(GPIO_8M_AF_EN, "GPK1");
+	if (ret) {
+		printk(KERN_ERR "fail to request gpio(8M_AF_EN)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_ISP_RESET, "ISP_RESET");
+	if (ret) {
+		printk(KERN_ERR "faile to request gpio(ISP_RESET)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_CAM_IO_EN, "GPE2");
+	if (ret) {
+		printk(KERN_ERR "fail to request gpio(GPIO_CAM_IO_EN)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_CAM_SENSOR_CORE, "GPE2");
+	if (ret) {
+		printk(KERN_ERR "fail to request gpio(CAM_SENSOR_COR)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_VT_CAM_15V, "GPE2");
+	if (ret) {
+		printk(KERN_ERR "faile to request gpio(GPIO_VT_CAM_15V)\n");
+		return ret;
+	}
+
+	/* s3c_i2c0_force_stop(); */
+
+	mdelay(3);
+
+	/* ISP_RESET */
+	ret = gpio_direction_output(GPIO_ISP_RESET, 0);
+	CAM_CHECK_ERR(ret, "output reset");
+#ifdef CONFIG_TARGET_LOCALE_KOR
+	mdelay(3);		/* fix without seeing signal form for kor. */
+#else
+	mdelay(2);
+#endif
+
+	/* MCLK */
+	ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_DOWN);
+	CAM_CHECK_ERR(ret, "cfg mclk");
+	udelay(20);
+
+	/* CAM_AF_2.8V */
+	/* 8M_AF_2.8V_EN */
+	ret = gpio_direction_output(GPIO_8M_AF_EN, 0);
+	CAM_CHECK_ERR(ret, "output AF");
+
+	/* CAM_SENSOR_IO_1.8V */
+	regulator = regulator_get(NULL, "cam_sensor_io");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "disable, sensor_io");
+	udelay(10);
+
+	/* CAM_ISP_1.8V */
+	regulator = regulator_get(NULL, "cam_isp");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "disable cam_isp");
+	udelay(500);		/* 100us -> 500us */
+
+	/* VT_CAM_1.8V */
+	regulator = regulator_get(NULL, "vt_cam_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "disable vt_1.8v");
+	udelay(250);		/* 10us -> 250us */
+
+	/* VT_CORE_1.5V */
+	ret = gpio_direction_output(GPIO_VT_CAM_15V, 0);
+	CAM_CHECK_ERR(ret, "output VT_CAM_1.5V");
+	udelay(300);		/*10 -> 300 us */
+
+	/* CAM_SENSOR_A2.8V */
+	ret = gpio_direction_output(GPIO_CAM_IO_EN, 0);
+	CAM_CHECK_ERR(ret, "output IO_EN");
+	udelay(800);
+
+	/* CAM_SENSOR_CORE_1.2V */
+	ret = gpio_direction_output(GPIO_CAM_SENSOR_CORE, 0);
+	CAM_CHECK_ERR(ret, "output SENSOR_CORE");
+	udelay(5);
+
+	/* CAM_ISP_CORE_1.2V */
+	regulator = regulator_get(NULL, "cam_isp_core");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "disable isp_core");
+
+#if defined(CONFIG_MACH_Q1_BD)
+	mdelay(250);
+#endif
+
+	gpio_free(GPIO_8M_AF_EN);
+	gpio_free(GPIO_ISP_RESET);
+	gpio_free(GPIO_CAM_IO_EN);
+	gpio_free(GPIO_CAM_SENSOR_CORE);
+	gpio_free(GPIO_VT_CAM_15V);
+
+	return ret;
+}
+
+int s3c_csis_power(int enable)
+{
+	struct regulator *regulator;
+	int ret = 0;
+	printk(KERN_DEBUG "%s: in\n", __func__);
+
+	/* mipi_1.1v ,mipi_1.8v are always powered-on.
+	 * If they are off, we then power them on.
+	 */
+	if (enable) {
+		/* VMIPI_1.1V */
+		regulator = regulator_get(NULL, "vmipi_1.1v");
+		if (IS_ERR(regulator))
+			goto error_out;
+		if (!regulator_is_enabled(regulator)) {
+			printk(KERN_WARNING "%s: vmipi_1.1v is off. so ON\n",
+			       __func__);
+			ret = regulator_enable(regulator);
+			CAM_CHECK_ERR(ret, "enable vmipi_1.1v");
+		}
+		regulator_put(regulator);
+
+		/* VMIPI_1.8V */
+		regulator = regulator_get(NULL, "vmipi_1.8v");
+		if (IS_ERR(regulator))
+			goto error_out;
+		if (!regulator_is_enabled(regulator)) {
+			printk(KERN_WARNING "%s: vmipi_1.8v is off. so ON\n",
+			       __func__);
+			ret = regulator_enable(regulator);
+			CAM_CHECK_ERR(ret, "enable vmipi_1.8v");
+		}
+		regulator_put(regulator);
+	}
+	printk(KERN_DEBUG "%s: out\n", __func__);
+
+	return 0;
+
+error_out:
+	printk(KERN_ERR "%s: ERROR: failed to check mipi-power\n", __func__);
+	return 0;
+}
+
+#if defined(CONFIG_MACH_Q1_BD)
+static bool is_torch;
+#endif
+
+static int m5mo_flash_power(int enable)
+{
+	struct regulator *flash = regulator_get(NULL, "led_flash");
+	struct regulator *movie = regulator_get(NULL, "led_movie");
+
+	if (enable) {
+
+#if defined(CONFIG_MACH_Q1_BD)
+		if (regulator_is_enabled(movie)) {
+			printk(KERN_DEBUG "%s: m5mo_torch set~~~~", __func__);
+			is_torch = true;
+			goto torch_exit;
+		}
+		is_torch = false;
+#endif
+		regulator_set_current_limit(flash, 490000, 530000);
+		regulator_enable(flash);
+		regulator_set_current_limit(movie, 90000, 110000);
+		regulator_enable(movie);
+	} else {
+
+#if defined(CONFIG_MACH_Q1_BD)
+		if (is_torch)
+			goto torch_exit;
+#endif
+
+		if (regulator_is_enabled(flash))
+			regulator_disable(flash);
+		if (regulator_is_enabled(movie))
+			regulator_disable(movie);
+	}
+torch_exit:
+	regulator_put(flash);
+	regulator_put(movie);
+
+	return 0;
+}
+
+static int m5mo_power(int enable)
+{
+	int ret = 0;
+
+	printk(KERN_DEBUG "%s %s\n", __func__, enable ? "on" : "down");
+	if (enable) {
+		ret = m5mo_power_on();
+		if (unlikely(ret))
+			goto error_out;
+	} else
+		ret = m5mo_power_down();
+
+	ret = s3c_csis_power(enable);
+	m5mo_flash_power(enable);
+
+error_out:
+	return ret;
+}
+
+static int m5mo_config_isp_irq(void)
+{
+	s3c_gpio_cfgpin(GPIO_ISP_INT, S3C_GPIO_SFN(0xF));
+	s3c_gpio_setpull(GPIO_ISP_INT, S3C_GPIO_PULL_NONE);
+	return 0;
+}
+
+static struct m5mo_platform_data m5mo_plat = {
+	.default_width = 640,	/* 1920 */
+	.default_height = 480,	/* 1080 */
+	.pixelformat = V4L2_PIX_FMT_UYVY,
+	.freq = 24000000,
+	.is_mipi = 1,
+	.config_isp_irq = m5mo_config_isp_irq,
+	.irq = IRQ_EINT(13),
+};
+
+static struct i2c_board_info m5mo_i2c_info = {
+	I2C_BOARD_INFO("M5MO", 0x1F),
+	.platform_data = &m5mo_plat,
+};
+
+static struct s3c_platform_camera m5mo = {
+	.id = CAMERA_CSI_C,
+	.clk_name = "sclk_cam0",
+	.get_i2c_busnum = m5mo_get_i2c_busnum,
+	.cam_power = m5mo_power,	/*smdkv310_mipi_cam0_reset, */
+	.type = CAM_TYPE_MIPI,
+	.fmt = ITU_601_YCBCR422_8BIT,	/*MIPI_CSI_YCBCR422_8BIT */
+	.order422 = CAM_ORDER422_8BIT_CBYCRY,
+	.info = &m5mo_i2c_info,
+	.pixelformat = V4L2_PIX_FMT_UYVY,
+	.srclk_name = "xusbxti",	/* "mout_mpll" */
+	.clk_rate = 24000000,	/* 48000000 */
+	.line_length = 1920,
+	.width = 640,
+	.height = 480,
+	.window = {
+		.left = 0,
+		.top = 0,
+		.width = 640,
+		.height = 480,
+	},
+
+	.mipi_lanes = 2,
+	.mipi_settle = 12,
+	.mipi_align = 32,
+
+	/* Polarity */
+	.inv_pclk = 0,
+	.inv_vsync = 1,
+	.inv_href = 0,
+	.inv_hsync = 0,
+	.reset_camera = 0,
+	.initialized = 0,
+};
+#endif				/* #ifdef CONFIG_VIDEO_M5MO */
+
+#ifdef CONFIG_VIDEO_S5K5BAFX
+static int s5k5bafx_get_i2c_busnum(void)
+{
+	return 12;
+}
+
+static int s5k5bafx_power_on(void)
+{
+	struct regulator *regulator;
+	int ret = 0;
+
+	/* printk("%s: in\n", __func__); */
+
+	ret = gpio_request(GPIO_ISP_RESET, "ISP_RESET");
+	if (ret) {
+		printk(KERN_ERR "faile to request gpio(ISP_RESET)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_CAM_IO_EN, "GPE2");
+	if (ret) {
+		printk(KERN_ERR "faile to request gpio(GPIO_CAM_IO_EN)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_VT_CAM_15V, "GPE2");
+	if (ret) {
+		printk(KERN_ERR "faile to request gpio(GPIO_VT_CAM_15V)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_CAM_VGA_nSTBY, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "faile to request gpio(GPIO_CAM_VGA_nSTBY)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_CAM_VGA_nRST, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "faile to request gpio(GPIO_CAM_VGA_nRST)\n");
+		return ret;
+	}
+
+#ifndef CONFIG_MACH_U1_KOR_LGT
+	if (system_rev >= 9) {
+#endif
+		s3c_gpio_setpull(VT_CAM_SDA_18V, S3C_GPIO_PULL_NONE);
+		s3c_gpio_setpull(VT_CAM_SCL_18V, S3C_GPIO_PULL_NONE);
+#ifndef CONFIG_MACH_U1_KOR_LGT
+	}
+#endif
+
+	/* ISP_RESET low */
+	ret = gpio_direction_output(GPIO_ISP_RESET, 0);
+	CAM_CHECK_ERR_RET(ret, "output reset");
+	udelay(100);
+
+	/* CAM_ISP_CORE_1.2V */
+	regulator = regulator_get(NULL, "cam_isp_core");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "enable isp_core");
+	udelay(10);
+
+	/* CAM_SENSOR_A2.8V */
+	ret = gpio_direction_output(GPIO_CAM_IO_EN, 1);
+	CAM_CHECK_ERR_RET(ret, "output io_en");
+	udelay(300);		/* don't change me */
+
+	/* VT_CORE_1.5V */
+	ret = gpio_direction_output(GPIO_VT_CAM_15V, 1);
+	CAM_CHECK_ERR_RET(ret, "output vt_15v");
+	udelay(100);
+
+	/* CAM_ISP_1.8V */
+	regulator = regulator_get(NULL, "cam_isp");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "enable cam_isp");
+	udelay(10);
+
+	/* VT_CAM_1.8V */
+	regulator = regulator_get(NULL, "vt_cam_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "enable vt_1.8v");
+	udelay(10);
+
+	/* CAM_VGA_nSTBY */
+	ret = gpio_direction_output(GPIO_CAM_VGA_nSTBY, 1);
+	CAM_CHECK_ERR_RET(ret, "output VGA_nSTBY");
+	udelay(50);
+
+	/* Mclk */
+	ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_SFN(2));
+	s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_NONE);
+	CAM_CHECK_ERR_RET(ret, "cfg mclk");
+	udelay(100);
+
+	/* CAM_VGA_nRST	 */
+	ret = gpio_direction_output(GPIO_CAM_VGA_nRST, 1);
+	CAM_CHECK_ERR_RET(ret, "output VGA_nRST");
+	mdelay(2);
+
+	gpio_free(GPIO_ISP_RESET);
+	gpio_free(GPIO_CAM_IO_EN);
+	gpio_free(GPIO_VT_CAM_15V);
+	gpio_free(GPIO_CAM_VGA_nSTBY);
+	gpio_free(GPIO_CAM_VGA_nRST);
+
+	return 0;
+}
+
+static int s5k5bafx_power_off(void)
+{
+	struct regulator *regulator;
+	int ret = 0;
+
+	/* printk("n%s: in\n", __func__); */
+
+	ret = gpio_request(GPIO_CAM_VGA_nRST, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "faile to request gpio(GPIO_CAM_VGA_nRST)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_CAM_VGA_nSTBY, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "faile to request gpio(GPIO_CAM_VGA_nSTBY)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_VT_CAM_15V, "GPE2");
+	if (ret) {
+		printk(KERN_ERR "faile to request gpio(GPIO_VT_CAM_15V)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_CAM_IO_EN, "GPE2");
+	if (ret) {
+		printk(KERN_ERR "faile to request gpio(GPIO_CAM_IO_EN)\n");
+		return ret;
+	}
+
+	/* CAM_VGA_nRST	 */
+	ret = gpio_direction_output(GPIO_CAM_VGA_nRST, 0);
+	CAM_CHECK_ERR(ret, "output VGA_nRST");
+	udelay(100);
+
+	/* Mclk */
+	ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_DOWN);
+	CAM_CHECK_ERR(ret, "cfg mclk");
+	udelay(20);
+
+	/* CAM_VGA_nSTBY */
+	ret = gpio_direction_output(GPIO_CAM_VGA_nSTBY, 0);
+	CAM_CHECK_ERR(ret, "output VGA_nSTBY");
+	udelay(20);
+
+	/* VT_CAM_1.8V */
+	regulator = regulator_get(NULL, "vt_cam_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "disable vt_1.8v");
+	udelay(10);
+
+	/* CAM_ISP_1.8V */
+	regulator = regulator_get(NULL, "cam_isp");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "disable cam_isp");
+	udelay(10);
+
+	/* VT_CORE_1.5V */
+	ret = gpio_direction_output(GPIO_VT_CAM_15V, 0);
+	CAM_CHECK_ERR(ret, "output vt_1.5v");
+	udelay(10);
+
+	/* CAM_SENSOR_A2.8V */
+	ret = gpio_direction_output(GPIO_CAM_IO_EN, 0);
+	CAM_CHECK_ERR(ret, "output io_en");
+	udelay(10);
+
+	/* CAM_ISP_CORE_1.2V */
+	regulator = regulator_get(NULL, "cam_isp_core");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "disable isp_core");
+
+#ifndef CONFIG_MACH_U1_KOR_LGT
+	if (system_rev >= 9) {
+#endif
+		gpio_direction_input(VT_CAM_SDA_18V);
+		s3c_gpio_setpull(VT_CAM_SDA_18V, S3C_GPIO_PULL_DOWN);
+		gpio_direction_input(VT_CAM_SCL_18V);
+		s3c_gpio_setpull(VT_CAM_SCL_18V, S3C_GPIO_PULL_DOWN);
+#ifndef CONFIG_MACH_U1_KOR_LGT
+	}
+#endif
+
+#if defined(CONFIG_MACH_Q1_BD)
+	mdelay(350);
+#endif
+
+	gpio_free(GPIO_CAM_VGA_nRST);
+	gpio_free(GPIO_CAM_VGA_nSTBY);
+	gpio_free(GPIO_VT_CAM_15V);
+	gpio_free(GPIO_CAM_IO_EN);
+
+	return 0;
+}
+
+static int s5k5bafx_power(int onoff)
+{
+	int ret = 0;
+#if defined(CONFIG_MACH_U1_KOR_LGT)
+	u32 cfg = 0;
+#endif
+	printk(KERN_INFO "%s(): %s\n", __func__, onoff ? "on" : "down");
+
+#if defined(CONFIG_MACH_U1_KOR_LGT)
+	cfg = readl(S5P_VA_GPIO2 + 0x002c);
+#endif
+
+	if (onoff) {
+
+#if defined(CONFIG_MACH_U1_KOR_LGT)
+		writel(cfg | 0x0080, S5P_VA_GPIO2 + 0x002c);
+#endif
+
+		ret = s5k5bafx_power_on();
+		if (unlikely(ret))
+			goto error_out;
+	} else {
+
+#if defined(CONFIG_MACH_U1_KOR_LGT)
+		writel(cfg & 0xff3f, S5P_VA_GPIO2 + 0x002c);
+#endif
+		ret = s5k5bafx_power_off();
+		/* s3c_i2c0_force_stop(); *//* DSLIM. Should be implemented */
+	}
+
+	ret = s3c_csis_power(onoff);
+
+error_out:
+	return ret;
+}
+
+static struct s5k5bafx_platform_data s5k5bafx_plat = {
+	.default_width = 640,
+	.default_height = 480,
+	.pixelformat = V4L2_PIX_FMT_UYVY,
+	.freq = 24000000,
+	.is_mipi = 1,
+};
+
+static struct i2c_board_info s5k5bafx_i2c_info = {
+	I2C_BOARD_INFO("S5K5BAFX", 0x5A >> 1),
+	.platform_data = &s5k5bafx_plat,
+};
+
+static struct s3c_platform_camera s5k5bafx = {
+	.id = CAMERA_CSI_D,
+	.type = CAM_TYPE_MIPI,
+	.fmt = ITU_601_YCBCR422_8BIT,
+	.order422 = CAM_ORDER422_8BIT_CBYCRY,
+	.mipi_lanes = 1,
+	.mipi_settle = 6,
+	.mipi_align = 32,
+
+	.get_i2c_busnum = s5k5bafx_get_i2c_busnum,
+	.info = &s5k5bafx_i2c_info,
+	.pixelformat = V4L2_PIX_FMT_UYVY,
+	.srclk_name = "xusbxti",
+	.clk_name = "sclk_cam0",
+	.clk_rate = 24000000,
+	.line_length = 640,
+	.width = 640,
+	.height = 480,
+	.window = {
+		.left = 0,
+		.top = 0,
+		.width = 640,
+		.height = 480,
+	},
+
+	/* Polarity */
+	.inv_pclk = 0,
+	.inv_vsync = 1,
+	.inv_href = 0,
+	.inv_hsync = 0,
+	.reset_camera = 0,
+	.initialized = 0,
+	.cam_power = s5k5bafx_power,
+};
+#endif
+
+#ifdef WRITEBACK_ENABLED
+static int get_i2c_busnum_writeback(void)
+{
+	return 0;
+}
+
+static struct i2c_board_info writeback_i2c_info = {
+	I2C_BOARD_INFO("WriteBack", 0x0),
+};
+
+static struct s3c_platform_camera writeback = {
+	.id = CAMERA_WB,
+	.fmt = ITU_601_YCBCR422_8BIT,
+	.order422 = CAM_ORDER422_8BIT_CBYCRY,
+	.get_i2c_busnum = get_i2c_busnum_writeback,
+	.info = &writeback_i2c_info,
+	.pixelformat = V4L2_PIX_FMT_YUV444,
+	.line_length = 800,
+	.width = 480,
+	.height = 800,
+	.window = {
+		.left = 0,
+		.top = 0,
+		.width = 480,
+		.height = 800,
+	},
+
+	.initialized = 0,
+};
+#endif
+
+void cam_cfg_gpio(struct platform_device *pdev)
+{
+	int ret = 0;
+	printk(KERN_INFO "\n\n\n%s: pdev->id=%d\n", __func__, pdev->id);
+
+	if (pdev->id != 0)
+		return;
+
+#ifdef CONFIG_VIDEO_S5K5BAFX
+#ifndef CONFIG_MACH_U1_KOR_LGT
+	if (system_rev >= 9) {
+#endif
+		/* Rev0.9 */
+		ret = gpio_direction_input(VT_CAM_SDA_18V);
+		CAM_CHECK_ERR(ret, "VT_CAM_SDA_18V");
+		s3c_gpio_setpull(VT_CAM_SDA_18V, S3C_GPIO_PULL_DOWN);
+
+		ret = gpio_direction_input(VT_CAM_SCL_18V);
+		CAM_CHECK_ERR(ret, "VT_CAM_SCL_18V");
+		s3c_gpio_setpull(VT_CAM_SCL_18V, S3C_GPIO_PULL_DOWN);
+#ifndef CONFIG_MACH_U1_KOR_LGT
+	}
+#endif
+#endif
+}
+
+/* Interface setting */
+static struct s3c_platform_fimc fimc_plat = {
+#ifdef CONFIG_ITU_A
+	.default_cam = CAMERA_PAR_A,
+#endif
+#ifdef CONFIG_ITU_B
+	.default_cam = CAMERA_PAR_B,
+#endif
+#ifdef CONFIG_CSI_C
+	.default_cam = CAMERA_CSI_C,
+#endif
+#ifdef CONFIG_CSI_D
+	.default_cam = CAMERA_CSI_D,
+#endif
+	.camera = {
+#ifdef CONFIG_VIDEO_M5MO
+		&m5mo,
+#endif
+#ifdef CONFIG_VIDEO_S5K5BAFX
+		&s5k5bafx,
+#endif
+#ifdef WRITEBACK_ENABLED
+		&writeback,
+#endif
+	},
+	.hw_ver = 0x51,
+	.cfg_gpio = cam_cfg_gpio,
+};
+#endif				/* CONFIG_VIDEO_FIMC */
+
+static DEFINE_MUTEX(notify_lock);
+
+#define DEFINE_MMC_CARD_NOTIFIER(num) \
+static void (*hsmmc##num##_notify_func)(struct platform_device *, int state); \
+static int ext_cd_init_hsmmc##num(void (*notify_func)( \
+			struct platform_device *, int state)) \
+{ \
+	mutex_lock(&notify_lock); \
+	WARN_ON(hsmmc##num##_notify_func); \
+	hsmmc##num##_notify_func = notify_func; \
+	mutex_unlock(&notify_lock); \
+	return 0; \
+} \
+static int ext_cd_cleanup_hsmmc##num(void (*notify_func)( \
+			struct platform_device *, int state)) \
+{ \
+	mutex_lock(&notify_lock); \
+	WARN_ON(hsmmc##num##_notify_func != notify_func); \
+	hsmmc##num##_notify_func = NULL; \
+	mutex_unlock(&notify_lock); \
+	return 0; \
+}
+
+#ifdef CONFIG_S3C_DEV_HSMMC3
+	DEFINE_MMC_CARD_NOTIFIER(3)
+#endif
+
+/*
+ * call this when you need sd stack to recognize insertion or removal of card
+ * that can't be told by SDHCI regs
+ */
+
+void mmc_force_presence_change(struct platform_device *pdev)
+{
+	void (*notify_func)(struct platform_device *, int state) = NULL;
+	mutex_lock(&notify_lock);
+#ifdef CONFIG_S3C_DEV_HSMMC3
+	printk("---------test logs pdev : %p s3c_device_hsmmc3 %p \n",
+		pdev, &s3c_device_hsmmc3);
+	if (pdev == &s3c_device_hsmmc3) {
+		notify_func = hsmmc3_notify_func;
+		printk("---------test logs notify_func : %p \n", notify_func);
+	}
+#endif
+
+	if (notify_func)
+		notify_func(pdev, 1);
+	else
+		pr_warn("%s: called for device with no notifier\n", __func__);
+	mutex_unlock(&notify_lock);
+}
+EXPORT_SYMBOL_GPL(mmc_force_presence_change);
+
+#ifdef CONFIG_S3C_DEV_HSMMC
+static struct s3c_sdhci_platdata exynos4_hsmmc0_pdata __initdata = {
+	.cd_type = S3C_SDHCI_CD_PERMANENT,
+	.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
+#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
+	.max_width = 8,
+	.host_caps = MMC_CAP_8_BIT_DATA,
+#endif
+};
+#endif
+
+#ifdef CONFIG_S3C_DEV_HSMMC2
+static struct s3c_sdhci_platdata exynos4_hsmmc2_pdata __initdata = {
+	.cd_type = S3C_SDHCI_CD_GPIO,
+	.ext_cd_gpio = EXYNOS4_GPX3(4),
+	.ext_cd_gpio_invert = 1,
+	.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
+	.vmmc_name = "vtf_2.8v",
+};
+#endif
+
+#ifdef CONFIG_S3C_DEV_HSMMC3
+static struct s3c_sdhci_platdata exynos4_hsmmc3_pdata __initdata = {
+/* For Wi-Fi */
+#if 0
+	.cd_type = S3C_SDHCI_CD_PERMANENT,
+	.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
+	.pm_flags = S3C_SDHCI_PM_IGNORE_SUSPEND_RESUME,
+#else
+	.cd_type = S3C_SDHCI_CD_EXTERNAL,
+	.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
+	.pm_flags = S3C_SDHCI_PM_IGNORE_SUSPEND_RESUME,
+	.ext_cd_init = ext_cd_init_hsmmc3,
+	.ext_cd_cleanup = ext_cd_cleanup_hsmmc3,
+#endif
+};
+#endif
+
+#ifdef CONFIG_EXYNOS4_DEV_MSHC
+static struct s3c_mshci_platdata exynos4_mshc_pdata __initdata = {
+	.cd_type = S3C_MSHCI_CD_PERMANENT,
+#if defined(CONFIG_EXYNOS4_MSHC_8BIT) &&	\
+	defined(CONFIG_EXYNOS4_MSHC_DDR)
+	.max_width = 8,
+	.host_caps = MMC_CAP_8_BIT_DATA | MMC_CAP_1_8V_DDR |
+			MMC_CAP_UHS_DDR50 | MMC_CAP_CMD23,
+#elif defined(CONFIG_EXYNOS4_MSHC_8BIT)
+	.max_width = 8,
+	.host_caps = MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
+#elif defined(CONFIG_EXYNOS4_MSHC_DDR)
+	.host_caps = MMC_CAP_1_8V_DDR | MMC_CAP_UHS_DDR50 |
+			MMC_CAP_CMD23,
+#endif
+	.int_power_gpio		= GPIO_XMMC0_CDn,
+};
+#endif
+
+#ifdef CONFIG_VIDEO_FIMG2D
+static struct fimg2d_platdata fimg2d_data __initdata = {
+	.hw_ver = 30,
+	.parent_clkname = "mout_g2d0",
+	.clkname = "sclk_fimg2d",
+	.gate_clkname = "fimg2d",
+	.clkrate = 267 * 1000000,	/* 266 Mhz */
+};
+#endif
+
+#ifdef CONFIG_FB_S3C
+#if defined(CONFIG_LCD_AMS369FG06)
+static int lcd_power_on(struct lcd_device *ld, int enable)
+{
+	return 1;
+}
+
+static int reset_lcd(struct lcd_device *ld)
+{
+	int err = 0;
+
+	err = gpio_request(EXYNOS4_GPX0(6), "GPX0");
+	if (err) {
+		printk(KERN_ERR "failed to request GPX0 for "
+		       "lcd reset control\n");
+		return err;
+	}
+
+	gpio_direction_output(EXYNOS4_GPX0(6), 1);
+	mdelay(100);
+
+	gpio_set_value(EXYNOS4_GPX0(6), 1);
+	mdelay(100);
+
+	gpio_free(EXYNOS4_GPX0(6));
+
+	return 1;
+}
+
+static struct lcd_platform_data ams369fg06_platform_data = {
+	.reset = reset_lcd,
+	.power_on = lcd_power_on,
+	.lcd_enabled = 0,
+	.reset_delay = 100,	/* 100ms */
+};
+
+#define		LCD_BUS_NUM	3
+#define		DISPLAY_CS	EXYNOS4_GPB(5)
+#define		DISPLAY_CLK	EXYNOS4_GPB(4)
+#define		DISPLAY_SI	EXYNOS4_GPB(7)
+
+static struct spi_board_info spi_board_info[] __initdata = {
+	{
+		.modalias = "ams369fg06",
+		.platform_data = (void *)&ams369fg06_platform_data,
+		.max_speed_hz = 1200000,
+		.bus_num = LCD_BUS_NUM,
+		.chip_select = 0,
+		.mode = SPI_MODE_3,
+		.controller_data = (void *)DISPLAY_CS,
+	}
+};
+
+static struct spi_gpio_platform_data ams369fg06_spi_gpio_data = {
+	.sck = DISPLAY_CLK,
+	.mosi = DISPLAY_SI,
+	.miso = -1,
+	.num_chipselect = 1,
+};
+
+static struct platform_device s3c_device_spi_gpio = {
+	.name = "spi_gpio",
+	.id = LCD_BUS_NUM,
+	.dev = {
+		.parent = &s5p_device_fimd0.dev,
+		.platform_data = &ams369fg06_spi_gpio_data,
+	},
+};
+
+static struct s3c_fb_pd_win smdkc210_fb_win0 = {
+	.win_mode = {
+		.left_margin = 9,
+		.right_margin = 9,
+		.upper_margin = 5,
+		.lower_margin = 5,
+		.hsync_len = 2,
+		.vsync_len = 2,
+		.xres = 480,
+		.yres = 800,
+	},
+	.virtual_x = 480,
+	.virtual_y = 1600,
+	.width = 48,
+	.height = 80,
+	.max_bpp = 32,
+	.default_bpp = 24,
+};
+
+static struct s3c_fb_pd_win smdkc210_fb_win1 = {
+	.win_mode = {
+		.left_margin = 9,
+		.right_margin = 9,
+		.upper_margin = 5,
+		.lower_margin = 5,
+		.hsync_len = 2,
+		.vsync_len = 2,
+		.xres = 480,
+		.yres = 800,
+	},
+	.virtual_x = 480,
+	.virtual_y = 1600,
+	.width = 48,
+	.height = 80,
+	.max_bpp = 32,
+	.default_bpp = 24,
+};
+
+static struct s3c_fb_pd_win smdkc210_fb_win2 = {
+	.win_mode = {
+		.left_margin = 9,
+		.right_margin = 9,
+		.upper_margin = 5,
+		.lower_margin = 5,
+		.hsync_len = 2,
+		.vsync_len = 2,
+		.xres = 480,
+		.yres = 800,
+	},
+	.virtual_x = 480,
+	.virtual_y = 1600,
+	.width = 48,
+	.height = 80,
+	.max_bpp = 32,
+	.default_bpp = 24,
+};
+
+#elif defined(CONFIG_LCD_WA101S)
+static void lcd_wa101s_set_power(struct plat_lcd_data *pd, unsigned int power)
+{
+	if (power) {
+#if !defined(CONFIG_BACKLIGHT_PWM)
+		gpio_request(EXYNOS4_GPD0(1), "GPD0");
+		gpio_direction_output(EXYNOS4_GPD0(1), 1);
+		gpio_free(EXYNOS4_GPD0(1));
+#endif
+	} else {
+#if !defined(CONFIG_BACKLIGHT_PWM)
+		gpio_request(EXYNOS4_GPD0(1), "GPD0");
+		gpio_direction_output(EXYNOS4_GPD0(1), 0);
+		gpio_free(EXYNOS4_GPD0(1));
+#endif
+	}
+}
+
+static struct plat_lcd_data smdkc210_lcd_wa101s_data = {
+	.set_power = lcd_wa101s_set_power,
+};
+
+static struct platform_device smdkc210_lcd_wa101s = {
+	.name = "platform-lcd",
+	.dev.parent = &s5p_device_fimd0.dev,
+	.dev.platform_data = &smdkc210_lcd_wa101s_data,
+};
+
+static struct s3c_fb_pd_win smdkc210_fb_win0 = {
+	.win_mode = {
+		.left_margin = 80,
+		.right_margin = 48,
+		.upper_margin = 14,
+		.lower_margin = 3,
+		.hsync_len = 32,
+		.vsync_len = 5,
+		.xres = 1366,
+		.yres = 768,
+	},
+	.virtual_x = 1366,
+	.virtual_y = 768 * 2,
+	.width = 223,
+	.height = 125,
+	.max_bpp = 32,
+	.default_bpp = 24,
+};
+
+#ifndef CONFIG_LCD_WA101S	/* temporarily disables window1 */
+static struct s3c_fb_pd_win smdkc210_fb_win1 = {
+	.win_mode = {
+		.left_margin = 80,
+		.right_margin = 48,
+		.upper_margin = 14,
+		.lower_margin = 3,
+		.hsync_len = 32,
+		.vsync_len = 5,
+		.xres = 1366,
+		.yres = 768,
+	},
+	.virtual_x = 1366,
+	.virtual_y = 768 * 2,
+	.max_bpp = 32,
+	.default_bpp = 24,
+};
+#endif
+
+#elif defined(CONFIG_LCD_LTE480WV)
+static void lcd_lte480wv_set_power(struct plat_lcd_data *pd, unsigned int power)
+{
+	if (power) {
+#if !defined(CONFIG_BACKLIGHT_PWM)
+		gpio_request(EXYNOS4_GPD0(1), "GPD0");
+		gpio_direction_output(EXYNOS4_GPD0(1), 1);
+		gpio_free(EXYNOS4_GPD0(1));
+#endif
+		/* fire nRESET on power up */
+		gpio_request(EXYNOS4_GPX0(6), "GPX0");
+
+		gpio_direction_output(EXYNOS4_GPX0(6), 1);
+		mdelay(100);
+
+		gpio_set_value(EXYNOS4_GPX0(6), 0);
+		mdelay(10);
+
+		gpio_set_value(EXYNOS4_GPX0(6), 1);
+		mdelay(10);
+
+		gpio_free(EXYNOS4_GPX0(6));
+	} else {
+#if !defined(CONFIG_BACKLIGHT_PWM)
+		gpio_request(EXYNOS4_GPD0(1), "GPD0");
+		gpio_direction_output(EXYNOS4_GPD0(1), 0);
+		gpio_free(EXYNOS4_GPD0(1));
+#endif
+	}
+}
+
+static struct plat_lcd_data smdkc210_lcd_lte480wv_data = {
+	.set_power = lcd_lte480wv_set_power,
+};
+
+static struct platform_device smdkc210_lcd_lte480wv = {
+	.name = "platform-lcd",
+	.dev.parent = &s5p_device_fimd0.dev,
+	.dev.platform_data = &smdkc210_lcd_lte480wv_data,
+};
+
+static struct s3c_fb_pd_win smdkc210_fb_win0 = {
+	.win_mode = {
+		.left_margin = 13,
+		.right_margin = 8,
+		.upper_margin = 7,
+		.lower_margin = 5,
+		.hsync_len = 3,
+		.vsync_len = 1,
+		.xres = 800,
+		.yres = 480,
+	},
+	.virtual_x = 800,
+	.virtual_y = 960,
+	.max_bpp = 32,
+	.default_bpp = 24,
+};
+
+static struct s3c_fb_pd_win smdkc210_fb_win1 = {
+	.win_mode = {
+		.left_margin = 13,
+		.right_margin = 8,
+		.upper_margin = 7,
+		.lower_margin = 5,
+		.hsync_len = 3,
+		.vsync_len = 1,
+		.xres = 800,
+		.yres = 480,
+	},
+	.virtual_x = 800,
+	.virtual_y = 960,
+	.max_bpp = 32,
+	.default_bpp = 24,
+};
+#endif
+
+static struct s3c_fb_platdata smdkc210_lcd0_pdata __initdata = {
+#if defined(CONFIG_LCD_AMS369FG06) || defined(CONFIG_LCD_WA101S) ||	\
+	defined(CONFIG_LCD_LTE480WV)
+	.win[0] = &smdkc210_fb_win0,
+#ifndef CONFIG_LCD_WA101S	/* temporarily disables window1 */
+	.win[1] = &smdkc210_fb_win1,
+#endif
+#endif
+	.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+#if defined(CONFIG_LCD_AMS369FG06)
+	.vidcon1 = VIDCON1_INV_VCLK | VIDCON1_INV_VDEN |
+	VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+#elif defined(CONFIG_LCD_WA101S)
+	.vidcon1 = VIDCON1_INV_VCLK | VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+#elif defined(CONFIG_LCD_LTE480WV)
+	.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+#endif
+	.setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
+};
+#endif
+
+#ifdef CONFIG_S3C64XX_DEV_SPI
+static struct s3c64xx_spi_csinfo spi0_csi[] = {
+	[0] = {
+		.line = EXYNOS4_GPB(1),
+		.set_level = gpio_set_value,
+		.fb_delay = 0x0,
+	},
+};
+
+static struct spi_board_info spi0_board_info[] __initdata = {
+#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE)
+	{
+		.modalias = "tdmbspi",
+		.platform_data = NULL,
+		.max_speed_hz = 5000000,
+		.bus_num = 0,
+		.chip_select = 0,
+		.mode = SPI_MODE_0,
+		.controller_data = &spi0_csi[0],
+	},
+#elif defined(CONFIG_ISDBT_FC8100)
+	{
+		.modalias	=	"isdbtspi",
+		.platform_data	=	NULL,
+		.max_speed_hz	=	400000,
+		.bus_num	=	0,
+		.chip_select	=	0,
+		.mode		=	(SPI_MODE_0|SPI_CS_HIGH),
+		.controller_data	=	&spi0_csi[0],
+	},
+
+#elif defined(CONFIG_PHONE_IPC_SPI)
+	{
+		.modalias = "ipc_spi",
+		.bus_num = 0,
+		.chip_select = 0,
+		.max_speed_hz = 12*1000*1000,
+		.mode = SPI_MODE_1,
+		.controller_data = &spi0_csi[0],
+	},
+#else
+	{
+		.modalias = "spidev",
+		.platform_data = NULL,
+		.max_speed_hz = 10 * 1000 * 1000,
+		.bus_num = 0,
+		.chip_select = 0,
+		.mode = SPI_MODE_0,
+		.controller_data = &spi0_csi[0],
+	}
+#endif
+};
+#endif
+
+#if defined(CONFIG_PHONE_IPC_SPI)
+static void ipc_spi_cfg_gpio(void);
+
+static struct ipc_spi_platform_data ipc_spi_data = {
+	.gpio_ipc_mrdy = GPIO_IPC_MRDY,
+	.gpio_ipc_srdy = GPIO_IPC_SRDY,
+	.gpio_ipc_sub_mrdy = GPIO_IPC_SUB_MRDY,
+	.gpio_ipc_sub_srdy = GPIO_IPC_SUB_SRDY,
+
+	.cfg_gpio = ipc_spi_cfg_gpio,
+};
+
+static struct resource ipc_spi_res[] = {
+	[0] = {
+		.start = IRQ_IPC_SRDY,
+		.end = IRQ_IPC_SRDY,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device ipc_spi_device = {
+	.name = "onedram",
+	.id = -1,
+	.num_resources = ARRAY_SIZE(ipc_spi_res),
+	.resource = ipc_spi_res,
+	.dev = {
+		.platform_data = &ipc_spi_data,
+	},
+};
+
+static void ipc_spi_cfg_gpio(void)
+{
+	int err = 0;
+
+	unsigned gpio_ipc_mrdy = ipc_spi_data.gpio_ipc_mrdy;
+	unsigned gpio_ipc_srdy = ipc_spi_data.gpio_ipc_srdy;
+	unsigned gpio_ipc_sub_mrdy = ipc_spi_data.gpio_ipc_sub_mrdy;
+	unsigned gpio_ipc_sub_srdy = ipc_spi_data.gpio_ipc_sub_srdy;
+
+	err = gpio_request(gpio_ipc_mrdy, "IPC_MRDY");
+	if (err) {
+		printk(KERN_ERR "ipc_spi_cfg_gpio - fail to request gpio %s : %d\n",
+			"IPC_MRDY", err);
+	} else {
+		gpio_direction_output(gpio_ipc_mrdy, 0);
+		s3c_gpio_setpull(gpio_ipc_mrdy, S3C_GPIO_PULL_DOWN);
+	}
+
+	err = gpio_request(gpio_ipc_srdy, "IPC_SRDY");
+	if (err) {
+		printk(KERN_ERR "ipc_spi_cfg_gpio - fail to request gpio %s : %d\n",
+			"IPC_SRDY", err);
+	} else {
+		gpio_direction_input(gpio_ipc_srdy);
+		s3c_gpio_cfgpin(gpio_ipc_srdy, S3C_GPIO_SFN(0xF));
+		s3c_gpio_setpull(gpio_ipc_srdy, S3C_GPIO_PULL_NONE);
+	}
+
+	err = gpio_request(gpio_ipc_sub_mrdy, "IPC_SUB_MRDY");
+	if (err) {
+		printk(KERN_ERR "ipc_spi_cfg_gpio - fail to request gpio %s : %d\n",
+			"IPC_SUB_MRDY", err);
+	} else {
+		gpio_direction_output(gpio_ipc_sub_mrdy, 0);
+		s3c_gpio_setpull(gpio_ipc_sub_mrdy, S3C_GPIO_PULL_DOWN);
+	}
+
+	err = gpio_request(gpio_ipc_sub_srdy, "IPC_SUB_SRDY");
+	if (err) {
+		printk(KERN_ERR "ipc_spi_cfg_gpio - fail to request gpio %s : %d\n",
+			"IPC_SUB_SRDY", err);
+	} else {
+		gpio_direction_input(gpio_ipc_sub_srdy);
+		s3c_gpio_cfgpin(gpio_ipc_sub_srdy, S3C_GPIO_SFN(0xF));
+		s3c_gpio_setpull(gpio_ipc_sub_srdy, S3C_GPIO_PULL_NONE);
+	}
+
+	irq_set_irq_type(gpio_to_irq(GPIO_IPC_SRDY), IRQ_TYPE_EDGE_RISING);
+	irq_set_irq_type(gpio_to_irq(GPIO_IPC_SUB_SRDY), IRQ_TYPE_EDGE_RISING);
+}
+#endif
+
+#ifdef CONFIG_FB_S5P
+unsigned int lcdtype;
+static int __init lcdtype_setup(char *str)
+{
+	get_option(&str, &lcdtype);
+	return 1;
+}
+__setup("lcdtype=", lcdtype_setup);
+
+#ifdef CONFIG_FB_S5P_LD9040
+unsigned int ld9040_lcdtype;
+static int __init ld9040_lcdtype_setup(char *str)
+{
+	get_option(&str, &ld9040_lcdtype);
+	return 1;
+}
+
+__setup("ld9040.get_lcdtype=0x", ld9040_lcdtype_setup);
+
+static int lcd_cfg_gpio(void)
+{
+	int i, f3_end = 4;
+
+	for (i = 0; i < 8; i++) {
+		/* set GPF0,1,2[0:7] for RGB Interface and Data line (32bit) */
+		s3c_gpio_cfgpin(EXYNOS4_GPF0(i), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(EXYNOS4_GPF0(i), S3C_GPIO_PULL_NONE);
+
+	}
+	for (i = 0; i < 8; i++) {
+		s3c_gpio_cfgpin(EXYNOS4_GPF1(i), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(EXYNOS4_GPF1(i), S3C_GPIO_PULL_NONE);
+	}
+
+	for (i = 0; i < 8; i++) {
+		s3c_gpio_cfgpin(EXYNOS4_GPF2(i), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(EXYNOS4_GPF2(i), S3C_GPIO_PULL_NONE);
+	}
+
+	for (i = 0; i < f3_end; i++) {
+		s3c_gpio_cfgpin(EXYNOS4_GPF3(i), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(EXYNOS4_GPF3(i), S3C_GPIO_PULL_NONE);
+	}
+
+#ifdef MAX_DRVSTR
+	/* drive strength to max */
+	writel(0xffffffff, S5P_VA_GPIO + 0x18c);
+	writel(0xffffffff, S5P_VA_GPIO + 0x1ac);
+	writel(0xffffffff, S5P_VA_GPIO + 0x1cc);
+	writel(readl(S5P_VA_GPIO + 0x1ec) | 0xffffff, S5P_VA_GPIO + 0x1ec);
+#else
+	/* drive strength to 2X */
+	writel(0xaaaaaaaa, S5P_VA_GPIO + 0x18c);
+	writel(0xaaaaaaaa, S5P_VA_GPIO + 0x1ac);
+	writel(0xaaaaaaaa, S5P_VA_GPIO + 0x1cc);
+	writel(readl(S5P_VA_GPIO + 0x1ec) | 0xaaaaaa, S5P_VA_GPIO + 0x1ec);
+#endif
+
+#if !defined(CONFIG_MACH_U1_KOR_LGT)
+	/* MLCD_RST */
+	s3c_gpio_cfgpin(EXYNOS4_GPY4(5), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPY4(5), S3C_GPIO_PULL_NONE);
+
+	/* LCD_nCS */
+	s3c_gpio_cfgpin(EXYNOS4_GPY4(3), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPY4(3), S3C_GPIO_PULL_NONE);
+	/* LCD_SCLK */
+	s3c_gpio_cfgpin(EXYNOS4_GPY3(1), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPY3(1), S3C_GPIO_PULL_NONE);
+	/* LCD_SDI */
+	s3c_gpio_cfgpin(EXYNOS4_GPY3(3), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPY3(3), S3C_GPIO_PULL_NONE);
+#else
+	/* MLCD_RST */
+	s3c_gpio_cfgpin(EXYNOS4_GPX1(3), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPX1(3), S3C_GPIO_PULL_NONE);
+	/* LCD_nCS */
+	s3c_gpio_cfgpin(EXYNOS4_GPY0(3), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPY0(3), S3C_GPIO_PULL_NONE);
+	/* LCD_SCLK */
+	s3c_gpio_cfgpin(EXYNOS4210_GPE2(3), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4210_GPE2(3), S3C_GPIO_PULL_NONE);
+	/* LCD_SDI */
+	s3c_gpio_cfgpin(EXYNOS4_GPX1(1), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPX1(1), S3C_GPIO_PULL_NONE);
+#endif
+
+	return 0;
+}
+
+static int lcd_power_on(struct lcd_device *ld, int enable)
+{
+	struct regulator *regulator;
+
+	if (ld == NULL) {
+		printk(KERN_ERR "lcd device object is NULL.\n");
+		return 0;
+	}
+
+	if (enable) {
+		regulator = regulator_get(NULL, "vlcd_3.0v");
+		if (IS_ERR(regulator))
+			return 0;
+
+		regulator_enable(regulator);
+		regulator_put(regulator);
+	} else {
+		regulator = regulator_get(NULL, "vlcd_3.0v");
+
+		if (IS_ERR(regulator))
+			return 0;
+
+		if (regulator_is_enabled(regulator))
+			regulator_force_disable(regulator);
+
+		regulator_put(regulator);
+	}
+
+	return 1;
+}
+
+static int reset_lcd(struct lcd_device *ld)
+{
+	int reset_gpio = -1;
+	int err;
+
+#if !defined(CONFIG_MACH_U1_KOR_LGT)
+	reset_gpio = EXYNOS4_GPY4(5);
+#else
+	reset_gpio = EXYNOS4_GPX1(3);
+#endif
+
+	err = gpio_request(reset_gpio, "MLCD_RST");
+	if (err) {
+		printk(KERN_ERR "failed to request MLCD_RST for "
+		       "lcd reset control\n");
+		return err;
+	}
+
+	gpio_request(reset_gpio, "MLCD_RST");
+
+	gpio_direction_output(reset_gpio, 1);
+	mdelay(5);
+	gpio_direction_output(reset_gpio, 0);
+	mdelay(5);
+	gpio_direction_output(reset_gpio, 1);
+
+	gpio_free(reset_gpio);
+
+	return 1;
+}
+
+static int lcd_gpio_cfg_earlysuspend(struct lcd_device *ld)
+{
+	int reset_gpio = -1;
+	int err;
+
+#if !defined(CONFIG_MACH_U1_KOR_LGT)
+	reset_gpio = EXYNOS4_GPY4(5);
+#else
+	reset_gpio = EXYNOS4_GPX1(3);
+#endif
+
+	err = gpio_request(reset_gpio, "MLCD_RST");
+	if (err) {
+		printk(KERN_ERR "failed to request MLCD_RST for "
+		       "lcd reset control\n");
+		return err;
+	}
+
+	mdelay(5);
+	gpio_direction_output(reset_gpio, 0);
+
+	gpio_free(reset_gpio);
+
+	return 0;
+}
+
+static int lcd_gpio_cfg_lateresume(struct lcd_device *ld)
+{
+#if !defined(CONFIG_MACH_U1_KOR_LGT)
+	/* MLCD_RST */
+	s3c_gpio_cfgpin(EXYNOS4_GPY4(5), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPY4(5), S3C_GPIO_PULL_NONE);
+
+	/* LCD_nCS */
+	s3c_gpio_cfgpin(EXYNOS4_GPY4(3), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPY4(3), S3C_GPIO_PULL_NONE);
+	/* LCD_SCLK */
+	s3c_gpio_cfgpin(EXYNOS4_GPY3(1), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPY3(1), S3C_GPIO_PULL_NONE);
+	/* LCD_SDI */
+	s3c_gpio_cfgpin(EXYNOS4_GPY3(3), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPY3(3), S3C_GPIO_PULL_NONE);
+#else
+	/* MLCD_RST */
+	s3c_gpio_cfgpin(EXYNOS4_GPX1(3), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPX1(3), S3C_GPIO_PULL_NONE);
+	/* LCD_nCS */
+	s3c_gpio_cfgpin(EXYNOS4_GPY0(3), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPY0(3), S3C_GPIO_PULL_NONE);
+	/* LCD_SCLK */
+	s3c_gpio_cfgpin(EXYNOS4210_GPE2(3), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4210_GPE2(3), S3C_GPIO_PULL_NONE);
+	/* LCD_SDI */
+	s3c_gpio_cfgpin(EXYNOS4_GPX1(1), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPX1(1), S3C_GPIO_PULL_NONE);
+#endif
+
+	return 0;
+}
+
+static struct s3cfb_lcd ld9040_info = {
+	.width = 480,
+	.height = 800,
+	.p_width = 56,
+	.p_height = 93,
+	.bpp = 24,
+
+	.freq = 60,
+	.timing = {
+		.h_fp = 16,
+		.h_bp = 14,
+		.h_sw = 2,
+		.v_fp = 10,
+		.v_fpe = 1,
+		.v_bp = 4,
+		.v_bpe = 1,
+		.v_sw = 2,
+	},
+	.polarity = {
+		.rise_vclk = 1,
+		.inv_hsync = 1,
+		.inv_vsync = 1,
+		.inv_vden = 1,
+	},
+};
+
+static struct lcd_platform_data ld9040_platform_data = {
+	.reset = reset_lcd,
+	.power_on = lcd_power_on,
+	.gpio_cfg_earlysuspend = lcd_gpio_cfg_earlysuspend,
+	.gpio_cfg_lateresume = lcd_gpio_cfg_lateresume,
+	/* it indicates whether lcd panel is enabled from u-boot. */
+	.lcd_enabled = 1,
+	.reset_delay = 20,	/* 10ms */
+	.power_on_delay = 20,	/* 20ms */
+	.power_off_delay = 200,	/* 120ms */
+	.pdata = &u1_panel_data,
+};
+
+#define LCD_BUS_NUM	3
+#if !defined(CONFIG_MACH_U1_KOR_LGT)
+#define DISPLAY_CS	EXYNOS4_GPY4(3)
+#else
+#define DISPLAY_CS	EXYNOS4_GPY0(3)
+#endif
+static struct spi_board_info spi_board_info[] __initdata = {
+	{
+		.max_speed_hz = 1200000,
+		.bus_num = LCD_BUS_NUM,
+		.chip_select = 0,
+		.mode = SPI_MODE_3,
+		.controller_data = (void *)DISPLAY_CS,
+	},
+};
+
+#if !defined(CONFIG_MACH_U1_KOR_LGT)
+#define DISPLAY_CLK	EXYNOS4_GPY3(1)
+#define DISPLAY_SI	EXYNOS4_GPY3(3)
+#else
+#define DISPLAY_CLK	EXYNOS4210_GPE2(3)
+#define DISPLAY_SI	EXYNOS4_GPX1(1)
+#endif
+static struct spi_gpio_platform_data lcd_spi_gpio_data = {
+	.sck = DISPLAY_CLK,
+	.mosi = DISPLAY_SI,
+	.miso = SPI_GPIO_NO_MISO,
+	.num_chipselect = 1,
+};
+
+static struct platform_device ld9040_spi_gpio = {
+	.name = "spi_gpio",
+	.id = LCD_BUS_NUM,
+	.dev = {
+		.parent = &s3c_device_fb.dev,
+		.platform_data = &lcd_spi_gpio_data,
+	},
+};
+
+static struct s3c_platform_fb fb_platform_data __initdata = {
+	.hw_ver = 0x70,
+	.clk_name = "fimd",
+	.nr_wins = 5,
+#ifdef CONFIG_FB_S5P_DEFAULT_WINDOW
+	.default_win = CONFIG_FB_S5P_DEFAULT_WINDOW,
+#else
+	.default_win = 0,
+#endif
+	.swap = FB_SWAP_HWORD | FB_SWAP_WORD,
+	.lcd = &ld9040_info,
+};
+
+/* reading with 3-WIRE SPI with GPIO */
+static inline void setcs(u8 is_on)
+{
+	gpio_set_value(DISPLAY_CS, is_on);
+}
+
+static inline void setsck(u8 is_on)
+{
+	gpio_set_value(DISPLAY_CLK, is_on);
+}
+
+static inline void setmosi(u8 is_on)
+{
+	gpio_set_value(DISPLAY_SI, is_on);
+}
+
+static inline unsigned int getmiso(void)
+{
+	return !!gpio_get_value(DISPLAY_SI);
+}
+
+static inline void setmosi2miso(u8 is_on)
+{
+	if (is_on)
+		s3c_gpio_cfgpin(DISPLAY_SI, S3C_GPIO_INPUT);
+	else
+		s3c_gpio_cfgpin(DISPLAY_SI, S3C_GPIO_OUTPUT);
+}
+
+struct spi_ops ops = {
+	.setcs = setcs,
+	.setsck = setsck,
+	.setmosi = setmosi,
+	.setmosi2miso = setmosi2miso,
+	.getmiso = getmiso,
+};
+
+static void __init ld9040_fb_init(void)
+{
+	struct ld9040_panel_data *pdata;
+
+	strcpy(spi_board_info[0].modalias, "ld9040");
+	spi_board_info[0].platform_data = (void *)&ld9040_platform_data;
+
+	lcdtype = max(ld9040_lcdtype, lcdtype);
+
+	if (lcdtype == LCDTYPE_SM2_A2)
+		ld9040_platform_data.pdata = &u1_panel_data_a2;
+	else if (lcdtype == LCDTYPE_M2)
+		ld9040_platform_data.pdata = &u1_panel_data_m2;
+
+	pdata = ld9040_platform_data.pdata;
+	pdata->ops = &ops;
+
+	printk(KERN_INFO "%s :: lcdtype=%d\n", __func__, lcdtype);
+
+	spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
+
+	if (!ld9040_platform_data.lcd_enabled)
+		lcd_cfg_gpio();
+	s3cfb_set_platdata(&fb_platform_data);
+}
+#endif
+
+#ifdef CONFIG_FB_S5P_NT35560
+static int lcd_cfg_gpio(void)
+{
+	int i, f3_end = 4;
+
+	for (i = 0; i < 8; i++) {
+		/* set GPF0,1,2[0:7] for RGB Interface and Data line (32bit) */
+		s3c_gpio_cfgpin(EXYNOS4_GPF0(i), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(EXYNOS4_GPF0(i), S3C_GPIO_PULL_NONE);
+
+	}
+	for (i = 0; i < 8; i++) {
+		s3c_gpio_cfgpin(EXYNOS4_GPF1(i), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(EXYNOS4_GPF1(i), S3C_GPIO_PULL_NONE);
+	}
+
+	for (i = 0; i < 8; i++) {
+		s3c_gpio_cfgpin(EXYNOS4_GPF2(i), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(EXYNOS4_GPF2(i), S3C_GPIO_PULL_NONE);
+	}
+
+	for (i = 0; i < f3_end; i++) {
+		s3c_gpio_cfgpin(EXYNOS4_GPF3(i), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(EXYNOS4_GPF3(i), S3C_GPIO_PULL_NONE);
+	}
+
+#ifdef MAX_DRVSTR
+	/* drive strength to max */
+	writel(0xffffffff, S5P_VA_GPIO + 0x18c);
+	writel(0xffffffff, S5P_VA_GPIO + 0x1ac);
+	writel(0xffffffff, S5P_VA_GPIO + 0x1cc);
+	writel(readl(S5P_VA_GPIO + 0x1ec) | 0xffffff, S5P_VA_GPIO + 0x1ec);
+#else
+	/* drive strength to 2X */
+	writel(0xaaaaaaaa, S5P_VA_GPIO + 0x18c);
+	writel(0xaaaaaaaa, S5P_VA_GPIO + 0x1ac);
+	writel(0xaaaaaaaa, S5P_VA_GPIO + 0x1cc);
+	writel(readl(S5P_VA_GPIO + 0x1ec) | 0xaaaaaa, S5P_VA_GPIO + 0x1ec);
+#endif
+
+	/* MLCD_RST */
+	s3c_gpio_cfgpin(EXYNOS4_GPY4(5), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPY4(5), S3C_GPIO_PULL_NONE);
+
+	/* LCD_nCS */
+	s3c_gpio_cfgpin(EXYNOS4_GPY4(3), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPY4(3), S3C_GPIO_PULL_NONE);
+
+	/* LCD_SCLK */
+	s3c_gpio_cfgpin(EXYNOS4_GPY3(1), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPY3(1), S3C_GPIO_PULL_NONE);
+
+	/* LCD_SDI */
+	s3c_gpio_cfgpin(EXYNOS4_GPY3(3), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPY3(3), S3C_GPIO_PULL_NONE);
+
+	return 0;
+}
+
+static int lcd_power_on(struct lcd_device *ld, int enable)
+{
+	struct regulator *regulator;
+
+	if (ld == NULL) {
+		printk(KERN_ERR "lcd device object is NULL.\n");
+		return 0;
+	}
+
+	if (enable) {
+		regulator = regulator_get(NULL, "vlcd_3.0v");
+		if (IS_ERR(regulator))
+			return 0;
+
+		regulator_enable(regulator);
+		regulator_put(regulator);
+
+		regulator = regulator_get(NULL, "vlcd_1.8v");
+		if (IS_ERR(regulator))
+			return 0;
+
+		regulator_enable(regulator);
+		regulator_put(regulator);
+	} else {
+		regulator = regulator_get(NULL, "vlcd_1.8v");
+
+		if (IS_ERR(regulator))
+			return 0;
+
+		if (regulator_is_enabled(regulator))
+			regulator_force_disable(regulator);
+
+		regulator_put(regulator);
+
+		regulator = regulator_get(NULL, "vlcd_3.0v");
+
+		if (IS_ERR(regulator))
+			return 0;
+
+		if (regulator_is_enabled(regulator))
+			regulator_force_disable(regulator);
+
+		regulator_put(regulator);
+	}
+
+	return 1;
+}
+
+static int reset_lcd(struct lcd_device *ld)
+{
+	int reset_gpio = -1;
+	int err;
+
+	reset_gpio = EXYNOS4_GPY4(5);
+
+	err = gpio_request(reset_gpio, "MLCD_RST");
+	if (err) {
+		printk(KERN_ERR "failed to request MLCD_RST for "
+		       "lcd reset control\n");
+		return err;
+	}
+
+	gpio_request(reset_gpio, "MLCD_RST");
+
+	gpio_direction_output(reset_gpio, 1);
+	mdelay(5);
+	gpio_direction_output(reset_gpio, 0);
+	mdelay(5);
+	gpio_direction_output(reset_gpio, 1);
+
+	gpio_free(reset_gpio);
+
+	return 1;
+}
+
+static int lcd_gpio_cfg_earlysuspend(struct lcd_device *ld)
+{
+	int reset_gpio = -1;
+	int err;
+
+	reset_gpio = EXYNOS4_GPY4(5);
+
+	err = gpio_request(reset_gpio, "MLCD_RST");
+	if (err) {
+		printk(KERN_ERR "failed to request MLCD_RST for "
+		       "lcd reset control\n");
+		return err;
+	}
+
+	mdelay(5);
+	gpio_direction_output(reset_gpio, 0);
+
+	gpio_free(reset_gpio);
+
+	return 0;
+}
+
+static int lcd_gpio_cfg_lateresume(struct lcd_device *ld)
+{
+	/* MLCD_RST */
+	s3c_gpio_cfgpin(EXYNOS4_GPY4(5), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPY4(5), S3C_GPIO_PULL_NONE);
+
+	/* LCD_nCS */
+	s3c_gpio_cfgpin(EXYNOS4_GPY4(3), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPY4(3), S3C_GPIO_PULL_NONE);
+
+	/* LCD_SCLK */
+	s3c_gpio_cfgpin(EXYNOS4_GPY3(1), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPY3(1), S3C_GPIO_PULL_NONE);
+
+	/* LCD_SDI */
+	s3c_gpio_cfgpin(EXYNOS4_GPY3(3), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPY3(3), S3C_GPIO_PULL_NONE);
+
+	return 0;
+}
+
+static struct s3cfb_lcd nt35560_info = {
+	.width = 480,
+	.height = 800,
+	.p_width = 52,
+	.p_height = 86,
+	.bpp = 24,
+
+	.freq = 60,
+	.timing = {
+		.h_fp = 10,
+		.h_bp = 10,
+		.h_sw = 10,
+		.v_fp = 9,
+		.v_fpe = 1,
+		.v_bp = 4,
+		.v_bpe = 1,
+		.v_sw = 2,
+	},
+	.polarity = {
+		.rise_vclk = 1,
+		.inv_hsync = 1,
+		.inv_vsync = 1,
+		.inv_vden = 1,
+	},
+};
+
+static struct lcd_platform_data nt35560_platform_data = {
+	.reset = reset_lcd,
+	.power_on = lcd_power_on,
+	.gpio_cfg_earlysuspend = lcd_gpio_cfg_earlysuspend,
+	.gpio_cfg_lateresume = lcd_gpio_cfg_lateresume,
+	/* it indicates whether lcd panel is enabled from u-boot. */
+	.lcd_enabled = 1,
+	.reset_delay = 10,	/* 10ms */
+	.power_on_delay = 10,	/* 10ms */
+	.power_off_delay = 150,	/* 150ms */
+};
+
+#define LCD_BUS_NUM	3
+#define DISPLAY_CS	EXYNOS4_GPY4(3)
+static struct spi_board_info spi_board_info[] __initdata = {
+	{
+		.max_speed_hz = 1200000,
+		.bus_num = LCD_BUS_NUM,
+		.chip_select = 0,
+		.mode = SPI_MODE_3,
+		.controller_data = (void *)DISPLAY_CS,
+	},
+};
+
+#define DISPLAY_CLK	EXYNOS4_GPY3(1)
+#define DISPLAY_SI	EXYNOS4_GPY3(3)
+static struct spi_gpio_platform_data lcd_spi_gpio_data = {
+	.sck = DISPLAY_CLK,
+	.mosi = DISPLAY_SI,
+	.miso = SPI_GPIO_NO_MISO,
+	.num_chipselect = 1,
+};
+
+static struct platform_device nt35560_spi_gpio = {
+	.name = "spi_gpio",
+	.id = LCD_BUS_NUM,
+	.dev = {
+		.parent = &s3c_device_fb.dev,
+		.platform_data = &lcd_spi_gpio_data,
+	},
+};
+
+static struct s3c_platform_fb fb_platform_data __initdata = {
+	.hw_ver = 0x70,
+	.clk_name = "fimd",
+	.nr_wins = 5,
+#ifdef CONFIG_FB_S5P_DEFAULT_WINDOW
+	.default_win = CONFIG_FB_S5P_DEFAULT_WINDOW,
+#else
+	.default_win = 0,
+#endif
+	.swap = FB_SWAP_HWORD | FB_SWAP_WORD,
+	.lcd = &nt35560_info,
+};
+
+static void __init nt35560_fb_init(void)
+{
+	struct ld9040_panel_data *pdata;
+
+	strcpy(spi_board_info[0].modalias, "nt35560");
+	spi_board_info[0].platform_data = (void *)&nt35560_platform_data;
+
+	pdata = nt35560_platform_data.pdata;
+
+	spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
+
+	if (!nt35560_platform_data.lcd_enabled)
+		lcd_cfg_gpio();
+	s3cfb_set_platdata(&fb_platform_data);
+}
+#endif
+
+#ifdef CONFIG_FB_S5P_AMS369FG06
+static struct s3c_platform_fb ams369fg06_data __initdata = {
+	.hw_ver = 0x70,
+	.clk_name = "sclk_lcd",
+	.nr_wins = 5,
+	.default_win = CONFIG_FB_S5P_DEFAULT_WINDOW,
+	.swap = FB_SWAP_HWORD | FB_SWAP_WORD,
+};
+
+#define		LCD_BUS_NUM	3
+#define		DISPLAY_CS	EXYNOS4_GPB(5)
+#define		DISPLAY_CLK	EXYNOS4_GPB(4)
+#define		DISPLAY_SI	EXYNOS4_GPB(7)
+
+static struct spi_board_info spi_board_info[] __initdata = {
+	{
+		.modalias = "ams369fg06",
+		.platform_data = NULL,
+		.max_speed_hz = 1200000,
+		.bus_num = LCD_BUS_NUM,
+		.chip_select = 0,
+		.mode = SPI_MODE_3,
+		.controller_data = (void *)DISPLAY_CS,
+	}
+};
+
+static struct spi_gpio_platform_data ams369fg06_spi_gpio_data = {
+	.sck = DISPLAY_CLK,
+	.mosi = DISPLAY_SI,
+	.miso = -1,
+	.num_chipselect = 1,
+};
+
+static struct platform_device s3c_device_spi_gpio = {
+	.name = "spi_gpio",
+	.id = LCD_BUS_NUM,
+	.dev = {
+		.parent = &s3c_device_fb.dev,
+		.platform_data = &ams369fg06_spi_gpio_data,
+	},
+};
+#endif
+
+#ifdef CONFIG_FB_S5P_MDNIE
+static struct platform_device mdnie_device = {
+	.name = "mdnie",
+	.id = -1,
+	.dev = {
+		.parent = &exynos4_device_pd[PD_LCD0].dev,
+	},
+};
+#endif
+
+#endif
+
+static struct platform_device u1_regulator_consumer = {
+	.name = "u1-regulator-consumer",
+	.id = -1,
+};
+
+#ifdef CONFIG_REGULATOR_MAX8997
+static struct regulator_consumer_supply ldo1_supply[] = {
+	REGULATOR_SUPPLY("vadc_3.3v", NULL),
+};
+
+static struct regulator_consumer_supply ldo3_supply[] = {
+	REGULATOR_SUPPLY("vusb_1.1v", "usb_otg"),
+	REGULATOR_SUPPLY("vmipi_1.1v", "m5mo"),
+	REGULATOR_SUPPLY("vmipi_1.1v", NULL),
+};
+
+static struct regulator_consumer_supply ldo4_supply[] = {
+	REGULATOR_SUPPLY("vmipi_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo5_supply[] = {
+	REGULATOR_SUPPLY("vhsic", NULL),
+};
+
+static struct regulator_consumer_supply ldo7_supply[] = {
+	REGULATOR_SUPPLY("cam_isp", NULL),
+};
+
+static struct regulator_consumer_supply ldo8_supply[] = {
+	REGULATOR_SUPPLY("vusb_3.3v", NULL),
+};
+
+#if defined(CONFIG_S5PV310_HI_ARMCLK_THAN_1_2GHZ)
+static struct regulator_consumer_supply ldo10_supply[] = {
+	REGULATOR_SUPPLY("vpll_1.2v", NULL),
+};
+#else
+static struct regulator_consumer_supply ldo10_supply[] = {
+	REGULATOR_SUPPLY("vpll_1.1v", NULL),
+};
+#endif
+
+static struct regulator_consumer_supply ldo11_supply[] = {
+	REGULATOR_SUPPLY("touch", NULL),
+};
+
+static struct regulator_consumer_supply ldo12_supply[] = {
+	REGULATOR_SUPPLY("vt_cam_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo13_supply[] = {
+	REGULATOR_SUPPLY("vlcd_3.0v", NULL),
+};
+
+#ifdef CONFIG_MACH_Q1_BD
+static struct regulator_consumer_supply ldo14_supply[] = {
+	REGULATOR_SUPPLY("vlcd_2.2v", NULL),
+};
+#else
+static struct regulator_consumer_supply ldo14_supply[] = {
+	REGULATOR_SUPPLY("vmotor", NULL),
+};
+#endif
+
+static struct regulator_consumer_supply ldo15_supply[] = {
+	REGULATOR_SUPPLY("vled", NULL),
+};
+
+static struct regulator_consumer_supply ldo16_supply[] = {
+	REGULATOR_SUPPLY("cam_sensor_io", NULL),
+};
+
+static struct regulator_consumer_supply ldo17_supply[] = {
+	REGULATOR_SUPPLY("vtf_2.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo18_supply[] = {
+	REGULATOR_SUPPLY("touch_led", NULL),
+};
+
+
+static struct regulator_consumer_supply ldo21_supply[] = {
+	REGULATOR_SUPPLY("vddq_m1m2", NULL),
+};
+
+static struct regulator_consumer_supply buck1_supply[] = {
+	REGULATOR_SUPPLY("vdd_arm", NULL),
+};
+
+static struct regulator_consumer_supply buck2_supply[] = {
+	REGULATOR_SUPPLY("vdd_int", NULL),
+};
+
+static struct regulator_consumer_supply buck3_supply[] = {
+	REGULATOR_SUPPLY("vdd_g3d", NULL),
+};
+
+static struct regulator_consumer_supply buck4_supply[] = {
+	REGULATOR_SUPPLY("cam_isp_core", NULL),
+};
+
+static struct regulator_consumer_supply buck7_supply[] = {
+	REGULATOR_SUPPLY("vcc_sub", NULL),
+};
+
+static struct regulator_consumer_supply safeout1_supply[] = {
+	REGULATOR_SUPPLY("safeout1", NULL),
+};
+
+static struct regulator_consumer_supply safeout2_supply[] = {
+	REGULATOR_SUPPLY("safeout2", NULL),
+};
+
+static struct regulator_consumer_supply led_flash_supply[] = {
+	REGULATOR_SUPPLY("led_flash", NULL),
+};
+
+static struct regulator_consumer_supply led_movie_supply[] = {
+	REGULATOR_SUPPLY("led_movie", NULL),
+};
+
+#if defined(CONFIG_MACH_Q1_BD)
+static struct regulator_consumer_supply led_torch_supply[] = {
+	REGULATOR_SUPPLY("led_torch", NULL),
+};
+#endif /* CONFIG_MACH_Q1_BD */
+
+#define REGULATOR_INIT(_ldo, _name, _min_uV, _max_uV, _always_on, _ops_mask, \
+		       _disabled)					\
+	static struct regulator_init_data _ldo##_init_data = {		\
+		.constraints = {					\
+			.name	= _name,				\
+			.min_uV = _min_uV,				\
+			.max_uV = _max_uV,				\
+			.always_on	= _always_on,			\
+			.boot_on	= _always_on,			\
+			.apply_uV	= 1,				\
+			.valid_ops_mask = _ops_mask,			\
+			.state_mem	= {				\
+				.disabled =				\
+					(_disabled == -1 ? 0 : _disabled),\
+				.enabled =				\
+					(_disabled == -1 ? 0 : !(_disabled)),\
+			}						\
+		},							\
+		.num_consumer_supplies = ARRAY_SIZE(_ldo##_supply),	\
+		.consumer_supplies = &_ldo##_supply[0],			\
+	};
+
+REGULATOR_INIT(ldo1, "VADC_3.3V_C210", 3300000, 3300000, 1,
+		REGULATOR_CHANGE_STATUS, 0);
+REGULATOR_INIT(ldo3, "VUSB_1.1V", 1100000, 1100000, 1,
+		REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo4, "VMIPI_1.8V", 1800000, 1800000, 1,
+		REGULATOR_CHANGE_STATUS, 1);
+#if defined(CONFIG_MACH_U1_KOR_LGT)
+REGULATOR_INIT(ldo5, "VHSIC_1.2V", 1200000, 1200000, 0,
+		REGULATOR_CHANGE_STATUS, 1);
+#else
+REGULATOR_INIT(ldo5, "VHSIC_1.2V", 1200000, 1200000, 1,
+		REGULATOR_CHANGE_STATUS, 1);
+#endif
+REGULATOR_INIT(ldo7, "CAM_ISP_1.8V", 1800000, 1800000, 0,
+		REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo8, "VUSB_3.3V", 3300000, 3300000, 1,
+		REGULATOR_CHANGE_STATUS, 1);
+#if defined(CONFIG_S5PV310_HI_ARMCLK_THAN_1_2GHZ)
+REGULATOR_INIT(ldo10, "VPLL_1.2V", 1200000, 1200000, 1,
+		REGULATOR_CHANGE_STATUS, 1);
+#else
+REGULATOR_INIT(ldo10, "VPLL_1.1V", 1100000, 1100000, 1,
+		REGULATOR_CHANGE_STATUS, 1);
+#endif
+REGULATOR_INIT(ldo11, "TOUCH_2.8V", 2800000, 2800000, 0,
+		REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo12, "VT_CAM_1.8V", 1800000, 1800000, 0,
+		REGULATOR_CHANGE_STATUS, 1);
+#if defined(CONFIG_MACH_Q1_BD)
+REGULATOR_INIT(ldo13, "VCC_3.0V_LCD", 3100000, 3100000, 1,
+		REGULATOR_CHANGE_STATUS, 1);
+#else
+REGULATOR_INIT(ldo13, "VCC_3.0V_LCD", 3000000, 3000000, 1,
+		REGULATOR_CHANGE_STATUS, 1);
+#endif
+#if defined(CONFIG_MACH_Q1_BD)
+REGULATOR_INIT(ldo14, "VCC_2.2V_LCD", 2200000, 2200000, 1,
+		REGULATOR_CHANGE_STATUS, 1);
+#else
+REGULATOR_INIT(ldo14, "VCC_2.8V_MOTOR", 2800000, 2800000, 0,
+		REGULATOR_CHANGE_STATUS, 1);
+#endif
+REGULATOR_INIT(ldo15, "LED_A_2.8V", 2800000, 2800000, 0,
+		REGULATOR_CHANGE_STATUS, -1);
+REGULATOR_INIT(ldo16, "CAM_SENSOR_IO_1.8V", 1800000, 1800000, 0,
+		REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo17, "VTF_2.8V", 2800000, 2800000, 0,
+		REGULATOR_CHANGE_STATUS, 1);
+#if defined(CONFIG_MACH_Q1_BD)
+REGULATOR_INIT(ldo18, "TOUCH_LED_3.3V", 3300000, 3300000, 0,
+		REGULATOR_CHANGE_STATUS, 1);
+#else
+REGULATOR_INIT(ldo18, "TOUCH_LED_3.3V", 3000000, 3300000, 0,
+	REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE, 1);
+#endif
+REGULATOR_INIT(ldo21, "VDDQ_M1M2_1.2V", 1200000, 1200000, 1,
+		REGULATOR_CHANGE_STATUS, 1);
+
+
+static struct regulator_init_data buck1_init_data = {
+	.constraints	= {
+		.name		= "vdd_arm range",
+		.min_uV		= 650000,
+		.max_uV		= 2225000,
+		.always_on	= 1,
+		.boot_on	= 1,
+		.apply_uV	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE |
+				  REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.mode		= REGULATOR_MODE_NORMAL,
+			.disabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &buck1_supply[0],
+};
+
+static struct regulator_init_data buck2_init_data = {
+	.constraints	= {
+		.name		= "vdd_int range",
+		.min_uV		= 650000,
+		.max_uV		= 2225000,
+		.always_on	= 1,
+		.boot_on	= 1,
+		.apply_uV	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE |
+				  REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.mode		= REGULATOR_MODE_NORMAL,
+			.disabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &buck2_supply[0],
+};
+
+static struct regulator_init_data buck3_init_data = {
+	.constraints	= {
+		.name		= "G3D_1.1V",
+		.min_uV		= 900000,
+		.max_uV		= 1200000,
+		.always_on	= 0,
+		.boot_on	= 0,
+		.apply_uV	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE |
+				  REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.mode		= REGULATOR_MODE_NORMAL,
+			.disabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &buck3_supply[0],
+};
+
+static struct regulator_init_data buck4_init_data = {
+	.constraints	= {
+		.name		= "CAM_ISP_CORE_1.2V",
+		.min_uV		= 1200000,
+		.max_uV		= 1200000,
+		.apply_uV	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.disabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &buck4_supply[0],
+};
+
+static struct regulator_init_data buck5_init_data = {
+	.constraints	= {
+		.name		= "VMEM_1.2V",
+		.min_uV		= 1200000,
+		.max_uV		= 1200000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.state_mem	= {
+			.uV	= 1200000,
+			.mode	= REGULATOR_MODE_NORMAL,
+			.enabled = 1,
+		},
+	},
+};
+
+static struct regulator_init_data buck7_init_data = {
+	.constraints	= {
+		.name		= "VCC_SUB_2.0V",
+		.min_uV		= 2000000,
+		.max_uV		= 2000000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.enabled = 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &buck7_supply[0],
+};
+
+static struct regulator_init_data safeout1_init_data = {
+	.constraints	= {
+		.name		= "safeout1 range",
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.boot_on	= 1,
+		.state_mem	= {
+			.enabled = 1,
+		},
+	},
+	.num_consumer_supplies	= ARRAY_SIZE(safeout1_supply),
+	.consumer_supplies	= safeout1_supply,
+};
+
+static struct regulator_init_data safeout2_init_data = {
+	.constraints	= {
+		.name		= "safeout2 range",
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.enabled = 1,
+		},
+	},
+	.num_consumer_supplies	= ARRAY_SIZE(safeout2_supply),
+	.consumer_supplies	= safeout2_supply,
+};
+
+static struct regulator_init_data led_flash_init_data = {
+	.constraints = {
+		.name	= "FLASH_CUR",
+		.min_uA = 23440,
+		.max_uA = 750080,
+		.valid_ops_mask	= REGULATOR_CHANGE_CURRENT |
+				  REGULATOR_CHANGE_STATUS,
+#if !defined(CONFIG_MACH_Q1_BD)
+		.state_mem	= {
+			.disabled	= 1,
+		},
+#endif
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &led_flash_supply[0],
+};
+
+static struct regulator_init_data led_movie_init_data = {
+	.constraints = {
+		.name	= "MOVIE_CUR",
+		.min_uA = 15625,
+		.max_uA = 250000,
+		.valid_ops_mask	= REGULATOR_CHANGE_CURRENT |
+				  REGULATOR_CHANGE_STATUS,
+#if !defined(CONFIG_MACH_Q1_BD)
+		.state_mem	= {
+			.disabled	= 1,
+		},
+#endif
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &led_movie_supply[0],
+};
+
+#if defined(CONFIG_MACH_Q1_BD)
+static struct regulator_init_data led_torch_init_data = {
+	.constraints = {
+		.name	= "FLASH_TORCH",
+		.min_uA = 15625,
+		.max_uA = 250000,
+		.valid_ops_mask	= REGULATOR_CHANGE_CURRENT |
+				  REGULATOR_CHANGE_STATUS,
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &led_torch_supply[0],
+};
+#endif /* CONFIG_MACH_Q1_BD */
+
+static struct max8997_regulator_data max8997_regulators[] = {
+	{ MAX8997_LDO1,	 &ldo1_init_data, NULL, },
+	{ MAX8997_LDO3,	 &ldo3_init_data, NULL, },
+	{ MAX8997_LDO4,	 &ldo4_init_data, NULL, },
+	{ MAX8997_LDO5,	 &ldo5_init_data, NULL, },
+	{ MAX8997_LDO7,	 &ldo7_init_data, NULL, },
+	{ MAX8997_LDO8,	 &ldo8_init_data, NULL, },
+	{ MAX8997_LDO10, &ldo10_init_data, NULL, },
+	{ MAX8997_LDO11, &ldo11_init_data, NULL, },
+	{ MAX8997_LDO12, &ldo12_init_data, NULL, },
+	{ MAX8997_LDO13, &ldo13_init_data, NULL, },
+	{ MAX8997_LDO14, &ldo14_init_data, NULL, },
+	{ MAX8997_LDO15, &ldo15_init_data, NULL, },
+	{ MAX8997_LDO16, &ldo16_init_data, NULL, },
+	{ MAX8997_LDO17, &ldo17_init_data, NULL, },
+	{ MAX8997_LDO18, &ldo18_init_data, NULL, },
+	{ MAX8997_LDO21, &ldo21_init_data, NULL, },
+	{ MAX8997_BUCK1, &buck1_init_data, NULL, },
+	{ MAX8997_BUCK2, &buck2_init_data, NULL, },
+	{ MAX8997_BUCK3, &buck3_init_data, NULL, },
+	{ MAX8997_BUCK4, &buck4_init_data, NULL, },
+	{ MAX8997_BUCK5, &buck5_init_data, NULL, },
+	{ MAX8997_BUCK7, &buck7_init_data, NULL, },
+	{ MAX8997_ESAFEOUT1, &safeout1_init_data, NULL, },
+	{ MAX8997_ESAFEOUT2, &safeout2_init_data, NULL, },
+	{ MAX8997_FLASH_CUR, &led_flash_init_data, NULL, },
+	{ MAX8997_MOVIE_CUR, &led_movie_init_data, NULL, },
+#if defined CONFIG_MACH_Q1_BD
+	{ MAX8997_FLASH_TORCH, &led_torch_init_data, NULL, },
+#endif /* CONFIG_MACH_Q1_BD */
+};
+
+static struct max8997_power_data max8997_power = {
+	.batt_detect = 1,
+};
+
+#if defined(CONFIG_MACH_Q1_BD)
+static void motor_init_hw(void)
+{
+	if (gpio_request(GPIO_MOTOR_EN, "MOTOR_EN") < 0)
+		pr_err("[VIB] Failed to request GPIO_MOTOR_EN\n");
+}
+
+static void motor_en(bool enable)
+{
+	gpio_direction_output(GPIO_MOTOR_EN, enable);
+}
+#endif
+
+#ifdef CONFIG_VIBETONZ
+#ifdef CONFIG_TARGET_LOCALE_NTT
+static struct max8997_motor_data max8997_motor = {
+	.max_timeout = 10000,
+	.duty = 43696,
+	.period = 44138,
+	.init_hw = NULL,
+	.motor_en = NULL,
+	.pwm_id = 1,
+};
+#elif defined(CONFIG_TARGET_LOCALE_KOR) || defined(CONFIG_TARGET_LOCALE_NA)
+static struct max8997_motor_data max8997_motor = {
+	.max_timeout = 10000,
+	.duty = 44196,
+	.period = 44643,
+	.init_hw = NULL,
+	.motor_en = NULL,
+	.pwm_id = 1,
+};
+#elif defined(CONFIG_MACH_Q1_BD)
+static struct max8997_motor_data max8997_motor = {
+	.max_timeout = 10000,
+	.duty = 37641,
+	.period = 38022,
+	.init_hw = motor_init_hw,
+	.motor_en = motor_en,
+	.pwm_id = 1,
+};
+#else
+static struct max8997_motor_data max8997_motor = {
+	.max_timeout = 10000,
+	.duty = 37641,
+	.period = 38022,
+	.init_hw = NULL,
+	.motor_en = NULL,
+	.pwm_id = 1,
+};
+#endif
+#endif
+
+#ifdef CONFIG_MACH_U1_KOR_LGT
+static int max8997_muic_set_safeout(int path)
+{
+	static int safeout2_enabled;
+	struct regulator *regulator;
+
+	pr_info("%s: path = %d\n", __func__, path);
+
+	if (path == CP_USB_MODE) {
+		regulator = regulator_get(NULL, "safeout1");
+		if (IS_ERR(regulator))
+			return -ENODEV;
+		if (regulator_is_enabled(regulator))
+			regulator_force_disable(regulator);
+		regulator_put(regulator);
+
+		regulator = regulator_get(NULL, "safeout2");
+		if (IS_ERR(regulator))
+			return -ENODEV;
+		if (!safeout2_enabled) {
+			pr_info("%s: enable safeout2\n", __func__);
+			regulator_enable(regulator);
+			safeout2_enabled = 1;
+		} else
+			pr_info("%s: safeout2 is already enabled\n",
+							__func__);
+		regulator_put(regulator);
+	} else {
+		/* AP_USB_MODE || AUDIO_MODE */
+		regulator = regulator_get(NULL, "safeout1");
+		if (IS_ERR(regulator))
+			return -ENODEV;
+		if (!regulator_is_enabled(regulator))
+			regulator_enable(regulator);
+		regulator_put(regulator);
+
+		regulator = regulator_get(NULL, "safeout2");
+		if (IS_ERR(regulator))
+			return -ENODEV;
+		if (safeout2_enabled) {
+			pr_info("%s: disable safeout2\n", __func__);
+			regulator_disable(regulator);
+			safeout2_enabled = 0;
+		} else
+			pr_info("%s: safeout2 is already disabled\n",
+							__func__);
+		regulator_put(regulator);
+	}
+
+	return 0;
+}
+#else
+static int max8997_muic_set_safeout(int path)
+{
+	struct regulator *regulator;
+
+	if (path == CP_USB_MODE) {
+		regulator = regulator_get(NULL, "safeout1");
+		if (IS_ERR(regulator))
+			return -ENODEV;
+		if (regulator_is_enabled(regulator))
+			regulator_force_disable(regulator);
+		regulator_put(regulator);
+
+		regulator = regulator_get(NULL, "safeout2");
+		if (IS_ERR(regulator))
+			return -ENODEV;
+		if (!regulator_is_enabled(regulator))
+			regulator_enable(regulator);
+		regulator_put(regulator);
+	} else {
+		/* AP_USB_MODE || AUDIO_MODE */
+		regulator = regulator_get(NULL, "safeout1");
+		if (IS_ERR(regulator))
+			return -ENODEV;
+		if (!regulator_is_enabled(regulator))
+			regulator_enable(regulator);
+		regulator_put(regulator);
+
+		regulator = regulator_get(NULL, "safeout2");
+		if (IS_ERR(regulator))
+			return -ENODEV;
+		if (regulator_is_enabled(regulator))
+			regulator_force_disable(regulator);
+		regulator_put(regulator);
+	}
+
+	return 0;
+}
+#endif
+
+static struct charging_status_callbacks {
+	void (*tsp_set_charging_cable) (int type);
+} charging_cbs;
+
+bool is_cable_attached;
+static int connected_cable_type = CABLE_TYPE_NONE;
+
+static int max8997_muic_charger_cb(int cable_type)
+{
+	struct power_supply *psy = power_supply_get_by_name("battery");
+	union power_supply_propval value;
+
+	connected_cable_type = cable_type;
+
+	if (!psy) {
+		pr_err("%s: fail to get battery ps\n", __func__);
+#if defined(CONFIG_MACH_Q1_BD)
+		return 0;
+#else
+		return -ENODEV;
+#endif
+	}
+
+	switch (cable_type) {
+	case CABLE_TYPE_NONE:
+	case CABLE_TYPE_OTG:
+	case CABLE_TYPE_JIG_UART_OFF:
+	case CABLE_TYPE_MHL:
+		value.intval = POWER_SUPPLY_TYPE_BATTERY;
+		is_cable_attached = false;
+		break;
+	case CABLE_TYPE_USB:
+	case CABLE_TYPE_JIG_USB_OFF:
+	case CABLE_TYPE_JIG_USB_ON:
+		value.intval = POWER_SUPPLY_TYPE_USB;
+		is_cable_attached = true;
+		break;
+	case CABLE_TYPE_MHL_VB:
+		value.intval = POWER_SUPPLY_TYPE_MISC;
+		is_cable_attached = true;
+		break;
+	case CABLE_TYPE_TA:
+	case CABLE_TYPE_CARDOCK:
+	case CABLE_TYPE_DESKDOCK:
+	case CABLE_TYPE_JIG_UART_OFF_VB:
+		value.intval = POWER_SUPPLY_TYPE_MAINS;
+		is_cable_attached = true;
+		break;
+	default:
+		pr_err("%s: invalid type:%d\n", __func__, cable_type);
+		return -EINVAL;
+	}
+
+	if (charging_cbs.tsp_set_charging_cable)
+		charging_cbs.tsp_set_charging_cable(value.intval);
+
+	return psy->set_property(psy, POWER_SUPPLY_PROP_ONLINE, &value);
+}
+
+#ifdef CONFIG_USB_HOST_NOTIFY
+static void usb_otg_accessory_power(int enable)
+{
+#ifdef CONFIG_SMB328_CHARGER	/* Q1_EUR_OPEN */
+	u8 on = (u8)!!enable;
+	struct power_supply *psy_sub =
+		power_supply_get_by_name("smb328-charger");
+	union power_supply_propval value;
+	int ret;
+
+	if (!psy_sub) {
+		pr_info("%s: fail to get charger ps\n", __func__);
+		return;
+	}
+
+	value.intval = on;
+	ret = psy_sub->set_property(psy_sub,
+		POWER_SUPPLY_PROP_CHARGE_TYPE, /* only for OTG */
+		&value);
+	if (ret) {
+		pr_info("%s: fail to set OTG (%d)\n",
+			__func__, ret);
+		return;
+	}
+	pr_info("%s: otg power = %d\n", __func__, on);
+#else
+	u8 on = (u8)!!enable;
+
+	gpio_request(GPIO_USB_OTG_EN, "USB_OTG_EN");
+	gpio_direction_output(GPIO_USB_OTG_EN, on);
+	gpio_free(GPIO_USB_OTG_EN);
+	pr_info("%s: otg accessory power = %d\n", __func__, on);
+#endif
+}
+
+static struct host_notifier_platform_data host_notifier_pdata = {
+	.ndev.name	= "usb_otg",
+	.booster	= usb_otg_accessory_power,
+};
+
+struct platform_device host_notifier_device = {
+	.name = "host_notifier",
+	.dev.platform_data = &host_notifier_pdata,
+};
+
+#include "u1-otg.c"
+static void max8997_muic_usb_cb(u8 usb_mode)
+{
+	struct s3c_udc *udc = platform_get_drvdata(&s3c_device_usbgadget);
+	int ret = 0;
+
+	pr_info("otg %s: usb mode=%d\n", __func__, usb_mode);
+
+#if 0
+	u32 lpcharging = __raw_readl(S5P_INFORM2);
+	if (lpcharging == 1) {
+		struct regulator *regulator;
+		pr_info("%s: lpcharging: disable USB\n", __func__);
+
+		ret = c210_change_usb_mode(udc, USB_CABLE_DETACHED);
+		if (ret < 0)
+			pr_warn("%s: fail to change mode!!!\n", __func__);
+
+		regulator = regulator_get(NULL, "safeout1");
+		if (IS_ERR(regulator)) {
+			pr_err("%s: fail to get regulator\n", __func__);
+			return;
+		}
+
+		if (regulator_is_enabled(regulator))
+			regulator_force_disable(regulator);
+		regulator_put(regulator);
+
+		return;
+	}
+#endif
+
+#ifdef CONFIG_TARGET_LOCALE_KOR
+	if (u1_switch_get_usb_lock_state()) {
+		pr_info("%s: usb locked by mdm\n", __func__);
+		return;
+	}
+#endif
+
+	if (udc) {
+		if (usb_mode == USB_OTGHOST_ATTACHED) {
+			usb_otg_accessory_power(1);
+			max8997_muic_charger_cb(CABLE_TYPE_OTG);
+		}
+
+		ret = c210_change_usb_mode(udc, usb_mode);
+		if (ret < 0)
+			pr_err("%s: fail to change mode!!!\n", __func__);
+
+		if (usb_mode == USB_OTGHOST_DETACHED)
+			usb_otg_accessory_power(0);
+	} else
+		pr_info("otg error s3c_udc is null.\n");
+}
+#endif
+
+static void max8997_muic_mhl_cb(int attached)
+{
+	pr_info("%s(%d)\n", __func__, attached);
+
+	if (attached == MAX8997_MUIC_ATTACHED) {
+#ifdef	CONFIG_SAMSUNG_MHL
+		mhl_onoff_ex(true);
+	} else if (attached == MAX8997_MUIC_DETACHED) {
+		mhl_onoff_ex(false);
+#endif
+	}
+}
+
+static bool max8997_muic_is_mhl_attached(void)
+{
+	int val;
+
+	gpio_request(GPIO_MHL_SEL, "MHL_SEL");
+	val = gpio_get_value(GPIO_MHL_SEL);
+	gpio_free(GPIO_MHL_SEL);
+
+	return !!val;
+}
+
+static struct switch_dev switch_dock = {
+	.name = "dock",
+};
+
+static void max8997_muic_deskdock_cb(bool attached)
+{
+	if (attached)
+		switch_set_state(&switch_dock, 1);
+	else
+		switch_set_state(&switch_dock, 0);
+}
+
+static void max8997_muic_cardock_cb(bool attached)
+{
+	if (attached)
+		switch_set_state(&switch_dock, 2);
+	else
+		switch_set_state(&switch_dock, 0);
+}
+
+static void max8997_muic_init_cb(void)
+{
+	int ret;
+
+	/* for CarDock, DeskDock */
+	ret = switch_dev_register(&switch_dock);
+	if (ret < 0)
+		pr_err("Failed to register dock switch. %d\n", ret);
+}
+
+static int max8997_muic_cfg_uart_gpio(void)
+{
+	int val, path;
+
+	val = gpio_get_value(GPIO_UART_SEL);
+	path = val ? UART_PATH_AP : UART_PATH_CP;
+#if 0
+	/* Workaround
+	 * Sometimes sleep current is 15 ~ 20mA if UART path was CP.
+	 */
+	if (path == UART_PATH_CP)
+		gpio_set_value(GPIO_UART_SEL, GPIO_LEVEL_HIGH);
+#endif
+	pr_info("%s: path=%d\n", __func__, path);
+	return path;
+}
+
+static void max8997_muic_jig_uart_cb(int path)
+{
+	int val;
+
+	val = path == UART_PATH_AP ? GPIO_LEVEL_HIGH : GPIO_LEVEL_LOW;
+	gpio_set_value(GPIO_UART_SEL, val);
+	pr_info("%s: val:%d\n", __func__, val);
+}
+
+static int max8997_muic_host_notify_cb(int enable)
+{
+	struct host_notify_dev *ndev = &host_notifier_pdata.ndev;
+
+	if (ndev) {
+		ndev->booster = enable ? NOTIFY_POWER_ON : NOTIFY_POWER_OFF;
+		pr_info("%s: mode %d, enable %d\n", __func__,
+				ndev->mode, enable);
+		return ndev->mode;
+	} else
+		pr_info("%s: host_notify_dev is null, enable %d\n",
+				__func__, enable);
+
+	return -1;
+}
+
+static struct max8997_muic_data max8997_muic = {
+	.usb_cb = max8997_muic_usb_cb,
+	.charger_cb = max8997_muic_charger_cb,
+	.mhl_cb = max8997_muic_mhl_cb,
+	.is_mhl_attached = max8997_muic_is_mhl_attached,
+	.set_safeout = max8997_muic_set_safeout,
+	.init_cb = max8997_muic_init_cb,
+	.deskdock_cb = max8997_muic_deskdock_cb,
+	.cardock_cb = max8997_muic_cardock_cb,
+	.cfg_uart_gpio = max8997_muic_cfg_uart_gpio,
+	.jig_uart_cb = max8997_muic_jig_uart_cb,
+	.host_notify_cb = max8997_muic_host_notify_cb,
+	.gpio_usb_sel = GPIO_USB_SEL,
+};
+
+static struct max8997_buck1_dvs_funcs *buck1_dvs_funcs;
+
+void max8997_set_arm_voltage_table(int *voltage_table, int arr_size)
+{
+	pr_info("%s\n", __func__);
+	if (buck1_dvs_funcs && buck1_dvs_funcs->set_buck1_dvs_table)
+		buck1_dvs_funcs->set_buck1_dvs_table(buck1_dvs_funcs,
+			 voltage_table, arr_size);
+}
+
+static void max8997_register_buck1dvs_funcs(struct max8997_buck1_dvs_funcs *ptr)
+{
+	buck1_dvs_funcs = ptr;
+}
+
+
+static struct max8997_platform_data exynos4_max8997_info = {
+	.num_regulators = ARRAY_SIZE(max8997_regulators),
+	.regulators	= &max8997_regulators[0],
+	.irq_base	= IRQ_BOARD_START,
+	.wakeup		= 1,
+	.buck1_gpiodvs	= false,
+	.buck1_max_vol	= 1350000,
+	.buck2_max_vol	= 1150000,
+	.buck5_max_vol	= 1200000,
+	.buck_set1 = GPIO_BUCK1_EN_A,
+	.buck_set2 = GPIO_BUCK1_EN_B,
+	.buck_set3 = GPIO_BUCK2_EN,
+	.buck_ramp_en = true,
+	.buck_ramp_delay = 10,		/* 10.00mV /us (default) */
+	.flash_cntl_val = 0x5F,	/* Flash safety timer duration: 800msec,
+					   Maximum timer mode */
+	.power = &max8997_power,
+#ifdef CONFIG_VIBETONZ
+	.motor = &max8997_motor,
+#endif
+	.muic = &max8997_muic,
+	.register_buck1_dvs_funcs = max8997_register_buck1dvs_funcs,
+};
+#endif /* CONFIG_REGULATOR_MAX8997 */
+
+/* Bluetooth */
+#ifdef CONFIG_BT_BCM4330
+static struct platform_device bcm4330_bluetooth_device = {
+	.name = "bcm4330_bluetooth",
+	.id = -1,
+};
+#endif				/* CONFIG_BT_BCM4330 */
+
+#ifdef CONFIG_TARGET_LOCALE_KOR
+#define SYSTEM_REV_SND 0x05
+#else
+#define SYSTEM_REV_SND 0x09
+#endif
+
+#ifdef CONFIG_SND_SOC_U1_MC1N2
+static DEFINE_SPINLOCK(mic_bias_lock);
+static bool mc1n2_mainmic_bias;
+static bool mc1n2_submic_bias;
+
+static void set_shared_mic_bias(void)
+{
+	if (system_rev >= 0x03)
+		gpio_set_value(GPIO_MIC_BIAS_EN, mc1n2_mainmic_bias
+			       || mc1n2_submic_bias);
+	else
+		gpio_set_value(GPIO_EAR_MIC_BIAS_EN, mc1n2_mainmic_bias
+			       || mc1n2_submic_bias);
+}
+
+void sec_set_sub_mic_bias(bool on)
+{
+#ifdef CONFIG_SND_SOC_USE_EXTERNAL_MIC_BIAS
+#if defined(CONFIG_MACH_Q1_BD)
+	gpio_set_value(GPIO_SUB_MIC_BIAS_EN, on);
+#else
+	if (system_rev < SYSTEM_REV_SND) {
+		unsigned long flags;
+		spin_lock_irqsave(&mic_bias_lock, flags);
+		mc1n2_submic_bias = on;
+		set_shared_mic_bias();
+		spin_unlock_irqrestore(&mic_bias_lock, flags);
+	} else
+		gpio_set_value(GPIO_SUB_MIC_BIAS_EN, on);
+#endif /* #if defined(CONFIG_MACH_Q1_BD) */
+#endif
+}
+
+void sec_set_main_mic_bias(bool on)
+{
+#ifdef CONFIG_SND_SOC_USE_EXTERNAL_MIC_BIAS
+#if defined(CONFIG_MACH_Q1_BD)
+	gpio_set_value(GPIO_MIC_BIAS_EN, on);
+#else
+	if (system_rev < SYSTEM_REV_SND) {
+		unsigned long flags;
+		spin_lock_irqsave(&mic_bias_lock, flags);
+		mc1n2_mainmic_bias = on;
+		set_shared_mic_bias();
+		spin_unlock_irqrestore(&mic_bias_lock, flags);
+	} else
+		gpio_set_value(GPIO_MIC_BIAS_EN, on);
+#endif /* #if defined(CONFIG_MACH_Q1_BD) */
+#endif
+}
+
+int sec_set_ldo1_constraints(int disabled)
+{
+	struct regulator *regulator;
+
+	if (!disabled) {
+		regulator = regulator_get(NULL, "vadc_3.3v");
+		if (IS_ERR(regulator))
+			return -1;
+		regulator_enable(regulator);
+		regulator_put(regulator);
+	} else {
+		regulator = regulator_get(NULL, "vadc_3.3v");
+		if (IS_ERR(regulator))
+			return -1;
+		if (regulator_is_enabled(regulator))
+			regulator_force_disable(regulator);
+		regulator_put(regulator);
+	}
+
+	return 0;
+}
+
+static struct mc1n2_platform_data mc1n2_pdata = {
+	.set_main_mic_bias = sec_set_main_mic_bias,
+	.set_sub_mic_bias = sec_set_sub_mic_bias,
+	.set_adc_power_constraints = sec_set_ldo1_constraints,
+};
+
+static void u1_sound_init(void)
+{
+#ifdef CONFIG_SND_SOC_USE_EXTERNAL_MIC_BIAS
+	int err;
+
+	err = gpio_request(GPIO_MIC_BIAS_EN, "GPE1");
+	if (err) {
+		pr_err(KERN_ERR "MIC_BIAS_EN GPIO set error!\n");
+		return;
+	}
+	gpio_direction_output(GPIO_MIC_BIAS_EN, 1);
+	gpio_set_value(GPIO_MIC_BIAS_EN, 0);
+	gpio_free(GPIO_MIC_BIAS_EN);
+
+	err = gpio_request(GPIO_EAR_MIC_BIAS_EN, "GPE2");
+	if (err) {
+		pr_err(KERN_ERR "EAR_MIC_BIAS_EN GPIO set error!\n");
+		return;
+	}
+	gpio_direction_output(GPIO_EAR_MIC_BIAS_EN, 1);
+	gpio_set_value(GPIO_EAR_MIC_BIAS_EN, 0);
+	gpio_free(GPIO_EAR_MIC_BIAS_EN);
+
+#if defined(CONFIG_MACH_Q1_BD)
+	err = gpio_request(GPIO_SUB_MIC_BIAS_EN, "submic_bias");
+	if (err) {
+		pr_err(KERN_ERR "SUB_MIC_BIAS_EN GPIO set error!\n");
+		return;
+	}
+	gpio_direction_output(GPIO_SUB_MIC_BIAS_EN, 1);
+	gpio_set_value(GPIO_SUB_MIC_BIAS_EN, 0);
+	gpio_free(GPIO_SUB_MIC_BIAS_EN);
+
+#else
+	if (system_rev >= SYSTEM_REV_SND) {
+		err = gpio_request(GPIO_SUB_MIC_BIAS_EN, "submic_bias");
+		if (err) {
+			pr_err(KERN_ERR "SUB_MIC_BIAS_EN GPIO set error!\n");
+			return;
+		}
+		gpio_direction_output(GPIO_SUB_MIC_BIAS_EN, 0);
+		gpio_free(GPIO_SUB_MIC_BIAS_EN);
+	}
+#endif /* #if defined(CONFIG_MACH_Q1_BD) */
+#endif
+}
+#endif
+
+#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE)
+static void tdmb_set_config_poweron(void)
+{
+	s3c_gpio_cfgpin(GPIO_TDMB_EN, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TDMB_EN, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TDMB_EN, GPIO_LEVEL_LOW);
+
+	s3c_gpio_cfgpin(GPIO_TDMB_RST_N, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TDMB_RST_N, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TDMB_RST_N, GPIO_LEVEL_LOW);
+
+	s3c_gpio_cfgpin(GPIO_TDMB_INT, S3C_GPIO_SFN(GPIO_TDMB_INT_AF));
+	s3c_gpio_setpull(GPIO_TDMB_INT, S3C_GPIO_PULL_NONE);
+}
+static void tdmb_set_config_poweroff(void)
+{
+	s3c_gpio_cfgpin(GPIO_TDMB_EN, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TDMB_EN, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TDMB_EN, GPIO_LEVEL_LOW);
+
+	s3c_gpio_cfgpin(GPIO_TDMB_RST_N, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TDMB_RST_N, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TDMB_RST_N, GPIO_LEVEL_LOW);
+
+	s3c_gpio_cfgpin(GPIO_TDMB_INT, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TDMB_INT, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TDMB_INT, GPIO_LEVEL_LOW);
+}
+
+static void tdmb_gpio_on(void)
+{
+	printk(KERN_DEBUG "tdmb_gpio_on\n");
+
+	tdmb_set_config_poweron();
+
+	gpio_set_value(GPIO_TDMB_EN, GPIO_LEVEL_HIGH);
+	usleep_range(10000, 10000);
+	gpio_set_value(GPIO_TDMB_RST_N, GPIO_LEVEL_LOW);
+	usleep_range(2000, 2000);
+	gpio_set_value(GPIO_TDMB_RST_N, GPIO_LEVEL_HIGH);
+	usleep_range(10000, 10000);
+}
+
+static void tdmb_gpio_off(void)
+{
+	printk(KERN_DEBUG "tdmb_gpio_off\n");
+
+	tdmb_set_config_poweroff();
+
+	gpio_set_value(GPIO_TDMB_RST_N, GPIO_LEVEL_LOW);
+	usleep_range(1000, 1000);
+	gpio_set_value(GPIO_TDMB_EN, GPIO_LEVEL_LOW);
+
+}
+
+static struct tdmb_platform_data tdmb_pdata = {
+	.gpio_on = tdmb_gpio_on,
+	.gpio_off = tdmb_gpio_off,
+};
+
+static struct platform_device tdmb_device = {
+	.name			= "tdmb",
+	.id				= -1,
+	.dev			= {
+		.platform_data = &tdmb_pdata,
+	},
+};
+
+static int __init tdmb_dev_init(void)
+{
+	tdmb_set_config_poweroff();
+	s5p_register_gpio_interrupt(GPIO_TDMB_INT);
+	tdmb_pdata.irq = GPIO_TDMB_IRQ;
+	platform_device_register(&tdmb_device);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_BATTERY_SEC_U1
+static int c1_charger_topoff_cb(void)
+{
+	struct power_supply *psy = power_supply_get_by_name("battery");
+	union power_supply_propval value;
+
+	if (!psy) {
+		pr_err("%s: fail to get battery ps\n", __func__);
+		return -ENODEV;
+	}
+
+	value.intval = POWER_SUPPLY_STATUS_FULL;
+	return psy->set_property(psy, POWER_SUPPLY_PROP_STATUS, &value);
+}
+#endif
+
+#if defined(CONFIG_MACH_Q1_CHN) && \
+	(defined(CONFIG_SMB136_CHARGER_Q1) || defined(CONFIG_SMB328_CHARGER))
+static int c1_charger_ovp_cb(bool is_ovp)
+{
+	struct power_supply *psy = power_supply_get_by_name("battery");
+	union power_supply_propval value;
+
+	if (!psy) {
+		pr_err("%s: fail to get battery ps\n", __func__);
+		return -ENODEV;
+	}
+
+	if (is_ovp)
+		value.intval = POWER_SUPPLY_HEALTH_OVERVOLTAGE;
+	else
+		value.intval = POWER_SUPPLY_HEALTH_GOOD;
+
+	return psy->set_property(psy, POWER_SUPPLY_PROP_VOLTAGE_MAX, &value);
+}
+#endif
+
+#ifdef CONFIG_LEDS_MAX8997
+struct led_max8997_platform_data led_max8997_platform_data = {
+	.name = "leds-sec",
+	.brightness = 0,
+};
+
+struct platform_device sec_device_leds_max8997 = {
+	.name   = "leds-max8997",
+	.id     = -1,
+	.dev = { .platform_data = &led_max8997_platform_data},
+};
+#endif /* CONFIG_LEDS_MAX8997 */
+
+#ifdef CONFIG_CHARGER_MAX8922_U1
+static int max8922_cfg_gpio(void)
+{
+	if (system_rev < HWREV_FOR_BATTERY)
+		return -ENODEV;
+
+	s3c_gpio_cfgpin(GPIO_CHG_EN, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_CHG_EN, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_CHG_EN, GPIO_LEVEL_LOW);
+
+	s3c_gpio_cfgpin(GPIO_CHG_ING_N, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_CHG_ING_N, S3C_GPIO_PULL_NONE);
+
+	s3c_gpio_cfgpin(GPIO_TA_nCONNECTED, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_TA_nCONNECTED, S3C_GPIO_PULL_NONE);
+
+	return 0;
+}
+
+static struct max8922_platform_data max8922_pdata = {
+#ifdef CONFIG_BATTERY_SEC_U1
+	.topoff_cb = c1_charger_topoff_cb,
+#endif
+	.cfg_gpio = max8922_cfg_gpio,
+	.gpio_chg_en = GPIO_CHG_EN,
+	.gpio_chg_ing = GPIO_CHG_ING_N,
+	.gpio_ta_nconnected = GPIO_TA_nCONNECTED,
+};
+
+static struct platform_device max8922_device_charger = {
+	.name = "max8922-charger",
+	.id = -1,
+	.dev.platform_data = &max8922_pdata,
+};
+#endif /* CONFIG_CHARGER_MAX8922_U1 */
+
+#ifdef CONFIG_BATTERY_SAMSUNG
+static struct platform_device samsung_device_battery = {
+	.name = "samsung-fake-battery",
+	.id = -1,
+};
+#endif
+
+#ifdef CONFIG_BATTERY_SEC_U1
+
+#ifdef CONFIG_TARGET_LOCALE_KOR
+/* temperature table for ADC 6 */
+static struct sec_bat_adc_table_data temper_table[] =  {
+	{  264,	 500 },
+	{  275,	 490 },
+	{  286,	 480 },
+	{  293,	 480 },
+	{  299,	 470 },
+	{  306,	 460 },
+	{  324,	 450 },
+	{  341,	 450 },
+	{  354,	 440 },
+	{  368,	 430 },
+	{  381,	 420 },
+	{  396,	 420 },
+	{  411,	 410 },
+	{  427,	 400 },
+	{  442,	 390 },
+	{  457,	 390 },
+	{  472,	 380 },
+	{  487,	 370 },
+	{  503,	 370 },
+	{  518,	 360 },
+	{  533,	 350 },
+	{  554,	 340 },
+	{  574,	 330 },
+	{  595,	 330 },
+	{  615,	 320 },
+	{  636,	 310 },
+	{  656,	 310 },
+	{  677,	 300 },
+	{  697,	 290 },
+	{  718,	 280 },
+	{  738,	 270 },
+	{  761,	 270 },
+	{  784,	 260 },
+	{  806,	 250 },
+	{  829,	 240 },
+	{  852,	 230 },
+	{  875,	 220 },
+	{  898,	 210 },
+	{  920,	 200 },
+	{  943,	 190 },
+	{  966,	 180 },
+	{  990,	 170 },
+	{ 1013,	 160 },
+	{ 1037,	 150 },
+	{ 1060,	 140 },
+	{ 1084,	 130 },
+	{ 1108,	 120 },
+	{ 1131,	 110 },
+	{ 1155,	 100 },
+	{ 1178,	  90 },
+	{ 1202,	  80 },
+	{ 1226,	  70 },
+	{ 1251,	  60 },
+	{ 1275,	  50 },
+	{ 1299,	  40 },
+	{ 1324,	  30 },
+	{ 1348,	  20 },
+	{ 1372,	  10 },
+	{ 1396,	   0 },
+	{ 1421,	 -10 },
+	{ 1445,	 -20 },
+	{ 1468,	 -30 },
+	{ 1491,	 -40 },
+	{ 1513,	 -50 },
+	{ 1536,	 -60 },
+	{ 1559,	 -70 },
+	{ 1577,	 -80 },
+	{ 1596,	 -90 },
+	{ 1614,	 -100 },
+	{ 1619,	 -110 },
+	{ 1632,	 -120 },
+	{ 1658,	 -130 },
+	{ 1667,	 -140 },
+};
+#elif defined(CONFIG_TARGET_LOCALE_NTT)
+/* temperature table for ADC 6 */
+static struct sec_bat_adc_table_data temper_table[] =  {
+	{  273,	 670 },
+	{  289,	 660 },
+	{  304,	 650 },
+	{  314,	 640 },
+	{  325,	 630 },
+	{  337,	 620 },
+	{  347,	 610 },
+	{  361,	 600 },
+	{  376,	 590 },
+	{  391,	 580 },
+	{  406,	 570 },
+	{  417,	 560 },
+	{  431,	 550 },
+	{  447,	 540 },
+	{  474,	 530 },
+	{  491,	 520 },
+	{  499,	 510 },
+	{  511,	 500 },
+	{  519,	 490 },
+	{  547,	 480 },
+	{  568,	 470 },
+	{  585,	 460 },
+	{  597,	 450 },
+	{  614,	 440 },
+	{  629,	 430 },
+	{  647,	 420 },
+	{  672,	 410 },
+	{  690,	 400 },
+	{  720,	 390 },
+	{  735,	 380 },
+	{  755,	 370 },
+	{  775,	 360 },
+	{  795,	 350 },
+	{  818,	 340 },
+	{  841,	 330 },
+	{  864,	 320 },
+	{  887,	 310 },
+	{  909,	 300 },
+	{  932,	 290 },
+	{  954,	 280 },
+	{  976,	 270 },
+	{  999,	 260 },
+	{ 1021,	 250 },
+	{ 1051,	 240 },
+	{ 1077,	 230 },
+	{ 1103,	 220 },
+	{ 1129,	 210 },
+	{ 1155,	 200 },
+	{ 1177,	 190 },
+	{ 1199,	 180 },
+	{ 1220,	 170 },
+	{ 1242,	 160 },
+	{ 1263,	 150 },
+	{ 1284,	 140 },
+	{ 1306,	 130 },
+	{ 1326,	 120 },
+	{ 1349,	 110 },
+	{ 1369,	 100 },
+	{ 1390,	  90 },
+	{ 1411,	  80 },
+	{ 1433,	  70 },
+	{ 1454,	  60 },
+	{ 1474,	  50 },
+	{ 1486,	  40 },
+	{ 1499,	  30 },
+	{ 1512,	  20 },
+	{ 1531,	  10 },
+	{ 1548,	   0 },
+	{ 1570,	 -10 },
+	{ 1597,	 -20 },
+	{ 1624,	 -30 },
+	{ 1633,	 -40 },
+	{ 1643,	 -50 },
+	{ 1652,	 -60 },
+	{ 1663,	 -70 },
+};
+#else
+/* temperature table for ADC 6 */
+static struct sec_bat_adc_table_data temper_table[] = {
+	{  165,	 800 },
+	{  171,	 790 },
+	{  177,	 780 },
+	{  183,	 770 },
+	{  189,	 760 },
+	{  196,	 750 },
+	{  202,	 740 },
+	{  208,	 730 },
+	{  214,	 720 },
+	{  220,	 710 },
+	{  227,	 700 },
+	{  237,	 690 },
+	{  247,	 680 },
+	{  258,	 670 },
+	{  269,	 660 },
+	{  281,	 650 },
+	{  296,	 640 },
+	{  311,	 630 },
+	{  326,	 620 },
+	{  341,	 610 },
+	{  356,	 600 },
+	{  370,	 590 },
+	{  384,	 580 },
+	{  398,	 570 },
+	{  412,	 560 },
+	{  427,	 550 },
+	{  443,	 540 },
+	{  457,	 530 },
+	{  471,	 520 },
+	{  485,	 510 },
+	{  498,	 500 },
+	{  507,	 490 },
+	{  516,	 480 },
+	{  525,	 470 },
+	{  535,	 460 },
+	{  544,	 450 },
+	{  553,	 440 },
+	{  562,	 430 },
+	{  579,	 420 },
+	{  596,	 410 },
+	{  613,	 400 },
+	{  630,	 390 },
+	{  648,	 380 },
+	{  665,	 370 },
+	{  684,	 360 },
+	{  702,	 350 },
+	{  726,	 340 },
+	{  750,	 330 },
+	{  774,	 320 },
+	{  798,	 310 },
+	{  821,	 300 },
+	{  844,	 290 },
+	{  867,	 280 },
+	{  891,	 270 },
+	{  914,	 260 },
+	{  937,	 250 },
+	{  960,	 240 },
+	{  983,	 230 },
+	{ 1007,	 220 },
+	{ 1030,	 210 },
+	{ 1054,	 200 },
+	{ 1083,	 190 },
+	{ 1113,	 180 },
+	{ 1143,	 170 },
+	{ 1173,	 160 },
+	{ 1202,	 150 },
+	{ 1232,	 140 },
+	{ 1262,	 130 },
+	{ 1291,	 120 },
+	{ 1321,	 110 },
+	{ 1351,	 100 },
+	{ 1357,	  90 },
+	{ 1363,	  80 },
+	{ 1369,	  70 },
+	{ 1375,	  60 },
+	{ 1382,	  50 },
+	{ 1402,	  40 },
+	{ 1422,	  30 },
+	{ 1442,	  20 },
+	{ 1462,	  10 },
+	{ 1482,	   0 },
+	{ 1519,	 -10 },
+	{ 1528,	 -20 },
+	{ 1546,	 -30 },
+	{ 1563,	 -40 },
+	{ 1587,	 -50 },
+	{ 1601,	 -60 },
+	{ 1614,	 -70 },
+	{ 1625,  -80 },
+	{ 1641,  -90 },
+	{ 1663, -100 },
+	{ 1678, -110 },
+	{ 1693, -120 },
+	{ 1705, -130 },
+	{ 1720, -140 },
+	{ 1736, -150 },
+	{ 1751, -160 },
+	{ 1767, -170 },
+	{ 1782, -180 },
+	{ 1798, -190 },
+	{ 1815, -200 },
+};
+#endif
+#ifdef CONFIG_TARGET_LOCALE_NTT
+/* temperature table for ADC 7 */
+static struct sec_bat_adc_table_data temper_table_ADC7[] =  {
+	{  300,	 670 },
+	{  310,	 660 },
+	{  324,	 650 },
+	{  330,	 640 },
+	{  340,	 630 },
+	{  353,	 620 },
+	{  368,	 610 },
+	{  394,	 600 },
+	{  394,	 590 },
+	{  401,	 580 },
+	{  418,	 570 },
+	{  431,	 560 },
+	{  445,	 550 },
+	{  460,	 540 },
+	{  478,	 530 },
+	{  496,	 520 },
+	{  507,	 510 },
+	{  513,	 500 },
+	{  531,	 490 },
+	{  553,	 480 },
+	{  571,	 470 },
+	{  586,	 460 },
+	{  604,	 450 },
+	{  614,	 440 },
+	{  640,	 430 },
+	{  659,	 420 },
+	{  669,	 410 },
+	{  707,	 400 },
+	{  722,	 390 },
+	{  740,	 380 },
+	{  769,	 370 },
+	{  783,	 360 },
+	{  816,	 350 },
+	{  818,	 340 },
+	{  845,	 330 },
+	{  859,	 320 },
+	{  889,	 310 },
+	{  929,	 300 },
+	{  942,	 290 },
+	{  955,	 280 },
+	{  972,	 270 },
+	{  996,	 260 },
+	{ 1040,	 250 },
+	{ 1049,	 240 },
+	{ 1073,	 230 },
+	{ 1096,	 220 },
+	{ 1114,	 210 },
+	{ 1159,	 200 },
+	{ 1165,	 190 },
+	{ 1206,	 180 },
+	{ 1214,	 170 },
+	{ 1227,	 160 },
+	{ 1256,	 150 },
+	{ 1275,	 140 },
+	{ 1301,	 130 },
+	{ 1308,	 120 },
+	{ 1357,	 110 },
+	{ 1388,	 100 },
+	{ 1396,	  90 },
+	{ 1430,	  80 },
+	{ 1448,	  70 },
+	{ 1468,	  60 },
+	{ 1499,	  50 },
+	{ 1506,	  40 },
+	{ 1522,	  30 },
+	{ 1535,	  20 },
+	{ 1561,	  10 },
+	{ 1567,	   0 },
+	{ 1595,	 -10 },
+	{ 1620,	 -20 },
+	{ 1637,	 -30 },
+	{ 1640,	 -40 },
+	{ 1668,	 -50 },
+	{ 1669,	 -60 },
+	{ 1688,	 -70 },
+};
+#else
+/* temperature table for ADC 7 */
+static struct sec_bat_adc_table_data temper_table_ADC7[] = {
+	{  193,	 800 },
+	{  200,	 790 },
+	{  207,	 780 },
+	{  215,	 770 },
+	{  223,	 760 },
+	{  230,	 750 },
+	{  238,	 740 },
+	{  245,	 730 },
+	{  252,	 720 },
+	{  259,	 710 },
+	{  266,	 700 },
+	{  277,	 690 },
+	{  288,	 680 },
+	{  300,	 670 },
+	{  311,	 660 },
+	{  326,	 650 },
+	{  340,	 640 },
+	{  354,	 630 },
+	{  368,	 620 },
+	{  382,	 610 },
+	{  397,	 600 },
+	{  410,	 590 },
+	{  423,	 580 },
+	{  436,	 570 },
+	{  449,	 560 },
+	{  462,	 550 },
+	{  475,	 540 },
+	{  488,	 530 },
+	{  491,	 520 },
+	{  503,	 510 },
+	{  535,	 500 },
+	{  548,	 490 },
+	{  562,	 480 },
+	{  576,	 470 },
+	{  590,	 460 },
+	{  603,	 450 },
+	{  616,	 440 },
+	{  630,	 430 },
+	{  646,	 420 },
+	{  663,	 410 },
+	{  679,	 400 },
+	{  696,	 390 },
+	{  712,	 380 },
+	{  728,	 370 },
+	{  745,	 360 },
+	{  762,	 350 },
+	{  784,	 340 },
+	{  806,	 330 },
+	{  828,	 320 },
+	{  850,	 310 },
+	{  872,	 300 },
+	{  895,	 290 },
+	{  919,	 280 },
+	{  942,	 270 },
+	{  966,	 260 },
+	{  989,	 250 },
+	{ 1013,	 240 },
+	{ 1036,	 230 },
+	{ 1060,	 220 },
+	{ 1083,	 210 },
+	{ 1107,	 200 },
+	{ 1133,	 190 },
+	{ 1159,	 180 },
+	{ 1186,	 170 },
+	{ 1212,	 160 },
+	{ 1238,	 150 },
+	{ 1265,	 140 },
+	{ 1291,	 130 },
+	{ 1316,	 120 },
+	{ 1343,	 110 },
+	{ 1370,	 100 },
+	{ 1381,	  90 },
+	{ 1393,	  80 },
+	{ 1404,	  70 },
+	{ 1416,	  60 },
+	{ 1427,	  50 },
+	{ 1453,	  40 },
+	{ 1479,	  30 },
+	{ 1505,	  20 },
+	{ 1531,	  10 },
+	{ 1557,	   0 },
+	{ 1565,	 -10 },
+	{ 1577,	 -20 },
+	{ 1601,	 -30 },
+	{ 1620,	 -40 },
+	{ 1633,	 -50 },
+	{ 1642,	 -60 },
+	{ 1656,	 -70 },
+	{ 1667,  -80 },
+	{ 1674,  -90 },
+	{ 1689, -100 },
+	{ 1704, -110 },
+	{ 1719, -120 },
+	{ 1734, -130 },
+	{ 1749, -140 },
+	{ 1763, -150 },
+	{ 1778, -160 },
+	{ 1793, -170 },
+	{ 1818, -180 },
+	{ 1823, -190 },
+	{ 1838, -200 },
+};
+#endif
+
+#define ADC_CH_TEMPERATURE_PMIC	6
+#define ADC_CH_TEMPERATURE_LCD	7
+
+static unsigned int sec_bat_get_lpcharging_state(void)
+{
+	u32 val = __raw_readl(S5P_INFORM2);
+	struct power_supply *psy = power_supply_get_by_name("max8997-charger");
+	union power_supply_propval value;
+
+	BUG_ON(!psy);
+
+	if (val == 1) {
+		psy->get_property(psy, POWER_SUPPLY_PROP_STATUS, &value);
+		pr_info("%s: charging status: %d\n", __func__, value.intval);
+		if (value.intval == POWER_SUPPLY_STATUS_DISCHARGING)
+			pr_warn("%s: DISCHARGING\n", __func__);
+	}
+
+	pr_info("%s: LP charging:%d\n", __func__, val);
+	return val;
+}
+
+static void sec_bat_initial_check(void)
+{
+	pr_info("%s: connected_cable_type:%d\n",
+		__func__, connected_cable_type);
+	if (connected_cable_type != CABLE_TYPE_NONE)
+		max8997_muic_charger_cb(connected_cable_type);
+}
+
+static struct sec_bat_platform_data sec_bat_pdata = {
+	.fuel_gauge_name	= "fuelgauge",
+	.charger_name		= "max8997-charger",
+#ifdef CONFIG_CHARGER_MAX8922_U1
+	.sub_charger_name	= "max8922-charger",
+#elif defined(CONFIG_MAX8903_CHARGER)
+	.sub_charger_name	= "max8903-charger",
+#endif
+	/* TODO: should provide temperature table */
+	.adc_arr_size		= ARRAY_SIZE(temper_table),
+	.adc_table			= temper_table,
+	.adc_channel		= ADC_CH_TEMPERATURE_PMIC,
+	.adc_sub_arr_size	= ARRAY_SIZE(temper_table_ADC7),
+	.adc_sub_table		= temper_table_ADC7,
+	.adc_sub_channel	= ADC_CH_TEMPERATURE_LCD,
+	.get_lpcharging_state	= sec_bat_get_lpcharging_state,
+#if defined(CONFIG_MACH_Q1_BD)
+	.initial_check		= sec_bat_initial_check,
+#else
+	.initial_check		= NULL,
+#endif
+};
+
+static struct platform_device sec_device_battery = {
+	.name = "sec-battery",
+	.id = -1,
+	.dev.platform_data = &sec_bat_pdata,
+};
+#endif /* CONFIG_BATTERY_SEC_U1 */
+
+#ifdef CONFIG_SMB136_CHARGER_Q1
+static void smb136_set_charger_name(void)
+{
+	sec_bat_pdata.sub_charger_name = "smb136-charger";
+}
+
+static struct smb136_platform_data smb136_pdata = {
+	.topoff_cb = c1_charger_topoff_cb,
+#if defined(CONFIG_MACH_Q1_CHN) && defined(CONFIG_SMB136_CHARGER_Q1)
+	.ovp_cb = c1_charger_ovp_cb,
+#endif
+	.set_charger_name = smb136_set_charger_name,
+	.gpio_chg_en = GPIO_CHG_EN,
+	.gpio_otg_en = GPIO_OTG_EN,
+#if defined(CONFIG_MACH_Q1_CHN) && defined(CONFIG_SMB136_CHARGER_Q1)
+	.gpio_chg_ing = GPIO_CHG_ING_N,
+#endif
+	.gpio_ta_nconnected = 0,	/*GPIO_TA_nCONNECTED,*/
+};
+#endif /* CONFIG_SMB136_CHARGER_Q1 */
+
+#ifdef CONFIG_SMB328_CHARGER
+static void smb328_set_charger_name(void)
+{
+	sec_bat_pdata.sub_charger_name = "smb328-charger";
+}
+
+static struct smb328_platform_data smb328_pdata = {
+	.topoff_cb = c1_charger_topoff_cb,
+#if defined(CONFIG_MACH_Q1_CHN) && defined(CONFIG_SMB328_CHARGER)
+	.ovp_cb = c1_charger_ovp_cb,
+#endif
+	.set_charger_name = smb328_set_charger_name,
+	.gpio_chg_ing = GPIO_CHG_ING_N,
+	.gpio_ta_nconnected = 0,	/*GPIO_TA_nCONNECTED,*/
+};
+#endif /* CONFIG_SMB328_CHARGER */
+
+#if defined(CONFIG_SMB136_CHARGER_Q1) || defined(CONFIG_SMB328_CHARGER)
+static struct i2c_gpio_platform_data gpio_i2c_data19 = {
+	.sda_pin = GPIO_CHG_SDA,
+	.scl_pin = GPIO_CHG_SCL,
+};
+
+static struct platform_device s3c_device_i2c19 = {
+	.name = "i2c-gpio",
+	.id = 19,
+	.dev.platform_data = &gpio_i2c_data19,
+};
+
+static struct i2c_board_info i2c_devs19_emul[] = {
+#ifdef CONFIG_SMB136_CHARGER_Q1
+	{
+		I2C_BOARD_INFO("smb136-charger", SMB136_SLAVE_ADDR>>1),
+		.platform_data	= &smb136_pdata,
+	},
+#endif
+#ifdef CONFIG_SMB328_CHARGER
+	{
+		I2C_BOARD_INFO("smb328-charger", SMB328_SLAVE_ADDR>>1),
+		.platform_data	= &smb328_pdata,
+	},
+#endif
+};
+#endif
+
+#if defined(CONFIG_SEC_THERMISTOR)
+#if defined(CONFIG_MACH_Q1_BD)
+/* temperature table for ADC CH 6 */
+static struct sec_therm_adc_table adc_ch6_table[] = {
+	/* ADC, Temperature */
+	{  165,  800 },
+	{  173,  790 },
+	{  179,  780 },
+	{  185,  770 },
+	{  191,  760 },
+	{  197,  750 },
+	{  203,  740 },
+	{  209,  730 },
+	{  215,  720 },
+	{  221,  710 },
+	{  227,  700 },
+	{  236,  690 },
+	{  247,  680 },
+	{  258,  670 },
+	{  269,  660 },
+	{  281,  650 },
+	{  296,  640 },
+	{  311,  630 },
+	{  326,  620 },
+	{  341,  610 },
+	{  356,  600 },
+	{  372,  590 },
+	{  386,  580 },
+	{  400,  570 },
+	{  414,  560 },
+	{  428,  550 },
+	{  442,  540 },
+	{  456,  530 },
+	{  470,  520 },
+	{  484,  510 },
+	{  498,  500 },
+	{  508,  490 },
+	{  517,  480 },
+	{  526,  470 },
+	{  535,  460 },
+	{  544,  450 },
+	{  553,  440 },
+	{  562,  430 },
+	{  576,  420 },
+	{  594,  410 },
+	{  612,  400 },
+	{  630,  390 },
+	{  648,  380 },
+	{  666,  370 },
+	{  684,  360 },
+	{  702,  350 },
+	{  725,  340 },
+	{  749,  330 },
+	{  773,  320 },
+	{  797,  310 },
+	{  821,  300 },
+	{  847,  290 },
+	{  870,  280 },
+	{  893,  270 },
+	{  916,  260 },
+	{  939,  250 },
+	{  962,  240 },
+	{  985,  230 },
+	{ 1008,  220 },
+	{ 1031,  210 },
+	{ 1054,  200 },
+	{ 1081,  190 },
+	{ 1111,  180 },
+	{ 1141,  170 },
+	{ 1171,  160 },
+	{ 1201,  150 },
+	{ 1231,  140 },
+	{ 1261,  130 },
+	{ 1291,  120 },
+	{ 1321,  110 },
+	{ 1351,  100 },
+	{ 1358,   90 },
+	{ 1364,   80 },
+	{ 1370,   70 },
+	{ 1376,   60 },
+	{ 1382,   50 },
+	{ 1402,   40 },
+	{ 1422,   30 },
+	{ 1442,   20 },
+	{ 1462,   10 },
+	{ 1482,    0 },
+	{ 1519,  -10 },
+	{ 1528,  -20 },
+	{ 1546,  -30 },
+	{ 1563,  -40 },
+	{ 1587,  -50 },
+	{ 1601,  -60 },
+	{ 1614,  -70 },
+	{ 1625,  -80 },
+	{ 1641,  -90 },
+	{ 1663,  -100 },
+	{ 1680,  -110 },
+	{ 1695,  -120 },
+	{ 1710,  -130 },
+	{ 1725,  -140 },
+	{ 1740,  -150 },
+	{ 1755,  -160 },
+	{ 1770,  -170 },
+	{ 1785,  -180 },
+	{ 1800,  -190 },
+	{ 1815,  -200 },
+};
+#else
+/* temperature table for ADC CH 6 */
+static struct sec_therm_adc_table adc_ch6_table[] = {
+	/* ADC, Temperature */
+	{  173,  800 },
+	{  180,  790 },
+	{  188,  780 },
+	{  196,  770 },
+	{  204,  760 },
+	{  212,  750 },
+	{  220,  740 },
+	{  228,  730 },
+	{  236,  720 },
+	{  244,  710 },
+	{  252,  700 },
+	{  259,  690 },
+	{  266,  680 },
+	{  273,  670 },
+	{  289,  660 },
+	{  304,  650 },
+	{  314,  640 },
+	{  325,  630 },
+	{  337,  620 },
+	{  347,  610 },
+	{  361,  600 },
+	{  376,  590 },
+	{  391,  580 },
+	{  406,  570 },
+	{  417,  560 },
+	{  431,  550 },
+	{  447,  540 },
+	{  474,  530 },
+	{  491,  520 },
+	{  499,  510 },
+	{  511,  500 },
+	{  519,  490 },
+	{  547,  480 },
+	{  568,  470 },
+	{  585,  460 },
+	{  597,  450 },
+	{  614,  440 },
+	{  629,  430 },
+	{  647,  420 },
+	{  672,  410 },
+	{  690,  400 },
+	{  720,  390 },
+	{  735,  380 },
+	{  755,  370 },
+	{  775,  360 },
+	{  795,  350 },
+	{  818,  340 },
+	{  841,  330 },
+	{  864,  320 },
+	{  887,  310 },
+	{  909,  300 },
+	{  932,  290 },
+	{  954,  280 },
+	{  976,  270 },
+	{  999,  260 },
+	{ 1021,  250 },
+	{ 1051,  240 },
+	{ 1077,  230 },
+	{ 1103,  220 },
+	{ 1129,  210 },
+	{ 1155,  200 },
+	{ 1177,  190 },
+	{ 1199,  180 },
+	{ 1220,  170 },
+	{ 1242,  160 },
+	{ 1263,  150 },
+	{ 1284,  140 },
+	{ 1306,  130 },
+	{ 1326,  120 },
+	{ 1349,  110 },
+	{ 1369,  100 },
+	{ 1390,   90 },
+	{ 1411,   80 },
+	{ 1433,   70 },
+	{ 1454,   60 },
+	{ 1474,   50 },
+	{ 1486,   40 },
+	{ 1499,   30 },
+	{ 1512,   20 },
+	{ 1531,   10 },
+	{ 1548,    0 },
+	{ 1570,  -10 },
+	{ 1597,  -20 },
+	{ 1624,  -30 },
+	{ 1633,  -40 },
+	{ 1643,  -50 },
+	{ 1652,  -60 },
+	{ 1663,  -70 },
+	{ 1687,  -80 },
+	{ 1711,  -90 },
+	{ 1735,  -100 },
+	{ 1746,  -110 },
+	{ 1757,  -120 },
+	{ 1768,  -130 },
+	{ 1779,  -140 },
+	{ 1790,  -150 },
+	{ 1801,  -160 },
+	{ 1812,  -170 },
+	{ 1823,  -180 },
+	{ 1834,  -190 },
+	{ 1845,  -200 },
+};
+#endif
+
+static struct sec_therm_platform_data sec_therm_pdata = {
+	.adc_channel	= 6,
+	.adc_arr_size	= ARRAY_SIZE(adc_ch6_table),
+	.adc_table	= adc_ch6_table,
+	.polling_interval = 30 * 1000, /* msecs */
+};
+
+static struct platform_device sec_device_thermistor = {
+	.name = "sec-thermistor",
+	.id = -1,
+	.dev.platform_data = &sec_therm_pdata,
+};
+#endif /* CONFIG_SEC_THERMISTOR */
+
+
+struct gpio_keys_button u1_buttons[] = {
+	{
+		.code = KEY_VOLUMEUP,
+		.gpio = GPIO_VOL_UP,
+		.active_low = 1,
+		.type = EV_KEY,
+		.wakeup = 1,
+		.isr_hook = sec_debug_check_crash_key,
+		.debounce_interval = 10,
+	},			/* vol up */
+	{
+		.code = KEY_VOLUMEDOWN,
+		.gpio = GPIO_VOL_DOWN,
+		.active_low = 1,
+		.type = EV_KEY,
+		.wakeup = 1,
+		.isr_hook = sec_debug_check_crash_key,
+		.debounce_interval = 10,
+	},			/* vol down */
+	{
+		.code = KEY_POWER,
+		.gpio = GPIO_nPOWER,
+		.active_low = 1,
+		.type = EV_KEY,
+		.wakeup = 1,
+		.isr_hook = sec_debug_check_crash_key,
+		.debounce_interval = 10,
+	},			/* power key */
+	{
+		.code = KEY_HOME,
+		.gpio = GPIO_OK_KEY,
+		.active_low = 1,
+		.type = EV_KEY,
+		.wakeup = 1,
+		.debounce_interval = 10,
+	},			/* ok key */
+};
+
+struct gpio_keys_platform_data u1_keypad_platform_data = {
+	u1_buttons,
+	ARRAY_SIZE(u1_buttons),
+};
+
+struct platform_device u1_keypad = {
+	.name = "gpio-keys",
+	.dev.platform_data = &u1_keypad_platform_data,
+};
+
+#ifdef CONFIG_SEC_DEV_JACK
+static void sec_set_jack_micbias(bool on)
+{
+#ifdef CONFIG_SND_SOC_USE_EXTERNAL_MIC_BIAS
+#if defined(CONFIG_MACH_Q1_BD)
+	gpio_set_value(GPIO_EAR_MIC_BIAS_EN, on);
+#else
+	if (system_rev >= 3)
+		gpio_set_value(GPIO_EAR_MIC_BIAS_EN, on);
+	else
+		gpio_set_value(GPIO_MIC_BIAS_EN, on);
+#endif /* #if defined(CONFIG_MACH_Q1_BD) */
+#endif /* #ifdef CONFIG_SND_SOC_USE_EXTERNAL_MIC_BIAS */
+}
+
+static struct sec_jack_zone sec_jack_zones[] = {
+	{
+		/* adc == 0, unstable zone, default to 3pole if it stays
+		 * in this range for 300ms (15ms delays, 20 samples)
+		 */
+		.adc_high = 0,
+		.delay_ms = 15,
+		.check_count = 20,
+		.jack_type = SEC_HEADSET_3POLE,
+	},
+	{
+		/* 0 < adc <= 1200, unstable zone, default to 3pole if it stays
+		 * in this range for 300ms (15ms delays, 20 samples)
+		 */
+		.adc_high = 1200,
+		.delay_ms = 10,
+		.check_count = 80,
+		.jack_type = SEC_HEADSET_3POLE,
+	},
+	{
+		/* 950 < adc <= 2600, unstable zone, default to 4pole if it
+		 * stays in this range for 800ms (10ms delays, 80 samples)
+		 */
+		.adc_high = 2600,
+		.delay_ms = 10,
+		.check_count = 10,
+		.jack_type = SEC_HEADSET_4POLE,
+	},
+	{
+		/* 2600 < adc <= 3400, 3 pole zone, default to 3pole if it
+		 * stays in this range for 100ms (10ms delays, 10 samples)
+		 */
+		.adc_high = 3800,
+#if defined(CONFIG_MACH_Q1_BD)
+		.delay_ms = 15,
+		.check_count = 20,
+#else
+		.delay_ms = 10,
+		.check_count = 5,
+#endif
+		.jack_type = SEC_HEADSET_4POLE,
+	},
+	{
+		/* adc > 3400, unstable zone, default to 3pole if it stays
+		 * in this range for two seconds (10ms delays, 200 samples)
+		 */
+		.adc_high = 0x7fffffff,
+		.delay_ms = 10,
+		.check_count = 200,
+		.jack_type = SEC_HEADSET_3POLE,
+	},
+};
+
+/* To support 3-buttons earjack */
+static struct sec_jack_buttons_zone sec_jack_buttons_zones[] = {
+	{
+		/* 0 <= adc <=170, stable zone */
+		.code = KEY_MEDIA,
+		.adc_low = 0,
+#if defined(CONFIG_TARGET_LOCALE_NTT)
+		.adc_high = 150,
+#else
+		.adc_high = 170,
+#endif
+	},
+	{
+		/* 171 <= adc <= 370, stable zone */
+		.code = KEY_VOLUMEUP,
+#if defined(CONFIG_TARGET_LOCALE_NTT)
+		.adc_low = 151,
+#else
+		.adc_low = 171,
+#endif
+		.adc_high = 370,
+	},
+	{
+		/* 371 <= adc <= 850, stable zone */
+		.code = KEY_VOLUMEDOWN,
+		.adc_low = 371,
+		.adc_high = 850,
+	},
+};
+
+static struct sec_jack_platform_data sec_jack_data = {
+	.set_micbias_state = sec_set_jack_micbias,
+	.zones = sec_jack_zones,
+	.num_zones = ARRAY_SIZE(sec_jack_zones),
+	.buttons_zones = sec_jack_buttons_zones,
+	.num_buttons_zones = ARRAY_SIZE(sec_jack_buttons_zones),
+	.det_gpio = GPIO_DET_35,
+	.send_end_gpio = GPIO_EAR_SEND_END,
+};
+
+static struct platform_device sec_device_jack = {
+	.name = "sec_jack",
+	.id = 1,		/* will be used also for gpio_event id */
+	.dev.platform_data = &sec_jack_data,
+};
+#endif
+
+void tsp_register_callback(void *function)
+{
+	charging_cbs.tsp_set_charging_cable = function;
+}
+
+void tsp_read_ta_status(void *ta_status)
+{
+	*(bool *)ta_status = is_cable_attached;
+}
+#ifdef CONFIG_TOUCHSCREEN_ATMEL_MXT224_GC
+static void mxt224_power_on(void)
+{
+	s3c_gpio_cfgpin(GPIO_TSP_LDO_ON, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TSP_LDO_ON, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TSP_LDO_ON, 1);
+	mdelay(70);
+	s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_NONE);
+	s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_SFN(0xf));
+	mdelay(40);
+}
+
+static void mxt224_power_off(void)
+{
+	s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_DOWN);
+
+	s3c_gpio_cfgpin(GPIO_TSP_LDO_ON, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TSP_LDO_ON, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TSP_LDO_ON, 0);
+}
+
+static u8 t7_config[] = {GEN_POWERCONFIG_T7,
+	64, 255, 50
+};
+static u8 t8_config[] = {GEN_ACQUISITIONCONFIG_T8,
+	10, 0, 5, 1, 0, 0, 9, 27
+};
+static u8 t9_config[] = {TOUCH_MULTITOUCHSCREEN_T9,
+	143, 0, 0, 18, 11, 0, 16, 32, 2, 0,
+	0, 3, 1, 46, 10, 5, 40, 10, 31, 3,
+	223, 1, 0, 0, 0, 0, 0, 0, 0, 0,
+	18
+};
+static u8 t15_config[] = {TOUCH_KEYARRAY_T15,
+	131, 16, 11, 2, 1, 0, 0, 45, 4, 0,
+	0
+};
+static u8 t18_config[] = {SPT_COMCONFIG_T18,
+	0, 0
+};
+static u8 t19_config[] = {SPT_GPIOPWM_T19,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 0, 0, 0
+};
+static u8 t20_config[] = {PROCI_GRIPFACESUPPRESSION_T20,
+	19, 0, 0, 5, 5, 0, 0, 30, 20, 4, 15,
+	10
+};
+static u8 t22_config[] = {PROCG_NOISESUPPRESSION_T22,
+	5, 0, 0, 0, 0, 0, 0, 3, 27, 0,
+	0, 29, 34, 39, 49, 58, 3
+};
+static u8 t23_config[] = {TOUCH_PROXIMITY_T23,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 0, 0
+};
+static u8 t24_config[] = {PROCI_ONETOUCHGESTUREPROCESSOR_T24,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+static u8 t25_config[] = {SPT_SELFTEST_T25,
+	0, 0
+};
+static u8 t27_config[] = {PROCI_TWOTOUCHGESTUREPROCESSOR_T27,
+	0, 0, 0, 0, 0, 0, 0
+};
+static u8 t28_config[] = {SPT_CTECONFIG_T28,
+	1, 0, 2, 16, 63, 60
+};
+static u8 end_config[] = {RESERVED_T255};
+
+static const u8 *mxt224_config[] = {
+	t7_config,
+	t8_config,
+	t9_config,
+	t15_config,
+	t18_config,
+	t19_config,
+	t20_config,
+	t22_config,
+	t23_config,
+	t24_config,
+	t25_config,
+	t27_config,
+	t28_config,
+	end_config,
+};
+
+
+static struct mxt224_platform_data mxt224_data = {
+	.max_finger_touches = 10,
+	.gpio_read_done = GPIO_TSP_INT,
+	.config = mxt224_config,
+	.min_x = 0,
+	.max_x = 479,
+	.min_y = 0,
+	.max_y = 799,
+	.min_z = 0,
+	.max_z = 255,
+	.min_w = 0,
+	.max_w = 30,
+	.power_on = mxt224_power_on,
+	.power_off = mxt224_power_off,
+};
+
+
+#endif
+#ifdef CONFIG_TOUCHSCREEN_ATMEL_MXT224_U1
+static void mxt224_power_on(void)
+{
+	s3c_gpio_cfgpin(GPIO_TSP_LDO_ON, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TSP_LDO_ON, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TSP_LDO_ON, 1);
+	mdelay(70);
+	s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_NONE);
+	s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_SFN(0xf));
+	mdelay(40);
+	/* printk("mxt224_power_on is finished\n"); */
+}
+
+static void mxt224_power_off(void)
+{
+	s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_DOWN);
+
+	s3c_gpio_cfgpin(GPIO_TSP_LDO_ON, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TSP_LDO_ON, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TSP_LDO_ON, 0);
+	/* printk("mxt224_power_off is finished\n"); */
+}
+
+/*
+  Configuration for MXT224
+*/
+#define MXT224_THRESHOLD_BATT		40
+#define MXT224_THRESHOLD_BATT_INIT		55
+#define MXT224_THRESHOLD_CHRG		70
+#define MXT224_NOISE_THRESHOLD_BATT		30
+#define MXT224_NOISE_THRESHOLD_CHRG		40
+#define MXT224_MOVFILTER_BATT		11
+#define MXT224_MOVFILTER_CHRG		47
+#define MXT224_ATCHCALST		4
+#define MXT224_ATCHCALTHR		35
+
+static u8 t7_config[] = { GEN_POWERCONFIG_T7,
+	48,			/* IDLEACQINT */
+	255,			/* ACTVACQINT */
+	25			/* ACTV2IDLETO: 25 * 200ms = 5s */
+};
+
+static u8 t8_config[] = { GEN_ACQUISITIONCONFIG_T8,
+	10, 0, 5, 1, 0, 0, MXT224_ATCHCALST, MXT224_ATCHCALTHR
+};				/*byte 3: 0 */
+
+static u8 t9_config[] = { TOUCH_MULTITOUCHSCREEN_T9,
+	131, 0, 0, 19, 11, 0, 32, MXT224_THRESHOLD_BATT, 2, 1,
+	0,
+	15,			/* MOVHYSTI */
+	1, MXT224_MOVFILTER_BATT, MXT224_MAX_MT_FINGERS, 5, 40, 10, 31, 3,
+	223, 1, 0, 0, 0, 0, 143, 55, 143, 90, 18
+};
+
+static u8 t18_config[] = { SPT_COMCONFIG_T18,
+	0, 1
+};
+
+static u8 t20_config[] = { PROCI_GRIPFACESUPPRESSION_T20,
+	7, 0, 0, 0, 0, 0, 0, 30, 20, 4, 15, 10
+};
+
+static u8 t22_config[] = { PROCG_NOISESUPPRESSION_T22,
+	143, 0, 0, 0, 0, 0, 0, 3, MXT224_NOISE_THRESHOLD_BATT, 0,
+	0, 29, 34, 39, 49, 58, 3
+};
+
+static u8 t28_config[] = { SPT_CTECONFIG_T28,
+			   0, 0, 3, 16, 19, 60
+};
+static u8 end_config[] = { RESERVED_T255 };
+
+static const u8 *mxt224_config[] = {
+	t7_config,
+	t8_config,
+	t9_config,
+	t18_config,
+	t20_config,
+	t22_config,
+	t28_config,
+	end_config,
+};
+
+/*
+  Configuration for MXT224-E
+*/
+#ifdef CONFIG_TARGET_LOCALE_NAATT_TEMP
+#define MXT224E_THRESHOLD_BATT		50
+#define MXT224E_THRESHOLD_CHRG		40
+#define MXT224E_T48_THRESHOLD_BATT		33
+#define MXT224E_CALCFG_BATT		0x72
+#define MXT224E_CALCFG_CHRG		0x72
+#define MXT224E_ATCHFRCCALTHR_NORMAL		40
+#define MXT224E_ATCHFRCCALRATIO_NORMAL		55
+#define MXT224E_GHRGTIME_BATT		22
+#define MXT224E_GHRGTIME_CHRG		22
+#define MXT224E_ATCHCALST		4
+#define MXT224E_ATCHCALTHR		35
+#define MXT224E_BLEN_BATT		32
+#define MXT224E_T48_BLEN_BATT		0
+#define MXT224E_BLEN_CHRG		0
+#define MXT224E_MOVFILTER_BATT		14
+#define MXT224E_MOVFILTER_CHRG		46
+#define MXT224E_ACTVSYNCSPERX_NORMAL		29
+#define MXT224E_NEXTTCHDI_NORMAL		0
+#define MXT224E_NEXTTCHDI_CHRG		1
+#else
+#define MXT224E_THRESHOLD_BATT		50
+#define MXT224E_THRESHOLD_CHRG		40
+#define MXT224E_CALCFG_BATT		0x42
+#define MXT224E_CALCFG_CHRG		0x52
+#if defined(CONFIG_TARGET_LOCALE_NA)
+#define MXT224E_ATCHFRCCALTHR_NORMAL		45
+#define MXT224E_ATCHFRCCALRATIO_NORMAL		60
+#else
+#define MXT224E_ATCHFRCCALTHR_NORMAL		40
+#define MXT224E_ATCHFRCCALRATIO_NORMAL		55
+#endif
+#define MXT224E_GHRGTIME_BATT		27
+#define MXT224E_GHRGTIME_CHRG		22
+#define MXT224E_ATCHCALST		4
+#define MXT224E_ATCHCALTHR		35
+#define MXT224E_BLEN_BATT		32
+#define MXT224E_BLEN_CHRG		16
+#define MXT224E_MOVFILTER_BATT		13
+#define MXT224E_MOVFILTER_CHRG		46
+#define MXT224E_ACTVSYNCSPERX_NORMAL		32
+#define MXT224E_NEXTTCHDI_NORMAL		0
+#endif
+
+#if defined(CONFIG_TARGET_LOCALE_NAATT_TEMP)
+static u8 t7_config_e[] = { GEN_POWERCONFIG_T7,
+	48, 255, 25
+};
+
+static u8 t8_config_e[] = { GEN_ACQUISITIONCONFIG_T8,
+	MXT224E_GHRGTIME_BATT, 0, 5, 1, 0, 0,
+	MXT224E_ATCHCALST, MXT224E_ATCHCALTHR,
+	MXT224E_ATCHFRCCALTHR_NORMAL,
+	MXT224E_ATCHFRCCALRATIO_NORMAL
+};
+
+static u8 t9_config_e[] = { TOUCH_MULTITOUCHSCREEN_T9,
+	139, 0, 0, 19, 11, 0, MXT224E_BLEN_BATT, MXT224E_THRESHOLD_BATT, 2, 1,
+	10,
+	15,			/* MOVHYSTI */
+	1, MXT224E_MOVFILTER_BATT, MXT224_MAX_MT_FINGERS, 5, 40, 10, 31, 3,
+	223, 1, 10, 10, 10, 10, 143, 40, 143, 80,
+	18, 15, 50, 50, MXT224E_NEXTTCHDI_NORMAL
+};
+
+static u8 t15_config_e[] = { TOUCH_KEYARRAY_T15,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t18_config_e[] = { SPT_COMCONFIG_T18,
+	0, 0
+};
+
+static u8 t23_config_e[] = { TOUCH_PROXIMITY_T23,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t25_config_e[] = { SPT_SELFTEST_T25,
+	0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t38_config_e[] = { SPT_USERDATA_T38,
+	0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t40_config_e[] = { PROCI_GRIPSUPPRESSION_T40,
+	0, 0, 0, 0, 0
+};
+
+static u8 t42_config_e[] = { PROCI_TOUCHSUPPRESSION_T42,
+	0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t46_config_e[] = { SPT_CTECONFIG_T46,
+	0, 3, 16, MXT224E_ACTVSYNCSPERX_NORMAL, 0, 0, 1, 0, 0
+};
+
+static u8 t47_config_e[] = { PROCI_STYLUS_T47,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t48_config_e[] = { PROCG_NOISESUPPRESSION_T48,
+	3, 132, MXT224E_CALCFG_BATT, 20, 0, 0, 0, 0, 1, 2,
+	0, 0, 0, 6, 6, 0, 0, 64, 4, 64,
+	10, 0, 10, 5, 0, 20, 0, 5, 0, 0,
+	0, 0, 0, 0, MXT224E_T48_BLEN_BATT, MXT224E_T48_THRESHOLD_BATT, 2,
+	15,
+	1, MXT224E_MOVFILTER_BATT,
+	MXT224_MAX_MT_FINGERS, 5, 40, 235, 235, 10, 10, 160, 50, 143,
+	80, 18, 15, MXT224E_NEXTTCHDI_NORMAL
+};
+
+static u8 t48_config_chrg_e[] = { PROCG_NOISESUPPRESSION_T48,
+	3, 132, MXT224E_CALCFG_CHRG, 0, 0, 0, 0, 0, 10, 15,
+	0, 0, 0, 6, 6, 0, 0, 64, 4, 64,
+	10, 0, 9, 5, 0, 15, 0, 20, 0, 0,
+	0, 0, 0, 0, MXT224E_BLEN_CHRG, MXT224E_THRESHOLD_CHRG, 2,
+	15,			/* MOVHYSTI */
+	1, 47,
+	MXT224_MAX_MT_FINGERS, 5, 40, 235, 235, 10, 10, 160, 50, 143,
+	80, 18, 10, MXT224E_NEXTTCHDI_CHRG
+};
+
+#else
+static u8 t7_config_e[] = { GEN_POWERCONFIG_T7,
+	48,			/* IDLEACQINT */
+	255,			/* ACTVACQINT */
+	25			/* ACTV2IDLETO: 25 * 200ms = 5s */
+};
+
+static u8 t8_config_e[] = { GEN_ACQUISITIONCONFIG_T8,
+	MXT224E_GHRGTIME_BATT, 0, 5, 1, 0, 0,
+	MXT224E_ATCHCALST, MXT224E_ATCHCALTHR,
+	MXT224E_ATCHFRCCALTHR_NORMAL,
+	MXT224E_ATCHFRCCALRATIO_NORMAL
+};
+
+/* MXT224E_0V5_CONFIG */
+/* NEXTTCHDI added */
+#ifdef CONFIG_TARGET_LOCALE_NA
+#ifdef CONFIG_MACH_U1_NA_USCC_REV05
+static u8 t9_config_e[] = { TOUCH_MULTITOUCHSCREEN_T9,
+	139, 0, 0, 19, 11, 0, MXT224E_BLEN_BATT, MXT224E_THRESHOLD_BATT, 2, 1,
+	10,
+	10,			/* MOVHYSTI */
+	1, MXT224E_MOVFILTER_BATT, MXT224_MAX_MT_FINGERS, 5, 40, 10, 31, 3,
+	223, 1, 10, 10, 10, 10, 143, 40, 143, 80,
+	18, 15, 50, 50, 0
+};
+
+#else
+static u8 t9_config_e[] = { TOUCH_MULTITOUCHSCREEN_T9,
+	139, 0, 0, 19, 11, 0, MXT224E_BLEN_BATT, MXT224E_THRESHOLD_BATT, 2, 1,
+	10,
+	10,			/* MOVHYSTI */
+	1, MXT224E_MOVFILTER_BATT, MXT224_MAX_MT_FINGERS, 5, 40, 10, 31, 3,
+	223, 1, 10, 10, 10, 10, 143, 40, 143, 80,
+	18, 15, 50, 50, 2
+};
+#endif
+#else
+static u8 t9_config_e[] = { TOUCH_MULTITOUCHSCREEN_T9,
+	139, 0, 0, 19, 11, 0, MXT224E_BLEN_BATT, MXT224E_THRESHOLD_BATT, 2, 1,
+	10,
+	15,			/* MOVHYSTI */
+	1, MXT224E_MOVFILTER_BATT, MXT224_MAX_MT_FINGERS, 5, 40, 10, 31, 3,
+	223, 1, 10, 10, 10, 10, 143, 40, 143, 80,
+	18, 15, 50, 50, MXT224E_NEXTTCHDI_NORMAL
+};
+#endif
+
+static u8 t15_config_e[] = { TOUCH_KEYARRAY_T15,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t18_config_e[] = { SPT_COMCONFIG_T18,
+	0, 0
+};
+
+static u8 t23_config_e[] = { TOUCH_PROXIMITY_T23,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t25_config_e[] = { SPT_SELFTEST_T25,
+	0, 0, 0, 0, 0, 0, 0, 0
+};
+
+#ifdef CONFIG_MACH_U1_NA_USCC_REV05
+static u8 t38_config_e[] = { SPT_USERDATA_T38,
+	0, 1, 13, 19, 44, 0, 0, 0
+};
+#else
+static u8 t38_config_e[] = { SPT_USERDATA_T38,
+	0, 1, 14, 23, 44, 0, 0, 0
+};
+#endif
+
+static u8 t40_config_e[] = { PROCI_GRIPSUPPRESSION_T40,
+	0, 0, 0, 0, 0
+};
+
+static u8 t42_config_e[] = { PROCI_TOUCHSUPPRESSION_T42,
+	0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t46_config_e[] = { SPT_CTECONFIG_T46,
+	0, 3, 16, MXT224E_ACTVSYNCSPERX_NORMAL, 0, 0, 1, 0, 0
+};
+
+static u8 t47_config_e[] = { PROCI_STYLUS_T47,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*MXT224E_0V5_CONFIG */
+#ifdef CONFIG_TARGET_LOCALE_NA
+#ifdef CONFIG_MACH_U1_NA_USCC_REV05
+static u8 t48_config_chrg_e[] = { PROCG_NOISESUPPRESSION_T48,
+	3, 132, 0x52, 0, 0, 0, 0, 0, 10, 15,
+	0, 0, 0, 6, 6, 0, 0, 64, 4, 64,
+	10, 0, 10, 5, 0, 19, 0, 20, 0, 0,
+	0, 0, 0, 0, 0, 40, 2,	/*blen=0,threshold=50 */
+	10,			/* MOVHYSTI */
+	1, 47,
+	10, 5, 40, 240, 245, 10, 10, 148, 50, 143,
+	80, 18, 10, 0
+};
+
+static u8 t48_config_e[] = { PROCG_NOISESUPPRESSION_T48,
+	3, 132, 0x40, 0, 0, 0, 0, 0, 10, 15,
+	0, 0, 0, 6, 6, 0, 0, 64, 4, 64,
+	10, 0, 20, 5, 0, 38, 0, 5, 0, 0,	/*byte 27 original value 20 */
+	0, 0, 0, 0, 32, MXT224E_THRESHOLD, 2,
+	10,
+	1, 46,
+	MXT224_MAX_MT_FINGERS, 5, 40, 10, 0, 10, 10, 143, 40, 143,
+	80, 18, 15, 0
+};
+#else
+static u8 t48_config_chrg_e[] = { PROCG_NOISESUPPRESSION_T48,
+	1, 4, 0x50, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 6, 6, 0, 0, 100, 4, 64,
+	10, 0, 20, 5, 0, 38, 0, 20, 0, 0,
+	0, 0, 0, 0, 0, 40, 2,	/*blen=0,threshold=50 */
+	10,			/* MOVHYSTI */
+	1, 15,
+	10, 5, 40, 240, 245, 10, 10, 148, 50, 143,
+	80, 18, 10, 2
+};
+
+static u8 t48_config_e[] = { PROCG_NOISESUPPRESSION_T48,
+	1, 4, 0x40, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 6, 6, 0, 0, 100, 4, 64,
+	10, 0, 20, 5, 0, 38, 0, 5, 0, 0,	/*byte 27 original value 20 */
+	0, 0, 0, 0, 32, 50, 2,
+	10,
+	1, 46,
+	MXT224_MAX_MT_FINGERS, 5, 40, 10, 0, 10, 10, 143, 40, 143,
+	80, 18, 15, 2
+};
+#endif				/*CONFIG_MACH_U1_NA_USCC_REV05 */
+#else
+static u8 t48_config_chrg_e[] = { PROCG_NOISESUPPRESSION_T48,
+	3, 132, MXT224E_CALCFG_CHRG, 0, 0, 0, 0, 0, 10, 15,
+	0, 0, 0, 6, 6, 0, 0, 64, 4, 64,
+	10, 0, 9, 5, 0, 15, 0, 20, 0, 0,
+	0, 0, 0, 0, 0, MXT224E_THRESHOLD_CHRG, 2,
+	15,			/* MOVHYSTI */
+	1, 47,
+	MXT224_MAX_MT_FINGERS, 5, 40, 235, 235, 10, 10, 160, 50, 143,
+	80, 18, 10, 0
+};
+
+static u8 t48_config_e[] = { PROCG_NOISESUPPRESSION_T48,
+	3, 132, MXT224E_CALCFG_BATT, 0, 0, 0, 0, 0, 10, 15,
+	0, 0, 0, 6, 6, 0, 0, 48, 4, 48,
+	10, 0, 10, 5, 0, 20, 0, 5, 0, 0,	/*byte 27 original value 20 */
+	0, 0, 0, 0, 32, MXT224E_THRESHOLD_BATT, 2,
+	15,
+	1, 46,
+	MXT224_MAX_MT_FINGERS, 5, 40, 10, 10, 10, 10, 143, 40, 143,
+	80, 18, 15, 0
+};
+#endif				/*CONFIG_TARGET_LOCALE_NA */
+#endif				/*CONFIG_TARGET_LOCALE_NAATT */
+
+static u8 end_config_e[] = { RESERVED_T255 };
+
+static const u8 *mxt224e_config[] = {
+	t7_config_e,
+	t8_config_e,
+	t9_config_e,
+	t15_config_e,
+	t18_config_e,
+	t23_config_e,
+	t25_config_e,
+	t38_config_e,
+	t40_config_e,
+	t42_config_e,
+	t46_config_e,
+	t47_config_e,
+	t48_config_e,
+	end_config_e,
+};
+
+static struct mxt224_platform_data mxt224_data = {
+	.max_finger_touches = MXT224_MAX_MT_FINGERS,
+	.gpio_read_done = GPIO_TSP_INT,
+	.config = mxt224_config,
+	.config_e = mxt224e_config,
+	.t48_config_batt_e = t48_config_e,
+	.t48_config_chrg_e = t48_config_chrg_e,
+	.min_x = 0,
+	.max_x = 479,
+	.min_y = 0,
+	.max_y = 799,
+	.min_z = 0,
+	.max_z = 255,
+	.min_w = 0,
+	.max_w = 30,
+	.atchcalst = MXT224_ATCHCALST,
+	.atchcalsthr = MXT224_ATCHCALTHR,
+	.tchthr_batt = MXT224_THRESHOLD_BATT,
+	.tchthr_batt_init = MXT224_THRESHOLD_BATT_INIT,
+	.tchthr_charging = MXT224_THRESHOLD_CHRG,
+	.noisethr_batt = MXT224_NOISE_THRESHOLD_BATT,
+	.noisethr_charging = MXT224_NOISE_THRESHOLD_CHRG,
+	.movfilter_batt = MXT224_MOVFILTER_BATT,
+	.movfilter_charging = MXT224_MOVFILTER_CHRG,
+	.atchcalst_e = MXT224E_ATCHCALST,
+	.atchcalsthr_e = MXT224E_ATCHCALTHR,
+	.tchthr_batt_e = MXT224E_THRESHOLD_BATT,
+	.tchthr_charging_e = MXT224E_THRESHOLD_CHRG,
+	.calcfg_batt_e = MXT224E_CALCFG_BATT,
+	.calcfg_charging_e = MXT224E_CALCFG_CHRG,
+	.atchfrccalthr_e = MXT224E_ATCHFRCCALTHR_NORMAL,
+	.atchfrccalratio_e = MXT224E_ATCHFRCCALRATIO_NORMAL,
+	.chrgtime_batt_e = MXT224E_GHRGTIME_BATT,
+	.chrgtime_charging_e = MXT224E_GHRGTIME_CHRG,
+	.blen_batt_e = MXT224E_BLEN_BATT,
+	.blen_charging_e = MXT224E_BLEN_CHRG,
+	.movfilter_batt_e = MXT224E_MOVFILTER_BATT,
+	.movfilter_charging_e = MXT224E_MOVFILTER_CHRG,
+	.actvsyncsperx_e = MXT224E_ACTVSYNCSPERX_NORMAL,
+	.nexttchdi_e = MXT224E_NEXTTCHDI_NORMAL,
+	.power_on = mxt224_power_on,
+	.power_off = mxt224_power_off,
+	.register_cb = tsp_register_callback,
+	.read_ta_status = tsp_read_ta_status,
+};
+
+#endif				/*CONFIG_TOUCHSCREEN_ATMEL_MXT224_U1 */
+
+#if defined(CONFIG_TOUCHSCREEN_ATMEL_MXT540E)
+static void mxt540e_power_on(void)
+{
+	gpio_request(GPIO_TSP_SDA, "TSP_SDA");
+	gpio_request(GPIO_TSP_SCL, "TSP_SCL");
+
+	s3c_gpio_cfgpin(GPIO_TSP_SDA, S3C_GPIO_SFN(3));
+	s3c_gpio_cfgpin(GPIO_TSP_SCL, S3C_GPIO_SFN(3));
+	s3c_gpio_setpull(GPIO_TSP_SDA, S3C_GPIO_PULL_UP);
+	s3c_gpio_setpull(GPIO_TSP_SCL, S3C_GPIO_PULL_UP);
+
+	s3c_gpio_cfgpin(GPIO_TSP_LDO_ON, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TSP_LDO_ON, S3C_GPIO_PULL_NONE);
+	gpio_direction_output(GPIO_TSP_LDO_ON, GPIO_LEVEL_HIGH);
+	msleep(MXT540E_HW_RESET_TIME);
+	s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_NONE);
+	s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_SFN(0xf));
+
+	gpio_free(GPIO_TSP_SDA);
+	gpio_free(GPIO_TSP_SCL);
+}
+
+static void mxt540e_power_off(void)
+{
+	gpio_request(GPIO_TSP_SDA, "TSP_SDA");
+	gpio_request(GPIO_TSP_SCL, "TSP_SCL");
+
+	s3c_gpio_cfgpin(GPIO_TSP_SDA, S3C_GPIO_OUTPUT);
+	s3c_gpio_cfgpin(GPIO_TSP_SCL, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TSP_SDA, S3C_GPIO_PULL_NONE);
+	s3c_gpio_setpull(GPIO_TSP_SCL, S3C_GPIO_PULL_NONE);
+	gpio_direction_output(GPIO_TSP_SDA, GPIO_LEVEL_LOW);
+	gpio_direction_output(GPIO_TSP_SCL, GPIO_LEVEL_LOW);
+
+	s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_DOWN);
+
+	s3c_gpio_cfgpin(GPIO_TSP_LDO_ON, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TSP_LDO_ON, S3C_GPIO_PULL_NONE);
+	gpio_direction_output(GPIO_TSP_LDO_ON, GPIO_LEVEL_LOW);
+
+	gpio_free(GPIO_TSP_SDA);
+	gpio_free(GPIO_TSP_SCL);
+}
+
+static void mxt540e_power_on_oled(void)
+{
+	gpio_request(GPIO_OLED_DET, "OLED_DET");
+
+	mxt540e_power_on();
+
+	s3c_gpio_setpull(GPIO_OLED_DET, S3C_GPIO_PULL_NONE);
+	s3c_gpio_cfgpin(GPIO_OLED_DET, S3C_GPIO_SFN(0xf));
+
+	gpio_free(GPIO_OLED_DET);
+
+	printk(KERN_INFO "[TSP] %s\n", __func__);
+}
+
+static void mxt540e_power_off_oled(void)
+{
+	gpio_request(GPIO_OLED_DET, "OLED_DET");
+
+	s3c_gpio_cfgpin(GPIO_OLED_DET, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_OLED_DET, S3C_GPIO_PULL_NONE);
+	gpio_direction_output(GPIO_OLED_DET, GPIO_LEVEL_LOW);
+
+	mxt540e_power_off();
+
+	gpio_free(GPIO_OLED_DET);
+
+	printk(KERN_INFO "[TSP] %s\n", __func__);
+}
+
+/*
+  Configuration for MXT540E
+*/
+#define MXT540E_MAX_MT_FINGERS		10
+#define MXT540E_CHRGTIME_BATT		48
+#define MXT540E_CHRGTIME_CHRG		48
+#define MXT540E_THRESHOLD_BATT		50
+#define MXT540E_THRESHOLD_CHRG		40
+#define MXT540E_ACTVSYNCSPERX_BATT		34
+#define MXT540E_ACTVSYNCSPERX_CHRG		34
+#define MXT540E_CALCFG_BATT		98
+#define MXT540E_CALCFG_CHRG		114
+#define MXT540E_ATCHFRCCALTHR_WAKEUP		8
+#define MXT540E_ATCHFRCCALRATIO_WAKEUP		180
+#define MXT540E_ATCHFRCCALTHR_NORMAL		40
+#define MXT540E_ATCHFRCCALRATIO_NORMAL		55
+
+static u8 t7_config_e[] = { GEN_POWERCONFIG_T7,
+	48, 255, 50
+};
+
+static u8 t8_config_e[] = { GEN_ACQUISITIONCONFIG_T8,
+	MXT540E_CHRGTIME_BATT, 0, 5, 1, 0, 0, 4, 20,
+	MXT540E_ATCHFRCCALTHR_WAKEUP, MXT540E_ATCHFRCCALRATIO_WAKEUP
+};
+
+static u8 t9_config_e[] = { TOUCH_MULTITOUCHSCREEN_T9,
+	131, 0, 0, 16, 26, 0, 192, MXT540E_THRESHOLD_BATT, 2, 6,
+	10, 10, 10, 80, MXT540E_MAX_MT_FINGERS, 20, 40, 20, 31, 3,
+	255, 4, 3, 3, 2, 2, 136, 60, 136, 40,
+	18, 15, 0, 0, 0
+};
+
+static u8 t15_config_e[] = { TOUCH_KEYARRAY_T15,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t18_config_e[] = { SPT_COMCONFIG_T18,
+	0, 0
+};
+
+static u8 t19_config_e[] = { SPT_GPIOPWM_T19,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t24_config_e[] = { PROCI_ONETOUCHGESTUREPROCESSOR_T24,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t25_config_e[] = { SPT_SELFTEST_T25,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t27_config_e[] = { PROCI_TWOTOUCHGESTUREPROCESSOR_T27,
+	0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t40_config_e[] = { PROCI_GRIPSUPPRESSION_T40,
+	0, 0, 0, 0, 0
+};
+
+static u8 t42_config_e[] = { PROCI_TOUCHSUPPRESSION_T42,
+	0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t43_config_e[] = { SPT_DIGITIZER_T43,
+	0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t46_config_e[] = { SPT_CTECONFIG_T46,
+	0, 0, 16, MXT540E_ACTVSYNCSPERX_BATT, 0, 0, 1, 0
+};
+
+static u8 t47_config_e[] = { PROCI_STYLUS_T47,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t48_config_e[] = { PROCG_NOISESUPPRESSION_T48,
+	3, 132, MXT540E_CALCFG_BATT, 0, 0, 0, 0, 0, 1, 2,
+	0, 0, 0, 6, 6, 0, 0, 28, 4, 64,
+	10, 0, 20, 6, 0, 30, 0, 0, 0, 0,
+	0, 0, 0, 0, 192, MXT540E_THRESHOLD_BATT, 2, 10, 10, 47,
+	MXT540E_MAX_MT_FINGERS, 5, 20, 253, 0, 7, 7, 160, 55, 136,
+	0, 18, 5, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 0
+};
+
+static u8 t48_config_chrg_e[] = { PROCG_NOISESUPPRESSION_T48,
+	3, 132, MXT540E_CALCFG_CHRG, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 6, 6, 0, 0, 36, 4, 64,
+	10, 0, 10, 6, 0, 20, 0, 0, 0, 0,
+	0, 0, 0, 0, 112, MXT540E_THRESHOLD_CHRG, 2, 10, 5, 47,
+	MXT540E_MAX_MT_FINGERS, 5, 20, 253, 0, 7, 7, 160, 55, 136,
+	0, 18, 10, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 0
+};
+
+static u8 t52_config_e[] = { TOUCH_PROXKEY_T52,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t55_config_e[] = {ADAPTIVE_T55,
+	0, 0, 0, 0, 0, 0
+};
+
+static u8 t57_config_e[] = {SPT_GENERICDATA_T57,
+	243, 25, 1
+};
+
+static u8 t61_config_e[] = {SPT_TIMER_T61,
+	0, 0, 0, 0, 0
+};
+
+static u8 end_config_e[] = { RESERVED_T255 };
+
+static const u8 *mxt540e_config[] = {
+	t7_config_e,
+	t8_config_e,
+	t9_config_e,
+	t15_config_e,
+	t18_config_e,
+	t19_config_e,
+	t24_config_e,
+	t25_config_e,
+	t27_config_e,
+	t40_config_e,
+	t42_config_e,
+	t43_config_e,
+	t46_config_e,
+	t47_config_e,
+	t48_config_e,
+	t52_config_e,
+	t55_config_e,
+	t57_config_e,
+	t61_config_e,
+	end_config_e,
+};
+
+struct mxt540e_platform_data mxt540e_data = {
+	.max_finger_touches = MXT540E_MAX_MT_FINGERS,
+	.gpio_read_done = GPIO_TSP_INT,
+	.config_e = mxt540e_config,
+	.min_x = 0,
+	.max_x = 799,
+	.min_y = 0,
+	.max_y = 1279,
+	.min_z = 0,
+	.max_z = 255,
+	.min_w = 0,
+	.max_w = 30,
+	.chrgtime_batt = MXT540E_CHRGTIME_BATT,
+	.chrgtime_charging = MXT540E_CHRGTIME_CHRG,
+	.tchthr_batt = MXT540E_THRESHOLD_BATT,
+	.tchthr_charging = MXT540E_THRESHOLD_CHRG,
+	.actvsyncsperx_batt = MXT540E_ACTVSYNCSPERX_BATT,
+	.actvsyncsperx_charging = MXT540E_ACTVSYNCSPERX_CHRG,
+	.calcfg_batt_e = MXT540E_CALCFG_BATT,
+	.calcfg_charging_e = MXT540E_CALCFG_CHRG,
+	.atchfrccalthr_e = MXT540E_ATCHFRCCALTHR_NORMAL,
+	.atchfrccalratio_e = MXT540E_ATCHFRCCALRATIO_NORMAL,
+	.t48_config_batt_e = t48_config_e,
+	.t48_config_chrg_e = t48_config_chrg_e,
+	.power_on = mxt540e_power_on,
+	.power_off = mxt540e_power_off,
+	.power_on_with_oleddet = mxt540e_power_on_oled,
+	.power_off_with_oleddet = mxt540e_power_off_oled,
+	.register_cb = tsp_register_callback,
+	.read_ta_status = tsp_read_ta_status,
+};
+#endif
+
+#ifdef CONFIG_EPEN_WACOM_G5SP
+static int p6_wacom_init_hw(void);
+static int p6_wacom_exit_hw(void);
+static int p6_wacom_suspend_hw(void);
+static int p6_wacom_resume_hw(void);
+static int p6_wacom_early_suspend_hw(void);
+static int p6_wacom_late_resume_hw(void);
+static int p6_wacom_reset_hw(void);
+static void p6_wacom_register_callbacks(struct wacom_g5_callbacks *cb);
+
+static struct wacom_g5_platform_data p6_wacom_platform_data = {
+	.x_invert = 1,
+	.y_invert = 0,
+	.xy_switch = 1,
+	.min_x = 0,
+	.max_x = WACOM_POSX_MAX,
+	.min_y = 0,
+	.max_y = WACOM_POSY_MAX,
+	.min_pressure = 0,
+	.max_pressure = WACOM_PRESSURE_MAX,
+	.gpio_pendct = GPIO_PEN_PDCT,
+	.init_platform_hw = p6_wacom_init_hw,
+/*	.exit_platform_hw =,	*/
+	.suspend_platform_hw = p6_wacom_suspend_hw,
+	.resume_platform_hw = p6_wacom_resume_hw,
+	.early_suspend_platform_hw = p6_wacom_early_suspend_hw,
+	.late_resume_platform_hw = p6_wacom_late_resume_hw,
+	.reset_platform_hw = p6_wacom_reset_hw,
+	.register_cb = p6_wacom_register_callbacks,
+};
+
+#endif
+
+#ifdef CONFIG_EPEN_WACOM_G5SP
+static int p6_wacom_suspend_hw(void)
+{
+	return p6_wacom_early_suspend_hw();
+}
+
+static int p6_wacom_resume_hw(void)
+{
+	return p6_wacom_late_resume_hw();
+}
+
+static int p6_wacom_early_suspend_hw(void)
+{
+	gpio_direction_input(GPIO_PEN_PDCT);
+	gpio_set_value(GPIO_PEN_RESET, 0);
+	return 0;
+}
+
+static int p6_wacom_late_resume_hw(void)
+{
+	gpio_direction_output(GPIO_PEN_PDCT, 1);
+	gpio_set_value(GPIO_PEN_RESET, 1);
+	return 0;
+}
+
+static int p6_wacom_reset_hw(void)
+{
+	p6_wacom_early_suspend_hw();
+	msleep(200);
+	p6_wacom_late_resume_hw();
+
+	return 0;
+}
+
+static void p6_wacom_register_callbacks(struct wacom_g5_callbacks *cb)
+{
+	wacom_callbacks = cb;
+};
+#endif /* CONFIG_EPEN_WACOM_G5SP */
+
+
+#ifdef CONFIG_S3C_DEV_I2C8_EMUL
+static struct i2c_board_info i2c_devs8_emul[];
+#endif
+#ifdef CONFIG_KEYBOARD_CYPRESS_TOUCH
+static void touchkey_init_hw(void)
+{
+	gpio_request(GPIO_3_TOUCH_INT, "3_TOUCH_INT");
+	s3c_gpio_setpull(GPIO_3_TOUCH_INT, S3C_GPIO_PULL_NONE);
+	s5p_register_gpio_interrupt(GPIO_3_TOUCH_INT);
+	gpio_direction_input(GPIO_3_TOUCH_INT);
+
+	i2c_devs8_emul[0].irq = gpio_to_irq(GPIO_3_TOUCH_INT);
+	irq_set_irq_type(gpio_to_irq(GPIO_3_TOUCH_INT), IRQF_TRIGGER_FALLING);
+	s3c_gpio_cfgpin(GPIO_3_TOUCH_INT, S3C_GPIO_SFN(0xf));
+}
+
+static int touchkey_suspend(void)
+{
+	struct regulator *regulator;
+
+	regulator = regulator_get(NULL, TK_REGULATOR_NAME);
+	if (IS_ERR(regulator))
+		return 0;
+	if (regulator_is_enabled(regulator))
+		regulator_force_disable(regulator);
+
+	regulator_put(regulator);
+
+	return 1;
+}
+
+static int touchkey_resume(void)
+{
+	struct regulator *regulator;
+
+	regulator = regulator_get(NULL, TK_REGULATOR_NAME);
+	if (IS_ERR(regulator))
+		return 0;
+	regulator_enable(regulator);
+	regulator_put(regulator);
+
+	return 1;
+}
+
+static int touchkey_power_on(bool on)
+{
+	int ret;
+
+	if (on) {
+		gpio_direction_output(GPIO_3_TOUCH_INT, 1);
+		irq_set_irq_type(gpio_to_irq(GPIO_3_TOUCH_INT), IRQF_TRIGGER_FALLING);
+		s3c_gpio_cfgpin(GPIO_3_TOUCH_INT, S3C_GPIO_SFN(0xf));
+		s3c_gpio_setpull(GPIO_3_TOUCH_INT, S3C_GPIO_PULL_NONE);
+	}
+	else
+		gpio_direction_input(GPIO_3_TOUCH_INT);
+
+	if (on)
+		ret = touchkey_resume();
+	else
+		ret = touchkey_suspend();
+
+	return ret;
+}
+
+static int touchkey_led_power_on(bool on)
+{
+#if defined(LED_LDO_WITH_EN_PIN)
+	if (on) {
+		gpio_direction_output(GPIO_3_TOUCH_EN, 1);
+	} else {
+		gpio_direction_output(GPIO_3_TOUCH_EN, 0);
+	}
+#else
+	struct regulator *regulator;
+
+	if (on) {
+		regulator = regulator_get(NULL, "touch_led");
+		if (IS_ERR(regulator))
+			return 0;
+		regulator_enable(regulator);
+		regulator_put(regulator);
+	} else {
+		regulator = regulator_get(NULL, "touch_led");
+		if (IS_ERR(regulator))
+			return 0;
+		if (regulator_is_enabled(regulator))
+			regulator_force_disable(regulator);
+		regulator_put(regulator);
+	}
+#endif
+	return 1;
+}
+
+static struct touchkey_platform_data touchkey_pdata = {
+	.gpio_sda = GPIO_3_TOUCH_SDA,
+	.gpio_scl = GPIO_3_TOUCH_SCL,
+	.gpio_int = GPIO_3_TOUCH_INT,
+	.init_platform_hw = touchkey_init_hw,
+	.suspend = touchkey_suspend,
+	.resume = touchkey_resume,
+	.power_on = touchkey_power_on,
+	.led_power_on = touchkey_led_power_on,
+};
+#endif /*CONFIG_KEYBOARD_CYPRESS_TOUCH*/
+
+
+
+#ifdef CONFIG_I2C_S3C2410
+/* I2C0 */
+static struct i2c_board_info i2c_devs0[] __initdata = {
+	{I2C_BOARD_INFO("24c128", 0x50),},	/* Samsung S524AD0XD1 */
+	{I2C_BOARD_INFO("24c128", 0x52),},	/* Samsung S524AD0XD1 */
+};
+
+#ifdef CONFIG_S3C_DEV_I2C1
+/* I2C1 */
+static struct i2c_board_info i2c_devs1[] __initdata = {
+	{
+		I2C_BOARD_INFO("k3g", 0x69),
+		.irq = IRQ_EINT(1),
+	},
+	{
+		I2C_BOARD_INFO("k3dh", 0x19),
+	},
+#ifdef CONFIG_MACH_Q1_BD
+	{
+		I2C_BOARD_INFO("bmp180", 0x77),
+	},
+#endif
+};
+#endif
+#ifdef CONFIG_S3C_DEV_I2C2
+/* I2C2 */
+static struct i2c_board_info i2c_devs2[] __initdata = {
+};
+#endif
+#ifdef CONFIG_S3C_DEV_I2C3
+/* I2C3 */
+static struct i2c_board_info i2c_devs3[] __initdata = {
+#ifdef CONFIG_TOUCHSCREEN_ATMEL_MXT224_U1
+	{
+		I2C_BOARD_INFO(MXT224_DEV_NAME, 0x4a),
+		.platform_data = &mxt224_data,
+	},
+#endif
+#ifdef CONFIG_TOUCHSCREEN_ATMEL_MXT540E
+	{
+		I2C_BOARD_INFO(MXT540E_DEV_NAME, 0x4c),
+		.platform_data = &mxt540e_data,
+	},
+#endif
+#ifdef CONFIG_TOUCHSCREEN_ATMEL_MXT224_GC
+	{
+		I2C_BOARD_INFO(MXT224_DEV_NAME, 0x4a),
+		.platform_data = &mxt224_data,
+	},
+#endif
+};
+#endif
+#ifdef CONFIG_S3C_DEV_I2C4
+/* I2C4 */
+static struct i2c_board_info i2c_devs4[] __initdata = {
+};
+#endif
+
+#ifdef CONFIG_S3C_DEV_I2C5
+/* I2C5 */
+static struct i2c_board_info i2c_devs5[] __initdata = {
+#ifdef CONFIG_MFD_MAX8998
+	{
+		I2C_BOARD_INFO("lp3974", 0x66),
+		.platform_data = &s5pv310_max8998_info,
+	},
+#endif
+#ifdef CONFIG_MFD_MAX8997
+	{
+		I2C_BOARD_INFO("max8997", (0xcc >> 1)),
+		.platform_data = &exynos4_max8997_info,
+	},
+#endif
+};
+#endif
+#ifdef CONFIG_S3C_DEV_I2C6
+/* I2C6 */
+static struct i2c_board_info i2c_devs6[] __initdata = {
+#ifdef CONFIG_SND_SOC_U1_MC1N2
+	{
+		I2C_BOARD_INFO("mc1n2", 0x3a),	/* MC1N2 */
+		.platform_data = &mc1n2_pdata,
+	},
+#endif
+#ifdef CONFIG_EPEN_WACOM_G5SP
+	{
+		I2C_BOARD_INFO("wacom_g5sp_i2c", 0x56),
+		.platform_data = &p6_wacom_platform_data,
+	},
+#endif
+};
+#endif
+#ifdef CONFIG_S3C_DEV_I2C7
+static struct akm8975_platform_data akm8975_pdata = {
+	.gpio_data_ready_int = GPIO_MSENSE_INT,
+};
+
+/* I2C7 */
+static struct i2c_board_info i2c_devs7[] __initdata = {
+	{
+		I2C_BOARD_INFO("ak8975", 0x0C),
+		.platform_data = &akm8975_pdata,
+	},
+#ifdef CONFIG_VIDEO_TVOUT
+	{
+		I2C_BOARD_INFO("s5p_ddc", (0x74 >> 1)),
+	},
+#endif
+};
+
+static void s3c_i2c7_cfg_gpio_u1(struct platform_device *dev)
+{
+	/* u1 magnetic sensor & MHL are using i2c7
+	 * and the i2c line has external pull-resistors.
+	 */
+	s3c_gpio_cfgall_range(EXYNOS4_GPD0(2), 2,
+		S3C_GPIO_SFN(3), S3C_GPIO_PULL_NONE);
+}
+
+static struct s3c2410_platform_i2c default_i2c7_data __initdata = {
+	.bus_num	= 7,
+	.flags		= 0,
+	.slave_addr	= 0x10,
+	.frequency	= 100*1000,
+	.sda_delay	= 100,
+	.cfg_gpio	= s3c_i2c7_cfg_gpio_u1,
+};
+#endif
+
+#ifdef CONFIG_S3C_DEV_I2C8_EMUL
+static struct i2c_gpio_platform_data gpio_i2c_data8 = {
+	.sda_pin = GPIO_3_TOUCH_SDA,
+	.scl_pin = GPIO_3_TOUCH_SCL,
+};
+
+struct platform_device s3c_device_i2c8 = {
+	.name = "i2c-gpio",
+	.id = 8,
+	.dev.platform_data = &gpio_i2c_data8,
+};
+
+/* I2C8 */
+static struct i2c_board_info i2c_devs8_emul[] = {
+#ifdef CONFIG_KEYBOARD_CYPRESS_TOUCH
+	{
+		I2C_BOARD_INFO("sec_touchkey", 0x20),
+		.platform_data = &touchkey_pdata,
+	},
+#endif
+};
+#endif
+
+#ifdef CONFIG_S3C_DEV_I2C9_EMUL
+static struct i2c_gpio_platform_data gpio_i2c_data9 = {
+	.sda_pin = GPIO_FUEL_SDA,
+	.scl_pin = GPIO_FUEL_SCL,
+};
+
+struct platform_device s3c_device_i2c9 = {
+	.name = "i2c-gpio",
+	.id = 9,
+	.dev.platform_data = &gpio_i2c_data9,
+};
+
+#ifdef CONFIG_BATTERY_MAX17042_FUELGAUGE_U1
+
+struct max17042_reg_data max17042_init_data[] = {
+	{ MAX17042_REG_CGAIN,		0x00,	0x00 },
+	{ MAX17042_REG_MISCCFG,		0x03,	0x00 },
+	{ MAX17042_REG_LEARNCFG,	0x07,	0x00 },
+	/* RCOMP: 0x0050 2011.02.29 from MAXIM */
+	{ MAX17042_REG_RCOMP,		0x50,	0x00 },
+};
+
+struct max17042_reg_data max17042_alert_init_data[] = {
+#ifdef CONFIG_MACH_Q1_BD
+	/* SALRT Threshold setting to 1% wake lock */
+	{ MAX17042_REG_SALRT_TH,	0x01,	0xFF },
+#elif defined(CONFIG_TARGET_LOCALE_KOR)
+	/* SALRT Threshold setting to 1% wake lock */
+	{ MAX17042_REG_SALRT_TH,	0x01,	0xFF },
+#else
+	/* SALRT Threshold setting to 2% => 1% wake lock */
+	{ MAX17042_REG_SALRT_TH,	0x02,	0xFF },
+#endif
+	/* VALRT Threshold setting (disable) */
+	{ MAX17042_REG_VALRT_TH,	0x00,	0xFF },
+	/* TALRT Threshold setting (disable) */
+	{ MAX17042_REG_TALRT_TH,	0x80,	0x7F },
+};
+
+bool max17042_is_low_batt(void)
+{
+	struct power_supply *psy = power_supply_get_by_name("battery");
+	union power_supply_propval value;
+
+	if (!psy) {
+		pr_err("%s: fail to get battery ps\n", __func__);
+		return -ENODEV;
+	}
+
+	if (!(psy->get_property(psy, POWER_SUPPLY_PROP_CAPACITY, &value)))
+		if (value.intval > SEC_BATTERY_SOC_3_6)
+			return false;
+
+	return true;
+}
+EXPORT_SYMBOL(max17042_is_low_batt);
+
+static int max17042_low_batt_cb(void)
+{
+	struct power_supply *psy = power_supply_get_by_name("battery");
+	union power_supply_propval value;
+
+	if (!psy) {
+		pr_err("%s: fail to get battery ps\n", __func__);
+		return -ENODEV;
+	}
+
+	value.intval = POWER_SUPPLY_CAPACITY_LEVEL_CRITICAL;
+	return psy->set_property(psy, POWER_SUPPLY_PROP_CAPACITY_LEVEL, &value);
+}
+
+#ifdef RECAL_SOC_FOR_MAXIM
+static bool max17042_need_soc_recal(void)
+{
+	pr_info("%s: HW(0x%x)\n", __func__, system_rev);
+
+	if (system_rev >= NO_NEED_RECAL_SOC_HW_REV)
+		return false;
+	else
+		return true;
+}
+#endif
+
+static struct max17042_platform_data s5pv310_max17042_info = {
+	.low_batt_cb = max17042_low_batt_cb,
+	.init = max17042_init_data,
+	.init_size = sizeof(max17042_init_data),
+	.alert_init = max17042_alert_init_data,
+	.alert_init_size = sizeof(max17042_alert_init_data),
+	.alert_gpio = GPIO_FUEL_ALERT,
+	.alert_irq = 0,
+	.enable_current_sense = false,
+	.enable_gauging_temperature = true,
+#ifdef RECAL_SOC_FOR_MAXIM
+	.need_soc_recal = max17042_need_soc_recal,
+#endif
+};
+#endif	/* CONFIG_BATTERY_MAX17042_U1 */
+
+/* I2C9 */
+static struct i2c_board_info i2c_devs9_emul[] __initdata = {
+#ifdef CONFIG_BATTERY_MAX17042_FUELGAUGE_U1
+	{
+		I2C_BOARD_INFO("max17042", 0x36),
+		.platform_data	= &s5pv310_max17042_info,
+		.irq = IRQ_EINT(19),
+	},
+#endif
+#ifdef CONFIG_BATTERY_MAX17040
+	{
+		I2C_BOARD_INFO("max17040", 0x36),
+	},
+#endif
+};
+#endif
+
+#ifdef CONFIG_S3C_DEV_I2C10_EMUL
+static struct i2c_gpio_platform_data gpio_i2c_data10 __initdata = {
+	.sda_pin = GPIO_USB_SDA,
+	.scl_pin = GPIO_USB_SCL,
+};
+
+struct platform_device s3c_device_i2c10 = {
+	.name = "i2c-gpio",
+	.id = 10,
+	.dev.platform_data = &gpio_i2c_data10,
+};
+
+/* I2C10 */
+static struct fsa9480_platform_data fsa9480_info = {
+};
+
+static struct i2c_board_info i2c_devs10_emul[] __initdata = {
+	{
+		I2C_BOARD_INFO("fsa9480", 0x25),
+		.platform_data = &fsa9480_info,
+	},
+};
+#endif
+
+#ifdef CONFIG_S3C_DEV_I2C11_EMUL
+static struct i2c_gpio_platform_data gpio_i2c_data11 = {
+	.sda_pin = GPIO_PS_ALS_SDA,
+	.scl_pin = GPIO_PS_ALS_SCL,
+};
+
+struct platform_device s3c_device_i2c11 = {
+	.name = "i2c-gpio",
+	.id = 11,
+	.dev.platform_data = &gpio_i2c_data11,
+};
+
+/* I2C11 */
+#ifdef CONFIG_SENSORS_CM3663
+static int cm3663_ldo(bool on)
+{
+	struct regulator *regulator;
+
+	if (on) {
+		regulator = regulator_get(NULL, "vled");
+		if (IS_ERR(regulator))
+			return 0;
+		regulator_enable(regulator);
+		regulator_put(regulator);
+	} else {
+		regulator = regulator_get(NULL, "vled");
+		if (IS_ERR(regulator))
+			return 0;
+		if (regulator_is_enabled(regulator))
+			regulator_force_disable(regulator);
+		regulator_put(regulator);
+	}
+
+	return 0;
+}
+
+static struct cm3663_platform_data cm3663_pdata = {
+	.proximity_power = cm3663_ldo,
+};
+#ifdef CONFIG_SENSORS_PAS2M110
+static struct pas2m110_platform_data pas2m110_pdata = {
+	.proximity_power = cm3663_ldo,
+};
+#endif
+#endif
+#ifdef CONFIG_SENSORS_GP2A_ANALOG
+static int gp2a_power(bool on)
+{
+	struct regulator *regulator;
+
+	if (on) {
+		regulator = regulator_get(NULL, "vled");
+		if (IS_ERR(regulator))
+			return 0;
+		regulator_enable(regulator);
+		regulator_put(regulator);
+	} else {
+		regulator = regulator_get(NULL, "vled");
+		if (IS_ERR(regulator))
+			return 0;
+		if (regulator_is_enabled(regulator))
+			regulator_force_disable(regulator);
+		regulator_put(regulator);
+	}
+
+	return 0;
+}
+
+static struct gp2a_platform_data gp2a_pdata = {
+	.p_out = GPIO_PS_ALS_INT,
+	.power = gp2a_power,
+};
+#endif
+
+static struct i2c_board_info i2c_devs11_emul[] __initdata = {
+#ifdef CONFIG_MACH_U1_BD
+	{
+		I2C_BOARD_INFO("cm3663", 0x20),
+		.irq = GPIO_PS_ALS_INT,
+		.platform_data = &cm3663_pdata,
+	},
+#ifdef CONFIG_SENSORS_PAS2M110
+	{
+		I2C_BOARD_INFO("pas2m110", (0x88>>1)),
+		.irq = GPIO_PS_ALS_INT,
+		.platform_data = &pas2m110_pdata,
+	},
+#endif
+#endif
+#ifdef CONFIG_MACH_Q1_BD
+	{
+		I2C_BOARD_INFO("gp2a", (0x88 >> 1)),
+		.platform_data = &gp2a_pdata,
+	},
+#endif
+};
+#endif
+
+#ifdef CONFIG_S3C_DEV_I2C14_EMUL
+static struct i2c_gpio_platform_data i2c14_platdata = {
+	.sda_pin = GPIO_NFC_SDA,
+	.scl_pin = GPIO_NFC_SCL,
+	.udelay = 2,
+	.sda_is_open_drain = 0,
+	.scl_is_open_drain = 0,
+	.scl_is_output_only = 0,
+};
+
+static struct platform_device s3c_device_i2c14 = {
+	.name = "i2c-gpio",
+	.id = 14,
+	.dev.platform_data = &i2c14_platdata,
+};
+
+static struct pn544_i2c_platform_data pn544_pdata = {
+	.irq_gpio = GPIO_NFC_IRQ,
+	.ven_gpio = GPIO_NFC_EN,
+	.firm_gpio = GPIO_NFC_FIRM,
+};
+
+static struct i2c_board_info i2c_devs14[] __initdata = {
+	{
+		I2C_BOARD_INFO("pn544", 0x2b),
+		.irq = IRQ_EINT(15),
+		.platform_data = &pn544_pdata,
+	},
+};
+
+static unsigned int nfc_gpio_table[][4] = {
+	{GPIO_NFC_IRQ, S3C_GPIO_INPUT, GPIO_LEVEL_NONE, S3C_GPIO_PULL_DOWN},
+	{GPIO_NFC_EN, S3C_GPIO_OUTPUT, GPIO_LEVEL_LOW, S3C_GPIO_PULL_NONE},
+	{GPIO_NFC_FIRM, S3C_GPIO_OUTPUT, GPIO_LEVEL_LOW, S3C_GPIO_PULL_NONE},
+/*	{GPIO_NFC_SCL, S3C_GPIO_INPUT, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, */
+/*	{GPIO_NFC_SDA, S3C_GPIO_INPUT, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, */
+};
+
+void nfc_setup_gpio(void)
+{
+	/* s3c_config_gpio_alive_table(ARRAY_SIZE(nfc_gpio_table),
+	   nfc_gpio_table); */
+	int array_size = ARRAY_SIZE(nfc_gpio_table);
+	u32 i, gpio;
+	for (i = 0; i < array_size; i++) {
+		gpio = nfc_gpio_table[i][0];
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(nfc_gpio_table[i][1]));
+		s3c_gpio_setpull(gpio, nfc_gpio_table[i][3]);
+		if (nfc_gpio_table[i][2] != GPIO_LEVEL_NONE)
+			gpio_set_value(gpio, nfc_gpio_table[i][2]);
+	}
+
+	/* s3c_gpio_cfgpin(GPIO_NFC_IRQ, EINT_MODE); */
+	/* s3c_gpio_setpull(GPIO_NFC_IRQ, S3C_GPIO_PULL_DOWN); */
+}
+#endif
+
+#if defined(CONFIG_VIDEO_S5K5BAFX)
+static struct i2c_gpio_platform_data i2c12_platdata = {
+	.sda_pin = VT_CAM_SDA_18V,
+	.scl_pin = VT_CAM_SCL_18V,
+	.udelay = 2,		/* 250KHz */
+	.sda_is_open_drain = 0,
+	.scl_is_open_drain = 0,
+	.scl_is_output_only = 0,
+};
+
+static struct platform_device s3c_device_i2c12 = {
+	.name = "i2c-gpio",
+	.id = 12,
+	.dev.platform_data = &i2c12_platdata,
+};
+
+/* I2C12 */
+static struct i2c_board_info i2c_devs12_emul[] __initdata = {
+	/* need to work here */
+};
+#endif
+
+#ifdef CONFIG_FM_SI4709_MODULE
+static struct i2c_gpio_platform_data i2c16_platdata = {
+	.sda_pin		= GPIO_FM_SDA_28V,
+	.scl_pin		= GPIO_FM_SCL_28V,
+	.udelay			= 2,	/* 250KHz */
+	.sda_is_open_drain	= 0,
+	.scl_is_open_drain	= 0,
+	.scl_is_output_only	= 0,
+};
+
+static struct platform_device s3c_device_i2c16 = {
+	.name					= "i2c-gpio",
+	.id						= 16,
+	.dev.platform_data	= &i2c16_platdata,
+};
+
+static struct i2c_board_info i2c_devs16[] __initdata = {
+	{
+		I2C_BOARD_INFO("Si4709", (0x20 >> 1)),
+	},
+};
+#endif
+
+#endif
+
+#ifdef CONFIG_TOUCHSCREEN_S3C2410
+static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
+	.delay = 10000,
+	.presc = 49,
+	.oversampling_shift = 2,
+	.cal_x_max = 480,
+	.cal_y_max = 800,
+	.cal_param = {
+		33, -9156, 34720100, 14819, 57, -4234968, 65536,
+	},
+};
+#endif
+
+#ifdef	CONFIG_ISDBT_FC8100
+static struct	i2c_board_info i2c_devs17[]	__initdata = {
+	{
+		I2C_BOARD_INFO("isdbti2c", 0x77),
+	},
+};
+
+static struct i2c_gpio_platform_data i2c17_platdata = {
+	.sda_pin		= GPIO_ISDBT_SDA_28V,
+	.scl_pin		= GPIO_ISDBT_SCL_28V,
+	.udelay			= 3,	/*  kHz	*/
+	.sda_is_open_drain	= 0,
+	.scl_is_open_drain	= 0,
+	.scl_is_output_only = 0,
+};
+
+static struct platform_device s3c_device_i2c17 = {
+	.name			= "i2c-gpio",
+	.id				= 17,
+	.dev.platform_data	= &i2c17_platdata,
+};
+#endif
+
+
+#ifdef CONFIG_FB_S5P_MIPI_DSIM
+#ifdef CONFIG_FB_S5P_S6E8AA0
+/* for Geminus based on MIPI-DSI interface */
+static struct s3cfb_lcd s6e8aa0 = {
+	.name = "s6e8aa0",
+	.width = 800,
+	.height = 1280,
+	.p_width = 64,
+	.p_height = 106,
+	.bpp = 24,
+
+	.freq = 57,
+
+	/* minumun value is 0 except for wr_act time. */
+	.cpu_timing = {
+		.cs_setup = 0,
+		.wr_setup = 0,
+		.wr_act = 1,
+		.wr_hold = 0,
+	},
+
+	.timing = {
+		.h_fp = 10,
+		.h_bp = 10,
+		.h_sw = 10,
+		.v_fp = 13,
+		.v_fpe = 1,
+		.v_bp = 1,
+		.v_bpe = 1,
+		.v_sw = 2,
+		.cmd_allow_len = 11,	/*v_fp=stable_vfp + cmd_allow_len */
+		.stable_vfp = 2,
+	},
+
+	.polarity = {
+		.rise_vclk = 1,
+		.inv_hsync = 0,
+		.inv_vsync = 0,
+		.inv_vden = 0,
+	},
+};
+#endif
+static struct s3c_platform_fb fb_platform_data __initdata = {
+	.hw_ver		= 0x70,
+	.clk_name	= "fimd",
+	.nr_wins	= 5,
+#ifdef CONFIG_FB_S5P_DEFAULT_WINDOW
+	.default_win	= CONFIG_FB_S5P_DEFAULT_WINDOW,
+#else
+	.default_win = 0,
+#endif
+	.swap = FB_SWAP_HWORD | FB_SWAP_WORD,
+#ifdef CONFIG_FB_S5P_S6E8AA0
+	.lcd = &s6e8aa0
+#endif
+};
+
+#ifdef CONFIG_FB_S5P_S6E8AA0
+static int reset_lcd(void)
+{
+	int err;
+
+	/* Set GPY4[5] OUTPUT HIGH */
+	err = gpio_request(EXYNOS4_GPY4(5), "MLCD_RST");
+	if (err) {
+		printk(KERN_ERR "failed to request GPY4(5) for "
+		       "lcd reset control\n");
+		return -EPERM;
+	}
+
+	gpio_direction_output(EXYNOS4_GPY4(5), 1);
+	msleep(5);
+	gpio_set_value(EXYNOS4_GPY4(5), 0);
+	msleep(5);
+	gpio_set_value(EXYNOS4_GPY4(5), 1);
+	msleep(5);
+
+	gpio_free(EXYNOS4_GPY4(5));
+
+	return 0;
+}
+#endif
+static void lcd_cfg_gpio(void)
+{
+	/* MLCD_RST */
+	s3c_gpio_cfgpin(EXYNOS4_GPY4(5), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPY4(5), S3C_GPIO_PULL_NONE);
+
+	/* LCD_EN */
+	s3c_gpio_cfgpin(GPIO_LCD_EN, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_LCD_EN, S3C_GPIO_PULL_NONE);
+
+	return;
+}
+
+static int lcd_power_on(void *ld, int enable)
+{
+	struct regulator *regulator;
+	int err;
+
+	printk(KERN_INFO "%s : enable=%d\n", __func__, enable);
+
+	if (ld == NULL) {
+		printk(KERN_ERR "lcd device object is NULL.\n");
+		return -EPERM;
+	}
+
+	err = gpio_request(EXYNOS4_GPY4(5), "MLCD_RST");
+	if (err) {
+		printk(KERN_ERR "failed to request GPY4[5] for "
+		       "MLCD_RST control\n");
+		return -EPERM;
+	}
+
+	err = gpio_request(GPIO_LCD_EN, "LCD_EN");
+	if (err) {
+		printk(KERN_ERR "failed to request GPY3[1] for "
+				"LCD_EN control\n");
+		return -EPERM;
+	}
+
+	if (enable) {
+#ifdef CONFIG_MACH_Q1_BD
+		if (system_rev < 8) {
+			regulator = regulator_get(NULL, "vlcd_2.2v");
+			if (IS_ERR(regulator))
+				return 0;
+			regulator_enable(regulator);
+			regulator_put(regulator);
+		} else
+			gpio_set_value(GPIO_LCD_EN, GPIO_LEVEL_HIGH);
+#endif
+		regulator = regulator_get(NULL, "vlcd_3.0v");
+		if (IS_ERR(regulator))
+			return 0;
+		regulator_enable(regulator);
+		regulator_put(regulator);
+	} else {
+		regulator = regulator_get(NULL, "vlcd_3.0v");
+		if (IS_ERR(regulator))
+			return 0;
+		if (regulator_is_enabled(regulator))
+			regulator_force_disable(regulator);
+		regulator_put(regulator);
+#ifdef CONFIG_MACH_Q1_BD
+		if (system_rev < 8) {
+			regulator = regulator_get(NULL, "vlcd_2.2v");
+			if (IS_ERR(regulator))
+				return 0;
+			if (regulator_is_enabled(regulator))
+				regulator_force_disable(regulator);
+			regulator_put(regulator);
+		} else
+			gpio_set_value(GPIO_LCD_EN, GPIO_LEVEL_LOW);
+#endif
+
+		gpio_set_value(EXYNOS4_GPY4(5), 0);
+	}
+
+	/* Release GPIO */
+	gpio_free(EXYNOS4_GPY4(5));
+	gpio_free(GPIO_LCD_EN);
+
+	return 0;
+}
+
+static void __init mipi_fb_init(void)
+{
+	struct s5p_platform_dsim *dsim_pd = NULL;
+	struct mipi_ddi_platform_data *mipi_ddi_pd = NULL;
+	struct dsim_lcd_config *dsim_lcd_info = NULL;
+
+	/* set platform data */
+
+	/* gpio pad configuration for rgb and spi interface. */
+	lcd_cfg_gpio();
+
+	/*
+	 * register lcd panel data.
+	 */
+	printk(KERN_INFO "%s :: fb_platform_data.hw_ver = 0x%x\n",
+	       __func__, fb_platform_data.hw_ver);
+
+	fb_platform_data.mipi_is_enabled = 1;
+	fb_platform_data.interface_mode = FIMD_CPU_INTERFACE;
+
+	dsim_pd = (struct s5p_platform_dsim *)
+	    s5p_device_dsim.dev.platform_data;
+
+	dsim_pd->platform_rev = 1;
+
+	dsim_lcd_info = dsim_pd->dsim_lcd_info;
+
+#ifdef CONFIG_FB_S5P_S6E8AA0
+	dsim_lcd_info->lcd_panel_info = (void *)&s6e8aa0;
+
+	/* 483Mbps for Q1 */
+	dsim_pd->dsim_info->p = 4;
+	dsim_pd->dsim_info->m = 161;
+	dsim_pd->dsim_info->s = 1;
+#endif
+
+	mipi_ddi_pd = (struct mipi_ddi_platform_data *)
+	    dsim_lcd_info->mipi_ddi_pd;
+	mipi_ddi_pd->lcd_reset = reset_lcd;
+	mipi_ddi_pd->lcd_power_on = lcd_power_on;
+
+	platform_device_register(&s5p_device_dsim);
+
+	s3cfb_set_platdata(&fb_platform_data);
+
+	printk(KERN_INFO
+	       "platform data of %s lcd panel has been registered.\n",
+	       dsim_pd->lcd_panel_name);
+}
+#endif
+
+#ifdef CONFIG_ANDROID_PMEM
+static struct android_pmem_platform_data pmem_pdata = {
+	.name = "pmem",
+	.no_allocator = 1,
+	.cached = 0,
+	.start = 0,
+	.size = 0
+};
+
+static struct android_pmem_platform_data pmem_gpu1_pdata = {
+	.name = "pmem_gpu1",
+	.no_allocator = 1,
+	.cached = 0,
+	.start = 0,
+	.size = 0,
+};
+
+static struct platform_device pmem_device = {
+	.name = "android_pmem",
+	.id = 0,
+	.dev = {
+		.platform_data = &pmem_pdata},
+};
+
+static struct platform_device pmem_gpu1_device = {
+	.name = "android_pmem",
+	.id = 1,
+	.dev = {
+		.platform_data = &pmem_gpu1_pdata},
+};
+
+static void __init android_pmem_set_platdata(void)
+{
+#if defined(CONFIG_S5P_MEM_CMA)
+	pmem_pdata.size = CONFIG_ANDROID_PMEM_MEMSIZE_PMEM * SZ_1K;
+	pmem_gpu1_pdata.size = CONFIG_ANDROID_PMEM_MEMSIZE_PMEM_GPU1 * SZ_1K;
+#else
+	pmem_pdata.start = (u32) s5p_get_media_memory_bank(S5P_MDEV_PMEM, 0);
+	pmem_pdata.size = (u32) s5p_get_media_memsize_bank(S5P_MDEV_PMEM, 0);
+	pmem_gpu1_pdata.start =
+		(u32) s5p_get_media_memory_bank(S5P_MDEV_PMEM_GPU1, 0);
+	pmem_gpu1_pdata.size =
+		(u32) s5p_get_media_memsize_bank(S5P_MDEV_PMEM_GPU1, 0);
+#endif
+}
+#endif
+
+/* USB EHCI */
+#ifdef CONFIG_USB_EHCI_S5P
+static struct s5p_ehci_platdata smdkc210_ehci_pdata;
+
+static void __init smdkc210_ehci_init(void)
+{
+	struct s5p_ehci_platdata *pdata = &smdkc210_ehci_pdata;
+
+	s5p_ehci_set_platdata(pdata);
+}
+#endif
+
+#ifdef CONFIG_USB_OHCI_S5P
+static struct s5p_ohci_platdata smdkc210_ohci_pdata;
+
+static void __init smdkc210_ohci_init(void)
+{
+	struct s5p_ohci_platdata *pdata = &smdkc210_ohci_pdata;
+
+	s5p_ohci_set_platdata(pdata);
+}
+#endif
+
+/* USB GADGET */
+#ifdef CONFIG_USB_GADGET
+static struct s5p_usbgadget_platdata smdkc210_usbgadget_pdata;
+
+#include <linux/usb/android_composite.h>
+static void __init smdkc210_usbgadget_init(void)
+{
+	struct s5p_usbgadget_platdata *pdata = &smdkc210_usbgadget_pdata;
+
+#if defined(CONFIG_USB_ANDROID) || defined(CONFIG_USB_G_ANDROID)
+	struct android_usb_platform_data *android_pdata =
+		s3c_device_android_usb.dev.platform_data;
+	if (android_pdata) {
+		unsigned int newluns = 2;
+		printk(KERN_DEBUG "usb: %s: default luns=%d, new luns=%d\n",
+				__func__, android_pdata->nluns, newluns);
+		android_pdata->nluns = newluns;
+	} else {
+		printk(KERN_DEBUG "usb: %s android_pdata is not available\n",
+				__func__);
+	}
+#endif
+
+	s5p_usbgadget_set_platdata(pdata);
+
+	pdata = s3c_device_usbgadget.dev.platform_data;
+	if (pdata) {
+		/* Enables HS Transmitter pre-emphasis [20] */
+		pdata->phy_tune_mask = 0;
+		pdata->phy_tune_mask |= (0x1 << 20);
+		pdata->phy_tune |= (0x1 << 20);
+
+#if defined(CONFIG_MACH_U1_KOR_SKT) || defined(CONFIG_MACH_U1_KOR_KT)
+		/* Squelch Threshold Tune [13:11] (101 : -10%) */
+		pdata->phy_tune_mask |= (0x7 << 11);
+		pdata->phy_tune |= (0x5 << 11);
+
+		/* HS DC Voltage Level Adjustment [3:0] (1011 : +16%) */
+		pdata->phy_tune_mask |= 0xf;
+		pdata->phy_tune |= 0xb;
+#elif defined(CONFIG_MACH_U1_KOR_LGT)
+		/* Squelch Threshold Tune [13:11] (100 : -5%) */
+		pdata->phy_tune_mask |= (0x7 << 11);
+		pdata->phy_tune |= (0x4 << 11);
+
+		/* HS DC Voltage Level Adjustment [3:0] (1100 : +18%) */
+		pdata->phy_tune_mask |= 0xf;
+		pdata->phy_tune |= 0xc;
+#else
+		/* Squelch Threshold Tune [13:11] (101 : -10%) */
+		pdata->phy_tune_mask |= (0x7 << 11);
+		pdata->phy_tune |= (0x5 << 11);
+		/* HS DC Voltage Level Adjustment [3:0] (1011 : +16%) */
+		pdata->phy_tune_mask |= 0xf;
+		pdata->phy_tune |= 0xb;
+#endif
+
+		printk(KERN_DEBUG "usb: %s tune_mask=0x%x, tune=0x%x\n",
+			__func__, pdata->phy_tune_mask, pdata->phy_tune);
+	}
+}
+#endif
+
+#ifdef CONFIG_BUSFREQ_OPP
+/* BUSFREQ to control memory/bus*/
+static struct device_domain busfreq;
+
+static struct platform_device exynos4_busfreq = {
+	.id = -1,
+	.name = "exynos-busfreq",
+};
+#endif
+
+#ifdef CONFIG_SEC_WATCHDOG_RESET
+static struct platform_device watchdog_reset_device = {
+	.name = "watchdog-reset",
+	.id = -1,
+};
+#endif
+
+static struct platform_device *smdkc210_devices[] __initdata = {
+#ifdef CONFIG_SEC_WATCHDOG_RESET
+	&watchdog_reset_device,
+#endif
+	&exynos4_device_pd[PD_MFC],
+	&exynos4_device_pd[PD_G3D],
+	&exynos4_device_pd[PD_LCD0],
+	&exynos4_device_pd[PD_LCD1],
+	&exynos4_device_pd[PD_CAM],
+	&exynos4_device_pd[PD_TV],
+	&exynos4_device_pd[PD_GPS],
+
+#ifdef CONFIG_BATTERY_SAMSUNG
+	&samsung_device_battery,
+#endif
+#ifdef CONFIG_FB_S5P
+	&s3c_device_fb,
+#endif
+
+#ifdef CONFIG_I2C_S3C2410
+	&s3c_device_i2c0,
+#if defined(CONFIG_S3C_DEV_I2C1)
+	&s3c_device_i2c1,
+#endif
+#if defined(CONFIG_S3C_DEV_I2C2)
+	&s3c_device_i2c2,
+#endif
+#if defined(CONFIG_S3C_DEV_I2C3)
+	&s3c_device_i2c3,
+#endif
+#if defined(CONFIG_S3C_DEV_I2C4)
+	&s3c_device_i2c4,
+#endif
+#if defined(CONFIG_S3C_DEV_I2C5)
+	&s3c_device_i2c5,
+#endif
+#if defined(CONFIG_S3C_DEV_I2C6)
+	&s3c_device_i2c6,
+#endif
+#if defined(CONFIG_S3C_DEV_I2C7)
+	&s3c_device_i2c7,
+#endif
+#if defined(CONFIG_S3C_DEV_I2C8_EMUL)
+	&s3c_device_i2c8,
+#endif
+#if defined(CONFIG_S3C_DEV_I2C9_EMUL)
+	&s3c_device_i2c9,
+#endif
+#if defined(CONFIG_S3C_DEV_I2C10_EMUL)
+	&s3c_device_i2c10,
+#endif
+#if defined(CONFIG_S3C_DEV_I2C11_EMUL)
+	&s3c_device_i2c11,
+#endif
+#if defined(CONFIG_S3C_DEV_I2C14_EMUL)
+	&s3c_device_i2c14,
+#endif
+#if defined(CONFIG_VIDEO_S5K5BAFX)
+	&s3c_device_i2c12,
+#endif
+#ifdef CONFIG_SAMSUNG_MHL
+		&s3c_device_i2c15,
+#endif
+#ifdef CONFIG_FM_SI4709_MODULE
+	&s3c_device_i2c16,
+#endif
+#ifdef	CONFIG_ISDBT_FC8100
+	&s3c_device_i2c17,	/* ISDBT */
+#endif
+#if defined(CONFIG_SMB136_CHARGER_Q1) || defined(CONFIG_SMB328_CHARGER)
+	&s3c_device_i2c19,	/* SMB136, SMB328 */
+#endif
+#endif
+
+	/* consumer driver should resume after resuming i2c drivers */
+	&u1_regulator_consumer,
+
+#ifdef CONFIG_EXYNOS4_DEV_MSHC
+	&s3c_device_mshci,
+#endif
+
+#ifdef CONFIG_S3C_DEV_HSMMC
+	&s3c_device_hsmmc0,
+#endif
+
+#ifdef CONFIG_S3C_DEV_HSMMC1
+	&s3c_device_hsmmc1,
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC2
+	&s3c_device_hsmmc2,
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC3
+	&s3c_device_hsmmc3,
+#endif
+#ifdef CONFIG_S3C_ADC
+	&s3c_device_adc,
+#endif
+#ifdef CONFIG_TOUCHSCREEN_S3C2410
+#ifdef CONFIG_S3C_DEV_ADC
+	&s3c_device_ts,
+#elif CONFIG_S3C_DEV_ADC1
+	&s3c_device_ts1,
+#endif
+#endif
+	&u1_keypad,
+	&s3c_device_rtc,
+	&s3c_device_wdt,
+#ifdef CONFIG_SND_SAMSUNG_AC97
+	&exynos_device_ac97,
+#endif
+#ifdef CONFIG_SND_SAMSUNG_I2S
+	&exynos_device_i2s0,
+#endif
+#ifdef CONFIG_SND_SAMSUNG_PCM
+	&exynos_device_pcm0,
+#endif
+#if defined(CONFIG_SND_SAMSUNG_RP) || defined(CONFIG_SND_SAMSUNG_ALP)
+	&exynos_device_srp,
+#endif
+#ifdef CONFIG_SND_SAMSUNG_SPDIF
+	&exynos_device_spdif,
+#endif
+#ifdef CONFIG_BATTERY_SEC_U1
+	&sec_device_battery,
+#endif
+#ifdef	CONFIG_LEDS_MAX8997
+	&sec_device_leds_max8997,
+#endif
+#ifdef CONFIG_CHARGER_MAX8922_U1
+	&max8922_device_charger,
+#endif
+#ifdef CONFIG_S5P_SYSTEM_MMU
+	&SYSMMU_PLATDEV(fimc0),
+	&SYSMMU_PLATDEV(fimc1),
+	&SYSMMU_PLATDEV(fimc2),
+	&SYSMMU_PLATDEV(fimc3),
+	&SYSMMU_PLATDEV(2d),
+	&SYSMMU_PLATDEV(tv),
+	&SYSMMU_PLATDEV(mfc_l),
+	&SYSMMU_PLATDEV(mfc_r),
+#endif
+#ifdef CONFIG_ION_EXYNOS
+	&exynos_device_ion,
+#endif
+
+	&samsung_asoc_dma,
+#ifndef CONFIG_SND_SOC_SAMSUNG_USE_DMA_WRAPPER
+	&samsung_asoc_idma,
+#endif
+
+#ifdef CONFIG_S3C64XX_DEV_SPI
+	&exynos_device_spi0,
+#endif
+
+#ifdef CONFIG_PHONE_IPC_SPI
+	&ipc_spi_device,
+#endif
+
+/* mainline fimd */
+#ifdef CONFIG_FB_S3C
+	&s5p_device_fimd0,
+#if defined(CONFIG_LCD_AMS369FG06)
+	&s3c_device_spi_gpio,
+#elif defined(CONFIG_LCD_WA101S)
+	&smdkc210_lcd_wa101s,
+#elif defined(CONFIG_LCD_LTE480WV)
+	&smdkc210_lcd_lte480wv,
+#endif
+#endif
+/* legacy fimd */
+#ifdef CONFIG_FB_S5P_AMS369FG06
+	&s3c_device_spi_gpio,
+#endif
+#ifdef CONFIG_FB_S5P_LD9040
+	&ld9040_spi_gpio,
+#endif
+#ifdef CONFIG_FB_S5P_NT35560
+	&nt35560_spi_gpio,
+#endif
+#ifdef CONFIG_FB_S5P_MDNIE
+	&mdnie_device,
+#endif
+#ifdef CONFIG_VIDEO_TVOUT
+	&s5p_device_tvout,
+	&s5p_device_cec,
+	&s5p_device_hpd,
+#endif
+#ifdef CONFIG_ANDROID_PMEM
+	&pmem_device,
+	&pmem_gpu1_device,
+#endif
+#ifdef CONFIG_VIDEO_FIMC
+	&s3c_device_fimc0,
+	&s3c_device_fimc1,
+	&s3c_device_fimc2,
+	&s3c_device_fimc3,
+#ifdef CONFIG_VIDEO_FIMC_MIPI
+	&s3c_device_csis0,
+	&s3c_device_csis1,
+#endif
+#endif
+#if defined(CONFIG_VIDEO_MFC5X) || defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC)
+	&s5p_device_mfc,
+#endif
+#ifdef CONFIG_VIDEO_FIMG2D
+	&s5p_device_fimg2d,
+#endif
+#ifdef CONFIG_VIDEO_JPEG
+	&s5p_device_jpeg,
+#endif
+#if defined CONFIG_USB_EHCI_S5P && !defined CONFIG_LINK_DEVICE_HSIC
+	&s5p_device_ehci,
+#endif
+#ifdef CONFIG_USB_OHCI_S5P
+	&s5p_device_ohci,
+#endif
+#ifdef CONFIG_USB_GADGET
+	&s3c_device_usbgadget,
+#endif
+#ifdef CONFIG_USB_ANDROID_RNDIS
+	&s3c_device_rndis,
+#endif
+#if defined(CONFIG_USB_ANDROID) || defined(CONFIG_USB_G_ANDROID)
+	&s3c_device_android_usb,
+	&s3c_device_usb_mass_storage,
+#endif
+#ifdef CONFIG_HAVE_PWM
+	&s3c_device_timer[0],
+	&s3c_device_timer[1],
+	&s3c_device_timer[2],
+	&s3c_device_timer[3],
+#endif
+#ifdef CONFIG_VIDEO_TSI
+	&s3c_device_tsi,
+#endif
+#ifdef CONFIG_EXYNOS4_SETUP_THERMAL
+	&s5p_device_tmu,
+#endif
+#ifdef CONFIG_BT_BCM4330
+	&bcm4330_bluetooth_device,
+#endif
+#ifdef CONFIG_S5P_DEV_ACE
+	&s5p_device_ace,
+#endif
+#ifdef CONFIG_BUSFREQ_OPP
+	&exynos4_busfreq,
+#endif
+#ifdef CONFIG_SEC_DEV_JACK
+	&sec_device_jack,
+#endif
+#ifdef CONFIG_USB_HOST_NOTIFY
+	&host_notifier_device,
+#endif
+	&s3c_device_usb_otghcd,
+};
+
+#ifdef CONFIG_EXYNOS4_SETUP_THERMAL
+/* below temperature base on the celcius degree */
+struct s5p_platform_tmu u1_tmu_data __initdata = {
+	.ts = {
+		.stop_1st_throttle  = 61,
+		.start_1st_throttle = 64,
+		.stop_2nd_throttle  = 87,
+		.start_2nd_throttle = 103,
+		.start_tripping     = 110,
+		.start_emergency    = 120,
+		.stop_mem_throttle  = 80,
+		.start_mem_throttle = 85,
+	},
+	.cpufreq = {
+		.limit_1st_throttle  = 800000, /* 800MHz in KHz order */
+		.limit_2nd_throttle  = 200000, /* 200MHz in KHz order */
+	},
+};
+#endif
+
+#if defined CONFIG_USB_EHCI_S5P && defined CONFIG_LINK_DEVICE_HSIC
+static int __init s5p_ehci_device_initcall(void)
+{
+	return platform_device_register(&s5p_device_ehci);
+}
+late_initcall(s5p_ehci_device_initcall);
+#endif
+
+#if defined(CONFIG_VIDEO_TVOUT)
+static struct s5p_platform_hpd hdmi_hpd_data __initdata = {
+
+};
+
+static struct s5p_platform_cec hdmi_cec_data __initdata = {
+
+};
+#endif
+
+#if defined(CONFIG_S5P_MEM_CMA)
+static void __init exynos4_cma_region_reserve(struct cma_region *regions_normal,
+					      struct cma_region *regions_secure)
+{
+	struct cma_region *reg;
+	size_t size_secure = 0, align_secure = 0;
+	phys_addr_t paddr = 0;
+
+	for (reg = regions_normal; reg->size != 0; reg++) {
+		if (WARN_ON(cma_early_region_register(reg)))
+			continue;
+
+		if ((reg->alignment & (reg->alignment - 1)) || reg->reserved)
+			continue;
+
+		if (reg->start) {
+			if (!memblock_is_region_reserved(reg->start, reg->size)
+			    && memblock_reserve(reg->start, reg->size) >= 0)
+				reg->reserved = 1;
+		} else {
+			paddr = __memblock_alloc_base(reg->size, reg->alignment,
+						      MEMBLOCK_ALLOC_ACCESSIBLE);
+			if (paddr) {
+				reg->start = paddr;
+				reg->reserved = 1;
+			}
+		}
+	}
+
+	if (regions_secure && regions_secure->size) {
+		for (reg = regions_secure; reg->size != 0; reg++)
+			size_secure += reg->size;
+
+		reg--;
+
+		align_secure = reg->alignment;
+		BUG_ON(align_secure & (align_secure - 1));
+
+		paddr -= size_secure;
+		paddr &= ~(align_secure - 1);
+
+		if (!memblock_reserve(paddr, size_secure)) {
+			do {
+				reg->start = paddr;
+				reg->reserved = 1;
+				paddr += reg->size;
+
+				if (WARN_ON(cma_early_region_register(reg)))
+					memblock_free(reg->start, reg->size);
+			} while (reg-- != regions_secure);
+		}
+	}
+}
+
+static void __init exynos4_reserve_mem(void)
+{
+	static struct cma_region regions[] = {
+#ifdef CONFIG_ANDROID_PMEM_MEMSIZE_PMEM
+		{
+			.name = "pmem",
+			.size = CONFIG_ANDROID_PMEM_MEMSIZE_PMEM * SZ_1K,
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_ANDROID_PMEM_MEMSIZE_PMEM_GPU1
+		{
+			.name = "pmem_gpu1",
+			.size = CONFIG_ANDROID_PMEM_MEMSIZE_PMEM_GPU1 * SZ_1K,
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMD
+		{
+			.name = "fimd",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMD * SZ_1K,
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC0
+		{
+			.name = "fimc0",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC0 * SZ_1K,
+			.start = 0,
+		},
+#endif
+#ifndef CONFIG_ION_EXYNOS_CONTIGHEAP_SIZE
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC1
+		{
+			.name = "fimc1",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC1 * SZ_1K,
+			.start = 0,
+		},
+#endif
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC2
+		{
+			.name = "fimc2",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC2 * SZ_1K,
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC3
+		{
+			.name = "fimc3",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC3 * SZ_1K,
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_ION_EXYNOS_CONTIGHEAP_SIZE
+                {
+                        .name   = "ion",
+                        .size   = CONFIG_ION_EXYNOS_CONTIGHEAP_SIZE * SZ_1K,
+                },
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC1
+		{
+			.name = "mfc1",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC1 * SZ_1K,
+			{
+				.alignment = 1 << 17,
+			},
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC0
+		{
+			.name = "mfc0",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC0 * SZ_1K,
+			{
+				.alignment = 1 << 17,
+			},
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC
+		{
+			.name = "mfc",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC * SZ_1K,
+			{
+				.alignment = 1 << 17,
+			},
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_JPEG
+		{
+			.name = "jpeg",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_JPEG * SZ_1K,
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_AUDIO_SAMSUNG_MEMSIZE_SRP
+		{
+			.name = "srp",
+			.size = CONFIG_AUDIO_SAMSUNG_MEMSIZE_SRP * SZ_1K,
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMG2D
+		{
+			.name = "fimg2d",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMG2D * SZ_1K,
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_TVOUT
+		{
+			.name = "tvout",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_TVOUT * SZ_1K,
+			.start = 0,
+		},
+#endif
+		{
+			.size = 0,
+		},
+	};
+
+	static const char map[] __initconst =
+		"android_pmem.0=pmem;android_pmem.1=pmem_gpu1;"
+		"s3cfb.0=fimd;exynos4-fb.0=fimd;"
+		"s3c-fimc.0=fimc0;s3c-fimc.1=fimc1;s3c-fimc.2=fimc2;"
+		"exynos4210-fimc.0=fimc0;exynos4210-fimc.1=fimc1;exynos4210-fimc.2=fimc2;exynos4210-fimc3=fimc3;"
+#ifdef CONFIG_ION_EXYNOS
+                "ion-exynos=ion;"
+#endif
+#ifdef CONFIG_VIDEO_MFC5X
+		"s3c-mfc/A=mfc0,mfc-secure;"
+		"s3c-mfc/B=mfc1,mfc-normal;"
+		"s3c-mfc/AB=mfc;"
+#endif
+		"samsung-rp=srp;"
+		"s5p-jpeg=jpeg;"
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_IS
+		"exynos4-fimc-is=fimc_is;"
+#endif
+		"s5p-fimg2d=fimg2d;"
+		"s5p-tvout=tvout";
+
+	cma_set_defaults(regions, map);
+	exynos4_cma_region_reserve(regions, NULL);
+
+}
+#endif
+
+static void __init exynos_sysmmu_init(void)
+{
+	ASSIGN_SYSMMU_POWERDOMAIN(fimc0, &exynos4_device_pd[PD_CAM].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(fimc1, &exynos4_device_pd[PD_CAM].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(fimc2, &exynos4_device_pd[PD_CAM].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(fimc3, &exynos4_device_pd[PD_CAM].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(jpeg, &exynos4_device_pd[PD_CAM].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(fimd0, &exynos4_device_pd[PD_LCD0].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(2d, &exynos4_device_pd[PD_LCD0].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(rot, &exynos4_device_pd[PD_LCD0].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(tv, &exynos4_device_pd[PD_TV].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(mfc_l, &exynos4_device_pd[PD_MFC].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(mfc_r, &exynos4_device_pd[PD_MFC].dev);
+#if defined CONFIG_VIDEO_FIMC
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc0).dev, &s3c_device_fimc0.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc1).dev, &s3c_device_fimc1.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc2).dev, &s3c_device_fimc2.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc3).dev, &s3c_device_fimc3.dev);
+#elif defined CONFIG_VIDEO_SAMSUNG_S5P_FIMC
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc0).dev, &s5p_device_fimc0.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc1).dev, &s5p_device_fimc1.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc2).dev, &s5p_device_fimc2.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc3).dev, &s5p_device_fimc3.dev);
+#endif
+#ifdef CONFIG_VIDEO_JPEG
+	sysmmu_set_owner(&SYSMMU_PLATDEV(jpeg).dev, &s5p_device_jpeg.dev);
+#endif
+#ifdef CONFIG_FB_S3C
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimd0).dev, &s5p_device_fimd0.dev);
+#endif
+#ifdef CONFIG_VIDEO_FIMG2D
+	sysmmu_set_owner(&SYSMMU_PLATDEV(2d).dev, &s5p_device_fimg2d.dev);
+#endif
+#ifdef CONFIG_VIDEO_TVOUT
+	sysmmu_set_owner(&SYSMMU_PLATDEV(tv).dev, &s5p_device_tvout.dev);
+#endif
+#if defined(CONFIG_VIDEO_MFC5X) || defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC)
+	sysmmu_set_owner(&SYSMMU_PLATDEV(mfc_l).dev, &s5p_device_mfc.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(mfc_r).dev, &s5p_device_mfc.dev);
+#endif
+}
+
+static void __init smdkc210_map_io(void)
+{
+	clk_xusbxti.rate = 24000000;
+
+	s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+	s3c24xx_init_clocks(24000000);
+	s3c24xx_init_uarts(smdkc210_uartcfgs, ARRAY_SIZE(smdkc210_uartcfgs));
+
+#if defined(CONFIG_S5P_MEM_CMA)
+	exynos4_reserve_mem();
+#else
+	s5p_reserve_mem(S5P_RANGE_MFC);
+#endif
+
+	/* as soon as INFORM3 is visible, sec_debug is ready to run */
+	sec_debug_init();
+}
+
+static void __init universal_tsp_init(void)
+{
+	int gpio;
+
+	/* TSP_LDO_ON: XMDMADDR_11 */
+	gpio = GPIO_TSP_LDO_ON;
+	gpio_request(gpio, "TSP_LDO_ON");
+	gpio_direction_output(gpio, 1);
+	gpio_export(gpio, 0);
+
+	/* TSP_INT: XMDMADDR_7 */
+	gpio = GPIO_TSP_INT;
+	gpio_request(gpio, "TSP_INT");
+	s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
+	s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+	i2c_devs3[0].irq = gpio_to_irq(gpio);
+
+	printk(KERN_INFO "%s touch : %d\n", __func__, i2c_devs3[0].irq);
+#ifdef CONFIG_MACH_Q1_BD
+	gpio_request(GPIO_TSP_SDA, "TSP_SDA");
+	gpio_request(GPIO_TSP_SCL, "TSP_SCL");
+	gpio_request(GPIO_OLED_DET, "OLED_DET");
+#endif
+}
+
+#ifdef CONFIG_EPEN_WACOM_G5SP
+static int p6_wacom_init_hw(void)
+{
+	int gpio;
+	int ret;
+
+	gpio = GPIO_PEN_RESET;
+	ret = gpio_request(gpio, "PEN_RESET");
+	s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT);
+	gpio_direction_output(gpio, 1);
+
+	gpio = GPIO_PEN_SLP;
+	ret = gpio_request(gpio, "PEN_SLP");
+	s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0x1));
+	s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+	gpio_direction_output(gpio, 0);
+
+	gpio = GPIO_PEN_PDCT;
+	ret = gpio_request(gpio, "PEN_PDCT");
+	s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
+	s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+	s5p_register_gpio_interrupt(gpio);
+	gpio_direction_input(gpio);
+
+	irq_set_irq_type(gpio_to_irq(gpio), IRQ_TYPE_EDGE_BOTH);
+
+	gpio = GPIO_PEN_IRQ;
+	ret = gpio_request(gpio, "PEN_IRQ");
+	s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+	s5p_register_gpio_interrupt(gpio);
+	gpio_direction_input(gpio);
+
+	i2c_devs6[1].irq = gpio_to_irq(gpio);
+	irq_set_irq_type(i2c_devs6[1].irq, IRQ_TYPE_EDGE_RISING);
+
+	s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
+
+	return 0;
+}
+
+static int __init p6_wacom_init(void)
+{
+	p6_wacom_init_hw();
+	printk(KERN_INFO "[E-PEN] : wacom IC initialized.\n");
+	return 0;
+}
+#endif
+
+static void __init smdkc210_machine_init(void)
+{
+#ifdef CONFIG_S3C64XX_DEV_SPI
+	struct clk *sclk = NULL;
+	struct clk *prnt = NULL;
+	struct device *spi0_dev = &exynos_device_spi0.dev;
+#endif
+	/* initialise the gpios */
+	u1_config_gpio_table();
+	exynos4_sleep_gpio_table_set = u1_config_sleep_gpio_table;
+
+#ifdef CONFIG_I2C_S3C2410
+	s3c_i2c0_set_platdata(NULL);
+	i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
+
+#ifdef CONFIG_S3C_DEV_I2C1
+	s3c_i2c1_set_platdata(NULL);
+	i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
+#endif
+#ifdef CONFIG_S3C_DEV_I2C2
+	s3c_i2c2_set_platdata(NULL);
+	i2c_register_board_info(2, i2c_devs2, ARRAY_SIZE(i2c_devs2));
+#endif
+#ifdef CONFIG_S3C_DEV_I2C3
+	universal_tsp_init();
+	s3c_i2c3_set_platdata(NULL);
+	i2c_register_board_info(3, i2c_devs3, ARRAY_SIZE(i2c_devs3));
+#endif
+#ifdef CONFIG_S3C_DEV_I2C4
+	s3c_i2c4_set_platdata(NULL);
+	i2c_register_board_info(4, i2c_devs4, ARRAY_SIZE(i2c_devs4));
+#endif
+#ifdef CONFIG_S3C_DEV_I2C5
+	s3c_i2c5_set_platdata(NULL);
+	s3c_gpio_cfgpin(GPIO_PMIC_IRQ, S3C_GPIO_SFN(0xF));
+	s3c_gpio_setpull(GPIO_PMIC_IRQ, S3C_GPIO_PULL_NONE);
+	i2c_devs5[0].irq = gpio_to_irq(GPIO_PMIC_IRQ);
+	i2c_register_board_info(5, i2c_devs5, ARRAY_SIZE(i2c_devs5));
+#endif
+#ifdef CONFIG_S3C_DEV_I2C6
+#ifdef CONFIG_EPEN_WACOM_G5SP
+	p6_wacom_init();
+#endif
+	s3c_i2c6_set_platdata(NULL);
+	i2c_register_board_info(6, i2c_devs6, ARRAY_SIZE(i2c_devs6));
+#endif
+#ifdef CONFIG_S3C_DEV_I2C7
+	s3c_i2c7_set_platdata(&default_i2c7_data);
+	i2c_register_board_info(7, i2c_devs7, ARRAY_SIZE(i2c_devs7));
+#endif
+#ifdef CONFIG_SAMSUNG_MHL
+	printk(KERN_INFO "%s() register sii9234 driver\n", __func__);
+
+	i2c_register_board_info(15, tuna_i2c15_boardinfo,
+			ARRAY_SIZE(tuna_i2c15_boardinfo));
+#endif
+#ifdef CONFIG_S3C_DEV_I2C8_EMUL
+#ifdef CONFIG_KEYBOARD_CYPRESS_TOUCH
+	touchkey_init_hw();
+#endif
+	i2c_register_board_info(8, i2c_devs8_emul, ARRAY_SIZE(i2c_devs8_emul));
+#endif
+#ifdef CONFIG_S3C_DEV_I2C9_EMUL
+	i2c_register_board_info(9, i2c_devs9_emul, ARRAY_SIZE(i2c_devs9_emul));
+#endif
+#ifdef CONFIG_S3C_DEV_I2C10_EMUL
+	i2c_register_board_info(10, i2c_devs10_emul,
+				ARRAY_SIZE(i2c_devs10_emul));
+#endif
+#ifdef CONFIG_S3C_DEV_I2C11_EMUL
+	s3c_gpio_setpull(GPIO_PS_ALS_INT, S3C_GPIO_PULL_NONE);
+	i2c_register_board_info(11, i2c_devs11_emul,
+				ARRAY_SIZE(i2c_devs11_emul));
+#endif
+#ifdef CONFIG_S3C_DEV_I2C14_EMUL
+	nfc_setup_gpio();
+	i2c_register_board_info(14, i2c_devs14, ARRAY_SIZE(i2c_devs14));
+#endif
+#if defined(CONFIG_VIDEO_S5K5BAFX)
+	i2c_register_board_info(12, i2c_devs12_emul,
+				ARRAY_SIZE(i2c_devs12_emul));
+#endif
+#ifdef CONFIG_FM_SI4709_MODULE
+	i2c_register_board_info(16, i2c_devs16, ARRAY_SIZE(i2c_devs16));
+#endif
+#ifdef	CONFIG_ISDBT_FC8100
+	i2c_register_board_info(17, i2c_devs17, ARRAY_SIZE(i2c_devs17));
+#endif
+
+#if defined(CONFIG_SMB136_CHARGER_Q1) || defined(CONFIG_SMB328_CHARGER)
+	i2c_register_board_info(19, i2c_devs19_emul,
+				ARRAY_SIZE(i2c_devs19_emul));
+#endif
+#endif
+
+	/* 400 kHz for initialization of MMC Card  */
+	__raw_writel((__raw_readl(EXYNOS4_CLKDIV_FSYS3) & 0xfffffff0)
+		     | 0x9, EXYNOS4_CLKDIV_FSYS3);
+	__raw_writel((__raw_readl(EXYNOS4_CLKDIV_FSYS2) & 0xfff0fff0)
+		     | 0x80008, EXYNOS4_CLKDIV_FSYS2);
+	__raw_writel((__raw_readl(EXYNOS4_CLKDIV_FSYS1) & 0xfff0fff0)
+		     | 0x90009, EXYNOS4_CLKDIV_FSYS1);
+
+#ifdef CONFIG_S3C_DEV_HSMMC
+	s3c_sdhci0_set_platdata(&exynos4_hsmmc0_pdata);
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC1
+	s3c_sdhci1_set_platdata(&exynos4_hsmmc1_pdata);
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC2
+	s3c_sdhci2_set_platdata(&exynos4_hsmmc2_pdata);
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC3
+	s3c_sdhci3_set_platdata(&exynos4_hsmmc3_pdata);
+#endif
+
+#ifdef CONFIG_EXYNOS4_DEV_MSHC
+	s3c_mshci_set_platdata(&exynos4_mshc_pdata);
+#endif
+
+#ifdef CONFIG_FB_S3C
+#ifdef CONFIG_LCD_AMS369FG06
+	spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
+#endif
+	s5p_fimd0_set_platdata(&smdkc210_lcd0_pdata);
+#ifdef CONFIG_EXYNOS_DEV_PD
+	s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
+#endif
+#endif
+
+#ifdef CONFIG_FB_S5P
+#ifdef CONFIG_FB_S5P_AMS369FG06
+	spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
+	s3cfb_set_platdata(&ams369fg06_data);
+#else
+	s3cfb_set_platdata(NULL);
+#endif
+#ifdef CONFIG_EXYNOS_DEV_PD
+	s3c_device_fb.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
+#endif
+#endif
+
+#ifdef CONFIG_EXYNOS_DEV_PD
+#ifdef CONFIG_VIDEO_JPEG
+	s5p_device_jpeg.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+#endif
+#endif
+#if defined(CONFIG_VIDEO_TVOUT)
+	s5p_hdmi_hpd_set_platdata(&hdmi_hpd_data);
+	s5p_hdmi_cec_set_platdata(&hdmi_cec_data);
+#ifdef CONFIG_EXYNOS_DEV_PD
+	s5p_device_tvout.dev.parent = &exynos4_device_pd[PD_TV].dev;
+#endif
+#endif
+#ifdef CONFIG_TOUCHSCREEN_S3C2410
+#ifdef CONFIG_S3C_DEV_ADC
+	s3c24xx_ts_set_platdata(&s3c_ts_platform);
+#endif
+#ifdef CONFIG_S3C_DEV_ADC1
+	s3c24xx_ts1_set_platdata(&s3c_ts_platform);
+#endif
+#endif
+#ifdef CONFIG_ANDROID_PMEM
+	android_pmem_set_platdata();
+#endif
+#ifdef CONFIG_VIDEO_FIMC
+	/* fimc */
+	s3c_fimc0_set_platdata(&fimc_plat);
+	s3c_fimc1_set_platdata(NULL);
+	s3c_fimc2_set_platdata(&fimc_plat);
+	s3c_fimc3_set_platdata(NULL);
+#ifdef CONFIG_VIDEO_FIMC_MIPI
+	s3c_csis0_set_platdata(NULL);
+	s3c_csis1_set_platdata(NULL);
+#endif
+#endif
+
+#ifdef CONFIG_EXYNOS_DEV_PD
+#ifdef CONFIG_VIDEO_FIMC
+	s3c_device_fimc0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+	s3c_device_fimc1.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+	s3c_device_fimc2.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+	s3c_device_fimc3.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+#endif
+#endif
+#ifdef CONFIG_ION_EXYNOS
+	exynos_ion_set_platdata();
+#endif
+
+#ifdef CONFIG_EXYNOS4_SETUP_THERMAL
+	s5p_tmu_set_platdata(&u1_tmu_data);
+#endif
+
+#if defined(CONFIG_VIDEO_MFC5X) || defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC)
+#ifdef CONFIG_EXYNOS_DEV_PD
+	s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
+#endif
+#endif
+
+#if defined(CONFIG_VIDEO_MFC5X)
+	exynos4_mfc_setup_clock(&s5p_device_mfc.dev, 200 * MHZ);
+#endif
+#if defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC)
+	dev_set_name(&s5p_device_mfc.dev, "s3c-mfc");
+	clk_add_alias("mfc", "s5p-mfc", "mfc", &s5p_device_mfc.dev);
+	s5p_mfc_setname(&s5p_device_mfc, "s5p-mfc");
+#endif
+
+#ifdef CONFIG_VIDEO_FIMG2D
+	s5p_fimg2d_set_platdata(&fimg2d_data);
+#ifdef CONFIG_EXYNOS_DEV_PD
+	s5p_device_fimg2d.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
+#endif
+#endif
+#ifdef CONFIG_USB_EHCI_S5P
+	smdkc210_ehci_init();
+#endif
+#ifdef CONFIG_USB_OHCI_S5P
+	smdkc210_ohci_init();
+#endif
+#ifdef CONFIG_USB_GADGET
+	smdkc210_usbgadget_init();
+#endif
+#ifdef CONFIG_FB_S5P_LD9040
+	ld9040_fb_init();
+#endif
+#ifdef CONFIG_FB_S5P_NT35560
+	nt35560_fb_init();
+#endif
+#if defined(CONFIG_FB_S5P_MIPI_DSIM)
+	mipi_fb_init();
+#endif
+
+#ifdef CONFIG_SND_SOC_U1_MC1N2
+	u1_sound_init();
+#endif
+
+	brcm_wlan_init();
+
+	exynos_sysmmu_init();
+
+	platform_add_devices(smdkc210_devices, ARRAY_SIZE(smdkc210_devices));
+
+#ifdef CONFIG_SEC_THERMISTOR
+	platform_device_register(&sec_device_thermistor);
+#endif
+
+#ifdef CONFIG_FB_S3C
+	exynos4_fimd0_setup_clock(&s5p_device_fimd0.dev, "mout_mpll",
+				  800 * MHZ);
+#endif
+
+#ifdef CONFIG_S3C64XX_DEV_SPI
+	sclk = clk_get(spi0_dev, "dout_spi0");
+	if (IS_ERR(sclk))
+		dev_err(spi0_dev, "failed to get sclk for SPI-0\n");
+	prnt = clk_get(spi0_dev, "mout_mpll");
+	if (IS_ERR(prnt))
+		dev_err(spi0_dev, "failed to get prnt\n");
+	clk_set_parent(sclk, prnt);
+
+	clk_put(sclk);
+	clk_put(prnt);
+
+	if (!gpio_request(EXYNOS4_GPB(1), "SPI_CS0")) {
+		gpio_direction_output(EXYNOS4_GPB(1), 1);
+		s3c_gpio_cfgpin(EXYNOS4_GPB(1), S3C_GPIO_SFN(1));
+		s3c_gpio_setpull(EXYNOS4_GPB(1), S3C_GPIO_PULL_UP);
+		exynos_spi_set_info(0, EXYNOS_SPI_SRCCLK_SCLK,
+				    ARRAY_SIZE(spi0_csi));
+	}
+	spi_register_board_info(spi0_board_info, ARRAY_SIZE(spi0_board_info));
+#endif
+
+#ifdef CONFIG_BUSFREQ_OPP
+	dev_add(&busfreq, &exynos4_busfreq.dev);
+#endif
+
+#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE)
+	tdmb_dev_init();
+#endif
+
+}
+
+static void __init exynos_init_reserve(void)
+{
+	sec_debug_magic_init();
+}
+
+#ifdef CONFIG_MACH_U1_KOR_SKT
+#define MODEL_NAME "SHW-M250S"
+#elif defined(CONFIG_MACH_U1_KOR_KT)
+#define MODEL_NAME "SHW-M250K"
+#elif defined(CONFIG_MACH_U1_KOR_LGT)
+#define MODEL_NAME "SHW-M250L"
+#else
+#define MODEL_NAME "SMDK4210"
+#endif
+
+MACHINE_START(SMDKC210, MODEL_NAME)
+	/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
+	.boot_params	= S5P_PA_SDRAM + 0x100,
+	.init_irq	= exynos4_init_irq,
+	.map_io		= smdkc210_map_io,
+	.init_machine	= smdkc210_machine_init,
+	.timer		= &exynos4_timer,
+	.init_early	= &exynos_init_reserve,
+MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-u1cam.c b/arch/arm/mach-exynos/mach-u1cam.c
new file mode 100644
index 0000000..b5ddf3b
--- /dev/null
+++ b/arch/arm/mach-exynos/mach-u1cam.c
@@ -0,0 +1,6993 @@
+/* linux/arch/arm/mach-exynos/mach-u1cam.c
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/serial_core.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/gpio_keys.h>
+#include <linux/gpio_event.h>
+#include <linux/lcd.h>
+#include <linux/mmc/host.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/i2c.h>
+#include <linux/i2c-gpio.h>
+#include <linux/input.h>
+#include <linux/switch.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi_gpio.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+#include <linux/mfd/max8997.h>
+#include <linux/mfd/max8997-private.h>
+#include <linux/sensor/k3g.h>
+#include <linux/sensor/k3dh.h>
+#include <linux/sensor/ak8975.h>
+#ifdef CONFIG_MACH_U1_BD
+#include <linux/sensor/cm3663.h>
+#include <linux/sensor/pas2m110.h>
+#endif
+#ifdef CONFIG_MACH_Q1_BD
+#include <linux/sensor/gp2a_analog.h>
+#endif
+#include <linux/pn544.h>
+#ifdef CONFIG_SND_SOC_U1_MC1N2
+#include <linux/mfd/mc1n2_pdata.h>
+#endif
+#if defined(CONFIG_TOUCHSCREEN_ATMEL_MXT540E)
+#include <linux/i2c/mxt540e.h>
+#else
+#ifdef CONFIG_TOUCHSCREEN_ATMEL_MXT224_GC
+#include <linux/i2c/mxt224_gc.h>
+#else
+#include <linux/i2c/mxt224_u1.h>
+#endif
+#endif
+#include <linux/memblock.h>
+#include <linux/power_supply.h>
+#if defined(CONFIG_S5P_MEM_CMA)
+#include <linux/cma.h>
+#endif
+#ifdef CONFIG_ANDROID_PMEM
+#include <linux/android_pmem.h>
+#endif
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <video/platform_lcd.h>
+
+#include <plat/regs-serial.h>
+#include <plat/regs-srom.h>
+#include <plat/exynos4.h>
+#include <plat/clock.h>
+#include <plat/hwmon.h>
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/fb-s5p.h>
+#include <plat/fimc.h>
+#include <plat/csis.h>
+#include <plat/gpio-cfg.h>
+#include <plat/adc.h>
+#include <plat/ts.h>
+#include <plat/keypad.h>
+#include <plat/sdhci.h>
+#include <plat/mshci.h>
+#include <plat/iic.h>
+#include <plat/sysmmu.h>
+#include <plat/pd.h>
+#include <plat/regs-fb-v4.h>
+#include <plat/media.h>
+#include <plat/udc-hs.h>
+#include <plat/s5p-clock.h>
+#include <plat/tvout.h>
+#include <plat/fimg2d.h>
+#include <plat/ehci.h>
+#include <plat/usbgadget.h>
+
+#ifdef CONFIG_S3C64XX_DEV_SPI
+#include <plat/s3c64xx-spi.h>
+#endif
+
+#include <mach/map.h>
+#include <mach/exynos-clock.h>
+#include <mach/media.h>
+#include <plat/regs-fb.h>
+
+#include <mach/dev-sysmmu.h>
+#include <mach/dev.h>
+#include <mach/regs-clock.h>
+#include <mach/exynos-ion.h>
+
+#ifdef CONFIG_FB_S5P_MIPI_DSIM
+#include <mach/mipi_ddi.h>
+#include <mach/dsim.h>
+#include <plat/fb-s5p.h>
+#endif
+
+#if defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC) || defined(CONFIG_VIDEO_MFC5X)
+#include <plat/s5p-mfc.h>
+#endif
+
+#ifdef CONFIG_S3C64XX_DEV_SPI
+#include <mach/spi-clocks.h>
+#endif
+
+#ifdef CONFIG_VIDEO_M9MO
+#include <media/m9mo_platform.h>
+#endif
+#ifdef CONFIG_VIDEO_S5K5BAFX
+#include <media/s5k5bafx_platform.h>
+#endif
+
+#if defined(CONFIG_EXYNOS4_SETUP_THERMAL)
+#include <plat/s5p-tmu.h>
+#include <mach/regs-tmu.h>
+#endif
+
+#ifdef CONFIG_SEC_DEV_JACK
+#include <linux/sec_jack.h>
+#endif
+
+#ifdef CONFIG_BT_BCM4330
+#include <mach/board-bluetooth-bcm.h>
+#endif
+
+#ifdef CONFIG_FB_S5P_LD9040
+#include <linux/ld9040.h>
+#endif
+
+#ifdef CONFIG_FB_S5P_MDNIE
+#include <linux/mdnie.h>
+#endif
+
+#include <../../../drivers/video/samsung/s3cfb.h>
+#include "u1.h"
+
+#include <mach/sec_debug.h>
+
+#ifdef	CONFIG_SAMSUNG_MHL
+#include <linux/irq.h>
+#include <linux/sii9234.h>
+#endif
+
+#ifdef CONFIG_BATTERY_SEC_U1
+#include <linux/power/sec_battery_u1.h>
+#endif
+
+#ifdef CONFIG_SEC_THERMISTOR
+#include <mach/sec_thermistor.h>
+#endif
+
+#ifdef CONFIG_BATTERY_MAX17042_FUELGAUGE_U1
+#include <linux/power/max17042_fuelgauge_u1.h>
+#endif
+
+#ifdef CONFIG_CHARGER_MAX8922_U1
+#include <linux/power/max8922_charger_u1.h>
+#endif
+
+#ifdef CONFIG_SMB136_CHARGER_Q1
+#include <linux/power/smb136_charger_q1.h>
+#endif
+
+#ifdef CONFIG_SMB328_CHARGER
+#include <linux/power/smb328_charger.h>
+#endif
+
+#ifdef CONFIG_USB_HOST_NOTIFY
+#include <linux/host_notify.h>
+#endif
+
+#ifdef CONFIG_EPEN_WACOM_G5SP
+#include <linux/wacom_i2c.h>
+static struct wacom_g5_callbacks *wacom_callbacks;
+#endif /* CONFIG_EPEN_WACOM_G5SP */
+
+
+#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE)
+#include <mach/tdmb_pdata.h>
+#endif
+
+#ifdef CONFIG_LEDS_MAX8997
+#include <linux/leds-max8997.h>
+#endif
+
+/* Following are default values for UCON, ULCON and UFCON UART registers */
+#define SMDKC210_UCON_DEFAULT	(S3C2410_UCON_TXILEVEL |	\
+				 S3C2410_UCON_RXILEVEL |	\
+				 S3C2410_UCON_TXIRQMODE |	\
+				 S3C2410_UCON_RXIRQMODE |	\
+				 S3C2410_UCON_RXFIFO_TOI |	\
+				 S3C2443_UCON_RXERR_IRQEN)
+
+#define SMDKC210_ULCON_DEFAULT	S3C2410_LCON_CS8
+
+#define SMDKC210_UFCON_DEFAULT	(S3C2410_UFCON_FIFOMODE |	\
+				 S5PV210_UFCON_TXTRIG4 |	\
+				 S5PV210_UFCON_RXTRIG4)
+
+#define SMDKC210_UFCON_GPS	(S3C2410_UFCON_FIFOMODE |	\
+				S5PV210_UFCON_TXTRIG8 |	\
+				S5PV210_UFCON_RXTRIG32)
+
+static struct s3c2410_uartcfg smdk4212_uartcfgs[] __initdata = {
+	[0] = {
+		.hwport = 0,
+		.flags = 0,
+		.ucon = SMDKC210_UCON_DEFAULT,
+		.ulcon = SMDKC210_ULCON_DEFAULT,
+		.ufcon = SMDKC210_UFCON_DEFAULT,
+#ifdef CONFIG_BT_BCM4330
+		.wake_peer = bcm_bt_lpm_exit_lpm_locked,
+#endif
+	},
+	[1] = {
+		.hwport = 1,
+		.flags = 0,
+		.ucon = SMDKC210_UCON_DEFAULT,
+		.ulcon = SMDKC210_ULCON_DEFAULT,
+		.ufcon = SMDKC210_UFCON_GPS,
+		.set_runstate = set_gps_uart_op,
+	},
+	[2] = {
+		.hwport = 2,
+		.flags = 0,
+		.ucon = SMDKC210_UCON_DEFAULT,
+		.ulcon = SMDKC210_ULCON_DEFAULT,
+		.ufcon = SMDKC210_UFCON_DEFAULT,
+	},
+	[3] = {
+		.hwport = 3,
+		.flags = 0,
+		.ucon = SMDKC210_UCON_DEFAULT,
+		.ulcon = SMDKC210_ULCON_DEFAULT,
+		.ufcon = SMDKC210_UFCON_DEFAULT,
+	},
+};
+
+#define WRITEBACK_ENABLED
+
+#ifdef CONFIG_VIDEO_FIMC
+/*
+ * External camera reset
+ * Because the most of cameras take i2c bus signal, so that
+ * you have to reset at the boot time for other i2c slave devices.
+ * This function also called at fimc_init_camera()
+ * Do optimization for cameras on your platform.
+ */
+
+#ifdef CONFIG_VIDEO_M9MO
+#define CAM_CHECK_ERR_RET(x, msg)					\
+	if (unlikely((x) < 0)) {					\
+		printk(KERN_ERR "\nfail to %s: err = %d\n", msg, x);	\
+		return x;						\
+	}
+#define CAM_CHECK_ERR(x, msg)						\
+	if (unlikely((x) < 0)) {					\
+		printk(KERN_ERR "\nfail to %s: err = %d\n", msg, x);	\
+	}
+
+static int m9mo_get_i2c_busnum(void)
+{
+#ifdef CONFIG_VIDEO_M9MO_USE_SWI2C
+	return 25;
+#else
+	return 0;
+#endif
+}
+
+static int m9mo_power_on(void)
+{
+	struct regulator *regulator;
+	int ret = 0;
+
+	printk(KERN_ERR "%s: in\n", __func__);
+
+	/* CIS_LDO_1.8V_EN -> CIS 1.2 */
+	ret = gpio_request(GPIO_CAM_SENSOR_CORE, "GPE2");
+	if (ret) {
+		printk(KERN_ERR "fail to request gpio(CAM_SENSOR_CORE)\n");
+		return ret;
+	}
+
+	ret = gpio_request(GPIO_ISP_RESET, "ISP_RESET");
+	if (ret) {
+		printk(KERN_ERR "faile to request gpio(ISP_RESET)\n");
+		return ret;
+	}
+
+	/* CIS 1.8V */
+	regulator = regulator_get(NULL, "cis_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "cis_1.8v");
+	udelay(10);
+
+	/* CIS_2.8 */
+	regulator = regulator_get(NULL, "cis_2.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "enable cis_2.8v");
+	udelay(10);
+
+	/* CIS_1.2V */
+	ret = gpio_direction_output(GPIO_CAM_SENSOR_CORE, 1);
+	CAM_CHECK_ERR_RET(ret, "output reset");
+	udelay(10);
+
+	/* CAM_ISP_CORE_1.2V */
+	regulator = regulator_get(NULL, "cam_isp_core");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "enable cam_isp_core");
+
+	udelay(10);
+
+	/* CAM_ISP_1.8V */
+	regulator = regulator_get(NULL, "cam_isp");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "enable cam_isp");
+	udelay(120);		/* at least */
+
+	/* MCLK */
+	ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_SFN(2));
+	CAM_CHECK_ERR_RET(ret, "cfg mclk");
+	s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_NONE);
+	udelay(70);
+
+	/* ISP_RESET */
+	ret = gpio_direction_output(GPIO_ISP_RESET, 1);
+	CAM_CHECK_ERR_RET(ret, "output reset");
+	mdelay(4);
+
+	gpio_free(GPIO_CAM_SENSOR_CORE);
+	gpio_free(GPIO_ISP_RESET);
+
+	printk(KERN_DEBUG "%s: out\n", __func__);
+
+	return ret;
+}
+#ifdef	CONFIG_SAMSUNG_MHL
+
+
+static void sii9234_cfg_gpio(void)
+{
+	printk(KERN_INFO "%s()\n", __func__);
+
+	s3c_gpio_cfgpin(GPIO_AP_SDA_18V, S3C_GPIO_SFN(0x0));
+	s3c_gpio_setpull(GPIO_AP_SDA_18V, S3C_GPIO_PULL_NONE);
+
+	s3c_gpio_cfgpin(GPIO_AP_SCL_18V, S3C_GPIO_SFN(0x1));
+	s3c_gpio_setpull(GPIO_AP_SCL_18V, S3C_GPIO_PULL_NONE);
+
+	s3c_gpio_cfgpin(GPIO_MHL_WAKE_UP, S3C_GPIO_INPUT);
+	irq_set_irq_type(MHL_WAKEUP_IRQ, IRQ_TYPE_EDGE_RISING);
+	s3c_gpio_setpull(GPIO_MHL_WAKE_UP, S3C_GPIO_PULL_DOWN);
+
+	gpio_request(GPIO_MHL_INT, "MHL_INT");
+	s5p_register_gpio_interrupt(GPIO_MHL_INT);
+	s3c_gpio_setpull(GPIO_MHL_INT, S3C_GPIO_PULL_DOWN);
+	irq_set_irq_type(MHL_INT_IRQ, IRQ_TYPE_EDGE_RISING);
+	s3c_gpio_cfgpin(GPIO_MHL_INT, GPIO_MHL_INT_AF);
+
+#ifdef CONFIG_TARGET_LOCALE_KOR
+	s3c_gpio_cfgpin(GPIO_HDMI_EN, S3C_GPIO_OUTPUT);
+	gpio_set_value(GPIO_HDMI_EN, GPIO_LEVEL_LOW);
+	s3c_gpio_setpull(GPIO_HDMI_EN, S3C_GPIO_PULL_NONE);
+#else
+	if (system_rev < 7) {
+		s3c_gpio_cfgpin(GPIO_HDMI_EN, S3C_GPIO_OUTPUT);
+		gpio_set_value(GPIO_HDMI_EN, GPIO_LEVEL_LOW);
+		s3c_gpio_setpull(GPIO_HDMI_EN, S3C_GPIO_PULL_NONE);
+	} else {
+		s3c_gpio_cfgpin(GPIO_HDMI_EN_REV07, S3C_GPIO_OUTPUT);
+		gpio_set_value(GPIO_HDMI_EN_REV07, GPIO_LEVEL_LOW);
+		s3c_gpio_setpull(GPIO_HDMI_EN_REV07, S3C_GPIO_PULL_NONE);
+	}
+#endif
+
+	s3c_gpio_cfgpin(GPIO_MHL_RST, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_MHL_RST, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_MHL_RST, GPIO_LEVEL_LOW);
+
+	s3c_gpio_cfgpin(GPIO_MHL_SEL, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_MHL_SEL, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_MHL_SEL, GPIO_LEVEL_LOW);
+
+}
+
+void sii9234_power_onoff(bool on)
+{
+	pr_info("%s(%d)\n", __func__, on);
+
+	if (on) {
+		/*s3c_gpio_cfgpin(GPIO_HDMI_EN,S3C_GPIO_OUTPUT);*/
+#ifdef CONFIG_TARGET_LOCALE_KOR
+		gpio_set_value(GPIO_HDMI_EN, GPIO_LEVEL_HIGH);
+#else
+		if (system_rev < 7)
+			gpio_set_value(GPIO_HDMI_EN, GPIO_LEVEL_HIGH);
+		else
+			gpio_set_value(GPIO_HDMI_EN_REV07, GPIO_LEVEL_HIGH);
+#endif
+
+		s3c_gpio_setpull(GPIO_AP_SCL_18V, S3C_GPIO_PULL_DOWN);
+		s3c_gpio_setpull(GPIO_AP_SCL_18V, S3C_GPIO_PULL_NONE);
+
+	} else {
+		gpio_set_value(GPIO_MHL_RST, GPIO_LEVEL_LOW);
+		usleep_range(10000, 20000);
+		gpio_set_value(GPIO_MHL_RST, GPIO_LEVEL_HIGH);
+#ifdef CONFIG_TARGET_LOCALE_KOR
+		gpio_set_value(GPIO_HDMI_EN, GPIO_LEVEL_HIGH);
+#else
+		if (system_rev < 7)
+			gpio_set_value(GPIO_HDMI_EN, GPIO_LEVEL_LOW);
+		else
+			gpio_set_value(GPIO_HDMI_EN_REV07, GPIO_LEVEL_LOW);
+#endif
+		gpio_set_value(GPIO_MHL_RST, GPIO_LEVEL_LOW);
+	}
+	pr_info("[MHL]%s : %d\n", __func__, on);
+}
+
+void sii9234_reset(void)
+{
+	s3c_gpio_cfgpin(GPIO_MHL_RST, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_MHL_RST, S3C_GPIO_PULL_NONE);
+
+	gpio_set_value(GPIO_MHL_RST, GPIO_LEVEL_LOW);
+	usleep_range(10000, 20000);
+	gpio_set_value(GPIO_MHL_RST, GPIO_LEVEL_HIGH);
+
+}
+
+void mhl_usb_switch_control(bool on)
+{
+	pr_info("%s() [MHL] USB path change : %s\n",
+			__func__, on ? "MHL" : "USB");
+	if (on == 1) {
+		if (gpio_get_value(GPIO_MHL_SEL))
+			pr_info("[MHL] GPIO_MHL_SEL :already 1\n");
+		else {
+			gpio_set_value(GPIO_MHL_SEL, GPIO_LEVEL_HIGH);
+			/* sii9234_cfg_power(1);	// onegun */
+			/* sii9234_init();		// onegun */
+		}
+	} else {
+		if (!gpio_get_value(GPIO_MHL_SEL))
+			pr_info("[MHL]	GPIO_MHL_SEL :already0\n");
+		else {
+			/* sii9234_cfg_power(0);	// onegun */
+			gpio_set_value(GPIO_MHL_SEL, GPIO_LEVEL_LOW);
+		}
+	}
+}
+
+static struct sii9234_platform_data sii9234_pdata = {
+	.init = sii9234_cfg_gpio,
+	.mhl_sel = mhl_usb_switch_control,
+	.hw_onoff = sii9234_power_onoff,
+	.hw_reset = sii9234_reset,
+	.enable_vbus = NULL,
+	.vbus_present = NULL,
+};
+
+static struct i2c_board_info __initdata tuna_i2c15_boardinfo[] = {
+	{
+		I2C_BOARD_INFO("sii9234_mhl_tx", 0x72>>1),
+		.platform_data = &sii9234_pdata,
+	},
+	{
+		I2C_BOARD_INFO("sii9234_tpi", 0x7A>>1),
+		.platform_data = &sii9234_pdata,
+	},
+	{
+		I2C_BOARD_INFO("sii9234_hdmi_rx", 0x92>>1),
+		.platform_data = &sii9234_pdata,
+	},
+	{
+		I2C_BOARD_INFO("sii9234_cbus", 0xC8>>1),
+		.platform_data = &sii9234_pdata,
+	},
+};
+
+#define I2C_BUS_ID_MHL	15
+static struct i2c_gpio_platform_data gpio_i2c_data15 = {
+	.sda_pin = GPIO_MHL_SDA_18V,
+	.scl_pin = GPIO_MHL_SCL_18V,
+	.udelay = 2,
+	.sda_is_open_drain	= 0,
+	.scl_is_open_drain	= 0,
+	.scl_is_output_only	= 0,
+};
+
+struct platform_device s3c_device_i2c15 = {
+	.name = "i2c-gpio",
+	.id = I2C_BUS_ID_MHL,
+	.dev = {
+		.platform_data = &gpio_i2c_data15,
+	}
+};
+
+#endif
+
+static int m9mo_power_down(void)
+{
+	struct regulator *regulator;
+	int ret = 0;
+
+	printk(KERN_DEBUG "%s: in\n", __func__);
+
+	ret = gpio_request(GPIO_ISP_RESET, "ISP_RESET");
+	if (ret) {
+		printk(KERN_ERR "faile to request gpio(ISP_RESET)\n");
+		return ret;
+	}
+
+	ret = gpio_request(GPIO_CAM_SENSOR_CORE, "GPE2");
+	if (ret) {
+		printk(KERN_ERR "fail to request gpio(CAM_SENSOR_CORE)\n");
+		return ret;
+	}
+
+	/* ISP_RESET */
+	ret = gpio_direction_output(GPIO_ISP_RESET, 0);
+	CAM_CHECK_ERR(ret, "output reset");
+
+	mdelay(2);
+
+	/* MCLK */
+	ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_DOWN);
+	CAM_CHECK_ERR(ret, "cfg mclk");
+	udelay(20);
+
+	/* CAM_ISP_1.8V */
+	regulator = regulator_get(NULL, "cam_isp");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "disable cam_isp");
+	udelay(500);		/* 100us -> 500us */
+
+	/* CAM_ISP_CORE_1.2V */
+	regulator = regulator_get(NULL, "cam_isp_core");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "disable isp_core");
+
+	ret = gpio_direction_output(GPIO_CAM_SENSOR_CORE, 0);
+	CAM_CHECK_ERR_RET(ret, "output reset");
+	udelay(10);
+
+	regulator = regulator_get(NULL, "cis_2.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "disable cis_2.8v");
+	udelay(500);		/* 100us -> 500us */
+
+	regulator = regulator_get(NULL, "cis_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "disable cis_1.8v");
+	udelay(500);		/* 100us -> 500us */
+
+	gpio_free(GPIO_ISP_RESET);
+	gpio_free(GPIO_CAM_SENSOR_CORE);
+
+	return ret;
+}
+
+int s3c_csis_power(int enable)
+{
+	struct regulator *regulator;
+	int ret = 0;
+	printk(KERN_DEBUG "%s: in\n", __func__);
+
+	/* mipi_1.1v ,mipi_1.8v are always powered-on.
+	 * If they are off, we then power them on.
+	 */
+	if (enable) {
+		/* VMIPI_1.1V */
+		regulator = regulator_get(NULL, "vmipi_1.1v");
+		if (IS_ERR(regulator))
+			goto error_out;
+		if (!regulator_is_enabled(regulator)) {
+			printk(KERN_WARNING "%s: vmipi_1.1v is off. so ON\n",
+			       __func__);
+			ret = regulator_enable(regulator);
+			CAM_CHECK_ERR(ret, "enable vmipi_1.1v");
+		}
+		regulator_put(regulator);
+
+		/* VMIPI_1.8V */
+		regulator = regulator_get(NULL, "vmipi_1.8v");
+		if (IS_ERR(regulator))
+			goto error_out;
+		if (!regulator_is_enabled(regulator)) {
+			printk(KERN_WARNING "%s: vmipi_1.8v is off. so ON\n",
+			       __func__);
+			ret = regulator_enable(regulator);
+			CAM_CHECK_ERR(ret, "enable vmipi_1.8v");
+		}
+		regulator_put(regulator);
+	}
+	printk(KERN_DEBUG "%s: out\n", __func__);
+
+	return 0;
+
+error_out:
+	printk(KERN_ERR "%s: ERROR: failed to check mipi-power\n", __func__);
+	return 0;
+}
+
+#if defined(CONFIG_MACH_Q1_BD)
+static bool is_torch;
+#endif
+
+static int m9mo_flash_power(int enable)
+{
+	struct regulator *flash = regulator_get(NULL, "led_flash");
+	struct regulator *movie = regulator_get(NULL, "led_movie");
+
+	if (enable) {
+
+#if defined(CONFIG_MACH_Q1_BD)
+		if (regulator_is_enabled(movie)) {
+			printk(KERN_DEBUG "%s: m9mo_torch set~~~~", __func__);
+			is_torch = true;
+			goto torch_exit;
+		}
+		is_torch = false;
+#endif
+		regulator_set_current_limit(flash, 490000, 530000);
+		regulator_enable(flash);
+		regulator_set_current_limit(movie, 90000, 110000);
+		regulator_enable(movie);
+	} else {
+
+#if defined(CONFIG_MACH_Q1_BD)
+		if (is_torch)
+			goto torch_exit;
+#endif
+
+		if (regulator_is_enabled(flash))
+			regulator_disable(flash);
+		if (regulator_is_enabled(movie))
+			regulator_disable(movie);
+	}
+torch_exit:
+	regulator_put(flash);
+	regulator_put(movie);
+
+	return 0;
+}
+
+static int m9mo_power(int enable)
+{
+	int ret = 0;
+
+	printk(KERN_DEBUG "%s %s\n", __func__, enable ? "on" : "down");
+	if (enable) {
+		ret = m9mo_power_on();
+		if (unlikely(ret))
+			goto error_out;
+	} else
+		ret = m9mo_power_down();
+
+	ret = s3c_csis_power(enable);
+/*	m9mo_flash_power(enable);*/
+
+error_out:
+	return ret;
+}
+
+static int m9mo_config_isp_irq(void)
+{
+	s3c_gpio_cfgpin(GPIO_ISP_INT, S3C_GPIO_SFN(0xF));
+	s3c_gpio_setpull(GPIO_ISP_INT, S3C_GPIO_PULL_NONE);
+	return 0;
+}
+
+static struct m9mo_platform_data m9mo_plat = {
+	.default_width = 640,	/* 1920 */
+	.default_height = 480,	/* 1080 */
+	.pixelformat = V4L2_PIX_FMT_UYVY,
+	.freq = 24000000,
+	.is_mipi = 1,
+	.config_isp_irq = m9mo_config_isp_irq,
+	.irq = IRQ_EINT(13),
+};
+
+static struct i2c_board_info m9mo_i2c_info = {
+	I2C_BOARD_INFO("M9MO", 0x1F),
+	.platform_data = &m9mo_plat,
+};
+
+static struct s3c_platform_camera m9mo = {
+	.id = CAMERA_CSI_C,
+	.clk_name = "sclk_cam0",
+	.get_i2c_busnum = m9mo_get_i2c_busnum,
+	.cam_power = m9mo_power,	/*smdkv310_mipi_cam0_reset, */
+	.type = CAM_TYPE_MIPI,
+	.fmt = ITU_601_YCBCR422_8BIT,	/*MIPI_CSI_YCBCR422_8BIT */
+	.order422 = CAM_ORDER422_8BIT_CBYCRY,
+	.info = &m9mo_i2c_info,
+	.pixelformat = V4L2_PIX_FMT_UYVY,
+	.srclk_name = "xusbxti",	/* "mout_mpll" */
+	.clk_rate = 24000000,	/* 48000000 */
+	.line_length = 1920,
+	.width = 640,
+	.height = 480,
+	.window = {
+		.left = 0,
+		.top = 0,
+		.width = 640,
+		.height = 480,
+	},
+
+	.mipi_lanes = 4,
+	.mipi_settle = 12,
+	.mipi_align = 32,
+
+	/* Polarity */
+	.inv_pclk = 0,
+	.inv_vsync = 1,
+	.inv_href = 0,
+	.inv_hsync = 0,
+	.reset_camera = 0,
+	.initialized = 0,
+};
+#endif				/* #ifdef CONFIG_VIDEO_M9MO */
+
+#ifdef CONFIG_VIDEO_S5K5BAFX
+static int s5k5bafx_get_i2c_busnum(void)
+{
+	return 12;
+}
+
+static int s5k5bafx_power_on(void)
+{
+	struct regulator *regulator;
+	int ret = 0;
+
+	/* printk("%s: in\n", __func__); */
+
+	ret = gpio_request(GPIO_ISP_RESET, "ISP_RESET");
+	if (ret) {
+		printk(KERN_ERR "faile to request gpio(ISP_RESET)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_CAM_IO_EN, "GPE2");
+	if (ret) {
+		printk(KERN_ERR "faile to request gpio(GPIO_CAM_IO_EN)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_VT_CAM_15V, "GPE2");
+	if (ret) {
+		printk(KERN_ERR "faile to request gpio(GPIO_VT_CAM_15V)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_CAM_VGA_nSTBY, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "faile to request gpio(GPIO_CAM_VGA_nSTBY)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_CAM_VGA_nRST, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "faile to request gpio(GPIO_CAM_VGA_nRST)\n");
+		return ret;
+	}
+
+#ifndef CONFIG_MACH_U1_KOR_LGT
+	if (system_rev >= 9) {
+#endif
+		s3c_gpio_setpull(VT_CAM_SDA_18V, S3C_GPIO_PULL_NONE);
+		s3c_gpio_setpull(VT_CAM_SCL_18V, S3C_GPIO_PULL_NONE);
+#ifndef CONFIG_MACH_U1_KOR_LGT
+	}
+#endif
+
+	/* ISP_RESET low */
+	ret = gpio_direction_output(GPIO_ISP_RESET, 0);
+	CAM_CHECK_ERR_RET(ret, "output reset");
+	udelay(100);
+
+	/* CAM_ISP_CORE_1.2V */
+	regulator = regulator_get(NULL, "cam_isp_core");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "enable isp_core");
+	udelay(10);
+
+	/* CAM_SENSOR_A2.8V */
+	ret = gpio_direction_output(GPIO_CAM_IO_EN, 1);
+	CAM_CHECK_ERR_RET(ret, "output io_en");
+	udelay(300);		/* don't change me */
+
+	/* VT_CORE_1.5V */
+	ret = gpio_direction_output(GPIO_VT_CAM_15V, 1);
+	CAM_CHECK_ERR_RET(ret, "output vt_15v");
+	udelay(100);
+
+	/* CAM_ISP_1.8V */
+	regulator = regulator_get(NULL, "cam_isp");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "enable cam_isp");
+	udelay(10);
+
+	/* VT_CAM_1.8V */
+	regulator = regulator_get(NULL, "vt_cam_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "enable vt_1.8v");
+	udelay(10);
+
+	/* CAM_VGA_nSTBY */
+	ret = gpio_direction_output(GPIO_CAM_VGA_nSTBY, 1);
+	CAM_CHECK_ERR_RET(ret, "output VGA_nSTBY");
+	udelay(50);
+
+	/* Mclk */
+	ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_SFN(2));
+	s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_NONE);
+	CAM_CHECK_ERR_RET(ret, "cfg mclk");
+	udelay(100);
+
+	/* CAM_VGA_nRST	 */
+	ret = gpio_direction_output(GPIO_CAM_VGA_nRST, 1);
+	CAM_CHECK_ERR_RET(ret, "output VGA_nRST");
+	mdelay(2);
+
+	gpio_free(GPIO_ISP_RESET);
+	gpio_free(GPIO_CAM_IO_EN);
+	gpio_free(GPIO_VT_CAM_15V);
+	gpio_free(GPIO_CAM_VGA_nSTBY);
+	gpio_free(GPIO_CAM_VGA_nRST);
+
+	return 0;
+}
+
+static int s5k5bafx_power_off(void)
+{
+	struct regulator *regulator;
+	int ret = 0;
+
+	/* printk("n%s: in\n", __func__); */
+
+	ret = gpio_request(GPIO_CAM_VGA_nRST, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "faile to request gpio(GPIO_CAM_VGA_nRST)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_CAM_VGA_nSTBY, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "faile to request gpio(GPIO_CAM_VGA_nSTBY)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_VT_CAM_15V, "GPE2");
+	if (ret) {
+		printk(KERN_ERR "faile to request gpio(GPIO_VT_CAM_15V)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_CAM_IO_EN, "GPE2");
+	if (ret) {
+		printk(KERN_ERR "faile to request gpio(GPIO_CAM_IO_EN)\n");
+		return ret;
+	}
+
+	/* CAM_VGA_nRST	 */
+	ret = gpio_direction_output(GPIO_CAM_VGA_nRST, 0);
+	CAM_CHECK_ERR(ret, "output VGA_nRST");
+	udelay(100);
+
+	/* Mclk */
+	ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_DOWN);
+	CAM_CHECK_ERR(ret, "cfg mclk");
+	udelay(20);
+
+	/* CAM_VGA_nSTBY */
+	ret = gpio_direction_output(GPIO_CAM_VGA_nSTBY, 0);
+	CAM_CHECK_ERR(ret, "output VGA_nSTBY");
+	udelay(20);
+
+	/* VT_CAM_1.8V */
+	regulator = regulator_get(NULL, "vt_cam_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "disable vt_1.8v");
+	udelay(10);
+
+	/* CAM_ISP_1.8V */
+	regulator = regulator_get(NULL, "cam_isp");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "disable cam_isp");
+	udelay(10);
+
+	/* VT_CORE_1.5V */
+	ret = gpio_direction_output(GPIO_VT_CAM_15V, 0);
+	CAM_CHECK_ERR(ret, "output vt_1.5v");
+	udelay(10);
+
+	/* CAM_SENSOR_A2.8V */
+	ret = gpio_direction_output(GPIO_CAM_IO_EN, 0);
+	CAM_CHECK_ERR(ret, "output io_en");
+	udelay(10);
+
+	/* CAM_ISP_CORE_1.2V */
+	regulator = regulator_get(NULL, "cam_isp_core");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "disable isp_core");
+
+#ifndef CONFIG_MACH_U1_KOR_LGT
+	if (system_rev >= 9) {
+#endif
+		gpio_direction_input(VT_CAM_SDA_18V);
+		s3c_gpio_setpull(VT_CAM_SDA_18V, S3C_GPIO_PULL_DOWN);
+		gpio_direction_input(VT_CAM_SCL_18V);
+		s3c_gpio_setpull(VT_CAM_SCL_18V, S3C_GPIO_PULL_DOWN);
+#ifndef CONFIG_MACH_U1_KOR_LGT
+	}
+#endif
+
+#if defined(CONFIG_MACH_Q1_BD)
+	mdelay(350);
+#endif
+
+	gpio_free(GPIO_CAM_VGA_nRST);
+	gpio_free(GPIO_CAM_VGA_nSTBY);
+	gpio_free(GPIO_VT_CAM_15V);
+	gpio_free(GPIO_CAM_IO_EN);
+
+	return 0;
+}
+
+static int s5k5bafx_power(int onoff)
+{
+	int ret = 0;
+#if defined(CONFIG_MACH_U1_KOR_LGT)
+	u32 cfg = 0;
+#endif
+	printk(KERN_INFO "%s(): %s\n", __func__, onoff ? "on" : "down");
+
+#if defined(CONFIG_MACH_U1_KOR_LGT)
+	cfg = readl(S5P_VA_GPIO2 + 0x002c);
+#endif
+
+	if (onoff) {
+
+#if defined(CONFIG_MACH_U1_KOR_LGT)
+		writel(cfg | 0x0080, S5P_VA_GPIO2 + 0x002c);
+#endif
+
+		ret = s5k5bafx_power_on();
+		if (unlikely(ret))
+			goto error_out;
+	} else {
+
+#if defined(CONFIG_MACH_U1_KOR_LGT)
+		writel(cfg & 0xff3f, S5P_VA_GPIO2 + 0x002c);
+#endif
+		ret = s5k5bafx_power_off();
+		/* s3c_i2c0_force_stop(); *//* DSLIM. Should be implemented */
+	}
+
+	ret = s3c_csis_power(onoff);
+
+error_out:
+	return ret;
+}
+
+static struct s5k5bafx_platform_data s5k5bafx_plat = {
+	.default_width = 640,
+	.default_height = 480,
+	.pixelformat = V4L2_PIX_FMT_UYVY,
+	.freq = 24000000,
+	.is_mipi = 1,
+};
+
+static struct i2c_board_info s5k5bafx_i2c_info = {
+	I2C_BOARD_INFO("S5K5BAFX", 0x5A >> 1),
+	.platform_data = &s5k5bafx_plat,
+};
+
+static struct s3c_platform_camera s5k5bafx = {
+	.id = CAMERA_CSI_D,
+	.type = CAM_TYPE_MIPI,
+	.fmt = ITU_601_YCBCR422_8BIT,
+	.order422 = CAM_ORDER422_8BIT_CBYCRY,
+	.mipi_lanes = 1,
+	.mipi_settle = 6,
+	.mipi_align = 32,
+
+	.get_i2c_busnum = s5k5bafx_get_i2c_busnum,
+	.info = &s5k5bafx_i2c_info,
+	.pixelformat = V4L2_PIX_FMT_UYVY,
+	.srclk_name = "xusbxti",
+	.clk_name = "sclk_cam0",
+	.clk_rate = 24000000,
+	.line_length = 640,
+	.width = 640,
+	.height = 480,
+	.window = {
+		.left = 0,
+		.top = 0,
+		.width = 640,
+		.height = 480,
+	},
+
+	/* Polarity */
+	.inv_pclk = 0,
+	.inv_vsync = 1,
+	.inv_href = 0,
+	.inv_hsync = 0,
+	.reset_camera = 0,
+	.initialized = 0,
+	.cam_power = s5k5bafx_power,
+};
+#endif
+
+#ifdef WRITEBACK_ENABLED
+static int get_i2c_busnum_writeback(void)
+{
+	return 0;
+}
+
+static struct i2c_board_info writeback_i2c_info = {
+	I2C_BOARD_INFO("WriteBack", 0x0),
+};
+
+static struct s3c_platform_camera writeback = {
+	.id = CAMERA_WB,
+	.fmt = ITU_601_YCBCR422_8BIT,
+	.order422 = CAM_ORDER422_8BIT_CBYCRY,
+	.get_i2c_busnum = get_i2c_busnum_writeback,
+	.info = &writeback_i2c_info,
+	.pixelformat = V4L2_PIX_FMT_YUV444,
+	.line_length = 800,
+	.width = 480,
+	.height = 800,
+	.window = {
+		.left = 0,
+		.top = 0,
+		.width = 480,
+		.height = 800,
+	},
+
+	.initialized = 0,
+};
+#endif
+
+void cam_cfg_gpio(struct platform_device *pdev)
+{
+	int ret = 0;
+	printk(KERN_INFO "\n\n\n%s: pdev->id=%d\n", __func__, pdev->id);
+
+	if (pdev->id != 0)
+		return;
+}
+
+/* Interface setting */
+static struct s3c_platform_fimc fimc_plat = {
+#ifdef CONFIG_ITU_A
+	.default_cam = CAMERA_PAR_A,
+#endif
+#ifdef CONFIG_ITU_B
+	.default_cam = CAMERA_PAR_B,
+#endif
+#ifdef CONFIG_CSI_C
+	.default_cam = CAMERA_CSI_C,
+#endif
+#ifdef CONFIG_CSI_D
+	.default_cam = CAMERA_CSI_D,
+#endif
+	.camera = {
+#ifdef CONFIG_VIDEO_M9MO
+		&m9mo,
+#endif
+#ifdef CONFIG_VIDEO_S5K5BAFX
+		&s5k5bafx,
+#endif
+#ifdef WRITEBACK_ENABLED
+		&writeback,
+#endif
+	},
+	.hw_ver = 0x51,
+	.cfg_gpio = cam_cfg_gpio,
+};
+#endif				/* CONFIG_VIDEO_FIMC */
+
+static DEFINE_MUTEX(notify_lock);
+
+#define DEFINE_MMC_CARD_NOTIFIER(num) \
+static void (*hsmmc##num##_notify_func)(struct platform_device *, int state); \
+static int ext_cd_init_hsmmc##num(void (*notify_func)( \
+			struct platform_device *, int state)) \
+{ \
+	mutex_lock(&notify_lock); \
+	WARN_ON(hsmmc##num##_notify_func); \
+	hsmmc##num##_notify_func = notify_func; \
+	mutex_unlock(&notify_lock); \
+	return 0; \
+} \
+static int ext_cd_cleanup_hsmmc##num(void (*notify_func)( \
+			struct platform_device *, int state)) \
+{ \
+	mutex_lock(&notify_lock); \
+	WARN_ON(hsmmc##num##_notify_func != notify_func); \
+	hsmmc##num##_notify_func = NULL; \
+	mutex_unlock(&notify_lock); \
+	return 0; \
+}
+
+#ifdef CONFIG_S3C_DEV_HSMMC3
+	DEFINE_MMC_CARD_NOTIFIER(3)
+#endif
+
+/*
+ * call this when you need sd stack to recognize insertion or removal of card
+ * that can't be told by SDHCI regs
+ */
+
+void mmc_force_presence_change(struct platform_device *pdev)
+{
+	void (*notify_func)(struct platform_device *, int state) = NULL;
+	mutex_lock(&notify_lock);
+#ifdef CONFIG_S3C_DEV_HSMMC3
+	printk(KERN_INFO "---------test logs pdev : %p s3c_device_hsmmc3 %p\n",
+		pdev, &s3c_device_hsmmc3);
+	if (pdev == &s3c_device_hsmmc3) {
+		notify_func = hsmmc3_notify_func;
+		printk(KERN_INFO "---------test logs notify_func : %p\n",
+				notify_func);
+	}
+#endif
+
+	if (notify_func)
+		notify_func(pdev, 1);
+	else
+		pr_warn("%s: called for device with no notifier\n", __func__);
+	mutex_unlock(&notify_lock);
+}
+EXPORT_SYMBOL_GPL(mmc_force_presence_change);
+
+#ifdef CONFIG_S3C_DEV_HSMMC
+static struct s3c_sdhci_platdata exynos4_hsmmc0_pdata __initdata = {
+	.cd_type = S3C_SDHCI_CD_PERMANENT,
+	.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
+#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
+	.max_width = 8,
+	.host_caps = MMC_CAP_8_BIT_DATA,
+#endif
+};
+#endif
+
+#ifdef CONFIG_S3C_DEV_HSMMC2
+static struct s3c_sdhci_platdata exynos4_hsmmc2_pdata __initdata = {
+	.cd_type = S3C_SDHCI_CD_GPIO,
+	.ext_cd_gpio = EXYNOS4_GPX3(4),
+	.ext_cd_gpio_invert = 1,
+	.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
+	.vmmc_name = "vtf_2.8v",
+};
+#endif
+
+#ifdef CONFIG_S3C_DEV_HSMMC3
+static struct s3c_sdhci_platdata exynos4_hsmmc3_pdata __initdata = {
+/* For Wi-Fi */
+#if 0
+	.cd_type = S3C_SDHCI_CD_PERMANENT,
+	.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
+	.pm_flags = S3C_SDHCI_PM_IGNORE_SUSPEND_RESUME,
+#else
+	.cd_type = S3C_SDHCI_CD_EXTERNAL,
+	.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
+	.pm_flags = S3C_SDHCI_PM_IGNORE_SUSPEND_RESUME,
+	.ext_cd_init = ext_cd_init_hsmmc3,
+	.ext_cd_cleanup = ext_cd_cleanup_hsmmc3,
+#endif
+};
+#endif
+
+#ifdef CONFIG_EXYNOS4_DEV_MSHC
+static struct s3c_mshci_platdata exynos4_mshc_pdata __initdata = {
+	.cd_type = S3C_MSHCI_CD_PERMANENT,
+#if defined(CONFIG_EXYNOS4_MSHC_8BIT) &&	\
+	defined(CONFIG_EXYNOS4_MSHC_DDR)
+	.max_width = 8,
+	.host_caps = MMC_CAP_8_BIT_DATA | MMC_CAP_1_8V_DDR |
+			MMC_CAP_UHS_DDR50 | MMC_CAP_CMD23,
+#elif defined(CONFIG_EXYNOS4_MSHC_8BIT)
+	.max_width = 8,
+	.host_caps = MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
+#elif defined(CONFIG_EXYNOS4_MSHC_DDR)
+	.host_caps = MMC_CAP_1_8V_DDR | MMC_CAP_UHS_DDR50 |
+			MMC_CAP_CMD23,
+#endif
+	.int_power_gpio		= GPIO_XMMC0_CDn,
+};
+#endif
+
+#ifdef CONFIG_VIDEO_FIMG2D
+static struct fimg2d_platdata fimg2d_data __initdata = {
+	.hw_ver = 30,
+	.parent_clkname = "mout_g2d0",
+	.clkname = "sclk_fimg2d",
+	.gate_clkname = "fimg2d",
+	.clkrate = 267 * 1000000,	/* 266 Mhz */
+};
+#endif
+
+#ifdef CONFIG_FB_S3C
+#if defined(CONFIG_LCD_AMS369FG06)
+static int lcd_power_on(struct lcd_device *ld, int enable)
+{
+	return 1;
+}
+
+static int reset_lcd(struct lcd_device *ld)
+{
+	int err = 0;
+
+	err = gpio_request(EXYNOS4_GPX0(6), "GPX0");
+	if (err) {
+		printk(KERN_ERR "failed to request GPX0 for "
+		       "lcd reset control\n");
+		return err;
+	}
+
+	gpio_direction_output(EXYNOS4_GPX0(6), 1);
+	mdelay(100);
+
+	gpio_set_value(EXYNOS4_GPX0(6), 1);
+	mdelay(100);
+
+	gpio_free(EXYNOS4_GPX0(6));
+
+	return 1;
+}
+
+static struct lcd_platform_data ams369fg06_platform_data = {
+	.reset = reset_lcd,
+	.power_on = lcd_power_on,
+	.lcd_enabled = 0,
+	.reset_delay = 100,	/* 100ms */
+};
+
+#define		LCD_BUS_NUM	3
+#define		DISPLAY_CS	EXYNOS4_GPB(5)
+#define		DISPLAY_CLK	EXYNOS4_GPB(4)
+#define		DISPLAY_SI	EXYNOS4_GPB(7)
+
+static struct spi_board_info spi_board_info[] __initdata = {
+	{
+		.modalias = "ams369fg06",
+		.platform_data = (void *)&ams369fg06_platform_data,
+		.max_speed_hz = 1200000,
+		.bus_num = LCD_BUS_NUM,
+		.chip_select = 0,
+		.mode = SPI_MODE_3,
+		.controller_data = (void *)DISPLAY_CS,
+	}
+};
+
+static struct spi_gpio_platform_data ams369fg06_spi_gpio_data = {
+	.sck = DISPLAY_CLK,
+	.mosi = DISPLAY_SI,
+	.miso = -1,
+	.num_chipselect = 1,
+};
+
+static struct platform_device s3c_device_spi_gpio = {
+	.name = "spi_gpio",
+	.id = LCD_BUS_NUM,
+	.dev = {
+		.parent = &s5p_device_fimd0.dev,
+		.platform_data = &ams369fg06_spi_gpio_data,
+	},
+};
+
+static struct s3c_fb_pd_win smdkc210_fb_win0 = {
+	.win_mode = {
+		.left_margin = 9,
+		.right_margin = 9,
+		.upper_margin = 5,
+		.lower_margin = 5,
+		.hsync_len = 2,
+		.vsync_len = 2,
+		.xres = 480,
+		.yres = 800,
+	},
+	.virtual_x = 480,
+	.virtual_y = 1600,
+	.width = 48,
+	.height = 80,
+	.max_bpp = 32,
+	.default_bpp = 24,
+};
+
+static struct s3c_fb_pd_win smdkc210_fb_win1 = {
+	.win_mode = {
+		.left_margin = 9,
+		.right_margin = 9,
+		.upper_margin = 5,
+		.lower_margin = 5,
+		.hsync_len = 2,
+		.vsync_len = 2,
+		.xres = 480,
+		.yres = 800,
+	},
+	.virtual_x = 480,
+	.virtual_y = 1600,
+	.width = 48,
+	.height = 80,
+	.max_bpp = 32,
+	.default_bpp = 24,
+};
+
+static struct s3c_fb_pd_win smdkc210_fb_win2 = {
+	.win_mode = {
+		.left_margin = 9,
+		.right_margin = 9,
+		.upper_margin = 5,
+		.lower_margin = 5,
+		.hsync_len = 2,
+		.vsync_len = 2,
+		.xres = 480,
+		.yres = 800,
+	},
+	.virtual_x = 480,
+	.virtual_y = 1600,
+	.width = 48,
+	.height = 80,
+	.max_bpp = 32,
+	.default_bpp = 24,
+};
+
+#elif defined(CONFIG_LCD_WA101S)
+static void lcd_wa101s_set_power(struct plat_lcd_data *pd, unsigned int power)
+{
+	if (power) {
+#if !defined(CONFIG_BACKLIGHT_PWM)
+		gpio_request(EXYNOS4_GPD0(1), "GPD0");
+		gpio_direction_output(EXYNOS4_GPD0(1), 1);
+		gpio_free(EXYNOS4_GPD0(1));
+#endif
+	} else {
+#if !defined(CONFIG_BACKLIGHT_PWM)
+		gpio_request(EXYNOS4_GPD0(1), "GPD0");
+		gpio_direction_output(EXYNOS4_GPD0(1), 0);
+		gpio_free(EXYNOS4_GPD0(1));
+#endif
+	}
+}
+
+static struct plat_lcd_data smdkc210_lcd_wa101s_data = {
+	.set_power = lcd_wa101s_set_power,
+};
+
+static struct platform_device smdkc210_lcd_wa101s = {
+	.name = "platform-lcd",
+	.dev.parent = &s5p_device_fimd0.dev,
+	.dev.platform_data = &smdkc210_lcd_wa101s_data,
+};
+
+static struct s3c_fb_pd_win smdkc210_fb_win0 = {
+	.win_mode = {
+		.left_margin = 80,
+		.right_margin = 48,
+		.upper_margin = 14,
+		.lower_margin = 3,
+		.hsync_len = 32,
+		.vsync_len = 5,
+		.xres = 1366,
+		.yres = 768,
+	},
+	.virtual_x = 1366,
+	.virtual_y = 768 * 2,
+	.width = 223,
+	.height = 125,
+	.max_bpp = 32,
+	.default_bpp = 24,
+};
+
+#ifndef CONFIG_LCD_WA101S	/* temporarily disables window1 */
+static struct s3c_fb_pd_win smdkc210_fb_win1 = {
+	.win_mode = {
+		.left_margin = 80,
+		.right_margin = 48,
+		.upper_margin = 14,
+		.lower_margin = 3,
+		.hsync_len = 32,
+		.vsync_len = 5,
+		.xres = 1366,
+		.yres = 768,
+	},
+	.virtual_x = 1366,
+	.virtual_y = 768 * 2,
+	.max_bpp = 32,
+	.default_bpp = 24,
+};
+#endif
+
+#elif defined(CONFIG_LCD_LTE480WV)
+static void lcd_lte480wv_set_power(struct plat_lcd_data *pd, unsigned int power)
+{
+	if (power) {
+#if !defined(CONFIG_BACKLIGHT_PWM)
+		gpio_request(EXYNOS4_GPD0(1), "GPD0");
+		gpio_direction_output(EXYNOS4_GPD0(1), 1);
+		gpio_free(EXYNOS4_GPD0(1));
+#endif
+		/* fire nRESET on power up */
+		gpio_request(EXYNOS4_GPX0(6), "GPX0");
+
+		gpio_direction_output(EXYNOS4_GPX0(6), 1);
+		mdelay(100);
+
+		gpio_set_value(EXYNOS4_GPX0(6), 0);
+		mdelay(10);
+
+		gpio_set_value(EXYNOS4_GPX0(6), 1);
+		mdelay(10);
+
+		gpio_free(EXYNOS4_GPX0(6));
+	} else {
+#if !defined(CONFIG_BACKLIGHT_PWM)
+		gpio_request(EXYNOS4_GPD0(1), "GPD0");
+		gpio_direction_output(EXYNOS4_GPD0(1), 0);
+		gpio_free(EXYNOS4_GPD0(1));
+#endif
+	}
+}
+
+static struct plat_lcd_data smdkc210_lcd_lte480wv_data = {
+	.set_power = lcd_lte480wv_set_power,
+};
+
+static struct platform_device smdkc210_lcd_lte480wv = {
+	.name = "platform-lcd",
+	.dev.parent = &s5p_device_fimd0.dev,
+	.dev.platform_data = &smdkc210_lcd_lte480wv_data,
+};
+
+static struct s3c_fb_pd_win smdkc210_fb_win0 = {
+	.win_mode = {
+		.left_margin = 13,
+		.right_margin = 8,
+		.upper_margin = 7,
+		.lower_margin = 5,
+		.hsync_len = 3,
+		.vsync_len = 1,
+		.xres = 800,
+		.yres = 480,
+	},
+	.virtual_x = 800,
+	.virtual_y = 960,
+	.max_bpp = 32,
+	.default_bpp = 24,
+};
+
+static struct s3c_fb_pd_win smdkc210_fb_win1 = {
+	.win_mode = {
+		.left_margin = 13,
+		.right_margin = 8,
+		.upper_margin = 7,
+		.lower_margin = 5,
+		.hsync_len = 3,
+		.vsync_len = 1,
+		.xres = 800,
+		.yres = 480,
+	},
+	.virtual_x = 800,
+	.virtual_y = 960,
+	.max_bpp = 32,
+	.default_bpp = 24,
+};
+#endif
+
+static struct s3c_fb_platdata smdkc210_lcd0_pdata __initdata = {
+#if defined(CONFIG_LCD_AMS369FG06) || defined(CONFIG_LCD_WA101S) ||	\
+	defined(CONFIG_LCD_LTE480WV)
+	.win[0] = &smdkc210_fb_win0,
+#ifndef CONFIG_LCD_WA101S	/* temporarily disables window1 */
+	.win[1] = &smdkc210_fb_win1,
+#endif
+#endif
+	.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+#if defined(CONFIG_LCD_AMS369FG06)
+	.vidcon1 = VIDCON1_INV_VCLK | VIDCON1_INV_VDEN |
+	VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+#elif defined(CONFIG_LCD_WA101S)
+	.vidcon1 = VIDCON1_INV_VCLK | VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+#elif defined(CONFIG_LCD_LTE480WV)
+	.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+#endif
+	.setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
+};
+#endif
+
+#ifdef CONFIG_S3C64XX_DEV_SPI
+static struct s3c64xx_spi_csinfo spi0_csi[] = {
+	[0] = {
+		.line = EXYNOS4_GPB(1),
+		.set_level = gpio_set_value,
+		.fb_delay = 0x0,
+	},
+};
+
+static struct spi_board_info spi0_board_info[] __initdata = {
+#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE)
+	{
+		.modalias = "tdmbspi",
+		.platform_data = NULL,
+		.max_speed_hz = 5000000,
+		.bus_num = 0,
+		.chip_select = 0,
+		.mode = SPI_MODE_0,
+		.controller_data = &spi0_csi[0],
+	},
+#elif defined(CONFIG_ISDBT_FC8100)
+	{
+		.modalias	=	"isdbtspi",
+		.platform_data	=	NULL,
+		.max_speed_hz	=	400000,
+		.bus_num	=	0,
+		.chip_select	=	0,
+		.mode		=	(SPI_MODE_0|SPI_CS_HIGH),
+		.controller_data	=	&spi0_csi[0],
+	},
+
+#else
+	{
+		.modalias = "spidev",
+		.platform_data = NULL,
+		.max_speed_hz = 10 * 1000 * 1000,
+		.bus_num = 0,
+		.chip_select = 0,
+		.mode = SPI_MODE_0,
+		.controller_data = &spi0_csi[0],
+	}
+#endif
+};
+#endif
+
+#ifdef CONFIG_FB_S5P
+unsigned int lcdtype;
+static int __init lcdtype_setup(char *str)
+{
+	get_option(&str, &lcdtype);
+	return 1;
+}
+__setup("lcdtype=", lcdtype_setup);
+
+#ifdef CONFIG_FB_S5P_LD9040
+unsigned int ld9040_lcdtype;
+static int __init ld9040_lcdtype_setup(char *str)
+{
+	get_option(&str, &ld9040_lcdtype);
+	return 1;
+}
+
+__setup("ld9040.get_lcdtype=0x", ld9040_lcdtype_setup);
+
+static int lcd_cfg_gpio(void)
+{
+	int i, f3_end = 4;
+
+	for (i = 0; i < 8; i++) {
+		/* set GPF0,1,2[0:7] for RGB Interface and Data line (32bit) */
+		s3c_gpio_cfgpin(EXYNOS4_GPF0(i), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(EXYNOS4_GPF0(i), S3C_GPIO_PULL_NONE);
+
+	}
+	for (i = 0; i < 8; i++) {
+		s3c_gpio_cfgpin(EXYNOS4_GPF1(i), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(EXYNOS4_GPF1(i), S3C_GPIO_PULL_NONE);
+	}
+
+	for (i = 0; i < 8; i++) {
+		s3c_gpio_cfgpin(EXYNOS4_GPF2(i), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(EXYNOS4_GPF2(i), S3C_GPIO_PULL_NONE);
+	}
+
+	for (i = 0; i < f3_end; i++) {
+		s3c_gpio_cfgpin(EXYNOS4_GPF3(i), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(EXYNOS4_GPF3(i), S3C_GPIO_PULL_NONE);
+	}
+
+#ifdef MAX_DRVSTR
+	/* drive strength to max */
+	writel(0xffffffff, S5P_VA_GPIO + 0x18c);
+	writel(0xffffffff, S5P_VA_GPIO + 0x1ac);
+	writel(0xffffffff, S5P_VA_GPIO + 0x1cc);
+	writel(readl(S5P_VA_GPIO + 0x1ec) | 0xffffff, S5P_VA_GPIO + 0x1ec);
+#else
+	/* drive strength to 2X */
+	writel(0xaaaaaaaa, S5P_VA_GPIO + 0x18c);
+	writel(0xaaaaaaaa, S5P_VA_GPIO + 0x1ac);
+	writel(0xaaaaaaaa, S5P_VA_GPIO + 0x1cc);
+	writel(readl(S5P_VA_GPIO + 0x1ec) | 0xaaaaaa, S5P_VA_GPIO + 0x1ec);
+#endif
+
+#if !defined(CONFIG_MACH_U1_KOR_LGT)
+	/* MLCD_RST */
+	s3c_gpio_cfgpin(EXYNOS4_GPY4(5), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPY4(5), S3C_GPIO_PULL_NONE);
+
+	/* LCD_nCS */
+	s3c_gpio_cfgpin(EXYNOS4_GPY4(3), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPY4(3), S3C_GPIO_PULL_NONE);
+	/* LCD_SCLK */
+	s3c_gpio_cfgpin(EXYNOS4_GPY3(1), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPY3(1), S3C_GPIO_PULL_NONE);
+	/* LCD_SDI */
+	s3c_gpio_cfgpin(EXYNOS4_GPY3(3), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPY3(3), S3C_GPIO_PULL_NONE);
+#else
+	/* MLCD_RST */
+	s3c_gpio_cfgpin(EXYNOS4_GPX1(3), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPX1(3), S3C_GPIO_PULL_NONE);
+	/* LCD_nCS */
+	s3c_gpio_cfgpin(EXYNOS4_GPY0(3), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPY0(3), S3C_GPIO_PULL_NONE);
+	/* LCD_SCLK */
+	s3c_gpio_cfgpin(EXYNOS4210_GPE2(3), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4210_GPE2(3), S3C_GPIO_PULL_NONE);
+	/* LCD_SDI */
+	s3c_gpio_cfgpin(EXYNOS4_GPX1(1), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPX1(1), S3C_GPIO_PULL_NONE);
+#endif
+
+	return 0;
+}
+
+static int lcd_power_on(struct lcd_device *ld, int enable)
+{
+	struct regulator *regulator;
+
+	if (ld == NULL) {
+		printk(KERN_ERR "lcd device object is NULL.\n");
+		return 0;
+	}
+
+	if (enable) {
+		regulator = regulator_get(NULL, "vlcd_3.0v");
+		if (IS_ERR(regulator))
+			return 0;
+
+		regulator_enable(regulator);
+		regulator_put(regulator);
+	} else {
+		regulator = regulator_get(NULL, "vlcd_3.0v");
+
+		if (IS_ERR(regulator))
+			return 0;
+
+		if (regulator_is_enabled(regulator))
+			regulator_force_disable(regulator);
+
+		regulator_put(regulator);
+	}
+
+	return 1;
+}
+
+static int reset_lcd(struct lcd_device *ld)
+{
+	int reset_gpio = -1;
+	int err;
+
+#if !defined(CONFIG_MACH_U1_KOR_LGT)
+	reset_gpio = EXYNOS4_GPY4(5);
+#else
+	reset_gpio = EXYNOS4_GPX1(3);
+#endif
+
+	err = gpio_request(reset_gpio, "MLCD_RST");
+	if (err) {
+		printk(KERN_ERR "failed to request MLCD_RST for "
+		       "lcd reset control\n");
+		return err;
+	}
+
+	gpio_request(reset_gpio, "MLCD_RST");
+
+	gpio_direction_output(reset_gpio, 1);
+	mdelay(5);
+	gpio_direction_output(reset_gpio, 0);
+	mdelay(5);
+	gpio_direction_output(reset_gpio, 1);
+
+	gpio_free(reset_gpio);
+
+	return 1;
+}
+
+static int lcd_gpio_cfg_earlysuspend(struct lcd_device *ld)
+{
+	int reset_gpio = -1;
+	int err;
+
+#if !defined(CONFIG_MACH_U1_KOR_LGT)
+	reset_gpio = EXYNOS4_GPY4(5);
+#else
+	reset_gpio = EXYNOS4_GPX1(3);
+#endif
+
+	err = gpio_request(reset_gpio, "MLCD_RST");
+	if (err) {
+		printk(KERN_ERR "failed to request MLCD_RST for "
+		       "lcd reset control\n");
+		return err;
+	}
+
+	mdelay(5);
+	gpio_direction_output(reset_gpio, 0);
+
+	gpio_free(reset_gpio);
+
+	return 0;
+}
+
+static int lcd_gpio_cfg_lateresume(struct lcd_device *ld)
+{
+#if !defined(CONFIG_MACH_U1_KOR_LGT)
+	/* MLCD_RST */
+	s3c_gpio_cfgpin(EXYNOS4_GPY4(5), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPY4(5), S3C_GPIO_PULL_NONE);
+
+	/* LCD_nCS */
+	s3c_gpio_cfgpin(EXYNOS4_GPY4(3), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPY4(3), S3C_GPIO_PULL_NONE);
+	/* LCD_SCLK */
+	s3c_gpio_cfgpin(EXYNOS4_GPY3(1), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPY3(1), S3C_GPIO_PULL_NONE);
+	/* LCD_SDI */
+	s3c_gpio_cfgpin(EXYNOS4_GPY3(3), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPY3(3), S3C_GPIO_PULL_NONE);
+#else
+	/* MLCD_RST */
+	s3c_gpio_cfgpin(EXYNOS4_GPX1(3), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPX1(3), S3C_GPIO_PULL_NONE);
+	/* LCD_nCS */
+	s3c_gpio_cfgpin(EXYNOS4_GPY0(3), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPY0(3), S3C_GPIO_PULL_NONE);
+	/* LCD_SCLK */
+	s3c_gpio_cfgpin(EXYNOS4210_GPE2(3), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4210_GPE2(3), S3C_GPIO_PULL_NONE);
+	/* LCD_SDI */
+	s3c_gpio_cfgpin(EXYNOS4_GPX1(1), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPX1(1), S3C_GPIO_PULL_NONE);
+#endif
+
+	return 0;
+}
+
+static struct s3cfb_lcd ld9040_info = {
+	.width = 480,
+	.height = 800,
+	.p_width = 56,
+	.p_height = 93,
+	.bpp = 24,
+
+	.freq = 60,
+	.timing = {
+		.h_fp = 16,
+		.h_bp = 14,
+		.h_sw = 2,
+		.v_fp = 10,
+		.v_fpe = 1,
+		.v_bp = 4,
+		.v_bpe = 1,
+		.v_sw = 2,
+	},
+	.polarity = {
+		.rise_vclk = 1,
+		.inv_hsync = 1,
+		.inv_vsync = 1,
+		.inv_vden = 1,
+	},
+};
+
+static struct lcd_platform_data ld9040_platform_data = {
+	.reset = reset_lcd,
+	.power_on = lcd_power_on,
+	.gpio_cfg_earlysuspend = lcd_gpio_cfg_earlysuspend,
+	.gpio_cfg_lateresume = lcd_gpio_cfg_lateresume,
+	/* it indicates whether lcd panel is enabled from u-boot. */
+	.lcd_enabled = 1,
+	.reset_delay = 20,	/* 10ms */
+	.power_on_delay = 20,	/* 20ms */
+	.power_off_delay = 200,	/* 120ms */
+	.pdata = &u1_panel_data,
+};
+
+#define LCD_BUS_NUM	3
+#if !defined(CONFIG_MACH_U1_KOR_LGT)
+#define DISPLAY_CS	EXYNOS4_GPY4(3)
+#else
+#define DISPLAY_CS	EXYNOS4_GPY0(3)
+#endif
+static struct spi_board_info spi_board_info[] __initdata = {
+	{
+		.max_speed_hz = 1200000,
+		.bus_num = LCD_BUS_NUM,
+		.chip_select = 0,
+		.mode = SPI_MODE_3,
+		.controller_data = (void *)DISPLAY_CS,
+	},
+};
+
+#if !defined(CONFIG_MACH_U1_KOR_LGT)
+#define DISPLAY_CLK	EXYNOS4_GPY3(1)
+#define DISPLAY_SI	EXYNOS4_GPY3(3)
+#else
+#define DISPLAY_CLK	EXYNOS4210_GPE2(3)
+#define DISPLAY_SI	EXYNOS4_GPX1(1)
+#endif
+static struct spi_gpio_platform_data lcd_spi_gpio_data = {
+	.sck = DISPLAY_CLK,
+	.mosi = DISPLAY_SI,
+	.miso = SPI_GPIO_NO_MISO,
+	.num_chipselect = 1,
+};
+
+static struct platform_device ld9040_spi_gpio = {
+	.name = "spi_gpio",
+	.id = LCD_BUS_NUM,
+	.dev = {
+		.parent = &s3c_device_fb.dev,
+		.platform_data = &lcd_spi_gpio_data,
+	},
+};
+
+static struct s3c_platform_fb fb_platform_data __initdata = {
+	.hw_ver = 0x70,
+	.clk_name = "fimd",
+	.nr_wins = 5,
+#ifdef CONFIG_FB_S5P_DEFAULT_WINDOW
+	.default_win = CONFIG_FB_S5P_DEFAULT_WINDOW,
+#else
+	.default_win = 0,
+#endif
+	.swap = FB_SWAP_HWORD | FB_SWAP_WORD,
+	.lcd = &ld9040_info,
+};
+
+/* reading with 3-WIRE SPI with GPIO */
+static inline void setcs(u8 is_on)
+{
+	gpio_set_value(DISPLAY_CS, is_on);
+}
+
+static inline void setsck(u8 is_on)
+{
+	gpio_set_value(DISPLAY_CLK, is_on);
+}
+
+static inline void setmosi(u8 is_on)
+{
+	gpio_set_value(DISPLAY_SI, is_on);
+}
+
+static inline unsigned int getmiso(void)
+{
+	return !!gpio_get_value(DISPLAY_SI);
+}
+
+static inline void setmosi2miso(u8 is_on)
+{
+	if (is_on)
+		s3c_gpio_cfgpin(DISPLAY_SI, S3C_GPIO_INPUT);
+	else
+		s3c_gpio_cfgpin(DISPLAY_SI, S3C_GPIO_OUTPUT);
+}
+
+struct spi_ops ops = {
+	.setcs = setcs,
+	.setsck = setsck,
+	.setmosi = setmosi,
+	.setmosi2miso = setmosi2miso,
+	.getmiso = getmiso,
+};
+
+static void __init ld9040_fb_init(void)
+{
+	struct ld9040_panel_data *pdata;
+
+	strcpy(spi_board_info[0].modalias, "ld9040");
+	spi_board_info[0].platform_data = (void *)&ld9040_platform_data;
+
+	lcdtype = max(ld9040_lcdtype, lcdtype);
+
+	if (lcdtype == LCDTYPE_SM2_A2)
+		ld9040_platform_data.pdata = &u1_panel_data_a2;
+	else if (lcdtype == LCDTYPE_M2)
+		ld9040_platform_data.pdata = &u1_panel_data_m2;
+
+	pdata = ld9040_platform_data.pdata;
+	pdata->ops = &ops;
+
+	printk(KERN_INFO "%s :: lcdtype=%d\n", __func__, lcdtype);
+
+	spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
+
+	if (!ld9040_platform_data.lcd_enabled)
+		lcd_cfg_gpio();
+	s3cfb_set_platdata(&fb_platform_data);
+}
+#endif
+
+#ifdef CONFIG_FB_S5P_NT35560
+static int lcd_cfg_gpio(void)
+{
+	int i, f3_end = 4;
+
+	for (i = 0; i < 8; i++) {
+		/* set GPF0,1,2[0:7] for RGB Interface and Data line (32bit) */
+		s3c_gpio_cfgpin(EXYNOS4_GPF0(i), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(EXYNOS4_GPF0(i), S3C_GPIO_PULL_NONE);
+
+	}
+	for (i = 0; i < 8; i++) {
+		s3c_gpio_cfgpin(EXYNOS4_GPF1(i), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(EXYNOS4_GPF1(i), S3C_GPIO_PULL_NONE);
+	}
+
+	for (i = 0; i < 8; i++) {
+		s3c_gpio_cfgpin(EXYNOS4_GPF2(i), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(EXYNOS4_GPF2(i), S3C_GPIO_PULL_NONE);
+	}
+
+	for (i = 0; i < f3_end; i++) {
+		s3c_gpio_cfgpin(EXYNOS4_GPF3(i), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(EXYNOS4_GPF3(i), S3C_GPIO_PULL_NONE);
+	}
+
+#ifdef MAX_DRVSTR
+	/* drive strength to max */
+	writel(0xffffffff, S5P_VA_GPIO + 0x18c);
+	writel(0xffffffff, S5P_VA_GPIO + 0x1ac);
+	writel(0xffffffff, S5P_VA_GPIO + 0x1cc);
+	writel(readl(S5P_VA_GPIO + 0x1ec) | 0xffffff, S5P_VA_GPIO + 0x1ec);
+#else
+	/* drive strength to 2X */
+	writel(0xaaaaaaaa, S5P_VA_GPIO + 0x18c);
+	writel(0xaaaaaaaa, S5P_VA_GPIO + 0x1ac);
+	writel(0xaaaaaaaa, S5P_VA_GPIO + 0x1cc);
+	writel(readl(S5P_VA_GPIO + 0x1ec) | 0xaaaaaa, S5P_VA_GPIO + 0x1ec);
+#endif
+
+	/* MLCD_RST */
+	s3c_gpio_cfgpin(EXYNOS4_GPY4(5), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPY4(5), S3C_GPIO_PULL_NONE);
+
+	/* LCD_nCS */
+	s3c_gpio_cfgpin(EXYNOS4_GPY4(3), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPY4(3), S3C_GPIO_PULL_NONE);
+
+	/* LCD_SCLK */
+	s3c_gpio_cfgpin(EXYNOS4_GPY3(1), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPY3(1), S3C_GPIO_PULL_NONE);
+
+	/* LCD_SDI */
+	s3c_gpio_cfgpin(EXYNOS4_GPY3(3), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPY3(3), S3C_GPIO_PULL_NONE);
+
+	return 0;
+}
+
+static int lcd_power_on(struct lcd_device *ld, int enable)
+{
+	struct regulator *regulator;
+
+	if (ld == NULL) {
+		printk(KERN_ERR "lcd device object is NULL.\n");
+		return 0;
+	}
+
+	if (enable) {
+		regulator = regulator_get(NULL, "vlcd_3.0v");
+		if (IS_ERR(regulator))
+			return 0;
+
+		regulator_enable(regulator);
+		regulator_put(regulator);
+
+		regulator = regulator_get(NULL, "vlcd_1.8v");
+		if (IS_ERR(regulator))
+			return 0;
+
+		regulator_enable(regulator);
+		regulator_put(regulator);
+	} else {
+		regulator = regulator_get(NULL, "vlcd_1.8v");
+
+		if (IS_ERR(regulator))
+			return 0;
+
+		if (regulator_is_enabled(regulator))
+			regulator_force_disable(regulator);
+
+		regulator_put(regulator);
+
+		regulator = regulator_get(NULL, "vlcd_3.0v");
+
+		if (IS_ERR(regulator))
+			return 0;
+
+		if (regulator_is_enabled(regulator))
+			regulator_force_disable(regulator);
+
+		regulator_put(regulator);
+	}
+
+	return 1;
+}
+
+static int reset_lcd(struct lcd_device *ld)
+{
+	int reset_gpio = -1;
+	int err;
+
+	reset_gpio = EXYNOS4_GPY4(5);
+
+	err = gpio_request(reset_gpio, "MLCD_RST");
+	if (err) {
+		printk(KERN_ERR "failed to request MLCD_RST for "
+		       "lcd reset control\n");
+		return err;
+	}
+
+	gpio_request(reset_gpio, "MLCD_RST");
+
+	gpio_direction_output(reset_gpio, 1);
+	mdelay(5);
+	gpio_direction_output(reset_gpio, 0);
+	mdelay(5);
+	gpio_direction_output(reset_gpio, 1);
+
+	gpio_free(reset_gpio);
+
+	return 1;
+}
+
+static int lcd_gpio_cfg_earlysuspend(struct lcd_device *ld)
+{
+	int reset_gpio = -1;
+	int err;
+
+	reset_gpio = EXYNOS4_GPY4(5);
+
+	err = gpio_request(reset_gpio, "MLCD_RST");
+	if (err) {
+		printk(KERN_ERR "failed to request MLCD_RST for "
+		       "lcd reset control\n");
+		return err;
+	}
+
+	mdelay(5);
+	gpio_direction_output(reset_gpio, 0);
+
+	gpio_free(reset_gpio);
+
+	return 0;
+}
+
+static int lcd_gpio_cfg_lateresume(struct lcd_device *ld)
+{
+	/* MLCD_RST */
+	s3c_gpio_cfgpin(EXYNOS4_GPY4(5), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPY4(5), S3C_GPIO_PULL_NONE);
+
+	/* LCD_nCS */
+	s3c_gpio_cfgpin(EXYNOS4_GPY4(3), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPY4(3), S3C_GPIO_PULL_NONE);
+
+	/* LCD_SCLK */
+	s3c_gpio_cfgpin(EXYNOS4_GPY3(1), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPY3(1), S3C_GPIO_PULL_NONE);
+
+	/* LCD_SDI */
+	s3c_gpio_cfgpin(EXYNOS4_GPY3(3), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPY3(3), S3C_GPIO_PULL_NONE);
+
+	return 0;
+}
+
+static struct s3cfb_lcd nt35560_info = {
+	.width = 480,
+	.height = 800,
+	.p_width = 52,
+	.p_height = 86,
+	.bpp = 24,
+
+	.freq = 60,
+	.timing = {
+		.h_fp = 10,
+		.h_bp = 10,
+		.h_sw = 10,
+		.v_fp = 9,
+		.v_fpe = 1,
+		.v_bp = 4,
+		.v_bpe = 1,
+		.v_sw = 2,
+	},
+	.polarity = {
+		.rise_vclk = 1,
+		.inv_hsync = 1,
+		.inv_vsync = 1,
+		.inv_vden = 1,
+	},
+};
+
+static struct lcd_platform_data nt35560_platform_data = {
+	.reset = reset_lcd,
+	.power_on = lcd_power_on,
+	.gpio_cfg_earlysuspend = lcd_gpio_cfg_earlysuspend,
+	.gpio_cfg_lateresume = lcd_gpio_cfg_lateresume,
+	/* it indicates whether lcd panel is enabled from u-boot. */
+	.lcd_enabled = 1,
+	.reset_delay = 10,	/* 10ms */
+	.power_on_delay = 10,	/* 10ms */
+	.power_off_delay = 150,	/* 150ms */
+};
+
+#define LCD_BUS_NUM	3
+#define DISPLAY_CS	EXYNOS4_GPY4(3)
+static struct spi_board_info spi_board_info[] __initdata = {
+	{
+		.max_speed_hz = 1200000,
+		.bus_num = LCD_BUS_NUM,
+		.chip_select = 0,
+		.mode = SPI_MODE_3,
+		.controller_data = (void *)DISPLAY_CS,
+	},
+};
+
+#define DISPLAY_CLK	EXYNOS4_GPY3(1)
+#define DISPLAY_SI	EXYNOS4_GPY3(3)
+static struct spi_gpio_platform_data lcd_spi_gpio_data = {
+	.sck = DISPLAY_CLK,
+	.mosi = DISPLAY_SI,
+	.miso = SPI_GPIO_NO_MISO,
+	.num_chipselect = 1,
+};
+
+static struct platform_device nt35560_spi_gpio = {
+	.name = "spi_gpio",
+	.id = LCD_BUS_NUM,
+	.dev = {
+		.parent = &s3c_device_fb.dev,
+		.platform_data = &lcd_spi_gpio_data,
+	},
+};
+
+static struct s3c_platform_fb fb_platform_data __initdata = {
+	.hw_ver = 0x70,
+	.clk_name = "fimd",
+	.nr_wins = 5,
+#ifdef CONFIG_FB_S5P_DEFAULT_WINDOW
+	.default_win = CONFIG_FB_S5P_DEFAULT_WINDOW,
+#else
+	.default_win = 0,
+#endif
+	.swap = FB_SWAP_HWORD | FB_SWAP_WORD,
+	.lcd = &nt35560_info,
+};
+
+static void __init nt35560_fb_init(void)
+{
+	struct ld9040_panel_data *pdata;
+
+	strcpy(spi_board_info[0].modalias, "nt35560");
+	spi_board_info[0].platform_data = (void *)&nt35560_platform_data;
+
+	pdata = nt35560_platform_data.pdata;
+
+	spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
+
+	if (!nt35560_platform_data.lcd_enabled)
+		lcd_cfg_gpio();
+	s3cfb_set_platdata(&fb_platform_data);
+}
+#endif
+
+#ifdef CONFIG_FB_S5P_AMS369FG06
+static struct s3c_platform_fb ams369fg06_data __initdata = {
+	.hw_ver = 0x70,
+	.clk_name = "sclk_lcd",
+	.nr_wins = 5,
+	.default_win = CONFIG_FB_S5P_DEFAULT_WINDOW,
+	.swap = FB_SWAP_HWORD | FB_SWAP_WORD,
+};
+
+#define		LCD_BUS_NUM	3
+#define		DISPLAY_CS	EXYNOS4_GPB(5)
+#define		DISPLAY_CLK	EXYNOS4_GPB(4)
+#define		DISPLAY_SI	EXYNOS4_GPB(7)
+
+static struct spi_board_info spi_board_info[] __initdata = {
+	{
+		.modalias = "ams369fg06",
+		.platform_data = NULL,
+		.max_speed_hz = 1200000,
+		.bus_num = LCD_BUS_NUM,
+		.chip_select = 0,
+		.mode = SPI_MODE_3,
+		.controller_data = (void *)DISPLAY_CS,
+	}
+};
+
+static struct spi_gpio_platform_data ams369fg06_spi_gpio_data = {
+	.sck = DISPLAY_CLK,
+	.mosi = DISPLAY_SI,
+	.miso = -1,
+	.num_chipselect = 1,
+};
+
+static struct platform_device s3c_device_spi_gpio = {
+	.name = "spi_gpio",
+	.id = LCD_BUS_NUM,
+	.dev = {
+		.parent = &s3c_device_fb.dev,
+		.platform_data = &ams369fg06_spi_gpio_data,
+	},
+};
+#endif
+
+#ifdef CONFIG_FB_S5P_MDNIE
+static struct platform_device mdnie_device = {
+	.name = "mdnie",
+	.id = -1,
+	.dev = {
+		.parent = &exynos4_device_pd[PD_LCD0].dev,
+	},
+};
+#endif
+
+#endif
+
+static struct platform_device u1_regulator_consumer = {
+	.name = "u1-regulator-consumer",
+	.id = -1,
+};
+
+#ifdef CONFIG_REGULATOR_MAX8997
+static struct regulator_consumer_supply ldo1_supply[] = {
+	REGULATOR_SUPPLY("vadc_3.3v", NULL),
+};
+
+static struct regulator_consumer_supply ldo3_supply[] = {
+	REGULATOR_SUPPLY("vusb_1.1v", "usb_otg"),
+	REGULATOR_SUPPLY("vmipi_1.1v", "m9mo"),
+	REGULATOR_SUPPLY("vmipi_1.1v", NULL),
+};
+
+static struct regulator_consumer_supply ldo4_supply[] = {
+	REGULATOR_SUPPLY("vmipi_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo5_supply[] = {
+	REGULATOR_SUPPLY("vhsic", NULL),
+};
+
+static struct regulator_consumer_supply ldo7_supply[] = {
+	REGULATOR_SUPPLY("cam_isp", NULL),
+};
+
+static struct regulator_consumer_supply ldo8_supply[] = {
+	REGULATOR_SUPPLY("vusb_3.3v", NULL),
+};
+
+#if defined(CONFIG_S5PV310_HI_ARMCLK_THAN_1_2GHZ)
+static struct regulator_consumer_supply ldo10_supply[] = {
+	REGULATOR_SUPPLY("vpll_1.2v", NULL),
+};
+#else
+static struct regulator_consumer_supply ldo10_supply[] = {
+	REGULATOR_SUPPLY("vpll_1.1v", NULL),
+};
+#endif
+
+#if defined(CONFIG_MACH_U1CAMERA_BD)
+static struct regulator_consumer_supply ldo11_supply[] = {
+	REGULATOR_SUPPLY("top_3.3v", NULL),
+};
+#else
+static struct regulator_consumer_supply ldo11_supply[] = {
+	REGULATOR_SUPPLY("touch", NULL),
+};
+#endif
+
+#if defined(CONFIG_MACH_U1CAMERA_BD)
+static struct regulator_consumer_supply ldo12_supply[] = {
+	REGULATOR_SUPPLY("vlcd_1.8v", NULL),
+};
+#else
+static struct regulator_consumer_supply ldo12_supply[] = {
+	REGULATOR_SUPPLY("vt_cam_1.8v", NULL),
+};
+#endif
+
+static struct regulator_consumer_supply ldo13_supply[] = {
+	REGULATOR_SUPPLY("vlcd_3.0v", NULL),
+};
+
+#ifdef CONFIG_MACH_Q1_BD
+static struct regulator_consumer_supply ldo14_supply[] = {
+	REGULATOR_SUPPLY("vlcd_2.2v", NULL),
+};
+#else
+static struct regulator_consumer_supply ldo14_supply[] = {
+	REGULATOR_SUPPLY("vmotor", NULL),
+};
+#endif
+
+#if defined(CONFIG_MACH_U1CAMERA_BD)
+static struct regulator_consumer_supply ldo15_supply[] = {
+	REGULATOR_SUPPLY("ois_1.5v", NULL),
+};
+#else
+static struct regulator_consumer_supply ldo15_supply[] = {
+	REGULATOR_SUPPLY("vled", NULL),
+};
+#endif
+
+#if defined(CONFIG_MACH_U1CAMERA_BD)
+static struct regulator_consumer_supply ldo16_supply[] = {
+	REGULATOR_SUPPLY("cis_1.8v", NULL),
+};
+#else
+static struct regulator_consumer_supply ldo16_supply[] = {
+	REGULATOR_SUPPLY("cam_sensor_io", NULL),
+};
+#endif
+
+static struct regulator_consumer_supply ldo17_supply[] = {
+	REGULATOR_SUPPLY("vtf_2.8v", NULL),
+};
+
+#if defined(CONFIG_MACH_U1CAMERA_BD)
+static struct regulator_consumer_supply ldo18_supply[] = {
+	REGULATOR_SUPPLY("cis_2.8v", NULL),
+};
+#else
+static struct regulator_consumer_supply ldo18_supply[] = {
+	REGULATOR_SUPPLY("touch_led", NULL),
+};
+#endif
+
+
+static struct regulator_consumer_supply ldo21_supply[] = {
+	REGULATOR_SUPPLY("vddq_m1m2", NULL),
+};
+
+static struct regulator_consumer_supply buck1_supply[] = {
+	REGULATOR_SUPPLY("vdd_arm", NULL),
+};
+
+static struct regulator_consumer_supply buck2_supply[] = {
+	REGULATOR_SUPPLY("vdd_int", NULL),
+};
+
+static struct regulator_consumer_supply buck3_supply[] = {
+	REGULATOR_SUPPLY("vdd_g3d", NULL),
+};
+
+static struct regulator_consumer_supply buck4_supply[] = {
+	REGULATOR_SUPPLY("cam_isp_core", NULL),
+};
+
+static struct regulator_consumer_supply buck7_supply[] = {
+	REGULATOR_SUPPLY("vcc_sub", NULL),
+};
+
+static struct regulator_consumer_supply safeout1_supply[] = {
+	REGULATOR_SUPPLY("safeout1", NULL),
+};
+
+static struct regulator_consumer_supply safeout2_supply[] = {
+	REGULATOR_SUPPLY("safeout2", NULL),
+};
+
+static struct regulator_consumer_supply led_flash_supply[] = {
+	REGULATOR_SUPPLY("led_flash", NULL),
+};
+
+static struct regulator_consumer_supply led_movie_supply[] = {
+	REGULATOR_SUPPLY("led_movie", NULL),
+};
+
+#if defined(CONFIG_MACH_Q1_BD)
+static struct regulator_consumer_supply led_torch_supply[] = {
+	REGULATOR_SUPPLY("led_torch", NULL),
+};
+#endif /* CONFIG_MACH_Q1_BD */
+
+#define REGULATOR_INIT(_ldo, _name, _min_uV, _max_uV, _always_on, _ops_mask, \
+		       _disabled)					\
+	static struct regulator_init_data _ldo##_init_data = {		\
+		.constraints = {					\
+			.name	= _name,				\
+			.min_uV = _min_uV,				\
+			.max_uV = _max_uV,				\
+			.always_on	= _always_on,			\
+			.boot_on	= _always_on,			\
+			.apply_uV	= 1,				\
+			.valid_ops_mask = _ops_mask,			\
+			.state_mem	= {				\
+				.disabled =				\
+					(_disabled == -1 ? 0 : _disabled),\
+				.enabled =				\
+					(_disabled == -1 ? 0 : !(_disabled)),\
+			}						\
+		},							\
+		.num_consumer_supplies = ARRAY_SIZE(_ldo##_supply),	\
+		.consumer_supplies = &_ldo##_supply[0],			\
+	};
+
+REGULATOR_INIT(ldo1, "VADC_3.3V_C210", 3300000, 3300000, 1,
+		REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo3, "VUSB_1.1V", 1100000, 1100000, 1,
+		REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo4, "VMIPI_1.8V", 1800000, 1800000, 1,
+		REGULATOR_CHANGE_STATUS, 1);
+#if defined(CONFIG_MACH_U1_KOR_LGT)
+REGULATOR_INIT(ldo5, "VHSIC_1.2V", 1200000, 1200000, 0,
+		REGULATOR_CHANGE_STATUS, 1);
+#else
+REGULATOR_INIT(ldo5, "VHSIC_1.2V", 1200000, 1200000, 1,
+		REGULATOR_CHANGE_STATUS, 1);
+#endif
+REGULATOR_INIT(ldo7, "CAM_ISP_1.8V", 1800000, 1800000, 0,
+		REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo8, "VUSB_3.3V", 3300000, 3300000, 1,
+		REGULATOR_CHANGE_STATUS, 1);
+#if defined(CONFIG_S5PV310_HI_ARMCLK_THAN_1_2GHZ)
+REGULATOR_INIT(ldo10, "VPLL_1.2V", 1200000, 1200000, 1,
+		REGULATOR_CHANGE_STATUS, 1);
+#else
+REGULATOR_INIT(ldo10, "VPLL_1.1V", 1100000, 1100000, 1,
+		REGULATOR_CHANGE_STATUS, 1);
+#endif
+#if defined(CONFIG_MACH_U1CAMERA_BD)
+REGULATOR_INIT(ldo11, "TOP_3.3V", 3300000, 3300000, 1,
+		REGULATOR_CHANGE_STATUS, 1);
+#else
+REGULATOR_INIT(ldo11, "TOUCH_2.8V", 2800000, 2800000, 0,
+		REGULATOR_CHANGE_STATUS, 1);
+#endif
+#if defined(CONFIG_MACH_U1CAMERA_BD)
+REGULATOR_INIT(ldo12, "VLCD_1.8V", 1800000, 1800000, 1,
+		REGULATOR_CHANGE_STATUS, 1);
+#else
+REGULATOR_INIT(ldo12, "VT_CAM_1.8V", 1800000, 1800000, 0,
+		REGULATOR_CHANGE_STATUS, 1);
+#endif
+REGULATOR_INIT(ldo13, "VCC_3.0V_LCD", 3000000, 3000000, 1,
+		REGULATOR_CHANGE_STATUS, 1);
+#if defined(CONFIG_MACH_Q1_BD)
+REGULATOR_INIT(ldo14, "VCC_2.2V_LCD", 2200000, 2200000, 1,
+		REGULATOR_CHANGE_STATUS, 1);
+#elif defined(CONFIG_MACH_U1CAMERA_BD)
+REGULATOR_INIT(ldo14, "MOT_3.3V", 3300000, 3300000, 1,
+		REGULATOR_CHANGE_STATUS, 1);
+#else
+REGULATOR_INIT(ldo14, "VCC_2.8V_MOTOR", 2800000, 2800000, 0,
+		REGULATOR_CHANGE_STATUS, 1);
+#endif
+#if defined(CONFIG_MACH_U1CAMERA_BD)
+REGULATOR_INIT(ldo15, "OIS_1.5V", 1500000, 1500000, 0,
+		REGULATOR_CHANGE_STATUS, 1);
+#else
+REGULATOR_INIT(ldo15, "LED_A_2.8V", 2800000, 2800000, 0,
+		REGULATOR_CHANGE_STATUS, -1);
+#endif
+#if defined(CONFIG_MACH_U1CAMERA_BD)
+REGULATOR_INIT(ldo16, "CIS_1.8V", 1800000, 1800000, 0,
+		REGULATOR_CHANGE_STATUS, 1);
+#else
+REGULATOR_INIT(ldo16, "CAM_SENSOR_IO_1.8V", 1800000, 1800000, 0,
+		REGULATOR_CHANGE_STATUS, 1);
+#endif
+REGULATOR_INIT(ldo17, "VTF_2.8V", 2800000, 2800000, 0,
+		REGULATOR_CHANGE_STATUS, 1);
+#if defined(CONFIG_MACH_U1CAMERA_BD)
+REGULATOR_INIT(ldo18, "CIS_2.8V", 2800000, 2800000, 0,
+		REGULATOR_CHANGE_STATUS, 1);
+#else
+REGULATOR_INIT(ldo18, "TOUCH_LED_3.3V", 3000000, 3300000, 0,
+		REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE, 1);
+#endif
+REGULATOR_INIT(ldo21, "VDDQ_M1M2_1.2V", 1200000, 1200000, 1,
+		REGULATOR_CHANGE_STATUS, 1);
+
+
+static struct regulator_init_data buck1_init_data = {
+	.constraints	= {
+		.name		= "vdd_arm range",
+		.min_uV		= 650000,
+		.max_uV		= 2225000,
+		.always_on	= 1,
+		.boot_on	= 1,
+		.apply_uV	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE |
+				  REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.mode		= REGULATOR_MODE_NORMAL,
+			.disabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &buck1_supply[0],
+};
+
+static struct regulator_init_data buck2_init_data = {
+	.constraints	= {
+		.name		= "vdd_int range",
+		.min_uV		= 650000,
+		.max_uV		= 2225000,
+		.always_on	= 1,
+		.boot_on	= 1,
+		.apply_uV	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE |
+				  REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.mode		= REGULATOR_MODE_NORMAL,
+			.disabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &buck2_supply[0],
+};
+
+static struct regulator_init_data buck3_init_data = {
+	.constraints	= {
+		.name		= "G3D_1.1V",
+		.min_uV		= 900000,
+		.max_uV		= 1200000,
+		.always_on	= 0,
+		.boot_on	= 0,
+		.apply_uV	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE |
+				  REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.mode		= REGULATOR_MODE_NORMAL,
+			.disabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &buck3_supply[0],
+};
+
+static struct regulator_init_data buck4_init_data = {
+	.constraints	= {
+		.name		= "CAM_ISP_CORE_1.2V",
+		.min_uV		= 1200000,
+		.max_uV		= 1200000,
+		.apply_uV	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.disabled	= 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &buck4_supply[0],
+};
+
+static struct regulator_init_data buck5_init_data = {
+	.constraints	= {
+		.name		= "VMEM_1.2V",
+		.min_uV		= 1200000,
+		.max_uV		= 1200000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.state_mem	= {
+			.uV	= 1200000,
+			.mode	= REGULATOR_MODE_NORMAL,
+			.enabled = 1,
+		},
+	},
+};
+
+static struct regulator_init_data buck7_init_data = {
+	.constraints	= {
+		.name		= "VCC_SUB_2.0V",
+		.min_uV		= 2000000,
+		.max_uV		= 2000000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.enabled = 1,
+		},
+	},
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &buck7_supply[0],
+};
+
+static struct regulator_init_data safeout1_init_data = {
+	.constraints	= {
+		.name		= "safeout1 range",
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.boot_on	= 1,
+		.state_mem	= {
+			.enabled = 1,
+		},
+	},
+	.num_consumer_supplies	= ARRAY_SIZE(safeout1_supply),
+	.consumer_supplies	= safeout1_supply,
+};
+
+static struct regulator_init_data safeout2_init_data = {
+	.constraints	= {
+		.name		= "safeout2 range",
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.enabled = 1,
+		},
+	},
+	.num_consumer_supplies	= ARRAY_SIZE(safeout2_supply),
+	.consumer_supplies	= safeout2_supply,
+};
+
+static struct regulator_init_data led_flash_init_data = {
+	.constraints = {
+		.name	= "FLASH_CUR",
+		.min_uA = 23440,
+		.max_uA = 750080,
+		.valid_ops_mask	= REGULATOR_CHANGE_CURRENT |
+				  REGULATOR_CHANGE_STATUS,
+#if !defined(CONFIG_MACH_Q1_BD)
+		.state_mem	= {
+			.disabled	= 1,
+		},
+#endif
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &led_flash_supply[0],
+};
+
+static struct regulator_init_data led_movie_init_data = {
+	.constraints = {
+		.name	= "MOVIE_CUR",
+		.min_uA = 15625,
+		.max_uA = 250000,
+		.valid_ops_mask	= REGULATOR_CHANGE_CURRENT |
+				  REGULATOR_CHANGE_STATUS,
+#if !defined(CONFIG_MACH_Q1_BD)
+		.state_mem	= {
+			.disabled	= 1,
+		},
+#endif
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &led_movie_supply[0],
+};
+
+#if defined(CONFIG_MACH_Q1_BD)
+static struct regulator_init_data led_torch_init_data = {
+	.constraints = {
+		.name	= "FLASH_TORCH",
+		.min_uA = 15625,
+		.max_uA = 250000,
+		.valid_ops_mask	= REGULATOR_CHANGE_CURRENT |
+				  REGULATOR_CHANGE_STATUS,
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &led_torch_supply[0],
+};
+#endif /* CONFIG_MACH_Q1_BD */
+
+static struct max8997_regulator_data max8997_regulators[] = {
+	{ MAX8997_LDO1,	 &ldo1_init_data, NULL, },
+	{ MAX8997_LDO3,	 &ldo3_init_data, NULL, },
+	{ MAX8997_LDO4,	 &ldo4_init_data, NULL, },
+	{ MAX8997_LDO5,	 &ldo5_init_data, NULL, },
+	{ MAX8997_LDO7,	 &ldo7_init_data, NULL, },
+	{ MAX8997_LDO8,	 &ldo8_init_data, NULL, },
+	{ MAX8997_LDO10, &ldo10_init_data, NULL, },
+	{ MAX8997_LDO11, &ldo11_init_data, NULL, },
+	{ MAX8997_LDO12, &ldo12_init_data, NULL, },
+	{ MAX8997_LDO13, &ldo13_init_data, NULL, },
+	{ MAX8997_LDO14, &ldo14_init_data, NULL, },
+	{ MAX8997_LDO15, &ldo15_init_data, NULL, },
+	{ MAX8997_LDO16, &ldo16_init_data, NULL, },
+	{ MAX8997_LDO17, &ldo17_init_data, NULL, },
+	{ MAX8997_LDO18, &ldo18_init_data, NULL, },
+	{ MAX8997_LDO21, &ldo21_init_data, NULL, },
+	{ MAX8997_BUCK1, &buck1_init_data, NULL, },
+	{ MAX8997_BUCK2, &buck2_init_data, NULL, },
+	{ MAX8997_BUCK3, &buck3_init_data, NULL, },
+	{ MAX8997_BUCK4, &buck4_init_data, NULL, },
+	{ MAX8997_BUCK5, &buck5_init_data, NULL, },
+	{ MAX8997_BUCK7, &buck7_init_data, NULL, },
+	{ MAX8997_ESAFEOUT1, &safeout1_init_data, NULL, },
+	{ MAX8997_ESAFEOUT2, &safeout2_init_data, NULL, },
+	{ MAX8997_FLASH_CUR, &led_flash_init_data, NULL, },
+	{ MAX8997_MOVIE_CUR, &led_movie_init_data, NULL, },
+#if defined CONFIG_MACH_Q1_BD
+	{ MAX8997_FLASH_TORCH, &led_torch_init_data, NULL, },
+#endif /* CONFIG_MACH_Q1_BD */
+};
+
+static struct max8997_power_data max8997_power = {
+	.batt_detect = 1,
+};
+
+#if defined(CONFIG_MACH_Q1_BD)
+static void motor_init_hw(void)
+{
+	if (gpio_request(GPIO_MOTOR_EN, "MOTOR_EN") < 0)
+		pr_err("[VIB] Failed to request GPIO_MOTOR_EN\n");
+}
+
+static void motor_en(bool enable)
+{
+	gpio_direction_output(GPIO_MOTOR_EN, enable);
+}
+#endif
+
+#ifdef CONFIG_VIBETONZ
+#ifdef CONFIG_TARGET_LOCALE_NTT
+static struct max8997_motor_data max8997_motor = {
+	.max_timeout = 10000,
+	.duty = 43696,
+	.period = 44138,
+	.init_hw = NULL,
+	.motor_en = NULL,
+	.pwm_id = 1,
+};
+#elif defined(CONFIG_TARGET_LOCALE_KOR) || defined(CONFIG_TARGET_LOCALE_NA)
+static struct max8997_motor_data max8997_motor = {
+	.max_timeout = 10000,
+	.duty = 44196,
+	.period = 44643,
+	.init_hw = NULL,
+	.motor_en = NULL,
+	.pwm_id = 1,
+};
+#elif defined(CONFIG_MACH_Q1_BD)
+static struct max8997_motor_data max8997_motor = {
+	.max_timeout = 10000,
+	.duty = 37641,
+	.period = 38022,
+	.init_hw = motor_init_hw,
+	.motor_en = motor_en,
+	.pwm_id = 1,
+};
+#else
+static struct max8997_motor_data max8997_motor = {
+	.max_timeout = 10000,
+	.duty = 37641,
+	.period = 38022,
+	.init_hw = NULL,
+	.motor_en = NULL,
+	.pwm_id = 1,
+};
+#endif
+#endif
+
+#ifdef CONFIG_MACH_U1_KOR_LGT
+static int max8997_muic_set_safeout(int path)
+{
+	static int safeout2_enabled;
+	struct regulator *regulator;
+
+	pr_info("%s: path = %d\n", __func__, path);
+
+	if (path == CP_USB_MODE) {
+		regulator = regulator_get(NULL, "safeout1");
+		if (IS_ERR(regulator))
+			return -ENODEV;
+		if (regulator_is_enabled(regulator))
+			regulator_force_disable(regulator);
+		regulator_put(regulator);
+
+		regulator = regulator_get(NULL, "safeout2");
+		if (IS_ERR(regulator))
+			return -ENODEV;
+		if (!safeout2_enabled) {
+			pr_info("%s: enable safeout2\n", __func__);
+			regulator_enable(regulator);
+			safeout2_enabled = 1;
+		} else
+			pr_info("%s: safeout2 is already enabled\n",
+							__func__);
+		regulator_put(regulator);
+	} else {
+		/* AP_USB_MODE || AUDIO_MODE */
+		regulator = regulator_get(NULL, "safeout1");
+		if (IS_ERR(regulator))
+			return -ENODEV;
+		if (!regulator_is_enabled(regulator))
+			regulator_enable(regulator);
+		regulator_put(regulator);
+
+		regulator = regulator_get(NULL, "safeout2");
+		if (IS_ERR(regulator))
+			return -ENODEV;
+		if (safeout2_enabled) {
+			pr_info("%s: disable safeout2\n", __func__);
+			regulator_disable(regulator);
+			safeout2_enabled = 0;
+		} else
+			pr_info("%s: safeout2 is already disabled\n",
+							__func__);
+		regulator_put(regulator);
+	}
+
+	return 0;
+}
+#else
+static int max8997_muic_set_safeout(int path)
+{
+	struct regulator *regulator;
+
+	if (path == CP_USB_MODE) {
+		regulator = regulator_get(NULL, "safeout1");
+		if (IS_ERR(regulator))
+			return -ENODEV;
+		if (regulator_is_enabled(regulator))
+			regulator_force_disable(regulator);
+		regulator_put(regulator);
+
+		regulator = regulator_get(NULL, "safeout2");
+		if (IS_ERR(regulator))
+			return -ENODEV;
+		if (!regulator_is_enabled(regulator))
+			regulator_enable(regulator);
+		regulator_put(regulator);
+	} else {
+		/* AP_USB_MODE || AUDIO_MODE */
+		regulator = regulator_get(NULL, "safeout1");
+		if (IS_ERR(regulator))
+			return -ENODEV;
+		if (!regulator_is_enabled(regulator))
+			regulator_enable(regulator);
+		regulator_put(regulator);
+
+		regulator = regulator_get(NULL, "safeout2");
+		if (IS_ERR(regulator))
+			return -ENODEV;
+		if (regulator_is_enabled(regulator))
+			regulator_force_disable(regulator);
+		regulator_put(regulator);
+	}
+
+	return 0;
+}
+#endif
+
+static struct charging_status_callbacks {
+	void (*tsp_set_charging_cable) (int type);
+} charging_cbs;
+
+bool is_cable_attached;
+static int connected_cable_type = CABLE_TYPE_NONE;
+
+static int max8997_muic_charger_cb(int cable_type)
+{
+	struct power_supply *psy = power_supply_get_by_name("battery");
+	union power_supply_propval value;
+
+	connected_cable_type = cable_type;
+
+	if (!psy) {
+		pr_err("%s: fail to get battery ps\n", __func__);
+		return -ENODEV;
+	}
+
+	switch (cable_type) {
+	case CABLE_TYPE_NONE:
+	case CABLE_TYPE_OTG:
+	case CABLE_TYPE_JIG_UART_OFF:
+	case CABLE_TYPE_MHL:
+		value.intval = POWER_SUPPLY_TYPE_BATTERY;
+		is_cable_attached = false;
+		break;
+	case CABLE_TYPE_USB:
+	case CABLE_TYPE_JIG_USB_OFF:
+	case CABLE_TYPE_JIG_USB_ON:
+		value.intval = POWER_SUPPLY_TYPE_USB;
+		is_cable_attached = true;
+		break;
+	case CABLE_TYPE_MHL_VB:
+		value.intval = POWER_SUPPLY_TYPE_MISC;
+		is_cable_attached = true;
+		break;
+	case CABLE_TYPE_TA:
+	case CABLE_TYPE_CARDOCK:
+	case CABLE_TYPE_DESKDOCK:
+	case CABLE_TYPE_JIG_UART_OFF_VB:
+		value.intval = POWER_SUPPLY_TYPE_MAINS;
+		is_cable_attached = true;
+		break;
+	default:
+		pr_err("%s: invalid type:%d\n", __func__, cable_type);
+		return -EINVAL;
+	}
+
+	if (charging_cbs.tsp_set_charging_cable)
+		charging_cbs.tsp_set_charging_cable(value.intval);
+
+	return psy->set_property(psy, POWER_SUPPLY_PROP_ONLINE, &value);
+}
+
+#ifdef CONFIG_USB_HOST_NOTIFY
+static void usb_otg_accessory_power(int enable)
+{
+#ifdef CONFIG_SMB328_CHARGER	/* Q1_EUR_OPEN */
+	u8 on = (u8)!!enable;
+	struct power_supply *psy_sub =
+		power_supply_get_by_name("smb328-charger");
+	union power_supply_propval value;
+	int ret;
+
+	if (!psy_sub) {
+		pr_info("%s: fail to get charger ps\n", __func__);
+		return;
+	}
+
+	value.intval = on;
+	ret = psy_sub->set_property(psy_sub,
+		POWER_SUPPLY_PROP_CHARGE_TYPE, /* only for OTG */
+		&value);
+	if (ret) {
+		pr_info("%s: fail to set OTG (%d)\n",
+			__func__, ret);
+		return;
+	}
+	pr_info("%s: otg power = %d\n", __func__, on);
+#else
+	u8 on = (u8)!!enable;
+
+	gpio_request(GPIO_USB_OTG_EN, "USB_OTG_EN");
+	gpio_direction_output(GPIO_USB_OTG_EN, on);
+	gpio_free(GPIO_USB_OTG_EN);
+	pr_info("%s: otg accessory power = %d\n", __func__, on);
+#endif
+}
+
+static struct host_notifier_platform_data host_notifier_pdata = {
+	.ndev.name	= "usb_otg",
+	.booster	= usb_otg_accessory_power,
+};
+
+struct platform_device host_notifier_device = {
+	.name = "host_notifier",
+	.dev.platform_data = &host_notifier_pdata,
+};
+
+#include "u1-otg.c"
+static void max8997_muic_usb_cb(u8 usb_mode)
+{
+	struct s3c_udc *udc = platform_get_drvdata(&s3c_device_usbgadget);
+	int ret = 0;
+
+	pr_info("otg %s: usb mode=%d\n", __func__, usb_mode);
+
+#if 0
+	u32 lpcharging = __raw_readl(S5P_INFORM2);
+	if (lpcharging == 1) {
+		struct regulator *regulator;
+		pr_info("%s: lpcharging: disable USB\n", __func__);
+
+		ret = c210_change_usb_mode(udc, USB_CABLE_DETACHED);
+		if (ret < 0)
+			pr_warn("%s: fail to change mode!!!\n", __func__);
+
+		regulator = regulator_get(NULL, "safeout1");
+		if (IS_ERR(regulator)) {
+			pr_err("%s: fail to get regulator\n", __func__);
+			return;
+		}
+
+		if (regulator_is_enabled(regulator))
+			regulator_force_disable(regulator);
+		regulator_put(regulator);
+
+		return;
+	}
+#endif
+
+#ifdef CONFIG_TARGET_LOCALE_KOR
+	if (u1_switch_get_usb_lock_state()) {
+		pr_info("%s: usb locked by mdm\n", __func__);
+		return;
+	}
+#endif
+
+	if (udc) {
+		if (usb_mode == USB_OTGHOST_ATTACHED) {
+			usb_otg_accessory_power(1);
+			max8997_muic_charger_cb(CABLE_TYPE_OTG);
+		}
+
+		ret = c210_change_usb_mode(udc, usb_mode);
+		if (ret < 0)
+			pr_err("%s: fail to change mode!!!\n", __func__);
+
+		if (usb_mode == USB_OTGHOST_DETACHED)
+			usb_otg_accessory_power(0);
+	} else
+		pr_info("otg error s3c_udc is null.\n");
+}
+#endif
+
+static void max8997_muic_mhl_cb(int attached)
+{
+	pr_info("%s(%d)\n", __func__, attached);
+
+	if (attached == MAX8997_MUIC_ATTACHED) {
+#ifdef	CONFIG_SAMSUNG_MHL
+		sii9234_mhl_detection_sched();
+#endif
+	}
+}
+
+static bool max8997_muic_is_mhl_attached(void)
+{
+	int val;
+
+	gpio_request(GPIO_MHL_SEL, "MHL_SEL");
+	val = gpio_get_value(GPIO_MHL_SEL);
+	gpio_free(GPIO_MHL_SEL);
+
+	return !!val;
+}
+
+static struct switch_dev switch_dock = {
+	.name = "dock",
+};
+
+static void max8997_muic_deskdock_cb(bool attached)
+{
+	if (attached)
+		switch_set_state(&switch_dock, 1);
+	else
+		switch_set_state(&switch_dock, 0);
+}
+
+static void max8997_muic_cardock_cb(bool attached)
+{
+	if (attached)
+		switch_set_state(&switch_dock, 2);
+	else
+		switch_set_state(&switch_dock, 0);
+}
+
+static void max8997_muic_init_cb(void)
+{
+	int ret;
+
+	/* for CarDock, DeskDock */
+	ret = switch_dev_register(&switch_dock);
+	if (ret < 0)
+		pr_err("Failed to register dock switch. %d\n", ret);
+}
+
+static void max8997_muic_jig_uart_cb(int path)
+{
+	int val;
+
+	val = path == UART_PATH_AP ? GPIO_LEVEL_HIGH : GPIO_LEVEL_LOW;
+	gpio_set_value(GPIO_UART_SEL, val);
+	pr_info("%s: val:%d\n", __func__, val);
+}
+
+static int max8997_muic_host_notify_cb(int enable)
+{
+	struct host_notify_dev *ndev = &host_notifier_pdata.ndev;
+
+	if (ndev) {
+		ndev->booster = enable ? NOTIFY_POWER_ON : NOTIFY_POWER_OFF;
+		pr_info("%s: mode %d, enable %d\n", __func__,
+				ndev->mode, enable);
+		return ndev->mode;
+	} else
+		pr_info("%s: host_notify_dev is null, enable %d\n",
+				__func__, enable);
+
+	return -1;
+}
+
+static struct max8997_muic_data max8997_muic = {
+	.usb_cb = max8997_muic_usb_cb,
+	.charger_cb = max8997_muic_charger_cb,
+	.mhl_cb = max8997_muic_mhl_cb,
+	.is_mhl_attached = max8997_muic_is_mhl_attached,
+	.set_safeout = max8997_muic_set_safeout,
+	.init_cb = max8997_muic_init_cb,
+	.deskdock_cb = max8997_muic_deskdock_cb,
+	.cardock_cb = max8997_muic_cardock_cb,
+	.jig_uart_cb = max8997_muic_jig_uart_cb,
+	.host_notify_cb = max8997_muic_host_notify_cb,
+};
+
+static struct max8997_buck1_dvs_funcs *buck1_dvs_funcs;
+
+void max8997_set_arm_voltage_table(int *voltage_table, int arr_size)
+{
+	pr_info("%s\n", __func__);
+	if (buck1_dvs_funcs && buck1_dvs_funcs->set_buck1_dvs_table)
+		buck1_dvs_funcs->set_buck1_dvs_table(buck1_dvs_funcs,
+			 voltage_table, arr_size);
+}
+
+static void max8997_register_buck1dvs_funcs(struct max8997_buck1_dvs_funcs *ptr)
+{
+	buck1_dvs_funcs = ptr;
+}
+
+
+static struct max8997_platform_data exynos4_max8997_info = {
+	.num_regulators = ARRAY_SIZE(max8997_regulators),
+	.regulators	= &max8997_regulators[0],
+	.irq_base	= IRQ_BOARD_START,
+	.wakeup		= 1,
+	.buck1_gpiodvs	= false,
+	.buck1_max_vol	= 1350000,
+	.buck2_max_vol	= 1150000,
+	.buck5_max_vol	= 1200000,
+	.buck_set1 = GPIO_BUCK1_EN_A,
+	.buck_set2 = GPIO_BUCK1_EN_B,
+	.buck_set3 = GPIO_BUCK2_EN,
+	.buck_ramp_en = true,
+	.buck_ramp_delay = 10,		/* 10.00mV /us (default) */
+	.flash_cntl_val = 0x5F,	/* Flash safety timer duration: 800msec,
+					   Maximum timer mode */
+	.power = &max8997_power,
+#ifdef CONFIG_VIBETONZ
+	.motor = &max8997_motor,
+#endif
+	.muic = &max8997_muic,
+	.register_buck1_dvs_funcs = max8997_register_buck1dvs_funcs,
+};
+#endif /* CONFIG_REGULATOR_MAX8997 */
+
+/* Bluetooth */
+#ifdef CONFIG_BT_BCM4330
+static struct platform_device bcm4330_bluetooth_device = {
+	.name = "bcm4330_bluetooth",
+	.id = -1,
+};
+#endif				/* CONFIG_BT_BCM4330 */
+
+#ifdef CONFIG_TARGET_LOCALE_KOR
+#define SYSTEM_REV_SND 0x05
+#else
+#define SYSTEM_REV_SND 0x09
+#endif
+
+#ifdef CONFIG_SND_SOC_U1_MC1N2
+void sec_set_main_mic_bias(bool on)
+{
+#ifdef CONFIG_SND_SOC_USE_EXTERNAL_MIC_BIAS
+	gpio_set_value(GPIO_MIC_BIAS_EN, on);
+#endif
+}
+
+int sec_set_ldo1_constraints(int disabled)
+{
+	struct regulator *regulator;
+
+	if (!disabled) {
+		regulator = regulator_get(NULL, "vadc_3.3v");
+		if (IS_ERR(regulator))
+			return -1;
+		regulator_enable(regulator);
+		regulator_put(regulator);
+	} else {
+		regulator = regulator_get(NULL, "vadc_3.3v");
+		if (IS_ERR(regulator))
+			return -1;
+		if (regulator_is_enabled(regulator))
+			regulator_force_disable(regulator);
+		regulator_put(regulator);
+	}
+
+	return 0;
+}
+
+static struct mc1n2_platform_data mc1n2_pdata = {
+	.set_main_mic_bias = sec_set_main_mic_bias,
+	.set_adc_power_constraints = sec_set_ldo1_constraints,
+};
+
+static void u1_sound_init(void)
+{
+#ifdef CONFIG_SND_SOC_USE_EXTERNAL_MIC_BIAS
+	int err;
+
+	err = gpio_request(GPIO_MIC_BIAS_EN, "GPE1");
+	if (err) {
+		pr_err(KERN_ERR "MIC_BIAS_EN GPIO set error!\n");
+		return;
+	}
+	gpio_direction_output(GPIO_MIC_BIAS_EN, 1);
+	gpio_set_value(GPIO_MIC_BIAS_EN, 0);
+	gpio_free(GPIO_MIC_BIAS_EN);
+
+	err = gpio_request(GPIO_EAR_MIC_BIAS_EN, "GPE2");
+	if (err) {
+		pr_err(KERN_ERR "EAR_MIC_BIAS_EN GPIO set error!\n");
+		return;
+	}
+	gpio_direction_output(GPIO_EAR_MIC_BIAS_EN, 1);
+	gpio_set_value(GPIO_EAR_MIC_BIAS_EN, 0);
+	gpio_free(GPIO_EAR_MIC_BIAS_EN);
+
+#endif
+}
+#endif
+
+#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE)
+static void tdmb_set_config_poweron(void)
+{
+	s3c_gpio_cfgpin(GPIO_TDMB_EN, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TDMB_EN, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TDMB_EN, GPIO_LEVEL_LOW);
+
+	s3c_gpio_cfgpin(GPIO_TDMB_RST_N, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TDMB_RST_N, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TDMB_RST_N, GPIO_LEVEL_LOW);
+
+	s3c_gpio_cfgpin(GPIO_TDMB_INT, S3C_GPIO_SFN(GPIO_TDMB_INT_AF));
+	s3c_gpio_setpull(GPIO_TDMB_INT, S3C_GPIO_PULL_NONE);
+}
+static void tdmb_set_config_poweroff(void)
+{
+	s3c_gpio_cfgpin(GPIO_TDMB_EN, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TDMB_EN, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TDMB_EN, GPIO_LEVEL_LOW);
+
+	s3c_gpio_cfgpin(GPIO_TDMB_RST_N, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TDMB_RST_N, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TDMB_RST_N, GPIO_LEVEL_LOW);
+
+	s3c_gpio_cfgpin(GPIO_TDMB_INT, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TDMB_INT, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TDMB_INT, GPIO_LEVEL_LOW);
+}
+
+static void tdmb_gpio_on(void)
+{
+	printk(KERN_DEBUG "tdmb_gpio_on\n");
+
+	tdmb_set_config_poweron();
+
+	gpio_set_value(GPIO_TDMB_EN, GPIO_LEVEL_HIGH);
+	usleep_range(10000, 10000);
+	gpio_set_value(GPIO_TDMB_RST_N, GPIO_LEVEL_LOW);
+	usleep_range(2000, 2000);
+	gpio_set_value(GPIO_TDMB_RST_N, GPIO_LEVEL_HIGH);
+	usleep_range(10000, 10000);
+}
+
+static void tdmb_gpio_off(void)
+{
+	printk(KERN_DEBUG "tdmb_gpio_off\n");
+
+	tdmb_set_config_poweroff();
+
+	gpio_set_value(GPIO_TDMB_RST_N, GPIO_LEVEL_LOW);
+	usleep_range(1000, 1000);
+	gpio_set_value(GPIO_TDMB_EN, GPIO_LEVEL_LOW);
+
+}
+
+static struct tdmb_platform_data tdmb_pdata = {
+	.gpio_on = tdmb_gpio_on,
+	.gpio_off = tdmb_gpio_off,
+};
+
+static struct platform_device tdmb_device = {
+	.name			= "tdmb",
+	.id				= -1,
+	.dev			= {
+		.platform_data = &tdmb_pdata,
+	},
+};
+
+static int __init tdmb_dev_init(void)
+{
+	tdmb_set_config_poweroff();
+	s5p_register_gpio_interrupt(GPIO_TDMB_INT);
+	tdmb_pdata.irq = GPIO_TDMB_IRQ;
+	platform_device_register(&tdmb_device);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_BATTERY_SEC_U1
+static int c1_charger_topoff_cb(void)
+{
+	struct power_supply *psy = power_supply_get_by_name("battery");
+	union power_supply_propval value;
+
+	if (!psy) {
+		pr_err("%s: fail to get battery ps\n", __func__);
+		return -ENODEV;
+	}
+
+	value.intval = POWER_SUPPLY_STATUS_FULL;
+	return psy->set_property(psy, POWER_SUPPLY_PROP_STATUS, &value);
+}
+#endif
+
+#if defined(CONFIG_MACH_Q1_CHN) && \
+	(defined(CONFIG_SMB136_CHARGER_Q1) || defined(CONFIG_SMB328_CHARGER))
+static int c1_charger_ovp_cb(bool is_ovp)
+{
+	struct power_supply *psy = power_supply_get_by_name("battery");
+	union power_supply_propval value;
+
+	if (!psy) {
+		pr_err("%s: fail to get battery ps\n", __func__);
+		return -ENODEV;
+	}
+
+	if (is_ovp)
+		value.intval = POWER_SUPPLY_HEALTH_OVERVOLTAGE;
+	else
+		value.intval = POWER_SUPPLY_HEALTH_GOOD;
+
+	return psy->set_property(psy, POWER_SUPPLY_PROP_VOLTAGE_MAX, &value);
+}
+#endif
+
+#ifdef CONFIG_LEDS_MAX8997
+struct led_max8997_platform_data led_max8997_platform_data = {
+	.name = "leds-sec",
+	.brightness = 0,
+};
+
+struct platform_device sec_device_leds_max8997 = {
+	.name   = "leds-max8997",
+	.id     = -1,
+	.dev = { .platform_data = &led_max8997_platform_data},
+};
+#endif /* CONFIG_LEDS_MAX8997 */
+
+#ifdef CONFIG_CHARGER_MAX8922_U1
+static int max8922_cfg_gpio(void)
+{
+	if (system_rev < HWREV_FOR_BATTERY)
+		return -ENODEV;
+
+	s3c_gpio_cfgpin(GPIO_CHG_EN, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_CHG_EN, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_CHG_EN, GPIO_LEVEL_LOW);
+
+	s3c_gpio_cfgpin(GPIO_CHG_ING_N, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_CHG_ING_N, S3C_GPIO_PULL_NONE);
+
+	s3c_gpio_cfgpin(GPIO_TA_nCONNECTED, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_TA_nCONNECTED, S3C_GPIO_PULL_NONE);
+
+	return 0;
+}
+
+static struct max8922_platform_data max8922_pdata = {
+#ifdef CONFIG_BATTERY_SEC_U1
+	.topoff_cb = c1_charger_topoff_cb,
+#endif
+	.cfg_gpio = max8922_cfg_gpio,
+	.gpio_chg_en = GPIO_CHG_EN,
+	.gpio_chg_ing = GPIO_CHG_ING_N,
+	.gpio_ta_nconnected = GPIO_TA_nCONNECTED,
+};
+
+static struct platform_device max8922_device_charger = {
+	.name = "max8922-charger",
+	.id = -1,
+	.dev.platform_data = &max8922_pdata,
+};
+#endif /* CONFIG_CHARGER_MAX8922_U1 */
+
+#ifdef CONFIG_BATTERY_SAMSUNG
+static struct platform_device samsung_device_battery = {
+	.name = "samsung-fake-battery",
+	.id = -1,
+};
+#endif
+
+#ifdef CONFIG_BATTERY_SEC_U1
+
+#ifdef CONFIG_TARGET_LOCALE_KOR
+/* temperature table for ADC 6 */
+static struct sec_bat_adc_table_data temper_table[] =  {
+	{  264,	 500 },
+	{  275,	 490 },
+	{  286,	 480 },
+	{  293,	 480 },
+	{  299,	 470 },
+	{  306,	 460 },
+	{  324,	 450 },
+	{  341,	 450 },
+	{  354,	 440 },
+	{  368,	 430 },
+	{  381,	 420 },
+	{  396,	 420 },
+	{  411,	 410 },
+	{  427,	 400 },
+	{  442,	 390 },
+	{  457,	 390 },
+	{  472,	 380 },
+	{  487,	 370 },
+	{  503,	 370 },
+	{  518,	 360 },
+	{  533,	 350 },
+	{  554,	 340 },
+	{  574,	 330 },
+	{  595,	 330 },
+	{  615,	 320 },
+	{  636,	 310 },
+	{  656,	 310 },
+	{  677,	 300 },
+	{  697,	 290 },
+	{  718,	 280 },
+	{  738,	 270 },
+	{  761,	 270 },
+	{  784,	 260 },
+	{  806,	 250 },
+	{  829,	 240 },
+	{  852,	 230 },
+	{  875,	 220 },
+	{  898,	 210 },
+	{  920,	 200 },
+	{  943,	 190 },
+	{  966,	 180 },
+	{  990,	 170 },
+	{ 1013,	 160 },
+	{ 1037,	 150 },
+	{ 1060,	 140 },
+	{ 1084,	 130 },
+	{ 1108,	 120 },
+	{ 1131,	 110 },
+	{ 1155,	 100 },
+	{ 1178,	  90 },
+	{ 1202,	  80 },
+	{ 1226,	  70 },
+	{ 1251,	  60 },
+	{ 1275,	  50 },
+	{ 1299,	  40 },
+	{ 1324,	  30 },
+	{ 1348,	  20 },
+	{ 1372,	  10 },
+	{ 1396,	   0 },
+	{ 1421,	 -10 },
+	{ 1445,	 -20 },
+	{ 1468,	 -30 },
+	{ 1491,	 -40 },
+	{ 1513,	 -50 },
+	{ 1536,	 -60 },
+	{ 1559,	 -70 },
+	{ 1577,	 -80 },
+	{ 1596,	 -90 },
+	{ 1614,	 -100 },
+	{ 1619,	 -110 },
+	{ 1632,	 -120 },
+	{ 1658,	 -130 },
+	{ 1667,	 -140 },
+};
+#elif defined(CONFIG_TARGET_LOCALE_NTT)
+/* temperature table for ADC 6 */
+static struct sec_bat_adc_table_data temper_table[] =  {
+	{  273,	 670 },
+	{  289,	 660 },
+	{  304,	 650 },
+	{  314,	 640 },
+	{  325,	 630 },
+	{  337,	 620 },
+	{  347,	 610 },
+	{  361,	 600 },
+	{  376,	 590 },
+	{  391,	 580 },
+	{  406,	 570 },
+	{  417,	 560 },
+	{  431,	 550 },
+	{  447,	 540 },
+	{  474,	 530 },
+	{  491,	 520 },
+	{  499,	 510 },
+	{  511,	 500 },
+	{  519,	 490 },
+	{  547,	 480 },
+	{  568,	 470 },
+	{  585,	 460 },
+	{  597,	 450 },
+	{  614,	 440 },
+	{  629,	 430 },
+	{  647,	 420 },
+	{  672,	 410 },
+	{  690,	 400 },
+	{  720,	 390 },
+	{  735,	 380 },
+	{  755,	 370 },
+	{  775,	 360 },
+	{  795,	 350 },
+	{  818,	 340 },
+	{  841,	 330 },
+	{  864,	 320 },
+	{  887,	 310 },
+	{  909,	 300 },
+	{  932,	 290 },
+	{  954,	 280 },
+	{  976,	 270 },
+	{  999,	 260 },
+	{ 1021,	 250 },
+	{ 1051,	 240 },
+	{ 1077,	 230 },
+	{ 1103,	 220 },
+	{ 1129,	 210 },
+	{ 1155,	 200 },
+	{ 1177,	 190 },
+	{ 1199,	 180 },
+	{ 1220,	 170 },
+	{ 1242,	 160 },
+	{ 1263,	 150 },
+	{ 1284,	 140 },
+	{ 1306,	 130 },
+	{ 1326,	 120 },
+	{ 1349,	 110 },
+	{ 1369,	 100 },
+	{ 1390,	  90 },
+	{ 1411,	  80 },
+	{ 1433,	  70 },
+	{ 1454,	  60 },
+	{ 1474,	  50 },
+	{ 1486,	  40 },
+	{ 1499,	  30 },
+	{ 1512,	  20 },
+	{ 1531,	  10 },
+	{ 1548,	   0 },
+	{ 1570,	 -10 },
+	{ 1597,	 -20 },
+	{ 1624,	 -30 },
+	{ 1633,	 -40 },
+	{ 1643,	 -50 },
+	{ 1652,	 -60 },
+	{ 1663,	 -70 },
+};
+#else
+/* temperature table for ADC 6 */
+static struct sec_bat_adc_table_data temper_table[] = {
+	{  165,	 800 },
+	{  171,	 790 },
+	{  177,	 780 },
+	{  183,	 770 },
+	{  189,	 760 },
+	{  196,	 750 },
+	{  202,	 740 },
+	{  208,	 730 },
+	{  214,	 720 },
+	{  220,	 710 },
+	{  227,	 700 },
+	{  237,	 690 },
+	{  247,	 680 },
+	{  258,	 670 },
+	{  269,	 660 },
+	{  281,	 650 },
+	{  296,	 640 },
+	{  311,	 630 },
+	{  326,	 620 },
+	{  341,	 610 },
+	{  356,	 600 },
+	{  370,	 590 },
+	{  384,	 580 },
+	{  398,	 570 },
+	{  412,	 560 },
+	{  427,	 550 },
+	{  443,	 540 },
+	{  457,	 530 },
+	{  471,	 520 },
+	{  485,	 510 },
+	{  498,	 500 },
+	{  507,	 490 },
+	{  516,	 480 },
+	{  525,	 470 },
+	{  535,	 460 },
+	{  544,	 450 },
+	{  553,	 440 },
+	{  562,	 430 },
+	{  579,	 420 },
+	{  596,	 410 },
+	{  613,	 400 },
+	{  630,	 390 },
+	{  648,	 380 },
+	{  665,	 370 },
+	{  684,	 360 },
+	{  702,	 350 },
+	{  726,	 340 },
+	{  750,	 330 },
+	{  774,	 320 },
+	{  798,	 310 },
+	{  821,	 300 },
+	{  844,	 290 },
+	{  867,	 280 },
+	{  891,	 270 },
+	{  914,	 260 },
+	{  937,	 250 },
+	{  960,	 240 },
+	{  983,	 230 },
+	{ 1007,	 220 },
+	{ 1030,	 210 },
+	{ 1054,	 200 },
+	{ 1083,	 190 },
+	{ 1113,	 180 },
+	{ 1143,	 170 },
+	{ 1173,	 160 },
+	{ 1202,	 150 },
+	{ 1232,	 140 },
+	{ 1262,	 130 },
+	{ 1291,	 120 },
+	{ 1321,	 110 },
+	{ 1351,	 100 },
+	{ 1357,	  90 },
+	{ 1363,	  80 },
+	{ 1369,	  70 },
+	{ 1375,	  60 },
+	{ 1382,	  50 },
+	{ 1402,	  40 },
+	{ 1422,	  30 },
+	{ 1442,	  20 },
+	{ 1462,	  10 },
+	{ 1482,	   0 },
+	{ 1519,	 -10 },
+	{ 1528,	 -20 },
+	{ 1546,	 -30 },
+	{ 1563,	 -40 },
+	{ 1587,	 -50 },
+	{ 1601,	 -60 },
+	{ 1614,	 -70 },
+	{ 1625,  -80 },
+	{ 1641,  -90 },
+	{ 1663, -100 },
+	{ 1678, -110 },
+	{ 1693, -120 },
+	{ 1705, -130 },
+	{ 1720, -140 },
+	{ 1736, -150 },
+	{ 1751, -160 },
+	{ 1767, -170 },
+	{ 1782, -180 },
+	{ 1798, -190 },
+	{ 1815, -200 },
+};
+#endif
+#ifdef CONFIG_TARGET_LOCALE_NTT
+/* temperature table for ADC 7 */
+static struct sec_bat_adc_table_data temper_table_ADC7[] =  {
+	{  300,	 670 },
+	{  310,	 660 },
+	{  324,	 650 },
+	{  330,	 640 },
+	{  340,	 630 },
+	{  353,	 620 },
+	{  368,	 610 },
+	{  394,	 600 },
+	{  394,	 590 },
+	{  401,	 580 },
+	{  418,	 570 },
+	{  431,	 560 },
+	{  445,	 550 },
+	{  460,	 540 },
+	{  478,	 530 },
+	{  496,	 520 },
+	{  507,	 510 },
+	{  513,	 500 },
+	{  531,	 490 },
+	{  553,	 480 },
+	{  571,	 470 },
+	{  586,	 460 },
+	{  604,	 450 },
+	{  614,	 440 },
+	{  640,	 430 },
+	{  659,	 420 },
+	{  669,	 410 },
+	{  707,	 400 },
+	{  722,	 390 },
+	{  740,	 380 },
+	{  769,	 370 },
+	{  783,	 360 },
+	{  816,	 350 },
+	{  818,	 340 },
+	{  845,	 330 },
+	{  859,	 320 },
+	{  889,	 310 },
+	{  929,	 300 },
+	{  942,	 290 },
+	{  955,	 280 },
+	{  972,	 270 },
+	{  996,	 260 },
+	{ 1040,	 250 },
+	{ 1049,	 240 },
+	{ 1073,	 230 },
+	{ 1096,	 220 },
+	{ 1114,	 210 },
+	{ 1159,	 200 },
+	{ 1165,	 190 },
+	{ 1206,	 180 },
+	{ 1214,	 170 },
+	{ 1227,	 160 },
+	{ 1256,	 150 },
+	{ 1275,	 140 },
+	{ 1301,	 130 },
+	{ 1308,	 120 },
+	{ 1357,	 110 },
+	{ 1388,	 100 },
+	{ 1396,	  90 },
+	{ 1430,	  80 },
+	{ 1448,	  70 },
+	{ 1468,	  60 },
+	{ 1499,	  50 },
+	{ 1506,	  40 },
+	{ 1522,	  30 },
+	{ 1535,	  20 },
+	{ 1561,	  10 },
+	{ 1567,	   0 },
+	{ 1595,	 -10 },
+	{ 1620,	 -20 },
+	{ 1637,	 -30 },
+	{ 1640,	 -40 },
+	{ 1668,	 -50 },
+	{ 1669,	 -60 },
+	{ 1688,	 -70 },
+};
+#else
+/* temperature table for ADC 7 */
+static struct sec_bat_adc_table_data temper_table_ADC7[] = {
+	{  193,	 800 },
+	{  200,	 790 },
+	{  207,	 780 },
+	{  215,	 770 },
+	{  223,	 760 },
+	{  230,	 750 },
+	{  238,	 740 },
+	{  245,	 730 },
+	{  252,	 720 },
+	{  259,	 710 },
+	{  266,	 700 },
+	{  277,	 690 },
+	{  288,	 680 },
+	{  300,	 670 },
+	{  311,	 660 },
+	{  326,	 650 },
+	{  340,	 640 },
+	{  354,	 630 },
+	{  368,	 620 },
+	{  382,	 610 },
+	{  397,	 600 },
+	{  410,	 590 },
+	{  423,	 580 },
+	{  436,	 570 },
+	{  449,	 560 },
+	{  462,	 550 },
+	{  475,	 540 },
+	{  488,	 530 },
+	{  491,	 520 },
+	{  503,	 510 },
+	{  535,	 500 },
+	{  548,	 490 },
+	{  562,	 480 },
+	{  576,	 470 },
+	{  590,	 460 },
+	{  603,	 450 },
+	{  616,	 440 },
+	{  630,	 430 },
+	{  646,	 420 },
+	{  663,	 410 },
+	{  679,	 400 },
+	{  696,	 390 },
+	{  712,	 380 },
+	{  728,	 370 },
+	{  745,	 360 },
+	{  762,	 350 },
+	{  784,	 340 },
+	{  806,	 330 },
+	{  828,	 320 },
+	{  850,	 310 },
+	{  872,	 300 },
+	{  895,	 290 },
+	{  919,	 280 },
+	{  942,	 270 },
+	{  966,	 260 },
+	{  989,	 250 },
+	{ 1013,	 240 },
+	{ 1036,	 230 },
+	{ 1060,	 220 },
+	{ 1083,	 210 },
+	{ 1107,	 200 },
+	{ 1133,	 190 },
+	{ 1159,	 180 },
+	{ 1186,	 170 },
+	{ 1212,	 160 },
+	{ 1238,	 150 },
+	{ 1265,	 140 },
+	{ 1291,	 130 },
+	{ 1316,	 120 },
+	{ 1343,	 110 },
+	{ 1370,	 100 },
+	{ 1381,	  90 },
+	{ 1393,	  80 },
+	{ 1404,	  70 },
+	{ 1416,	  60 },
+	{ 1427,	  50 },
+	{ 1453,	  40 },
+	{ 1479,	  30 },
+	{ 1505,	  20 },
+	{ 1531,	  10 },
+	{ 1557,	   0 },
+	{ 1565,	 -10 },
+	{ 1577,	 -20 },
+	{ 1601,	 -30 },
+	{ 1620,	 -40 },
+	{ 1633,	 -50 },
+	{ 1642,	 -60 },
+	{ 1656,	 -70 },
+	{ 1667,  -80 },
+	{ 1674,  -90 },
+	{ 1689, -100 },
+	{ 1704, -110 },
+	{ 1719, -120 },
+	{ 1734, -130 },
+	{ 1749, -140 },
+	{ 1763, -150 },
+	{ 1778, -160 },
+	{ 1793, -170 },
+	{ 1818, -180 },
+	{ 1823, -190 },
+	{ 1838, -200 },
+};
+#endif
+
+#define ADC_CH_TEMPERATURE_PMIC	6
+#define ADC_CH_TEMPERATURE_LCD	7
+
+static unsigned int sec_bat_get_lpcharging_state(void)
+{
+	u32 val = __raw_readl(S5P_INFORM2);
+	struct power_supply *psy = power_supply_get_by_name("max8997-charger");
+	union power_supply_propval value;
+
+	BUG_ON(!psy);
+
+	if (val == 1) {
+		psy->get_property(psy, POWER_SUPPLY_PROP_STATUS, &value);
+		pr_info("%s: charging status: %d\n", __func__, value.intval);
+		if (value.intval == POWER_SUPPLY_STATUS_DISCHARGING)
+			pr_warn("%s: DISCHARGING\n", __func__);
+	}
+
+	pr_info("%s: LP charging:%d\n", __func__, val);
+	return val;
+}
+
+static void sec_bat_initial_check(void)
+{
+	pr_info("%s: connected_cable_type:%d\n",
+		__func__, connected_cable_type);
+	if (connected_cable_type != CABLE_TYPE_NONE)
+		max8997_muic_charger_cb(connected_cable_type);
+}
+
+static struct sec_bat_platform_data sec_bat_pdata = {
+	.fuel_gauge_name	= "fuelgauge",
+	.charger_name		= "max8997-charger",
+#ifdef CONFIG_CHARGER_MAX8922_U1
+	.sub_charger_name	= "max8922-charger",
+#elif defined(CONFIG_MAX8903_CHARGER)
+	.sub_charger_name	= "max8903-charger",
+#endif
+	/* TODO: should provide temperature table */
+	.adc_arr_size		= ARRAY_SIZE(temper_table),
+	.adc_table			= temper_table,
+	.adc_channel		= ADC_CH_TEMPERATURE_PMIC,
+	.adc_sub_arr_size	= ARRAY_SIZE(temper_table_ADC7),
+	.adc_sub_table		= temper_table_ADC7,
+	.adc_sub_channel	= ADC_CH_TEMPERATURE_LCD,
+	.get_lpcharging_state	= sec_bat_get_lpcharging_state,
+#if defined(CONFIG_MACH_Q1_BD)
+	.initial_check		= sec_bat_initial_check,
+#else
+	.initial_check		= NULL,
+#endif
+};
+
+static struct platform_device sec_device_battery = {
+	.name = "sec-battery",
+	.id = -1,
+	.dev.platform_data = &sec_bat_pdata,
+};
+#endif /* CONFIG_BATTERY_SEC_U1 */
+
+#ifdef CONFIG_SMB136_CHARGER_Q1
+static void smb136_set_charger_name(void)
+{
+	sec_bat_pdata.sub_charger_name = "smb136-charger";
+}
+
+static struct smb136_platform_data smb136_pdata = {
+	.topoff_cb = c1_charger_topoff_cb,
+#if defined(CONFIG_MACH_Q1_CHN) && defined(CONFIG_SMB136_CHARGER_Q1)
+	.ovp_cb = c1_charger_ovp_cb,
+#endif
+	.set_charger_name = smb136_set_charger_name,
+	.gpio_chg_en = GPIO_CHG_EN,
+	.gpio_otg_en = GPIO_OTG_EN,
+#if defined(CONFIG_MACH_Q1_CHN) && defined(CONFIG_SMB136_CHARGER_Q1)
+	.gpio_chg_ing = GPIO_CHG_ING_N,
+#endif
+	.gpio_ta_nconnected = 0,	/*GPIO_TA_nCONNECTED,*/
+};
+#endif /* CONFIG_SMB136_CHARGER_Q1 */
+
+#ifdef CONFIG_SMB328_CHARGER
+static void smb328_set_charger_name(void)
+{
+	sec_bat_pdata.sub_charger_name = "smb328-charger";
+}
+
+static struct smb328_platform_data smb328_pdata = {
+	.topoff_cb = c1_charger_topoff_cb,
+#if defined(CONFIG_MACH_Q1_CHN) && defined(CONFIG_SMB328_CHARGER)
+	.ovp_cb = c1_charger_ovp_cb,
+#endif
+	.set_charger_name = smb328_set_charger_name,
+	.gpio_chg_ing = GPIO_CHG_ING_N,
+	.gpio_ta_nconnected = 0,	/*GPIO_TA_nCONNECTED,*/
+};
+#endif /* CONFIG_SMB328_CHARGER */
+
+#if defined(CONFIG_SMB136_CHARGER_Q1) || defined(CONFIG_SMB328_CHARGER)
+static struct i2c_gpio_platform_data gpio_i2c_data19 = {
+	.sda_pin = GPIO_CHG_SDA,
+	.scl_pin = GPIO_CHG_SCL,
+};
+
+static struct platform_device s3c_device_i2c19 = {
+	.name = "i2c-gpio",
+	.id = 19,
+	.dev.platform_data = &gpio_i2c_data19,
+};
+
+static struct i2c_board_info i2c_devs19_emul[] = {
+#ifdef CONFIG_SMB136_CHARGER_Q1
+	{
+		I2C_BOARD_INFO("smb136-charger", SMB136_SLAVE_ADDR>>1),
+		.platform_data	= &smb136_pdata,
+	},
+#endif
+#ifdef CONFIG_SMB328_CHARGER
+	{
+		I2C_BOARD_INFO("smb328-charger", SMB328_SLAVE_ADDR>>1),
+		.platform_data	= &smb328_pdata,
+	},
+#endif
+};
+#endif
+
+#if defined(CONFIG_SEC_THERMISTOR)
+/* temperature table for ADC CH 6 */
+static struct sec_therm_adc_table adc_ch6_table[] = {
+	/* ADC, Temperature */
+	{  173,  800 },
+	{  180,  790 },
+	{  188,  780 },
+	{  196,  770 },
+	{  204,  760 },
+	{  212,  750 },
+	{  220,  740 },
+	{  228,  730 },
+	{  236,  720 },
+	{  244,  710 },
+	{  252,  700 },
+	{  259,  690 },
+	{  266,  680 },
+	{  273,  670 },
+	{  289,  660 },
+	{  304,  650 },
+	{  314,  640 },
+	{  325,  630 },
+	{  337,  620 },
+	{  347,  610 },
+	{  361,  600 },
+	{  376,  590 },
+	{  391,  580 },
+	{  406,  570 },
+	{  417,  560 },
+	{  431,  550 },
+	{  447,  540 },
+	{  474,  530 },
+	{  491,  520 },
+	{  499,  510 },
+	{  511,  500 },
+	{  519,  490 },
+	{  547,  480 },
+	{  568,  470 },
+	{  585,  460 },
+	{  597,  450 },
+	{  614,  440 },
+	{  629,  430 },
+	{  647,  420 },
+	{  672,  410 },
+	{  690,  400 },
+	{  720,  390 },
+	{  735,  380 },
+	{  755,  370 },
+	{  775,  360 },
+	{  795,  350 },
+	{  818,  340 },
+	{  841,  330 },
+	{  864,  320 },
+	{  887,  310 },
+	{  909,  300 },
+	{  932,  290 },
+	{  954,  280 },
+	{  976,  270 },
+	{  999,  260 },
+	{ 1021,  250 },
+	{ 1051,  240 },
+	{ 1077,  230 },
+	{ 1103,  220 },
+	{ 1129,  210 },
+	{ 1155,  200 },
+	{ 1177,  190 },
+	{ 1199,  180 },
+	{ 1220,  170 },
+	{ 1242,  160 },
+	{ 1263,  150 },
+	{ 1284,  140 },
+	{ 1306,  130 },
+	{ 1326,  120 },
+	{ 1349,  110 },
+	{ 1369,  100 },
+	{ 1390,   90 },
+	{ 1411,   80 },
+	{ 1433,   70 },
+	{ 1454,   60 },
+	{ 1474,   50 },
+	{ 1486,   40 },
+	{ 1499,   30 },
+	{ 1512,   20 },
+	{ 1531,   10 },
+	{ 1548,    0 },
+	{ 1570,  -10 },
+	{ 1597,  -20 },
+	{ 1624,  -30 },
+	{ 1633,  -40 },
+	{ 1643,  -50 },
+	{ 1652,  -60 },
+	{ 1663,  -70 },
+	{ 1687,  -80 },
+	{ 1711,  -90 },
+	{ 1735,  -100 },
+	{ 1746,  -110 },
+	{ 1757,  -120 },
+	{ 1768,  -130 },
+	{ 1779,  -140 },
+	{ 1790,  -150 },
+	{ 1801,  -160 },
+	{ 1812,  -170 },
+	{ 1823,  -180 },
+	{ 1834,  -190 },
+	{ 1845,  -200 },
+};
+
+static struct sec_therm_platform_data sec_therm_pdata = {
+	.adc_channel	= 6,
+	.adc_arr_size	= ARRAY_SIZE(adc_ch6_table),
+	.adc_table	= adc_ch6_table,
+	.polling_interval = 30 * 1000, /* msecs */
+};
+
+static struct platform_device sec_device_thermistor = {
+	.name = "sec-thermistor",
+	.id = -1,
+	.dev.platform_data = &sec_therm_pdata,
+};
+#endif /* CONFIG_SEC_THERMISTOR */
+
+
+struct gpio_keys_button u1_buttons[] = {
+#if defined(CONFIG_MACH_U1CAMERA_BD)
+	{
+		.code = KEY_POWER,
+		.gpio = GPIO_nPOWER,
+		.active_low = 1,
+		.type = EV_KEY,
+		.wakeup = 1,
+		.isr_hook = sec_debug_check_crash_key,
+	},
+	{
+		.code = KEY_RESERVED,
+		.gpio = GPIO_RSERVED_KEY,
+		.active_low = 1,
+		.type = EV_KEY,
+		.wakeup = 1,
+	},
+	{
+		.code = KEY_PLAY,
+		.gpio = GPIO_PLAY_KEY,
+		.active_low = 1,
+		.type = EV_KEY,
+		.wakeup = 1,
+	},
+	{
+		.code = KEY_RECORD,
+		.gpio = GPIO_RECORD_KEY,
+		.active_low = 1,
+		.type = EV_KEY,
+		.wakeup = 1,
+	},
+	{
+		.code = KEY_MENU,
+		.gpio = GPIO_MENU_KEY,
+		.active_low = 1,
+		.type = EV_KEY,
+		.wakeup = 1,
+	},
+	{
+		.code = KEY_HOME,
+		.gpio = GPIO_HOME_KEY,
+		.active_low = 1,
+		.type = EV_KEY,
+		.wakeup = 1,
+	},
+	{
+		.code = KEY_BACK,
+		.gpio = GPIO_BACK_KEY,
+		.active_low = 1,
+		.type = EV_KEY,
+		.wakeup = 1,
+	},
+	{
+		.code = KEY_CAMERA_FOCUS,
+		.gpio = GPIO_S1_KEY,
+		.active_low = 1,
+		.type = EV_KEY,
+		.wakeup = 1,
+	},
+	{
+		/*KEY_CAMERA_SHUTTER*/
+		.code = 0x220,
+		.gpio = GPIO_S2_KEY,
+		.active_low = 1,
+		.type = EV_KEY,
+		.wakeup = 1,
+	},
+	{
+		.code = KEY_CAMERA_ZOOMIN,
+		.gpio = GPIO_TELE_KEY,
+		.active_low = 1,
+		.type = EV_KEY,
+		.wakeup = 1,
+	},
+	{
+		.code = KEY_CAMERA_ZOOMOUT,
+		.gpio = GPIO_WIDE_KEY,
+		.active_low = 1,
+		.type = EV_KEY,
+		.wakeup = 1,
+	},
+#else
+	{
+		.code = KEY_VOLUMEUP,
+		.gpio = GPIO_VOL_UP,
+		.active_low = 1,
+		.type = EV_KEY,
+		.wakeup = 1,
+		.isr_hook = sec_debug_check_crash_key,
+	},			/* vol up */
+	{
+		.code = KEY_VOLUMEDOWN,
+		.gpio = GPIO_VOL_DOWN,
+		.active_low = 1,
+		.type = EV_KEY,
+		.wakeup = 1,
+		.isr_hook = sec_debug_check_crash_key,
+	},			/* vol down */
+	{
+		.code = KEY_POWER,
+		.gpio = GPIO_nPOWER,
+		.active_low = 1,
+		.type = EV_KEY,
+		.wakeup = 1,
+		.isr_hook = sec_debug_check_crash_key,
+	},			/* power key */
+	{
+		.code = KEY_HOME,
+		.gpio = GPIO_OK_KEY,
+		.active_low = 1,
+		.type = EV_KEY,
+		.wakeup = 1,
+	},			/* ok key */
+#endif
+};
+
+struct gpio_keys_platform_data u1_keypad_platform_data = {
+	u1_buttons,
+	ARRAY_SIZE(u1_buttons),
+};
+
+struct platform_device u1_keypad = {
+	.name = "gpio-keys",
+	.dev.platform_data = &u1_keypad_platform_data,
+};
+
+#ifdef CONFIG_SEC_DEV_JACK
+static void sec_set_jack_micbias(bool on)
+{
+		gpio_set_value(GPIO_EAR_MIC_BIAS_EN, on);
+}
+
+static struct sec_jack_zone sec_jack_zones[] = {
+	{
+		/* adc == 0, unstable zone, default to 3pole if it stays
+		 * in this range for 300ms (15ms delays, 20 samples)
+		 */
+		.adc_high = 0,
+		.delay_ms = 15,
+		.check_count = 20,
+		.jack_type = SEC_HEADSET_3POLE,
+	},
+	{
+		/* 0 < adc <= 1200, unstable zone, default to 3pole if it stays
+		 * in this range for 300ms (15ms delays, 20 samples)
+		 */
+		.adc_high = 1200,
+		.delay_ms = 10,
+		.check_count = 80,
+		.jack_type = SEC_HEADSET_3POLE,
+	},
+	{
+		/* 950 < adc <= 2600, unstable zone, default to 4pole if it
+		 * stays in this range for 800ms (10ms delays, 80 samples)
+		 */
+		.adc_high = 2600,
+		.delay_ms = 10,
+		.check_count = 10,
+		.jack_type = SEC_HEADSET_4POLE,
+	},
+	{
+		/* 2600 < adc <= 3400, 3 pole zone, default to 3pole if it
+		 * stays in this range for 100ms (10ms delays, 10 samples)
+		 */
+		.adc_high = 3800,
+		.delay_ms = 10,
+		.check_count = 5,
+		.jack_type = SEC_HEADSET_4POLE,
+	},
+	{
+		/* adc > 3400, unstable zone, default to 3pole if it stays
+		 * in this range for two seconds (10ms delays, 200 samples)
+		 */
+		.adc_high = 0x7fffffff,
+		.delay_ms = 10,
+		.check_count = 200,
+		.jack_type = SEC_HEADSET_3POLE,
+	},
+};
+
+/* To support 3-buttons earjack */
+static struct sec_jack_buttons_zone sec_jack_buttons_zones[] = {
+	{
+		/* 0 <= adc <=170, stable zone */
+		.code = KEY_MEDIA,
+		.adc_low = 0,
+		.adc_high = 170,
+	},
+	{
+		/* 171 <= adc <= 370, stable zone */
+		.code = KEY_VOLUMEUP,
+		.adc_low = 171,
+		.adc_high = 370,
+	},
+	{
+		/* 371 <= adc <= 850, stable zone */
+		.code = KEY_VOLUMEDOWN,
+		.adc_low = 371,
+		.adc_high = 850,
+	},
+};
+
+static struct sec_jack_platform_data sec_jack_data = {
+	.set_micbias_state = sec_set_jack_micbias,
+	.zones = sec_jack_zones,
+	.num_zones = ARRAY_SIZE(sec_jack_zones),
+	.buttons_zones = sec_jack_buttons_zones,
+	.num_buttons_zones = ARRAY_SIZE(sec_jack_buttons_zones),
+	.det_gpio = GPIO_DET_35,
+	.send_end_gpio = GPIO_EAR_SEND_END,
+};
+
+static struct platform_device sec_device_jack = {
+	.name = "sec_jack",
+	.id = 1,		/* will be used also for gpio_event id */
+	.dev.platform_data = &sec_jack_data,
+};
+#endif
+
+void tsp_register_callback(void *function)
+{
+	charging_cbs.tsp_set_charging_cable = function;
+}
+
+void tsp_read_ta_status(void *ta_status)
+{
+	*(bool *)ta_status = is_cable_attached;
+}
+#ifdef CONFIG_TOUCHSCREEN_ATMEL_MXT224_GC
+static void mxt224_power_on(void)
+{
+	s3c_gpio_cfgpin(GPIO_TSP_LDO_ON, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TSP_LDO_ON, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TSP_LDO_ON, 1);
+	mdelay(70);
+	s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_NONE);
+	s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_SFN(0xf));
+	mdelay(40);
+}
+
+static void mxt224_power_off(void)
+{
+	s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_DOWN);
+
+	s3c_gpio_cfgpin(GPIO_TSP_LDO_ON, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TSP_LDO_ON, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TSP_LDO_ON, 0);
+}
+
+static u8 t7_config[] = {GEN_POWERCONFIG_T7,
+	64, 255, 50
+};
+static u8 t8_config[] = {GEN_ACQUISITIONCONFIG_T8,
+	10, 0, 5, 1, 0, 0, 9, 27
+};
+static u8 t9_config[] = {TOUCH_MULTITOUCHSCREEN_T9,
+	143, 0, 0, 18, 11, 0, 16, 32, 2, 0,
+	0, 3, 1, 46, 10, 5, 40, 10, 31, 3,
+	223, 1, 0, 0, 0, 0, 0, 0, 0, 0,
+	18
+};
+static u8 t15_config[] = {TOUCH_KEYARRAY_T15,
+	131, 16, 11, 2, 1, 0, 0, 45, 4, 0,
+	0
+};
+static u8 t18_config[] = {SPT_COMCONFIG_T18,
+	0, 0
+};
+static u8 t19_config[] = {SPT_GPIOPWM_T19,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 0, 0, 0
+};
+static u8 t20_config[] = {PROCI_GRIPFACESUPPRESSION_T20,
+	19, 0, 0, 5, 5, 0, 0, 30, 20, 4, 15,
+	10
+};
+static u8 t22_config[] = {PROCG_NOISESUPPRESSION_T22,
+	5, 0, 0, 0, 0, 0, 0, 3, 27, 0,
+	0, 29, 34, 39, 49, 58, 3
+};
+static u8 t23_config[] = {TOUCH_PROXIMITY_T23,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 0, 0
+};
+static u8 t24_config[] = {PROCI_ONETOUCHGESTUREPROCESSOR_T24,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+static u8 t25_config[] = {SPT_SELFTEST_T25,
+	0, 0
+};
+static u8 t27_config[] = {PROCI_TWOTOUCHGESTUREPROCESSOR_T27,
+	0, 0, 0, 0, 0, 0, 0
+};
+static u8 t28_config[] = {SPT_CTECONFIG_T28,
+	1, 0, 2, 16, 63, 60
+};
+static u8 end_config[] = {RESERVED_T255};
+
+static const u8 *mxt224_config[] = {
+	t7_config,
+	t8_config,
+	t9_config,
+	t15_config,
+	t18_config,
+	t19_config,
+	t20_config,
+	t22_config,
+	t23_config,
+	t24_config,
+	t25_config,
+	t27_config,
+	t28_config,
+	end_config,
+};
+
+
+static struct mxt224_platform_data mxt224_data = {
+	.max_finger_touches = 10,
+	.gpio_read_done = GPIO_TSP_INT,
+	.config = mxt224_config,
+	.min_x = 0,
+	.max_x = 479,
+	.min_y = 0,
+	.max_y = 799,
+	.min_z = 0,
+	.max_z = 255,
+	.min_w = 0,
+	.max_w = 30,
+	.power_on = mxt224_power_on,
+	.power_off = mxt224_power_off,
+};
+
+
+#endif
+#ifdef CONFIG_TOUCHSCREEN_ATMEL_MXT224_U1
+static void mxt224_power_on(void)
+{
+	s3c_gpio_cfgpin(GPIO_TSP_LDO_ON, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TSP_LDO_ON, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TSP_LDO_ON, 1);
+	mdelay(70);
+	s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_NONE);
+	s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_SFN(0xf));
+	mdelay(40);
+	/* printk("mxt224_power_on is finished\n"); */
+}
+
+static void mxt224_power_off(void)
+{
+	s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_DOWN);
+
+	s3c_gpio_cfgpin(GPIO_TSP_LDO_ON, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TSP_LDO_ON, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TSP_LDO_ON, 0);
+	/* printk("mxt224_power_off is finished\n"); */
+}
+
+/*
+  Configuration for MXT224
+*/
+#define MXT224_THRESHOLD_BATT		40
+#define MXT224_THRESHOLD_BATT_INIT		55
+#define MXT224_THRESHOLD_CHRG		70
+#define MXT224_NOISE_THRESHOLD_BATT		30
+#define MXT224_NOISE_THRESHOLD_CHRG		40
+#define MXT224_MOVFILTER_BATT		47
+#define MXT224_MOVFILTER_CHRG		47
+#define MXT224_ATCHCALST		4
+#define MXT224_ATCHCALTHR		35
+
+static u8 t7_config[] = { GEN_POWERCONFIG_T7,
+	48,			/* IDLEACQINT */
+	255,			/* ACTVACQINT */
+	25			/* ACTV2IDLETO: 25 * 200ms = 5s */
+};
+
+static u8 t8_config[] = { GEN_ACQUISITIONCONFIG_T8,
+	10, 0, 5, 1, 0, 0, MXT224_ATCHCALST, MXT224_ATCHCALTHR
+};				/*byte 3: 0 */
+
+static u8 t9_config[] = { TOUCH_MULTITOUCHSCREEN_T9,
+	131, 0, 0, 19, 11, 0, 32, MXT224_THRESHOLD_BATT, 2, 1,
+	0,
+	15,			/* MOVHYSTI */
+	1, MXT224_MOVFILTER_BATT, MXT224_MAX_MT_FINGERS, 5, 40, 10, 31, 3,
+	223, 1, 0, 0, 0, 0, 143, 55, 143, 90, 18
+};
+
+static u8 t18_config[] = { SPT_COMCONFIG_T18,
+	0, 1
+};
+
+static u8 t20_config[] = { PROCI_GRIPFACESUPPRESSION_T20,
+	7, 0, 0, 0, 0, 0, 0, 30, 20, 4, 15, 10
+};
+
+static u8 t22_config[] = { PROCG_NOISESUPPRESSION_T22,
+	143, 0, 0, 0, 0, 0, 0, 3, MXT224_NOISE_THRESHOLD_BATT, 0,
+	0, 29, 34, 39, 49, 58, 3
+};
+
+static u8 t28_config[] = { SPT_CTECONFIG_T28,
+			   0, 0, 3, 16, 19, 60
+};
+static u8 end_config[] = { RESERVED_T255 };
+
+static const u8 *mxt224_config[] = {
+	t7_config,
+	t8_config,
+	t9_config,
+	t18_config,
+	t20_config,
+	t22_config,
+	t28_config,
+	end_config,
+};
+
+/*
+  Configuration for MXT224-E
+*/
+#define MXT224E_THRESHOLD_BATT		50
+#define MXT224E_THRESHOLD_CHRG		40
+#define MXT224E_CALCFG_BATT		0x42
+#define MXT224E_CALCFG_CHRG		0x52
+#define MXT224E_ATCHFRCCALTHR_NORMAL		40
+#define MXT224E_ATCHFRCCALRATIO_NORMAL		55
+#define MXT224E_GHRGTIME_BATT		27
+#define MXT224E_GHRGTIME_CHRG		22
+#define MXT224E_ATCHCALST		4
+#define MXT224E_ATCHCALTHR		35
+#define MXT224E_BLEN_BATT		32
+#define MXT224E_BLEN_CHRG		16
+#define MXT224E_MOVFILTER_BATT		46
+#define MXT224E_MOVFILTER_CHRG		46
+#define MXT224E_ACTVSYNCSPERX_NORMAL		32
+#define MXT224E_NEXTTCHDI_NORMAL		0
+
+#if defined(CONFIG_TARGET_LOCALE_NAATT)
+static u8 t7_config_e[] = { GEN_POWERCONFIG_T7,
+	48, 255, 25
+};
+
+static u8 t8_config_e[] = { GEN_ACQUISITIONCONFIG_T8,
+	27, 0, 5, 1, 0, 0, 8, 8, 8, 180
+};
+
+/* MXT224E_0V5_CONFIG */
+/* NEXTTCHDI added */
+static u8 t9_config_e[] = { TOUCH_MULTITOUCHSCREEN_T9,
+	139, 0, 0, 19, 11, 0, 32, 50, 2, 1,
+	10, 3, 1, 11, MXT224_MAX_MT_FINGERS, 5, 40, 10, 31, 3,
+	223, 1, 10, 10, 10, 10, 143, 40, 143, 80,
+	18, 15, 50, 50, 2
+};
+
+static u8 t15_config_e[] = { TOUCH_KEYARRAY_T15,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t18_config_e[] = { SPT_COMCONFIG_T18,
+	0, 0
+};
+
+static u8 t23_config_e[] = { TOUCH_PROXIMITY_T23,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t25_config_e[] = { SPT_SELFTEST_T25,
+	0, 0, 188, 52, 124, 21, 188, 52, 124, 21, 0, 0, 0, 0
+};
+
+static u8 t40_config_e[] = { PROCI_GRIPSUPPRESSION_T40,
+	0, 0, 0, 0, 0
+};
+
+static u8 t42_config_e[] = { PROCI_TOUCHSUPPRESSION_T42,
+	0, 32, 120, 100, 0, 0, 0, 0
+};
+
+static u8 t46_config_e[] = { SPT_CTECONFIG_T46,
+	0, 3, 16, 35, 0, 0, 1, 0
+};
+
+static u8 t47_config_e[] = { PROCI_STYLUS_T47,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*MXT224E_0V5_CONFIG */
+static u8 t48_config_e[] = { PROCG_NOISESUPPRESSION_T48,
+	3, 4, 72, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	6, 6, 0, 0, 100, 4, 64, 10, 0, 20, 5, 0, 38, 0, 5,
+	0, 0, 0, 0, 0, 0, 32, 50, 2, 3, 1, 11, 10, 5, 40, 10, 10,
+	10, 10, 143, 40, 143, 80, 18, 15, 2
+};
+
+static u8 t48_config_chrg_e[] = { PROCG_NOISESUPPRESSION_T48,
+	1, 4, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	6, 6, 0, 0, 100, 4, 64, 10, 0, 20, 5, 0, 38, 0, 20,
+	0, 0, 0, 0, 0, 0, 16, 70, 2, 5, 2, 46, 10, 5, 40, 10, 0,
+	10, 10, 143, 40, 143, 80, 18, 15, 2
+};
+
+#else
+static u8 t7_config_e[] = { GEN_POWERCONFIG_T7,
+	48,			/* IDLEACQINT */
+	255,			/* ACTVACQINT */
+	25			/* ACTV2IDLETO: 25 * 200ms = 5s */
+};
+
+static u8 t8_config_e[] = { GEN_ACQUISITIONCONFIG_T8,
+	MXT224E_GHRGTIME_BATT, 0, 5, 1, 0, 0,
+	MXT224E_ATCHCALST, MXT224E_ATCHCALTHR,
+	MXT224E_ATCHFRCCALTHR_NORMAL,
+	MXT224E_ATCHFRCCALRATIO_NORMAL
+};
+
+/* MXT224E_0V5_CONFIG */
+/* NEXTTCHDI added */
+#ifdef CONFIG_TARGET_LOCALE_NA
+#ifdef CONFIG_MACH_U1_NA_USCC_REV05
+static u8 t9_config_e[] = { TOUCH_MULTITOUCHSCREEN_T9,
+	139, 0, 0, 19, 11, 0, MXT224E_BLEN_BATT, MXT224E_THRESHOLD_BATT, 2, 1,
+	10,
+	10,			/* MOVHYSTI */
+	1, MXT224E_MOVFILTER_BATT, MXT224_MAX_MT_FINGERS, 5, 40, 10, 31, 3,
+	223, 1, 10, 10, 10, 10, 143, 40, 143, 80,
+	18, 15, 50, 50, 0
+};
+
+#else
+static u8 t9_config_e[] = { TOUCH_MULTITOUCHSCREEN_T9,
+	139, 0, 0, 19, 11, 0, MXT224E_BLEN_BATT, MXT224E_THRESHOLD_BATT, 2, 1,
+	10,
+	10,			/* MOVHYSTI */
+	1, MXT224E_MOVFILTER_BATT, MXT224_MAX_MT_FINGERS, 5, 40, 10, 31, 3,
+	223, 1, 10, 10, 10, 10, 143, 40, 143, 80,
+	18, 15, 50, 50, 2
+};
+#endif
+#else
+static u8 t9_config_e[] = { TOUCH_MULTITOUCHSCREEN_T9,
+	139, 0, 0, 19, 11, 0, MXT224E_BLEN_BATT, MXT224E_THRESHOLD_BATT, 2, 1,
+	10,
+	15,			/* MOVHYSTI */
+	1, MXT224E_MOVFILTER_BATT, MXT224_MAX_MT_FINGERS, 5, 40, 10, 31, 3,
+	223, 1, 10, 10, 10, 10, 143, 40, 143, 80,
+	18, 15, 50, 50, MXT224E_NEXTTCHDI_NORMAL
+};
+#endif
+
+static u8 t15_config_e[] = { TOUCH_KEYARRAY_T15,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t18_config_e[] = { SPT_COMCONFIG_T18,
+	0, 0
+};
+
+static u8 t23_config_e[] = { TOUCH_PROXIMITY_T23,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t25_config_e[] = { SPT_SELFTEST_T25,
+	0, 0, 0, 0, 0, 0, 0, 0
+};
+
+#ifdef CONFIG_MACH_U1_NA_USCC_REV05
+static u8 t38_config_e[] = { SPT_USERDATA_T38,
+	0, 1, 13, 19, 44, 0, 0, 0
+};
+#else
+static u8 t38_config_e[] = { SPT_USERDATA_T38,
+	0, 1, 14, 23, 44, 0, 0, 0
+};
+#endif
+
+static u8 t40_config_e[] = { PROCI_GRIPSUPPRESSION_T40,
+	0, 0, 0, 0, 0
+};
+
+static u8 t42_config_e[] = { PROCI_TOUCHSUPPRESSION_T42,
+	0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t46_config_e[] = { SPT_CTECONFIG_T46,
+	0, 3, 16, MXT224E_ACTVSYNCSPERX_NORMAL, 0, 0, 1, 0, 0
+};
+
+static u8 t47_config_e[] = { PROCI_STYLUS_T47,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*MXT224E_0V5_CONFIG */
+#ifdef CONFIG_TARGET_LOCALE_NA
+#ifdef CONFIG_MACH_U1_NA_USCC_REV05
+static u8 t48_config_chrg_e[] = { PROCG_NOISESUPPRESSION_T48,
+	3, 132, 0x52, 0, 0, 0, 0, 0, 10, 15,
+	0, 0, 0, 6, 6, 0, 0, 64, 4, 64,
+	10, 0, 10, 5, 0, 19, 0, 20, 0, 0,
+	0, 0, 0, 0, 0, 40, 2,	/*blen=0,threshold=50 */
+	10,			/* MOVHYSTI */
+	1, 47,
+	10, 5, 40, 240, 245, 10, 10, 148, 50, 143,
+	80, 18, 10, 0
+};
+
+static u8 t48_config_e[] = { PROCG_NOISESUPPRESSION_T48,
+	3, 132, 0x40, 0, 0, 0, 0, 0, 10, 15,
+	0, 0, 0, 6, 6, 0, 0, 64, 4, 64,
+	10, 0, 20, 5, 0, 38, 0, 5, 0, 0,	/*byte 27 original value 20 */
+	0, 0, 0, 0, 32, MXT224E_THRESHOLD, 2,
+	10,
+	1, 46,
+	MXT224_MAX_MT_FINGERS, 5, 40, 10, 0, 10, 10, 143, 40, 143,
+	80, 18, 15, 0
+};
+#else
+static u8 t48_config_chrg_e[] = { PROCG_NOISESUPPRESSION_T48,
+	1, 4, 0x50, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 6, 6, 0, 0, 100, 4, 64,
+	10, 0, 20, 5, 0, 38, 0, 20, 0, 0,
+	0, 0, 0, 0, 0, 40, 2,	/*blen=0,threshold=50 */
+	10,			/* MOVHYSTI */
+	1, 15,
+	10, 5, 40, 240, 245, 10, 10, 148, 50, 143,
+	80, 18, 10, 2
+};
+
+static u8 t48_config_e[] = { PROCG_NOISESUPPRESSION_T48,
+	1, 4, 0x40, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 6, 6, 0, 0, 100, 4, 64,
+	10, 0, 20, 5, 0, 38, 0, 5, 0, 0,	/*byte 27 original value 20 */
+	0, 0, 0, 0, 32, 50, 2,
+	10,
+	1, 46,
+	MXT224_MAX_MT_FINGERS, 5, 40, 10, 0, 10, 10, 143, 40, 143,
+	80, 18, 15, 2
+};
+#endif				/*CONFIG_MACH_U1_NA_USCC_REV05 */
+#else
+static u8 t48_config_chrg_e[] = { PROCG_NOISESUPPRESSION_T48,
+	3, 132, MXT224E_CALCFG_CHRG, 0, 0, 0, 0, 0, 10, 15,
+	0, 0, 0, 6, 6, 0, 0, 64, 4, 64,
+	10, 0, 9, 5, 0, 15, 0, 20, 0, 0,
+	0, 0, 0, 0, 0, MXT224E_THRESHOLD_CHRG, 2,
+	15,			/* MOVHYSTI */
+	1, 47,
+	MXT224_MAX_MT_FINGERS, 5, 40, 235, 235, 10, 10, 160, 50, 143,
+	80, 18, 10, 0
+};
+
+static u8 t48_config_e[] = { PROCG_NOISESUPPRESSION_T48,
+	3, 132, MXT224E_CALCFG_BATT, 0, 0, 0, 0, 0, 10, 15,
+	0, 0, 0, 6, 6, 0, 0, 48, 4, 48,
+	10, 0, 10, 5, 0, 20, 0, 5, 0, 0,	/*byte 27 original value 20 */
+	0, 0, 0, 0, 32, MXT224E_THRESHOLD_BATT, 2,
+	15,
+	1, 46,
+	MXT224_MAX_MT_FINGERS, 5, 40, 10, 10, 10, 10, 143, 40, 143,
+	80, 18, 15, 0
+};
+#endif				/*CONFIG_TARGET_LOCALE_NA */
+#endif				/*CONFIG_TARGET_LOCALE_NAATT */
+
+static u8 end_config_e[] = { RESERVED_T255 };
+
+static const u8 *mxt224e_config[] = {
+	t7_config_e,
+	t8_config_e,
+	t9_config_e,
+	t15_config_e,
+	t18_config_e,
+	t23_config_e,
+	t25_config_e,
+	t38_config_e,
+	t40_config_e,
+	t42_config_e,
+	t46_config_e,
+	t47_config_e,
+	t48_config_e,
+	end_config_e,
+};
+
+static struct mxt224_platform_data mxt224_data = {
+	.max_finger_touches = MXT224_MAX_MT_FINGERS,
+	.gpio_read_done = GPIO_TSP_INT,
+	.config = mxt224_config,
+	.config_e = mxt224e_config,
+	.t48_config_batt_e = t48_config_e,
+	.t48_config_chrg_e = t48_config_chrg_e,
+	.min_x = 0,
+	.max_x = 479,
+	.min_y = 0,
+	.max_y = 799,
+	.min_z = 0,
+	.max_z = 255,
+	.min_w = 0,
+	.max_w = 30,
+	.atchcalst = MXT224_ATCHCALST,
+	.atchcalsthr = MXT224_ATCHCALTHR,
+	.tchthr_batt = MXT224_THRESHOLD_BATT,
+	.tchthr_batt_init = MXT224_THRESHOLD_BATT_INIT,
+	.tchthr_charging = MXT224_THRESHOLD_CHRG,
+	.noisethr_batt = MXT224_NOISE_THRESHOLD_BATT,
+	.noisethr_charging = MXT224_NOISE_THRESHOLD_CHRG,
+	.movfilter_batt = MXT224_MOVFILTER_BATT,
+	.movfilter_charging = MXT224_MOVFILTER_CHRG,
+	.atchcalst_e = MXT224E_ATCHCALST,
+	.atchcalsthr_e = MXT224E_ATCHCALTHR,
+	.tchthr_batt_e = MXT224E_THRESHOLD_BATT,
+	.tchthr_charging_e = MXT224E_THRESHOLD_CHRG,
+	.calcfg_batt_e = MXT224E_CALCFG_BATT,
+	.calcfg_charging_e = MXT224E_CALCFG_CHRG,
+	.atchfrccalthr_e = MXT224E_ATCHFRCCALTHR_NORMAL,
+	.atchfrccalratio_e = MXT224E_ATCHFRCCALRATIO_NORMAL,
+	.chrgtime_batt_e = MXT224E_GHRGTIME_BATT,
+	.chrgtime_charging_e = MXT224E_GHRGTIME_CHRG,
+	.blen_batt_e = MXT224E_BLEN_BATT,
+	.blen_charging_e = MXT224E_BLEN_CHRG,
+	.movfilter_batt_e = MXT224E_MOVFILTER_BATT,
+	.movfilter_charging_e = MXT224E_MOVFILTER_CHRG,
+	.actvsyncsperx_e = MXT224E_ACTVSYNCSPERX_NORMAL,
+	.nexttchdi_e = MXT224E_NEXTTCHDI_NORMAL,
+	.power_on = mxt224_power_on,
+	.power_off = mxt224_power_off,
+	.register_cb = tsp_register_callback,
+	.read_ta_status = tsp_read_ta_status,
+};
+
+#endif				/*CONFIG_TOUCHSCREEN_ATMEL_MXT224_U1 */
+
+#if defined(CONFIG_TOUCHSCREEN_ATMEL_MXT540E)
+static void mxt540e_power_on(void)
+{
+	gpio_request(GPIO_TSP_SDA, "TSP_SDA");
+	gpio_request(GPIO_TSP_SCL, "TSP_SCL");
+
+	s3c_gpio_cfgpin(GPIO_TSP_SDA, S3C_GPIO_SFN(3));
+	s3c_gpio_cfgpin(GPIO_TSP_SCL, S3C_GPIO_SFN(3));
+	s3c_gpio_setpull(GPIO_TSP_SDA, S3C_GPIO_PULL_UP);
+	s3c_gpio_setpull(GPIO_TSP_SCL, S3C_GPIO_PULL_UP);
+
+	s3c_gpio_cfgpin(GPIO_TSP_LDO_ON, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TSP_LDO_ON, S3C_GPIO_PULL_NONE);
+	gpio_direction_output(GPIO_TSP_LDO_ON, GPIO_LEVEL_HIGH);
+	msleep(MXT540E_HW_RESET_TIME);
+	s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_NONE);
+	s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_SFN(0xf));
+
+	gpio_free(GPIO_TSP_SDA);
+	gpio_free(GPIO_TSP_SCL);
+}
+
+static void mxt540e_power_off(void)
+{
+	gpio_request(GPIO_TSP_SDA, "TSP_SDA");
+	gpio_request(GPIO_TSP_SCL, "TSP_SCL");
+
+	s3c_gpio_cfgpin(GPIO_TSP_SDA, S3C_GPIO_OUTPUT);
+	s3c_gpio_cfgpin(GPIO_TSP_SCL, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TSP_SDA, S3C_GPIO_PULL_NONE);
+	s3c_gpio_setpull(GPIO_TSP_SCL, S3C_GPIO_PULL_NONE);
+	gpio_direction_output(GPIO_TSP_SDA, GPIO_LEVEL_LOW);
+	gpio_direction_output(GPIO_TSP_SCL, GPIO_LEVEL_LOW);
+
+	s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_DOWN);
+	gpio_direction_output(GPIO_TSP_INT, GPIO_LEVEL_LOW);
+
+	s3c_gpio_cfgpin(GPIO_TSP_LDO_ON, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TSP_LDO_ON, S3C_GPIO_PULL_NONE);
+	gpio_direction_output(GPIO_TSP_LDO_ON, GPIO_LEVEL_LOW);
+
+	gpio_free(GPIO_TSP_SDA);
+	gpio_free(GPIO_TSP_SCL);
+}
+
+static void mxt540e_power_on_oled(void)
+{
+	gpio_request(GPIO_OLED_DET, "OLED_DET");
+
+	mxt540e_power_on();
+
+	s3c_gpio_setpull(GPIO_OLED_DET, S3C_GPIO_PULL_NONE);
+	s3c_gpio_cfgpin(GPIO_OLED_DET, S3C_GPIO_SFN(0xf));
+
+	gpio_free(GPIO_OLED_DET);
+
+	printk(KERN_INFO "[TSP] %s\n", __func__);
+}
+
+static void mxt540e_power_off_oled(void)
+{
+	gpio_request(GPIO_OLED_DET, "OLED_DET");
+
+	s3c_gpio_cfgpin(GPIO_OLED_DET, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_OLED_DET, S3C_GPIO_PULL_NONE);
+	gpio_direction_output(GPIO_OLED_DET, GPIO_LEVEL_LOW);
+
+	mxt540e_power_off();
+
+	gpio_free(GPIO_OLED_DET);
+
+	printk(KERN_INFO "[TSP] %s\n", __func__);
+}
+
+/*
+  Configuration for MXT540E
+*/
+#define MXT540E_MAX_MT_FINGERS		10
+#define MXT540E_CHRGTIME_BATT		48
+#define MXT540E_CHRGTIME_CHRG		48
+#define MXT540E_THRESHOLD_BATT		50
+#define MXT540E_THRESHOLD_CHRG		40
+#define MXT540E_ACTVSYNCSPERX_BATT		24
+#define MXT540E_ACTVSYNCSPERX_CHRG		28
+#define MXT540E_CALCFG_BATT		98
+#define MXT540E_CALCFG_CHRG		114
+#define MXT540E_ATCHFRCCALTHR_WAKEUP		8
+#define MXT540E_ATCHFRCCALRATIO_WAKEUP		180
+#define MXT540E_ATCHFRCCALTHR_NORMAL		40
+#define MXT540E_ATCHFRCCALRATIO_NORMAL		55
+
+static u8 t7_config_e[] = { GEN_POWERCONFIG_T7,
+	48, 255, 50
+};
+
+static u8 t8_config_e[] = { GEN_ACQUISITIONCONFIG_T8,
+	MXT540E_CHRGTIME_BATT, 0, 5, 1, 0, 0, 4, 20,
+	MXT540E_ATCHFRCCALTHR_WAKEUP, MXT540E_ATCHFRCCALRATIO_WAKEUP
+};
+
+static u8 t9_config_e[] = { TOUCH_MULTITOUCHSCREEN_T9,
+	131, 0, 0, 16, 26, 0, 192, MXT540E_THRESHOLD_BATT, 2, 6,
+	10, 10, 10, 80, MXT540E_MAX_MT_FINGERS, 20, 40, 20, 31, 3,
+	255, 4, 3, 3, 2, 2, 136, 60, 136, 40,
+	18, 15, 0, 0, 0
+};
+
+static u8 t15_config_e[] = { TOUCH_KEYARRAY_T15,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t18_config_e[] = { SPT_COMCONFIG_T18,
+	0, 0
+};
+
+static u8 t19_config_e[] = { SPT_GPIOPWM_T19,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t24_config_e[] = { PROCI_ONETOUCHGESTUREPROCESSOR_T24,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t25_config_e[] = { SPT_SELFTEST_T25,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t27_config_e[] = { PROCI_TWOTOUCHGESTUREPROCESSOR_T27,
+	0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t40_config_e[] = { PROCI_GRIPSUPPRESSION_T40,
+	0, 0, 0, 0, 0
+};
+
+static u8 t42_config_e[] = { PROCI_TOUCHSUPPRESSION_T42,
+	0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t43_config_e[] = { SPT_DIGITIZER_T43,
+	0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t46_config_e[] = { SPT_CTECONFIG_T46,
+	0, 0, 16, MXT540E_ACTVSYNCSPERX_BATT, 0, 0, 1, 0
+};
+
+static u8 t47_config_e[] = { PROCI_STYLUS_T47,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t48_config_e[] = { PROCG_NOISESUPPRESSION_T48,
+	3, 132, MXT540E_CALCFG_BATT, 0, 0, 0, 0, 0, 1, 2,
+	0, 0, 0, 6, 6, 0, 0, 28, 4, 64,
+	10, 0, 20, 6, 0, 30, 0, 0, 0, 0,
+	0, 0, 0, 0, 192, MXT540E_THRESHOLD_BATT, 2, 10, 10, 47,
+	MXT540E_MAX_MT_FINGERS, 5, 20, 253, 0, 7, 7, 160, 55, 136,
+	0, 18, 5, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 0
+};
+
+static u8 t48_config_chrg_e[] = { PROCG_NOISESUPPRESSION_T48,
+	3, 132, MXT540E_CALCFG_CHRG, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 6, 6, 0, 0, 36, 4, 64,
+	10, 0, 10, 6, 0, 20, 0, 0, 0, 0,
+	0, 0, 0, 0, 112, MXT540E_THRESHOLD_CHRG, 2, 10, 5, 47,
+	MXT540E_MAX_MT_FINGERS, 5, 20, 253, 0, 7, 7, 160, 55, 136,
+	0, 18, 10, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 0
+};
+
+static u8 t52_config_e[] = { TOUCH_PROXKEY_T52,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t55_config_e[] = {ADAPTIVE_T55,
+	0, 0, 0, 0, 0, 0
+};
+
+static u8 t57_config_e[] = {SPT_GENERICDATA_T57,
+	243, 25, 1
+};
+
+static u8 t61_config_e[] = {SPT_TIMER_T61,
+	0, 0, 0, 0, 0
+};
+
+static u8 end_config_e[] = { RESERVED_T255 };
+
+static const u8 *mxt540e_config[] = {
+	t7_config_e,
+	t8_config_e,
+	t9_config_e,
+	t15_config_e,
+	t18_config_e,
+	t19_config_e,
+	t24_config_e,
+	t25_config_e,
+	t27_config_e,
+	t40_config_e,
+	t42_config_e,
+	t43_config_e,
+	t46_config_e,
+	t47_config_e,
+	t48_config_e,
+	t52_config_e,
+	t55_config_e,
+	t57_config_e,
+	t61_config_e,
+	end_config_e,
+};
+
+struct mxt540e_platform_data mxt540e_data = {
+	.max_finger_touches = MXT540E_MAX_MT_FINGERS,
+	.gpio_read_done = GPIO_TSP_INT,
+	.config_e = mxt540e_config,
+	.min_x = 0,
+	.max_x = 799,
+	.min_y = 0,
+	.max_y = 1279,
+	.min_z = 0,
+	.max_z = 255,
+	.min_w = 0,
+	.max_w = 30,
+	.chrgtime_batt = MXT540E_CHRGTIME_BATT,
+	.chrgtime_charging = MXT540E_CHRGTIME_CHRG,
+	.tchthr_batt = MXT540E_THRESHOLD_BATT,
+	.tchthr_charging = MXT540E_THRESHOLD_CHRG,
+	.actvsyncsperx_batt = MXT540E_ACTVSYNCSPERX_BATT,
+	.actvsyncsperx_charging = MXT540E_ACTVSYNCSPERX_CHRG,
+	.calcfg_batt_e = MXT540E_CALCFG_BATT,
+	.calcfg_charging_e = MXT540E_CALCFG_CHRG,
+	.atchfrccalthr_e = MXT540E_ATCHFRCCALTHR_NORMAL,
+	.atchfrccalratio_e = MXT540E_ATCHFRCCALRATIO_NORMAL,
+	.t48_config_batt_e = t48_config_e,
+	.t48_config_chrg_e = t48_config_chrg_e,
+	.power_on = mxt540e_power_on,
+	.power_off = mxt540e_power_off,
+	.power_on_with_oleddet = mxt540e_power_on_oled,
+	.power_off_with_oleddet = mxt540e_power_off_oled,
+	.register_cb = tsp_register_callback,
+	.read_ta_status = tsp_read_ta_status,
+};
+#endif
+
+#ifdef CONFIG_EPEN_WACOM_G5SP
+static int p6_wacom_init_hw(void);
+static int p6_wacom_exit_hw(void);
+static int p6_wacom_suspend_hw(void);
+static int p6_wacom_resume_hw(void);
+static int p6_wacom_early_suspend_hw(void);
+static int p6_wacom_late_resume_hw(void);
+static int p6_wacom_reset_hw(void);
+static void p6_wacom_register_callbacks(struct wacom_g5_callbacks *cb);
+
+static struct wacom_g5_platform_data p6_wacom_platform_data = {
+	.x_invert = 1,
+	.y_invert = 0,
+	.xy_switch = 1,
+	.min_x = 0,
+	.max_x = WACOM_POSX_MAX,
+	.min_y = 0,
+	.max_y = WACOM_POSY_MAX,
+	.min_pressure = 0,
+	.max_pressure = WACOM_PRESSURE_MAX,
+	.init_platform_hw = p6_wacom_init_hw,
+/*	.exit_platform_hw =,	*/
+	.suspend_platform_hw = p6_wacom_suspend_hw,
+	.resume_platform_hw = p6_wacom_resume_hw,
+	.early_suspend_platform_hw = p6_wacom_early_suspend_hw,
+	.late_resume_platform_hw = p6_wacom_late_resume_hw,
+	.reset_platform_hw = p6_wacom_reset_hw,
+	.register_cb = p6_wacom_register_callbacks,
+};
+
+#endif
+
+#ifdef CONFIG_EPEN_WACOM_G5SP
+static int p6_wacom_suspend_hw(void)
+{
+	return p6_wacom_early_suspend_hw();
+}
+
+static int p6_wacom_resume_hw(void)
+{
+	return p6_wacom_late_resume_hw();
+}
+
+static int p6_wacom_early_suspend_hw(void)
+{
+	gpio_set_value(GPIO_PEN_RESET, 0);
+	return 0;
+}
+
+static int p6_wacom_late_resume_hw(void)
+{
+	gpio_set_value(GPIO_PEN_RESET, 1);
+	return 0;
+}
+
+static int p6_wacom_reset_hw(void)
+{
+	gpio_set_value(GPIO_PEN_RESET, 0);
+	msleep(200);
+	gpio_set_value(GPIO_PEN_RESET, 1);
+	return 0;
+}
+
+static void p6_wacom_register_callbacks(struct wacom_g5_callbacks *cb)
+{
+	wacom_callbacks = cb;
+};
+
+#endif /* CONFIG_EPEN_WACOM_G5SP */
+
+#ifdef CONFIG_I2C_S3C2410
+/* I2C0 */
+static struct i2c_board_info i2c_devs0[] __initdata = {
+	{I2C_BOARD_INFO("24c128", 0x50),},	/* Samsung S524AD0XD1 */
+	{I2C_BOARD_INFO("24c128", 0x52),},	/* Samsung S524AD0XD1 */
+};
+
+#ifdef CONFIG_S3C_DEV_I2C1
+/* I2C1 */
+static struct i2c_board_info i2c_devs1[] __initdata = {
+	{
+		I2C_BOARD_INFO("k3g", 0x69),
+		.irq = IRQ_EINT(1),
+	},
+	{
+		I2C_BOARD_INFO("k3dh", 0x19),
+	},
+#ifdef CONFIG_MACH_Q1_BD
+	{
+		I2C_BOARD_INFO("bmp180", 0x77),
+	},
+#endif
+};
+#endif
+#ifdef CONFIG_S3C_DEV_I2C2
+/* I2C2 */
+static struct i2c_board_info i2c_devs2[] __initdata = {
+};
+#endif
+#ifdef CONFIG_S3C_DEV_I2C3
+/* I2C3 */
+static struct i2c_board_info i2c_devs3[] __initdata = {
+#ifdef CONFIG_TOUCHSCREEN_ATMEL_MXT224_U1
+	{
+		I2C_BOARD_INFO(MXT224_DEV_NAME, 0x4a),
+		.platform_data = &mxt224_data,
+	},
+#endif
+#ifdef CONFIG_TOUCHSCREEN_ATMEL_MXT540E
+	{
+		I2C_BOARD_INFO(MXT540E_DEV_NAME, 0x4c),
+		.platform_data = &mxt540e_data,
+	},
+#endif
+#ifdef CONFIG_TOUCHSCREEN_ATMEL_MXT224_GC
+	{
+		I2C_BOARD_INFO(MXT224_DEV_NAME, 0x4a),
+		.platform_data = &mxt224_data,
+	},
+#endif
+};
+#endif
+#ifdef CONFIG_S3C_DEV_I2C4
+/* I2C4 */
+static struct i2c_board_info i2c_devs4[] __initdata = {
+};
+#endif
+
+#ifdef CONFIG_S3C_DEV_I2C5
+/* I2C5 */
+static struct i2c_board_info i2c_devs5[] __initdata = {
+#ifdef CONFIG_MFD_MAX8998
+	{
+		I2C_BOARD_INFO("lp3974", 0x66),
+		.platform_data = &s5pv310_max8998_info,
+	},
+#endif
+#ifdef CONFIG_MFD_MAX8997
+	{
+		I2C_BOARD_INFO("max8997", (0xcc >> 1)),
+		.platform_data = &exynos4_max8997_info,
+	},
+#endif
+};
+#endif
+#ifdef CONFIG_S3C_DEV_I2C6
+/* I2C6 */
+static struct i2c_board_info i2c_devs6[] __initdata = {
+#ifdef CONFIG_SND_SOC_U1_MC1N2
+	{
+		I2C_BOARD_INFO("mc1n2", 0x3a),	/* MC1N2 */
+		.platform_data = &mc1n2_pdata,
+	},
+#endif
+#ifdef CONFIG_EPEN_WACOM_G5SP
+	{
+		I2C_BOARD_INFO("wacom_g5sp_i2c", 0x56),
+		.platform_data = &p6_wacom_platform_data,
+	},
+#endif
+};
+#endif
+#ifdef CONFIG_S3C_DEV_I2C7
+static struct akm8975_platform_data akm8975_pdata = {
+	.gpio_data_ready_int = GPIO_MSENSE_INT,
+};
+
+/* I2C7 */
+static struct i2c_board_info i2c_devs7[] __initdata = {
+	{
+		I2C_BOARD_INFO("ak8975", 0x0C),
+		.platform_data = &akm8975_pdata,
+	},
+#ifdef CONFIG_VIDEO_TVOUT
+	{
+		I2C_BOARD_INFO("s5p_ddc", (0x74 >> 1)),
+	},
+#endif
+};
+#endif
+#ifdef CONFIG_S3C_DEV_I2C8_EMUL
+static struct i2c_gpio_platform_data gpio_i2c_data8 = {
+	.sda_pin = GPIO_3_TOUCH_SDA,
+	.scl_pin = GPIO_3_TOUCH_SCL,
+};
+
+struct platform_device s3c_device_i2c8 = {
+	.name = "i2c-gpio",
+	.id = 8,
+	.dev.platform_data = &gpio_i2c_data8,
+};
+
+/* I2C8 */
+static struct i2c_board_info i2c_devs8_emul[] = {
+	{
+		I2C_BOARD_INFO("sec_touchkey", 0x20),
+	},
+};
+#endif
+
+#ifdef CONFIG_S3C_DEV_I2C9_EMUL
+static struct i2c_gpio_platform_data gpio_i2c_data9 = {
+	.sda_pin = GPIO_FUEL_SDA,
+	.scl_pin = GPIO_FUEL_SCL,
+};
+
+struct platform_device s3c_device_i2c9 = {
+	.name = "i2c-gpio",
+	.id = 9,
+	.dev.platform_data = &gpio_i2c_data9,
+};
+
+#ifdef CONFIG_BATTERY_MAX17042_FUELGAUGE_U1
+
+struct max17042_reg_data max17042_init_data[] = {
+	{ MAX17042_REG_CGAIN,		0x00,	0x00 },
+	{ MAX17042_REG_MISCCFG,		0x03,	0x00 },
+	{ MAX17042_REG_LEARNCFG,	0x07,	0x00 },
+	/* RCOMP: 0x0050 2011.02.29 from MAXIM */
+	{ MAX17042_REG_RCOMP,		0x50,	0x00 },
+};
+
+struct max17042_reg_data max17042_alert_init_data[] = {
+#ifdef CONFIG_MACH_Q1_BD
+	/* SALRT Threshold setting to 1% wake lock */
+	{ MAX17042_REG_SALRT_TH,	0x01,	0xFF },
+#elif defined(CONFIG_TARGET_LOCALE_KOR)
+	/* SALRT Threshold setting to 1% wake lock */
+	{ MAX17042_REG_SALRT_TH,	0x01,	0xFF },
+#else
+	/* SALRT Threshold setting to 2% => 1% wake lock */
+	{ MAX17042_REG_SALRT_TH,	0x02,	0xFF },
+#endif
+	/* VALRT Threshold setting (disable) */
+	{ MAX17042_REG_VALRT_TH,	0x00,	0xFF },
+	/* TALRT Threshold setting (disable) */
+	{ MAX17042_REG_TALRT_TH,	0x80,	0x7F },
+};
+
+bool max17042_is_low_batt(void)
+{
+	struct power_supply *psy = power_supply_get_by_name("battery");
+	union power_supply_propval value;
+
+	if (!psy) {
+		pr_err("%s: fail to get battery ps\n", __func__);
+		return -ENODEV;
+	}
+
+	if (!(psy->get_property(psy, POWER_SUPPLY_PROP_CAPACITY, &value)))
+		if (value.intval > SEC_BATTERY_SOC_3_6)
+			return false;
+
+	return true;
+}
+EXPORT_SYMBOL(max17042_is_low_batt);
+
+static int max17042_low_batt_cb(void)
+{
+	struct power_supply *psy = power_supply_get_by_name("battery");
+	union power_supply_propval value;
+
+	if (!psy) {
+		pr_err("%s: fail to get battery ps\n", __func__);
+		return -ENODEV;
+	}
+
+	value.intval = POWER_SUPPLY_CAPACITY_LEVEL_CRITICAL;
+	return psy->set_property(psy, POWER_SUPPLY_PROP_CAPACITY_LEVEL, &value);
+}
+
+#ifdef RECAL_SOC_FOR_MAXIM
+static bool max17042_need_soc_recal(void)
+{
+	pr_info("%s: HW(0x%x)\n", __func__, system_rev);
+
+	if (system_rev >= NO_NEED_RECAL_SOC_HW_REV)
+		return false;
+	else
+		return true;
+}
+#endif
+
+static struct max17042_platform_data s5pv310_max17042_info = {
+	.low_batt_cb = max17042_low_batt_cb,
+	.init = max17042_init_data,
+	.init_size = sizeof(max17042_init_data),
+	.alert_init = max17042_alert_init_data,
+	.alert_init_size = sizeof(max17042_alert_init_data),
+	.alert_gpio = GPIO_FUEL_ALERT,
+	.alert_irq = 0,
+	.enable_current_sense = false,
+	.enable_gauging_temperature = true,
+#ifdef RECAL_SOC_FOR_MAXIM
+	.need_soc_recal = max17042_need_soc_recal,
+#endif
+};
+#endif	/* CONFIG_BATTERY_MAX17042_U1 */
+
+/* I2C9 */
+static struct i2c_board_info i2c_devs9_emul[] __initdata = {
+#ifdef CONFIG_BATTERY_MAX17042_FUELGAUGE_U1
+	{
+		I2C_BOARD_INFO("max17042", 0x36),
+		.platform_data	= &s5pv310_max17042_info,
+		.irq = IRQ_EINT(19),
+	},
+#endif
+#ifdef CONFIG_BATTERY_MAX17040
+	{
+		I2C_BOARD_INFO("max17040", 0x36),
+	},
+#endif
+};
+#endif
+
+#ifdef CONFIG_S3C_DEV_I2C10_EMUL
+static struct i2c_gpio_platform_data gpio_i2c_data10 __initdata = {
+	.sda_pin = GPIO_USB_SDA,
+	.scl_pin = GPIO_USB_SCL,
+};
+
+struct platform_device s3c_device_i2c10 = {
+	.name = "i2c-gpio",
+	.id = 10,
+	.dev.platform_data = &gpio_i2c_data10,
+};
+
+/* I2C10 */
+static struct fsa9480_platform_data fsa9480_info = {
+};
+
+static struct i2c_board_info i2c_devs10_emul[] __initdata = {
+	{
+		I2C_BOARD_INFO("fsa9480", 0x25),
+		.platform_data = &fsa9480_info,
+	},
+};
+#endif
+
+#ifdef CONFIG_S3C_DEV_I2C11_EMUL
+static struct i2c_gpio_platform_data gpio_i2c_data11 = {
+	.sda_pin = GPIO_PS_ALS_SDA,
+	.scl_pin = GPIO_PS_ALS_SCL,
+};
+
+struct platform_device s3c_device_i2c11 = {
+	.name = "i2c-gpio",
+	.id = 11,
+	.dev.platform_data = &gpio_i2c_data11,
+};
+
+/* I2C11 */
+#ifdef CONFIG_SENSORS_CM3663
+static int cm3663_ldo(bool on)
+{
+	struct regulator *regulator;
+
+	if (on) {
+		regulator = regulator_get(NULL, "vled");
+		if (IS_ERR(regulator))
+			return 0;
+		regulator_enable(regulator);
+		regulator_put(regulator);
+	} else {
+		regulator = regulator_get(NULL, "vled");
+		if (IS_ERR(regulator))
+			return 0;
+		if (regulator_is_enabled(regulator))
+			regulator_force_disable(regulator);
+		regulator_put(regulator);
+	}
+
+	return 0;
+}
+
+static struct cm3663_platform_data cm3663_pdata = {
+	.proximity_power = cm3663_ldo,
+};
+#ifdef CONFIG_SENSORS_PAS2M110
+static struct pas2m110_platform_data pas2m110_pdata = {
+	.proximity_power = cm3663_ldo,
+};
+#endif
+#endif
+#ifdef CONFIG_SENSORS_GP2A_ANALOG
+static int gp2a_power(bool on)
+{
+	struct regulator *regulator;
+
+	if (on) {
+		regulator = regulator_get(NULL, "vled");
+		if (IS_ERR(regulator))
+			return 0;
+		regulator_enable(regulator);
+		regulator_put(regulator);
+	} else {
+		regulator = regulator_get(NULL, "vled");
+		if (IS_ERR(regulator))
+			return 0;
+		if (regulator_is_enabled(regulator))
+			regulator_force_disable(regulator);
+		regulator_put(regulator);
+	}
+
+	return 0;
+}
+
+static struct gp2a_platform_data gp2a_pdata = {
+	.p_out = GPIO_PS_ALS_INT,
+	.power = gp2a_power,
+};
+#endif
+
+static struct i2c_board_info i2c_devs11_emul[] __initdata = {
+#ifdef CONFIG_MACH_U1_BD
+	{
+		I2C_BOARD_INFO("cm3663", 0x20),
+		.irq = GPIO_PS_ALS_INT,
+		.platform_data = &cm3663_pdata,
+	},
+#ifdef CONFIG_SENSORS_PAS2M110
+	{
+		I2C_BOARD_INFO("pas2m110", (0x88>>1)),
+		.irq = GPIO_PS_ALS_INT,
+		.platform_data = &pas2m110_pdata,
+	},
+#endif
+#endif
+#ifdef CONFIG_MACH_Q1_BD
+	{
+		I2C_BOARD_INFO("gp2a", (0x88 >> 1)),
+		.platform_data = &gp2a_pdata,
+	},
+#endif
+};
+#endif
+
+#ifdef CONFIG_S3C_DEV_I2C14_EMUL
+static struct i2c_gpio_platform_data i2c14_platdata = {
+	.sda_pin = GPIO_NFC_SDA,
+	.scl_pin = GPIO_NFC_SCL,
+	.udelay = 2,
+	.sda_is_open_drain = 0,
+	.scl_is_open_drain = 0,
+	.scl_is_output_only = 0,
+};
+
+static struct platform_device s3c_device_i2c14 = {
+	.name = "i2c-gpio",
+	.id = 14,
+	.dev.platform_data = &i2c14_platdata,
+};
+
+static struct pn544_i2c_platform_data pn544_pdata = {
+	.irq_gpio = GPIO_NFC_IRQ,
+	.ven_gpio = GPIO_NFC_EN,
+	.firm_gpio = GPIO_NFC_FIRM,
+};
+
+static struct i2c_board_info i2c_devs14[] __initdata = {
+	{
+		I2C_BOARD_INFO("pn544", 0x2b),
+		.irq = IRQ_EINT(15),
+		.platform_data = &pn544_pdata,
+	},
+};
+
+static unsigned int nfc_gpio_table[][4] = {
+	{GPIO_NFC_IRQ, S3C_GPIO_INPUT, GPIO_LEVEL_NONE, S3C_GPIO_PULL_DOWN},
+	{GPIO_NFC_EN, S3C_GPIO_OUTPUT, GPIO_LEVEL_LOW, S3C_GPIO_PULL_NONE},
+	{GPIO_NFC_FIRM, S3C_GPIO_OUTPUT, GPIO_LEVEL_LOW, S3C_GPIO_PULL_NONE},
+/*	{GPIO_NFC_SCL, S3C_GPIO_INPUT, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, */
+/*	{GPIO_NFC_SDA, S3C_GPIO_INPUT, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, */
+};
+
+void nfc_setup_gpio(void)
+{
+	/* s3c_config_gpio_alive_table(ARRAY_SIZE(nfc_gpio_table),
+	   nfc_gpio_table); */
+	int array_size = ARRAY_SIZE(nfc_gpio_table);
+	u32 i, gpio;
+	for (i = 0; i < array_size; i++) {
+		gpio = nfc_gpio_table[i][0];
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(nfc_gpio_table[i][1]));
+		s3c_gpio_setpull(gpio, nfc_gpio_table[i][3]);
+		if (nfc_gpio_table[i][2] != GPIO_LEVEL_NONE)
+			gpio_set_value(gpio, nfc_gpio_table[i][2]);
+	}
+
+	/* s3c_gpio_cfgpin(GPIO_NFC_IRQ, EINT_MODE); */
+	/* s3c_gpio_setpull(GPIO_NFC_IRQ, S3C_GPIO_PULL_DOWN); */
+}
+#endif
+
+#if defined(CONFIG_VIDEO_S5K5BAFX)
+static struct i2c_gpio_platform_data i2c12_platdata = {
+	.sda_pin = VT_CAM_SDA_18V,
+	.scl_pin = VT_CAM_SCL_18V,
+	.udelay = 2,		/* 250KHz */
+	.sda_is_open_drain = 0,
+	.scl_is_open_drain = 0,
+	.scl_is_output_only = 0,
+};
+
+static struct platform_device s3c_device_i2c12 = {
+	.name = "i2c-gpio",
+	.id = 12,
+	.dev.platform_data = &i2c12_platdata,
+};
+
+/* I2C12 */
+static struct i2c_board_info i2c_devs12_emul[] __initdata = {
+	/* need to work here */
+};
+#endif
+
+#ifdef CONFIG_FM_SI4709_MODULE
+static struct i2c_gpio_platform_data i2c16_platdata = {
+	.sda_pin		= GPIO_FM_SDA_28V,
+	.scl_pin		= GPIO_FM_SCL_28V,
+	.udelay			= 2,	/* 250KHz */
+	.sda_is_open_drain	= 0,
+	.scl_is_open_drain	= 0,
+	.scl_is_output_only	= 0,
+};
+
+static struct platform_device s3c_device_i2c16 = {
+	.name					= "i2c-gpio",
+	.id						= 16,
+	.dev.platform_data	= &i2c16_platdata,
+};
+
+static struct i2c_board_info i2c_devs16[] __initdata = {
+	{
+		I2C_BOARD_INFO("Si4709", (0x20 >> 1)),
+	},
+};
+#endif
+
+#endif
+
+#ifdef CONFIG_TOUCHSCREEN_S3C2410
+static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
+	.delay = 10000,
+	.presc = 49,
+	.oversampling_shift = 2,
+	.cal_x_max = 480,
+	.cal_y_max = 800,
+	.cal_param = {
+		33, -9156, 34720100, 14819, 57, -4234968, 65536,
+	},
+};
+#endif
+
+#ifdef	CONFIG_ISDBT_FC8100
+static struct	i2c_board_info i2c_devs17[]	__initdata = {
+	{
+		I2C_BOARD_INFO("isdbti2c", 0x77),
+	},
+};
+
+static struct i2c_gpio_platform_data i2c17_platdata = {
+	.sda_pin		= GPIO_ISDBT_SDA_28V,
+	.scl_pin		= GPIO_ISDBT_SCL_28V,
+	.udelay			= 3,	/*  kHz	*/
+	.sda_is_open_drain	= 0,
+	.scl_is_open_drain	= 0,
+	.scl_is_output_only = 0,
+};
+
+static struct platform_device s3c_device_i2c17 = {
+	.name			= "i2c-gpio",
+	.id				= 17,
+	.dev.platform_data	= &i2c17_platdata,
+};
+#endif
+
+
+#ifdef CONFIG_FB_S5P_MIPI_DSIM
+#ifdef CONFIG_FB_S5P_S6E8AA0
+/* for Geminus based on MIPI-DSI interface */
+static struct s3cfb_lcd s6e8aa0 = {
+	.name = "s6e8aa0",
+	.width = 800,
+	.height = 1280,
+	.p_width = 64,
+	.p_height = 106,
+	.bpp = 24,
+
+	.freq = 57,
+
+	/* minumun value is 0 except for wr_act time. */
+	.cpu_timing = {
+		.cs_setup = 0,
+		.wr_setup = 0,
+		.wr_act = 1,
+		.wr_hold = 0,
+	},
+
+	.timing = {
+		.h_fp = 10,
+		.h_bp = 10,
+		.h_sw = 10,
+		.v_fp = 13,
+		.v_fpe = 1,
+		.v_bp = 1,
+		.v_bpe = 1,
+		.v_sw = 2,
+		.cmd_allow_len = 11,	/*v_fp=stable_vfp + cmd_allow_len */
+		.stable_vfp = 2,
+	},
+
+	.polarity = {
+		.rise_vclk = 1,
+		.inv_hsync = 0,
+		.inv_vsync = 0,
+		.inv_vden = 0,
+	},
+};
+#endif
+static struct s3c_platform_fb fb_platform_data __initdata = {
+	.hw_ver		= 0x70,
+	.clk_name	= "fimd",
+	.nr_wins	= 5,
+#ifdef CONFIG_FB_S5P_DEFAULT_WINDOW
+	.default_win	= CONFIG_FB_S5P_DEFAULT_WINDOW,
+#else
+	.default_win = 0,
+#endif
+	.swap = FB_SWAP_HWORD | FB_SWAP_WORD,
+#ifdef CONFIG_FB_S5P_S6E8AA0
+	.lcd = &s6e8aa0
+#endif
+};
+
+#ifdef CONFIG_FB_S5P_S6E8AA0
+static int reset_lcd(void)
+{
+	int err;
+
+	/* Set GPY4[5] OUTPUT HIGH */
+	err = gpio_request(EXYNOS4_GPY4(5), "MLCD_RST");
+	if (err) {
+		printk(KERN_ERR "failed to request GPY4(5) for "
+		       "lcd reset control\n");
+		return -EPERM;
+	}
+
+	gpio_direction_output(EXYNOS4_GPY4(5), 1);
+	msleep(5);
+	gpio_set_value(EXYNOS4_GPY4(5), 0);
+	msleep(5);
+	gpio_set_value(EXYNOS4_GPY4(5), 1);
+	msleep(5);
+
+	gpio_free(EXYNOS4_GPY4(5));
+
+	return 0;
+}
+#endif
+static void lcd_cfg_gpio(void)
+{
+	/* MLCD_RST */
+	s3c_gpio_cfgpin(EXYNOS4_GPY4(5), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPY4(5), S3C_GPIO_PULL_NONE);
+
+	/* LCD_EN */
+	s3c_gpio_cfgpin(GPIO_LCD_EN, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_LCD_EN, S3C_GPIO_PULL_NONE);
+
+	return;
+}
+
+static int lcd_power_on(void *ld, int enable)
+{
+	struct regulator *regulator;
+	int err;
+
+	printk(KERN_INFO "%s : enable=%d\n", __func__, enable);
+
+	if (ld == NULL) {
+		printk(KERN_ERR "lcd device object is NULL.\n");
+		return -EPERM;
+	}
+
+	err = gpio_request(EXYNOS4_GPY4(5), "MLCD_RST");
+	if (err) {
+		printk(KERN_ERR "failed to request GPY4[5] for "
+		       "MLCD_RST control\n");
+		return -EPERM;
+	}
+
+	err = gpio_request(GPIO_LCD_EN, "LCD_EN");
+	if (err) {
+		printk(KERN_ERR "failed to request GPY3[1] for "
+				"LCD_EN control\n");
+		return -EPERM;
+	}
+
+	if (enable) {
+#ifdef CONFIG_MACH_Q1_BD
+		if (system_rev < 8) {
+			regulator = regulator_get(NULL, "vlcd_2.2v");
+			if (IS_ERR(regulator))
+				return 0;
+			regulator_enable(regulator);
+			regulator_put(regulator);
+		} else
+			gpio_set_value(GPIO_LCD_EN, GPIO_LEVEL_HIGH);
+#endif
+		regulator = regulator_get(NULL, "vlcd_3.0v");
+		if (IS_ERR(regulator))
+			return 0;
+		regulator_enable(regulator);
+		regulator_put(regulator);
+	} else {
+		regulator = regulator_get(NULL, "vlcd_3.0v");
+		if (IS_ERR(regulator))
+			return 0;
+		if (regulator_is_enabled(regulator))
+			regulator_force_disable(regulator);
+		regulator_put(regulator);
+#ifdef CONFIG_MACH_Q1_BD
+		if (system_rev < 8) {
+			regulator = regulator_get(NULL, "vlcd_2.2v");
+			if (IS_ERR(regulator))
+				return 0;
+			if (regulator_is_enabled(regulator))
+				regulator_force_disable(regulator);
+			regulator_put(regulator);
+		} else
+			gpio_set_value(GPIO_LCD_EN, GPIO_LEVEL_LOW);
+#endif
+
+		gpio_set_value(EXYNOS4_GPY4(5), 0);
+	}
+
+	/* Release GPIO */
+	gpio_free(EXYNOS4_GPY4(5));
+	gpio_free(GPIO_LCD_EN);
+
+	return 0;
+}
+
+static void __init mipi_fb_init(void)
+{
+	struct s5p_platform_dsim *dsim_pd = NULL;
+	struct mipi_ddi_platform_data *mipi_ddi_pd = NULL;
+	struct dsim_lcd_config *dsim_lcd_info = NULL;
+
+	/* set platform data */
+
+	/* gpio pad configuration for rgb and spi interface. */
+	lcd_cfg_gpio();
+
+	/*
+	 * register lcd panel data.
+	 */
+	printk(KERN_INFO "%s :: fb_platform_data.hw_ver = 0x%x\n",
+	       __func__, fb_platform_data.hw_ver);
+
+	fb_platform_data.mipi_is_enabled = 1;
+	fb_platform_data.interface_mode = FIMD_CPU_INTERFACE;
+
+	dsim_pd = (struct s5p_platform_dsim *)
+	    s5p_device_dsim.dev.platform_data;
+
+	dsim_pd->platform_rev = 1;
+
+	dsim_lcd_info = dsim_pd->dsim_lcd_info;
+
+#ifdef CONFIG_FB_S5P_S6E8AA0
+	dsim_lcd_info->lcd_panel_info = (void *)&s6e8aa0;
+
+	/* 483Mbps for Q1 */
+	dsim_pd->dsim_info->p = 4;
+	dsim_pd->dsim_info->m = 161;
+	dsim_pd->dsim_info->s = 1;
+#endif
+
+	mipi_ddi_pd = (struct mipi_ddi_platform_data *)
+	    dsim_lcd_info->mipi_ddi_pd;
+	mipi_ddi_pd->lcd_reset = reset_lcd;
+	mipi_ddi_pd->lcd_power_on = lcd_power_on;
+
+	platform_device_register(&s5p_device_dsim);
+
+	s3cfb_set_platdata(&fb_platform_data);
+
+	printk(KERN_INFO
+	       "platform data of %s lcd panel has been registered.\n",
+	       dsim_pd->lcd_panel_name);
+}
+#endif
+
+#ifdef CONFIG_ANDROID_PMEM
+static struct android_pmem_platform_data pmem_pdata = {
+	.name = "pmem",
+	.no_allocator = 1,
+	.cached = 0,
+	.start = 0,
+	.size = 0
+};
+
+static struct android_pmem_platform_data pmem_gpu1_pdata = {
+	.name = "pmem_gpu1",
+	.no_allocator = 1,
+	.cached = 0,
+	.start = 0,
+	.size = 0,
+};
+
+static struct platform_device pmem_device = {
+	.name = "android_pmem",
+	.id = 0,
+	.dev = {
+		.platform_data = &pmem_pdata},
+};
+
+static struct platform_device pmem_gpu1_device = {
+	.name = "android_pmem",
+	.id = 1,
+	.dev = {
+		.platform_data = &pmem_gpu1_pdata},
+};
+
+static void __init android_pmem_set_platdata(void)
+{
+#if defined(CONFIG_S5P_MEM_CMA)
+	pmem_pdata.size = CONFIG_ANDROID_PMEM_MEMSIZE_PMEM * SZ_1K;
+	pmem_gpu1_pdata.size = CONFIG_ANDROID_PMEM_MEMSIZE_PMEM_GPU1 * SZ_1K;
+#else
+	pmem_pdata.start = (u32) s5p_get_media_memory_bank(S5P_MDEV_PMEM, 0);
+	pmem_pdata.size = (u32) s5p_get_media_memsize_bank(S5P_MDEV_PMEM, 0);
+	pmem_gpu1_pdata.start =
+		(u32) s5p_get_media_memory_bank(S5P_MDEV_PMEM_GPU1, 0);
+	pmem_gpu1_pdata.size =
+		(u32) s5p_get_media_memsize_bank(S5P_MDEV_PMEM_GPU1, 0);
+#endif
+}
+#endif
+
+/* USB EHCI */
+#ifdef CONFIG_USB_EHCI_S5P
+static struct s5p_ehci_platdata smdkc210_ehci_pdata;
+
+static void __init smdkc210_ehci_init(void)
+{
+	struct s5p_ehci_platdata *pdata = &smdkc210_ehci_pdata;
+
+	s5p_ehci_set_platdata(pdata);
+}
+#endif
+
+#ifdef CONFIG_USB_OHCI_S5P
+static struct s5p_ohci_platdata smdkc210_ohci_pdata;
+
+static void __init smdkc210_ohci_init(void)
+{
+	struct s5p_ohci_platdata *pdata = &smdkc210_ohci_pdata;
+
+	s5p_ohci_set_platdata(pdata);
+}
+#endif
+
+/* USB GADGET */
+#ifdef CONFIG_USB_GADGET
+static struct s5p_usbgadget_platdata smdkc210_usbgadget_pdata;
+
+#include <linux/usb/android_composite.h>
+static void __init smdkc210_usbgadget_init(void)
+{
+	struct s5p_usbgadget_platdata *pdata = &smdkc210_usbgadget_pdata;
+
+#if defined(CONFIG_USB_ANDROID) || defined(CONFIG_USB_G_ANDROID)
+	struct android_usb_platform_data *android_pdata =
+		s3c_device_android_usb.dev.platform_data;
+	if (android_pdata) {
+		unsigned int newluns = 2;
+		printk(KERN_DEBUG "usb: %s: default luns=%d, new luns=%d\n",
+				__func__, android_pdata->nluns, newluns);
+		android_pdata->nluns = newluns;
+	} else {
+		printk(KERN_DEBUG "usb: %s android_pdata is not available\n",
+				__func__);
+	}
+#endif
+
+	s5p_usbgadget_set_platdata(pdata);
+
+	pdata = s3c_device_usbgadget.dev.platform_data;
+	if (pdata) {
+		/* Enables HS Transmitter pre-emphasis [20] */
+		pdata->phy_tune_mask = 0;
+		pdata->phy_tune_mask |= (0x1 << 20);
+		pdata->phy_tune |= (0x1 << 20);
+
+#if defined(CONFIG_MACH_U1_KOR_SKT) || defined(CONFIG_MACH_U1_KOR_KT)
+		/* Squelch Threshold Tune [13:11] (101 : -10%) */
+		pdata->phy_tune_mask |= (0x7 << 11);
+		pdata->phy_tune |= (0x5 << 11);
+
+		/* HS DC Voltage Level Adjustment [3:0] (1011 : +16%) */
+		pdata->phy_tune_mask |= 0xf;
+		pdata->phy_tune |= 0xb;
+#elif defined(CONFIG_MACH_U1_KOR_LGT)
+		/* Squelch Threshold Tune [13:11] (100 : -5%) */
+		pdata->phy_tune_mask |= (0x7 << 11);
+		pdata->phy_tune |= (0x4 << 11);
+
+		/* HS DC Voltage Level Adjustment [3:0] (1100 : +18%) */
+		pdata->phy_tune_mask |= 0xf;
+		pdata->phy_tune |= 0xc;
+#else
+		/* Squelch Threshold Tune [13:11] (101 : -10%) */
+		pdata->phy_tune_mask |= (0x7 << 11);
+		pdata->phy_tune |= (0x5 << 11);
+		/* HS DC Voltage Level Adjustment [3:0] (1011 : +16%) */
+		pdata->phy_tune_mask |= 0xf;
+		pdata->phy_tune |= 0xb;
+#endif
+
+		printk(KERN_DEBUG "usb: %s tune_mask=0x%x, tune=0x%x\n",
+			__func__, pdata->phy_tune_mask, pdata->phy_tune);
+	}
+}
+#endif
+
+#ifdef CONFIG_BUSFREQ_OPP
+/* BUSFREQ to control memory/bus*/
+static struct device_domain busfreq;
+
+static struct platform_device exynos4_busfreq = {
+	.id = -1,
+	.name = "exynos-busfreq",
+};
+#endif
+
+#ifdef CONFIG_SEC_WATCHDOG_RESET
+static struct platform_device watchdog_reset_device = {
+	.name = "watchdog-reset",
+	.id = -1,
+};
+#endif
+
+static struct platform_device *smdkc210_devices[] __initdata = {
+#ifdef CONFIG_SEC_WATCHDOG_RESET
+	&watchdog_reset_device,
+#endif
+	&exynos4_device_pd[PD_MFC],
+	&exynos4_device_pd[PD_G3D],
+	&exynos4_device_pd[PD_LCD0],
+	&exynos4_device_pd[PD_LCD1],
+	&exynos4_device_pd[PD_CAM],
+	&exynos4_device_pd[PD_TV],
+	&exynos4_device_pd[PD_GPS],
+
+#ifdef CONFIG_BATTERY_SAMSUNG
+	&samsung_device_battery,
+#endif
+#ifdef CONFIG_FB_S5P
+	&s3c_device_fb,
+#endif
+
+#ifdef CONFIG_I2C_S3C2410
+	&s3c_device_i2c0,
+#if defined(CONFIG_S3C_DEV_I2C1)
+	&s3c_device_i2c1,
+#endif
+#if defined(CONFIG_S3C_DEV_I2C2)
+	&s3c_device_i2c2,
+#endif
+#if defined(CONFIG_S3C_DEV_I2C3)
+	&s3c_device_i2c3,
+#endif
+#if defined(CONFIG_S3C_DEV_I2C4)
+	&s3c_device_i2c4,
+#endif
+#if defined(CONFIG_S3C_DEV_I2C5)
+	&s3c_device_i2c5,
+#endif
+#if defined(CONFIG_S3C_DEV_I2C6)
+	&s3c_device_i2c6,
+#endif
+#if defined(CONFIG_S3C_DEV_I2C7)
+	&s3c_device_i2c7,
+#endif
+#if defined(CONFIG_S3C_DEV_I2C8_EMUL)
+	&s3c_device_i2c8,
+#endif
+#if defined(CONFIG_S3C_DEV_I2C9_EMUL)
+	&s3c_device_i2c9,
+#endif
+#if defined(CONFIG_S3C_DEV_I2C10_EMUL)
+	&s3c_device_i2c10,
+#endif
+#if defined(CONFIG_S3C_DEV_I2C11_EMUL)
+	&s3c_device_i2c11,
+#endif
+#if defined(CONFIG_S3C_DEV_I2C14_EMUL)
+	&s3c_device_i2c14,
+#endif
+#if defined(CONFIG_VIDEO_S5K5BAFX)
+	&s3c_device_i2c12,
+#endif
+#ifdef CONFIG_SAMSUNG_MHL
+		&s3c_device_i2c15,
+#endif
+#ifdef CONFIG_FM_SI4709_MODULE
+	&s3c_device_i2c16,
+#endif
+#ifdef	CONFIG_ISDBT_FC8100
+	&s3c_device_i2c17,	/* ISDBT */
+#endif
+#if defined(CONFIG_SMB136_CHARGER_Q1) || defined(CONFIG_SMB328_CHARGER)
+	&s3c_device_i2c19,	/* SMB136, SMB328 */
+#endif
+#endif
+
+	/* consumer driver should resume after resuming i2c drivers */
+	&u1_regulator_consumer,
+
+#ifdef CONFIG_EXYNOS4_DEV_MSHC
+	&s3c_device_mshci,
+#endif
+
+#ifdef CONFIG_S3C_DEV_HSMMC
+	&s3c_device_hsmmc0,
+#endif
+
+#ifdef CONFIG_S3C_DEV_HSMMC1
+	&s3c_device_hsmmc1,
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC2
+	&s3c_device_hsmmc2,
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC3
+	&s3c_device_hsmmc3,
+#endif
+#ifdef CONFIG_S3C_ADC
+	&s3c_device_adc,
+#endif
+#ifdef CONFIG_TOUCHSCREEN_S3C2410
+#ifdef CONFIG_S3C_DEV_ADC
+	&s3c_device_ts,
+#elif CONFIG_S3C_DEV_ADC1
+	&s3c_device_ts1,
+#endif
+#endif
+	&u1_keypad,
+	&s3c_device_rtc,
+	&s3c_device_wdt,
+#ifdef CONFIG_SND_SAMSUNG_AC97
+	&exynos_device_ac97,
+#endif
+#ifdef CONFIG_SND_SAMSUNG_I2S
+	&exynos_device_i2s0,
+#endif
+#ifdef CONFIG_SND_SAMSUNG_PCM
+	&exynos_device_pcm0,
+#endif
+#if defined(CONFIG_SND_SAMSUNG_RP) || defined(CONFIG_SND_SAMSUNG_ALP)
+	&exynos_device_srp,
+#endif
+#ifdef CONFIG_SND_SAMSUNG_SPDIF
+	&exynos_device_spdif,
+#endif
+#ifdef CONFIG_BATTERY_SEC_U1
+	&sec_device_battery,
+#endif
+#ifdef	CONFIG_LEDS_MAX8997
+	&sec_device_leds_max8997,
+#endif
+#ifdef CONFIG_CHARGER_MAX8922_U1
+	&max8922_device_charger,
+#endif
+#ifdef CONFIG_S5P_SYSTEM_MMU
+	&SYSMMU_PLATDEV(fimc0),
+	&SYSMMU_PLATDEV(fimc1),
+	&SYSMMU_PLATDEV(fimc2),
+	&SYSMMU_PLATDEV(fimc3),
+	&SYSMMU_PLATDEV(2d),
+	&SYSMMU_PLATDEV(tv),
+	&SYSMMU_PLATDEV(mfc_l),
+	&SYSMMU_PLATDEV(mfc_r),
+#endif
+#ifdef CONFIG_ION_EXYNOS
+	&exynos_device_ion,
+#endif
+
+	&samsung_asoc_dma,
+#ifndef CONFIG_SND_SOC_SAMSUNG_USE_DMA_WRAPPER
+	&samsung_asoc_idma,
+#endif
+
+#ifdef CONFIG_S3C64XX_DEV_SPI
+	&exynos_device_spi0,
+#endif
+
+/* mainline fimd */
+#ifdef CONFIG_FB_S3C
+	&s5p_device_fimd0,
+#if defined(CONFIG_LCD_AMS369FG06)
+	&s3c_device_spi_gpio,
+#elif defined(CONFIG_LCD_WA101S)
+	&smdkc210_lcd_wa101s,
+#elif defined(CONFIG_LCD_LTE480WV)
+	&smdkc210_lcd_lte480wv,
+#endif
+#endif
+/* legacy fimd */
+#ifdef CONFIG_FB_S5P_AMS369FG06
+	&s3c_device_spi_gpio,
+#endif
+#ifdef CONFIG_FB_S5P_LD9040
+	&ld9040_spi_gpio,
+#endif
+#ifdef CONFIG_FB_S5P_NT35560
+	&nt35560_spi_gpio,
+#endif
+#ifdef CONFIG_FB_S5P_MDNIE
+	&mdnie_device,
+#endif
+#ifdef CONFIG_VIDEO_TVOUT
+	&s5p_device_tvout,
+	&s5p_device_cec,
+	&s5p_device_hpd,
+#endif
+#ifdef CONFIG_ANDROID_PMEM
+	&pmem_device,
+	&pmem_gpu1_device,
+#endif
+#ifdef CONFIG_VIDEO_FIMC
+	&s3c_device_fimc0,
+	&s3c_device_fimc1,
+	&s3c_device_fimc2,
+	&s3c_device_fimc3,
+#ifdef CONFIG_VIDEO_FIMC_MIPI
+	&s3c_device_csis0,
+	&s3c_device_csis1,
+#endif
+#endif
+#if defined(CONFIG_VIDEO_MFC5X) || defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC)
+	&s5p_device_mfc,
+#endif
+#ifdef CONFIG_VIDEO_FIMG2D
+	&s5p_device_fimg2d,
+#endif
+#ifdef CONFIG_VIDEO_JPEG
+	&s5p_device_jpeg,
+#endif
+#if defined CONFIG_USB_EHCI_S5P && !defined CONFIG_LINK_DEVICE_HSIC
+	&s5p_device_ehci,
+#endif
+#ifdef CONFIG_USB_OHCI_S5P
+	&s5p_device_ohci,
+#endif
+#ifdef CONFIG_USB_GADGET
+	&s3c_device_usbgadget,
+#endif
+#ifdef CONFIG_USB_ANDROID_RNDIS
+	&s3c_device_rndis,
+#endif
+#if defined(CONFIG_USB_ANDROID) || defined(CONFIG_USB_G_ANDROID)
+	&s3c_device_android_usb,
+	&s3c_device_usb_mass_storage,
+#endif
+#ifdef CONFIG_HAVE_PWM
+	&s3c_device_timer[0],
+	&s3c_device_timer[1],
+	&s3c_device_timer[2],
+	&s3c_device_timer[3],
+#endif
+#ifdef CONFIG_VIDEO_TSI
+	&s3c_device_tsi,
+#endif
+#ifdef CONFIG_EXYNOS4_SETUP_THERMAL
+	&s5p_device_tmu,
+#endif
+#ifdef CONFIG_BT_BCM4330
+	&bcm4330_bluetooth_device,
+#endif
+#ifdef CONFIG_S5P_DEV_ACE
+	&s5p_device_ace,
+#endif
+#ifdef CONFIG_BUSFREQ_OPP
+	&exynos4_busfreq,
+#endif
+#ifdef CONFIG_SEC_DEV_JACK
+	&sec_device_jack,
+#endif
+#ifdef CONFIG_USB_HOST_NOTIFY
+	&host_notifier_device,
+#endif
+	&s3c_device_usb_otghcd,
+};
+
+#ifdef CONFIG_EXYNOS4_SETUP_THERMAL
+/* below temperature base on the celcius degree */
+struct s5p_platform_tmu u1_tmu_data __initdata = {
+	.ts = {
+		.stop_1st_throttle  = 61,
+		.start_1st_throttle = 64,
+		.stop_2nd_throttle  = 87,
+		.start_2nd_throttle = 103,
+		.start_tripping     = 110,
+		.start_emergency    = 120,
+		.stop_mem_throttle  = 80,
+		.start_mem_throttle = 85,
+	},
+	.cpufreq = {
+		.limit_1st_throttle  = 800000, /* 800MHz in KHz order */
+		.limit_2nd_throttle  = 200000, /* 200MHz in KHz order */
+	},
+};
+#endif
+
+#if defined CONFIG_USB_EHCI_S5P && defined CONFIG_LINK_DEVICE_HSIC
+static int __init s5p_ehci_device_initcall(void)
+{
+	return platform_device_register(&s5p_device_ehci);
+}
+late_initcall(s5p_ehci_device_initcall);
+#endif
+
+#if defined(CONFIG_VIDEO_TVOUT)
+static struct s5p_platform_hpd hdmi_hpd_data __initdata = {
+
+};
+
+static struct s5p_platform_cec hdmi_cec_data __initdata = {
+
+};
+#endif
+
+#if defined(CONFIG_S5P_MEM_CMA)
+static void __init exynos4_cma_region_reserve(struct cma_region *regions_normal,
+					      struct cma_region *regions_secure)
+{
+	struct cma_region *reg;
+	size_t size_secure = 0, align_secure = 0;
+	phys_addr_t paddr = 0;
+
+	for (reg = regions_normal; reg->size != 0; reg++) {
+		if (WARN_ON(cma_early_region_register(reg)))
+			continue;
+
+		if ((reg->alignment & (reg->alignment - 1)) || reg->reserved)
+			continue;
+
+		if (reg->start) {
+			if (!memblock_is_region_reserved(reg->start, reg->size)
+			    && memblock_reserve(reg->start, reg->size) >= 0)
+				reg->reserved = 1;
+		} else {
+			paddr = __memblock_alloc_base(reg->size, reg->alignment,
+						     MEMBLOCK_ALLOC_ACCESSIBLE);
+			if (paddr) {
+				reg->start = paddr;
+				reg->reserved = 1;
+			}
+		}
+	}
+
+	if (regions_secure && regions_secure->size) {
+		for (reg = regions_secure; reg->size != 0; reg++)
+			size_secure += reg->size;
+
+		reg--;
+
+		align_secure = reg->alignment;
+		BUG_ON(align_secure & (align_secure - 1));
+
+		paddr -= size_secure;
+		paddr &= ~(align_secure - 1);
+
+		if (!memblock_reserve(paddr, size_secure)) {
+			do {
+				reg->start = paddr;
+				reg->reserved = 1;
+				paddr += reg->size;
+
+				if (WARN_ON(cma_early_region_register(reg)))
+					memblock_free(reg->start, reg->size);
+			} while (reg-- != regions_secure);
+		}
+	}
+}
+
+static void __init exynos4_reserve_mem(void)
+{
+	static struct cma_region regions[] = {
+#ifdef CONFIG_ANDROID_PMEM_MEMSIZE_PMEM
+		{
+			.name = "pmem",
+			.size = CONFIG_ANDROID_PMEM_MEMSIZE_PMEM * SZ_1K,
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_ANDROID_PMEM_MEMSIZE_PMEM_GPU1
+		{
+			.name = "pmem_gpu1",
+			.size = CONFIG_ANDROID_PMEM_MEMSIZE_PMEM_GPU1 * SZ_1K,
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMD
+		{
+			.name = "fimd",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMD * SZ_1K,
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC0
+		{
+			.name = "fimc0",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC0 * SZ_1K,
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC1
+		{
+			.name = "fimc1",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC1 * SZ_1K,
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC2
+		{
+			.name = "fimc2",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC2 * SZ_1K,
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC3
+		{
+			.name = "fimc3",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC3 * SZ_1K,
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC1
+		{
+			.name = "mfc1",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC1 * SZ_1K,
+			{
+				.alignment = 1 << 17,
+			},
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC0
+		{
+			.name = "mfc0",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC0 * SZ_1K,
+			{
+				.alignment = 1 << 17,
+			},
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC
+		{
+			.name = "mfc",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC * SZ_1K,
+			{
+				.alignment = 1 << 17,
+			},
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_JPEG
+		{
+			.name = "jpeg",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_JPEG * SZ_1K,
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_AUDIO_SAMSUNG_MEMSIZE_SRP
+		{
+			.name = "srp",
+			.size = CONFIG_AUDIO_SAMSUNG_MEMSIZE_SRP * SZ_1K,
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMG2D
+		{
+			.name = "fimg2d",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMG2D * SZ_1K,
+			.start = 0,
+		},
+#endif
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_TVOUT
+		{
+			.name = "tvout",
+			.size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_TVOUT * SZ_1K,
+			.start = 0,
+		},
+#endif
+		{
+			.size = 0,
+		},
+	};
+
+	static const char map[] __initconst =
+		"android_pmem.0=pmem;android_pmem.1=pmem_gpu1;"
+		"s3cfb.0=fimd;exynos4-fb.0=fimd;"
+		"s3c-fimc.0=fimc0;s3c-fimc.1=fimc1;s3c-fimc.2=fimc2;"
+		"exynos4210-fimc.0=fimc0;exynos4210-fimc.1=fimc1;exynos4210-fimc.2=fimc2;exynos4210-fimc3=fimc3;"
+#ifdef CONFIG_VIDEO_MFC5X
+		"s3c-mfc/A=mfc0,mfc-secure;"
+		"s3c-mfc/B=mfc1,mfc-normal;"
+		"s3c-mfc/AB=mfc;"
+#endif
+		"samsung-rp=srp;"
+		"s5p-jpeg=jpeg;"
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_IS
+		"exynos4-fimc-is=fimc_is;"
+#endif
+		"s5p-fimg2d=fimg2d;"
+		"s5p-tvout=tvout";
+
+	cma_set_defaults(regions, map);
+	exynos4_cma_region_reserve(regions, NULL);
+
+}
+#endif
+
+static void __init exynos_sysmmu_init(void)
+{
+	ASSIGN_SYSMMU_POWERDOMAIN(fimc0, &exynos4_device_pd[PD_CAM].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(fimc1, &exynos4_device_pd[PD_CAM].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(fimc2, &exynos4_device_pd[PD_CAM].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(fimc3, &exynos4_device_pd[PD_CAM].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(jpeg, &exynos4_device_pd[PD_CAM].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(fimd0, &exynos4_device_pd[PD_LCD0].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(2d, &exynos4_device_pd[PD_LCD0].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(rot, &exynos4_device_pd[PD_LCD0].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(tv, &exynos4_device_pd[PD_TV].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(mfc_l, &exynos4_device_pd[PD_MFC].dev);
+	ASSIGN_SYSMMU_POWERDOMAIN(mfc_r, &exynos4_device_pd[PD_MFC].dev);
+#if defined CONFIG_VIDEO_FIMC
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc0).dev, &s3c_device_fimc0.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc1).dev, &s3c_device_fimc1.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc2).dev, &s3c_device_fimc2.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc3).dev, &s3c_device_fimc3.dev);
+#elif defined CONFIG_VIDEO_SAMSUNG_S5P_FIMC
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc0).dev, &s5p_device_fimc0.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc1).dev, &s5p_device_fimc1.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc2).dev, &s5p_device_fimc2.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimc3).dev, &s5p_device_fimc3.dev);
+#endif
+#ifdef CONFIG_VIDEO_JPEG
+	sysmmu_set_owner(&SYSMMU_PLATDEV(jpeg).dev, &s5p_device_jpeg.dev);
+#endif
+#ifdef CONFIG_FB_S3C
+	sysmmu_set_owner(&SYSMMU_PLATDEV(fimd0).dev, &s5p_device_fimd0.dev);
+#endif
+#ifdef CONFIG_VIDEO_FIMG2D
+	sysmmu_set_owner(&SYSMMU_PLATDEV(2d).dev, &s5p_device_fimg2d.dev);
+#endif
+#ifdef CONFIG_VIDEO_TVOUT
+	sysmmu_set_owner(&SYSMMU_PLATDEV(tv).dev, &s5p_device_tvout.dev);
+#endif
+#if defined(CONFIG_VIDEO_MFC5X) || defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC)
+	sysmmu_set_owner(&SYSMMU_PLATDEV(mfc_l).dev, &s5p_device_mfc.dev);
+	sysmmu_set_owner(&SYSMMU_PLATDEV(mfc_r).dev, &s5p_device_mfc.dev);
+#endif
+}
+
+static void __init smdkc210_map_io(void)
+{
+	clk_xusbxti.rate = 24000000;
+
+	s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+	s3c24xx_init_clocks(24000000);
+	s3c24xx_init_uarts(smdkc210_uartcfgs, ARRAY_SIZE(smdkc210_uartcfgs));
+
+#if defined(CONFIG_S5P_MEM_CMA)
+	exynos4_reserve_mem();
+#else
+	s5p_reserve_mem(S5P_RANGE_MFC);
+#endif
+
+	/* as soon as INFORM3 is visible, sec_debug is ready to run */
+	sec_debug_init();
+}
+
+static void __init universal_tsp_init(void)
+{
+	int gpio;
+
+	/* TSP_LDO_ON: XMDMADDR_11 */
+	gpio = GPIO_TSP_LDO_ON;
+	gpio_request(gpio, "TSP_LDO_ON");
+	gpio_direction_output(gpio, 1);
+	gpio_export(gpio, 0);
+
+	/* TSP_INT: XMDMADDR_7 */
+	gpio = GPIO_TSP_INT;
+	gpio_request(gpio, "TSP_INT");
+	s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
+	s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+	i2c_devs3[0].irq = gpio_to_irq(gpio);
+
+	printk(KERN_INFO "%s touch : %d\n", __func__, i2c_devs3[0].irq);
+#ifdef CONFIG_MACH_Q1_BD
+	gpio_request(GPIO_TSP_SDA, "TSP_SDA");
+	gpio_request(GPIO_TSP_SCL, "TSP_SCL");
+	gpio_request(GPIO_OLED_DET, "OLED_DET");
+#endif
+}
+
+#ifdef CONFIG_EPEN_WACOM_G5SP
+static int p6_wacom_init_hw(void)
+{
+	int gpio;
+	int ret;
+
+	gpio = GPIO_PEN_RESET;
+	ret = gpio_request(gpio, "PEN_RESET");
+	s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT);
+	gpio_direction_output(gpio, 1);
+
+	gpio = GPIO_PEN_SLP;
+	ret = gpio_request(gpio, "PEN_SLP");
+	s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0x1));
+	s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+	gpio_direction_output(gpio, 0);
+
+	gpio = GPIO_PEN_PDCT;
+	ret = gpio_request(gpio, "PEN_PDCT");
+	s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0x0));
+	s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+	gpio_direction_input(gpio);
+
+	gpio = GPIO_PEN_IRQ;
+	ret = gpio_request(gpio, "PEN_IRQ");
+	s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+	s5p_register_gpio_interrupt(gpio);
+	gpio_direction_input(gpio);
+
+	i2c_devs6[1].irq = gpio_to_irq(gpio);
+	irq_set_irq_type(i2c_devs6[1].irq, IRQ_TYPE_EDGE_RISING);
+
+	s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
+
+	return 0;
+}
+
+static int __init p6_wacom_init(void)
+{
+	p6_wacom_init_hw();
+	printk(KERN_INFO "[E-PEN] : wacom IC initialized.\n");
+	return 0;
+}
+#endif
+
+static void __init smdkc210_machine_init(void)
+{
+#ifdef CONFIG_S3C64XX_DEV_SPI
+	struct clk *sclk = NULL;
+	struct clk *prnt = NULL;
+	struct device *spi0_dev = &exynos_device_spi0.dev;
+#endif
+	/* initialise the gpios */
+	u1_config_gpio_table();
+	exynos4_sleep_gpio_table_set = u1_config_sleep_gpio_table;
+
+#ifdef CONFIG_I2C_S3C2410
+	s3c_i2c0_set_platdata(NULL);
+	i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
+
+#ifdef CONFIG_S3C_DEV_I2C1
+	s3c_i2c1_set_platdata(NULL);
+	i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
+#endif
+#ifdef CONFIG_S3C_DEV_I2C2
+	s3c_i2c2_set_platdata(NULL);
+	i2c_register_board_info(2, i2c_devs2, ARRAY_SIZE(i2c_devs2));
+#endif
+#ifdef CONFIG_S3C_DEV_I2C3
+	universal_tsp_init();
+	s3c_i2c3_set_platdata(NULL);
+	i2c_register_board_info(3, i2c_devs3, ARRAY_SIZE(i2c_devs3));
+#endif
+#ifdef CONFIG_S3C_DEV_I2C4
+	s3c_i2c4_set_platdata(NULL);
+	i2c_register_board_info(4, i2c_devs4, ARRAY_SIZE(i2c_devs4));
+#endif
+#ifdef CONFIG_S3C_DEV_I2C5
+	s3c_i2c5_set_platdata(NULL);
+	s3c_gpio_cfgpin(GPIO_PMIC_IRQ, S3C_GPIO_SFN(0xF));
+	s3c_gpio_setpull(GPIO_PMIC_IRQ, S3C_GPIO_PULL_NONE);
+	i2c_devs5[0].irq = gpio_to_irq(GPIO_PMIC_IRQ);
+	i2c_register_board_info(5, i2c_devs5, ARRAY_SIZE(i2c_devs5));
+#endif
+#ifdef CONFIG_S3C_DEV_I2C6
+#ifdef CONFIG_EPEN_WACOM_G5SP
+	p6_wacom_init();
+#endif
+	s3c_i2c6_set_platdata(NULL);
+	i2c_register_board_info(6, i2c_devs6, ARRAY_SIZE(i2c_devs6));
+#endif
+#ifdef CONFIG_S3C_DEV_I2C7
+	s3c_i2c7_set_platdata(NULL);
+	i2c_register_board_info(7, i2c_devs7, ARRAY_SIZE(i2c_devs7));
+#endif
+#ifdef CONFIG_SAMSUNG_MHL
+	printk(KERN_INFO "%s() register sii9234 driver\n", __func__);
+
+	i2c_register_board_info(15, tuna_i2c15_boardinfo,
+			ARRAY_SIZE(tuna_i2c15_boardinfo));
+#endif
+#ifdef CONFIG_S3C_DEV_I2C8_EMUL
+	i2c_register_board_info(8, i2c_devs8_emul, ARRAY_SIZE(i2c_devs8_emul));
+	gpio_request(GPIO_3_TOUCH_INT, "sec_touchkey");
+	s5p_register_gpio_interrupt(GPIO_3_TOUCH_INT);
+
+#endif
+#ifdef CONFIG_S3C_DEV_I2C9_EMUL
+	i2c_register_board_info(9, i2c_devs9_emul, ARRAY_SIZE(i2c_devs9_emul));
+#endif
+#ifdef CONFIG_S3C_DEV_I2C10_EMUL
+	i2c_register_board_info(10, i2c_devs10_emul,
+				ARRAY_SIZE(i2c_devs10_emul));
+#endif
+#ifdef CONFIG_S3C_DEV_I2C11_EMUL
+	s3c_gpio_setpull(GPIO_PS_ALS_INT, S3C_GPIO_PULL_NONE);
+	i2c_register_board_info(11, i2c_devs11_emul,
+				ARRAY_SIZE(i2c_devs11_emul));
+#endif
+#ifdef CONFIG_S3C_DEV_I2C14_EMUL
+	nfc_setup_gpio();
+	i2c_register_board_info(14, i2c_devs14, ARRAY_SIZE(i2c_devs14));
+#endif
+#if defined(CONFIG_VIDEO_S5K5BAFX)
+	i2c_register_board_info(12, i2c_devs12_emul,
+				ARRAY_SIZE(i2c_devs12_emul));
+#endif
+#ifdef CONFIG_FM_SI4709_MODULE
+	i2c_register_board_info(16, i2c_devs16, ARRAY_SIZE(i2c_devs16));
+#endif
+#ifdef	CONFIG_ISDBT_FC8100
+	i2c_register_board_info(17, i2c_devs17, ARRAY_SIZE(i2c_devs17));
+#endif
+
+#if defined(CONFIG_SMB136_CHARGER_Q1) || defined(CONFIG_SMB328_CHARGER)
+	i2c_register_board_info(19, i2c_devs19_emul,
+				ARRAY_SIZE(i2c_devs19_emul));
+#endif
+#endif
+
+	/* 400 kHz for initialization of MMC Card  */
+	__raw_writel((__raw_readl(EXYNOS4_CLKDIV_FSYS3) & 0xfffffff0)
+		     | 0x9, EXYNOS4_CLKDIV_FSYS3);
+	__raw_writel((__raw_readl(EXYNOS4_CLKDIV_FSYS2) & 0xfff0fff0)
+		     | 0x80008, EXYNOS4_CLKDIV_FSYS2);
+	__raw_writel((__raw_readl(EXYNOS4_CLKDIV_FSYS1) & 0xfff0fff0)
+		     | 0x90009, EXYNOS4_CLKDIV_FSYS1);
+
+#ifdef CONFIG_S3C_DEV_HSMMC
+	s3c_sdhci0_set_platdata(&exynos4_hsmmc0_pdata);
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC1
+	s3c_sdhci1_set_platdata(&exynos4_hsmmc1_pdata);
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC2
+	s3c_sdhci2_set_platdata(&exynos4_hsmmc2_pdata);
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC3
+	s3c_sdhci3_set_platdata(&exynos4_hsmmc3_pdata);
+#endif
+
+#ifdef CONFIG_EXYNOS4_DEV_MSHC
+	s3c_mshci_set_platdata(&exynos4_mshc_pdata);
+#endif
+
+#ifdef CONFIG_FB_S3C
+#ifdef CONFIG_LCD_AMS369FG06
+	spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
+#endif
+	s5p_fimd0_set_platdata(&smdkc210_lcd0_pdata);
+#ifdef CONFIG_EXYNOS_DEV_PD
+	s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
+#endif
+#endif
+
+#ifdef CONFIG_FB_S5P
+#ifdef CONFIG_FB_S5P_AMS369FG06
+	spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
+	s3cfb_set_platdata(&ams369fg06_data);
+#else
+	s3cfb_set_platdata(NULL);
+#endif
+#ifdef CONFIG_EXYNOS_DEV_PD
+	s3c_device_fb.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
+#endif
+#endif
+
+#ifdef CONFIG_EXYNOS_DEV_PD
+#ifdef CONFIG_VIDEO_JPEG
+	s5p_device_jpeg.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+#endif
+#endif
+#if defined(CONFIG_VIDEO_TVOUT)
+	s5p_hdmi_hpd_set_platdata(&hdmi_hpd_data);
+	s5p_hdmi_cec_set_platdata(&hdmi_cec_data);
+#ifdef CONFIG_EXYNOS_DEV_PD
+	s5p_device_tvout.dev.parent = &exynos4_device_pd[PD_TV].dev;
+#endif
+#endif
+#ifdef CONFIG_TOUCHSCREEN_S3C2410
+#ifdef CONFIG_S3C_DEV_ADC
+	s3c24xx_ts_set_platdata(&s3c_ts_platform);
+#endif
+#ifdef CONFIG_S3C_DEV_ADC1
+	s3c24xx_ts1_set_platdata(&s3c_ts_platform);
+#endif
+#endif
+#ifdef CONFIG_ANDROID_PMEM
+	android_pmem_set_platdata();
+#endif
+#ifdef CONFIG_VIDEO_FIMC
+	/* fimc */
+	s3c_fimc0_set_platdata(&fimc_plat);
+	s3c_fimc1_set_platdata(NULL);
+	s3c_fimc2_set_platdata(&fimc_plat);
+	s3c_fimc3_set_platdata(NULL);
+#ifdef CONFIG_VIDEO_FIMC_MIPI
+	s3c_csis0_set_platdata(NULL);
+	s3c_csis1_set_platdata(NULL);
+#endif
+#endif
+
+#ifdef CONFIG_EXYNOS_DEV_PD
+#ifdef CONFIG_VIDEO_FIMC
+	s3c_device_fimc0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+	s3c_device_fimc1.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+	s3c_device_fimc2.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+	s3c_device_fimc3.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+#endif
+#endif
+#ifdef CONFIG_ION_EXYNOS
+	exynos_ion_set_platdata();
+#endif
+
+#ifdef CONFIG_EXYNOS4_SETUP_THERMAL
+	s5p_tmu_set_platdata(&u1_tmu_data);
+#endif
+
+#if defined(CONFIG_VIDEO_MFC5X) || defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC)
+#ifdef CONFIG_EXYNOS_DEV_PD
+	s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
+#endif
+#endif
+
+#if defined(CONFIG_VIDEO_MFC5X)
+	exynos4_mfc_setup_clock(&s5p_device_mfc.dev, 200 * MHZ);
+#endif
+#if defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC)
+	dev_set_name(&s5p_device_mfc.dev, "s3c-mfc");
+	clk_add_alias("mfc", "s5p-mfc", "mfc", &s5p_device_mfc.dev);
+	s5p_mfc_setname(&s5p_device_mfc, "s5p-mfc");
+#endif
+
+#ifdef CONFIG_VIDEO_FIMG2D
+	s5p_fimg2d_set_platdata(&fimg2d_data);
+#ifdef CONFIG_EXYNOS_DEV_PD
+	s5p_device_fimg2d.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
+#endif
+#endif
+#ifdef CONFIG_USB_EHCI_S5P
+	smdkc210_ehci_init();
+#endif
+#ifdef CONFIG_USB_OHCI_S5P
+	smdkc210_ohci_init();
+#endif
+#ifdef CONFIG_USB_GADGET
+	smdkc210_usbgadget_init();
+#endif
+#ifdef CONFIG_FB_S5P_LD9040
+	ld9040_fb_init();
+#endif
+#ifdef CONFIG_FB_S5P_NT35560
+	nt35560_fb_init();
+#endif
+#if defined(CONFIG_FB_S5P_MIPI_DSIM)
+	mipi_fb_init();
+#endif
+
+#ifdef CONFIG_SND_SOC_U1_MC1N2
+	u1_sound_init();
+#endif
+
+	brcm_wlan_init();
+
+	exynos_sysmmu_init();
+
+	platform_add_devices(smdkc210_devices, ARRAY_SIZE(smdkc210_devices));
+
+#ifdef CONFIG_SEC_THERMISTOR
+	platform_device_register(&sec_device_thermistor);
+#endif
+
+#ifdef CONFIG_FB_S3C
+	exynos4_fimd0_setup_clock(&s5p_device_fimd0.dev, "mout_mpll",
+				  800 * MHZ);
+#endif
+
+#ifdef CONFIG_S3C64XX_DEV_SPI
+	sclk = clk_get(spi0_dev, "dout_spi0");
+	if (IS_ERR(sclk))
+		dev_err(spi0_dev, "failed to get sclk for SPI-0\n");
+	prnt = clk_get(spi0_dev, "mout_mpll");
+	if (IS_ERR(prnt))
+		dev_err(spi0_dev, "failed to get prnt\n");
+	clk_set_parent(sclk, prnt);
+
+	clk_put(sclk);
+	clk_put(prnt);
+
+	if (!gpio_request(EXYNOS4_GPB(1), "SPI_CS0")) {
+		gpio_direction_output(EXYNOS4_GPB(1), 1);
+		s3c_gpio_cfgpin(EXYNOS4_GPB(1), S3C_GPIO_SFN(1));
+		s3c_gpio_setpull(EXYNOS4_GPB(1), S3C_GPIO_PULL_UP);
+		exynos_spi_set_info(0, EXYNOS_SPI_SRCCLK_SCLK,
+				    ARRAY_SIZE(spi0_csi));
+	}
+	spi_register_board_info(spi0_board_info, ARRAY_SIZE(spi0_board_info));
+#endif
+
+#ifdef CONFIG_BUSFREQ_OPP
+	dev_add(&busfreq, &exynos4_busfreq.dev);
+#endif
+
+#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE)
+	tdmb_dev_init();
+#endif
+
+}
+
+static void __init exynos_init_reserve(void)
+{
+	sec_debug_magic_init();
+}
+
+#ifdef CONFIG_MACH_U1_KOR_SKT
+#define MODEL_NAME "SHW-M250S"
+#elif defined(CONFIG_MACH_U1_KOR_KT)
+#define MODEL_NAME "SHW-M250K"
+#elif defined(CONFIG_MACH_U1_KOR_LGT)
+#define MODEL_NAME "SHW-M250L"
+#else
+#define MODEL_NAME "SMDK4210"
+#endif
+
+MACHINE_START(SMDKC210, MODEL_NAME)
+	/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
+	.boot_params	= S5P_PA_SDRAM + 0x100,
+	.init_irq	= exynos4_init_irq,
+	.map_io		= smdkc210_map_io,
+	.init_machine	= smdkc210_machine_init,
+	.timer		= &exynos4_timer,
+	.init_early	= &exynos_init_reserve,
+MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
new file mode 100644
index 0000000..a458483
--- /dev/null
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -0,0 +1,649 @@
+/* linux/arch/arm/mach-exynos/mach-universal_c210.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/platform_device.h>
+#include <linux/serial_core.h>
+#include <linux/input.h>
+#include <linux/i2c.h>
+#include <linux/gpio_keys.h>
+#include <linux/gpio.h>
+#include <linux/mfd/max8998.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/max8952.h>
+#include <linux/mmc/host.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <plat/regs-serial.h>
+#include <plat/exynos4.h>
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/iic.h>
+#include <plat/sdhci.h>
+
+#include <mach/map.h>
+
+/* Following are default values for UCON, ULCON and UFCON UART registers */
+#define UNIVERSAL_UCON_DEFAULT	(S3C2410_UCON_TXILEVEL |	\
+				 S3C2410_UCON_RXILEVEL |	\
+				 S3C2410_UCON_TXIRQMODE |	\
+				 S3C2410_UCON_RXIRQMODE |	\
+				 S3C2410_UCON_RXFIFO_TOI |	\
+				 S3C2443_UCON_RXERR_IRQEN)
+
+#define UNIVERSAL_ULCON_DEFAULT	S3C2410_LCON_CS8
+
+#define UNIVERSAL_UFCON_DEFAULT	(S3C2410_UFCON_FIFOMODE |	\
+				 S5PV210_UFCON_TXTRIG256 |	\
+				 S5PV210_UFCON_RXTRIG256)
+
+static struct s3c2410_uartcfg universal_uartcfgs[] __initdata = {
+	[0] = {
+		.hwport		= 0,
+		.ucon		= UNIVERSAL_UCON_DEFAULT,
+		.ulcon		= UNIVERSAL_ULCON_DEFAULT,
+		.ufcon		= UNIVERSAL_UFCON_DEFAULT,
+	},
+	[1] = {
+		.hwport		= 1,
+		.ucon		= UNIVERSAL_UCON_DEFAULT,
+		.ulcon		= UNIVERSAL_ULCON_DEFAULT,
+		.ufcon		= UNIVERSAL_UFCON_DEFAULT,
+	},
+	[2] = {
+		.hwport		= 2,
+		.ucon		= UNIVERSAL_UCON_DEFAULT,
+		.ulcon		= UNIVERSAL_ULCON_DEFAULT,
+		.ufcon		= UNIVERSAL_UFCON_DEFAULT,
+	},
+	[3] = {
+		.hwport		= 3,
+		.ucon		= UNIVERSAL_UCON_DEFAULT,
+		.ulcon		= UNIVERSAL_ULCON_DEFAULT,
+		.ufcon		= UNIVERSAL_UFCON_DEFAULT,
+	},
+};
+
+static struct regulator_consumer_supply max8952_consumer =
+	REGULATOR_SUPPLY("vddarm", NULL);
+
+static struct max8952_platform_data universal_max8952_pdata __initdata = {
+	.gpio_vid0	= EXYNOS4_GPX0(3),
+	.gpio_vid1	= EXYNOS4_GPX0(4),
+	.gpio_en	= -1, /* Not controllable, set "Always High" */
+	.default_mode	= 0, /* vid0 = 0, vid1 = 0 */
+	.dvs_mode	= { 48, 32, 28, 18 }, /* 1.25, 1.20, 1.05, 0.95V */
+	.sync_freq	= 0, /* default: fastest */
+	.ramp_speed	= 0, /* default: fastest */
+
+	.reg_data	= {
+		.constraints	= {
+			.name		= "VARM_1.2V",
+			.min_uV		= 770000,
+			.max_uV		= 1400000,
+			.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE,
+			.always_on	= 1,
+			.boot_on	= 1,
+		},
+		.num_consumer_supplies	= 1,
+		.consumer_supplies	= &max8952_consumer,
+	},
+};
+
+static struct regulator_consumer_supply lp3974_buck1_consumer =
+	REGULATOR_SUPPLY("vddint", NULL);
+
+static struct regulator_consumer_supply lp3974_buck2_consumer =
+	REGULATOR_SUPPLY("vddg3d", NULL);
+
+static struct regulator_init_data lp3974_buck1_data = {
+	.constraints	= {
+		.name		= "VINT_1.1V",
+		.min_uV		= 750000,
+		.max_uV		= 1500000,
+		.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE |
+			REGULATOR_CHANGE_STATUS,
+		.boot_on	= 1,
+		.state_mem	= {
+			.disabled	= 1,
+		},
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &lp3974_buck1_consumer,
+};
+
+static struct regulator_init_data lp3974_buck2_data = {
+	.constraints	= {
+		.name		= "VG3D_1.1V",
+		.min_uV		= 750000,
+		.max_uV		= 1500000,
+		.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE |
+			REGULATOR_CHANGE_STATUS,
+		.boot_on	= 1,
+		.state_mem	= {
+			.disabled	= 1,
+		},
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &lp3974_buck2_consumer,
+};
+
+static struct regulator_init_data lp3974_buck3_data = {
+	.constraints	= {
+		.name		= "VCC_1.8V",
+		.min_uV		= 1800000,
+		.max_uV		= 1800000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.state_mem	= {
+			.enabled	= 1,
+		},
+	},
+};
+
+static struct regulator_init_data lp3974_buck4_data = {
+	.constraints	= {
+		.name		= "VMEM_1.2V",
+		.min_uV		= 1200000,
+		.max_uV		= 1200000,
+		.valid_ops_mask	= REGULATOR_CHANGE_STATUS,
+		.apply_uV	= 1,
+		.state_mem	= {
+			.disabled	= 1,
+		},
+	},
+};
+
+static struct regulator_init_data lp3974_ldo2_data = {
+	.constraints	= {
+		.name		= "VALIVE_1.2V",
+		.min_uV		= 1200000,
+		.max_uV		= 1200000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.state_mem	= {
+			.enabled	= 1,
+		},
+	},
+};
+
+static struct regulator_init_data lp3974_ldo3_data = {
+	.constraints	= {
+		.name		= "VUSB+MIPI_1.1V",
+		.min_uV		= 1100000,
+		.max_uV		= 1100000,
+		.apply_uV	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.disabled	= 1,
+		},
+	},
+};
+
+static struct regulator_init_data lp3974_ldo4_data = {
+	.constraints	= {
+		.name		= "VADC_3.3V",
+		.min_uV		= 3300000,
+		.max_uV		= 3300000,
+		.apply_uV	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.disabled	= 1,
+		},
+	},
+};
+
+static struct regulator_init_data lp3974_ldo5_data = {
+	.constraints	= {
+		.name		= "VTF_2.8V",
+		.min_uV		= 2800000,
+		.max_uV		= 2800000,
+		.apply_uV	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.disabled	= 1,
+		},
+	},
+};
+
+static struct regulator_init_data lp3974_ldo6_data = {
+	.constraints	= {
+		.name		= "LDO6",
+		.min_uV		= 2000000,
+		.max_uV		= 2000000,
+		.apply_uV	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.disabled	= 1,
+		},
+	},
+};
+
+static struct regulator_init_data lp3974_ldo7_data = {
+	.constraints	= {
+		.name		= "VLCD+VMIPI_1.8V",
+		.min_uV		= 1800000,
+		.max_uV		= 1800000,
+		.apply_uV	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.disabled	= 1,
+		},
+	},
+};
+
+static struct regulator_init_data lp3974_ldo8_data = {
+	.constraints	= {
+		.name		= "VUSB+VDAC_3.3V",
+		.min_uV		= 3300000,
+		.max_uV		= 3300000,
+		.apply_uV	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.disabled	= 1,
+		},
+	},
+};
+
+static struct regulator_init_data lp3974_ldo9_data = {
+	.constraints	= {
+		.name		= "VCC_2.8V",
+		.min_uV		= 2800000,
+		.max_uV		= 2800000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.state_mem	= {
+			.enabled	= 1,
+		},
+	},
+};
+
+static struct regulator_init_data lp3974_ldo10_data = {
+	.constraints	= {
+		.name		= "VPLL_1.1V",
+		.min_uV		= 1100000,
+		.max_uV		= 1100000,
+		.boot_on	= 1,
+		.apply_uV	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.disabled	= 1,
+		},
+	},
+};
+
+static struct regulator_init_data lp3974_ldo11_data = {
+	.constraints	= {
+		.name		= "CAM_AF_3.3V",
+		.min_uV		= 3300000,
+		.max_uV		= 3300000,
+		.apply_uV	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.disabled	= 1,
+		},
+	},
+};
+
+static struct regulator_init_data lp3974_ldo12_data = {
+	.constraints	= {
+		.name		= "PS_2.8V",
+		.min_uV		= 2800000,
+		.max_uV		= 2800000,
+		.apply_uV	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.disabled	= 1,
+		},
+	},
+};
+
+static struct regulator_init_data lp3974_ldo13_data = {
+	.constraints	= {
+		.name		= "VHIC_1.2V",
+		.min_uV		= 1200000,
+		.max_uV		= 1200000,
+		.apply_uV	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.disabled	= 1,
+		},
+	},
+};
+
+static struct regulator_init_data lp3974_ldo14_data = {
+	.constraints	= {
+		.name		= "CAM_I_HOST_1.8V",
+		.min_uV		= 1800000,
+		.max_uV		= 1800000,
+		.apply_uV	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.disabled	= 1,
+		},
+	},
+};
+
+static struct regulator_init_data lp3974_ldo15_data = {
+	.constraints	= {
+		.name		= "CAM_S_DIG+FM33_CORE_1.2V",
+		.min_uV		= 1200000,
+		.max_uV		= 1200000,
+		.apply_uV	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.disabled	= 1,
+		},
+	},
+};
+
+static struct regulator_init_data lp3974_ldo16_data = {
+	.constraints	= {
+		.name		= "CAM_S_ANA_2.8V",
+		.min_uV		= 2800000,
+		.max_uV		= 2800000,
+		.apply_uV	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.disabled	= 1,
+		},
+	},
+};
+
+static struct regulator_init_data lp3974_ldo17_data = {
+	.constraints	= {
+		.name		= "VCC_3.0V_LCD",
+		.min_uV		= 3000000,
+		.max_uV		= 3000000,
+		.apply_uV	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_STATUS,
+		.boot_on	= 1,
+		.state_mem	= {
+			.disabled	= 1,
+		},
+	},
+};
+
+static struct regulator_init_data lp3974_32khz_ap_data = {
+	.constraints	= {
+		.name		= "32KHz AP",
+		.always_on	= 1,
+		.state_mem	= {
+			.enabled	= 1,
+		},
+	},
+};
+
+static struct regulator_init_data lp3974_32khz_cp_data = {
+	.constraints	= {
+		.name		= "32KHz CP",
+		.state_mem	= {
+			.disabled	= 1,
+		},
+	},
+};
+
+static struct regulator_init_data lp3974_vichg_data = {
+	.constraints	= {
+		.name		= "VICHG",
+		.state_mem	= {
+			.disabled	= 1,
+		},
+	},
+};
+
+static struct regulator_init_data lp3974_esafeout1_data = {
+	.constraints	= {
+		.name		= "SAFEOUT1",
+		.valid_ops_mask	= REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.enabled	= 1,
+		},
+	},
+};
+
+static struct regulator_init_data lp3974_esafeout2_data = {
+	.constraints	= {
+		.name		= "SAFEOUT2",
+		.boot_on	= 1,
+		.valid_ops_mask	= REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.enabled	= 1,
+		},
+	},
+};
+
+static struct max8998_regulator_data lp3974_regulators[] = {
+	{ MAX8998_LDO2,  &lp3974_ldo2_data },
+	{ MAX8998_LDO3,  &lp3974_ldo3_data },
+	{ MAX8998_LDO4,  &lp3974_ldo4_data },
+	{ MAX8998_LDO5,  &lp3974_ldo5_data },
+	{ MAX8998_LDO6,  &lp3974_ldo6_data },
+	{ MAX8998_LDO7,  &lp3974_ldo7_data },
+	{ MAX8998_LDO8,  &lp3974_ldo8_data },
+	{ MAX8998_LDO9,  &lp3974_ldo9_data },
+	{ MAX8998_LDO10, &lp3974_ldo10_data },
+	{ MAX8998_LDO11, &lp3974_ldo11_data },
+	{ MAX8998_LDO12, &lp3974_ldo12_data },
+	{ MAX8998_LDO13, &lp3974_ldo13_data },
+	{ MAX8998_LDO14, &lp3974_ldo14_data },
+	{ MAX8998_LDO15, &lp3974_ldo15_data },
+	{ MAX8998_LDO16, &lp3974_ldo16_data },
+	{ MAX8998_LDO17, &lp3974_ldo17_data },
+	{ MAX8998_BUCK1, &lp3974_buck1_data },
+	{ MAX8998_BUCK2, &lp3974_buck2_data },
+	{ MAX8998_BUCK3, &lp3974_buck3_data },
+	{ MAX8998_BUCK4, &lp3974_buck4_data },
+	{ MAX8998_EN32KHZ_AP, &lp3974_32khz_ap_data },
+	{ MAX8998_EN32KHZ_CP, &lp3974_32khz_cp_data },
+	{ MAX8998_ENVICHG, &lp3974_vichg_data },
+	{ MAX8998_ESAFEOUT1, &lp3974_esafeout1_data },
+	{ MAX8998_ESAFEOUT2, &lp3974_esafeout2_data },
+};
+
+static struct max8998_platform_data universal_lp3974_pdata = {
+	.num_regulators		= ARRAY_SIZE(lp3974_regulators),
+	.regulators		= lp3974_regulators,
+	.buck1_voltage1		= 1100000,	/* INT */
+	.buck1_voltage2		= 1000000,
+	.buck1_voltage3		= 1100000,
+	.buck1_voltage4		= 1000000,
+	.buck1_set1		= EXYNOS4_GPX0(5),
+	.buck1_set2		= EXYNOS4_GPX0(6),
+	.buck2_voltage1		= 1200000,	/* G3D */
+	.buck2_voltage2		= 1100000,
+	.buck1_default_idx	= 0,
+	.buck2_set3		= EXYNOS4_GPE2(0),
+	.buck2_default_idx	= 0,
+	.wakeup			= true,
+};
+
+/* GPIO I2C 5 (PMIC) */
+static struct i2c_board_info i2c5_devs[] __initdata = {
+	{
+		I2C_BOARD_INFO("max8952", 0xC0 >> 1),
+		.platform_data	= &universal_max8952_pdata,
+	}, {
+		I2C_BOARD_INFO("lp3974", 0xCC >> 1),
+		.platform_data	= &universal_lp3974_pdata,
+	},
+};
+
+/* GPIO KEYS */
+static struct gpio_keys_button universal_gpio_keys_tables[] = {
+	{
+		.code			= KEY_VOLUMEUP,
+		.gpio			= EXYNOS4_GPX2(0),	/* XEINT16 */
+		.desc			= "gpio-keys: KEY_VOLUMEUP",
+		.type			= EV_KEY,
+		.active_low		= 1,
+		.debounce_interval	= 1,
+	}, {
+		.code			= KEY_VOLUMEDOWN,
+		.gpio			= EXYNOS4_GPX2(1),	/* XEINT17 */
+		.desc			= "gpio-keys: KEY_VOLUMEDOWN",
+		.type			= EV_KEY,
+		.active_low		= 1,
+		.debounce_interval	= 1,
+	}, {
+		.code			= KEY_CONFIG,
+		.gpio			= EXYNOS4_GPX2(2),	/* XEINT18 */
+		.desc			= "gpio-keys: KEY_CONFIG",
+		.type			= EV_KEY,
+		.active_low		= 1,
+		.debounce_interval	= 1,
+	}, {
+		.code			= KEY_CAMERA,
+		.gpio			= EXYNOS4_GPX2(3),	/* XEINT19 */
+		.desc			= "gpio-keys: KEY_CAMERA",
+		.type			= EV_KEY,
+		.active_low		= 1,
+		.debounce_interval	= 1,
+	}, {
+		.code			= KEY_OK,
+		.gpio			= EXYNOS4_GPX3(5),	/* XEINT29 */
+		.desc			= "gpio-keys: KEY_OK",
+		.type			= EV_KEY,
+		.active_low		= 1,
+		.debounce_interval	= 1,
+	},
+};
+
+static struct gpio_keys_platform_data universal_gpio_keys_data = {
+	.buttons	= universal_gpio_keys_tables,
+	.nbuttons	= ARRAY_SIZE(universal_gpio_keys_tables),
+};
+
+static struct platform_device universal_gpio_keys = {
+	.name			= "gpio-keys",
+	.dev			= {
+		.platform_data	= &universal_gpio_keys_data,
+	},
+};
+
+/* eMMC */
+static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
+	.max_width		= 8,
+	.host_caps		= (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
+				MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
+				MMC_CAP_DISABLE),
+	.cd_type		= S3C_SDHCI_CD_PERMANENT,
+	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+
+static struct regulator_consumer_supply mmc0_supplies[] = {
+	REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
+};
+
+static struct regulator_init_data mmc0_fixed_voltage_init_data = {
+	.constraints		= {
+		.name		= "VMEM_VDD_2.8V",
+		.valid_ops_mask	= REGULATOR_CHANGE_STATUS,
+	},
+	.num_consumer_supplies	= ARRAY_SIZE(mmc0_supplies),
+	.consumer_supplies	= mmc0_supplies,
+};
+
+static struct fixed_voltage_config mmc0_fixed_voltage_config = {
+	.supply_name		= "MASSMEMORY_EN",
+	.microvolts		= 2800000,
+	.gpio			= EXYNOS4_GPE1(3),
+	.enable_high		= true,
+	.init_data		= &mmc0_fixed_voltage_init_data,
+};
+
+static struct platform_device mmc0_fixed_voltage = {
+	.name			= "reg-fixed-voltage",
+	.id			= 0,
+	.dev			= {
+		.platform_data	= &mmc0_fixed_voltage_config,
+	},
+};
+
+/* SD */
+static struct s3c_sdhci_platdata universal_hsmmc2_data __initdata = {
+	.max_width		= 4,
+	.host_caps		= MMC_CAP_4_BIT_DATA |
+				MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
+				MMC_CAP_DISABLE,
+	.ext_cd_gpio		= EXYNOS4_GPX3(4),      /* XEINT_28 */
+	.ext_cd_gpio_invert	= 1,
+	.cd_type		= S3C_SDHCI_CD_GPIO,
+	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+
+/* WiFi */
+static struct s3c_sdhci_platdata universal_hsmmc3_data __initdata = {
+	.max_width		= 4,
+	.host_caps		= MMC_CAP_4_BIT_DATA |
+				MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
+				MMC_CAP_DISABLE,
+	.cd_type		= S3C_SDHCI_CD_EXTERNAL,
+};
+
+static void __init universal_sdhci_init(void)
+{
+	s3c_sdhci0_set_platdata(&universal_hsmmc0_data);
+	s3c_sdhci2_set_platdata(&universal_hsmmc2_data);
+	s3c_sdhci3_set_platdata(&universal_hsmmc3_data);
+}
+
+/* I2C0 */
+static struct i2c_board_info i2c0_devs[] __initdata = {
+	/* Camera, To be updated */
+};
+
+/* I2C1 */
+static struct i2c_board_info i2c1_devs[] __initdata = {
+	/* Gyro, To be updated */
+};
+
+static struct platform_device *universal_devices[] __initdata = {
+	/* Samsung Platform Devices */
+	&mmc0_fixed_voltage,
+	&s3c_device_hsmmc0,
+	&s3c_device_hsmmc2,
+	&s3c_device_hsmmc3,
+	&s3c_device_i2c5,
+	/* Universal Devices */
+	&universal_gpio_keys,
+	&s5p_device_onenand,
+};
+
+static void __init universal_map_io(void)
+{
+	s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+	s3c24xx_init_clocks(24000000);
+	s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
+}
+
+static void __init universal_machine_init(void)
+{
+	universal_sdhci_init();
+
+	i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));
+	i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
+
+	s3c_i2c5_set_platdata(NULL);
+	i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
+
+	/* Last */
+	platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices));
+}
+
+MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
+	/* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
+	.boot_params	= S5P_PA_SDRAM + 0x100,
+	.init_irq	= exynos4_init_irq,
+	.map_io		= universal_map_io,
+	.init_machine	= universal_machine_init,
+	.timer		= &exynos4_timer,
+MACHINE_END
diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
new file mode 100644
index 0000000..dececa1
--- /dev/null
+++ b/arch/arm/mach-exynos/mct.c
@@ -0,0 +1,489 @@
+/* linux/arch/arm/mach-exynos/mct.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS4 MCT(Multi-Core Timer) support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/percpu.h>
+
+#include <plat/cpu.h>
+
+#include <mach/map.h>
+#include <mach/regs-mct.h>
+
+#include <asm/mach/time.h>
+#include <asm/hardware/gic.h>
+
+#define TICK_BASE_CNT 1
+
+enum {
+	MCT_INT_PPI,
+	MCT_INT_SPI
+};
+
+static unsigned long clk_cnt_per_tick;
+static unsigned long clk_rate;
+static unsigned int mct_int_type;
+
+struct mct_clock_event_device {
+	struct clock_event_device *evt;
+	void __iomem *base;
+	char name[10];
+};
+
+struct mct_clock_event_device mct_tick[NR_CPUS];
+
+static void exynos4_mct_write(unsigned int value, void *addr)
+{
+	void __iomem *stat_addr;
+	u32 mask;
+	u32 i;
+
+	__raw_writel(value, addr);
+
+	if (likely(addr >= EXYNOS4_MCT_L_BASE(0))) {
+		u32 base = (u32) addr & EXYNOS4_MCT_L_MASK;
+		switch ((u32) addr & ~EXYNOS4_MCT_L_MASK) {
+		case (u32) MCT_L_TCON_OFFSET:
+			stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
+			mask = 1 << 3;		/* L_TCON write status */
+			break;
+		case (u32) MCT_L_ICNTB_OFFSET:
+			stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
+			mask = 1 << 1;		/* L_ICNTB write status */
+			break;
+		case (u32) MCT_L_TCNTB_OFFSET:
+			stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
+			mask = 1 << 0;		/* L_TCNTB write status */
+			break;
+		default:
+			return;
+		}
+	} else {
+		switch ((u32) addr) {
+		case (u32) EXYNOS4_MCT_G_TCON:
+			stat_addr = EXYNOS4_MCT_G_WSTAT;
+			mask = 1 << 16;		/* G_TCON write status */
+			break;
+		case (u32) EXYNOS4_MCT_G_COMP0_L:
+			stat_addr = EXYNOS4_MCT_G_WSTAT;
+			mask = 1 << 0;		/* G_COMP0_L write status */
+			break;
+		case (u32) EXYNOS4_MCT_G_COMP0_U:
+			stat_addr = EXYNOS4_MCT_G_WSTAT;
+			mask = 1 << 1;		/* G_COMP0_U write status */
+			break;
+		case (u32) EXYNOS4_MCT_G_COMP0_ADD_INCR:
+			stat_addr = EXYNOS4_MCT_G_WSTAT;
+			mask = 1 << 2;		/* G_COMP0_ADD_INCR write status */
+			break;
+		case (u32) EXYNOS4_MCT_G_CNT_L:
+			stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
+			mask = 1 << 0;		/* G_CNT_L write status */
+			break;
+		case (u32) EXYNOS4_MCT_G_CNT_U:
+			stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
+			mask = 1 << 1;		/* G_CNT_U write status */
+			break;
+		default:
+			return;
+		}
+	}
+
+	/* Wait until written values are applied */
+	for (i = 0; i < 0x1000; i++)
+		if (__raw_readl(stat_addr) & mask) {
+			__raw_writel(mask, stat_addr);
+			return;
+		}
+
+	/* Workaround: Try again if fail */
+	__raw_writel(value, addr);
+
+	printk(KERN_ERR "[%s]value=%d addr=0x%X\n", __func__, value, (u32)addr);
+
+	for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
+		if (__raw_readl(stat_addr) & mask) {
+			__raw_writel(mask, stat_addr);
+			return;
+		}
+
+	panic("MCT hangs after writing %d (addr:0x%08x)\n", value, (u32)addr);
+}
+
+/* Clocksource handling */
+static void exynos4_mct_frc_start(u32 hi, u32 lo)
+{
+	u32 reg;
+
+	exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
+	exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
+
+	reg = __raw_readl(EXYNOS4_MCT_G_TCON);
+	reg |= MCT_G_TCON_START;
+	exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
+}
+
+static cycle_t notrace exynos4_frc_read(struct clocksource *cs)
+{
+	unsigned int lo, hi;
+	u32 hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
+
+	do {
+		hi = hi2;
+		lo = __raw_readl(EXYNOS4_MCT_G_CNT_L);
+		hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
+	} while (hi != hi2);
+
+	return ((cycle_t)hi << 32) | lo;
+}
+
+cycle_t suspended_frc_count;
+
+static void exynos4_frc_suspend(struct clocksource *cs)
+{
+	suspended_frc_count = cs->read(cs);
+}
+
+static void exynos4_frc_resume(struct clocksource *cs)
+{
+	exynos4_mct_frc_start(suspended_frc_count >> 32, suspended_frc_count);
+}
+
+struct clocksource mct_frc = {
+	.name		= "mct-frc",
+	.rating		= 400,
+	.read		= exynos4_frc_read,
+	.mask		= CLOCKSOURCE_MASK(64),
+	.flags		= CLOCK_SOURCE_IS_CONTINUOUS |
+			  CLOCK_SOURCE_SCHED_CLOCK,
+	.suspend	= exynos4_frc_suspend,
+	.resume		= exynos4_frc_resume,
+};
+
+static void __init exynos4_clocksource_init(void)
+{
+	exynos4_mct_frc_start(0, 0);
+
+	if (clocksource_register_hz(&mct_frc, clk_rate))
+		panic("%s: can't register clocksource\n", mct_frc.name);
+}
+
+static void exynos4_mct_comp0_stop(void)
+{
+	unsigned int tcon;
+
+	tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
+	tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
+
+	exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
+	exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
+}
+
+static void exynos4_mct_comp0_start(enum clock_event_mode mode,
+				    unsigned long cycles)
+{
+	unsigned int tcon;
+	cycle_t comp_cycle;
+
+	tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
+
+	if (mode == CLOCK_EVT_MODE_PERIODIC) {
+		tcon |= MCT_G_TCON_COMP0_AUTO_INC;
+		exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
+	}
+
+	comp_cycle = exynos4_frc_read(&mct_frc) + cycles;
+	exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
+	exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);
+
+	exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);
+
+	tcon |= MCT_G_TCON_COMP0_ENABLE;
+	exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
+}
+
+static int exynos4_comp_set_next_event(unsigned long cycles,
+				       struct clock_event_device *evt)
+{
+	exynos4_mct_comp0_start(evt->mode, cycles);
+
+	return 0;
+}
+
+static void exynos4_comp_set_mode(enum clock_event_mode mode,
+				  struct clock_event_device *evt)
+{
+	exynos4_mct_comp0_stop();
+
+	switch (mode) {
+	case CLOCK_EVT_MODE_PERIODIC:
+		exynos4_mct_comp0_start(mode, clk_cnt_per_tick);
+		break;
+
+	case CLOCK_EVT_MODE_ONESHOT:
+	case CLOCK_EVT_MODE_UNUSED:
+	case CLOCK_EVT_MODE_SHUTDOWN:
+	case CLOCK_EVT_MODE_RESUME:
+		break;
+	}
+}
+
+static struct clock_event_device mct_comp_device = {
+	.name		= "mct-comp",
+	.features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+	.rating		= 250,
+	.set_next_event	= exynos4_comp_set_next_event,
+	.set_mode	= exynos4_comp_set_mode,
+};
+
+static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
+{
+	struct clock_event_device *evt = dev_id;
+
+	exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);
+
+	evt->event_handler(evt);
+
+	return IRQ_HANDLED;
+}
+
+static struct irqaction mct_comp_event_irq = {
+	.name		= "mct_comp_irq",
+	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
+	.handler	= exynos4_mct_comp_isr,
+	.dev_id		= &mct_comp_device,
+};
+
+static void exynos4_clockevent_init(void)
+{
+	clk_cnt_per_tick = clk_rate / HZ;
+
+	clockevents_calc_mult_shift(&mct_comp_device, clk_rate, 5);
+	mct_comp_device.max_delta_ns =
+		clockevent_delta2ns(0xffffffff, &mct_comp_device);
+	mct_comp_device.min_delta_ns =
+		clockevent_delta2ns(0xf, &mct_comp_device);
+	mct_comp_device.cpumask = cpumask_of(0);
+	clockevents_register_device(&mct_comp_device);
+
+	setup_irq(IRQ_MCT_G0, &mct_comp_event_irq);
+}
+
+#ifdef CONFIG_LOCAL_TIMERS
+/* Clock event handling */
+static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
+{
+	unsigned long tmp;
+	unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
+	void __iomem *addr = mevt->base + MCT_L_TCON_OFFSET;
+
+	tmp = __raw_readl(addr);
+	if (tmp & mask) {
+		tmp &= ~mask;
+		exynos4_mct_write(tmp, addr);
+	}
+}
+
+static void exynos4_mct_tick_start(unsigned long cycles,
+				   struct mct_clock_event_device *mevt)
+{
+	unsigned long tmp;
+
+	exynos4_mct_tick_stop(mevt);
+
+	tmp = (1 << 31) | cycles;	/* MCT_L_UPDATE_ICNTB */
+
+	/* update interrupt count buffer */
+	exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);
+
+	/* enable MCT tick interrupt */
+	exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
+
+	tmp = __raw_readl(mevt->base + MCT_L_TCON_OFFSET);
+	tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
+	       MCT_L_TCON_INTERVAL_MODE;
+	exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
+}
+
+static int exynos4_tick_set_next_event(unsigned long cycles,
+				       struct clock_event_device *evt)
+{
+	struct mct_clock_event_device *mevt = &mct_tick[smp_processor_id()];
+
+	if (cpu_online(smp_processor_id()))
+		exynos4_mct_tick_start(cycles, mevt);
+
+	return 0;
+}
+
+static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
+					 struct clock_event_device *evt)
+{
+	struct mct_clock_event_device *mevt = &mct_tick[smp_processor_id()];
+
+	exynos4_mct_tick_stop(mevt);
+
+	switch (mode) {
+	case CLOCK_EVT_MODE_PERIODIC:
+		exynos4_mct_tick_start(clk_cnt_per_tick / (TICK_BASE_CNT + 1)
+					, mevt);
+		break;
+
+	case CLOCK_EVT_MODE_ONESHOT:
+	case CLOCK_EVT_MODE_UNUSED:
+	case CLOCK_EVT_MODE_SHUTDOWN:
+		break;
+
+	case CLOCK_EVT_MODE_RESUME:
+		exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);
+		break;
+	}
+}
+
+static inline int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
+{
+	struct clock_event_device *evt = mevt->evt;
+
+	/*
+	 * This is for supporting oneshot mode.
+	 * Mct would generate interrupt periodically
+	 * without explicit stopping.
+	 */
+	if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
+		exynos4_mct_tick_stop(mevt);
+
+	/*
+	 * Clear the MCT tick interrupt.
+	 * Because of the limitation of MCT hardware,
+	 * it should be cleared twice.
+	 */
+	if (__raw_readl(mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
+		exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
+		exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
+		return 1;
+	} else {
+		return 0;
+	}
+}
+
+static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
+{
+	struct mct_clock_event_device *mevt = dev_id;
+	struct clock_event_device *evt = mevt->evt;
+
+	exynos4_mct_tick_clear(mevt);
+
+	evt->event_handler(evt);
+
+	return IRQ_HANDLED;
+}
+
+static struct irqaction mct_tick0_event_irq = {
+	.name		= "mct_tick0_irq",
+	.flags		= IRQF_TIMER | IRQF_NOBALANCING,
+	.handler	= exynos4_mct_tick_isr,
+};
+
+static struct irqaction mct_tick1_event_irq = {
+	.name		= "mct_tick1_irq",
+	.flags		= IRQF_TIMER | IRQF_NOBALANCING,
+	.handler	= exynos4_mct_tick_isr,
+};
+
+static void exynos4_mct_tick_init(struct clock_event_device *evt)
+{
+	unsigned int cpu = smp_processor_id();
+
+	mct_tick[cpu].evt = evt;
+
+	mct_tick[cpu].base = EXYNOS4_MCT_L_BASE(cpu);
+	sprintf(mct_tick[cpu].name, "mct_tick%d", cpu);
+
+	evt->name = mct_tick[cpu].name;
+	evt->cpumask = cpumask_of(cpu);
+	evt->set_next_event = exynos4_tick_set_next_event;
+	evt->set_mode = exynos4_tick_set_mode;
+	evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
+	evt->rating = 450;
+
+	clockevents_calc_mult_shift(evt, clk_rate / (TICK_BASE_CNT + 1), 5);
+	evt->max_delta_ns =
+		clockevent_delta2ns(0x7fffffff, evt);
+	evt->min_delta_ns =
+		clockevent_delta2ns(0xf, evt);
+
+	clockevents_register_device(evt);
+
+	exynos4_mct_write(TICK_BASE_CNT, mct_tick[cpu].base + MCT_L_TCNTB_OFFSET);
+
+	if (mct_int_type == MCT_INT_SPI) {
+		if (cpu == 0) {
+			mct_tick0_event_irq.dev_id = &mct_tick[cpu];
+			setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq);
+		} else {
+			mct_tick1_event_irq.dev_id = &mct_tick[cpu];
+			setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq);
+			irq_set_affinity(IRQ_MCT_L1, cpumask_of(1));
+		}
+	} else {
+		gic_enable_ppi(IRQ_PPI_MCT_L);
+	}
+}
+
+/* Setup the local clock events for a CPU */
+int __cpuinit local_timer_setup(struct clock_event_device *evt)
+{
+	exynos4_mct_tick_init(evt);
+
+	return 0;
+}
+
+int local_timer_ack(void)
+{
+	unsigned int cpu = smp_processor_id();
+	struct mct_clock_event_device *mevt = &mct_tick[cpu];
+
+	return exynos4_mct_tick_clear(mevt);
+}
+
+#endif /* CONFIG_LOCAL_TIMERS */
+
+static void __init exynos4_timer_resources(void)
+{
+	struct clk *mct_clk;
+	mct_clk = clk_get(NULL, "xtal");
+
+	clk_rate = clk_get_rate(mct_clk);
+}
+
+static void __init exynos4_timer_init(void)
+{
+	if (soc_is_exynos4210() ||
+	    (soc_is_exynos5250() && samsung_rev() >= EXYNOS5250_REV_1_0))
+		mct_int_type = MCT_INT_SPI;
+	else
+		mct_int_type = MCT_INT_PPI;
+
+	exynos4_timer_resources();
+	exynos4_clocksource_init();
+	exynos4_clockevent_init();
+}
+
+struct sys_timer exynos4_timer = {
+	.init		= exynos4_timer_init,
+};
diff --git a/arch/arm/mach-exynos/mdm2.c b/arch/arm/mach-exynos/mdm2.c
new file mode 100644
index 0000000..249b7cf
--- /dev/null
+++ b/arch/arm/mach-exynos/mdm2.c
@@ -0,0 +1,253 @@
+/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/mutex.h>
+#include <linux/miscdevice.h>
+#include <linux/fs.h>
+#include <linux/gpio.h>
+#include <linux/kernel.h>
+#include <linux/irq.h>
+#include <linux/ioctl.h>
+#include <linux/delay.h>
+#include <linux/reboot.h>
+#include <linux/debugfs.h>
+#include <linux/completion.h>
+#include <linux/workqueue.h>
+#include <linux/clk.h>
+#ifndef CONFIG_ARCH_EXYNOS
+#include <linux/mfd/pmic8058.h>
+#endif
+#include <asm/mach-types.h>
+#include <asm/uaccess.h>
+#include <mach/mdm2.h>
+#include <mach/restart.h>
+#include <mach/subsystem_notif.h>
+#include <mach/subsystem_restart.h>
+#include <linux/msm_charm.h>
+#ifndef CONFIG_ARCH_EXYNOS
+#include "msm_watchdog.h"
+#include "devices.h"
+#include "clock.h"
+#endif
+#include "mdm_private.h"
+#include <linux/wakelock.h>
+
+#define MDM_MODEM_TIMEOUT	6000
+#define MDM_HOLD_TIME		4000
+#define MDM_MODEM_DELTA		100
+
+static int mdm_debug_on;
+static int power_on_count;
+static int hsic_peripheral_status = 1;
+static DEFINE_MUTEX(hsic_status_lock);
+
+static void mdm_peripheral_connect(struct mdm_modem_drv *mdm_drv)
+{
+	pr_err("%s\n", __func__);
+	mutex_lock(&hsic_status_lock);
+	if (hsic_peripheral_status)
+		goto out;
+	if (mdm_drv->pdata->peripheral_platform_device)
+		platform_device_add(mdm_drv->pdata->peripheral_platform_device);
+	hsic_peripheral_status = 1;
+out:
+	mutex_unlock(&hsic_status_lock);
+	pr_err("%s : ap2mdm_status = %d\n", __func__,
+				gpio_get_value(mdm_drv->ap2mdm_status_gpio));
+}
+
+static void mdm_peripheral_disconnect(struct mdm_modem_drv *mdm_drv)
+{
+	pr_err("%s\n", __func__);
+	mutex_lock(&hsic_status_lock);
+	if (!hsic_peripheral_status)
+		goto out;
+	if (mdm_drv->pdata->peripheral_platform_device)
+		platform_device_del(mdm_drv->pdata->peripheral_platform_device);
+	hsic_peripheral_status = 0;
+out:
+	mutex_unlock(&hsic_status_lock);
+	pr_err("%s : ap2mdm_status = %d\n", __func__,
+				gpio_get_value(mdm_drv->ap2mdm_status_gpio));
+}
+
+static void power_on_mdm(struct mdm_modem_drv *mdm_drv)
+{
+	power_on_count++;
+
+	pr_err("%s: power count %d\n", __func__, power_on_count);
+	/* this gpio will be used to indicate apq readiness,
+	 * de-assert it now so that it can asserted later
+	 */
+	gpio_direction_output(mdm_drv->ap2mdm_wakeup_gpio, 0);
+
+	/* The second attempt to power-on the mdm is the first attempt
+	 * from user space, but we're already powered on. Ignore this.
+	 * Subsequent attempts are from SSR or if something failed, in
+	 * which case we must always reset the modem.
+	 */
+	if (power_on_count == 2)
+		return;
+
+	mdm_peripheral_disconnect(mdm_drv);
+
+	/* Pull RESET gpio low and wait for it to settle. */
+	pr_info("Pulling RESET gpio low\n");
+	gpio_direction_output(mdm_drv->ap2mdm_pmic_reset_n_gpio, 0);
+	usleep_range(5000, 10000);
+
+	/* Deassert RESET first and wait for ir to settle. */
+	pr_info("%s: Pulling RESET gpio high\n", __func__);
+	gpio_direction_output(mdm_drv->ap2mdm_pmic_reset_n_gpio, 1);
+	msleep(20);
+
+	/* Pull PWR gpio high and wait for it to settle, but only
+	 * the first time the mdm is powered up.
+	 * Some targets do not use ap2mdm_kpdpwr_n_gpio.
+	 */
+	if (power_on_count == 1) {
+		if (mdm_drv->ap2mdm_kpdpwr_n_gpio > 0) {
+			pr_debug("%s: Powering on mdm modem\n", __func__);
+			gpio_direction_output(mdm_drv->ap2mdm_kpdpwr_n_gpio, 1);
+			usleep_range(1000, 1000);
+		}
+	}
+
+#ifdef CONFIG_ARCH_EXYNOS
+	gpio_direction_output(mdm_drv->ap2mdm_status_gpio, 1);
+#endif
+	mdm_peripheral_connect(mdm_drv);
+
+	msleep(200);
+}
+
+static void power_down_mdm(struct mdm_modem_drv *mdm_drv)
+{
+	int i;
+
+	pr_err("%s\n", __func__);
+	for (i = MDM_MODEM_TIMEOUT; i > 0; i -= MDM_MODEM_DELTA) {
+		/* pet_watchdog(); */
+		msleep(MDM_MODEM_DELTA);
+		if (gpio_get_value(mdm_drv->mdm2ap_status_gpio) == 0)
+			break;
+	}
+	if (i <= 0) {
+		pr_err("%s: MDM2AP_STATUS never went low.\n",
+			 __func__);
+		gpio_direction_output(mdm_drv->ap2mdm_pmic_reset_n_gpio, 0);
+
+		for (i = MDM_HOLD_TIME; i > 0; i -= MDM_MODEM_DELTA) {
+			/* pet_watchdog(); */
+			msleep(MDM_MODEM_DELTA);
+		}
+	}
+	if (mdm_drv->ap2mdm_kpdpwr_n_gpio > 0)
+		gpio_direction_output(mdm_drv->ap2mdm_kpdpwr_n_gpio, 0);
+	mdm_peripheral_disconnect(mdm_drv);
+}
+
+#ifdef CONFIG_ARCH_EXYNOS
+static void normal_boot_done(struct mdm_modem_drv *mdm_drv)
+{
+	pr_err("%s\n", __func__);
+	mdm_peripheral_disconnect(mdm_drv);
+}
+#endif
+
+static void debug_state_changed(int value)
+{
+	mdm_debug_on = value;
+}
+
+static void mdm_status_changed(struct mdm_modem_drv *mdm_drv, int value)
+{
+	pr_debug("%s: value:%d\n", __func__, value);
+
+	pr_err("%s: ap2mdm_status = %d\n", __func__,
+				gpio_get_value(mdm_drv->ap2mdm_status_gpio));
+	if (value) {
+		mdm_peripheral_disconnect(mdm_drv);
+		mdm_peripheral_connect(mdm_drv);
+		gpio_direction_output(mdm_drv->ap2mdm_wakeup_gpio, 1);
+	}
+}
+
+static struct mdm_ops mdm_cb = {
+	.power_on_mdm_cb = power_on_mdm,
+	.power_down_mdm_cb = power_down_mdm,
+	.debug_state_changed_cb = debug_state_changed,
+	.status_cb = mdm_status_changed,
+#ifdef CONFIG_ARCH_EXYNOS
+	.normal_boot_done_cb = normal_boot_done,
+#endif
+};
+
+/* temprary wakelock, remove when L3 state implemented */
+#ifdef CONFIG_ARCH_EXYNOS
+static struct wake_lock mdm_wake;
+#endif
+
+static int __init mdm_modem_probe(struct platform_device *pdev)
+{
+	pr_err("%s\n", __func__);
+/* temprary wakelock, remove when L3 state implemented */
+#ifdef CONFIG_ARCH_EXYNOS
+	wake_lock_init(&mdm_wake, WAKE_LOCK_SUSPEND, "mdm_wake");
+	wake_lock(&mdm_wake);
+#endif
+	return mdm_common_create(pdev, &mdm_cb);
+}
+
+static int __devexit mdm_modem_remove(struct platform_device *pdev)
+{
+	return mdm_common_modem_remove(pdev);
+}
+
+static void mdm_modem_shutdown(struct platform_device *pdev)
+{
+	mdm_common_modem_shutdown(pdev);
+}
+
+static struct platform_driver mdm_modem_driver = {
+	.remove         = mdm_modem_remove,
+	.shutdown	= mdm_modem_shutdown,
+	.driver         = {
+		.name = "mdm2_modem",
+		.owner = THIS_MODULE
+	},
+};
+
+static int __init mdm_modem_init(void)
+{
+	return platform_driver_probe(&mdm_modem_driver, mdm_modem_probe);
+}
+
+static void __exit mdm_modem_exit(void)
+{
+	platform_driver_unregister(&mdm_modem_driver);
+}
+
+late_initcall(mdm_modem_init);
+/* module_init(mdm_modem_init); */
+module_exit(mdm_modem_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("mdm modem driver");
+MODULE_VERSION("2.0");
+MODULE_ALIAS("mdm_modem");
diff --git a/arch/arm/mach-exynos/mdm_common.c b/arch/arm/mach-exynos/mdm_common.c
new file mode 100644
index 0000000..30b5f75
--- /dev/null
+++ b/arch/arm/mach-exynos/mdm_common.c
@@ -0,0 +1,567 @@
+/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/mutex.h>
+#include <linux/miscdevice.h>
+#include <linux/fs.h>
+#include <linux/gpio.h>
+#include <linux/kernel.h>
+#include <linux/irq.h>
+#include <linux/ioctl.h>
+#include <linux/delay.h>
+#include <linux/reboot.h>
+#include <linux/debugfs.h>
+#include <linux/completion.h>
+#include <linux/workqueue.h>
+#include <linux/clk.h>
+#ifndef CONFIG_ARCH_EXYNOS
+#include <linux/mfd/pmic8058.h>
+#endif
+#include <asm/mach-types.h>
+#include <asm/uaccess.h>
+#include <mach/mdm2.h>
+#include <mach/restart.h>
+#include <mach/subsystem_notif.h>
+#include <mach/subsystem_restart.h>
+#include <linux/msm_charm.h>
+#ifndef CONFIG_ARCH_EXYNOS
+#include "msm_watchdog.h"
+#endif
+#include "mdm_private.h"
+
+#ifdef CONFIG_ARCH_EXYNOS
+#include <linux/interrupt.h>
+#include <plat/gpio-cfg.h>
+#endif
+
+#define MDM_MODEM_TIMEOUT	6000
+#define MDM_MODEM_DELTA	100
+#define MDM_BOOT_TIMEOUT	60000L
+#define MDM_RDUMP_TIMEOUT	60000L
+
+static int mdm_debug_on;
+static struct workqueue_struct *mdm_queue;
+
+#define EXTERNAL_MODEM "external_modem"
+
+static struct mdm_modem_drv *mdm_drv;
+
+DECLARE_COMPLETION(mdm_needs_reload);
+DECLARE_COMPLETION(mdm_boot);
+DECLARE_COMPLETION(mdm_ram_dumps);
+
+static int first_boot = 1;
+
+long mdm_modem_ioctl(struct file *filp, unsigned int cmd,
+				unsigned long arg)
+{
+	int status, ret = 0;
+
+	if (_IOC_TYPE(cmd) != CHARM_CODE) {
+		pr_err("%s: invalid ioctl code\n", __func__);
+		return -EINVAL;
+	}
+
+	pr_debug("%s: Entering ioctl cmd = %d\n", __func__, _IOC_NR(cmd));
+	switch (cmd) {
+	case WAKE_CHARM:
+		pr_info("%s: Powering on mdm\n", __func__);
+		mdm_drv->ops->power_on_mdm_cb(mdm_drv);
+		break;
+	case CHECK_FOR_BOOT:
+		if (gpio_get_value(mdm_drv->mdm2ap_status_gpio) == 0)
+			put_user(1, (unsigned long __user *) arg);
+		else
+			put_user(0, (unsigned long __user *) arg);
+		break;
+	case NORMAL_BOOT_DONE:
+		pr_info("%s: check if mdm is booted up\n", __func__);
+		get_user(status, (unsigned long __user *) arg);
+		if (status) {
+			pr_debug("%s: normal boot failed\n", __func__);
+			mdm_drv->mdm_boot_status = -EIO;
+		} else {
+			pr_info("%s: normal boot done\n", __func__);
+			mdm_drv->mdm_boot_status = 0;
+		}
+		mdm_drv->mdm_ready = 1;
+
+		if (mdm_drv->ops->normal_boot_done_cb != NULL)
+			mdm_drv->ops->normal_boot_done_cb(mdm_drv);
+
+		if (!first_boot)
+			complete(&mdm_boot);
+		else
+			first_boot = 0;
+		break;
+	case RAM_DUMP_DONE:
+		pr_info("%s: mdm done collecting RAM dumps\n", __func__);
+		get_user(status, (unsigned long __user *) arg);
+		if (status)
+			mdm_drv->mdm_ram_dump_status = -EIO;
+		else {
+			pr_info("%s: ramdump collection completed\n", __func__);
+			mdm_drv->mdm_ram_dump_status = 0;
+		}
+		complete(&mdm_ram_dumps);
+		break;
+	case WAIT_FOR_RESTART:
+		pr_info("%s: wait for mdm to need images reloaded\n",
+				__func__);
+		ret = wait_for_completion_interruptible(&mdm_needs_reload);
+		if (!ret)
+			put_user(mdm_drv->boot_type,
+					 (unsigned long __user *) arg);
+		INIT_COMPLETION(mdm_needs_reload);
+		break;
+	default:
+		pr_err("%s: invalid ioctl cmd = %d\n", __func__, _IOC_NR(cmd));
+		ret = -EINVAL;
+		break;
+	}
+
+	return ret;
+}
+
+static void mdm_fatal_fn(struct work_struct *work)
+{
+	pr_info("%s: Reseting the mdm due to an errfatal\n", __func__);
+	subsystem_restart(EXTERNAL_MODEM);
+}
+
+static DECLARE_WORK(mdm_fatal_work, mdm_fatal_fn);
+
+static void mdm_status_fn(struct work_struct *work)
+{
+	int value = gpio_get_value(mdm_drv->mdm2ap_status_gpio);
+
+	if (!mdm_drv->mdm_ready)
+		return;
+
+	mdm_drv->ops->status_cb(mdm_drv, value);
+
+	pr_err("%s: status:%d\n", __func__, value);
+
+	if ((value == 0)) {
+		pr_info("%s: unexpected reset external modem\n", __func__);
+		subsystem_restart(EXTERNAL_MODEM);
+	} else if (value == 1) {
+		pr_info("%s: status = 1: mdm is now ready\n", __func__);
+	}
+}
+
+static DECLARE_WORK(mdm_status_work, mdm_status_fn);
+
+static void mdm_disable_irqs(void)
+{
+	disable_irq_nosync(mdm_drv->mdm_errfatal_irq);
+	disable_irq_nosync(mdm_drv->mdm_status_irq);
+
+}
+
+static irqreturn_t mdm_errfatal(int irq, void *dev_id)
+{
+	pr_debug("%s: mdm got errfatal interrupt\n", __func__);
+	if (mdm_drv->mdm_ready &&
+		(gpio_get_value(mdm_drv->mdm2ap_status_gpio) == 1)) {
+		pr_debug("%s: scheduling work now\n", __func__);
+		queue_work(mdm_queue, &mdm_fatal_work);
+	}
+	return IRQ_HANDLED;
+}
+
+static int mdm_modem_open(struct inode *inode, struct file *file)
+{
+	return 0;
+}
+
+static const struct file_operations mdm_modem_fops = {
+	.owner		= THIS_MODULE,
+	.open		= mdm_modem_open,
+	.unlocked_ioctl	= mdm_modem_ioctl,
+};
+
+
+static struct miscdevice mdm_modem_misc = {
+	.minor	= MISC_DYNAMIC_MINOR,
+	.name	= "mdm",
+	.fops	= &mdm_modem_fops
+};
+
+static int mdm_panic_prep(struct notifier_block *this,
+				unsigned long event, void *ptr)
+{
+	int i;
+
+	pr_debug("%s: setting AP2MDM_ERRFATAL high for a non graceful reset\n",
+			 __func__);
+	mdm_disable_irqs();
+	gpio_set_value(mdm_drv->ap2mdm_errfatal_gpio, 1);
+
+	for (i = MDM_MODEM_TIMEOUT; i > 0; i -= MDM_MODEM_DELTA) {
+		/* pet_watchdog(); */
+		mdelay(MDM_MODEM_DELTA);
+		if (gpio_get_value(mdm_drv->mdm2ap_status_gpio) == 0)
+			break;
+	}
+	if (i <= 0)
+		pr_err("%s: MDM2AP_STATUS never went low\n", __func__);
+	return NOTIFY_DONE;
+}
+
+static struct notifier_block mdm_panic_blk = {
+	.notifier_call  = mdm_panic_prep,
+};
+
+static irqreturn_t mdm_status_change(int irq, void *dev_id)
+{
+	int value = gpio_get_value(mdm_drv->mdm2ap_status_gpio);
+	pr_err("%s: mdm sent status change interrupt : %d\n", __func__, value);
+
+	queue_work(mdm_queue, &mdm_status_work);
+
+	return IRQ_HANDLED;
+}
+
+static int mdm_subsys_shutdown(const struct subsys_data *crashed_subsys)
+{
+	pr_info("%s\n", __func__);
+	mdm_drv->mdm_ready = 0;
+	gpio_direction_output(mdm_drv->ap2mdm_errfatal_gpio, 1);
+	if (mdm_drv->pdata->ramdump_delay_ms > 0) {
+		/* Wait for the external modem to complete
+		 * its preparation for ramdumps.
+		 */
+		msleep(mdm_drv->pdata->ramdump_delay_ms);
+	}
+	mdm_drv->ops->power_down_mdm_cb(mdm_drv);
+	return 0;
+}
+
+static int mdm_subsys_powerup(const struct subsys_data *crashed_subsys)
+{
+	pr_info("%s\n", __func__);
+	gpio_direction_output(mdm_drv->ap2mdm_errfatal_gpio, 0);
+	gpio_direction_output(mdm_drv->ap2mdm_status_gpio, 1);
+	mdm_drv->ops->power_on_mdm_cb(mdm_drv);
+	mdm_drv->boot_type = CHARM_NORMAL_BOOT;
+	complete(&mdm_needs_reload);
+	if (!wait_for_completion_timeout(&mdm_boot,
+			msecs_to_jiffies(MDM_BOOT_TIMEOUT))) {
+		mdm_drv->mdm_boot_status = -ETIMEDOUT;
+		pr_info("%s: mdm modem restart timed out.\n", __func__);
+	} else
+		pr_info("%s: mdm modem has been restarted\n", __func__);
+	INIT_COMPLETION(mdm_boot);
+	return mdm_drv->mdm_boot_status;
+}
+
+static int mdm_subsys_ramdumps(int want_dumps,
+				const struct subsys_data *crashed_subsys)
+{
+	pr_info("%s\n", __func__);
+	mdm_drv->mdm_ram_dump_status = 0;
+	if (want_dumps) {
+		mdm_drv->boot_type = CHARM_RAM_DUMPS;
+		complete(&mdm_needs_reload);
+		if (!wait_for_completion_timeout(&mdm_ram_dumps,
+				msecs_to_jiffies(MDM_RDUMP_TIMEOUT))) {
+			mdm_drv->mdm_ram_dump_status = -ETIMEDOUT;
+			pr_info("%s: mdm modem ramdumps timed out.\n",
+					__func__);
+		} else
+			pr_info("%s: mdm modem ramdumps completed.\n",
+					__func__);
+		INIT_COMPLETION(mdm_ram_dumps);
+		gpio_direction_output(mdm_drv->ap2mdm_errfatal_gpio, 1);
+		mdm_drv->ops->power_down_mdm_cb(mdm_drv);
+	}
+	return mdm_drv->mdm_ram_dump_status;
+}
+
+static struct subsys_data mdm_subsystem = {
+	.shutdown = mdm_subsys_shutdown,
+	.ramdump = mdm_subsys_ramdumps,
+	.powerup = mdm_subsys_powerup,
+	.name = EXTERNAL_MODEM,
+};
+
+static int mdm_debug_on_set(void *data, u64 val)
+{
+	mdm_debug_on = val;
+	if (mdm_drv->ops->debug_state_changed_cb)
+		mdm_drv->ops->debug_state_changed_cb(mdm_debug_on);
+	return 0;
+}
+
+static int mdm_debug_on_get(void *data, u64 *val)
+{
+	*val = mdm_debug_on;
+	return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(mdm_debug_on_fops,
+			mdm_debug_on_get,
+			mdm_debug_on_set, "%llu\n");
+
+static int mdm_debugfs_init(void)
+{
+	struct dentry *dent;
+
+	dent = debugfs_create_dir("mdm_dbg", 0);
+	if (IS_ERR(dent))
+		return PTR_ERR(dent);
+
+	debugfs_create_file("debug_on", 0644, dent, NULL,
+			&mdm_debug_on_fops);
+	return 0;
+}
+
+static void mdm_modem_initialize_data(struct platform_device  *pdev,
+				struct mdm_ops *mdm_ops)
+{
+	struct resource *pres;
+
+	/* MDM2AP_ERRFATAL */
+	pres = platform_get_resource_byname(pdev, IORESOURCE_IO,
+							"MDM2AP_ERRFATAL");
+	if (pres)
+		mdm_drv->mdm2ap_errfatal_gpio = pres->start;
+
+	/* AP2MDM_ERRFATAL */
+	pres = platform_get_resource_byname(pdev, IORESOURCE_IO,
+							"AP2MDM_ERRFATAL");
+	if (pres)
+		mdm_drv->ap2mdm_errfatal_gpio = pres->start;
+
+	/* MDM2AP_STATUS */
+	pres = platform_get_resource_byname(pdev, IORESOURCE_IO,
+							"MDM2AP_STATUS");
+	if (pres)
+		mdm_drv->mdm2ap_status_gpio = pres->start;
+
+	/* AP2MDM_STATUS */
+	pres = platform_get_resource_byname(pdev, IORESOURCE_IO,
+							"AP2MDM_STATUS");
+	if (pres)
+		mdm_drv->ap2mdm_status_gpio = pres->start;
+
+	/* MDM2AP_WAKEUP */
+	pres = platform_get_resource_byname(pdev, IORESOURCE_IO,
+							"MDM2AP_WAKEUP");
+	if (pres)
+		mdm_drv->mdm2ap_wakeup_gpio = pres->start;
+
+	/* AP2MDM_WAKEUP */
+	pres = platform_get_resource_byname(pdev, IORESOURCE_IO,
+							"AP2MDM_WAKEUP");
+	if (pres)
+		mdm_drv->ap2mdm_wakeup_gpio = pres->start;
+
+	/* AP2MDM_PMIC_RESET_N */
+	pres = platform_get_resource_byname(pdev, IORESOURCE_IO,
+							"AP2MDM_PMIC_RESET_N");
+	if (pres)
+		mdm_drv->ap2mdm_pmic_reset_n_gpio = pres->start;
+
+	/* AP2MDM_KPDPWR_N */
+	pres = platform_get_resource_byname(pdev, IORESOURCE_IO,
+							"AP2MDM_KPDPWR_N");
+	if (pres)
+		mdm_drv->ap2mdm_kpdpwr_n_gpio = pres->start;
+
+	mdm_drv->boot_type                  = CHARM_NORMAL_BOOT;
+
+	mdm_drv->ops      = mdm_ops;
+	mdm_drv->pdata    = pdev->dev.platform_data;
+}
+
+int mdm_common_create(struct platform_device  *pdev,
+					  struct mdm_ops *p_mdm_cb)
+{
+	int ret = -1, irq;
+	pr_err("%s\n", __func__);
+
+	mdm_drv = kzalloc(sizeof(struct mdm_modem_drv), GFP_KERNEL);
+	if (mdm_drv == NULL) {
+		pr_err("%s: kzalloc fail.\n", __func__);
+		goto alloc_err;
+	}
+
+	mdm_modem_initialize_data(pdev, p_mdm_cb);
+	if (mdm_drv->ops->debug_state_changed_cb)
+		mdm_drv->ops->debug_state_changed_cb(mdm_debug_on);
+
+	gpio_request(mdm_drv->ap2mdm_status_gpio, "AP2MDM_STATUS");
+	gpio_request(mdm_drv->ap2mdm_errfatal_gpio, "AP2MDM_ERRFATAL");
+	gpio_request(mdm_drv->ap2mdm_kpdpwr_n_gpio, "AP2MDM_KPDPWR_N");
+	gpio_request(mdm_drv->ap2mdm_pmic_reset_n_gpio, "AP2MDM_PMIC_RESET_N");
+	gpio_request(mdm_drv->mdm2ap_status_gpio, "MDM2AP_STATUS");
+	gpio_request(mdm_drv->mdm2ap_errfatal_gpio, "MDM2AP_ERRFATAL");
+
+	if (mdm_drv->ap2mdm_wakeup_gpio > 0)
+		gpio_request(mdm_drv->ap2mdm_wakeup_gpio, "AP2MDM_WAKEUP");
+
+#ifdef CONFIG_ARCH_EXYNOS
+	gpio_set_value(mdm_drv->ap2mdm_status_gpio, 1);
+	s3c_gpio_cfgpin(mdm_drv->ap2mdm_status_gpio, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(mdm_drv->ap2mdm_status_gpio, S3C_GPIO_PULL_UP);
+#endif
+	gpio_direction_output(mdm_drv->ap2mdm_status_gpio, 1);
+	pr_err("%s> : right after ap2mdm_status = %d\n", __func__,
+				gpio_get_value(mdm_drv->ap2mdm_status_gpio));
+
+#ifdef CONFIG_ARCH_EXYNOS
+	gpio_set_value(mdm_drv->ap2mdm_errfatal_gpio, 0);
+	s3c_gpio_cfgpin(mdm_drv->ap2mdm_errfatal_gpio, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(mdm_drv->ap2mdm_errfatal_gpio, S3C_GPIO_PULL_DOWN);
+#endif
+	gpio_direction_output(mdm_drv->ap2mdm_errfatal_gpio, 0);
+	pr_err("%s>> : right after ap2mdm_status = %d\n", __func__,
+				gpio_get_value(mdm_drv->ap2mdm_status_gpio));
+
+	if (mdm_drv->ap2mdm_wakeup_gpio > 0)
+		gpio_direction_output(mdm_drv->ap2mdm_wakeup_gpio, 0);
+
+	gpio_direction_input(mdm_drv->mdm2ap_status_gpio);
+	gpio_direction_input(mdm_drv->mdm2ap_errfatal_gpio);
+
+	mdm_queue = create_singlethread_workqueue("mdm_queue");
+	if (!mdm_queue) {
+		pr_err("%s: could not create workqueue. All mdm "
+				"functionality will be disabled\n",
+			__func__);
+		ret = -ENOMEM;
+		goto fatal_err;
+	}
+
+	atomic_notifier_chain_register(&panic_notifier_list, &mdm_panic_blk);
+	mdm_debugfs_init();
+
+	/* Register subsystem handlers */
+	ssr_register_subsystem(&mdm_subsystem);
+
+	/* ERR_FATAL irq. */
+#ifdef CONFIG_ARCH_EXYNOS
+	irq = gpio_to_irq(mdm_drv->mdm2ap_errfatal_gpio);
+#else
+	irq = MSM_GPIO_TO_INT(mdm_drv->mdm2ap_errfatal_gpio);
+#endif
+	if (irq < 0) {
+		pr_err("%s: could not get MDM2AP_ERRFATAL IRQ resource. "
+			"error=%d No IRQ will be generated on errfatal.",
+			__func__, irq);
+		goto errfatal_err;
+	}
+	ret = request_irq(irq, mdm_errfatal,
+		IRQF_TRIGGER_RISING , "mdm errfatal", NULL);
+
+	if (ret < 0) {
+		pr_err("%s: MDM2AP_ERRFATAL IRQ#%d request failed with error=%d"
+			". No IRQ will be generated on errfatal.",
+			__func__, irq, ret);
+		goto errfatal_err;
+	}
+	mdm_drv->mdm_errfatal_irq = irq;
+
+errfatal_err:
+
+	/* status irq */
+#ifdef CONFIG_ARCH_EXYNOS
+	ret = s5p_register_gpio_interrupt(mdm_drv->mdm2ap_status_gpio);
+	if (ret)
+		pr_err("%s: register MDM2AP_STATUS ret = %d\n", __func__, ret);
+	irq = gpio_to_irq(mdm_drv->mdm2ap_status_gpio);
+#else
+	irq = MSM_GPIO_TO_INT(mdm_drv->mdm2ap_status_gpio);
+#endif
+	if (irq < 0) {
+		pr_err("%s: could not get MDM2AP_STATUS IRQ resource. "
+			"error=%d No IRQ will be generated on status change.",
+			__func__, irq);
+		goto status_err;
+	}
+
+	ret = request_threaded_irq(irq, NULL, mdm_status_change,
+		IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_SHARED,
+		"mdm status", mdm_drv);
+
+	if (ret < 0) {
+		pr_err("%s: MDM2AP_STATUS IRQ#%d request failed with error=%d"
+			". No IRQ will be generated on status change.",
+			__func__, irq, ret);
+		goto status_err;
+	}
+	mdm_drv->mdm_status_irq = irq;
+
+status_err:
+	/* Perform early powerup of the external modem in order to
+	 * allow tabla devices to be found.
+	 */
+	mdm_drv->ops->power_on_mdm_cb(mdm_drv);
+	pr_err("%s : ap2mdm_status = %d\n", __func__,
+				gpio_get_value(mdm_drv->ap2mdm_status_gpio));
+
+	pr_info("%s: Registering mdm modem\n", __func__);
+	return misc_register(&mdm_modem_misc);
+
+fatal_err:
+	gpio_free(mdm_drv->ap2mdm_status_gpio);
+	gpio_free(mdm_drv->ap2mdm_errfatal_gpio);
+	gpio_free(mdm_drv->ap2mdm_kpdpwr_n_gpio);
+	gpio_free(mdm_drv->ap2mdm_pmic_reset_n_gpio);
+	gpio_free(mdm_drv->mdm2ap_status_gpio);
+	gpio_free(mdm_drv->mdm2ap_errfatal_gpio);
+
+	if (mdm_drv->ap2mdm_wakeup_gpio > 0)
+		gpio_free(mdm_drv->ap2mdm_wakeup_gpio);
+
+	kfree(mdm_drv);
+	ret = -ENODEV;
+
+alloc_err:
+	return ret;
+}
+
+int mdm_common_modem_remove(struct platform_device *pdev)
+{
+	int ret;
+
+	gpio_free(mdm_drv->ap2mdm_status_gpio);
+	gpio_free(mdm_drv->ap2mdm_errfatal_gpio);
+	gpio_free(mdm_drv->ap2mdm_kpdpwr_n_gpio);
+	gpio_free(mdm_drv->ap2mdm_pmic_reset_n_gpio);
+	gpio_free(mdm_drv->mdm2ap_status_gpio);
+	gpio_free(mdm_drv->mdm2ap_errfatal_gpio);
+
+	if (mdm_drv->ap2mdm_wakeup_gpio > 0)
+		gpio_free(mdm_drv->ap2mdm_wakeup_gpio);
+
+	kfree(mdm_drv);
+
+	ret = misc_deregister(&mdm_modem_misc);
+	return ret;
+}
+
+void mdm_common_modem_shutdown(struct platform_device *pdev)
+{
+	mdm_disable_irqs();
+
+	mdm_drv->ops->power_down_mdm_cb(mdm_drv);
+}
+
diff --git a/arch/arm/mach-exynos/mdm_device.c b/arch/arm/mach-exynos/mdm_device.c
new file mode 100644
index 0000000..22be1d5
--- /dev/null
+++ b/arch/arm/mach-exynos/mdm_device.c
@@ -0,0 +1,64 @@
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <mach/gpio-exynos4.h>
+#include <plat/gpio-cfg.h>
+#include <plat/devs.h>
+#include <plat/ehci.h>
+#include <linux/msm_charm.h>
+#include <mach/mdm2.h>
+#include "mdm_private.h"
+
+static struct resource mdm_resources[] = {
+	{
+		.start	= MDM2AP_ERRFATAL,
+		.end	= MDM2AP_ERRFATAL,
+		.name	= "MDM2AP_ERRFATAL",
+		.flags	= IORESOURCE_IO,
+	},
+	{
+		.start	= AP2MDM_ERRFATAL,
+		.end	= AP2MDM_ERRFATAL,
+		.name	= "AP2MDM_ERRFATAL",
+		.flags	= IORESOURCE_IO,
+	},
+	{
+		.start	= MDM2AP_STATUS,
+		.end	= MDM2AP_STATUS,
+		.name	= "MDM2AP_STATUS",
+		.flags	= IORESOURCE_IO,
+	},
+	{
+		.start	= AP2MDM_STATUS,
+		.end	= AP2MDM_STATUS,
+		.name	= "AP2MDM_STATUS",
+		.flags	= IORESOURCE_IO,
+	},
+	{
+		.start	= AP2MDM_PMIC_RESET_N,
+		.end	= AP2MDM_PMIC_RESET_N,
+		.name	= "AP2MDM_PMIC_RESET_N",
+		.flags	= IORESOURCE_IO,
+	},
+};
+
+static struct mdm_platform_data mdm_platform_data = {
+	.mdm_version = "3.0",
+	.ramdump_delay_ms = 2000,
+	.peripheral_platform_device = &s5p_device_ehci,
+};
+
+struct platform_device mdm_device = {
+	.name		= "mdm2_modem",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(mdm_resources),
+	.resource	= mdm_resources,
+};
+
+static int __init init_mdm_modem(void)
+{
+	pr_err("%s	!!!	!!\n", __func__);
+	mdm_device.dev.platform_data = &mdm_platform_data;
+	return platform_device_register(&mdm_device);
+}
+module_init(init_mdm_modem);
diff --git a/arch/arm/mach-exynos/mdm_private.h b/arch/arm/mach-exynos/mdm_private.h
new file mode 100644
index 0000000..206bd8b
--- /dev/null
+++ b/arch/arm/mach-exynos/mdm_private.h
@@ -0,0 +1,56 @@
+/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _ARCH_ARM_MACH_MSM_MDM_PRIVATE_H
+#define _ARCH_ARM_MACH_MSM_MDM_PRIVATE_H
+
+struct mdm_modem_drv;
+
+struct mdm_ops {
+	void (*power_on_mdm_cb)(struct mdm_modem_drv *mdm_drv);
+	void (*normal_boot_done_cb)(struct mdm_modem_drv *mdm_drv);
+	void (*power_down_mdm_cb)(struct mdm_modem_drv *mdm_drv);
+	void (*debug_state_changed_cb)(int value);
+	void (*status_cb)(struct mdm_modem_drv *mdm_drv, int value);
+};
+
+/* Private mdm2 data structure */
+struct mdm_modem_drv {
+	unsigned mdm2ap_errfatal_gpio;
+	unsigned ap2mdm_errfatal_gpio;
+	unsigned mdm2ap_status_gpio;
+	unsigned ap2mdm_status_gpio;
+	unsigned mdm2ap_wakeup_gpio;
+	unsigned ap2mdm_wakeup_gpio;
+	unsigned ap2mdm_pmic_reset_n_gpio;
+	unsigned ap2mdm_kpdpwr_n_gpio;
+
+	int mdm_errfatal_irq;
+	int mdm_status_irq;
+	int mdm_ready;
+	int mdm_boot_status;
+	int mdm_ram_dump_status;
+	enum charm_boot_type boot_type;
+	int mdm_debug_on;
+
+	struct mdm_ops *ops;
+	struct mdm_platform_data *pdata;
+};
+
+int mdm_common_create(struct platform_device  *pdev,
+					  struct mdm_ops *mdm_cb);
+int mdm_common_modem_remove(struct platform_device *pdev);
+void mdm_common_modem_shutdown(struct platform_device *pdev);
+void mdm_common_set_debug_state(int value);
+
+#endif
+
diff --git a/arch/arm/mach-exynos/midas-camera.c b/arch/arm/mach-exynos/midas-camera.c
new file mode 100644
index 0000000..587a9be
--- /dev/null
+++ b/arch/arm/mach-exynos/midas-camera.c
@@ -0,0 +1,3450 @@
+/*
+ * camera class init
+ */
+
+#include <linux/gpio.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/clk.h>
+#include <linux/vmalloc.h>
+#include <media/v4l2-device.h>
+#include <linux/vmalloc.h>
+#include <linux/firmware.h>
+#include <linux/regulator/machine.h>
+#include <linux/init.h>
+
+#include <plat/devs.h>
+#include <plat/csis.h>
+#include <plat/pd.h>
+#include <plat/gpio-cfg.h>
+#ifdef CONFIG_VIDEO_SAMSUNG_S5P_FIMC
+#include <plat/fimc-core.h>
+#include <media/s5p_fimc.h>
+#endif
+
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_LITE
+#include <media/exynos_flite.h>
+#endif
+
+#if defined(CONFIG_VIDEO_S5C73M3) || defined(CONFIG_VIDEO_SLP_S5C73M3)
+#include <media/s5c73m3_platform.h>
+#endif
+
+#if defined(CONFIG_VIDEO_M5MO)
+#include <mach/regs-gpio.h>
+#include <media/m5mo_platform.h>
+#endif
+
+#if defined(CONFIG_VIDEO_M9MO)
+#include <mach/regs-gpio.h>
+#include <media/m9mo_platform.h>
+#endif
+
+#if defined(CONFIG_VIDEO_ISX012)
+#include <media/isx012_platform.h>
+#endif
+#if defined(CONFIG_VIDEO_S5K5CCGX_COMMON)
+#include <media/s5k5ccgx_platform.h>
+#endif
+
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+#include <mach/secmem.h>
+#endif
+
+#ifdef CONFIG_VIDEO_SR200PC20M
+#include <media/sr200pc20m_platform.h>
+#endif
+
+#ifdef CONFIG_VIDEO_SR200PC20
+#include <media/sr200pc20_platform.h>
+#endif
+
+struct class *camera_class;
+
+static int __init camera_class_init(void)
+{
+	camera_class = class_create(THIS_MODULE, "camera");
+	if (IS_ERR(camera_class)) {
+		pr_err("Failed to create class(camera)!\n");
+		return PTR_ERR(camera_class);
+	}
+
+	return 0;
+}
+
+subsys_initcall(camera_class_init);
+
+#if defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT)
+#define FRONT_CAM_MCLK_DEVIDED_REVISION	0x06
+#define USE_8M_CAM_SENSOR_CORE_REVISION	0x09
+#elif defined(CONFIG_MACH_C1_KOR_LGT)
+#define FRONT_CAM_MCLK_DEVIDED_REVISION	0x04
+#define USE_8M_CAM_SENSOR_CORE_REVISION	0x07
+#elif defined(CONFIG_MACH_C1_USA_ATT)
+#define FRONT_CAM_MCLK_DEVIDED_REVISION	0x05
+#elif defined(CONFIG_MACH_C1VZW)
+#define FRONT_CAM_MCLK_DEVIDED_REVISION	0x0A
+#else
+#define FRONT_CAM_MCLK_DEVIDED_REVISION	0x08
+#endif
+
+#if defined(CONFIG_VIDEO_FIMC)
+/*
+ * External camera reset
+ * Because the most of cameras take i2c bus signal, so that
+ * you have to reset at the boot time for other i2c slave devices.
+ * This function also called at fimc_init_camera()
+ * Do optimization for cameras on your platform.
+ */
+
+#define CAM_CHECK_ERR_RET(x, msg)					\
+	if (unlikely((x) < 0)) {					\
+		printk(KERN_ERR "\nfail to %s: err = %d\n", msg, x);	\
+		return x;						\
+	}
+#define CAM_CHECK_ERR(x, msg)						\
+	if (unlikely((x) < 0)) {					\
+		printk(KERN_ERR "\nfail to %s: err = %d\n", msg, x);	\
+	}
+#define CAM_CHECK_ERR_GOTO(x, out, fmt, ...) \
+	if (unlikely((x) < 0)) { \
+		printk(KERN_ERR fmt, ##__VA_ARGS__); \
+		goto out; \
+	}
+
+int s3c_csis_power(int enable)
+{
+	struct regulator *regulator;
+	int ret = 0;
+
+	/* mipi_1.1v ,mipi_1.8v are always powered-on.
+	 * If they are off, we then power them on.
+	 */
+	if (enable) {
+		/* VMIPI_1.0V */
+		regulator = regulator_get(NULL, "vmipi_1.0v");
+		if (IS_ERR(regulator))
+			goto error_out;
+		regulator_enable(regulator);
+		regulator_put(regulator);
+
+		/* VMIPI_1.8V */
+		regulator = regulator_get(NULL, "vmipi_1.8v");
+		if (IS_ERR(regulator))
+			goto error_out;
+		regulator_enable(regulator);
+		regulator_put(regulator);
+
+		printk(KERN_WARNING "%s: vmipi_1.0v and vmipi_1.8v were ON\n",
+		       __func__);
+	} else {
+		/* VMIPI_1.8V */
+		regulator = regulator_get(NULL, "vmipi_1.8v");
+		if (IS_ERR(regulator))
+			goto error_out;
+		if (regulator_is_enabled(regulator)) {
+			printk(KERN_WARNING "%s: vmipi_1.8v is on. so OFF\n",
+			       __func__);
+			ret = regulator_disable(regulator);
+		}
+		regulator_put(regulator);
+
+		/* VMIPI_1.0V */
+		regulator = regulator_get(NULL, "vmipi_1.0v");
+		if (IS_ERR(regulator))
+			goto error_out;
+		if (regulator_is_enabled(regulator)) {
+			printk(KERN_WARNING "%s: vmipi_1.1v is on. so OFF\n",
+			       __func__);
+			ret = regulator_disable(regulator);
+		}
+		regulator_put(regulator);
+
+		printk(KERN_WARNING "%s: vmipi_1.0v and vmipi_1.8v were OFF\n",
+		       __func__);
+	}
+
+	return 0;
+
+error_out:
+	printk(KERN_ERR "%s: ERROR: failed to check mipi-power\n", __func__);
+	return 0;
+}
+
+#ifdef CONFIG_WRITEBACK_ENABLED
+#define WRITEBACK_ENABLED
+#endif
+#ifdef WRITEBACK_ENABLED
+static int get_i2c_busnum_writeback(void)
+{
+	return 0;
+}
+
+static struct i2c_board_info writeback_i2c_info = {
+	I2C_BOARD_INFO("WriteBack", 0x0),
+};
+
+static struct s3c_platform_camera writeback = {
+	.id		= CAMERA_WB,
+	.fmt		= ITU_601_YCBCR422_8BIT,
+	.order422	= CAM_ORDER422_8BIT_CBYCRY,
+	.get_i2c_busnum = get_i2c_busnum_writeback,
+	.info		= &writeback_i2c_info,
+	.pixelformat	= V4L2_PIX_FMT_YUV444,
+	.line_length	= 1280,
+	.width		= 720,
+	.height		= 1280,
+	.window		= {
+		.left	= 0,
+		.top	= 0,
+		.width	= 720,
+		.height	= 1280,
+	},
+
+	.initialized	= 0,
+};
+#endif
+
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_IS
+#ifdef CONFIG_VIDEO_S5K6A3
+#ifdef CONFIG_MACH_P4NOTE
+/* For P4Note PegasusQ */
+static int s5k6a3_power_on(void)
+{
+	struct regulator *regulator;
+	int ret = 0;
+
+	printk(KERN_DEBUG "%s: in\n", __func__);
+
+	ret = gpio_request(GPIO_VT_CAM_nRST, "GPJ1");
+	if (unlikely(ret)) {
+		printk(KERN_ERR "request GPIO_VT_CAM_nRST\n");
+		return ret;
+	}
+
+	/* VT_CAM_2.8V */
+	regulator = regulator_get(NULL, "cam_a2.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "cam_a2.8v");
+	udelay(100);
+
+	/* MCLK */
+	ret = s3c_gpio_cfgpin(GPIO_VTCAM_MCLK, S3C_GPIO_SFN(3));
+	s3c_gpio_setpull(GPIO_VTCAM_MCLK, S3C_GPIO_PULL_NONE);
+	CAM_CHECK_ERR_RET(ret, "cfg mclk");
+	udelay(1);
+
+	/* VT_CAM_1.8V */
+	regulator = regulator_get(NULL, "vt_core_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "vt_core_1.8v");
+	udelay(1000);
+
+	/* VT_CAM_nRST */
+	ret = gpio_direction_output(GPIO_VT_CAM_nRST, 1);
+	CAM_CHECK_ERR_RET(ret, "GPIO_VT_CAM_nRST");
+	udelay(600);
+
+	ret = gpio_direction_output(GPIO_VT_CAM_nRST, 0);
+	CAM_CHECK_ERR_RET(ret, "GPIO_VT_CAM_nRST");
+	udelay(600);
+
+	ret = gpio_direction_output(GPIO_VT_CAM_nRST, 1);
+	CAM_CHECK_ERR_RET(ret, "GPIO_VT_CAM_nRST");
+
+	gpio_free(GPIO_VT_CAM_nRST);
+
+	return ret;
+}
+
+static int s5k6a3_power_down(void)
+{
+	struct regulator *regulator;
+	int ret = 0;
+
+	printk(KERN_DEBUG "%s: in\n", __func__);
+
+	ret = gpio_request(GPIO_VT_CAM_nRST, "GPJ1");
+	if (unlikely(ret)) {
+		printk(KERN_ERR "request GPIO_VT_CAM_nRST\n");
+		return ret;
+	}
+
+	/* VT_CAM_nRST */
+	ret = gpio_direction_output(GPIO_VT_CAM_nRST, 0);
+	CAM_CHECK_ERR_RET(ret, "GPIO_VT_CAM_nRST");
+
+	/* VT_CAM_1.8V */
+	regulator = regulator_get(NULL, "vt_core_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "vt_core_1.8v");
+
+
+	/* VT_CAM_2.8V */
+	regulator = regulator_get(NULL, "cam_a2.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "cam_a2.8v");
+	udelay(100);
+
+	/* MCLK */
+	ret = s3c_gpio_cfgpin(GPIO_VTCAM_MCLK, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_VTCAM_MCLK, S3C_GPIO_PULL_DOWN);
+	CAM_CHECK_ERR_RET(ret, "cfg mclk");
+	udelay(1);
+
+	gpio_free(GPIO_VT_CAM_nRST);
+
+	return ret;
+}
+#else /* !CONFIG_MACH_P4NOTE */
+static int s5k6a3_gpio_request(void)
+{
+	int ret = 0;
+
+	/* SENSOR_A2.8V */
+	ret = gpio_request(GPIO_CAM_IO_EN, "GPM0");
+	if (ret) {
+		printk(KERN_ERR "fail to request gpio(GPIO_CAM_IO_EN)\n");
+		return ret;
+	}
+
+	if (system_rev <= FRONT_CAM_MCLK_DEVIDED_REVISION)
+		ret = gpio_request(GPIO_CAM_MCLK, "GPJ1");
+	else
+		ret = gpio_request(GPIO_VTCAM_MCLK, "GPM2");
+	if (ret) {
+		printk(KERN_ERR "fail to request gpio(GPIO_VTCAM_MCLK)\n");
+		return ret;
+	}
+
+	ret = gpio_request(GPIO_CAM_VT_nRST, "GPM1");
+	if (ret) {
+		printk(KERN_ERR "fail to request gpio(GPIO_CAM_VT_nRST)\n");
+		return ret;
+	}
+
+	return ret;
+}
+
+static int s5k6a3_power_on(void)
+{
+	struct regulator *regulator;
+	int ret = 0;
+
+	printk(KERN_DEBUG "%s: in\n", __func__);
+
+	s5k6a3_gpio_request();
+
+	/* CAM_SENSOR_A2.8V */
+	ret = gpio_direction_output(GPIO_CAM_IO_EN, 1);
+	CAM_CHECK_ERR_RET(ret, "output GPIO_CAM_IO_EN");
+	/* delay is needed : external LDO control is slower than MCLK control*/
+	udelay(100);
+
+	/* MCLK */
+	if (system_rev <= FRONT_CAM_MCLK_DEVIDED_REVISION) {
+		ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_NONE);
+		s5p_gpio_set_drvstr(GPIO_CAM_MCLK, S5P_GPIO_DRVSTR_LV2);
+	} else {
+		ret = s3c_gpio_cfgpin(GPIO_VTCAM_MCLK, S3C_GPIO_SFN(3));
+		s3c_gpio_setpull(GPIO_VTCAM_MCLK, S3C_GPIO_PULL_NONE);
+		s5p_gpio_set_drvstr(GPIO_VTCAM_MCLK, S5P_GPIO_DRVSTR_LV2);
+	}
+	CAM_CHECK_ERR_RET(ret, "cfg mclk");
+
+	/* VT_CORE_1.8V */
+	regulator = regulator_get(NULL, "vt_cam_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "enable vt_cam_1.8v");
+	udelay(1000);
+
+	/* VT_RESET */
+	ret = gpio_direction_output(GPIO_CAM_VT_nRST, 1);
+	CAM_CHECK_ERR_RET(ret, "output GPIO_CAM_VT_nRST");
+	udelay(600);
+
+	ret = gpio_direction_output(GPIO_CAM_VT_nRST, 0);
+	CAM_CHECK_ERR_RET(ret, "output GPIO_CAM_VT_nRST");
+	udelay(600);
+
+	ret = gpio_direction_output(GPIO_CAM_VT_nRST, 1);
+	CAM_CHECK_ERR_RET(ret, "output GPIO_CAM_VT_nRST");
+
+	gpio_free(GPIO_CAM_IO_EN);
+	gpio_free(GPIO_CAM_VT_nRST);
+	if (system_rev <= FRONT_CAM_MCLK_DEVIDED_REVISION)
+		gpio_free(GPIO_CAM_MCLK);
+	else
+		gpio_free(GPIO_VTCAM_MCLK);
+
+	return ret;
+}
+
+static int s5k6a3_power_down(void)
+{
+	struct regulator *regulator;
+	int ret = 0;
+
+	printk(KERN_DEBUG "%s: in\n", __func__);
+
+	s5k6a3_gpio_request();
+
+	/* VT_RESET */
+	ret = gpio_direction_output(GPIO_CAM_VT_nRST, 0);
+	CAM_CHECK_ERR_RET(ret, "output GPIO_CAM_VT_nRST");
+
+	/* VT_CORE_1.8V */
+	regulator = regulator_get(NULL, "vt_cam_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "disable vt_cam_1.8v");
+
+	/* CAM_SENSOR_A2.8V */
+	ret = gpio_direction_output(GPIO_CAM_IO_EN, 0);
+	CAM_CHECK_ERR_RET(ret, "output GPIO_CAM_IO_EN");
+	/* delay is needed : external LDO control is slower than MCLK control*/
+	udelay(500);
+
+	/* MCLK */
+	if (system_rev <= FRONT_CAM_MCLK_DEVIDED_REVISION) {
+		ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_INPUT);
+		s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_DOWN);
+
+	} else {
+		ret = s3c_gpio_cfgpin(GPIO_VTCAM_MCLK, S3C_GPIO_INPUT);
+		s3c_gpio_setpull(GPIO_VTCAM_MCLK, S3C_GPIO_PULL_DOWN);
+	}
+	CAM_CHECK_ERR(ret, "cfg mclk");
+
+	gpio_free(GPIO_CAM_IO_EN);
+	gpio_free(GPIO_CAM_VT_nRST);
+
+	if (system_rev <= FRONT_CAM_MCLK_DEVIDED_REVISION)
+		gpio_free(GPIO_CAM_MCLK);
+	else
+		gpio_free(GPIO_VTCAM_MCLK);
+
+	return ret;
+}
+#endif /* CONFIG_MACH_P4NOTE */
+
+static int s5k6a3_power(int enable)
+{
+	int ret = 0;
+
+	if (enable) {
+		ret = s5k6a3_power_on();
+		if (unlikely(ret)) {
+			printk(KERN_ERR "%s: power-on fail\n", __func__);
+			goto error_out;
+		}
+	} else
+		ret = s5k6a3_power_down();
+
+	ret = s3c_csis_power(enable);
+
+error_out:
+	return ret;
+}
+
+static const char *s5k6a3_get_clk_name(void)
+{
+#ifdef CONFIG_MACH_P4NOTE
+	return "sclk_cam1";
+#else
+	if (system_rev <= FRONT_CAM_MCLK_DEVIDED_REVISION)
+		return "sclk_cam0";
+	else
+		return "sclk_cam1";
+#endif
+}
+
+static struct s3c_platform_camera s5k6a3 = {
+	.id		= CAMERA_CSI_D,
+	.get_clk_name = s5k6a3_get_clk_name,
+	.cam_power	= s5k6a3_power,
+	.type		= CAM_TYPE_MIPI,
+	.fmt		= MIPI_CSI_RAW10,
+	.order422	= CAM_ORDER422_8BIT_YCBYCR,
+	.pixelformat	= V4L2_PIX_FMT_UYVY,
+	.line_length	= 1920,
+	.width		= 1920,
+	.height		= 1080,
+	.window		= {
+		.left	= 0,
+		.top	= 0,
+		.width	= 1920,
+		.height	= 1080,
+	},
+	.srclk_name	= "xusbxti",
+	.clk_rate	= 24000000,
+	.mipi_lanes	= 1,
+	.mipi_settle	= 18,
+	.mipi_align	= 24,
+
+	.initialized	= 0,
+	.flite_id	= FLITE_IDX_B,
+	.use_isp	= true,
+	.sensor_index	= 102,
+};
+
+#ifdef CONFIG_S5K6A3_CSI_D
+static struct s3c_platform_camera s5k6a3_fd = {
+	.id		= CAMERA_CSI_D,
+	.get_clk_name = s5k6a3_get_clk_name,
+	.cam_power	= s5k6a3_power,
+	.type		= CAM_TYPE_MIPI,
+	.fmt		= MIPI_CSI_RAW10,
+	.order422	= CAM_ORDER422_8BIT_YCBYCR,
+	.pixelformat	= V4L2_PIX_FMT_UYVY,
+	.line_length	= 1920,
+	.width		= 1920,
+	.height		= 1080,
+	.window		= {
+		.left	= 0,
+		.top	= 0,
+		.width	= 1920,
+		.height	= 1080,
+	},
+	.srclk_name	= "xusbxti",
+	.clk_rate	= 24000000,
+	.mipi_lanes	= 1,
+	.mipi_settle	= 18,
+	.mipi_align	= 24,
+
+	.initialized	= 0,
+	.flite_id	= FLITE_IDX_B,
+	.use_isp	= true,
+	.sensor_index	= 200,
+};
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_VIDEO_S5C73M3) || defined(CONFIG_VIDEO_SLP_S5C73M3)
+static int vddCore = 1150000;
+static bool isVddCoreSet;
+static void s5c73m3_set_vdd_core(int level)
+{
+	vddCore = level;
+	isVddCoreSet = true;
+	printk(KERN_ERR "%s : %d\n", __func__, vddCore);
+}
+
+static void s5c73m3_check_vdd_core(void)
+{
+	struct file *fp;
+	mm_segment_t old_fs;
+	u8 *buf = NULL;
+	int err = 0;
+	int nread = 0;
+	int voltage = 0;
+	int count = 0;
+
+	if (!isVddCoreSet) {
+		old_fs = get_fs();
+		set_fs(KERNEL_DS);
+
+		fp = filp_open("/data/ISP_CV", O_RDONLY, 0);
+		if (IS_ERR(fp)) {
+			printk(KERN_ERR "failed open file. :: %ld\n",
+				PTR_ERR(fp));
+			set_fs(old_fs);
+			return;
+		}
+
+		buf = vmalloc(10);
+		if (!buf) {
+			printk(KERN_ERR "failed to allocate memory\n");
+			err = -ENOMEM;
+			goto out;
+		}
+
+		nread = vfs_read(fp, (char __user *)buf, 10, &fp->f_pos);
+		if (nread != 10) {
+			printk(KERN_ERR "failed to read file, %d Bytes\n",
+				nread);
+			err = -EIO;
+			goto out;
+		}
+
+		while (buf[count] != '\0' &&
+			buf[count] >= '0' && buf[count] <= '9') {
+			voltage = voltage * 10 + buf[count] - '0';
+			++count;
+		}
+
+		if (voltage == 1000000 || voltage == 1050000 ||
+		voltage == 1100000 || voltage == 1150000) {
+			printk(KERN_ERR "@@@@ Voltage = %d", voltage);
+			vddCore = voltage;
+			/*isVddCoreSet = true;*/
+		}
+out:
+		if (buf != NULL)
+			vfree(buf);
+
+		if (fp !=  NULL)
+			filp_close(fp, current->files);
+
+		set_fs(old_fs);
+	}
+}
+static bool s5c73m3_is_vdd_core_set(void)
+{
+	return isVddCoreSet;
+}
+
+static int s5c73m3_is_isp_reset(void)
+{
+	int ret = 0;
+
+		ret = gpio_request(GPIO_ISP_RESET, "GPF1");
+	if (ret) {
+		printk(KERN_ERR "faile to request gpio(GPIO_ISP_RESET)\n");
+		return ret;
+	}
+
+	/* ISP_RESET */
+	ret = gpio_direction_output(GPIO_ISP_RESET, 0);
+	CAM_CHECK_ERR_RET(ret, "output GPIO_ISP_RESET");
+	udelay(10);	/* 200 cycle */
+	ret = gpio_direction_output(GPIO_ISP_RESET, 1);
+	CAM_CHECK_ERR_RET(ret, "output GPIO_ISP_RESET");
+	udelay(10);	/* 200 cycle */
+
+	gpio_free(GPIO_ISP_RESET);
+
+	return ret;
+}
+
+static int s5c73m3_gpio_request(void)
+{
+	int ret = 0;
+
+	ret = gpio_request(GPIO_ISP_STANDBY, "GPM0");
+	if (ret) {
+		printk(KERN_ERR "faile to request gpio(GPIO_ISP_STANDBY)\n");
+		return ret;
+	}
+
+	ret = gpio_request(GPIO_ISP_RESET, "GPF1");
+	if (ret) {
+		printk(KERN_ERR "faile to request gpio(GPIO_ISP_RESET)\n");
+		return ret;
+	}
+
+	/* SENSOR_A2.8V */
+	ret = gpio_request(GPIO_CAM_IO_EN, "GPM0");
+	if (ret) {
+		printk(KERN_ERR "fail to request gpio(GPIO_CAM_IO_EN)\n");
+		return ret;
+	}
+
+	ret = gpio_request(GPIO_CAM_AF_EN, "GPM0");
+	if (ret) {
+		printk(KERN_ERR "faile to request gpio(GPIO_CAM_AF_EN)\n");
+		return ret;
+	}
+
+	ret = gpio_request(GPIO_ISP_CORE_EN, "GPM0");
+	if (ret) {
+		printk(KERN_ERR "fail to request gpio(GPIO_ISP_CORE_EN)\n");
+		return ret;
+	}
+
+#if defined(CONFIG_MACH_C1) && defined(CONFIG_TARGET_LOCALE_KOR)
+	if (system_rev >= USE_8M_CAM_SENSOR_CORE_REVISION) {
+		ret = gpio_request(GPIO_CAM_SENSOR_CORE_EN, "GPM0");
+		if (ret) {
+			printk(KERN_ERR "fail to request gpio(GPIO_CAM_SENSOR_CORE_EN)\n");
+			return ret;
+		}
+	}
+#endif
+
+	return ret;
+}
+
+static void s5c73m3_gpio_free(void)
+{
+	gpio_free(GPIO_ISP_STANDBY);
+	gpio_free(GPIO_ISP_RESET);
+	gpio_free(GPIO_CAM_IO_EN);
+	gpio_free(GPIO_CAM_AF_EN);
+	gpio_free(GPIO_ISP_CORE_EN);
+
+#if defined(CONFIG_MACH_C1) && defined(CONFIG_TARGET_LOCALE_KOR)
+	if (system_rev >= USE_8M_CAM_SENSOR_CORE_REVISION)
+		gpio_free(GPIO_CAM_SENSOR_CORE_EN);
+#endif
+}
+
+static int s5c73m3_power_on(void)
+{
+	struct regulator *regulator;
+	int ret = 0;
+
+	printk(KERN_DEBUG "%s: in\n", __func__);
+
+#ifndef CONFIG_VIDEO_SLP_S5C73M3
+	s5c73m3_check_vdd_core();
+#endif
+	printk(KERN_DEBUG "s5c73m3 vddCore : %d\n", vddCore);
+
+	s5c73m3_gpio_request();
+
+	/* CAM_ISP_CORE_1.2V */
+	ret = gpio_direction_output(GPIO_ISP_CORE_EN, 1);
+	CAM_CHECK_ERR_RET(ret, "output GPIO_ISP_CORE_EN");
+
+	regulator = regulator_get(NULL, "cam_isp_core_1.2v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	regulator_set_voltage(regulator, vddCore, vddCore);
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "enable cam_isp_core_1.2v");
+
+	/* CAM_SENSOR_A2.8V */
+	ret = gpio_direction_output(GPIO_CAM_IO_EN, 1);
+	CAM_CHECK_ERR_RET(ret, "output IO_EN");
+
+	/* CAM_SENSOR_CORE_1.2V */
+#if defined(CONFIG_MACH_C1) && defined(CONFIG_TARGET_LOCALE_KOR)
+	if (system_rev >= USE_8M_CAM_SENSOR_CORE_REVISION) {
+		ret = gpio_direction_output(GPIO_CAM_SENSOR_CORE_EN, 1);
+		CAM_CHECK_ERR_RET(ret, "output CAM_SENSOR_CORE_EN");
+		mdelay(5);
+	} else {
+		regulator = regulator_get(NULL, "cam_sensor_core_1.2v");
+		if (IS_ERR(regulator))
+			return -ENODEV;
+		ret = regulator_enable(regulator);
+		regulator_put(regulator);
+		CAM_CHECK_ERR_RET(ret, "enable cam_sensor_core_1.2v");
+		/* delay is needed : pmu control is slower than gpio control*/
+		mdelay(5);
+	}
+#else
+	regulator = regulator_get(NULL, "cam_sensor_core_1.2v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "enable cam_sensor_core_1.2v");
+       /* delay is needed : pmu control is slower than gpio control*/
+	mdelay(5);
+#endif
+
+	/* MCLK */
+	ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_SFN(2));
+	CAM_CHECK_ERR_RET(ret, "cfg mclk");
+	s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_NONE);
+	s5p_gpio_set_drvstr(GPIO_CAM_MCLK, S5P_GPIO_DRVSTR_LV3);
+
+	/* CAM_AF_2.8V */
+	ret = gpio_direction_output(GPIO_CAM_AF_EN, 1);
+	CAM_CHECK_ERR_RET(ret, "output GPIO_CAM_AF_EN");
+	udelay(2000);
+
+	/* CAM_ISP_SENSOR_1.8V */
+	regulator = regulator_get(NULL, "cam_isp_sensor_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "enable cam_isp_sensor_1.8v");
+
+	/* CAM_ISP_MIPI_1.2V */
+	regulator = regulator_get(NULL, "cam_isp_mipi_1.2v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "enable cam_isp_mipi_1.2v");
+       /* delay is needed : pmu control is slower than gpio control*/
+	mdelay(5);
+
+	/* ISP_STANDBY */
+	ret = gpio_direction_output(GPIO_ISP_STANDBY, 1);
+	CAM_CHECK_ERR_RET(ret, "output GPIO_ISP_STANDBY");
+	udelay(100);		/* 2000 cycle */
+
+	/* ISP_RESET */
+	ret = gpio_direction_output(GPIO_ISP_RESET, 1);
+	CAM_CHECK_ERR_RET(ret, "output GPIO_ISP_RESET");
+	udelay(10);		/* 200 cycle */
+
+	s5c73m3_gpio_free();
+
+	return ret;
+}
+
+static int s5c73m3_power_down(void)
+{
+	struct regulator *regulator;
+	int ret = 0;
+
+	printk(KERN_DEBUG "%s: in\n", __func__);
+
+	s5c73m3_gpio_request();
+
+	/* ISP_STANDBY */
+	ret = gpio_direction_output(GPIO_ISP_STANDBY, 0);
+	CAM_CHECK_ERR_RET(ret, "output GPIO_ISP_STANDBY");
+	udelay(2);		/* 40 cycle */
+
+	/* ISP_RESET */
+	ret = gpio_direction_output(GPIO_ISP_RESET, 0);
+	CAM_CHECK_ERR_RET(ret, "output GPIO_ISP_RESET");
+
+	/* CAM_AF_2.8V */
+	ret = gpio_direction_output(GPIO_CAM_AF_EN, 0);
+	CAM_CHECK_ERR_RET(ret, "output GPIO_CAM_AF_EN");
+
+	/* CAM_ISP_MIPI_1.2V */
+	regulator = regulator_get(NULL, "cam_isp_mipi_1.2v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "disable cam_isp_mipi_1.2v");
+	udelay(10);		/* 200 cycle */
+
+	/* CAM_ISP_SENSOR_1.8V */
+	regulator = regulator_get(NULL, "cam_isp_sensor_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "disable cam_isp_sensor_1.8v");
+
+	/* CAM_SENSOR_CORE_1.2V */
+#if defined(CONFIG_MACH_C1) && defined(CONFIG_TARGET_LOCALE_KOR)
+	if (system_rev >= USE_8M_CAM_SENSOR_CORE_REVISION) {
+		ret = gpio_direction_output(GPIO_CAM_SENSOR_CORE_EN, 0);
+		CAM_CHECK_ERR_RET(ret, "output CAM_SENSOR_CORE_EN");
+		udelay(500);
+	} else {
+		regulator = regulator_get(NULL, "cam_sensor_core_1.2v");
+		if (IS_ERR(regulator))
+			return -ENODEV;
+		if (regulator_is_enabled(regulator))
+			ret = regulator_force_disable(regulator);
+		regulator_put(regulator);
+		CAM_CHECK_ERR(ret, "disable cam_sensor_core_1.2v");
+		/* delay is needed : hw request*/
+		udelay(500);
+	}
+#else
+	regulator = regulator_get(NULL, "cam_sensor_core_1.2v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "disable cam_sensor_core_1.2v");
+	/* delay is needed : hw request*/
+	udelay(500);
+#endif
+
+	/* CAM_SENSOR_A2.8V */
+	ret = gpio_direction_output(GPIO_CAM_IO_EN, 0);
+	CAM_CHECK_ERR_RET(ret, "output GPIO_CAM_IO_EN");
+
+	/* CAM_ISP_CORE_1.2V */
+	regulator = regulator_get(NULL, "cam_isp_core_1.2v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "disable cam_isp_core_1.2v");
+
+	ret = gpio_direction_output(GPIO_ISP_CORE_EN, 0);
+	CAM_CHECK_ERR_RET(ret, "output GPIO_CAM_ISP_CORE_EN");
+	/* delay is needed : hw request*/
+	mdelay(30);
+
+	/* MCLK */
+	ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_DOWN);
+	CAM_CHECK_ERR(ret, "cfg mclk");
+
+	s5c73m3_gpio_free();
+
+	return ret;
+}
+
+static int s5c73m3_power(int enable)
+{
+	int ret = 0;
+
+	if (enable) {
+		ret = s5c73m3_power_on();
+
+		if (unlikely(ret))
+			goto error_out;
+	} else
+		ret = s5c73m3_power_down();
+
+	ret = s3c_csis_power(enable);
+
+error_out:
+	return ret;
+}
+
+static int s5c73m3_get_i2c_busnum(void)
+{
+#if 0
+	if (system_rev == 0x03) /*M0, M1 REV00*/
+		return 18;
+	else
+#endif
+	return 0;
+}
+
+static const char *s5c73m3_get_clk_name(void)
+{
+	return "sclk_cam0";
+}
+
+static struct s5c73m3_platform_data s5c73m3_plat = {
+	.default_width = 640,	/* 1920 */
+	.default_height = 480,	/* 1080 */
+	.pixelformat = V4L2_PIX_FMT_UYVY,
+	.freq = 24000000,
+	.is_mipi = 1,
+	.set_vdd_core = s5c73m3_set_vdd_core,
+	.is_vdd_core_set = s5c73m3_is_vdd_core_set,
+	.is_isp_reset = s5c73m3_is_isp_reset,
+};
+
+static struct i2c_board_info s5c73m3_i2c_info = {
+	I2C_BOARD_INFO("S5C73M3", 0x78 >> 1),
+	.platform_data = &s5c73m3_plat,
+};
+
+static struct s3c_platform_camera s5c73m3 = {
+	.id = CAMERA_CSI_C,
+	.get_clk_name = s5c73m3_get_clk_name,
+	.get_i2c_busnum = s5c73m3_get_i2c_busnum,
+	.cam_power = s5c73m3_power,
+	.type = CAM_TYPE_MIPI,
+	.fmt = MIPI_CSI_YCBCR422_8BIT,
+	.order422 = CAM_ORDER422_8BIT_YCBYCR,
+	.info = &s5c73m3_i2c_info,
+	.pixelformat = V4L2_PIX_FMT_UYVY,
+	.srclk_name = "xusbxti",	/* "mout_mpll" */
+	.clk_rate = 24000000,	/* 48000000 */
+	.line_length = 1920,
+	.width = 640,
+	.height = 480,
+	.window = {
+		.left = 0,
+		.top = 0,
+		.width = 640,
+		.height = 480,
+	},
+
+	.mipi_lanes = 4,
+	.mipi_settle = 12,
+	.mipi_align = 32,
+
+	/* Polarity */
+	.inv_pclk = 1,
+	.inv_vsync = 1,
+	.inv_href = 0,
+	.inv_hsync = 0,
+	.reset_camera = 0,
+	.initialized = 0,
+};
+#endif
+
+#ifdef CONFIG_VIDEO_M5MO
+static int m5mo_get_i2c_busnum(void)
+{
+#ifdef CONFIG_VIDEO_M5MO_USE_SWI2C
+	return 25;
+#else
+	return 0;
+#endif
+}
+
+static int m5mo_power_on(void)
+{
+	struct regulator *regulator;
+	int ret = 0;
+
+	printk(KERN_DEBUG "%s: in\n", __func__);
+
+	ret = gpio_request(GPIO_CAM_VT_nSTBY, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "faile to request gpio(GPIO_CAM_VGA_nSTBY)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_CAM_VT_nRST, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "faile to request gpio(GPIO_CAM_VGA_nRST)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_ISP_CORE_EN, "GPM0");
+	if (ret) {
+		printk(KERN_ERR "fail to request gpio(CAM_SENSOR_CORE)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_ISP_RESET, "GPY3");
+	if (ret) {
+		printk(KERN_ERR "faile to request gpio(GPIO_ISP_RESET)\n");
+		return ret;
+	}
+	/* CAM_VT_nSTBY low */
+	ret = gpio_direction_output(GPIO_CAM_VT_nSTBY, 0);
+	CAM_CHECK_ERR_RET(ret, "output VT_nSTBY");
+
+	/* CAM_VT_nRST	low */
+	gpio_direction_output(GPIO_CAM_VT_nRST, 0);
+	CAM_CHECK_ERR_RET(ret, "output VT_nRST");
+	udelay(10);
+
+	/* CAM_ISP_CORE_1.2V */
+	ret = gpio_direction_output(GPIO_ISP_CORE_EN, 1);
+	CAM_CHECK_ERR_RET(ret, "output GPIO_ISP_CORE_EN");
+
+	regulator = regulator_get(NULL, "cam_isp_core_1.2v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "enable cam_isp_core_1.2v");
+	udelay(10);
+	/* CAM_SENSOR_CORE_1.2V */
+	regulator = regulator_get(NULL, "cam_sensor_core_1.2v");
+	if (IS_ERR(regulator)) {
+		CAM_CHECK_ERR_RET(ret, "output Err cam_sensor_core_1.2v");
+		return -ENODEV;
+	}
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "enable cam_sensor_core_1.2v");
+	udelay(10);
+
+	/* CAM_SENSOR_A2.8V */
+	regulator = regulator_get(NULL, "cam_sensor_a2.8v");
+	if (IS_ERR(regulator)) {
+		CAM_CHECK_ERR_RET(ret, "output Err cam_sensor_a2.8v");
+		return -ENODEV;
+	}
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "enable cam_sensor_a2.8v");
+	/* it takes about 100us at least during level transition.*/
+	udelay(160); /* 130us -> 160us */
+	/* VT_CAM_DVDD_1.8V */
+	regulator = regulator_get(NULL, "vt_cam_dvdd_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "enable vt_cam_dvdd_1.8v");
+	udelay(10);
+
+	/* CAM_AF_2.8V */
+	regulator = regulator_get(NULL, "cam_af_2.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "output cam_af_2.8v");
+	mdelay(7);
+
+	/* VT_CAM_1.8V */
+	regulator = regulator_get(NULL, "vt_cam_1.8v");
+	if (IS_ERR(regulator)) {
+		CAM_CHECK_ERR_RET(ret, "output Err vt_cam_1.8v");
+		return -ENODEV;
+	}
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "enable vt_cam_1.8v");
+	udelay(20);
+
+	/* CAM_ISP_1.8V */
+	regulator = regulator_get(NULL, "cam_isp_1.8v");
+	if (IS_ERR(regulator)) {
+		CAM_CHECK_ERR_RET(ret, "output Err cam_isp_1.8v");
+		return -ENODEV;
+	}
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "enable cam_isp_1.8v");
+	udelay(120); /* at least */
+
+	/* CAM_ISP_SEN_IO_1.8V */
+	regulator = regulator_get(NULL, "cam_isp_sensor_1.8v");
+	if (IS_ERR(regulator)) {
+		CAM_CHECK_ERR_RET(ret, "output Err cam_isp_sensor_1.8v");
+		return -ENODEV;
+	}
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "enable cam_isp_sensor_1.8v");
+	udelay(30);
+
+	/* MCLK */
+	ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_SFN(2));
+	CAM_CHECK_ERR_RET(ret, "cfg mclk");
+	s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_NONE);
+	udelay(70);
+	/* ISP_RESET */
+	ret = gpio_direction_output(GPIO_ISP_RESET, 1);
+	CAM_CHECK_ERR_RET(ret, "output reset");
+	mdelay(4);
+
+	gpio_free(GPIO_CAM_VT_nSTBY);
+	gpio_free(GPIO_CAM_VT_nRST);
+	gpio_free(GPIO_ISP_CORE_EN);
+	gpio_free(GPIO_ISP_RESET);
+
+	return ret;
+}
+
+static int m5mo_power_down(void)
+{
+	struct regulator *regulator;
+	int ret = 0;
+
+	printk(KERN_DEBUG "%s: in\n", __func__);
+
+	ret = gpio_request(GPIO_CAM_VT_nSTBY, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "faile to request gpio(GPIO_CAM_VGA_nSTBY)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_CAM_VT_nRST, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "faile to request gpio(GPIO_CAM_VGA_nRST)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_ISP_CORE_EN, "GPM0");
+	if (ret) {
+		printk(KERN_ERR "fail to request gpio(CAM_SENSOR_CORE)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_ISP_RESET, "GPY3");
+	if (ret) {
+		printk(KERN_ERR "faile to request gpio(GPIO_ISP_RESET)\n");
+		return ret;
+	}
+
+	/* s3c_i2c0_force_stop(); */
+
+	mdelay(3);
+
+	/* ISP_RESET */
+	ret = gpio_direction_output(GPIO_ISP_RESET, 0);
+	CAM_CHECK_ERR(ret, "output reset");
+	mdelay(2);
+
+	/* MCLK */
+	ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_DOWN);
+	CAM_CHECK_ERR(ret, "cfg mclk");
+	udelay(20);
+
+	/* CAM_AF_2.8V */
+	regulator = regulator_get(NULL, "cam_af_2.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "disable cam_af_2.8v");
+
+	/* CAM_ISP_SEN_IO_1.8V */
+	regulator = regulator_get(NULL, "cam_isp_sensor_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "disable, cam_isp_sensor_1.8v");
+	udelay(10);
+
+	/* CAM_ISP_1.8V */
+	regulator = regulator_get(NULL, "cam_isp_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "disable cam_isp_1.8v");
+	udelay(500); /* 100us -> 500us */
+
+	/* VT_CAM_1.8V */
+	regulator = regulator_get(NULL, "vt_cam_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "disable vt_cam_1.8v");
+	udelay(250); /* 10us -> 250us */
+
+	/* VT_CAM_DVDD_1.8V */
+	regulator = regulator_get(NULL, "vt_cam_dvdd_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "disable vt_cam_dvdd_1.8v");
+	udelay(300); /*10 -> 300 us */
+
+	/* CAM_SENSOR_A2.8V */
+	regulator = regulator_get(NULL, "cam_sensor_a2.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "disable cam_sensor_a2.8v");
+	udelay(800);
+
+	/* CAM_SENSOR_CORE_1.2V */
+	regulator = regulator_get(NULL, "cam_sensor_core_1.2v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "disable cam_sensor_core_1.2v");
+	udelay(5);
+
+	/* CAM_ISP_CORE_1.2V */
+	ret = gpio_direction_output(GPIO_ISP_CORE_EN, 0);
+	CAM_CHECK_ERR(ret, "output ISP_CORE");
+
+	regulator = regulator_get(NULL, "cam_isp_core_1.2v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "disable cam_isp_core_1.2v");
+
+	gpio_free(GPIO_CAM_VT_nSTBY);
+	gpio_free(GPIO_CAM_VT_nRST);
+	gpio_free(GPIO_ISP_CORE_EN);
+	gpio_free(GPIO_ISP_RESET);
+
+	return ret;
+}
+
+static int m5mo_flash_power(int enable)
+{
+/* TODO */
+	return 0;
+}
+
+static int m5mo_power(int enable)
+{
+	int ret = 0;
+
+	printk(KERN_ERR "%s %s\n", __func__, enable ? "on" : "down");
+	if (enable) {
+		ret = m5mo_power_on();
+		if (unlikely(ret))
+			goto error_out;
+	} else
+		ret = m5mo_power_down();
+
+	ret = s3c_csis_power(enable);
+	m5mo_flash_power(enable);
+
+error_out:
+	return ret;
+}
+
+static int m5mo_config_isp_irq(void)
+{
+	s3c_gpio_cfgpin(GPIO_ISP_INT, S3C_GPIO_SFN(0xF));
+	s3c_gpio_setpull(GPIO_ISP_INT, S3C_GPIO_PULL_NONE);
+	return 0;
+}
+
+static const char *m5mo_get_clk_name(void)
+{
+	return "sclk_cam0";
+}
+
+static struct m5mo_platform_data m5mo_plat = {
+	.default_width = 640, /* 1920 */
+	.default_height = 480, /* 1080 */
+	.pixelformat = V4L2_PIX_FMT_UYVY,
+	.freq = 24000000,
+	.is_mipi = 1,
+	.config_isp_irq = m5mo_config_isp_irq,
+	.irq = IRQ_EINT(24),
+};
+
+static struct i2c_board_info  m5mo_i2c_info = {
+	I2C_BOARD_INFO("M5MO", 0x1F),
+	.platform_data = &m5mo_plat,
+};
+
+static struct s3c_platform_camera m5mo = {
+	.id		= CAMERA_CSI_C,
+	.get_clk_name	= m5mo_get_clk_name,
+	.get_i2c_busnum	= m5mo_get_i2c_busnum,
+	.cam_power	= m5mo_power, /*smdkv310_mipi_cam0_reset,*/
+	.type		= CAM_TYPE_MIPI,
+	.fmt		= ITU_601_YCBCR422_8BIT, /*MIPI_CSI_YCBCR422_8BIT*/
+	.order422	= CAM_ORDER422_8BIT_CBYCRY,
+
+	.info		= &m5mo_i2c_info,
+	.pixelformat	= V4L2_PIX_FMT_UYVY,
+	.srclk_name	= "xusbxti", /* "mout_mpll" */
+	.clk_rate	= 24000000, /* 48000000 */
+	.line_length	= 1920,
+	.width		= 640,
+	.height		= 480,
+	.window		= {
+		.left	= 0,
+		.top	= 0,
+		.width	= 640,
+		.height	= 480,
+	},
+
+	.mipi_lanes	= 2,
+	.mipi_settle	= 12,
+	.mipi_align	= 32,
+
+	/* Polarity */
+	.inv_pclk	= 0,
+	.inv_vsync	= 1,
+	.inv_href	= 0,
+	.inv_hsync	= 0,
+	.reset_camera	= 0,
+	.initialized	= 0,
+};
+#endif /* #ifdef CONFIG_VIDEO_M5MO */
+
+#ifdef CONFIG_VIDEO_M9MO
+static int m9mo_get_i2c_busnum(void)
+{
+	return 0;
+}
+
+static int m9mo_power_on(void)
+{
+	struct regulator *regulator;
+	int ret = 0;
+
+	printk(KERN_DEBUG "%s: in\n", __func__);
+
+	ret = gpio_request(GPIO_ISP_CORE_EN, "GPM0");
+	if (ret) {
+		printk(KERN_ERR "faile to request gpio(GPIO_ISP_CORE_EN)\n");
+		return ret;
+	}
+
+	ret = gpio_request(GPIO_ISP_RESET, "GPF1");
+	if (ret) {
+		printk(KERN_ERR "faile to request gpio(GPIO_ISP_RESET)\n");
+		return ret;
+	}
+	/* CAM_ISP_CORE_EN */
+	ret = gpio_direction_output(GPIO_ISP_CORE_EN, 1);
+	CAM_CHECK_ERR_RET(ret, "output GPIO_ISP_CORE_EN");
+
+	/* CAM_ISP_1.2V (ISP 1.2V) => BUCK 9*/
+	regulator = regulator_get(NULL, "cam_isp_1.2v");
+	if (IS_ERR(regulator)) {
+		CAM_CHECK_ERR_RET(ret, "output Err cam_isp_1.2v");
+		return -ENODEV;
+	}
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "enable cam_isp_1.2v");
+
+	/* CAM_SENSOR_CORE_1.2V (CIS 1.2V) => LDO17*/
+	regulator = regulator_get(NULL, "cam_sensor_core_1.2v");
+	if (IS_ERR(regulator)) {
+		CAM_CHECK_ERR_RET(ret, "output Err cam_sensor_core_1.2v");
+		return -ENODEV;
+	}
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "enable cam_sensor_core_1.2v");
+
+	/* CAM_ISP_1.8V (ISP 1.8V) => LDO23*/
+	regulator = regulator_get(NULL, "cam_isp_1.8v");
+	if (IS_ERR(regulator)) {
+		CAM_CHECK_ERR_RET(ret, "output Err cam_isp_1.8v");
+		return -ENODEV;
+	}
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "enable cam_isp_1.8v");
+
+	/* CAM_SENSOR_1.8V (CIS 1.8V) => LDO19*/
+	regulator = regulator_get(NULL, "cam_sensor_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "enable cam_sensor_1.8v");
+
+	/* CAM_SENSOR_2.8V (CIS 2.8V) => LDO25*/
+	regulator = regulator_get(NULL, "cam_sensor_2.8v");
+	if (IS_ERR(regulator)) {
+		CAM_CHECK_ERR_RET(ret, "output Err cam_sensor_2.8v");
+		return -ENODEV;
+	}
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "enable cam_sensor_2.8v");
+
+	/* MCLK */
+	ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_SFN(2));
+	CAM_CHECK_ERR_RET(ret, "cfg mclk");
+	s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_NONE);
+	udelay(70);
+
+	/* ISP_RESET */
+	ret = gpio_direction_output(GPIO_ISP_RESET, 1);
+	CAM_CHECK_ERR_RET(ret, "output reset");
+	mdelay(4);
+
+	gpio_free(GPIO_ISP_CORE_EN);
+	gpio_free(GPIO_ISP_RESET);
+
+	return ret;
+}
+
+static int m9mo_power_down(void)
+{
+	struct regulator *regulator;
+	int ret = 0;
+
+	printk(KERN_DEBUG "%s: in\n", __func__);
+
+	if (system_rev > 0) {
+		ret = gpio_request(GPIO_MOT_EN, "GPM0");
+		if (ret) {
+			printk(KERN_ERR "faile to request gpio(GPIO_MOT_EN)\n");
+			return ret;
+		}
+		ret = gpio_request(GPIO_SAMBAZ_RESET, "GPM0");
+		if (ret) {
+			printk(KERN_ERR "faile to request gpio(GPIO_SAMBAZ_RESET)\n");
+			return ret;
+		}
+	}
+	ret = gpio_request(GPIO_ISP_CORE_EN, "GPM0");
+	if (ret) {
+		printk(KERN_ERR "faile to request gpio(GPIO_ISP_CORE_EN)\n");
+		return ret;
+	}
+
+	ret = gpio_request(GPIO_ISP_RESET, "GPF1");
+	if (ret) {
+		printk(KERN_ERR "faile to request gpio(GPIO_ISP_RESET)\n");
+		return ret;
+	}
+	/* s3c_i2c0_force_stop(); */
+
+	mdelay(3);
+
+	/*MOT_3.3*/
+	regulator = regulator_get(NULL, "mot_3.3v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "mot_3.3v");
+
+	/*OIS_1.5*/
+	regulator = regulator_get(NULL, "ois_1.5v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "disable ois_1.5v");
+	msleep(10);
+
+	/* ISP_RESET */
+	ret = gpio_direction_output(GPIO_ISP_RESET, 0);
+	CAM_CHECK_ERR(ret, "output reset");
+	mdelay(2);
+
+	/* MCLK */
+	ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_DOWN);
+	CAM_CHECK_ERR(ret, "cfg mclk");
+	udelay(20);
+
+	/* CAM_SENSOR_2.8V (CIS 2.8V) => LDO25*/
+	regulator = regulator_get(NULL, "cam_sensor_2.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "disable cam_sensor_2.8v");
+
+	/* CAM_SENSOR_1.8V (CIS 1.8V) => LDO19*/
+	regulator = regulator_get(NULL, "cam_sensor_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "disable cam_sensor_1.8v");
+
+	/* CAM_ISP_1.8V (ISP 1.8V) => LDO23*/
+	regulator = regulator_get(NULL, "cam_isp_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "disable cam_isp_1.8v");
+
+	/* CAM_SENSOR_CORE_1.2V (CIS 1.2V) => LDO17*/
+	regulator = regulator_get(NULL, "cam_sensor_core_1.2v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "disable cam_sensor_core_1.2v");
+
+	/* CAM_ISP_1.2V (ISP 1.2V) => BUCK 9*/
+	regulator = regulator_get(NULL, "cam_isp_1.2v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "disable, cam_isp_1.2v");
+
+	/* CAM_ISP_CORE_1.2V */
+	ret = gpio_direction_output(GPIO_ISP_CORE_EN, 0);
+	CAM_CHECK_ERR(ret, "output ISP_CORE");
+
+	if (system_rev > 0) {
+		ret = gpio_direction_output(GPIO_SAMBAZ_RESET, 0);
+		CAM_CHECK_ERR(ret, "output GPIO_SAMBAZ_RESET");
+		mdelay(100);
+
+		ret = gpio_direction_output(GPIO_MOT_EN, 0);
+		CAM_CHECK_ERR(ret, "output GPIO_MOT_EN");
+		mdelay(2);
+
+		gpio_free(GPIO_MOT_EN);
+		gpio_free(GPIO_SAMBAZ_RESET);
+	}
+	gpio_free(GPIO_ISP_CORE_EN);
+	gpio_free(GPIO_ISP_RESET);
+
+	return ret;
+}
+
+static int m9mo_flash_power(int enable)
+{
+/* TODO */
+	return 0;
+}
+
+static int m9mo_power(int enable)
+{
+	int ret = 0;
+
+	printk(KERN_ERR "%s %s\n", __func__, enable ? "on" : "down");
+	if (enable) {
+		ret = m9mo_power_on();
+		if (unlikely(ret))
+			goto error_out;
+	} else
+		ret = m9mo_power_down();
+
+	ret = s3c_csis_power(enable);
+	m9mo_flash_power(enable);
+
+error_out:
+	return ret;
+}
+
+static int m9mo_config_isp_irq(void)
+{
+printk(KERN_ERR "m9mo_config_isp_irq~~~~~~~~~~\n");
+	s3c_gpio_cfgpin(GPIO_ISP_INT, S3C_GPIO_SFN(0xF));
+	s3c_gpio_setpull(GPIO_ISP_INT, S3C_GPIO_PULL_NONE);
+	return 0;
+}
+
+static int m9mo_config_sambaz(int enable)
+{
+	struct regulator *regulator;
+	int ret = 0;
+
+	if (enable) {
+		if (system_rev > 0) {
+			ret = gpio_request(GPIO_MOT_EN, "GPM0");
+			if (ret) {
+				printk(KERN_ERR "faile to request gpio(GPIO_ISP_CORE_EN)\n");
+				return ret;
+			}
+			ret = gpio_request(GPIO_SAMBAZ_RESET, "GPM0");
+			if (ret) {
+				printk(KERN_ERR "faile to request gpio(GPIO_ISP_RESET)\n");
+				return ret;
+			}
+			ret = gpio_direction_output(GPIO_MOT_EN, 1);
+			CAM_CHECK_ERR(ret, "output reset");
+			msleep(100);
+		}
+
+		regulator = regulator_get(NULL, "mot_3.3v");
+		if (IS_ERR(regulator))
+			return -ENODEV;
+		ret = regulator_enable(regulator);
+		regulator_put(regulator);
+		CAM_CHECK_ERR_RET(ret, "mot_3.3v");
+		mdelay(100);
+
+		regulator = regulator_get(NULL, "ois_1.5v");
+		if (IS_ERR(regulator))
+			return -ENODEV;
+		ret = regulator_enable(regulator);
+		regulator_put(regulator);
+		CAM_CHECK_ERR_RET(ret, "ois_1.5v");
+		mdelay(10);
+
+		if (system_rev > 0) {
+			ret = gpio_direction_output(GPIO_SAMBAZ_RESET, 1);
+			CAM_CHECK_ERR(ret, "output reset");
+			msleep(100);
+
+			gpio_free(GPIO_MOT_EN);
+			gpio_free(GPIO_SAMBAZ_RESET);
+		}
+
+	} else {
+		regulator = regulator_get(NULL, "mot_3.3v");
+		if (IS_ERR(regulator))
+			return -ENODEV;
+		if (regulator_is_enabled(regulator))
+			ret = regulator_force_disable(regulator);
+		regulator_put(regulator);
+		CAM_CHECK_ERR(ret, "mot_3.3v");
+
+		regulator = regulator_get(NULL, "ois_1.5v");
+		if (IS_ERR(regulator))
+			return -ENODEV;
+		if (regulator_is_enabled(regulator))
+			ret = regulator_force_disable(regulator);
+		regulator_put(regulator);
+		CAM_CHECK_ERR(ret, "disable ois_1.5v");
+	}
+	return ret;
+}
+
+static const char *m9mo_get_clk_name(void)
+{
+	return "sclk_cam0";
+}
+
+static struct m9mo_platform_data m9mo_plat = {
+	.default_width = 640, /* 1920 */
+	.default_height = 480, /* 1080 */
+	.pixelformat = V4L2_PIX_FMT_UYVY,
+	.freq = 24000000,
+	.is_mipi = 1,
+	.config_isp_irq = m9mo_config_isp_irq,
+	.config_sambaz = m9mo_config_sambaz,
+	.irq = IRQ_EINT(2),
+};
+
+static struct i2c_board_info  m9mo_i2c_info = {
+	I2C_BOARD_INFO("M9MO", 0x1F),
+	.platform_data = &m9mo_plat,
+};
+
+static struct s3c_platform_camera m9mo = {
+	.id		= CAMERA_CSI_C,
+	.get_clk_name	= m9mo_get_clk_name,
+	.get_i2c_busnum	= m9mo_get_i2c_busnum,
+	.cam_power	= m9mo_power, /*smdkv310_mipi_cam0_reset,*/
+	.type		= CAM_TYPE_MIPI,
+	.fmt		= ITU_601_YCBCR422_8BIT, /*MIPI_CSI_YCBCR422_8BIT*/
+	.order422	= CAM_ORDER422_8BIT_CBYCRY,
+
+	.info		= &m9mo_i2c_info,
+	.pixelformat	= V4L2_PIX_FMT_UYVY,
+	.srclk_name	= "xusbxti", /* "mout_mpll" */
+	.clk_rate	= 24000000, /* 48000000 */
+	.line_length	= 1920,
+	.width		= 640,
+	.height		= 480,
+	.window		= {
+		.left	= 0,
+		.top	= 0,
+		.width	= 640,
+		.height	= 480,
+	},
+
+	.mipi_lanes	= 4,
+	.mipi_settle	= 12,
+	.mipi_align	= 32,
+
+	/* Polarity */
+	.inv_pclk	= 0,
+	.inv_vsync	= 1,
+	.inv_href	= 0,
+	.inv_hsync	= 0,
+	.reset_camera	= 0,
+	.initialized	= 0,
+};
+#endif /* #ifdef CONFIG_VIDEO_M9MO */
+
+#ifdef CONFIG_VIDEO_ISX012
+static int isx012_get_i2c_busnum(void)
+{
+	return 0;
+}
+
+static void isx012_flashtimer_handler(unsigned long data)
+{
+	int ret = -ENODEV;
+	atomic_t *flash_status = (atomic_t *)data;
+
+	pr_info("********** flashtimer_handler **********\n");
+
+	ret = gpio_direction_output(GPIO_CAM_FLASH_EN, 0);
+	atomic_set(flash_status, ISX012_FLASH_OFF);
+	if (unlikely(ret))
+		pr_err("flash_timer: ERROR, failed to oneshot flash off\n");
+
+}
+
+static atomic_t flash_status = ATOMIC_INIT(ISX012_FLASH_OFF);
+static int isx012_flash_en(u32 mode, u32 onoff)
+{
+	static int flash_mode = ISX012_FLASH_MODE_NORMAL;
+	static DEFINE_MUTEX(flash_lock);
+	static DEFINE_TIMER(flash_timer, isx012_flashtimer_handler,
+			0, (unsigned long)&flash_status);
+	int ret = 0;
+
+	printk(KERN_DEBUG "flash_en: mode=%d, on=%d\n", mode, onoff);
+
+	if (unlikely((u32)mode >= ISX012_FLASH_MODE_MAX)) {
+		pr_err("flash_en: ERROR, invalid flash mode(%d)\n", mode);
+		return -EINVAL;
+	}
+
+	/* We could not use spin lock because of gpio kernel API.*/
+	mutex_lock(&flash_lock);
+	if (atomic_read(&flash_status) == onoff) {
+		mutex_unlock(&flash_lock);
+		pr_warn("flash_en: WARNING, already flash %s\n",
+			onoff ? "On" : "Off");
+		return 0;
+	}
+
+	switch (onoff) {
+	case ISX012_FLASH_ON:
+		if (mode == ISX012_FLASH_MODE_MOVIE)
+			ret = gpio_direction_output(GPIO_CAM_MOVIE_EN, 1);
+		else {
+			ret = gpio_direction_output(GPIO_CAM_FLASH_EN, 1);
+			flash_timer.expires = get_jiffies_64() + HZ / 2;
+			add_timer(&flash_timer);
+		}
+		CAM_CHECK_ERR_GOTO(ret, out,
+			"flash_en: ERROR, fail to turn flash on (mode:%d)\n",
+			mode);
+		flash_mode = mode;
+		break;
+
+	case ISX012_FLASH_OFF:
+		if (unlikely(flash_mode != mode)) {
+			pr_err("flash_en: ERROR, unmatched flash mode(%d, %d)\n",
+				flash_mode, mode);
+			WARN_ON(1);
+			goto out;
+		}
+
+		if (mode == ISX012_FLASH_MODE_MOVIE)
+			ret = gpio_direction_output(GPIO_CAM_MOVIE_EN, 0);
+		else {
+			if (del_timer_sync(&flash_timer)) {
+				pr_info("flash_en: terminate flash timer...\n");
+				ret = gpio_direction_output(GPIO_CAM_FLASH_EN,
+							0);
+			}
+		}
+		CAM_CHECK_ERR_GOTO(ret, out,
+			"flash_en: ERROR, flash off (mode:%d)\n", mode);
+		break;
+
+	default:
+		pr_err("flash_en: ERROR, invalid flash cmd(%d)\n", onoff);
+		goto out;
+		break;
+	}
+
+	atomic_set(&flash_status, onoff);
+
+out:
+	mutex_unlock(&flash_lock);
+	return 0;
+}
+
+static int isx012_is_flash_on(void)
+{
+	return atomic_read(&flash_status);
+}
+
+/* Power up/down func for P4C, P2. */
+static int isx012_power_on(void)
+{
+	struct regulator *regulator;
+	int ret = 0;
+
+	printk(KERN_DEBUG "[ISX012] power on\n");
+
+#ifndef USE_CAM_GPIO_CFG
+	ret = gpio_request(GPIO_5M_nSTBY, "GPJ0");
+	if (unlikely(ret)) {
+		printk(KERN_ERR "error: request 5M_nSTBY\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_5M_nRST, "GPL1");
+	if (unlikely(ret)) {
+		printk(KERN_ERR "error: request 5M_nRST\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_CAM_EN2, "GPJ0");
+	if (unlikely(ret)) {
+		printk(KERN_ERR "error: request CAM_EN2\n");
+		return ret;
+	}
+#endif
+
+	/* 5MP_CORE_1.2V */
+	regulator = regulator_get(NULL, "3mp_core_1.2v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "3mp_core_1.2v");
+	udelay(10);
+
+	/* CAM_IO_1.8V */
+	regulator = regulator_get(NULL, "cam_io_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "cam_io_1.8v");
+	udelay(10);
+
+	/* CAM_A2.8V */
+	ret = gpio_direction_output(GPIO_CAM_EN2, 1);
+	CAM_CHECK_ERR_RET(ret, "CAM_A2.8V");
+	udelay(200);
+
+	/* CAM_MCLK */
+	/*s5p_gpio_set_drvstr(GPIO_CAM_MCLK, S5P_GPIO_DRVSTR_LV2);*/
+	ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_SFN(2));
+	CAM_CHECK_ERR_RET(ret, "cfg mclk");
+	s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_NONE);
+	udelay(10);
+
+	/* 3M_nRST */
+	ret = gpio_direction_output(GPIO_5M_nRST, 1);
+	CAM_CHECK_ERR_RET(ret, "3M_nRST");
+	udelay(10);
+
+	/* 5MP_AF_2.8V */
+	regulator = regulator_get(NULL, "3mp_af_2.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "3mp_af_2.8v");
+	usleep_range(6000, 6500);
+
+#ifndef USE_CAM_GPIO_CFG
+	gpio_free(GPIO_5M_nSTBY);
+	gpio_free(GPIO_5M_nRST);
+	gpio_free(GPIO_CAM_EN2);
+#endif
+
+	return ret;
+}
+
+static int isx012_power_down(void)
+{
+	struct regulator *regulator;
+	int ret = 0;
+
+	printk(KERN_DEBUG "[ISX012] power down\n");
+
+	ret = gpio_request(GPIO_5M_nSTBY, "GPJ0");
+	if (unlikely(ret)) {
+		printk(KERN_ERR "error: request 3M_nSTBY\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_5M_nRST, "GPL1");
+	if (unlikely(ret)) {
+		printk(KERN_ERR "error: request 3M_nRST\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_CAM_EN2, "GPJ0");
+	if (unlikely(ret)) {
+		printk(KERN_ERR "error: request CAM_EN2\n");
+		return ret;
+	}
+
+	/* 5MP_AF_2.8V */
+	regulator = regulator_get(NULL, "3mp_af_2.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	CAM_CHECK_ERR_RET(ret, "3mp_af_2.8v");
+	udelay(10);
+
+	/* 5M_nSTBY */
+	ret = gpio_direction_output(GPIO_5M_nSTBY, 0);
+	CAM_CHECK_ERR(ret, "5M_nSTBY");
+	udelay(10);
+
+	/* 5M_nRST */
+	ret = gpio_direction_output(GPIO_5M_nRST, 0);
+	CAM_CHECK_ERR(ret, "5M_nRST");
+	udelay(50);
+
+	/* CAM_MCLK */
+	ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_DOWN);
+	CAM_CHECK_ERR(ret, "cfg mclk");
+	udelay(10);
+
+	/* CAM_A2.8V */
+	ret = gpio_direction_output(GPIO_CAM_EN2, 0);
+	CAM_CHECK_ERR_RET(ret, "CAM_A2.8V");
+	udelay(10);
+
+	/* CAM_IO_1.8V */
+	regulator = regulator_get(NULL, "cam_io_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "cam_io_1.8v");
+	udelay(10);
+
+	/* 5MP_CORE_1.2V */
+	regulator = regulator_get(NULL, "3mp_core_1.2v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "3mp_core_1.2v");
+
+	gpio_free(GPIO_5M_nSTBY);
+	gpio_free(GPIO_5M_nRST);
+	gpio_free(GPIO_CAM_EN2);
+
+	return ret;
+}
+
+static int isx012_power(int enable)
+{
+	int ret = 0;
+
+	if (enable) {
+		ret = isx012_power_on();
+	} else
+		ret = isx012_power_down();
+
+	if (unlikely(ret)) {
+		pr_err("%s: power-on/down failed\n", __func__);
+		return ret;
+	}
+
+	ret = s3c_csis_power(enable);
+	if (unlikely(ret)) {
+		pr_err("%s: csis power-on failed\n", __func__);
+		return ret;
+	}
+
+	return ret;
+}
+
+static int isx012_enable_standby(bool enable)
+{
+	int err;
+
+	pr_info("%s: %s\n", __func__, enable ? "on" : "off");
+
+	err = gpio_request(GPIO_5M_nSTBY, "GPJ0");
+	if (unlikely(err)) {
+		printk(KERN_ERR "error: request 5M_nSTBY\n");
+		return err;
+	}
+
+	/* GPIO_5M_nSTBY */
+	err = gpio_direction_output(GPIO_5M_nSTBY, enable ?
+			GPIO_LEVEL_LOW : GPIO_LEVEL_HIGH);
+	CAM_CHECK_ERR_RET(err, "GPIO_5M_nSTBY");
+
+	gpio_free(GPIO_5M_nSTBY);
+	return 0;
+}
+
+static int px_cam_cfg_init(void)
+{
+	int ret = -ENODEV;
+
+	pr_info("cam_cfg_init\n");
+
+	ret = gpio_request(GPIO_CAM_MOVIE_EN, "GPM3");
+	if (unlikely(ret)) {
+		pr_err("cam_cfg_init: fail to get gpio(MOVIE_EN), "
+			"err=%d\n", ret);
+		goto out;
+	}
+
+	ret = gpio_request(GPIO_CAM_FLASH_EN, "GPM3");
+	if (unlikely(ret)) {
+		pr_err("cam_cfg_init: fail to get gpio(FLASH_EN), "
+			"err=%d\n", ret);
+		goto out_free;
+	}
+
+	return 0;
+
+out_free:
+	gpio_free(GPIO_CAM_MOVIE_EN);
+out:
+	return ret;
+}
+
+static const char *isx012_get_clk_name(void)
+{
+	return "sclk_cam0";
+}
+
+static struct isx012_platform_data isx012_plat = {
+	.default_width = 1024,
+	.default_height = 768,
+	.pixelformat = V4L2_PIX_FMT_UYVY,
+	.freq = 24000000,
+	.is_mipi = 1,
+	.streamoff_delay = ISX012_STREAMOFF_DELAY,
+	.flash_en = isx012_flash_en,
+	.is_flash_on = isx012_is_flash_on,
+	.stby_on = isx012_enable_standby,
+	.dbg_level = CAMDBG_LEVEL_DEFAULT,
+};
+#define REAR_CAM_PLAT		(isx012_plat)
+
+static struct i2c_board_info  isx012_i2c_info = {
+	I2C_BOARD_INFO("ISX012", 0x7A>>1),
+	.platform_data = &isx012_plat,
+};
+
+static struct s3c_platform_camera isx012 = {
+	.id		= CAMERA_CSI_C,
+	.get_clk_name	= isx012_get_clk_name,
+	.get_i2c_busnum	= isx012_get_i2c_busnum,
+	.cam_power	= isx012_power, /*smdkv310_mipi_cam0_reset,*/
+	.type		= CAM_TYPE_MIPI,
+	.fmt		= ITU_601_YCBCR422_8BIT, /*MIPI_CSI_YCBCR422_8BIT*/
+	.order422	= CAM_ORDER422_8BIT_CBYCRY,
+	.info		= &isx012_i2c_info,
+	.pixelformat	= V4L2_PIX_FMT_UYVY,
+	.srclk_name	= "xusbxti", /* "mout_mpll" */
+	.clk_rate	= 24000000, /* 48000000 */
+	.line_length	= 640,
+	.width		= 640,
+	.height		= 480,
+	.window		= {
+		.left	= 0,
+		.top	= 0,
+		.width	= 640,
+		.height	= 480,
+	},
+
+	.mipi_lanes	= 2,
+	.mipi_settle	= 12,
+	.mipi_align	= 32,
+
+	/* Polarity */
+	.inv_pclk	= 0,
+	.inv_vsync	= 1,
+	.inv_href	= 0,
+	.inv_hsync	= 0,
+	.reset_camera	= 0,
+	.initialized	= 0,
+};
+
+static ssize_t isx012_camtype_show(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	const char cam_type[] = "SONY_ISX012";
+	pr_info("%s\n", __func__);
+	return sprintf(buf, "%s\n", cam_type);
+}
+static DEVICE_ATTR(rear_camtype, S_IRUGO, isx012_camtype_show, NULL);
+
+static ssize_t isx012_camfw_show(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	char type[] = "ISX012";
+	return sprintf(buf, "%s %s\n", type, type);
+
+}
+static DEVICE_ATTR(rear_camfw, S_IRUGO, isx012_camfw_show, NULL);
+
+static ssize_t flash_show(struct device *dev, struct device_attribute *attr,
+			char *buf)
+{
+	return sprintf(buf, "%s\n", isx012_is_flash_on() ? "on" : "off");
+}
+
+static ssize_t flash_store(struct device *dev, struct device_attribute *attr,
+			 const char *buf, size_t count)
+{
+
+	isx012_flash_en(ISX012_FLASH_MODE_MOVIE, (*buf == '0') ?
+		ISX012_FLASH_OFF : ISX012_FLASH_ON);
+
+	return count;
+}
+static DEVICE_ATTR(rear_flash, 0664, flash_show, flash_store);
+
+int isx012_create_file(struct class *cls)
+{
+	struct device *dev_rear = NULL;
+	int ret = -ENODEV;
+
+	dev_rear = device_create(cls, NULL, 0, NULL, "rear");
+	if (IS_ERR(dev_rear)) {
+		pr_err("cam_init: failed to create device(rearcam_dev)\n");
+		return -ENODEV;
+	}
+
+	ret = device_create_file(dev_rear, &dev_attr_rear_camtype);
+	if (unlikely(ret < 0))
+		pr_err("cam_init: failed to create device file, %s\n",
+			dev_attr_rear_camtype.attr.name);
+
+	ret = device_create_file(dev_rear, &dev_attr_rear_camfw);
+	if (unlikely(ret < 0))
+		pr_err("cam_init: failed to create device file, %s\n",
+			dev_attr_rear_camtype.attr.name);
+
+	ret = device_create_file(dev_rear, &dev_attr_rear_flash);
+	if (unlikely(ret < 0))
+		pr_err("cam_init: failed to create device file, %s\n",
+			dev_attr_rear_flash.attr.name);
+
+	return 0;
+}
+#endif /* CONFIG_VIDEO_ISX012*/
+
+#ifdef CONFIG_VIDEO_S5K5CCGX_COMMON
+static int s5k5ccgx_get_i2c_busnum(void)
+{
+	return 0;
+}
+
+/* Power up/down func for P4C, P2. */
+static int s5k5ccgx_power_on(void)
+{
+	struct regulator *regulator;
+	int ret = 0;
+
+	printk(KERN_DEBUG "%s in P4C,P2\n", __func__);
+
+#ifndef USE_CAM_GPIO_CFG
+	ret = gpio_request(GPIO_2M_nSTBY, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "Error: fail to request gpio(2M_nSTBY)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_2M_nRST, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "Error: fail to request gpio(2M_nRST)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_3M_nSTBY, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "Error: fail to request gpio(3M_nSTBY)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_3M_nRST, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "Error: fail to request gpio(3M_nRST)\n");
+		return ret;
+	}
+#endif
+
+	/* 2M_nSTBY low */
+	ret = gpio_direction_output(GPIO_2M_nSTBY, 0);
+	CAM_CHECK_ERR_RET(ret, "2M_nSTBY");
+
+	/* 2M_nRST low */
+	ret = gpio_direction_output(GPIO_2M_nRST, 0);
+	CAM_CHECK_ERR_RET(ret, "2M_nRST");
+
+	/* 3MP_CORE_1.2V */
+	regulator = regulator_get(NULL, "3mp_core_1.2v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "3mp_core_1.2v");
+
+	/* CAM_IO_1.8V */
+	regulator = regulator_get(NULL, "cam_io_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "cam_io_1.8v");
+
+	/* CAM_A2.8V, LDO13 */
+	regulator = regulator_get(NULL, "cam_a2.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "cam_a2.8v");
+
+	/* VT_CORE_1.8V */
+	regulator = regulator_get(NULL, "vt_core_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "vt_core_1.8v");
+	udelay(20);
+
+	/* 2M_nSTBY High */
+	ret = gpio_direction_output(GPIO_2M_nSTBY, 1);
+	CAM_CHECK_ERR_RET(ret, "2M_nSTBY");
+	udelay(3);
+
+	/* CAM_MCLK */
+	ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_SFN(2));
+	CAM_CHECK_ERR_RET(ret, "cfg mclk");
+	s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_NONE);
+	msleep(5); /* >=5ms */
+
+	/* 2M_nSTBY Low */
+	ret = gpio_direction_output(GPIO_2M_nSTBY, 0);
+	CAM_CHECK_ERR_RET(ret, "2M_nSTBY");
+	msleep(10); /* >=10ms */
+
+	/* 2M_nRST High */
+	ret = gpio_direction_output(GPIO_2M_nRST, 1);
+	CAM_CHECK_ERR_RET(ret, "2M_nRST");
+	msleep(5);
+
+	/* 2M_nSTBY High */
+	ret = gpio_direction_output(GPIO_2M_nSTBY, 1);
+	CAM_CHECK_ERR_RET(ret, "2M_nSTBY");
+	udelay(2);
+
+	/* 3M_nSTBY */
+	ret = gpio_direction_output(GPIO_3M_nSTBY, 1);
+	CAM_CHECK_ERR_RET(ret, "3M_nSTBY");
+	udelay(16);
+
+	/* 3M_nRST */
+	ret = gpio_direction_output(GPIO_3M_nRST, 1);
+	CAM_CHECK_ERR_RET(ret, "3M_nRST");
+	/* udelay(10); */
+
+	/* 3MP_AF_2.8V */
+	regulator = regulator_get(NULL, "3mp_af_2.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "3mp_af_2.8v");
+	msleep(10);
+
+#ifndef USE_CAM_GPIO_CFG
+	gpio_free(GPIO_2M_nSTBY);
+	gpio_free(GPIO_2M_nRST);
+	gpio_free(GPIO_3M_nSTBY);
+	gpio_free(GPIO_3M_nRST);
+#endif
+
+	return ret;
+}
+
+static int s5k5ccgx_power_down(void)
+{
+	struct regulator *regulator;
+	int ret = 0;
+
+	printk(KERN_DEBUG "%s in P4C,P2\n", __func__);
+
+#ifndef USE_CAM_GPIO_CFG
+	ret = gpio_request(GPIO_2M_nSTBY, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "Error: fail to request gpio(2M_nSTBY)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_2M_nRST, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "Error: fail to request gpio(2M_nRST)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_3M_nRST, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "Error: fail to request gpio(3M_nRST)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_3M_nSTBY, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "Error: fail to request gpio(3M_nSTBY)\n");
+		return ret;
+	}
+#endif
+	/* 3MP_AF_2.8V */
+	regulator = regulator_get(NULL, "3mp_af_2.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "3mp_af_2.8v");
+
+	/* 3M_nRST Low*/
+	ret = gpio_direction_output(GPIO_3M_nRST, 0);
+	CAM_CHECK_ERR(ret, "3M_nSTBY");
+	udelay(50);
+
+	/* CAM_MCLK */
+	ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_DOWN);
+	CAM_CHECK_ERR(ret, "cfg mclk");
+	udelay(5);
+
+	/* 3M_nSTBY */
+	ret = gpio_direction_output(GPIO_3M_nSTBY, 0);
+	CAM_CHECK_ERR(ret, "3M_nSTBY");
+	udelay(1);
+
+	/* 2M_nRST Low */
+	ret = gpio_direction_output(GPIO_2M_nRST, 0);
+	CAM_CHECK_ERR_RET(ret, "2M_nRST");
+
+	/* 2M_nSTBY Low */
+	ret = gpio_direction_output(GPIO_2M_nSTBY, 0);
+	CAM_CHECK_ERR_RET(ret, "2M_nSTBY");
+
+	/* VT_CORE_1.8V */
+	regulator = regulator_get(NULL, "vt_core_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "vt_core_1.8v");
+
+	/* CAM_A2.8V */
+	regulator = regulator_get(NULL, "cam_a2.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "cam_a2.8v");
+	/* udelay(50); */
+
+	/* CAM_IO_1.8V */
+	regulator = regulator_get(NULL, "cam_io_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "cam_io_1.8v");
+	/*udelay(50); */
+
+	/* 3MP_CORE_1.2V */
+	regulator = regulator_get(NULL, "3mp_core_1.2v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "3mp_core_1.2v");
+
+#ifndef USE_CAM_GPIO_CFG
+	gpio_free(GPIO_2M_nSTBY);
+	gpio_free(GPIO_2M_nRST);
+	gpio_free(GPIO_3M_nSTBY);
+	gpio_free(GPIO_3M_nRST);
+#endif
+	return ret;
+}
+
+static int s5k5ccgx_power(int enable)
+{
+	int ret = 0;
+
+	printk(KERN_DEBUG "%s %s\n", __func__, enable ? "on" : "down");
+	if (enable) {
+#ifdef USE_CAM_GPIO_CFG
+		if (cfg_gpio_err) {
+			printk(KERN_ERR "%s: ERROR: gpio configuration",
+				__func__);
+			return cfg_gpio_err;
+		}
+#endif
+		ret = s5k5ccgx_power_on();
+	} else
+		ret = s5k5ccgx_power_down();
+
+	s3c_csis_power(enable);
+
+	return ret;
+}
+
+static void s5k5ccgx_flashtimer_handler(unsigned long data)
+{
+#if 0 /* dslim */
+	int ret = -ENODEV;
+	atomic_t *flash_status = (atomic_t *)data;
+
+	pr_info("********** flashtimer_handler **********\n");
+
+	ret = gpio_direction_output(GPIO_CAM_FLASH_EN, 0);
+	atomic_set(flash_status, S5K5CCGX_FLASH_OFF);
+	if (unlikely(ret))
+		pr_err("flash_timer: ERROR, failed to oneshot flash off\n");
+#endif
+}
+
+static atomic_t flash_status = ATOMIC_INIT(S5K5CCGX_FLASH_OFF);
+static int s5k5ccgx_flash_en(u32 mode, u32 onoff)
+{
+#if 0 /* dslim */
+
+	static int flash_mode = S5K5CCGX_FLASH_MODE_NORMAL;
+	static DEFINE_MUTEX(flash_lock);
+	static DEFINE_TIMER(flash_timer, s5k5ccgx_flashtimer_handler,
+			0, (unsigned long)&flash_status);
+	int ret = 0;
+
+	printk(KERN_DEBUG "flash_en: mode=%d, on=%d\n", mode, onoff);
+
+	if (unlikely((u32)mode >= S5K5CCGX_FLASH_MODE_MAX)) {
+		pr_err("flash_en: ERROR, invalid flash mode(%d)\n", mode);
+		return -EINVAL;
+	}
+
+	/* We could not use spin lock because of gpio kernel API.*/
+	mutex_lock(&flash_lock);
+	if (atomic_read(&flash_status) == onoff) {
+		mutex_unlock(&flash_lock);
+		pr_warn("flash_en: WARNING, already flash %s\n",
+			onoff ? "On" : "Off");
+		return 0;
+	}
+
+	switch (onoff) {
+	case S5K5CCGX_FLASH_ON:
+		if (mode == S5K5CCGX_FLASH_MODE_MOVIE)
+			ret = gpio_direction_output(GPIO_CAM_MOVIE_EN, 1);
+		else {
+			ret = gpio_direction_output(GPIO_CAM_FLASH_EN, 1);
+			flash_timer.expires = get_jiffies_64() + HZ / 2;
+			add_timer(&flash_timer);
+		}
+		CAM_CHECK_ERR_GOTO(ret, out,
+			"flash_en: ERROR, fail to turn flash on (mode:%d)\n",
+			mode);
+		flash_mode = mode;
+		break;
+
+	case S5K5CCGX_FLASH_OFF:
+		if (unlikely(flash_mode != mode)) {
+			pr_err("flash_en: ERROR, unmatched flash mode(%d, %d)\n",
+				flash_mode, mode);
+			WARN_ON(1);
+			goto out;
+		}
+
+		if (mode == S5K5CCGX_FLASH_MODE_MOVIE)
+			ret = gpio_direction_output(GPIO_CAM_MOVIE_EN, 0);
+		else {
+			if (del_timer_sync(&flash_timer)) {
+				pr_info("flash_en: terminate flash timer...\n");
+				ret = gpio_direction_output(GPIO_CAM_FLASH_EN,
+							0);
+			}
+		}
+		CAM_CHECK_ERR_GOTO(ret, out,
+			"flash_en: ERROR, flash off (mode:%d)\n", mode);
+		break;
+
+	default:
+		pr_err("flash_en: ERROR, invalid flash cmd(%d)\n", onoff);
+		goto out;
+		break;
+	}
+
+	atomic_set(&flash_status, onoff);
+
+out:
+	mutex_unlock(&flash_lock);
+#endif
+	return 0;
+}
+
+static int s5k5ccgx_is_flash_on(void)
+{
+	return atomic_read(&flash_status);
+}
+
+static int px_cam_cfg_init(void)
+{
+	int ret = -ENODEV;
+
+	/* pr_info("%s\n", __func__); */
+#if 0 /* dslim */
+	ret = gpio_request(GPIO_CAM_MOVIE_EN, "GPL0");
+	if (unlikely(ret)) {
+		pr_err("cam_cfg_init: fail to get gpio(MOVIE_EN), "
+			"err=%d\n", ret);
+		goto out;
+	}
+
+	ret = gpio_request(GPIO_CAM_FLASH_EN, "GPL0");
+	if (unlikely(ret)) {
+		pr_err("cam_cfg_init: fail to get gpio(FLASH_EN), "
+			"err=%d\n", ret);
+		goto out_free;
+	}
+
+	return 0;
+
+out_free:
+	gpio_free(GPIO_CAM_MOVIE_EN);
+out:
+	return ret;
+#else
+	return 0;
+#endif
+}
+
+static const char *s5k5ccgx_get_clk_name(void)
+{
+	return "sclk_cam0";
+}
+
+static struct s5k5ccgx_platform_data s5k5ccgx_plat = {
+	.default_width = 1024,
+	.default_height = 768,
+	.pixelformat = V4L2_PIX_FMT_UYVY,
+	.freq = 24000000,
+	.is_mipi = 1,
+	.streamoff_delay = S5K5CCGX_STREAMOFF_DELAY,
+	.flash_en = s5k5ccgx_flash_en,
+	.is_flash_on = s5k5ccgx_is_flash_on,
+	.dbg_level = CAMDBG_LEVEL_DEFAULT,
+};
+#define REAR_CAM_PLAT		(s5k5ccgx_plat)
+
+static struct i2c_board_info  s5k5ccgx_i2c_info = {
+	I2C_BOARD_INFO("S5K5CCGX", 0x78>>1),
+	.platform_data = &s5k5ccgx_plat,
+};
+
+static struct s3c_platform_camera s5k5ccgx = {
+	.id		= CAMERA_CSI_C,
+	.get_clk_name	= s5k5ccgx_get_clk_name,
+	.get_i2c_busnum	= s5k5ccgx_get_i2c_busnum,
+	.cam_power	= s5k5ccgx_power, /*smdkv310_mipi_cam0_reset,*/
+	.type		= CAM_TYPE_MIPI,
+	.fmt		= ITU_601_YCBCR422_8BIT, /*MIPI_CSI_YCBCR422_8BIT*/
+	.order422	= CAM_ORDER422_8BIT_CBYCRY,
+	.info		= &s5k5ccgx_i2c_info,
+	.pixelformat	= V4L2_PIX_FMT_UYVY,
+	.srclk_name	= "xusbxti", /* "mout_mpll" */
+	.clk_rate	= 24000000, /* 48000000 */
+	.line_length	= 640,
+	.width		= 640,
+	.height		= 480,
+	.window		= {
+		.left	= 0,
+		.top	= 0,
+		.width	= 640,
+		.height	= 480,
+	},
+
+	.mipi_lanes	= 1,
+	.mipi_settle	= 6,
+	.mipi_align	= 32,
+
+	/* Polarity */
+	.inv_pclk	= 0,
+	.inv_vsync	= 1,
+	.inv_href	= 0,
+	.inv_hsync	= 0,
+	.reset_camera	= 0,
+	.initialized	= 0,
+};
+#endif /* #ifdef CONFIG_VIDEO_S5K5CCGX_COMMON */
+
+
+#ifdef CONFIG_VIDEO_SR200PC20M
+static int sr200pc20m_get_i2c_busnum(void)
+{
+		return 13;
+}
+
+static int sr200pc20m_power_on(void)
+{
+	struct regulator *regulator;
+	int ret = 0;
+
+	ret = gpio_request(GPIO_CAM_VT_nSTBY, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "faile to request gpio(GPIO_CAM_VGA_nSTBY)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_CAM_VT_nRST, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "faile to request gpio(GPIO_CAM_VGA_nRST)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_ISP_CORE_EN, "GPM0");
+	if (ret) {
+		printk(KERN_ERR "fail to request gpio(CAM_SENSOR_CORE)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_ISP_RESET, "GPY3");
+	if (ret) {
+		printk(KERN_ERR "faile to request gpio(GPIO_ISP_RESET)\n");
+		return ret;
+	}
+
+	/* CAM_VT_nSTBY low */
+	ret = gpio_direction_output(GPIO_CAM_VT_nSTBY, 0);
+	CAM_CHECK_ERR_RET(ret, "output VT_nSTBY");
+
+	/* CAM_VT_nRST	low */
+	gpio_direction_output(GPIO_CAM_VT_nRST, 0);
+	CAM_CHECK_ERR_RET(ret, "output VT_nRST");
+
+	/* ISP_RESET */
+	ret = gpio_direction_output(GPIO_ISP_RESET, 0);
+	CAM_CHECK_ERR(ret, "output reset");
+
+	/* CAM_ISP_CORE_1.2V */
+	ret = gpio_direction_output(GPIO_ISP_CORE_EN, 1);
+	CAM_CHECK_ERR_RET(ret, "output GPIO_ISP_CORE_EN");
+
+	regulator = regulator_get(NULL, "cam_isp_core_1.2v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "enable cam_isp_core_1.2v");
+	/* No delay */
+
+	/* CAM_SENSOR_CORE_1.2V */
+	regulator = regulator_get(NULL, "cam_sensor_core_1.2v");
+	if (IS_ERR(regulator)) {
+		CAM_CHECK_ERR_RET(ret, "output Err cam_sensor_core_1.2v");
+		return -ENODEV;
+	}
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "enable cam_sensor_core_1.2v");
+	udelay(10);
+
+	/* CAM_SENSOR_A2.8V */
+	regulator = regulator_get(NULL, "cam_sensor_a2.8v");
+	if (IS_ERR(regulator)) {
+		CAM_CHECK_ERR_RET(ret, "output Err cam_sensor_a2.8v");
+		return -ENODEV;
+	}
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "enable cam_sensor_a2.8v");
+	/* it takes about 100us at least during level transition.*/
+	udelay(160); /* 130us -> 160us */
+
+	/* VT_CAM_DVDD_1.8V */
+	regulator = regulator_get(NULL, "vt_cam_dvdd_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "enable vt_cam_dvdd_1.8v");
+	udelay(10);
+
+	/* VT_CAM_1.8V */
+	regulator = regulator_get(NULL, "vt_cam_1.8v");
+	if (IS_ERR(regulator)) {
+		CAM_CHECK_ERR_RET(ret, "output Err vt_cam_1.8v");
+		return -ENODEV;
+	}
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "enable vt_cam_1.8v");
+	udelay(20);
+
+	/* CAM_VT_nSTBY high */
+	ret = gpio_direction_output(GPIO_CAM_VT_nSTBY, 1);
+	CAM_CHECK_ERR_RET(ret, "output VT_nSTBY");
+	mdelay(2);
+
+	/* MCLK */
+	ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_SFN(2));
+	CAM_CHECK_ERR_RET(ret, "cfg mclk");
+	s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_NONE);
+	mdelay(30);
+
+	/* CAM_VT_nRST	high */
+	gpio_direction_output(GPIO_CAM_VT_nRST, 1);
+	CAM_CHECK_ERR_RET(ret, "output VT_nRST");
+
+	gpio_free(GPIO_CAM_VT_nSTBY);
+	gpio_free(GPIO_CAM_VT_nRST);
+	gpio_free(GPIO_ISP_CORE_EN);
+	gpio_free(GPIO_ISP_RESET);
+
+	return ret;
+}
+
+static int sr200pc20m_power_off(void)
+{
+	struct regulator *regulator;
+	int ret = 0;
+
+	printk(KERN_DEBUG "%s in\n", __func__);
+
+	ret = gpio_request(GPIO_CAM_VT_nSTBY, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "faile to request gpio(GPIO_CAM_VGA_nSTBY)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_CAM_VT_nRST, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "faile to request gpio(GPIO_CAM_VGA_nRST)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_ISP_CORE_EN, "GPM0");
+	if (ret) {
+		printk(KERN_ERR "fail to request gpio(CAM_SENSOR_CORE)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_ISP_RESET, "GPY3");
+	if (ret) {
+		printk(KERN_ERR "faile to request gpio(GPIO_ISP_RESET)\n");
+		return ret;
+	}
+
+	/* ISP_RESET */
+	ret = gpio_direction_output(GPIO_ISP_RESET, 0);
+	CAM_CHECK_ERR(ret, "output reset");
+
+	/* CAM_VT_nRST low */
+	gpio_direction_output(GPIO_CAM_VT_nRST, 0);
+	CAM_CHECK_ERR_RET(ret, "output VT_nRST");
+
+	/* MCLK */
+	ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_DOWN);
+	CAM_CHECK_ERR(ret, "cfg mclk");
+	udelay(20);
+
+	/* CAM_VT_nSTBY low */
+	ret = gpio_direction_output(GPIO_CAM_VT_nSTBY, 0);
+	CAM_CHECK_ERR_RET(ret, "output VT_nSTBY");
+	mdelay(2);
+
+	/* CAM_SENSOR_CORE_1.2V */
+	regulator = regulator_get(NULL, "cam_sensor_core_1.2v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "disable cam_sensor_core_1.2v");
+	udelay(5);
+
+	/* CAM_ISP_CORE_1.2V */
+	ret = gpio_direction_output(GPIO_ISP_CORE_EN, 0);
+	CAM_CHECK_ERR(ret, "output ISP_CORE");
+
+	regulator = regulator_get(NULL, "cam_isp_core_1.2v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "disable cam_isp_core_1.2v");
+
+	/* CAM_SENSOR_A2.8V */
+	regulator = regulator_get(NULL, "cam_sensor_a2.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "disable cam_sensor_a2.8v");
+	udelay(800);
+
+	/* VT_CAM_1.8V */
+	regulator = regulator_get(NULL, "vt_cam_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "disable vt_cam_1.8v");
+	udelay(250); /* 10us -> 250us */
+
+	/* VT_CAM_DVDD_1.8V */
+	regulator = regulator_get(NULL, "vt_cam_dvdd_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "disable vt_cam_dvdd_1.8v");
+	udelay(300); /*10 -> 300 us */
+
+	gpio_free(GPIO_CAM_VT_nSTBY);
+	gpio_free(GPIO_CAM_VT_nRST);
+	gpio_free(GPIO_ISP_CORE_EN);
+	gpio_free(GPIO_ISP_RESET);
+
+	return ret;
+}
+
+static int sr200pc20m_power(int onoff)
+{
+	int ret = 0;
+
+	printk(KERN_DEBUG "%s(): %s\n", __func__, onoff ? "on" : "down");
+
+	if (onoff) {
+		ret = sr200pc20m_power_on();
+		if (unlikely(ret))
+			goto error_out;
+	} else {
+		ret = sr200pc20m_power_off();
+	}
+
+	ret = s3c_csis_power(onoff);
+
+error_out:
+	return ret;
+}
+
+static const char *sr200pc20m_get_clk_name(void)
+{
+	return "sclk_cam0";
+}
+
+static struct sr200pc20m_platform_data sr200pc20m_plat = {
+	.default_width = 640,
+	.default_height = 480,
+	.pixelformat = V4L2_PIX_FMT_UYVY,
+	.freq = 24000000,
+	.is_mipi = 1,
+	.streamoff_delay = 0,
+	.dbg_level = CAMDBG_LEVEL_DEFAULT,
+};
+
+static struct i2c_board_info  sr200pc20m_i2c_info = {
+	I2C_BOARD_INFO("SR200PC20M", 0x40 >> 1),
+	.platform_data = &sr200pc20m_plat,
+};
+
+static struct s3c_platform_camera sr200pc20m = {
+	.id		= CAMERA_CSI_D,
+	.get_clk_name	= sr200pc20m_get_clk_name,
+	.type		= CAM_TYPE_MIPI,
+	.fmt		= ITU_601_YCBCR422_8BIT,
+	.order422	= CAM_ORDER422_8BIT_YCBYCR,
+	.get_i2c_busnum	= sr200pc20m_get_i2c_busnum,
+	.info		= &sr200pc20m_i2c_info,
+	.pixelformat	= V4L2_PIX_FMT_UYVY,
+	.srclk_name	= "xusbxti",
+	.clk_rate	= 24000000,
+	.line_length	= 640,
+	.width		= 640,
+	.height		= 480,
+	.window		= {
+		.left	= 0,
+		.top	= 0,
+		.width	= 640,
+		.height	= 480,
+	},
+
+	.mipi_lanes	= 1,
+	.mipi_settle = 6,
+	.mipi_align	= 32,
+
+	.inv_pclk	= 0,
+	.inv_vsync	= 0,
+	.inv_href	= 0,
+	.inv_hsync	= 0,
+	.reset_camera	= 0,
+	.initialized	= 0,
+	.cam_power	= sr200pc20m_power,
+};
+#endif /* CONFIG_VIDEO_SR200PC20M */
+
+#ifdef CONFIG_VIDEO_SR200PC20
+static int sr200pc20_get_i2c_busnum(void)
+{
+#ifdef CONFIG_MACH_P4
+	pr_info("%s: system_rev=%d\n", __func__);
+	if (system_rev >= 2)
+		return 0;
+	else
+#endif
+		return 13;
+}
+
+static int sr200pc20_power_on(void)
+{
+	struct regulator *regulator;
+	int ret = 0;
+
+#ifndef USE_CAM_GPIO_CFG
+	ret = gpio_request(GPIO_2M_nSTBY, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "Error: fail to request gpio(2M_nSTBY)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_2M_nRST, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "Error: fail to request gpio(2M_nRST)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_3M_nSTBY, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "Error: fail to request gpio(3M_nSTBY)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_3M_nRST, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "Error: fail to request gpio(3M_nRST)\n");
+		return ret;
+	}
+#endif
+
+	/* 3M_nSTBY low */
+	ret = gpio_direction_output(GPIO_3M_nSTBY, 0);
+	CAM_CHECK_ERR_RET(ret, "3M_nSTBY");
+
+	/* 3M_nRST low */
+	ret = gpio_direction_output(GPIO_3M_nRST, 0);
+	CAM_CHECK_ERR_RET(ret, "3M_nRST");
+
+	/* 2M_nSTBY low */
+	ret = gpio_direction_output(GPIO_2M_nSTBY, 0);
+	CAM_CHECK_ERR_RET(ret, "2M_nSTBY");
+
+	/* 2M_nRST low */
+	ret = gpio_direction_output(GPIO_2M_nRST, 0);
+	CAM_CHECK_ERR_RET(ret, "2M_nRST");
+
+	/* 3MP_CORE_1.2V */
+	regulator = regulator_get(NULL, "3mp_core_1.2v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "3mp_core_1.2v");
+	/* udelay(5); */
+
+	/* CAM_IO_1.8V */
+	regulator = regulator_get(NULL, "cam_io_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "cam_io_1.8v");
+	/*udelay(5); */
+
+	/* CAM_A2.8V */
+	regulator = regulator_get(NULL, "cam_a2.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "cam_a2.8v");
+	/* udelay(5); */
+
+	/* VT_CORE_1.8V */
+	regulator = regulator_get(NULL, "vt_core_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "vt_core_1.8v");
+	udelay(20);
+
+	/* ENB High */
+	ret = gpio_direction_output(GPIO_2M_nSTBY, 1);
+	CAM_CHECK_ERR_RET(ret, "2M_nSTBY");
+	udelay(3); /* 30 -> 3 */
+
+	/* CAM_MCLK */
+	ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_SFN(2));
+	CAM_CHECK_ERR_RET(ret, "cfg mclk");
+	s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_NONE);
+	msleep(5); /* >= 5ms */
+
+	/* ENB Low */
+	ret = gpio_direction_output(GPIO_2M_nSTBY, 0);
+	CAM_CHECK_ERR_RET(ret, "2M_nSTBY");
+	msleep(10); /* >= 10ms */
+
+	/* 2M_nRST High*/
+	ret = gpio_direction_output(GPIO_2M_nRST, 1);
+	CAM_CHECK_ERR_RET(ret, "2M_nRST");
+	/*msleep(7);*/ /* >= 7ms */
+
+#if 0
+	/* ENB High */
+	ret = gpio_direction_output(GPIO_2M_nSTBY, 1);
+	CAM_CHECK_ERR_RET(ret, "2M_nSTBY");
+	msleep(12); /* >= 10ms */
+
+	/* ENB Low */
+	ret = gpio_direction_output(GPIO_2M_nSTBY, 0);
+	CAM_CHECK_ERR_RET(ret, "2M_nSTBY");
+	msleep(12); /* >= 10ms */
+
+	/* 2M_nRST Low*/
+	ret = gpio_direction_output(GPIO_2M_nRST, 0);
+	CAM_CHECK_ERR_RET(ret, "2M_nRST");
+	udelay(10); /* >= 16 cycle */
+
+	/* 2M_nRST High */
+	ret = gpio_direction_output(GPIO_2M_nRST, 1);
+	CAM_CHECK_ERR_RET(ret, "2M_nRST");
+#endif
+	udelay(10); /* >= 16 cycle */
+
+#ifndef USE_CAM_GPIO_CFG
+	gpio_free(GPIO_2M_nSTBY);
+	gpio_free(GPIO_2M_nRST);
+	gpio_free(GPIO_3M_nSTBY);
+	gpio_free(GPIO_3M_nRST);
+#endif
+	return 0;
+}
+
+static int sr200pc20_power_off(void)
+{
+	struct regulator *regulator;
+	int ret = 0;
+
+	printk(KERN_DEBUG "%s in\n", __func__);
+
+#ifndef USE_CAM_GPIO_CFG
+	ret = gpio_request(GPIO_2M_nSTBY, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "Error: fail to request gpio(2M_nSTBY)\n");
+		return ret;
+	}
+	ret = gpio_request(GPIO_2M_nRST, "GPL2");
+	if (ret) {
+		printk(KERN_ERR "Error: fail to request gpio(2M_nRST)\n");
+		return ret;
+	}
+#endif
+
+#if 0
+	/* 2M_nRST */
+	ret = gpio_direction_output(GPIO_2M_nRST, 0);
+	CAM_CHECK_ERR_RET(ret, "2M_nRST");
+	udelay(100);
+
+	/* 2M_nSTBY */
+	ret = gpio_direction_output(GPIO_2M_nSTBY, 0);
+	CAM_CHECK_ERR_RET(ret, "2M_nSTBY");
+	udelay(100);
+#endif
+	/* Sleep command */
+	mdelay(1);
+
+	/* 2M_nRST Low*/
+	ret = gpio_direction_output(GPIO_2M_nRST, 0);
+	CAM_CHECK_ERR_RET(ret, "2M_nRST");
+	udelay(3);
+
+	/* CAM_MCLK */
+	ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_DOWN);
+	CAM_CHECK_ERR(ret, "cfg mclk");
+	udelay(10);
+
+	/* ENB High*/
+	ret = gpio_direction_output(GPIO_2M_nSTBY, 1);
+	CAM_CHECK_ERR_RET(ret, "2M_nSTBY");
+	mdelay(5);
+
+	/* ENB Low */
+	ret = gpio_direction_output(GPIO_2M_nSTBY, 0);
+	CAM_CHECK_ERR_RET(ret, "2M_spnSTBY");
+	/* udelay(1); */
+
+	/* VT_CORE_1.8V */
+	regulator = regulator_get(NULL, "vt_core_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "vt_core_1.8v");
+	/* udelay(10); */
+
+	/* CAM_A2.8V */
+	regulator = regulator_get(NULL, "cam_a2.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "cam_a2.8v");
+	/* udelay(10); */
+
+	/* CAM_IO_1.8V */
+	regulator = regulator_get(NULL, "cam_io_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR(ret, "cam_io_1.8v");
+	/*udelay(10); */
+
+	/* 3MP_CORE_1.2V */
+	regulator = regulator_get(NULL, "3mp_core_1.2v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+
+#ifndef USE_CAM_GPIO_CFG
+	gpio_free(GPIO_2M_nSTBY);
+	gpio_free(GPIO_2M_nRST);
+#endif
+	return 0;
+}
+
+static int sr200pc20_power(int onoff)
+{
+	int ret = 0;
+
+	printk(KERN_DEBUG "%s(): %s\n", __func__, onoff ? "on" : "down");
+
+	if (onoff) {
+#ifdef USE_CAM_GPIO_CFG
+		if (cfg_gpio_err) {
+			printk(KERN_ERR "%s: ERROR: gpio configuration",
+				__func__);
+			return cfg_gpio_err;
+		}
+#endif
+		ret = sr200pc20_power_on();
+	} else {
+		ret = sr200pc20_power_off();
+		/* s3c_i2c0_force_stop();*/ /* DSLIM. Should be implemented */
+	}
+
+	return ret;
+}
+
+static const char *sr200pc20_get_clk_name(void)
+{
+	return "sclk_cam0";
+}
+
+static struct sr200pc20_platform_data sr200pc20_plat = {
+	.default_width = 800,
+	.default_height = 600,
+	.pixelformat = V4L2_PIX_FMT_UYVY,
+	.is_mipi = 0,
+	.streamoff_delay = 0,
+	.dbg_level = CAMDBG_LEVEL_DEFAULT,
+};
+#define FRONT_CAM_PLAT		(sr200pc20_plat)
+
+static struct i2c_board_info  sr200pc20_i2c_info = {
+	I2C_BOARD_INFO("SR200PC20", 0x40 >> 1),
+	.platform_data = &sr200pc20_plat,
+};
+
+static struct s3c_platform_camera sr200pc20 = {
+	.id		= CAMERA_PAR_A,
+	.get_clk_name	= sr200pc20_get_clk_name,
+	.type		= CAM_TYPE_ITU,
+	.fmt		= ITU_601_YCBCR422_8BIT,
+	.order422	= CAM_ORDER422_8BIT_YCBYCR,
+	.get_i2c_busnum	= sr200pc20_get_i2c_busnum,
+	.info		= &sr200pc20_i2c_info,
+	.pixelformat	= V4L2_PIX_FMT_UYVY,
+	.srclk_name	= "xusbxti",
+	.clk_rate	= 24000000,
+	.line_length	= 800,
+	.width		= 800,
+	.height		= 600,
+	.window		= {
+		.left	= 0,
+		.top	= 0,
+		.width	= 800,
+		.height	= 600,
+	},
+
+	/* Polarity */
+#if 1 /*def CONFIG_VIDEO_SR200PC20_P4W */
+	.inv_pclk	= 0,
+	.inv_vsync	= 1,
+#else
+	.inv_pclk	= 1,
+	.inv_vsync	= 0,
+#endif
+	.inv_href	= 0,
+	.inv_hsync	= 0,
+	.reset_camera	= 0,
+	.initialized	= 0,
+	.cam_power	= sr200pc20_power,
+};
+#endif /* CONFIG_VIDEO_SR200PC20 */
+
+
+/* Interface setting */
+static struct s3c_platform_fimc fimc_plat = {
+	.default_cam = CAMERA_CSI_D,
+	.camera = {
+#if defined(CONFIG_VIDEO_S5C73M3) || defined(CONFIG_VIDEO_SLP_S5C73M3)
+		&s5c73m3,
+#endif
+#ifdef CONFIG_VIDEO_ISX012
+		&isx012,
+#endif
+#ifdef CONFIG_VIDEO_S5K6A3
+		&s5k6a3,
+#endif
+#if defined(CONFIG_VIDEO_S5K6A3) && defined(CONFIG_S5K6A3_CSI_D)
+		&s5k6a3_fd,
+#endif
+#if defined(CONFIG_VIDEO_M5MO)
+		&m5mo,
+#endif
+#if defined(CONFIG_VIDEO_M9MO)
+		&m9mo,
+#endif
+#if defined(CONFIG_VIDEO_SR200PC20M)
+		&sr200pc20m,
+#endif
+#ifdef CONFIG_VIDEO_S5K5CCGX_COMMON
+		&s5k5ccgx,
+#endif
+#ifdef CONFIG_VIDEO_SR200PC20
+		&sr200pc20,
+#endif
+#ifdef WRITEBACK_ENABLED
+		&writeback,
+#endif
+	},
+	.hw_ver		= 0x51,
+};
+
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_LITE
+static void __set_flite_camera_config(struct exynos_platform_flite *data,
+			u32 active_index, u32 max_cam)
+{
+	data->active_cam_index = active_index;
+	data->num_clients = max_cam;
+}
+
+static void __init smdk4x12_set_camera_flite_platdata(void)
+{
+	int flite0_cam_index = 0;
+	int flite1_cam_index = 0;
+#ifdef CONFIG_VIDEO_S5K6A3
+	exynos_flite1_default_data.cam[flite1_cam_index++] = &s5k6a3;
+#endif
+#ifdef CONFIG_VIDEO_SR200PC20M
+	exynos_flite1_default_data.cam[flite1_cam_index++] = &sr200pc20m;
+#endif
+	__set_flite_camera_config(&exynos_flite0_default_data, 0, flite0_cam_index);
+	__set_flite_camera_config(&exynos_flite1_default_data, 0, flite1_cam_index);
+}
+#endif /* CONFIG_VIDEO_EXYNOS_FIMC_LITE */
+#endif /* CONFIG_VIDEO_FIMC */
+
+#ifdef CONFIG_VIDEO_SAMSUNG_S5P_FIMC
+static struct i2c_board_info __initdata test_info = {
+	I2C_BOARD_INFO("testinfo", 0x0),
+};
+
+static struct s5p_fimc_isp_info isp_info[] = {
+	{
+		.board_info	= &test_info,
+		.bus_type	= FIMC_LCD_WB,
+		.i2c_bus_num	= 0,
+		.mux_id		= 0, /* A-Port : 0, B-Port : 1 */
+		.flags		= FIMC_CLK_INV_VSYNC,
+	},
+};
+
+static void __init midas_subdev_config(void)
+{
+	s3c_fimc0_default_data.isp_info[0] = &isp_info[0];
+	s3c_fimc0_default_data.isp_info[0]->use_cam = true;
+	s3c_fimc0_default_data.isp_info[1] = &isp_info[1];
+	s3c_fimc0_default_data.isp_info[1]->use_cam = false;
+	s3c_fimc0_default_data.isp_info[2] = &isp_info[1];
+	s3c_fimc0_default_data.isp_info[2]->use_cam = false;
+	s3c_fimc0_default_data.isp_info[3] = &isp_info[1];
+	s3c_fimc0_default_data.isp_info[3]->use_cam = false;
+}
+#endif	/* CONFIG_VIDEO_SAMSUNG_S5P_FIMC */
+
+void __init midas_camera_init(void)
+{
+#ifdef CONFIG_VIDEO_FIMC
+	s3c_fimc0_set_platdata(&fimc_plat);
+	s3c_fimc1_set_platdata(&fimc_plat);
+	s3c_fimc2_set_platdata(NULL);
+#ifdef CONFIG_DRM_EXYNOS_FIMD_WB
+	s3c_fimc3_set_platdata(&fimc_plat);
+#else
+	s3c_fimc3_set_platdata(NULL);
+#endif
+#ifdef CONFIG_EXYNOS_DEV_PD
+	s3c_device_fimc0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+	s3c_device_fimc1.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+	s3c_device_fimc2.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+	s3c_device_fimc3.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+	secmem.parent = &exynos4_device_pd[PD_CAM].dev;
+#endif
+#endif
+#ifdef CONFIG_VIDEO_FIMC_MIPI
+	s3c_csis0_set_platdata(NULL);
+	s3c_csis1_set_platdata(NULL);
+#ifdef CONFIG_EXYNOS_DEV_PD
+	s3c_device_csis0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+	s3c_device_csis1.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+#endif
+#endif
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_LITE
+	smdk4x12_set_camera_flite_platdata();
+	s3c_set_platdata(&exynos_flite0_default_data,
+		sizeof(exynos_flite0_default_data), &exynos_device_flite0);
+	s3c_set_platdata(&exynos_flite1_default_data,
+		sizeof(exynos_flite1_default_data), &exynos_device_flite1);
+#endif
+#endif /* CONFIG_VIDEO_FIMC */
+
+#ifdef CONFIG_VIDEO_SAMSUNG_S5P_FIMC
+	midas_subdev_config();
+
+	dev_set_name(&s5p_device_fimc0.dev, "s3c-fimc.0");
+	dev_set_name(&s5p_device_fimc1.dev, "s3c-fimc.1");
+	dev_set_name(&s5p_device_fimc2.dev, "s3c-fimc.2");
+	dev_set_name(&s5p_device_fimc3.dev, "s3c-fimc.3");
+
+	clk_add_alias("fimc", "exynos4210-fimc.0", "fimc",
+			&s5p_device_fimc0.dev);
+	clk_add_alias("fimc", "exynos4210-fimc.1", "fimc",
+			&s5p_device_fimc1.dev);
+	clk_add_alias("fimc", "exynos4210-fimc.2", "fimc",
+			&s5p_device_fimc2.dev);
+	clk_add_alias("fimc", "exynos4210-fimc.3", "fimc",
+			&s5p_device_fimc3.dev);
+	clk_add_alias("sclk_fimc", "exynos4210-fimc.0", "sclk_fimc",
+			&s5p_device_fimc0.dev);
+	clk_add_alias("sclk_fimc", "exynos4210-fimc.1", "sclk_fimc",
+			&s5p_device_fimc1.dev);
+	clk_add_alias("sclk_fimc", "exynos4210-fimc.2", "sclk_fimc",
+			&s5p_device_fimc2.dev);
+	clk_add_alias("sclk_fimc", "exynos4210-fimc.3", "sclk_fimc",
+			&s5p_device_fimc3.dev);
+
+	s3c_fimc_setname(0, "exynos4210-fimc");
+	s3c_fimc_setname(1, "exynos4210-fimc");
+	s3c_fimc_setname(2, "exynos4210-fimc");
+	s3c_fimc_setname(3, "exynos4210-fimc");
+
+	s3c_set_platdata(&s3c_fimc0_default_data,
+			 sizeof(s3c_fimc0_default_data), &s5p_device_fimc0);
+	s3c_set_platdata(&s3c_fimc1_default_data,
+			 sizeof(s3c_fimc1_default_data), &s5p_device_fimc1);
+	s3c_set_platdata(&s3c_fimc2_default_data,
+			 sizeof(s3c_fimc2_default_data), &s5p_device_fimc2);
+	s3c_set_platdata(&s3c_fimc3_default_data,
+			 sizeof(s3c_fimc3_default_data), &s5p_device_fimc3);
+#ifdef CONFIG_EXYNOS_DEV_PD
+	s5p_device_fimc0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+	s5p_device_fimc1.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+	s5p_device_fimc2.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+	s5p_device_fimc3.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+#endif
+#endif /* CONFIG_VIDEO_S5P_FIMC */
+
+#if defined(CONFIG_MACH_P4NOTE) && defined(CONFIG_VIDEO_ISX012)
+	px_cam_cfg_init();
+#endif
+}
diff --git a/arch/arm/mach-exynos/midas-extcon.c b/arch/arm/mach-exynos/midas-extcon.c
new file mode 100644
index 0000000..f65bf04
--- /dev/null
+++ b/arch/arm/mach-exynos/midas-extcon.c
@@ -0,0 +1,90 @@
+/*
+ * midas-extcon.c - EXTCON (External Connector)
+ *
+ *  Copyright (C) 2012 Samsung Electrnoics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/err.h>
+#include <linux/extcon.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/host_notify.h>
+#include <linux/power_supply.h>
+#include <linux/regulator/machine.h>
+
+#include <plat/devs.h>
+#include <plat/udc-hs.h>
+
+#ifdef CONFIG_JACK_MON
+#include <linux/jack.h>
+#endif
+
+#define EXTCON_DEV_NAME		"max77693-muic"
+
+static struct extcon_dev *midas_extcon;
+static struct notifier_block extcon_nb;
+static struct work_struct extcon_notifier_work;
+static unsigned long prev_value;
+
+static void midas_extcon_notifier_work(struct work_struct *work)
+{
+	/* TODO */
+}
+
+static int midas_extcon_notifier(struct notifier_block *self,
+		unsigned long event, void *ptr)
+{
+	/* Store the previous cable state of extcon device */
+	prev_value = event;
+
+	schedule_work(&extcon_notifier_work);
+
+	return NOTIFY_DONE;
+}
+
+static int __init midas_extcon_init(void)
+{
+	int ret;
+
+	midas_extcon = extcon_get_extcon_dev(EXTCON_DEV_NAME);
+	if (!midas_extcon) {
+		printk(KERN_ERR "Failed to get extcon device of %s\n",
+				EXTCON_DEV_NAME);
+		ret = -EINVAL;
+		goto err_extcon;
+	}
+
+	INIT_WORK(&extcon_notifier_work, midas_extcon_notifier_work);
+	extcon_nb.notifier_call = midas_extcon_notifier;
+	ret = extcon_register_notifier(midas_extcon, &extcon_nb);
+	if (ret < 0) {
+		pr_err("Failed to register extcon device for mms_ts\n");
+		ret = -EINVAL;
+		goto err_extcon;
+	}
+
+	/* TODO */
+
+	return 0;
+
+err_extcon:
+	midas_extcon = NULL;
+	return ret;
+}
+late_initcall(midas_extcon_init);
diff --git a/arch/arm/mach-exynos/midas-gpio.c b/arch/arm/mach-exynos/midas-gpio.c
new file mode 100644
index 0000000..cb69a05
--- /dev/null
+++ b/arch/arm/mach-exynos/midas-gpio.c
@@ -0,0 +1,2873 @@
+/*
+ *  linux/arch/arm/mach-exynos/midas-gpio.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * EXYNOS - GPIO setting in set board
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/gpio.h>
+#include <linux/serial_core.h>
+#include <plat/devs.h>
+#include <plat/gpio-cfg.h>
+#include <plat/regs-serial.h>
+#include <mach/gpio-midas.h>
+#include <plat/cpu.h>
+#include <mach/pmu.h>
+
+struct gpio_init_data {
+	uint num;
+	uint cfg;
+	uint val;
+	uint pud;
+	uint drv;
+};
+
+extern int s3c_gpio_slp_cfgpin(unsigned int pin, unsigned int config);
+extern int s3c_gpio_slp_setpull_updown(unsigned int pin, unsigned int config);
+
+#if !defined(CONFIG_MIDAS_COMMON)
+/* this is sample code for midas board */
+static struct gpio_init_data midas_init_gpios[] = {
+	{EXYNOS4_GPD0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* CODEC_SDA_1.8V */
+	{EXYNOS4_GPD0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* CODEC_SCL_1.8V */
+#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) || \
+	defined(CONFIG_MACH_M3)
+	{EXYNOS4_GPD1(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* NFC_SDA_1.8V */
+	{EXYNOS4_GPD1(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* NFC_SCL_1.8V */
+#endif
+	{EXYNOS4_GPD1(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* GSENSE_SDA_1.8V */
+	{EXYNOS4_GPD1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* GSENSE_SCL_1.8V */
+
+	{EXYNOS4_GPX0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* EAR_DET */
+	{EXYNOS4_GPX0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* PS_ALS_INT */
+	{EXYNOS4_GPX0(7), S3C_GPIO_SFN(0xF), S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* AP_PMIC_IRQ */
+
+	{EXYNOS4_GPX1(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* NFC_IRQ */
+
+	{EXYNOS4_GPX2(0), S3C_GPIO_SFN(2), S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* VOL_UP */
+	{EXYNOS4_GPX2(1), S3C_GPIO_SFN(2), S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* VOL_DOWN */
+	{EXYNOS4_GPX2(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* FUEL_ALERT */
+
+#ifdef CONFIG_BATTERY_WPC_CHARGER
+	{EXYNOS4_GPX2(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* V_BUS_INT */
+#endif
+	{EXYNOS4_GPX2(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_HOST_WAKEUP */
+	{EXYNOS4_GPX2(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* BT_HOST_WAKEUP */
+
+#ifdef CONFIG_BATTERY_WPC_CHARGER
+	{EXYNOS4_GPX3(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WPC_INT */
+#endif
+	{EXYNOS4_GPX3(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* BT_WAKE */
+
+	{EXYNOS4212_GPJ0(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_ZERO,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV4}, /* WLAN_EN */
+	{EXYNOS4_GPK3(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_CMD */
+	{EXYNOS4_GPK3(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(0) */
+	{EXYNOS4_GPK3(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(1) */
+	{EXYNOS4_GPK3(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(2) */
+	{EXYNOS4_GPK3(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(3) */
+
+};
+
+/* this table only for midas board */
+static unsigned int exynos4_sleep_gpio_table_common[][3] = {
+	{EXYNOS4_GPA0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+	{EXYNOS4_GPA0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+
+	{EXYNOS4_GPA1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPB(0),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(1),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(2),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(3),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(4),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPB(5),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+	{EXYNOS4_GPB(6),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPB(7),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+#if defined(CONFIG_MACH_C1_KOR_LGT)
+	{EXYNOS4_GPC0(0),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4_GPC0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+#endif
+	{EXYNOS4_GPC0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#if defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT)
+	{EXYNOS4_GPC0(2),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4_GPC0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+#endif
+	{EXYNOS4_GPC0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+#if defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT) || \
+	defined(CONFIG_MACH_C1_KOR_LGT)
+	{EXYNOS4_GPC0(4),  S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_NONE},
+#elif defined(CONFIG_MACH_C1VZW)
+	{EXYNOS4_GPC0(4),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4_GPC0(4),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+#endif
+
+	{EXYNOS4_GPC1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPC1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPC1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPC1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPC1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPD0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPD0(1),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPD0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPD0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPD1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPD1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPD1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPD1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPF0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#if defined(CONFIG_MACH_M0_KOR_SKT) || defined(CONFIG_MACH_M0_KOR_KT)
+	{EXYNOS4_GPF0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4_GPF0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+#endif
+	{EXYNOS4_GPF0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPF1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) || \
+	defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_M3)
+	/* GPF1(6) M0, C1 PDA_ACTIVE, let cp know AP sleep status*/
+	{EXYNOS4_GPF1(6),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4_GPF1(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+	{EXYNOS4_GPF1(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPF2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF2(3),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_DOWN}, /*UART_SEL*/
+	{EXYNOS4_GPF2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#if defined(CONFIG_MACH_C1VZW)
+	{EXYNOS4_GPF2(5),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4_GPF2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+	{EXYNOS4_GPF2(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF2(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPF3(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF3(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF3(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF3(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF3(4),  S3C_GPIO_SLP_OUT1,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF3(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPK0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPK1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK1(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPK2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPK3(0),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPK3(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+#if defined(CONFIG_MACH_M0_KOR_SKT) || defined(CONFIG_MACH_M0_KOR_KT)
+	{EXYNOS4_GPL0(0),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4_GPL0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+#if defined(CONFIG_MACH_S2PLUS)
+	{EXYNOS4_GPL0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+#else
+	{EXYNOS4_GPL0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL0(3),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+#endif
+	{EXYNOS4_GPL0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPL0(5),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL0(6),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL0(7),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+#if defined(CONFIG_MACH_S2PLUS)
+	{EXYNOS4_GPL1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+#else
+	{EXYNOS4_GPL1(0),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+#endif
+	{EXYNOS4_GPL1(2),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPL2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPL2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPL2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) || \
+	defined(CONFIG_MACH_M3)
+	/* GLP2(4) CMC_CPU_RESET, hold high */
+	{EXYNOS4_GPL2(4),  S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* NC */
+#else
+	{EXYNOS4_GPL2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+#if defined(CONFIG_MACH_M0_CMCC)
+	{EXYNOS4_GPL2(5),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4_GPL2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+#endif
+	{EXYNOS4_GPL2(6),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL2(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+#if defined(CONFIG_MACH_M0) || \
+	defined(CONFIG_MACH_JENGA) || defined(CONFIG_MACH_S2PLUS)
+	/* GPX3(2) M0 CP_PMU_RESET, hold high */
+	{EXYNOS4_GPX3(2),  S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE},
+#else
+#endif
+
+	{EXYNOS4_GPY0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPY1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPY3(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY3(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY3(4),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+#if defined(CONFIG_MACH_S2PLUS)
+	{EXYNOS4_GPY3(5),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4_GPY3(5),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+#endif
+	{EXYNOS4_GPY3(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY3(7),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPY4(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+#if defined(CONFIG_MACH_S2PLUS)
+	/* GPY4(2) S2Plus PDA_ACTIVE, let cp know AP sleep status*/
+	{EXYNOS4_GPY4(2),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4_GPY4(2),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+#endif
+	{EXYNOS4_GPY4(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+#if defined(CONFIG_MACH_S2PLUS)
+	{EXYNOS4_GPY4(5),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(6),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(7),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4_GPY4(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY4(6),  S3C_GPIO_SLP_OUT1,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(7),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+#endif
+
+	{EXYNOS4_GPY5(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY5(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY5(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY5(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY5(4),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	/* PMIC_DVS1(Q) / NC(D) */
+	{EXYNOS4_GPY5(5),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+	/* PMIC_DVS2(Q) / NC(D) */
+	{EXYNOS4_GPY5(6),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+	/* PMIC_DVS3(Q) / NC(D) */
+	{EXYNOS4_GPY5(7),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+
+	/* BUCK2_SEL(Q) / NC(D) */
+	{EXYNOS4_GPY6(0),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY6(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	/* BUCK3_SEL(Q) / NC(D) */
+	{EXYNOS4_GPY6(3),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+	/* BUCK4_SEL(Q) / NC(D) */
+	{EXYNOS4_GPY6(4),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY6(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+	{EXYNOS4_GPY6(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPZ(0),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPZ(1),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPZ(2),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPZ(3),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPZ(4),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPZ(5),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPZ(6),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+};
+
+static unsigned int exynos4210_sleep_gpio_table[][3] = {
+	{EXYNOS4210_GPE0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4210_GPE1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE1(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE1(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4210_GPE2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4210_GPE3(0),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE3(1),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE3(2),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE3(3),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE3(4),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE3(5),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE3(6),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE3(7),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4210_GPE4(0),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE4(1),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE4(2),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE4(3),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE4(4),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE4(5),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE4(6),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE4(7),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4210_GPJ0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPJ0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPJ0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPJ0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPJ0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPJ0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPJ0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPJ0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4210_GPJ1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPJ1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPJ1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPJ1(3),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPJ1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+};
+
+static unsigned int exynos4212_sleep_gpio_table[][3] = {
+	{EXYNOS4212_GPJ0(0),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4212_GPJ0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPJ0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPJ0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPJ0(4),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+#if defined(CONFIG_MACH_S2PLUS)
+	{EXYNOS4212_GPJ0(5),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4212_GPJ0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+#endif
+	{EXYNOS4212_GPJ0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPJ0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPJ1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4212_GPJ1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPJ1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPJ1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPJ1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPM0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPM1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM1(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPM2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPM2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPM3(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM3(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM3(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#if defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_SLP_PQ) || \
+	defined(CONFIG_MACH_JENGA) || defined(CONFIG_MACH_S2PLUS)
+	/* GPM3(3) M0, CP_RESET_REQ hold high */
+	{EXYNOS4212_GPM3(3),  S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_DOWN},
+#else
+	{EXYNOS4212_GPM3(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+	{EXYNOS4212_GPM3(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM3(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* ISP_TXD */
+	{EXYNOS4212_GPM3(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM3(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* ISP_RXD */
+
+	{EXYNOS4212_GPM4(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM4(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM4(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* VT_CAM_SCL */
+	{EXYNOS4212_GPM4(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* VT_CAM_SDA */
+	{EXYNOS4212_GPM4(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#if defined(CONFIG_MACH_S2PLUS)
+	{EXYNOS4212_GPM4(5),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* MICBAS_EN */
+	{EXYNOS4212_GPM4(6),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* SUB_MICBIAS_EN */
+#else
+	{EXYNOS4212_GPM4(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM4(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+	{EXYNOS4212_GPM4(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPV0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPV1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPV2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPV3(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPV4(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV4(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+};
+
+static unsigned int exynos4212_sleep_gpio_table_c2c[][3] = {
+	{EXYNOS4212_GPJ0(0),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4212_GPJ0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPJ0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPJ0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPJ0(4),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4212_GPJ0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPJ0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPJ0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPJ1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4212_GPJ1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPJ1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPJ1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPJ1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPM0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPM1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM1(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPM2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPM2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPM3(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM3(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM3(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM3(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM3(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM3(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* ISP_TXD */
+	{EXYNOS4212_GPM3(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM3(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* ISP_RXD */
+
+	{EXYNOS4212_GPM4(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM4(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM4(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* VT_CAM_SCL */
+	{EXYNOS4212_GPM4(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* VT_CAM_SDA */
+	{EXYNOS4212_GPM4(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM4(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM4(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM4(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPV0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPV1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPV2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPV3(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPV4(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV4(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+};
+#endif
+
+#ifdef CONFIG_MIDAS_COMMON
+/*
+ * M0 GPIO Init Table
+ */
+static struct gpio_init_data m0_init_gpios[] = {
+#if !defined(CONFIG_MACH_M0_CMCC)
+	{EXYNOS4_GPA1(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4_GPA1(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+#endif
+	{EXYNOS4_GPD0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPD0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1},
+#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW)
+	{EXYNOS4_GPD1(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* NFC_SDA_1.8V */
+	{EXYNOS4_GPD1(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* NFC_SCL_1.8V */
+#endif
+	{EXYNOS4_GPD1(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* GSENSE_SDA_1.8V */
+	{EXYNOS4_GPD1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* GSENSE_SCL_1.8V */
+
+#if defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT) || \
+	defined(CONFIG_MACH_C1_KOR_LGT)
+	{EXYNOS4_GPX0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+			S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* DET_3.5 */
+#endif
+	{EXYNOS4_GPX0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* PS_ALS_INT */
+	{EXYNOS4_GPX0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPX0(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPX0(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPX0(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+
+	{EXYNOS4_GPX0(7), S3C_GPIO_SFN(0xF), S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* AP_PMIC_IRQ */
+
+	{EXYNOS4_GPX1(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPX1(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* NFC_IRQ */
+
+	{EXYNOS4_GPX2(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPX2(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+#if defined(CONFIG_MACH_M0_CMCC)
+	{EXYNOS4_GPX2(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+#endif
+	{EXYNOS4_GPX2(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* V_BUS_INT */
+	{EXYNOS4_GPX2(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* FUEL_ALERT */
+	{EXYNOS4_GPX2(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_HOST_WAKEUP */
+	{EXYNOS4_GPX2(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* BT_HOST_WAKEUP */
+	{EXYNOS4_GPX2(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* nPower */
+
+	{EXYNOS4_GPX3(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WPC_INT */
+	{EXYNOS4_GPX3(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* BT_WAKE */
+#if defined(CONFIG_MACH_M0)
+	{EXYNOS4_GPX3(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* CP_PMU_RST */
+#endif
+#if defined(CONFIG_SEC_MODEM_M0_TD)
+	{EXYNOS4_GPX3(5), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1},
+#else
+	{EXYNOS4_GPX3(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+#endif
+	{EXYNOS4212_GPJ0(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_ZERO,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV4}, /* WLAN_EN */
+#if defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT) || \
+	defined(CONFIG_MACH_C1_KOR_LGT)
+	{EXYNOS4_GPK3(0), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_CLK */
+#endif
+	{EXYNOS4_GPK3(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_CMD */
+#if defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT) || \
+	defined(CONFIG_MACH_C1_KOR_LGT)
+	{EXYNOS4_GPK3(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+#endif
+	{EXYNOS4_GPK3(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(0) */
+	{EXYNOS4_GPK3(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(1) */
+	{EXYNOS4_GPK3(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(2) */
+	{EXYNOS4_GPK3(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(3) */
+
+	{EXYNOS4212_GPM3(0), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* PMIC_DVS1 */
+
+	{EXYNOS4_GPY0(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4_GPY0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+#if defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT) || \
+	defined(CONFIG_MACH_C1_KOR_LGT)
+	{EXYNOS4_GPY0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4_GPY0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+#endif
+	{EXYNOS4_GPY0(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4_GPY0(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4_GPY1(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4_GPY1(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4_GPY1(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4_GPY1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4_GPY2(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+
+	{EXYNOS4212_GPJ1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV3}, /* CAM_MCLK */
+	{EXYNOS4212_GPM2(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV3}, /* VTCAM_MCLK */
+};
+
+/*
+ * M0 GPIO Sleep Table
+ */
+static unsigned int m0_sleep_gpio_table[][3] = {
+	{EXYNOS4_GPA0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(1),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+	{EXYNOS4_GPA0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+
+	{EXYNOS4_GPA1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPB(0),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(1),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(2),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(3),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(4),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPB(5),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+	{EXYNOS4_GPB(6),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPB(7),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+#if defined(CONFIG_MACH_C1_KOR_LGT)
+	{EXYNOS4_GPC0(0),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4_GPC0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* REC_PCM_CLK(NC) */
+#endif
+	{EXYNOS4_GPC0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#if defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT)
+	{EXYNOS4_GPC0(2),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4_GPC0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* REC_PCM_SYNC(NC) */
+#endif
+#if defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT) || \
+	defined(CONFIG_MACH_C1_KOR_LGT)
+	{EXYNOS4_GPC0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPC0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+#elif defined(CONFIG_MACH_C1VZW)
+	{EXYNOS4_GPC0(3),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPC0(4),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4_GPC0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* REC_PCM_IN(NC) */
+	{EXYNOS4_GPC0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* REC_PCM_OUT(NC) */
+#endif
+#if defined(CONFIG_SEC_MODEM_M0_TD)
+	{EXYNOS4_GPC1(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4_GPC1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+#endif
+	{EXYNOS4_GPC1(1),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* FM_RST */
+
+	{EXYNOS4_GPC1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPC1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPC1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPD0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPD0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPD0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPD0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPD1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPD1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPD1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPD1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPF0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPF0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPF0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPF0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPF0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPF0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPF1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW)
+	/* CMC221 Active States */
+	{EXYNOS4_GPF1(1),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_DOWN}, /* NC */
+#else
+	{EXYNOS4_GPF1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+	{EXYNOS4_GPF1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPF1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) || \
+	defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_SLP_PQ)
+	/* GPF1(6) M0, C1 PDA_ACTIVE, let cp know AP sleep status*/
+	{EXYNOS4_GPF1(6),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4_GPF1(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+	{EXYNOS4_GPF1(7),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NC */
+
+	{EXYNOS4_GPF2(0),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPF2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#if defined(CONFIG_MACH_C1VZW)
+	{EXYNOS4_GPF2(5),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4_GPF2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+	{EXYNOS4_GPF2(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* S_LED_I2C_SCL */
+	{EXYNOS4_GPF2(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* S_LED_I2C_SDA */
+
+	{EXYNOS4_GPF3(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPF3(1),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* BUCK2_SEL */
+	{EXYNOS4_GPF3(2),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* BUCK3_SEL */
+	{EXYNOS4_GPF3(3),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* BUCK4_SEL */
+	{EXYNOS4_GPF3(4),  S3C_GPIO_SLP_OUT1,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF3(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPK0(0),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_CLK */
+	{EXYNOS4_GPK0(1),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_CMD */
+	{EXYNOS4_GPK0(2),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* eMMC_EN */
+	{EXYNOS4_GPK0(3),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(0) */
+	{EXYNOS4_GPK0(4),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(1) */
+	{EXYNOS4_GPK0(5),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(2) */
+	{EXYNOS4_GPK0(6),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(3) */
+
+	{EXYNOS4_GPK1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPK1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK1(3),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(4) */
+	{EXYNOS4_GPK1(4),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(5) */
+	{EXYNOS4_GPK1(5),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(6) */
+	{EXYNOS4_GPK1(6),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(7) */
+
+	{EXYNOS4_GPK2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPK2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPK3(0),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPK3(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPL0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPL0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL0(3),  S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL0(4),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* HDMI_EN */
+/*	{EXYNOS4_GPL0(5),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE}, */
+	{EXYNOS4_GPL0(6),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+/*	{EXYNOS4_GPL0(7),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE}, */
+
+	{EXYNOS4_GPL1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+/*	{EXYNOS4_GPL1(2),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE}, */
+
+	{EXYNOS4_GPL2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPL2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPL2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW)
+	/* GLP2(4) CMC_CPU_RESET, hold high */
+	{EXYNOS4_GPL2(4),  S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE},  /* NC */
+#else
+	{EXYNOS4_GPL2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+#if defined(CONFIG_MACH_M0_CMCC)
+	{EXYNOS4_GPL2(5),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4_GPL2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+#endif
+	{EXYNOS4_GPL2(6),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL2(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW)
+	{EXYNOS4_GPY0(0),  S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE},  /* DPRAM_CSN */
+#else
+	{EXYNOS4_GPY0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+
+#if defined(CONFIG_MACH_C1VZW)
+	{EXYNOS4_GPY0(1),  S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE},  /* VIA_DPRAM_CSN */
+#else
+	{EXYNOS4_GPY0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+
+	{EXYNOS4_GPY0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW)
+	{EXYNOS4_GPY0(4),  S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE},  /* DPRAM_REN */
+	{EXYNOS4_GPY0(5),  S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE},  /* DPRAM_WEN */
+#else
+	{EXYNOS4_GPY0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+
+#if defined(CONFIG_MACH_C1VZW)
+	{EXYNOS4_GPY1(0),  S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE},  /* DPRAM_LBN */
+	{EXYNOS4_GPY1(1),  S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE},  /* DPRAM_UBN */
+#else
+	{EXYNOS4_GPY1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+
+	{EXYNOS4_GPY1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY2(0),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},  /* TF_EN */
+	{EXYNOS4_GPY2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPY3(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY3(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY3(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY3(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY3(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY3(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY3(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY3(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPY4(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY4(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY4(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY4(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY4(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY4(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY4(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY4(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPY5(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPY6(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPZ(0),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPZ(1),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPZ(2),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPZ(3),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPZ(4),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPZ(5),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPZ(6),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	/* Exynos4212 specific gpio */
+	{EXYNOS4212_GPJ0(0),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4212_GPJ0(1),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_DOWN},/*USB_SEL*/
+	{EXYNOS4212_GPJ0(2),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	{EXYNOS4212_GPJ0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPJ0(4),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+#if defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_C1) ||\
+	defined(CONFIG_MACH_C1VZW) || defined(CONFIG_MACH_C1ATT) ||\
+	defined(CONFIG_MACH_S2PLUS) || defined(CONFIG_MACH_SLP_PQ)
+	/* GPIO_PS_ALS_EN */
+	{EXYNOS4212_GPJ0(5),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4212_GPJ0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+	{EXYNOS4212_GPJ0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPJ0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPJ1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPJ1(1),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* TORCH_EN */
+	{EXYNOS4212_GPJ1(2),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* TORCH_SET */
+	{EXYNOS4212_GPJ1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPJ1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPM0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPM1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4212_GPM1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4212_GPM1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4212_GPM1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4212_GPM1(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPM2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4212_GPM2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4212_GPM2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPM2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPM3(0),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* PMIC_DVS1 */
+	{EXYNOS4212_GPM3(1),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* PMIC_DVS2 */
+	{EXYNOS4212_GPM3(2),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* PMIC_DVS3 */
+#if (defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_SLP_PQ)) \
+	&& !defined(CONFIG_MACH_M0_CMCC)
+	/* GPM3(3) M0, CP_RESET_REQ hold high */
+	{EXYNOS4212_GPM3(3),  S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4212_GPM3(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+	{EXYNOS4212_GPM3(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM3(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM3(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM3(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* ISP_RXD */
+
+	{EXYNOS4212_GPM4(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM4(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM4(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* VT_CAM_SCL */
+	{EXYNOS4212_GPM4(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* VT_CAM_SDA */
+	{EXYNOS4212_GPM4(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM4(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM4(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM4(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPV0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPV1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPV2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPV3(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPV4(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV4(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+}; /* m0_sleep_gpio_table */
+
+/*
+ * M0 Rev0.4 GPIO Sleep Table
+ */
+static unsigned int m0_sleep_gpio_table_rev04[][3] = {
+	{EXYNOS4_GPF2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPJ0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPJ0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+};
+
+/*
+ * M0 Rev0.5 GPIO Sleep Table
+ */
+static unsigned int m0_sleep_gpio_table_rev05[][3] = {
+	{EXYNOS4212_GPJ1(0),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CAM_SW_EN */
+};
+
+/*
+ * M0 Rev0.6 GPIO Sleep Table
+ */
+static unsigned int m0_sleep_gpio_table_rev06[][3] = {
+	{EXYNOS4_GPC1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPL0(3),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE}, /* RADIO_EN */
+	{EXYNOS4_GPL2(3),  S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPJ0(2),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* 3_MICBIAS_EN */
+};
+
+/*
+ * M0 Rev0.8 GPIO Sleep Table
+ */
+static unsigned int m0_sleep_gpio_table_rev08[][3] = {
+	{EXYNOS4212_GPJ0(1),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* AP_DUMP_INT */
+	{EXYNOS4212_GPM2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* VTCAM_MCLK */
+};
+
+/*
+ * M0 Rev0.9 GPIO Sleep Table
+ */
+static unsigned int m0_sleep_gpio_table_rev09[][3] = {
+#if defined(CONFIG_SEC_MODEM_M0_TD)
+	{EXYNOS4_GPC1(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	{EXYNOS4212_GPJ0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+#else
+	{EXYNOS4_GPC1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+	{EXYNOS4_GPC1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPC1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+};
+
+/*
+ * M0 Rev1.0 GPIO Sleep Table
+ */
+static unsigned int m0_sleep_gpio_table_rev10[][3] = {
+	{EXYNOS4_GPL0(1),  S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN}, /* 2_TOUCH_SCL_1.8V */
+	{EXYNOS4_GPL0(2),  S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN}, /* 2_TOUCH_SDA_1.8V */
+	{EXYNOS4212_GPJ0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* 2_TOUCH_INT */
+};
+
+/*
+ * M0 Rev1.1 GPIO Sleep Table
+ */
+static unsigned int m0_sleep_gpio_table_rev11[][3] = {
+	{EXYNOS4212_GPJ0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+};
+
+#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW)
+/*
+ * C1 GPIO Sleep Table
+ * Based on C1 Rev0.4(0x6) / C1VZW Rev0.3(0xB)
+ */
+static unsigned int c1_sleep_gpio_table[][3] = {
+	{EXYNOS4_GPA0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(1),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+	{EXYNOS4_GPA0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+
+	{EXYNOS4_GPA1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+#if defined(CONFIG_MACH_C1VZW)
+	{EXYNOS4_GPA1(4),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* AP_VIA_TXD_1.8V */
+	{EXYNOS4_GPA1(5),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* AP_VIA_RXD_1.8V */
+#else
+	{EXYNOS4_GPA1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+#endif
+
+	{EXYNOS4_GPB(0),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(1),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(2),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(3),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(4),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPB(5),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+	{EXYNOS4_GPB(6),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPB(7),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPC0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPC0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* LCD_2.2V_EN */
+	{EXYNOS4_GPC0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC(AP_CP_WAKEUP_1.8V) */
+#if defined(CONFIG_MACH_C1VZW)
+	{EXYNOS4_GPC0(3),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE}, /* EARMICBIAS_EN */
+	{EXYNOS4_GPC0(4),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE}, /* 2MIC_WAKE */
+#else
+	{EXYNOS4_GPC0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* REC_PCM_IN(NC) */
+	{EXYNOS4_GPC0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* REC_PCM_OUT(NC) */
+#endif
+#if defined(CONFIG_MACH_C1VZW)
+	{EXYNOS4_GPC1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* CP_RST_INDICATE_1.8V */
+#else
+	{EXYNOS4_GPC1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+	{EXYNOS4_GPC1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPC1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#if defined(CONFIG_MACH_C1VZW)
+	{EXYNOS4_GPC1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* 2MIC_SDA_1.8V */
+	{EXYNOS4_GPC1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* 2MIC_SCL_1.8V */
+#else
+	{EXYNOS4_GPC1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPC1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+
+	{EXYNOS4_GPD0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPD0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPD0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPD0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPD1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPD1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPD1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPD1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPF0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPF0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPF0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPF0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPF0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPF0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+#if defined(CONFIG_MACH_C1VZW)
+	{EXYNOS4_GPF1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* OLED_ID */
+#else
+	{EXYNOS4_GPF1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+	{EXYNOS4_GPF1(1),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPF1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPF1(6),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF1(7),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NC */
+
+	{EXYNOS4_GPF2(0),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPF2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#if defined(CONFIG_MACH_C1VZW)
+	{EXYNOS4_GPF2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* AP_CMC_INT */
+#else
+	{EXYNOS4_GPF2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* AP_CP_INT */
+#endif
+	{EXYNOS4_GPF2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#if defined(CONFIG_MACH_C1VZW)
+	{EXYNOS4_GPF2(4),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CP_RST_1.8V */
+	{EXYNOS4_GPF2(5),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* 2MIC_RST */
+	{EXYNOS4_GPF2(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* S_LED_I2C_SCL */
+	{EXYNOS4_GPF2(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* S_LED_I2C_SDA */
+#else
+	{EXYNOS4_GPF2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF2(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF2(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+	{EXYNOS4_GPF3(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPF3(1),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* BUCK2_SEL */
+	{EXYNOS4_GPF3(2),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* BUCK3_SEL */
+	{EXYNOS4_GPF3(3),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* BUCK4_SEL */
+	{EXYNOS4_GPF3(4),  S3C_GPIO_SLP_OUT1,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF3(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPK0(0),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_CLK */
+	{EXYNOS4_GPK0(1),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_CMD */
+	{EXYNOS4_GPK0(2),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* eMMC_EN */
+	{EXYNOS4_GPK0(3),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(0) */
+	{EXYNOS4_GPK0(4),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(1) */
+	{EXYNOS4_GPK0(5),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(2) */
+	{EXYNOS4_GPK0(6),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(3) */
+
+	{EXYNOS4_GPK1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPK1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK1(3),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(4) */
+	{EXYNOS4_GPK1(4),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(5) */
+	{EXYNOS4_GPK1(5),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(6) */
+	{EXYNOS4_GPK1(6),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(7) */
+
+	{EXYNOS4_GPK2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPK2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPK3(0),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPK3(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPL0(0),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* USB_HUB_RST */
+	{EXYNOS4_GPL0(1),  S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN}, /* TOUCH_SCL */
+	{EXYNOS4_GPL0(2),  S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN}, /* TOUCH_SDA */
+#if defined(CONFIG_MACH_C1VZW)
+	{EXYNOS4_GPL0(3),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*FM_PW*/
+#else
+	{EXYNOS4_GPL0(3),  S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+	{EXYNOS4_GPL0(4),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* HDMI_EN */
+/*	{EXYNOS4_GPL0(5),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE}, */
+	{EXYNOS4_GPL0(6),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE}, /* BT_EN */
+/*	{EXYNOS4_GPL0(7),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE}, */
+
+	{EXYNOS4_GPL1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* USB_HUB_SCL */
+	{EXYNOS4_GPL1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* USB_HUB_SDA */
+/*	{EXYNOS4_GPL1(2),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE}, */
+
+	{EXYNOS4_GPL2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPL2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPL2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPL2(4),  S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE},  /* CMC221_CPU_RST */
+	{EXYNOS4_GPL2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CMC_PMIC_PWRON */
+	{EXYNOS4_GPL2(6),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL2(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPY0(0),  S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE},  /* DPRAM_CSN */
+#if defined(CONFIG_MACH_C1VZW)
+	{EXYNOS4_GPY0(1),  S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE},  /* VIA_DPRAM_CSN */
+#else
+	{EXYNOS4_GPY0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+	{EXYNOS4_GPY0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY0(4),  S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE},  /* DPRAM_REN */
+	{EXYNOS4_GPY0(5),  S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE},  /* DPRAM_WEN */
+
+#if defined(CONFIG_MACH_C1VZW)
+	{EXYNOS4_GPY1(0),  S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE},  /* DPRAM_LBN */
+	{EXYNOS4_GPY1(1),  S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE},  /* DPRAM_UBN */
+#else
+	{EXYNOS4_GPY1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+#if defined(CONFIG_MACH_C1VZW)
+	{EXYNOS4_GPY1(2),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},/*FM_BP*/
+	{EXYNOS4_GPY1(3),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},/*FM_RST*/
+#else
+	{EXYNOS4_GPY1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+	{EXYNOS4_GPY2(0),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},  /* TF_EN */
+	{EXYNOS4_GPY2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPY3(0),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* DPRAM_A(0) */
+	{EXYNOS4_GPY3(1),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* DPRAM_A(1) */
+	{EXYNOS4_GPY3(2),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* DPRAM_A(2) */
+	{EXYNOS4_GPY3(3),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* DPRAM_A(3) */
+	{EXYNOS4_GPY3(4),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* DPRAM_A(4) */
+	{EXYNOS4_GPY3(5),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* DPRAM_A(5) */
+	{EXYNOS4_GPY3(6),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* DPRAM_A(6) */
+	{EXYNOS4_GPY3(7),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* DPRAM_A(7) */
+
+	{EXYNOS4_GPY4(0),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* DPRAM_A(8) */
+	{EXYNOS4_GPY4(1),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* DPRAM_A(9) */
+	{EXYNOS4_GPY4(2),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* DPRAM_A(10) */
+	{EXYNOS4_GPY4(3),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* DPRAM_A(11) */
+	{EXYNOS4_GPY4(4),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* DPRAM_A(12) */
+	{EXYNOS4_GPY4(5),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* DPRAM_A(13) */
+	{EXYNOS4_GPY4(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY4(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPY5(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPY6(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPZ(0),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+#if defined(CONFIG_MACH_C1VZW)
+	{EXYNOS4_GPZ(1),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#else
+	{EXYNOS4_GPZ(1),   S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* AUTO_DFS */
+#endif
+	{EXYNOS4_GPZ(2),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPZ(3),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPZ(4),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPZ(5),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPZ(6),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	/* Exynos4212 specific gpio */
+	{EXYNOS4212_GPJ0(0),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE}, /* WLAN_EN */
+	{EXYNOS4212_GPJ0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPJ0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPJ0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* TOUCH_INT */
+	{EXYNOS4212_GPJ0(4),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE}, /* CODEC_LDO_EN */
+	{EXYNOS4212_GPJ0(5),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE}, /* PS_ALS_EN */
+#if defined(CONFIG_MACH_C1VZW)
+	{EXYNOS4212_GPJ0(6),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* LTE_VIA_UART_SEL */
+#else
+	{EXYNOS4212_GPJ0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+	{EXYNOS4212_GPJ0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPJ1(0),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CAM_SW_EN */
+	{EXYNOS4212_GPJ1(1),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* TORCH_EN */
+	{EXYNOS4212_GPJ1(2),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* TORCH_SET */
+	{EXYNOS4212_GPJ1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPJ1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPM0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#if defined(CONFIG_MACH_C1VZW)
+	{EXYNOS4212_GPM0(5),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CP_BOOT_SEL_1.8V */
+	{EXYNOS4212_GPM0(6),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CP_PMIC_ON */
+#else
+	{EXYNOS4212_GPM0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+	{EXYNOS4212_GPM0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+#if defined(CONFIG_MACH_C1VZW)
+	{EXYNOS4212_GPM1(0),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* VIA_PS_HOLD_OFF */
+	{EXYNOS4212_GPM1(1),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* VIA_USB_OFF */
+#else
+	{EXYNOS4212_GPM1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+	{EXYNOS4212_GPM1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4212_GPM1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4212_GPM1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4212_GPM1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4212_GPM1(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPM2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4212_GPM2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4212_GPM2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPM3(0),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* PMIC_DVS1 */
+	{EXYNOS4212_GPM3(1),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* PMIC_DVS2 */
+	{EXYNOS4212_GPM3(2),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* PMIC_DVS3 */
+	{EXYNOS4212_GPM3(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM3(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM3(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC(ISP_TXD) */
+	{EXYNOS4212_GPM3(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CMC_SPI_CLK_REQ */
+	{EXYNOS4212_GPM3(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC(ISP_RXD) */
+
+#if defined(CONFIG_MACH_C1VZW)
+	{EXYNOS4212_GPM4(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},/*FM_SCL*/
+	{EXYNOS4212_GPM4(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},/*FM_SDA*/
+#else
+	{EXYNOS4212_GPM4(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM4(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+	{EXYNOS4212_GPM4(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* VT_CAM_SCL */
+	{EXYNOS4212_GPM4(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* VT_CAM_SDA */
+	{EXYNOS4212_GPM4(4),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CMC_CLK_1.8V */
+	{EXYNOS4212_GPM4(5),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CMC_CS_1.8V */
+	{EXYNOS4212_GPM4(6),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CMC_DO_1.8V */
+	{EXYNOS4212_GPM4(7),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CMC_DI_1.8V */
+
+	{EXYNOS4212_GPV0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPV1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPV2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPV3(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPV4(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV4(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+}; /* c1_sleep_gpio_table */
+
+/*
+ * C1 Rev0.5(0x7)
+ */
+static unsigned int c1_sleep_gpio_table_rev05[][3] = {
+#if defined(CONFIG_MACH_C1)
+	{EXYNOS4_GPL0(1),  S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN}, /* TOUCH_SCL */
+	{EXYNOS4_GPL0(2),  S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN}, /* TOUCH_SDA */
+	{EXYNOS4212_GPJ0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* TOUCH_INT */
+	{EXYNOS4212_GPM0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* LED_VDD_EN */
+#endif
+};
+
+/*
+ * C1VZW Rev0.4(0xC)
+ */
+static unsigned int c1vzw_sleep_gpio_table_rev04[][3] = {
+#if defined(CONFIG_MACH_C1VZW)
+	{EXYNOS4_GPC0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPC1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPC1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+};
+#endif
+
+struct m0_sleep_table {
+	unsigned int (*ptr)[3];
+	int size;
+};
+
+#define GPIO_TABLE(_ptr) \
+	{.ptr = _ptr, \
+	.size = ARRAY_SIZE(_ptr)} \
+
+ #define GPIO_TABLE_NULL \
+	{.ptr = NULL, \
+	.size = 0} \
+
+static struct m0_sleep_table m0_sleep_table[] = {
+	GPIO_TABLE(m0_sleep_gpio_table),	/* Rev0.0(0x0) - SLP */
+	GPIO_TABLE_NULL,			/* Rev0.0(0x1) - Android */
+	GPIO_TABLE_NULL,
+	GPIO_TABLE_NULL,
+	GPIO_TABLE_NULL,
+	GPIO_TABLE(m0_sleep_gpio_table_rev04),	/* Rev0.4(0x5) */
+	GPIO_TABLE(m0_sleep_gpio_table_rev05),	/* Rev0.5(0x6) */
+	GPIO_TABLE(m0_sleep_gpio_table_rev06),	/* Rev0.6(0x7) */
+	GPIO_TABLE_NULL,
+	GPIO_TABLE(m0_sleep_gpio_table_rev08),	/* Rev0.8(0x9) */
+	GPIO_TABLE(m0_sleep_gpio_table_rev09),	/* Rev0.9(0xA) */
+	GPIO_TABLE(m0_sleep_gpio_table_rev10),	/* Rev1.0(0xB) */
+	GPIO_TABLE(m0_sleep_gpio_table_rev11),	/* Rev1.1(0xC) */
+};
+
+#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW)
+static struct m0_sleep_table c1_sleep_table[] = {
+	GPIO_TABLE(c1_sleep_gpio_table),	/* Rev0.0(0x0) */
+	GPIO_TABLE_NULL,
+	GPIO_TABLE_NULL,
+	GPIO_TABLE_NULL,
+	GPIO_TABLE_NULL,
+	GPIO_TABLE_NULL,
+	GPIO_TABLE_NULL,
+	GPIO_TABLE(c1_sleep_gpio_table_rev05),	/* C1 Rev0.5(0x7) */
+	GPIO_TABLE_NULL,
+	GPIO_TABLE_NULL,
+	GPIO_TABLE_NULL,
+	GPIO_TABLE_NULL,
+	GPIO_TABLE(c1vzw_sleep_gpio_table_rev04),	/* C1VZW Rev0.4(0xC) */
+};
+#endif
+
+#if defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT) || \
+	defined(CONFIG_MACH_C1_KOR_LGT)
+/*
+ * C1-KOR GPIO Sleep Table
+ */
+static unsigned int c1kor_sleep_gpio_table[][3] = {
+	{EXYNOS4_GPA0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* BT_UART_RXD */
+	{EXYNOS4_GPA0(1),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* BT_UART_TXD */
+	{EXYNOS4_GPA0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* BT_UART_CTS */
+	{EXYNOS4_GPA0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, /* BT_UART_RTS */
+	{EXYNOS4_GPA0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* GPS_UART_RXD */
+	{EXYNOS4_GPA0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* GPS_UART_TXD */
+	{EXYNOS4_GPA0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* GPS_UART_CTS */
+	{EXYNOS4_GPA0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, /* GPS_UART_RTS */
+
+	{EXYNOS4_GPA1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* AP_RXD */
+	{EXYNOS4_GPA1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* AP_TXD */
+	{EXYNOS4_GPA1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* TSP_SDA_1.8V */
+	{EXYNOS4_GPA1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* TSP_SCL_1.8V */
+#if defined(CONFIG_MACH_C1_KOR_LGT)
+	{EXYNOS4_GPA1(4),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* AP_VIA_TXD_1.8V */
+	{EXYNOS4_GPA1(5),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* AP_VIA_RXD_1.8V */
+#else
+	{EXYNOS4_GPA1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPA1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+
+	{EXYNOS4_GPB(0),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* CODEC_SDA_1.8V */
+	{EXYNOS4_GPB(1),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* CODEC_SCL_1.8V */
+	{EXYNOS4_GPB(2),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* MHL_DSCL_1.8V,NFC_SCL_1.8V */
+	{EXYNOS4_GPB(3),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* MHL_DSDA_1.8V,NFC_SDA_1.8V */
+	{EXYNOS4_GPB(4),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_SPI_SCLK */
+	{EXYNOS4_GPB(5),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, /* CAM_SPI_SSN */
+	{EXYNOS4_GPB(6),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_SPI_MISO */
+	{EXYNOS4_GPB(7),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_SPI_MOSI */
+
+#if defined(CONFIG_MACH_C1_KOR_LGT)
+	{EXYNOS4_GPC0(0),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* TDMB_PWR_EN */
+#else
+	{EXYNOS4_GPC0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+	{EXYNOS4_GPC0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* LCD_2.2V_EN */
+#if defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT)
+	{EXYNOS4_GPC0(2),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* TDMB_PWR_EN */
+	{EXYNOS4_GPC0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#else
+	{EXYNOS4_GPC0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* AP_CP_WAKEUP_1.8V */
+	{EXYNOS4_GPC0(3),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* EARMICBIAS_EN */
+#endif
+	{EXYNOS4_GPC0(4),  S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN}, /* TDMB_INT */
+
+#if defined(CONFIG_MACH_C1_KOR_LGT)
+	{EXYNOS4_GPC1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* CP_RST_INDICATE_1.8V */
+#else
+	{EXYNOS4_GPC1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+	{EXYNOS4_GPC1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* TDMB_SPI_CLK */
+	{EXYNOS4_GPC1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* TDMB_SPI_CS */
+	{EXYNOS4_GPC1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* TDMB_SPI_DI */
+	{EXYNOS4_GPC1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* TDMB_SPI_DO */
+
+	{EXYNOS4_GPD0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* VIBTONE_PWM */
+	{EXYNOS4_GPD0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPD0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* AP_PMIC_SDA_1.8V */
+	{EXYNOS4_GPD0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* AP_PMIC_SCL_1.8V */
+
+	{EXYNOS4_GPD1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* 8M_CAM_SDA_1.8V */
+	{EXYNOS4_GPD1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* 8M_CAM_SCL_1.8V */
+	{EXYNOS4_GPD1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* GSENSE_SDA_1.8V */
+	{EXYNOS4_GPD1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* GSENSE_SCL_1.8V */
+
+	{EXYNOS4_GPF0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* RGB_SDA_1.8V_AP */
+	{EXYNOS4_GPF0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* RGB_SCL_1.8V_AP */
+	{EXYNOS4_GPF0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* GYRO_INT */
+	{EXYNOS4_GPF0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* MHL_SDA_1.8V */
+	{EXYNOS4_GPF0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* BARO_INT */
+	{EXYNOS4_GPF0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* MHL_SCL_1.8V */
+	{EXYNOS4_GPF0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* OTG_EN */
+
+	{EXYNOS4_GPF1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* OLED_ID */
+	{EXYNOS4_GPF1(1),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_DOWN}, /* ACTIVE_STATE_HSIC */
+	{EXYNOS4_GPF1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* VT_CAM_ID */
+	{EXYNOS4_GPF1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* ISP_RESET */
+	{EXYNOS4_GPF1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* FUEL_SCL_1.8V */
+	{EXYNOS4_GPF1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* FUEL_SDA_1.8V */
+	{EXYNOS4_GPF1(6),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* PDA_ACTIVE */
+	{EXYNOS4_GPF1(7),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* MICBIAS_EN */
+
+	{EXYNOS4_GPF2(0),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* SUB_MICBIAS_EN */
+	{EXYNOS4_GPF2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* MLCD_RST */
+	{EXYNOS4_GPF2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* AP_CMC_INT */
+	{EXYNOS4_GPF2(3),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* UART_SEL */
+#if defined(CONFIG_MACH_C1_KOR_LGT)
+	{EXYNOS4_GPF2(4),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CP_RST_1.8V */
+#else
+	{EXYNOS4_GPF2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+	{EXYNOS4_GPF2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF2(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* S_LED_I2C_SCL */
+	{EXYNOS4_GPF2(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* S_LED_I2C_SDA */
+
+	{EXYNOS4_GPF3(0),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* OLED_DET */
+	{EXYNOS4_GPF3(1),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* BUCK2_SEL */
+	{EXYNOS4_GPF3(2),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* BUCK3_SEL */
+	{EXYNOS4_GPF3(3),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* BUCK4_SEL */
+	{EXYNOS4_GPF3(4),  S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN}, /* MHL_RST */
+	{EXYNOS4_GPF3(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* MHL_INT */
+
+	{EXYNOS4_GPK0(0),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_CLK */
+	{EXYNOS4_GPK0(1),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_CMD */
+	{EXYNOS4_GPK0(2),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* eMMC_EN */
+	{EXYNOS4_GPK0(3),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(0) */
+	{EXYNOS4_GPK0(4),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(1) */
+	{EXYNOS4_GPK0(5),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(2) */
+	{EXYNOS4_GPK0(6),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(3) */
+
+	{EXYNOS4_GPK1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPK1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPK1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPK1(3),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(4) */
+	{EXYNOS4_GPK1(4),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(5) */
+	{EXYNOS4_GPK1(5),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(6) */
+	{EXYNOS4_GPK1(6),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(7) */
+
+	{EXYNOS4_GPK2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* T_FLASH_CLK */
+	{EXYNOS4_GPK2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* T_FLASH_CMD */
+	{EXYNOS4_GPK2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPK2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* T_FLASH_D(0) */
+	{EXYNOS4_GPK2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* T_FLASH_D(1) */
+	{EXYNOS4_GPK2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* T_FLASH_D(2) */
+	{EXYNOS4_GPK2(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* T_FLASH_D(3) */
+
+	{EXYNOS4_GPK3(0),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE}, /* WLAN_SDIO_CLK */
+	{EXYNOS4_GPK3(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* WLAN_SDIO_CMD */
+	{EXYNOS4_GPK3(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPK3(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* WLAN_SDIO_D(0) */
+	{EXYNOS4_GPK3(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* WLAN_SDIO_D(1) */
+	{EXYNOS4_GPK3(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* WLAN_SDIO_D(2) */
+	{EXYNOS4_GPK3(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* WLAN_SDIO_D(3) */
+
+	{EXYNOS4_GPL0(0),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* USB_HUB_RST */
+	{EXYNOS4_GPL0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPL0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#if defined(CONFIG_MACH_C1_KOR_LGT)
+	{EXYNOS4_GPL0(3),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* GPIO_FM34_PWDN */
+#else
+	{EXYNOS4_GPL0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+	{EXYNOS4_GPL0(4),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* HDMI_EN */
+/*	{EXYNOS4_GPL0(5),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE}, */
+	{EXYNOS4_GPL0(6),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE}, /* BT_EN */
+/*	{EXYNOS4_GPL0(7),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE}, */
+
+	{EXYNOS4_GPL1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* USB_HUB_SCL */
+	{EXYNOS4_GPL1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* USB_HUB_SDA */
+/*	{EXYNOS4_GPL1(2),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE}, */
+
+	{EXYNOS4_GPL2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* GYRO_DE */
+	{EXYNOS4_GPL2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* GPS_nRST */
+	{EXYNOS4_GPL2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* GPS_EN */
+	{EXYNOS4_GPL2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPL2(4),  S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* CMC221_CPU_RST */
+	{EXYNOS4_GPL2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CMC_PMIC_PWRON */
+	{EXYNOS4_GPL2(6),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE}, /* NFC_EN */
+	{EXYNOS4_GPL2(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NFC_FIRMWARE */
+
+#if defined(CONFIG_MACH_C1_KOR_LGT)
+	{EXYNOS4_GPY0(0),  S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* DPRAM_CSN */
+	{EXYNOS4_GPY0(1),  S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* VIA_DPRAM_CSN */
+	{EXYNOS4_GPY0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY0(4),  S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* DPRAM_REN */
+	{EXYNOS4_GPY0(5),  S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* DPRAM_WEN */
+#else
+	{EXYNOS4_GPY0(0),  S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* DPRAM_CSN */
+	{EXYNOS4_GPY0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY0(4),  S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* DPRAM_REN */
+	{EXYNOS4_GPY0(5),  S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* DPRAM_WEN */
+#endif
+
+#if defined(CONFIG_MACH_C1_KOR_LGT)
+	{EXYNOS4_GPY1(0),  S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* DPRAM_LBN */
+	{EXYNOS4_GPY1(1),  S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* DPRAM_UBN */
+#else
+	{EXYNOS4_GPY1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+
+#if defined(CONFIG_MACH_C1_KOR_LGT)
+	{EXYNOS4_GPY1(2),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* GPIO_FM34_BYPASS */
+	{EXYNOS4_GPY1(3),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* GPIO_FM34_RESET */
+#else
+	{EXYNOS4_GPY1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+
+	{EXYNOS4_GPY2(0),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* TF_EN */
+	{EXYNOS4_GPY2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* BSENSE_SDA_1.8V */
+	{EXYNOS4_GPY2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* BSENSE_SCL_1.8V */
+	{EXYNOS4_GPY2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* MSENSE_SDA_1.8V */
+	{EXYNOS4_GPY2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* MSENSE_SCL_1.8V */
+
+	{EXYNOS4_GPY3(0),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* DPRAM_A(0) */
+	{EXYNOS4_GPY3(1),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* DPRAM_A(1) */
+	{EXYNOS4_GPY3(2),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* DPRAM_A(2) */
+	{EXYNOS4_GPY3(3),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* DPRAM_A(3) */
+	{EXYNOS4_GPY3(4),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* DPRAM_A(4) */
+	{EXYNOS4_GPY3(5),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* DPRAM_A(5) */
+	{EXYNOS4_GPY3(6),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* DPRAM_A(6) */
+	{EXYNOS4_GPY3(7),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* DPRAM_A(7) */
+
+	{EXYNOS4_GPY4(0),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* DPRAM_A(8) */
+	{EXYNOS4_GPY4(1),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* DPRAM_A(9) */
+	{EXYNOS4_GPY4(2),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* DPRAM_A(10) */
+	{EXYNOS4_GPY4(3),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* DPRAM_A(11) */
+	{EXYNOS4_GPY4(4),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* DPRAM_A(12) */
+	{EXYNOS4_GPY4(5),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* DPRAM_A(13) */
+	{EXYNOS4_GPY4(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY4(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPY5(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* DPRAM_D(0) */
+	{EXYNOS4_GPY5(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* DPRAM_D(1) */
+	{EXYNOS4_GPY5(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* DPRAM_D(2) */
+	{EXYNOS4_GPY5(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* DPRAM_D(3) */
+	{EXYNOS4_GPY5(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* DPRAM_D(4) */
+	{EXYNOS4_GPY5(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* DPRAM_D(5) */
+	{EXYNOS4_GPY5(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* DPRAM_D(6) */
+	{EXYNOS4_GPY5(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* DPRAM_D(7) */
+
+	{EXYNOS4_GPY6(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* DPRAM_D(8) */
+	{EXYNOS4_GPY6(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* DPRAM_D(9) */
+	{EXYNOS4_GPY6(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* DPRAM_D(10) */
+	{EXYNOS4_GPY6(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* DPRAM_D(11) */
+	{EXYNOS4_GPY6(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* DPRAM_D(12) */
+	{EXYNOS4_GPY6(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* DPRAM_D(13) */
+	{EXYNOS4_GPY6(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* DPRAM_D(14) */
+	{EXYNOS4_GPY6(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* DPRAM_D(15) */
+
+	{EXYNOS4_GPZ(0),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* MM_I2S_CLK */
+	{EXYNOS4_GPZ(1),   S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* AUTO_DFS */
+	{EXYNOS4_GPZ(2),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* MM_I2S_SYNC */
+	{EXYNOS4_GPZ(3),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* MM_I2S_DI */
+	{EXYNOS4_GPZ(4),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* MM_I2S_DO */
+	{EXYNOS4_GPZ(5),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPZ(6),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	/* Exynos4212 specific gpio */
+	{EXYNOS4212_GPJ0(0),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* WLAN_EN */
+	{EXYNOS4212_GPJ0(1),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* USB_SEL */
+	{EXYNOS4212_GPJ0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPJ0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CMC_USB_DETECT(Cur NC) */
+	{EXYNOS4212_GPJ0(4),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CODEC_LDO_EN */
+	{EXYNOS4212_GPJ0(5),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* PS_ALS_EN */
+#if defined(CONFIG_MACH_C1_KOR_LGT)
+	{EXYNOS4212_GPJ0(6),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* LTE_VIA_UART_SEL */
+#else
+	{EXYNOS4212_GPJ0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+	{EXYNOS4212_GPJ0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* MSENSE_INT */
+
+	{EXYNOS4212_GPJ1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPJ1(1),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* TORCH_EN */
+	{EXYNOS4212_GPJ1(2),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* TORCH_SET */
+	{EXYNOS4212_GPJ1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_MCLK */
+	{EXYNOS4212_GPJ1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* MHL_WAKE_UP */
+
+	{EXYNOS4212_GPM0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* ISP_STANDBY */
+	{EXYNOS4212_GPM0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_IO_EN */
+	{EXYNOS4212_GPM0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_ISP_CORE_EN */
+	{EXYNOS4212_GPM0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_AF_EN */
+#if defined(CONFIG_MACH_C1_KOR_LGT)
+	{EXYNOS4212_GPM0(5),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CP_BOOT_SEL_1.8V */
+	{EXYNOS4212_GPM0(6),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CP_ON */
+#else
+	{EXYNOS4212_GPM0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+	{EXYNOS4212_GPM0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+#if defined(CONFIG_MACH_C1_KOR_LGT)
+	{EXYNOS4212_GPM1(0),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* VIA_PS_HOLD_OFF */
+	{EXYNOS4212_GPM1(1),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* VIA_USB_OFF */
+#else
+	{EXYNOS4212_GPM1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+	{EXYNOS4212_GPM1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* HW_REV0 */
+	{EXYNOS4212_GPM1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* HW_REV1 */
+	{EXYNOS4212_GPM1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* HW_REV2 */
+	{EXYNOS4212_GPM1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* HW_REV3 */
+	{EXYNOS4212_GPM1(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_VT_nRST */
+
+	{EXYNOS4212_GPM2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* IF_PMIC_SDA_1.8V */
+	{EXYNOS4212_GPM2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* IF_PMIC_SCL_1.8V */
+	{EXYNOS4212_GPM2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* TSP_nINT */
+	{EXYNOS4212_GPM2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* SUSPEND_REQUEST_HSIC */
+
+	{EXYNOS4212_GPM3(0),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* PMIC_DVS1 */
+	{EXYNOS4212_GPM3(1),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* PMIC_DVS2 */
+	{EXYNOS4212_GPM3(2),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* PMIC_DVS3 */
+	{EXYNOS4212_GPM3(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM3(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM3(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC(SKT,KT),ISP_TXD(LGT) */
+	{EXYNOS4212_GPM3(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CMC_SPI_CLK_REQ */
+	{EXYNOS4212_GPM3(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC(SKT,KT),ISP_RXD(LGT) */
+
+	{EXYNOS4212_GPM4(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* 1K PU */
+	{EXYNOS4212_GPM4(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* 1K PU */
+	{EXYNOS4212_GPM4(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* VT_CAM_SCL */
+	{EXYNOS4212_GPM4(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* VT_CAM_SDA */
+	{EXYNOS4212_GPM4(4),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CMC_CLK_1.8V */
+	{EXYNOS4212_GPM4(5),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CMC_CS_1.8V */
+	{EXYNOS4212_GPM4(6),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CMC_DI_1.8V */
+	{EXYNOS4212_GPM4(7),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CMC_DO_1.8V */
+
+	{EXYNOS4212_GPV0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPV1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV1(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV1(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPV2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV2(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV2(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPV3(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV3(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV3(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV3(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV3(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV3(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV3(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV3(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPV4(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPV4(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+}; /* clkor_sleep_gpio_table */
+
+/*
+ * c1kor Rev0.5 GPIO Sleep Table
+ */
+static unsigned int c1kor_sleep_gpio_table_rev05[][3] = {
+#if defined(CONFIG_MACH_C1_KOR_LGT)
+	{EXYNOS4_GPC0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* EARMICBIAS_EN -> NC */
+	{EXYNOS4_GPL0(1),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NC -> VP_RST_N*/
+	{EXYNOS4_GPL0(2),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NC -> VP_BP_N */
+	{EXYNOS4_GPL0(3),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NC -> VP_PWDN_N */
+#endif
+	{EXYNOS4_GPF2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* UART_SEL -> NC(LG AUTO_DFS) */
+	{EXYNOS4212_GPJ0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* USB_SEL -> NC */
+	{EXYNOS4212_GPJ1(0),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NC -> CAM_SW_EN */
+#if defined(CONFIG_MACH_C1_KOR_LGT)
+	{EXYNOS4212_GPM0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CP_BOOT_SEL_1.8V -> Open */
+	{EXYNOS4212_GPM4(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC -> VP_SCL */
+	{EXYNOS4212_GPM4(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC -> VP_SDA */
+#else
+	{EXYNOS4212_GPM4(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* 1K PU (NC)*/
+	{EXYNOS4212_GPM4(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* 1K PU (NC)*/
+#endif
+};
+
+static unsigned int c1kor_sleep_gpio_table_rev06[][3] = {
+#if defined(CONFIG_MACH_C1_KOR_LGT)
+	{EXYNOS4_GPL0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* VP_RST_N -> TOUCH_SCL_1.8V */
+	{EXYNOS4_GPL0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* VP_BP_N -> TOUCH_SDA_1.8V*/
+	{EXYNOS4212_GPM0(0),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* NC -> KEY_LED_EN */
+	{EXYNOS4_GPY1(2),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NC -> VP_BP_N */
+	{EXYNOS4_GPY1(3),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NC -> VP_RST_N */
+#endif
+};
+
+static unsigned int c1kor_sleep_gpio_table_rev07[][3] = {
+	{EXYNOS4_GPF2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC -> AUTO_DFS */
+#if defined(CONFIG_MACH_C1_KOR_LGT)
+	{EXYNOS4212_GPM1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* VIA_USB_OFF -> NC */
+#endif
+	{EXYNOS4212_GPM2(2),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* CAM_MCLK_VGA */
+	{EXYNOS4_GPZ(1),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* AUTO_DFS -> NC */
+};
+
+static unsigned int c1kor_sleep_gpio_table_rev08[][3] = {
+#if defined(CONFIG_MACH_C1_KOR_LGT)
+	{EXYNOS4212_GPM0(7),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* NC -> CAM_SENSOR_CORE_EN */
+#endif
+};
+
+static unsigned int c1kor_sleep_gpio_table_rev09[][3] = {
+#if !defined(CONFIG_MACH_C1_KOR_LGT)
+	{EXYNOS4212_GPM0(0),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* NC -> LED_VDD_EN */
+#endif
+};
+
+static unsigned int c1kor_sleep_gpio_table_rev12[][3] = {
+#if !defined(CONFIG_MACH_C1_KOR_LGT)
+	{EXYNOS4212_GPM0(7),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* NC -> CAM_SENSOR_CORE_EN */
+#endif
+};
+
+struct c1kor_sleep_table {
+	unsigned int (*ptr)[3];
+	int size;
+};
+
+#define GPIO_TABLE(_ptr) \
+	{.ptr = _ptr, \
+	.size = ARRAY_SIZE(_ptr)} \
+
+ #define GPIO_TABLE_NULL \
+	{.ptr = NULL, \
+	.size = 0} \
+
+static struct c1kor_sleep_table c1kor_sleep_table[] = {
+	GPIO_TABLE_NULL,
+	GPIO_TABLE_NULL,
+	GPIO_TABLE(c1kor_sleep_gpio_table),/* Rev0.0(0x2) */
+	GPIO_TABLE_NULL,
+	GPIO_TABLE_NULL,
+	GPIO_TABLE(c1kor_sleep_gpio_table_rev05), /* Rev0.1(0x5) */
+	GPIO_TABLE(c1kor_sleep_gpio_table_rev06), /* KT Rev0.0(0x6), LGT Rev0.5(0x6) */
+	GPIO_TABLE(c1kor_sleep_gpio_table_rev07), /* Rev0.2(0x7), LGT Rev0.6(0x7) */
+	GPIO_TABLE(c1kor_sleep_gpio_table_rev08), /* kT Rev0.1(0x8), LGT Rev0.7(0x8) */
+	GPIO_TABLE(c1kor_sleep_gpio_table_rev09), /* Rev0.4(0x9) */
+	GPIO_TABLE_NULL, /* KT Rev0.3(0xA) */
+	GPIO_TABLE_NULL, /* Rev0.5(0xB) */
+	GPIO_TABLE(c1kor_sleep_gpio_table_rev12), /* Rev0.6(0xC) */
+	GPIO_TABLE_NULL, /* KT Rev0.4(0xD) */
+};
+#endif /* C1_KOR */
+#endif /* CONFIG_MIDAS_COMMON */
+
+#if	defined(CONFIG_MACH_S2PLUS)
+/*
+ * S2Plus GPIO Sleep Table
+ */
+static unsigned int s2plus_sleep_gpio_table[][3] = {
+	{EXYNOS4_GPA0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+	{EXYNOS4_GPA0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+
+	{EXYNOS4_GPA1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPB(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPB(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPB(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPB(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPC0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPC0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPC0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPC0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPC0(4), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPC1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPC1(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* FM_RST */
+	{EXYNOS4_GPC1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPC1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPC1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPD0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPD0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPD0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPD0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPD1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPD1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPD1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPD1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPF0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF1(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF1(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF3(4), S3C_GPIO_SLP_OUT1,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK0(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_CLK */
+	{EXYNOS4_GPK0(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_CMD */
+	{EXYNOS4_GPK0(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* eMMC_EN */
+	{EXYNOS4_GPK0(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(0) */
+	{EXYNOS4_GPK0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(1) */
+	{EXYNOS4_GPK0(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(2) */
+	{EXYNOS4_GPK0(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(3) */
+	{EXYNOS4_GPK1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK1(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(4) */
+	{EXYNOS4_GPK1(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(5) */
+	{EXYNOS4_GPK1(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(6) */
+	{EXYNOS4_GPK1(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(7) */
+	{EXYNOS4_GPK2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPK3(0), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPK3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPL0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPL0(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL0(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL0(3), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPL0(6), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPL1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPL2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL2(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL2(6), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPY0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPY0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPY0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPY1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY2(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* TF_EN */
+	{EXYNOS4_GPY2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPY3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY3(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPY4(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPY5(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPY6(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPZ(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPZ(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPZ(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPZ(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPZ(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPZ(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPZ(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	/* Exynos4212 specific gpio */
+	{EXYNOS4212_GPJ0(0),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4212_GPJ0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPJ0(2),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	{EXYNOS4212_GPJ0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPJ0(4),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4212_GPJ0(5),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	{EXYNOS4212_GPJ0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPJ0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPJ1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPJ1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPJ1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPJ1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPJ1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPM0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(6),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	{EXYNOS4212_GPM0(7),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4212_GPM1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4212_GPM1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4212_GPM1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4212_GPM1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4212_GPM1(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPM2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4212_GPM2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4212_GPM2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPM2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPM3(0),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4212_GPM3(1),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4212_GPM3(2),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* NC */
+	/* GPM3(3) M0, CP_RESET_REQ hold high */
+	{EXYNOS4212_GPM3(3),  S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE},
+	{EXYNOS4212_GPM3(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM3(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* ISP_TXD */
+	{EXYNOS4212_GPM3(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM3(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* ISP_RXD */
+
+	{EXYNOS4212_GPM4(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM4(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM4(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* VT_CAM_SCL */
+	{EXYNOS4212_GPM4(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* VT_CAM_SDA */
+	{EXYNOS4212_GPM4(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM4(5),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	{EXYNOS4212_GPM4(6),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	{EXYNOS4212_GPM4(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPV0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPV1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPV2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPV3(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPV4(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV4(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+}; /* S2Plus_sleep_gpio_table */
+#endif
+
+/*
+ * M0CTC GPIO Sleep Table
+ */
+static unsigned int m0ctc_sleep_gpio_table[][3] = {
+	{EXYNOS4_GPA0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+	{EXYNOS4_GPA0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPA1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPB(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPB(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+	{EXYNOS4_GPB(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPB(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPC0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPC0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPC0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPC0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPC0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPC1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPC1(1), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE}, /* FM_RST */
+	{EXYNOS4_GPC1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPC1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPC1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPD0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPD0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPD0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPD0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPD1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPD1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPD1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPD1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPF0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPF0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPF0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPF0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPF0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPF0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPF1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPF1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPF1(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPF1(7), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE}, /* NC */
+
+	{EXYNOS4_GPF2(0), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPF2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF2(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPF2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /*L_I2C_SCL*/
+	{EXYNOS4_GPF2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /*L_I2C_SDA*/
+
+	{EXYNOS4_GPF3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPF3(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*BUCK2_SEL*/
+	{EXYNOS4_GPF3(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*BUCK3_SEL*/
+	{EXYNOS4_GPF3(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*BUCK4_SEL*/
+	{EXYNOS4_GPF3(4), S3C_GPIO_SLP_OUT1,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPK0(0), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE}, /*NAND_CLK*/
+	{EXYNOS4_GPK0(1), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE}, /*NAND_CMD*/
+	{EXYNOS4_GPK0(2), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE}, /*eMMC_EN*/
+	{EXYNOS4_GPK0(3), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE}, /*NAND_D(0)*/
+	{EXYNOS4_GPK0(4), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE}, /*NAND_D(1)*/
+	{EXYNOS4_GPK0(5), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE}, /*NAND_D(2)*/
+	{EXYNOS4_GPK0(6), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE}, /*NAND_D(3)*/
+
+	{EXYNOS4_GPK1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK1(3), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE}, /*NAND_D(4)*/
+	{EXYNOS4_GPK1(4), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE}, /*NAND_D(5)*/
+	{EXYNOS4_GPK1(5), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE}, /*NAND_D(6)*/
+	{EXYNOS4_GPK1(6), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE}, /*NAND_D(7)*/
+
+	{EXYNOS4_GPK2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPK3(0), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPK3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPL0(0), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL0(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL0(4), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE}, /* HDMI_EN */
+/*	{EXYNOS4_GPL0(5), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE}, */
+	{EXYNOS4_GPL0(6), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+/*	{EXYNOS4_GPL0(7), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE}, */
+
+	{EXYNOS4_GPL1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+/*	{EXYNOS4_GPL1(2), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE}, */
+
+	{EXYNOS4_GPL2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPL2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPL2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL2(4), S3C_GPIO_SLP_OUT1,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL2(6), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPY0(0), S3C_GPIO_SLP_OUT1,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY0(4), S3C_GPIO_SLP_OUT1,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY0(5), S3C_GPIO_SLP_OUT1,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPY1(0), S3C_GPIO_SLP_OUT1,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY1(1), S3C_GPIO_SLP_OUT1,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+	{EXYNOS4_GPY1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPY2(0), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE}, /* TF_EN */
+	{EXYNOS4_GPY2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPY3(0), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(1), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(2), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(3), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(4), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(5), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(6), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(7), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPY4(0), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(1), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(2), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(3), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(4), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY4(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY4(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPY5(0), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY5(1), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY5(2), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY5(3), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY5(4), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY5(5), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY5(6), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY5(7), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPY6(0), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY6(1), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY6(2), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY6(3), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY6(4), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY6(5), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY6(6), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY6(7), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPZ(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPZ(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPZ(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPZ(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPZ(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPZ(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPZ(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	/* Exynos4212 specific gpio */
+	{EXYNOS4212_GPJ0(0), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4212_GPJ0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPJ0(2), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4212_GPJ0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPJ0(4), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4212_GPJ0(5),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	{EXYNOS4212_GPJ0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPJ0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPJ1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPJ1(1), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},/*TCH_EN*/
+	{EXYNOS4212_GPJ1(2), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},/*TCH_SET*/
+	{EXYNOS4212_GPJ1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPJ1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPM0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPM1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4212_GPM1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4212_GPM1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4212_GPM1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4212_GPM1(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPM2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4212_GPM2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4212_GPM2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPM2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPM3(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*PMIC_DVS1*/
+	{EXYNOS4212_GPM3(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*PMIC_DVS2*/
+	{EXYNOS4212_GPM3(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*PMIC_DVS3*/
+	{EXYNOS4212_GPM3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPM3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM3(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPM4(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM4(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM4(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},/*VTC_SCL*/
+	{EXYNOS4212_GPM4(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},/*VTC_SDA*/
+	{EXYNOS4212_GPM4(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM4(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM4(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM4(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPV0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPV1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPV2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPV3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPV4(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV4(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+}; /* m0ctc_sleep_gpio_table */
+
+static void config_sleep_gpio_table(int array_size,
+				    unsigned int (*gpio_table)[3])
+{
+	u32 i, gpio;
+
+	for (i = 0; i < array_size; i++) {
+		gpio = gpio_table[i][0];
+		s3c_gpio_slp_cfgpin(gpio, gpio_table[i][1]);
+		s3c_gpio_slp_setpull_updown(gpio, gpio_table[i][2]);
+	}
+}
+
+#ifdef CONFIG_MIDAS_COMMON
+void m0_config_sleep_gpio_table(void)
+{
+	int i;
+	int index = min(ARRAY_SIZE(m0_sleep_table), system_rev + 1);
+
+	for (i = 0; i < index; i++) {
+		if (m0_sleep_table[i].ptr == NULL)
+			continue;
+
+		config_sleep_gpio_table(m0_sleep_table[i].size,
+				m0_sleep_table[i].ptr);
+	}
+}
+
+#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW)
+void c1_config_sleep_gpio_table(void)
+{
+	int i;
+	int index = min(ARRAY_SIZE(c1_sleep_table), system_rev + 1);
+
+	for (i = 0; i < index; i++) {
+		if (c1_sleep_table[i].ptr == NULL)
+			continue;
+
+		config_sleep_gpio_table(c1_sleep_table[i].size,
+				c1_sleep_table[i].ptr);
+	}
+}
+#endif
+
+#if defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT) || \
+	defined(CONFIG_MACH_C1_KOR_LGT)
+void c1kor_config_sleep_gpio_table(void)
+{
+	int i;
+	int index = min(ARRAY_SIZE(c1kor_sleep_table), system_rev + 1);
+
+	for (i = 0; i < index; i++) {
+		if (c1kor_sleep_table[i].ptr == NULL)
+			continue;
+
+		config_sleep_gpio_table(c1kor_sleep_table[i].size,
+				c1kor_sleep_table[i].ptr);
+	}
+}
+#endif
+#endif
+
+/* To save power consumption, gpio pin set before enterling sleep */
+void midas_config_sleep_gpio_table(void)
+{
+#ifdef CONFIG_MIDAS_COMMON
+#if defined(CONFIG_MACH_S2PLUS)
+	config_sleep_gpio_table(ARRAY_SIZE(s2plus_sleep_gpio_table),
+			s2plus_sleep_gpio_table);
+#elif defined(CONFIG_MACH_C1CTC) || defined(CONFIG_MACH_M0_CTC) || \
+	defined(CONFIG_MACH_M0_GRANDECTC)
+	config_sleep_gpio_table(ARRAY_SIZE(m0ctc_sleep_gpio_table),
+			m0ctc_sleep_gpio_table);
+#elif defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT) || \
+	defined(CONFIG_MACH_C1_KOR_LGT)
+	c1kor_config_sleep_gpio_table();
+#elif defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW)
+	c1_config_sleep_gpio_table();
+#else
+	m0_config_sleep_gpio_table();
+#endif
+#else
+	config_sleep_gpio_table(ARRAY_SIZE(exynos4_sleep_gpio_table_common),
+			exynos4_sleep_gpio_table_common);
+
+	if (!soc_is_exynos4210()) {
+		if (exynos4_is_c2c_use()) {
+			config_sleep_gpio_table(ARRAY_SIZE(exynos4212_sleep_gpio_table_c2c),
+				exynos4212_sleep_gpio_table_c2c);
+		} else {
+			config_sleep_gpio_table(ARRAY_SIZE(exynos4212_sleep_gpio_table),
+				exynos4212_sleep_gpio_table);
+		}
+	} else {
+		config_sleep_gpio_table(ARRAY_SIZE(exynos4210_sleep_gpio_table),
+			exynos4210_sleep_gpio_table);
+	}
+#endif
+}
+
+/* Intialize gpio set in midas board */
+void midas_config_gpio_table(void)
+{
+	u32 i, gpio;
+
+	printk(KERN_DEBUG "%s\n", __func__);
+
+#ifdef CONFIG_MIDAS_COMMON
+	for (i = 0; i < ARRAY_SIZE(m0_init_gpios); i++) {
+		gpio = m0_init_gpios[i].num;
+		if (gpio <= EXYNOS4212_GPV4(1)) {
+			s3c_gpio_cfgpin(gpio, m0_init_gpios[i].cfg);
+			s3c_gpio_setpull(gpio, m0_init_gpios[i].pud);
+
+			if (m0_init_gpios[i].val != S3C_GPIO_SETPIN_NONE)
+				gpio_set_value(gpio, m0_init_gpios[i].val);
+
+			s5p_gpio_set_drvstr(gpio, m0_init_gpios[i].drv);
+		}
+	}
+#else
+	for (i = 0; i < ARRAY_SIZE(midas_init_gpios); i++) {
+		gpio = midas_init_gpios[i].num;
+		if (!soc_is_exynos4210()) {
+			if (gpio <= EXYNOS4212_GPV4(1)) {
+				s3c_gpio_cfgpin(gpio, midas_init_gpios[i].cfg);
+				s3c_gpio_setpull(gpio, midas_init_gpios[i].pud);
+
+				if (midas_init_gpios[i].val != S3C_GPIO_SETPIN_NONE)
+					gpio_set_value(gpio, midas_init_gpios[i].val);
+
+				s5p_gpio_set_drvstr(gpio, midas_init_gpios[i].drv);
+			}
+		} else {
+			if (gpio <= EXYNOS4210_GPJ1(4)) {
+				s3c_gpio_cfgpin(gpio, midas_init_gpios[i].cfg);
+				s3c_gpio_setpull(gpio, midas_init_gpios[i].pud);
+
+				if (midas_init_gpios[i].val != S3C_GPIO_SETPIN_NONE)
+					gpio_set_value(gpio, midas_init_gpios[i].val);
+
+				s5p_gpio_set_drvstr(gpio, midas_init_gpios[i].drv);
+			}
+		}
+	}
+#endif
+}
diff --git a/arch/arm/mach-exynos/midas-gps.c b/arch/arm/mach-exynos/midas-gps.c
new file mode 100644
index 0000000..ebfc1bd
--- /dev/null
+++ b/arch/arm/mach-exynos/midas-gps.c
@@ -0,0 +1,50 @@
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+//#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <mach/gpio.h>
+#include <plat/gpio-cfg.h>
+
+extern struct class *sec_class;
+static struct device *gps_dev;
+
+static int __init midas_gps_init(void)
+{
+	BUG_ON(!sec_class);
+	gps_dev = device_create(sec_class, NULL, 0, NULL, "gps");
+	BUG_ON(!gps_dev);
+
+	s3c_gpio_cfgpin(GPIO_GPS_RXD, S3C_GPIO_SFN(GPIO_GPS_RXD_AF));
+	s3c_gpio_setpull(GPIO_GPS_RXD, S3C_GPIO_PULL_UP);
+	s3c_gpio_cfgpin(GPIO_GPS_TXD, S3C_GPIO_SFN(GPIO_GPS_TXD_AF));
+	s3c_gpio_setpull(GPIO_GPS_TXD, S3C_GPIO_PULL_NONE);
+	s3c_gpio_cfgpin(GPIO_GPS_CTS, S3C_GPIO_SFN(GPIO_GPS_CTS_AF));
+	s3c_gpio_setpull(GPIO_GPS_CTS, S3C_GPIO_PULL_NONE);
+	s3c_gpio_cfgpin(GPIO_GPS_RTS, S3C_GPIO_SFN(GPIO_GPS_RTS_AF));
+	s3c_gpio_setpull(GPIO_GPS_RTS, S3C_GPIO_PULL_NONE);
+
+	if (gpio_request(GPIO_GPS_nRST, "GPS_nRST"))
+		WARN(1, "fail to request gpio (GPS_nRST)\n");
+
+	s3c_gpio_setpull(GPIO_GPS_nRST, S3C_GPIO_PULL_UP);
+	s3c_gpio_cfgpin(GPIO_GPS_nRST, S3C_GPIO_OUTPUT);
+	gpio_direction_output(GPIO_GPS_nRST, 1);
+
+	if (gpio_request(GPIO_GPS_PWR_EN, "GPS_PWR_EN"))
+		WARN(1, "fail to request gpio (GPS_PWR_EN)\n");
+
+	s3c_gpio_setpull(GPIO_GPS_PWR_EN, S3C_GPIO_PULL_NONE);
+	s3c_gpio_cfgpin(GPIO_GPS_PWR_EN, S3C_GPIO_OUTPUT);
+	gpio_direction_output(GPIO_GPS_PWR_EN, 0);
+
+	gpio_export(GPIO_GPS_nRST, 1);
+	gpio_export(GPIO_GPS_PWR_EN, 1);
+
+	gpio_export_link(gps_dev, "GPS_nRST", GPIO_GPS_nRST);
+	gpio_export_link(gps_dev, "GPS_PWR_EN", GPIO_GPS_PWR_EN);
+
+	return 0;
+}
+
+device_initcall(midas_gps_init);
diff --git a/arch/arm/mach-exynos/midas-lcd.c b/arch/arm/mach-exynos/midas-lcd.c
new file mode 100644
index 0000000..549a742
--- /dev/null
+++ b/arch/arm/mach-exynos/midas-lcd.c
@@ -0,0 +1,810 @@
+/*
+ * midas-lcd.c - lcd driver of MIDAS Project
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/delay.h>
+#include <linux/regulator/consumer.h>
+#include <linux/lcd.h>
+
+#include <plat/devs.h>
+#include <plat/fb-s5p.h>
+#include <plat/gpio-cfg.h>
+#include <plat/pd.h>
+#include <plat/map-base.h>
+#include <plat/map-s5p.h>
+
+#ifdef CONFIG_FB_S5P_LD9040
+#include <linux/ld9040.h>
+#endif
+
+#ifdef CONFIG_FB_S5P_MIPI_DSIM
+#include <mach/mipi_ddi.h>
+#include <mach/dsim.h>
+#endif
+#include <../../../drivers/video/samsung/s3cfb.h>
+
+#ifdef CONFIG_FB_S5P_MDNIE
+#include <linux/mdnie.h>
+#endif
+
+struct s3c_platform_fb fb_platform_data;
+unsigned int lcdtype;
+static int __init lcdtype_setup(char *str)
+{
+	get_option(&str, &lcdtype);
+	return 1;
+}
+__setup("lcdtype=", lcdtype_setup);
+
+
+#ifdef CONFIG_FB_S5P
+#ifdef CONFIG_FB_S5P_LD9040
+static int lcd_cfg_gpio(void)
+{
+	int i, f3_end = 4;
+
+	for (i = 0; i < 8; i++) {
+		/* set GPF0,1,2[0:7] for RGB Interface and Data line (32bit) */
+		s3c_gpio_cfgpin(EXYNOS4_GPF0(i), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(EXYNOS4_GPF0(i), S3C_GPIO_PULL_NONE);
+	}
+	for (i = 0; i < 8; i++) {
+		s3c_gpio_cfgpin(EXYNOS4_GPF1(i), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(EXYNOS4_GPF1(i), S3C_GPIO_PULL_NONE);
+	}
+
+	for (i = 0; i < 8; i++) {
+		s3c_gpio_cfgpin(EXYNOS4_GPF2(i), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(EXYNOS4_GPF2(i), S3C_GPIO_PULL_NONE);
+	}
+
+	for (i = 0; i < f3_end; i++) {
+		s3c_gpio_cfgpin(EXYNOS4_GPF3(i), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(EXYNOS4_GPF3(i), S3C_GPIO_PULL_NONE);
+	}
+
+	/* MLCD_RST */
+	s3c_gpio_cfgpin(EXYNOS4_GPY4(5), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPY4(5), S3C_GPIO_PULL_NONE);
+
+	/* LCD_nCS */
+	s3c_gpio_cfgpin(EXYNOS4_GPY4(3), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPY4(3), S3C_GPIO_PULL_NONE);
+
+	/* LCD_SCLK */
+	s3c_gpio_cfgpin(EXYNOS4_GPY3(1), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPY3(1), S3C_GPIO_PULL_NONE);
+
+	/* LCD_SDI */
+	s3c_gpio_cfgpin(EXYNOS4_GPY3(3), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPY3(3), S3C_GPIO_PULL_NONE);
+
+	return 0;
+}
+
+static int lcd_power_on(struct lcd_device *ld, int enable)
+{
+	struct regulator *regulator;
+
+	if (ld == NULL) {
+		printk(KERN_ERR "lcd device object is NULL.\n");
+		return 0;
+	}
+
+	if (enable) {
+		regulator = regulator_get(NULL, "vlcd_3.0v");
+		if (IS_ERR(regulator))
+			return 0;
+
+		regulator_enable(regulator);
+		regulator_put(regulator);
+	} else {
+		regulator = regulator_get(NULL, "vlcd_3.0v");
+
+	if (IS_ERR(regulator))
+		return 0;
+
+	if (regulator_is_enabled(regulator))
+		regulator_force_disable(regulator);
+
+		regulator_put(regulator);
+	}
+
+	return 1;
+}
+
+static int reset_lcd(struct lcd_device *ld)
+{
+	int reset_gpio = -1;
+	int err;
+
+	reset_gpio = EXYNOS4_GPY4(5);
+
+	err = gpio_request(reset_gpio, "MLCD_RST");
+	if (err) {
+		printk(KERN_ERR "failed to request MLCD_RST for "
+			"lcd reset control\n");
+		return err;
+	}
+
+	gpio_request(reset_gpio, "MLCD_RST");
+
+	mdelay(10);
+	gpio_direction_output(reset_gpio, 0);
+	mdelay(10);
+	gpio_direction_output(reset_gpio, 1);
+
+	gpio_free(reset_gpio);
+
+	return 1;
+}
+
+static int lcd_gpio_cfg_earlysuspend(struct lcd_device *ld)
+{
+	int reset_gpio = -1;
+	int err;
+
+	reset_gpio = EXYNOS4_GPY4(5);
+
+	err = gpio_request(reset_gpio, "MLCD_RST");
+	if (err) {
+		printk(KERN_ERR "failed to request MLCD_RST for "
+			"lcd reset control\n");
+		return err;
+	}
+
+	mdelay(10);
+	gpio_direction_output(reset_gpio, 0);
+
+	gpio_free(reset_gpio);
+
+	return 0;
+}
+
+static int lcd_gpio_cfg_lateresume(struct lcd_device *ld)
+{
+	/* MLCD_RST */
+	s3c_gpio_cfgpin(EXYNOS4_GPY4(5), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPY4(5), S3C_GPIO_PULL_NONE);
+
+	/* LCD_nCS */
+	s3c_gpio_cfgpin(EXYNOS4_GPY4(3), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPY4(3), S3C_GPIO_PULL_NONE);
+
+	/* LCD_SCLK */
+	s3c_gpio_cfgpin(EXYNOS4_GPY3(1), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPY3(1), S3C_GPIO_PULL_NONE);
+
+	/* LCD_SDI */
+	s3c_gpio_cfgpin(EXYNOS4_GPY3(3), S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(EXYNOS4_GPY3(3), S3C_GPIO_PULL_NONE);
+
+	return 0;
+}
+
+static struct s3cfb_lcd ld9040_info = {
+	.width = 480,
+	.height = 800,
+	.p_width = 56,
+	.p_height = 93,
+	.bpp = 24,
+
+	.freq = 60,
+	.timing = {
+		.h_fp = 16,
+		.h_bp = 14,
+		.h_sw = 2,
+		.v_fp = 10,
+		.v_fpe = 1,
+		.v_bp = 4,
+		.v_bpe = 1,
+		.v_sw = 2,
+	},
+	.polarity = {
+		.rise_vclk = 1,
+		.inv_hsync = 1,
+		.inv_vsync = 1,
+		.inv_vden = 1,
+	},
+};
+
+struct ld9040_panel_data s2plus_panel_data;
+static struct lcd_platform_data ld9040_platform_data = {
+	.reset = reset_lcd,
+	.power_on = lcd_power_on,
+	.gpio_cfg_earlysuspend = lcd_gpio_cfg_earlysuspend,
+	.gpio_cfg_lateresume = lcd_gpio_cfg_lateresume,
+		 /* it indicates whether lcd panel is enabled from u-boot. */
+#if defined(CONFIG_MACH_S2PLUS)
+	.lcd_enabled = 1,
+#else
+	.lcd_enabled = 0,
+#endif
+	.reset_delay = 20,  /* 20ms */
+	.power_on_delay = 20,	 /* 20ms */
+	.power_off_delay = 200, /* 200ms */
+	.sleep_in_delay = 160,
+	.pdata = &s2plus_panel_data,
+};
+
+#define LCD_BUS_NUM	3
+#define DISPLAY_CS	EXYNOS4_GPY4(3)
+static struct spi_board_info spi_board_info[] __initdata = {
+	{
+		.max_speed_hz = 1200000,
+		.bus_num = LCD_BUS_NUM,
+		.chip_select = 0,
+		.mode = SPI_MODE_3,
+		.controller_data = (void *)DISPLAY_CS,
+	},
+};
+
+#define DISPLAY_CLK	EXYNOS4_GPY3(1)
+#define DISPLAY_SI	EXYNOS4_GPY3(3)
+static struct spi_gpio_platform_data lcd_spi_gpio_data = {
+	.sck = DISPLAY_CLK,
+	.mosi = DISPLAY_SI,
+	.miso = SPI_GPIO_NO_MISO,
+	.num_chipselect = 1,
+};
+
+static struct platform_device ld9040_spi_gpio = {
+	.name = "spi_gpio",
+	.id = LCD_BUS_NUM,
+	.dev = {
+		.parent = &s3c_device_fb.dev,
+		.platform_data = &lcd_spi_gpio_data,
+	},
+};
+
+/* reading with 3-WIRE SPI with GPIO */
+static inline void setcs(u8 is_on)
+{
+	gpio_set_value(DISPLAY_CS, is_on);
+}
+
+static inline void setsck(u8 is_on)
+{
+	gpio_set_value(DISPLAY_CLK, is_on);
+}
+
+static inline void setmosi(u8 is_on)
+{
+	gpio_set_value(DISPLAY_SI, is_on);
+}
+
+static inline unsigned int getmiso(void)
+{
+	return !!gpio_get_value(DISPLAY_SI);
+}
+
+static inline void setmosi2miso(u8 is_on)
+{
+	if (is_on)
+		s3c_gpio_cfgpin(DISPLAY_SI, S3C_GPIO_INPUT);
+	else
+		s3c_gpio_cfgpin(DISPLAY_SI, S3C_GPIO_OUTPUT);
+}
+
+struct spi_ops ops = {
+	.setcs = setcs,
+	.setsck = setsck,
+	.setmosi = setmosi,
+	.setmosi2miso = setmosi2miso,
+	.getmiso = getmiso,
+};
+
+void __init ld9040_fb_init(void)
+{
+	struct ld9040_panel_data *pdata;
+
+	strcpy(spi_board_info[0].modalias, "ld9040");
+	spi_board_info[0].platform_data = (void *)&ld9040_platform_data;
+
+	pdata = ld9040_platform_data.pdata;
+	pdata->ops = &ops;
+
+	spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
+
+	if (!ld9040_platform_data.lcd_enabled)
+		lcd_cfg_gpio();
+	/*s3cfb_set_platdata(&fb_platform_data);*/
+}
+#endif
+
+#if defined(CONFIG_FB_S5P_S6C1372)
+int s6c1372_panel_gpio_init(void)
+{
+	int i, f3_end = 4;
+
+	for (i = 0; i < 8; i++) {
+		/* set GPF0,1,2[0:7] for RGB Interface and Data line (32bit) */
+		s3c_gpio_cfgpin(EXYNOS4_GPF0(i), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(EXYNOS4_GPF0(i), S3C_GPIO_PULL_NONE);
+	}
+
+	for (i = 0; i < 8; i++) {
+		s3c_gpio_cfgpin(EXYNOS4_GPF1(i), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(EXYNOS4_GPF1(i), S3C_GPIO_PULL_NONE);
+	}
+
+	for (i = 0; i < 8; i++) {
+		s3c_gpio_cfgpin(EXYNOS4_GPF2(i), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(EXYNOS4_GPF2(i), S3C_GPIO_PULL_NONE);
+	}
+
+	for (i = 0; i < f3_end; i++) {
+		s3c_gpio_cfgpin(EXYNOS4_GPF3(i), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(EXYNOS4_GPF3(i), S3C_GPIO_PULL_NONE);
+	}
+
+	return 0;
+}
+
+static struct s3cfb_lcd s6c1372 = {
+	.width = 1280,
+	.height = 800,
+	.p_width = 217,
+	.p_height = 135,
+	.bpp = 24,
+
+	.freq = 60,
+	.timing = {
+		.h_fp = 18,
+		.h_bp = 36,
+		.h_sw = 16,
+		.v_fp = 4,
+		.v_fpe = 1,
+		.v_bp = 16,
+		.v_bpe = 1,
+		.v_sw = 3,
+	},
+
+	.polarity = {
+		.rise_vclk = 1,
+		.inv_hsync = 1,
+		.inv_vsync = 1,
+		.inv_vden = 0,
+	},
+};
+
+static int lcd_power_on(struct lcd_device *ld, int enable)
+{
+	if (enable) {
+		/* LVDS_N_SHDN to high*/
+		mdelay(1);
+		gpio_set_value(GPIO_LVDS_NSHDN, GPIO_LEVEL_HIGH);
+		msleep(300);
+
+		gpio_set_value(GPIO_LED_BACKLIGHT_RESET, GPIO_LEVEL_HIGH);
+		mdelay(2);
+	} else {
+		gpio_set_value(GPIO_LED_BACKLIGHT_RESET, GPIO_LEVEL_LOW);
+		msleep(200);
+
+		/* LVDS_nSHDN low*/
+		gpio_set_value(GPIO_LVDS_NSHDN, GPIO_LEVEL_LOW);
+		msleep(40);
+}
+
+	return 0;
+}
+
+static struct lcd_platform_data s6c1372_platform_data = {
+	.power_on	= lcd_power_on,
+};
+
+struct platform_device lcd_s6c1372 = {
+	.name   = "s6c1372",
+	.id	= -1,
+	.dev.platform_data = &s6c1372_platform_data,
+};
+
+#endif
+
+#ifdef CONFIG_FB_S5P_LMS501KF03
+static struct s3c_platform_fb lms501kf03_data __initdata = {
+	.hw_ver = 0x70,
+	.clk_name = "sclk_lcd",
+	.nr_wins = 5,
+	.default_win = CONFIG_FB_S5P_DEFAULT_WINDOW,
+	.swap = FB_SWAP_HWORD | FB_SWAP_WORD,
+};
+
+#define		LCD_BUS_NUM	3
+#define		DISPLAY_CS	EXYNOS4_GPB(5)
+#define		DISPLAY_CLK	EXYNOS4_GPB(4)
+#define		DISPLAY_SI	EXYNOS4_GPB(7)
+
+static struct spi_board_info spi_board_info[] __initdata = {
+	{
+		.modalias	 = "lms501kf03",
+		.platform_data  = NULL,
+		.max_speed_hz	 = 1200000,
+		.bus_num	 = LCD_BUS_NUM,
+		.chip_select	 = 0,
+		.mode		 = SPI_MODE_3,
+		.controller_data = (void *)DISPLAY_CS,
+	}
+};
+
+static struct spi_gpio_platform_data lms501kf03_spi_gpio_data = {
+	.sck	 = DISPLAY_CLK,
+	.mosi	 = DISPLAY_SI,
+	.miso	 = -1,
+	.num_chipselect = 1,
+};
+
+static struct platform_device s3c_device_spi_gpio = {
+	.name	 = "spi_gpio",
+	.id = LCD_BUS_NUM,
+	.dev	 = {
+		.parent	 = &s3c_device_fb.dev,
+		.platform_data  = &lms501kf03_spi_gpio_data,
+	},
+};
+#endif
+
+#ifdef CONFIG_FB_S5P_MIPI_DSIM
+#ifdef CONFIG_FB_S5P_S6E8AA0
+/* for Geminus based on MIPI-DSI interface */
+static struct s3cfb_lcd s6e8aa0 = {
+	.name = "s6e8aa0",
+	.width = 720,
+	.height = 1280,
+	.p_width = 60,		/* 59.76 mm */
+	.p_height = 106,	 /* 106.24 mm */
+	.bpp = 24,
+
+	.freq = 60,
+
+	/* minumun value is 0 except for wr_act time. */
+	.cpu_timing = {
+		.cs_setup = 0,
+		.wr_setup = 0,
+		.wr_act = 1,
+		.wr_hold = 0,
+	},
+
+	.timing = {
+		.h_fp = 5,
+		.h_bp = 5,
+		.h_sw = 5,
+		.v_fp = 13,
+		.v_fpe = 1,
+		.v_bp = 1,
+		.v_bpe = 1,
+		.v_sw = 2,
+		.cmd_allow_len = 11,	 /* v_fp=stable_vfp + cmd_allow_len */
+		.stable_vfp = 2,
+	},
+
+	.polarity = {
+		.rise_vclk = 1,
+		.inv_hsync = 0,
+		.inv_vsync = 0,
+		.inv_vden = 0,
+	},
+};
+#endif
+
+#ifdef CONFIG_FB_S5P_S6E39A0
+static struct s3cfb_lcd s6e39a0 = {
+	.name = "s6e8aa0",
+	.width = 540,
+	.height = 960,
+	.p_width = 58,
+	.p_height = 103,
+	.bpp = 24,
+
+	.freq = 60,
+
+	/* minumun value is 0 except for wr_act time. */
+	.cpu_timing = {
+		.cs_setup = 0,
+		.wr_setup = 0,
+		.wr_act = 1,
+		.wr_hold = 0,
+	},
+
+	.timing = {
+		.h_fp = 0x48,
+		.h_bp = 12,
+		.h_sw = 4,
+		.v_fp = 13,
+		.v_fpe = 1,
+		.v_bp = 1,
+		.v_bpe = 1,
+		.v_sw = 2,
+		.cmd_allow_len = 0x4,
+	},
+
+	.polarity = {
+		.rise_vclk = 1,
+		.inv_hsync = 0,
+		.inv_vsync = 0,
+		.inv_vden = 0,
+	},
+};
+#endif
+
+#ifdef CONFIG_FB_S5P_S6D6AA1
+/* for Geminus based on MIPI-DSI interface */
+static struct s3cfb_lcd s6d6aa1 = {
+	.name = "s6d6aa1",
+	.width = 720,
+	.height = 1280,
+	.p_width = 63,		/* 63.2 mm */
+	.p_height = 114,	/* 114.19 mm */
+	.bpp = 24,
+
+	.freq = 60,
+
+	/* minumun value is 0 except for wr_act time. */
+	.cpu_timing = {
+		.cs_setup = 0,
+		.wr_setup = 0,
+		.wr_act = 1,
+		.wr_hold = 0,
+	},
+
+	.timing = {
+		.h_fp = 50,
+		.h_bp = 15,
+		.h_sw = 3,
+		.v_fp = 3,
+		.v_fpe = 1,
+		.v_bp = 2,
+		.v_bpe = 1,
+		.v_sw = 2,
+		.cmd_allow_len = 11,	 /* v_fp=stable_vfp + cmd_allow_len */
+		.stable_vfp = 2,
+	},
+
+	.polarity = {
+		.rise_vclk = 1,
+		.inv_hsync = 0,
+		.inv_vsync = 0,
+		.inv_vden = 0,
+	},
+};
+#endif
+
+static int reset_lcd(void)
+{
+	int err;
+
+	err = gpio_request(GPIO_MLCD_RST, "MLCD_RST");
+	if (err) {
+		printk(KERN_ERR "failed to request GPY4(5) for "
+			"lcd reset control\n");
+		return -EINVAL;
+	}
+
+	gpio_direction_output(GPIO_MLCD_RST, 1);
+	usleep_range(5000, 5000);
+	gpio_set_value(GPIO_MLCD_RST, 0);
+	usleep_range(5000, 5000);
+	gpio_set_value(GPIO_MLCD_RST, 1);
+	usleep_range(5000, 5000);
+	gpio_free(GPIO_MLCD_RST);
+	return 0;
+}
+
+static void lcd_cfg_gpio(void)
+{
+	/* MLCD_RST */
+	s3c_gpio_cfgpin(GPIO_MLCD_RST, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_MLCD_RST, S3C_GPIO_PULL_NONE);
+
+	/* LCD_EN */
+	s3c_gpio_cfgpin(GPIO_LCD_22V_EN_00, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_LCD_22V_EN_00, S3C_GPIO_PULL_NONE);
+
+	return;
+}
+
+static int lcd_power_on(void *ld, int enable)
+{
+	struct regulator *regulator;
+	int err;
+
+	printk(KERN_INFO "%s : enable=%d\n", __func__, enable);
+
+	err = gpio_request(GPIO_MLCD_RST, "MLCD_RST");
+	if (err) {
+		printk(KERN_ERR "failed to request GPY4[5] for "
+			"MLCD_RST control\n");
+		return -EPERM;
+	}
+
+	err = gpio_request(GPIO_LCD_22V_EN_00, "LCD_EN");
+	if (err) {
+		printk(KERN_ERR "failed to request GPM4[4] for "
+			"LCD_2.2V_EN control\n");
+		return -EPERM;
+	}
+
+	if (enable) {
+		gpio_set_value(GPIO_LCD_22V_EN_00, GPIO_LEVEL_HIGH);
+
+		regulator = regulator_get(NULL, "vlcd_3.3v");
+		if (IS_ERR(regulator))
+			goto out;
+		regulator_enable(regulator);
+		regulator_put(regulator);
+	} else {
+		regulator = regulator_get(NULL, "vlcd_3.3v");
+		if (IS_ERR(regulator))
+			goto out;
+		if (regulator_is_enabled(regulator))
+			regulator_force_disable(regulator);
+		regulator_put(regulator);
+		gpio_set_value(GPIO_LCD_22V_EN_00, GPIO_LEVEL_LOW);
+		gpio_set_value(GPIO_MLCD_RST, 0);
+	}
+
+out:
+/* Release GPIO */
+	gpio_free(GPIO_MLCD_RST);
+	gpio_free(GPIO_LCD_22V_EN_00);
+return 0;
+}
+
+static void s5p_dsim_mipi_power_control(int enable)
+{
+	struct regulator *regulator;
+	int power_en = 0;
+
+	if (power_en == 1) {
+		printk(KERN_INFO "%s : enable=%d\n", __func__, enable);
+
+		if (enable) {
+				regulator = regulator_get(NULL, "vmipi_1.0v");
+			if (IS_ERR(regulator))
+				goto out;
+			regulator_enable(regulator);
+			regulator_put(regulator);
+
+			regulator = regulator_get(NULL, "vmipi_1.8v");
+			if (IS_ERR(regulator))
+				goto out;
+			regulator_enable(regulator);
+			regulator_put(regulator);
+		} else {
+			regulator = regulator_get(NULL, "vmipi_1.8v");
+			if (IS_ERR(regulator))
+				goto out;
+			if (regulator_is_enabled(regulator))
+				regulator_disable(regulator);
+			regulator_put(regulator);
+
+			regulator = regulator_get(NULL, "vmipi_1.0v");
+			if (IS_ERR(regulator))
+				goto out;
+			if (regulator_is_enabled(regulator))
+				regulator_disable(regulator);
+			regulator_put(regulator);
+		}
+out:
+	return ;
+	} else {
+		return ;
+	}
+}
+
+void __init mipi_fb_init(void)
+{
+	struct s5p_platform_dsim *dsim_pd = NULL;
+	struct mipi_ddi_platform_data *mipi_ddi_pd = NULL;
+	struct dsim_lcd_config *dsim_lcd_info = NULL;
+
+	/* set platform data */
+
+	/* gpio pad configuration for rgb and spi interface. */
+	lcd_cfg_gpio();
+
+	/*
+	* register lcd panel data.
+	*/
+	printk(KERN_INFO "%s :: fb_platform_data.hw_ver = 0x%x\n",
+		__func__, fb_platform_data.hw_ver);
+
+	fb_platform_data.mipi_is_enabled = 1;
+	fb_platform_data.interface_mode = FIMD_CPU_INTERFACE;
+
+	dsim_pd = (struct s5p_platform_dsim *)
+		s5p_device_dsim.dev.platform_data;
+
+	dsim_pd->platform_rev = 1;
+	dsim_pd->mipi_power = s5p_dsim_mipi_power_control;
+
+	dsim_lcd_info = dsim_pd->dsim_lcd_info;
+
+#if defined(CONFIG_FB_S5P_S6E8AA0)
+	dsim_lcd_info->lcd_panel_info = (void *)&s6e8aa0;
+#endif
+#if defined(CONFIG_FB_S5P_S6D6AA1)
+	dsim_lcd_info->lcd_panel_info = (void *)&s6d6aa1;
+#endif
+
+	/* 500Mbps */
+	dsim_pd->dsim_info->p = 3;
+	dsim_pd->dsim_info->m = 125;
+	dsim_pd->dsim_info->s = 1;
+
+	mipi_ddi_pd = (struct mipi_ddi_platform_data *)
+	dsim_lcd_info->mipi_ddi_pd;
+	mipi_ddi_pd->lcd_reset = reset_lcd;
+	mipi_ddi_pd->lcd_power_on = lcd_power_on;
+
+	platform_device_register(&s5p_device_dsim);
+
+	/*s3cfb_set_platdata(&fb_platform_data);*/
+}
+#endif
+#endif
+
+struct s3c_platform_fb fb_platform_data __initdata = {
+	.hw_ver		= 0x70,
+	.clk_name	= "fimd",
+	.nr_wins	= 5,
+#ifdef CONFIG_FB_S5P_DEFAULT_WINDOW
+	.default_win	= CONFIG_FB_S5P_DEFAULT_WINDOW,
+#else
+	.default_win	= 0,
+#endif
+	.swap		= FB_SWAP_HWORD | FB_SWAP_WORD,
+#if defined(CONFIG_FB_S5P_S6E8AA0)
+	.lcd		= &s6e8aa0
+#endif
+#if defined(CONFIG_FB_S5P_S6E39A0)
+	.lcd		= &s6e39a0
+#endif
+#if defined(CONFIG_FB_S5P_LD9040)
+	.lcd		= &ld9040_info
+#endif
+#if defined(CONFIG_FB_S5P_S6C1372)
+	.lcd		= &s6c1372
+#endif
+#if defined(CONFIG_FB_S5P_S6D6AA1)
+	.lcd		= &s6d6aa1
+#endif
+};
+
+#ifdef CONFIG_FB_S5P_MDNIE
+static struct platform_mdnie_data mdnie_data = {
+	.display_type	= -1,
+#if defined(CONFIG_FB_S5P_S6C1372)
+	.lcd_pd		= &s6c1372_platform_data,
+#endif
+};
+#endif
+
+struct platform_device mdnie_device = {
+		.name		 = "mdnie",
+		.id	 = -1,
+		.dev		 = {
+			.parent = &exynos4_device_pd[PD_LCD0].dev,
+#ifdef CONFIG_FB_S5P_MDNIE
+			.platform_data = &mdnie_data,
+#endif
+	},
+};
diff --git a/arch/arm/mach-exynos/midas-leds.c b/arch/arm/mach-exynos/midas-leds.c
new file mode 100644
index 0000000..2d6e1e2
--- /dev/null
+++ b/arch/arm/mach-exynos/midas-leds.c
@@ -0,0 +1,54 @@
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/i2c-gpio.h>
+#include <linux/leds-lp5521.h>
+
+#include <plat/gpio-cfg.h>
+#include <mach/regs-gpio.h>
+#include <mach/gpio.h>
+#include "midas.h"
+
+#ifdef CONFIG_LEDS_LP5521
+static struct lp5521_led_config lp5521_led_config[] = {
+	{
+		.name = "red",
+		.chan_nr = 0,
+		.led_current = 50,
+		.max_current = 130,
+	}, {
+		.name = "green",
+		.chan_nr = 1,
+		.led_current = 30,
+		.max_current = 130,
+	}, {
+		.name = "blue",
+		.chan_nr = 2,
+		.led_current = 30,
+		.max_current = 130,
+	},
+};
+#define LP5521_CONFIGS (LP5521_PWM_HF | LP5521_PWRSAVE_EN | \
+LP5521_CP_MODE_AUTO | LP5521_R_TO_BATT | \
+LP5521_CLK_INT)
+
+static struct lp5521_platform_data lp5521_pdata = {
+	.led_config = lp5521_led_config,
+	.num_channels = ARRAY_SIZE(lp5521_led_config),
+	.clock_mode = LP5521_CLOCK_INT,
+	.update_config = LP5521_CONFIGS,
+};
+static struct i2c_board_info i2c_devs21_emul[] __initdata = {
+	{
+		I2C_BOARD_INFO("lp5521", 0x32),
+		.platform_data = &lp5521_pdata,
+	},
+};
+
+int __init plat_leds_init(void)
+{
+	i2c_add_devices(21, i2c_devs21_emul, ARRAY_SIZE(i2c_devs21_emul));
+	return 0;
+};
+module_init(plat_leds_init);
+#endif
diff --git a/arch/arm/mach-exynos/midas-mhl.c b/arch/arm/mach-exynos/midas-mhl.c
new file mode 100644
index 0000000..5a97b00
--- /dev/null
+++ b/arch/arm/mach-exynos/midas-mhl.c
@@ -0,0 +1,192 @@
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/i2c-gpio.h>
+#include <linux/irq.h>
+#include <linux/delay.h>
+#include <linux/sii9234.h>
+
+#include <plat/gpio-cfg.h>
+#include <mach/regs-gpio.h>
+#include <mach/gpio.h>
+#include "midas.h"
+
+#ifdef CONFIG_SAMSUNG_MHL
+static void sii9234_cfg_gpio(void)
+{
+	printk(KERN_INFO "%s()\n", __func__);
+
+	/* AP_MHL_SDA */
+	s3c_gpio_cfgpin(GPIO_MHL_SDA_1_8V, S3C_GPIO_SFN(0x0));
+	s3c_gpio_setpull(GPIO_MHL_SDA_1_8V, S3C_GPIO_PULL_NONE);
+
+	/* AP_MHL_SCL */
+	s3c_gpio_cfgpin(GPIO_MHL_SCL_1_8V, S3C_GPIO_SFN(0x1));
+	s3c_gpio_setpull(GPIO_MHL_SCL_1_8V, S3C_GPIO_PULL_NONE);
+
+	/* GPH1(6) XEINT 14 */
+	s3c_gpio_cfgpin(GPIO_MHL_WAKE_UP, S3C_GPIO_INPUT);
+	irq_set_irq_type(MHL_WAKEUP_IRQ, IRQ_TYPE_EDGE_RISING);
+	s3c_gpio_setpull(GPIO_MHL_WAKE_UP, S3C_GPIO_PULL_DOWN);
+
+	gpio_request(GPIO_MHL_INT, "MHL_INT");
+	s5p_register_gpio_interrupt(GPIO_MHL_INT);
+	s3c_gpio_setpull(GPIO_MHL_INT, S3C_GPIO_PULL_DOWN);
+	irq_set_irq_type(MHL_INT_IRQ, IRQ_TYPE_EDGE_RISING);
+	s3c_gpio_cfgpin(GPIO_MHL_INT, GPIO_MHL_INT_AF);
+
+	s3c_gpio_cfgpin(GPIO_HDMI_EN, S3C_GPIO_OUTPUT);	/* HDMI_EN */
+	gpio_set_value(GPIO_HDMI_EN, GPIO_LEVEL_LOW);
+	s3c_gpio_setpull(GPIO_HDMI_EN, S3C_GPIO_PULL_NONE);
+
+	s3c_gpio_cfgpin(GPIO_MHL_RST, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_MHL_RST, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_MHL_RST, GPIO_LEVEL_LOW);
+
+#if !defined(CONFIG_MACH_C1_KOR_LGT) && !defined(CONFIG_SAMSUNG_MHL_9290)
+#if !defined(CONFIG_MACH_P4NOTE)
+	s3c_gpio_cfgpin(GPIO_MHL_SEL, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_MHL_SEL, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_MHL_SEL, GPIO_LEVEL_LOW);
+#endif
+#endif
+}
+
+static void sii9234_power_onoff(bool on)
+{
+	printk(KERN_INFO "%s(%d)\n", __func__, on);
+
+	if (on) {
+		/* To avoid floating state of the HPD pin *
+		 * in the absence of external pull-up     */
+		s3c_gpio_setpull(GPIO_HDMI_HPD, S3C_GPIO_PULL_NONE);
+		gpio_set_value(GPIO_HDMI_EN, GPIO_LEVEL_HIGH);
+
+		s3c_gpio_setpull(GPIO_MHL_SCL_1_8V, S3C_GPIO_PULL_DOWN);
+		s3c_gpio_setpull(GPIO_MHL_SCL_1_8V, S3C_GPIO_PULL_NONE);
+
+		/* sii9234_unmaks_interrupt(); // - need to add */
+		/* VCC_SUB_2.0V is always on */
+	} else {
+		gpio_set_value(GPIO_MHL_RST, GPIO_LEVEL_LOW);
+		usleep_range(10000, 20000);
+		gpio_set_value(GPIO_MHL_RST, GPIO_LEVEL_HIGH);
+
+		/* To avoid floating state of the HPD pin *
+		 * in the absence of external pull-up     */
+		s3c_gpio_setpull(GPIO_HDMI_HPD, S3C_GPIO_PULL_DOWN);
+		gpio_set_value(GPIO_HDMI_EN, GPIO_LEVEL_LOW);
+
+		gpio_set_value(GPIO_MHL_RST, GPIO_LEVEL_LOW);
+	}
+}
+
+static void sii9234_reset(void)
+{
+	printk(KERN_INFO "%s()\n", __func__);
+
+	s3c_gpio_cfgpin(GPIO_MHL_RST, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_MHL_RST, S3C_GPIO_PULL_NONE);
+
+
+	gpio_set_value(GPIO_MHL_RST, GPIO_LEVEL_LOW);
+	usleep_range(10000, 20000);
+	gpio_set_value(GPIO_MHL_RST, GPIO_LEVEL_HIGH);
+}
+
+#ifndef CONFIG_SAMSUNG_USE_11PIN_CONNECTOR
+#ifndef CONFIG_MACH_P4NOTE
+static void mhl_usb_switch_control(bool on)
+{
+	printk(KERN_INFO "%s() [MHL] USB path change : %s\n",
+	       __func__, on ? "MHL" : "USB");
+	if (on == 1) {
+		if (gpio_get_value(GPIO_MHL_SEL))
+			printk(KERN_INFO "[MHL] GPIO_MHL_SEL : already 1\n");
+		else
+			gpio_set_value(GPIO_MHL_SEL, GPIO_LEVEL_HIGH);
+	} else {
+		if (!gpio_get_value(GPIO_MHL_SEL))
+			printk(KERN_INFO "[MHL] GPIO_MHL_SEL : already 0\n");
+		else
+			gpio_set_value(GPIO_MHL_SEL, GPIO_LEVEL_LOW);
+	}
+}
+#endif
+#endif
+
+static struct sii9234_platform_data sii9234_pdata = {
+	.init = sii9234_cfg_gpio,
+#if defined(CONFIG_SAMSUNG_USE_11PIN_CONNECTOR) || \
+		defined(CONFIG_MACH_P4NOTE)
+	.mhl_sel = NULL,
+#else
+	.mhl_sel = mhl_usb_switch_control,
+#endif
+	.hw_onoff = sii9234_power_onoff,
+	.hw_reset = sii9234_reset,
+	.enable_vbus = NULL,
+#if defined(__MHL_NEW_CBUS_MSC_CMD__)
+	.vbus_present = NULL,
+#else
+	.vbus_present = NULL,
+#endif
+
+#ifdef CONFIG_EXTCON
+	.extcon_name = "max77693-muic",
+#endif
+};
+
+static struct i2c_board_info __initdata i2c_devs_sii9234[] = {
+	{
+		I2C_BOARD_INFO("sii9234_mhl_tx", 0x72>>1),
+		.platform_data = &sii9234_pdata,
+	},
+	{
+		I2C_BOARD_INFO("sii9234_tpi", 0x7A>>1),
+		.platform_data = &sii9234_pdata,
+	},
+	{
+		I2C_BOARD_INFO("sii9234_hdmi_rx", 0x92>>1),
+		.platform_data = &sii9234_pdata,
+	},
+	{
+		I2C_BOARD_INFO("sii9234_cbus", 0xC8>>1),
+		.platform_data = &sii9234_pdata,
+	},
+};
+
+static struct i2c_board_info i2c_dev_hdmi_ddc __initdata = {
+	I2C_BOARD_INFO("s5p_ddc", (0x74 >> 1)),
+};
+
+static int __init midas_mhl_init(void)
+{
+	int ret;
+#define I2C_BUS_ID_MHL	15
+	ret = i2c_add_devices(I2C_BUS_ID_MHL, i2c_devs_sii9234,
+			ARRAY_SIZE(i2c_devs_sii9234));
+
+	if (ret < 0) {
+		printk(KERN_ERR "[MHL] adding i2c fail - nodevice\n");
+		return -ENODEV;
+	}
+#if defined(CONFIG_MACH_S2PLUS) || defined(CONFIG_MACH_P4NOTE)
+	sii9234_pdata.ddc_i2c_num = 5;
+#else
+	sii9234_pdata.ddc_i2c_num = (system_rev == 3 ? 16 : 5);
+#endif
+
+#ifdef CONFIG_MACH_SLP_PQ_LTE
+	sii9234_pdata.ddc_i2c_num = 16;
+#endif
+	ret = i2c_add_devices(sii9234_pdata.ddc_i2c_num, &i2c_dev_hdmi_ddc, 1);
+	if (ret < 0) {
+		printk(KERN_ERR "[MHL] adding ddc fail - nodevice\n");
+		return -ENODEV;
+	}
+
+	return 0;
+}
+module_init(midas_mhl_init);
+#endif
diff --git a/arch/arm/mach-exynos/midas-nfc.c b/arch/arm/mach-exynos/midas-nfc.c
new file mode 100644
index 0000000..c9c05f5
--- /dev/null
+++ b/arch/arm/mach-exynos/midas-nfc.c
@@ -0,0 +1,78 @@
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/nfc/pn65n.h>
+
+#include <plat/gpio-cfg.h>
+#include <mach/regs-gpio.h>
+#include <mach/gpio.h>
+#include "midas.h"
+
+/* GPIO_LEVEL_NONE = 2, GPIO_LEVEL_LOW = 0 */
+static unsigned int nfc_gpio_table[][4] = {
+	{GPIO_NFC_IRQ, S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{GPIO_NFC_EN, S3C_GPIO_OUTPUT, 0, S3C_GPIO_PULL_NONE},
+	{GPIO_NFC_FIRMWARE, S3C_GPIO_OUTPUT, 0, S3C_GPIO_PULL_NONE},
+};
+
+static inline void nfc_setup_gpio(void)
+{
+	int array_size = ARRAY_SIZE(nfc_gpio_table);
+	u32 i, gpio;
+	for (i = 0; i < array_size; i++) {
+		gpio = nfc_gpio_table[i][0];
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(nfc_gpio_table[i][1]));
+		s3c_gpio_setpull(gpio, nfc_gpio_table[i][3]);
+		if (nfc_gpio_table[i][2] != 2)
+			gpio_set_value(gpio, nfc_gpio_table[i][2]);
+	}
+}
+
+static struct pn65n_i2c_platform_data pn65n_pdata = {
+	.irq_gpio = GPIO_NFC_IRQ,
+	.ven_gpio = GPIO_NFC_EN,
+	.firm_gpio = GPIO_NFC_FIRMWARE,
+};
+
+static struct i2c_board_info i2c_dev_pn65n __initdata = {
+	I2C_BOARD_INFO("pn65n", 0x2b),
+	.irq = IRQ_EINT(15),
+	.platform_data = &pn65n_pdata,
+};
+
+#ifdef CONFIG_SLP
+/* In SLP Kernel, i2c_bus number is decided at board file. */
+int __init midas_nfc_init(int i2c_bus)
+{
+	nfc_setup_gpio();
+
+	i2c_register_board_info(i2c_bus, &i2c_dev_pn65n, 1);
+
+	return 0;
+}
+#else
+static int __init midas_nfc_init(void)
+{
+	int ret = 0;
+#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) || \
+	defined(CONFIG_MACH_M3)	|| defined(CONFIG_MACH_M0_CTC)
+#define I2C_BUSNUM_PN65N	(system_rev == 3 ? 0 : 5)
+#elif defined(CONFIG_MACH_M0) || \
+	defined(CONFIG_MACH_JENGA) || defined(CONFIG_MACH_S2PLUS)
+#define I2C_BUSNUM_PN65N	(system_rev == 3 ? 12 : 5)
+#else
+#define I2C_BUSNUM_PN65N	12
+#endif
+
+	nfc_setup_gpio();
+
+	ret = i2c_add_devices(I2C_BUSNUM_PN65N, &i2c_dev_pn65n, 1);
+	if (ret < 0) {
+		pr_err("%s, i2c%d adding i2c fail(err=%d)\n",
+			__func__, I2C_BUSNUM_PN65N, ret);
+		return ret;
+	}
+
+	return ret;
+}
+module_init(midas_nfc_init);
+#endif
diff --git a/arch/arm/mach-exynos/midas-power.c b/arch/arm/mach-exynos/midas-power.c
new file mode 100644
index 0000000..78318f2
--- /dev/null
+++ b/arch/arm/mach-exynos/midas-power.c
@@ -0,0 +1,1125 @@
+/*
+ * midas-power.c - Power Management of MIDAS Project
+ *
+ *  Copyright (C) 2011 Samsung Electrnoics
+ *  Chiwoong Byun <woong.byun@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/i2c.h>
+#include <linux/regulator/machine.h>
+#include <plat/gpio-cfg.h>
+#include <mach/gpio-midas.h>
+#include <mach/irqs.h>
+
+#include <linux/mfd/max8997.h>
+#include <linux/mfd/max77686.h>
+#include <linux/mfd/max77693.h>
+
+#if defined(CONFIG_REGULATOR_S5M8767)
+#include <linux/mfd/s5m87xx/s5m-pmic.h>
+#include <linux/mfd/s5m87xx/s5m-core.h>
+#endif
+
+#ifdef CONFIG_REGULATOR_MAX8997
+/* MOTOR */
+#ifdef CONFIG_VIBETONZ
+static void max8997_motor_init(void)
+{
+	gpio_request(GPIO_VIBTONE_EN, "VIBTONE_EN");
+	s3c_gpio_cfgpin(GPIO_VIBTONE_EN, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_VIBTONE_EN, S3C_GPIO_PULL_NONE);
+}
+
+static void max8997_motor_en(bool en)
+{
+	gpio_direction_output(GPIO_VIBTONE_EN, en);
+}
+
+static struct max8997_motor_data max8997_motor = {
+	.max_timeout = 10000,
+	.duty = 44000,
+	.period = 44642,
+	.reg2 = MOTOR_LRA | EXT_PWM | DIVIDER_128,
+	.init_hw = max8997_motor_init,
+	.motor_en = max8997_motor_en,
+	.pwm_id = 1,
+};
+#endif
+
+/* max8997 */
+static struct regulator_consumer_supply ldo1_supply[] = {
+	REGULATOR_SUPPLY("vmipi_1.8v", NULL),
+	REGULATOR_SUPPLY("VDD18", "s5p-mipi-dsim"),
+};
+
+#ifdef CONFIG_SND_SOC_WM8994
+static struct regulator_consumer_supply ldo6_supply[] = {
+	REGULATOR_SUPPLY("AVDD2", NULL),
+	REGULATOR_SUPPLY("CPVDD", NULL),
+	REGULATOR_SUPPLY("DBVDD1", NULL),
+	REGULATOR_SUPPLY("DBVDD2", NULL),
+	REGULATOR_SUPPLY("DBVDD3", NULL),
+};
+#endif
+
+static struct regulator_consumer_supply ldo7_supply[] = {
+	REGULATOR_SUPPLY("cam_sensor_core_1.2v", NULL),
+};
+
+static struct regulator_consumer_supply ldo8_supply[] = {
+	REGULATOR_SUPPLY("votg_3.0v", NULL),
+};
+
+static struct regulator_consumer_supply ldo11_supply[] = {
+	REGULATOR_SUPPLY("vmipi_1.0v", NULL),
+	REGULATOR_SUPPLY("VDD10", "s5p-mipi-dsim"),
+};
+
+static struct regulator_consumer_supply ldo13_supply[] = {
+	REGULATOR_SUPPLY("vlcd_3.3v", NULL),
+	REGULATOR_SUPPLY("VCI", "s6e8aa0"),
+};
+
+static struct regulator_consumer_supply ldo14_supply[] = {
+	REGULATOR_SUPPLY("vcc_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo15_supply[] = {
+	REGULATOR_SUPPLY("vlcd_2.2v", NULL),
+	REGULATOR_SUPPLY("VDD3", "s6e8aa0"),
+};
+
+static struct regulator_consumer_supply ldo12_supply[] = {
+	REGULATOR_SUPPLY("vt_cam_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo16_supply[] = {
+	REGULATOR_SUPPLY("cam_isp_sensor_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo17_supply[] = {
+	REGULATOR_SUPPLY("cam_af_2.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo18_supply[] = {
+	REGULATOR_SUPPLY("touch", NULL),
+};
+
+static struct regulator_consumer_supply max8997_buck1 =
+	REGULATOR_SUPPLY("vdd_arm", NULL);
+
+static struct regulator_consumer_supply max8997_buck2[] = {
+	REGULATOR_SUPPLY("vdd_int", NULL),
+	REGULATOR_SUPPLY("vdd_int", "exynos4412-busfreq"),
+};
+
+static struct regulator_consumer_supply max8997_buck3 =
+	REGULATOR_SUPPLY("vdd_g3d", NULL);
+
+static struct regulator_consumer_supply max8997_buck4 =
+	REGULATOR_SUPPLY("cam_isp_core_1.2v", NULL);
+
+#define REGULATOR_INIT(_ldo, _name, _min_uV, _max_uV, _always_on, _ops_mask, \
+		       _disabled)					\
+	static struct regulator_init_data _ldo##_init_data = {		\
+		.constraints = {					\
+			.name	= _name,				\
+			.min_uV = _min_uV,				\
+			.max_uV = _max_uV,				\
+			.always_on	= _always_on,			\
+			.boot_on	= _always_on,			\
+			.apply_uV	= 1,				\
+			.valid_ops_mask = _ops_mask,			\
+			.state_mem = {					\
+				.disabled	= _disabled,		\
+				.enabled	= !(_disabled),		\
+			}						\
+		},							\
+		.num_consumer_supplies = ARRAY_SIZE(_ldo##_supply),	\
+		.consumer_supplies = &_ldo##_supply[0],			\
+	};
+
+REGULATOR_INIT(ldo1, "VMIPI_1.8V", 1800000, 1800000, 1,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo6, "VCC_1.8V_AP", 1800000, 1800000, 1, 0, 0);
+REGULATOR_INIT(ldo7, "CAM_SENSOR_CORE_1.2V", 1200000, 1200000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo8, "VUOTG_3.0V", 3000000, 3000000, 1,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo11, "VMIPI_1.0V", 1000000, 1000000, 1,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo12, "VT_CAM_1.8V", 1800000, 1800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo13, "VCC_3.3V_LCD", 3300000, 3300000, 1,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo14, "VCC_1.8V_IO", 1800000, 1800000, 1,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo15, "VDD_2.2V_LCD", 2200000, 2200000, 1,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo16, "CAM_ISP_SENSOR_1.8V", 1800000, 1800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo17, "CAM_AF_2.8V", 2800000, 2800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo18, "TSP_AVDD_3.3V", 3300000, 3300000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+
+static struct regulator_init_data max8997_buck1_data = {
+	.constraints	= {
+		.name	= "vdd_arm range",
+		.min_uV	= 950000,
+		.max_uV	= 1100000,
+		.always_on = 1,
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+		.state_mem = {
+			.disabled = 1,
+		},
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &max8997_buck1,
+};
+
+static struct regulator_init_data max8997_buck2_data = {
+	.constraints	= {
+		.name	= "vdd_int range",
+		.min_uV	= 900000,
+		.max_uV	= 1100000,
+		.always_on = 1,
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+		.state_mem = {
+			.disabled = 1,
+		},
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max8997_buck2),
+	.consumer_supplies = max8997_buck2,
+};
+
+static struct regulator_init_data max8997_buck3_data = {
+	.constraints	= {
+		.name	= "vdd_g3d range",
+		.min_uV	= 950000,
+		.max_uV	= 1150000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+		REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.disabled = 1,
+		},
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &max8997_buck3,
+};
+
+static struct regulator_init_data max8997_buck4_data = {
+	.constraints	= {
+		.name	= "CAM_ISP_CORE_1.2V",
+		.min_uV	= 1200000,
+		.max_uV	= 1200000,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.disabled = 1,
+		},
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &max8997_buck4,
+};
+
+static struct max8997_regulator_data max8997_regulators[] = {
+	{ MAX8997_BUCK1, &max8997_buck1_data, },
+	{ MAX8997_BUCK2, &max8997_buck2_data, },
+	{ MAX8997_BUCK3, &max8997_buck3_data, },
+	{ MAX8997_BUCK4, &max8997_buck4_data, },
+	{ MAX8997_LDO1, &ldo1_init_data, },
+	{ MAX8997_LDO6, &ldo6_init_data, },
+	{ MAX8997_LDO7, &ldo7_init_data, },
+	{ MAX8997_LDO8, &ldo8_init_data, },
+	{ MAX8997_LDO11, &ldo11_init_data, },
+	{ MAX8997_LDO12, &ldo12_init_data, },
+	{ MAX8997_LDO13, &ldo13_init_data, },
+	{ MAX8997_LDO14, &ldo14_init_data, },
+	{ MAX8997_LDO15, &ldo15_init_data, },
+	{ MAX8997_LDO16, &ldo16_init_data, },
+	{ MAX8997_LDO17, &ldo17_init_data, },
+	{ MAX8997_LDO18, &ldo18_init_data, },
+};
+
+struct max8997_platform_data exynos4_max8997_info = {
+	.irq_base = IRQ_BOARD_PMIC_START,
+	.num_regulators = ARRAY_SIZE(max8997_regulators),
+	.regulators = max8997_regulators,
+	.buck1_max_vol = 1100000,
+	.buck2_max_vol = 1100000,
+	.buck5_max_vol = 1100000,
+	.buck_set1 = EXYNOS4212_GPJ1(1),
+	.buck_set2 = EXYNOS4212_GPJ1(2),
+	.buck_set3 = EXYNOS4_GPL0(0),
+#ifdef CONFIG_VIBETONZ
+	.motor = &max8997_motor,
+#endif
+};
+#elif defined(CONFIG_REGULATOR_MAX77686)
+/* max77686 */
+
+#ifdef CONFIG_SND_SOC_WM8994
+static struct regulator_consumer_supply ldo3_supply[] = {
+	REGULATOR_SUPPLY("AVDD2", NULL),
+	REGULATOR_SUPPLY("CPVDD", NULL),
+	REGULATOR_SUPPLY("DBVDD1", NULL),
+	REGULATOR_SUPPLY("DBVDD2", NULL),
+	REGULATOR_SUPPLY("DBVDD3", NULL),
+};
+#else
+static struct regulator_consumer_supply ldo3_supply[] = {};
+#endif
+
+static struct regulator_consumer_supply ldo5_supply[] = {
+	REGULATOR_SUPPLY("vcc_1.8v", NULL),
+	REGULATOR_SUPPLY("touchkey", NULL),
+};
+
+static struct regulator_consumer_supply ldo8_supply[] = {
+	REGULATOR_SUPPLY("vmipi_1.0v", NULL),
+	REGULATOR_SUPPLY("VDD10", "s5p-mipi-dsim.0"),
+	REGULATOR_SUPPLY("vdd", "exynos4-hdmi"),
+	REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"),
+};
+
+static struct regulator_consumer_supply ldo9_supply[] = {
+	REGULATOR_SUPPLY("cam_isp_mipi_1.2v", NULL),
+};
+
+static struct regulator_consumer_supply ldo10_supply[] = {
+	REGULATOR_SUPPLY("vmipi_1.8v", NULL),
+	REGULATOR_SUPPLY("VDD18", "s5p-mipi-dsim.0"),
+	REGULATOR_SUPPLY("vdd_osc", "exynos4-hdmi"),
+};
+
+static struct regulator_consumer_supply ldo11_supply[] = {
+	REGULATOR_SUPPLY("vabb1_1.95v", NULL),
+};
+
+static struct regulator_consumer_supply ldo12_supply[] = {
+	REGULATOR_SUPPLY("votg_3.0v", NULL),
+};
+
+#if defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT) || \
+	defined(CONFIG_MACH_C1_KOR_LGT) || defined(CONFIG_MACH_C1)
+static struct regulator_consumer_supply ldo13_supply[] = {
+	REGULATOR_SUPPLY("vusbhub_osc_1.8v", NULL),
+};
+#endif
+
+static struct regulator_consumer_supply ldo14_supply[] = {
+	REGULATOR_SUPPLY("vabb2_1.95v", NULL),
+};
+
+static struct regulator_consumer_supply ldo17_supply[] = {
+	REGULATOR_SUPPLY("cam_sensor_core_1.2v", NULL),
+};
+
+static struct regulator_consumer_supply ldo18_supply[] = {
+	REGULATOR_SUPPLY("cam_isp_sensor_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo19_supply[] = {
+	REGULATOR_SUPPLY("vt_cam_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo21_supply[] = {
+	REGULATOR_SUPPLY("vtf_2.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo23_supply[] = {
+	REGULATOR_SUPPLY("touch", NULL),
+};
+
+#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) ||	\
+	defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_M3) ||	\
+	defined(CONFIG_MACH_GC1)
+static struct regulator_consumer_supply ldo24_supply[] = {
+	REGULATOR_SUPPLY("touch_1.8v", NULL),
+};
+#else
+static struct regulator_consumer_supply ldo24_supply[] = {
+	REGULATOR_SUPPLY("vlcd_2.2v", NULL),
+	REGULATOR_SUPPLY("VDD3", "s6e8aa0"),
+};
+#endif
+
+static struct regulator_consumer_supply ldo25_supply[] = {
+	REGULATOR_SUPPLY("vlcd_3.3v", NULL),
+	REGULATOR_SUPPLY("VCI", "s6e8aa0"),
+};
+
+static struct regulator_consumer_supply ldo26_supply[] = {
+	REGULATOR_SUPPLY("vmotor", NULL),
+};
+
+static struct regulator_consumer_supply max77686_buck1[] = {
+	REGULATOR_SUPPLY("vdd_mif", NULL),
+	REGULATOR_SUPPLY("vdd_mif", "exynos4412-busfreq"),
+};
+
+static struct regulator_consumer_supply max77686_buck2 =
+	REGULATOR_SUPPLY("vdd_arm", NULL);
+
+static struct regulator_consumer_supply max77686_buck3[] = {
+	REGULATOR_SUPPLY("vdd_int", NULL),
+	REGULATOR_SUPPLY("vdd_int", "exynoss4412-busfreq"),
+};
+
+static struct regulator_consumer_supply max77686_buck4[] = {
+	REGULATOR_SUPPLY("vdd_g3d", NULL),
+	REGULATOR_SUPPLY("vdd_g3d", "mali_dev.0"),
+};
+
+static struct regulator_consumer_supply max77686_buck9 =
+	REGULATOR_SUPPLY("cam_isp_core_1.2v", NULL);
+
+static struct regulator_consumer_supply max77686_enp32khz[] = {
+	REGULATOR_SUPPLY("lpo_in", "bcm47511"),
+	REGULATOR_SUPPLY("lpo", "bcm4334_bluetooth"),
+};
+
+#define REGULATOR_INIT(_ldo, _name, _min_uV, _max_uV, _always_on, _ops_mask, \
+		       _disabled)					\
+	static struct regulator_init_data _ldo##_init_data = {		\
+		.constraints = {					\
+			.name = _name,					\
+			.min_uV = _min_uV,				\
+			.max_uV = _max_uV,				\
+			.always_on	= _always_on,			\
+			.boot_on	= _always_on,			\
+			.apply_uV	= 1,				\
+			.valid_ops_mask = _ops_mask,			\
+			.state_mem = {					\
+				.disabled	= _disabled,		\
+				.enabled	= !(_disabled),		\
+			}						\
+		},							\
+		.num_consumer_supplies = ARRAY_SIZE(_ldo##_supply),	\
+		.consumer_supplies = &_ldo##_supply[0],			\
+	};
+
+REGULATOR_INIT(ldo3, "VCC_1.8V_AP", 1800000, 1800000, 1, 0, 0);
+REGULATOR_INIT(ldo5, "VCC_1.8V_IO", 1800000, 1800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo8, "VMIPI_1.0V", 1000000, 1000000, 1,
+	       REGULATOR_CHANGE_STATUS, 0);
+REGULATOR_INIT(ldo9, "CAM_ISP_MIPI_1.2V", 1200000, 1200000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo10, "VMIPI_1.8V", 1800000, 1800000, 1,
+	       REGULATOR_CHANGE_STATUS, 0);
+REGULATOR_INIT(ldo11, "VABB1_1.95V", 1950000, 1950000, 1,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo12, "VUOTG_3.0V", 3000000, 3000000, 1,
+	       REGULATOR_CHANGE_STATUS, 0);
+#if defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT) || \
+	defined(CONFIG_MACH_C1_KOR_LGT) || defined(CONFIG_MACH_C1)
+REGULATOR_INIT(ldo13, "VUSBHUB_OSC_1.8V", 1800000, 1800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+#endif
+REGULATOR_INIT(ldo14, "VABB2_1.95V", 1950000, 1950000, 1,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo17, "CAM_SENSOR_CORE_1.2V", 1200000, 1200000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo18, "CAM_ISP_SENSOR_1.8V", 1800000, 1800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo19, "VT_CAM_1.8V", 1800000, 1800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo21, "VTF_2.8V", 2800000, 2800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo23, "TSP_AVDD_3.3V", 3300000, 3300000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) ||	\
+	defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_M3) ||	\
+	defined(CONFIG_MACH_GC1)
+REGULATOR_INIT(ldo24, "VDD_1.8V_TSP", 1800000, 1800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+#else
+REGULATOR_INIT(ldo24, "VDD_2.2V_LCD", 2200000, 2200000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+#endif
+REGULATOR_INIT(ldo25, "VCC_3.3V_LCD", 3300000, 3300000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo26, "VCC_MOTOR_3.0V", 3000000, 3000000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+
+#if defined(CONFIG_MACH_SLP_PQ)
+static struct regulator_init_data ldo24_pq11_init_data = {
+	.constraints = {
+		.name = "VDD_1.8V_TSP",
+		.min_uV = 1800000,
+		.max_uV = 1800000,
+		.always_on = 0,
+		.boot_on = 0,
+		.apply_uV = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.enabled	= 0,
+			.disabled	= 1,
+		}
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = ldo24_supply,
+};
+#endif
+
+static struct regulator_init_data max77686_buck1_data = {
+	.constraints = {
+		.name = "vdd_mif range",
+		.min_uV = 850000,
+#ifdef CONFIG_SLP
+		.max_uV = 1100000,
+#else
+		.max_uV = 1050000,
+#endif
+		.always_on = 1,
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_buck1),
+	.consumer_supplies = max77686_buck1,
+};
+
+static struct regulator_init_data max77686_buck2_data = {
+	.constraints = {
+		.name = "vdd_arm range",
+		.min_uV = 850000,
+		.max_uV = 1500000,
+		.apply_uV = 1,
+		.always_on = 1,
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &max77686_buck2,
+};
+
+static struct regulator_init_data max77686_buck3_data = {
+	.constraints = {
+		.name = "vdd_int range",
+		.min_uV = 850000,
+#ifdef CONFIG_SLP
+		.max_uV = 1150000,
+#else
+		.max_uV = 1100000,
+#endif
+		.always_on = 1,
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_buck3),
+	.consumer_supplies = max77686_buck3,
+};
+
+static struct regulator_init_data max77686_buck4_data = {
+	.constraints = {
+		.name = "vdd_g3d range",
+		.min_uV = 850000,
+#ifdef CONFIG_SLP
+		.max_uV = 1100000,
+#else
+		.max_uV = 1075000,
+#endif
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+		REGULATOR_CHANGE_STATUS,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_buck4),
+	.consumer_supplies = max77686_buck4,
+};
+
+static struct regulator_init_data max77686_buck9_data = {
+	.constraints = {
+		.name = "CAM_ISP_CORE_1.2V",
+		.min_uV = 1000000,
+		.max_uV = 1200000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+		REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.disabled = 1,
+		},
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &max77686_buck9,
+};
+
+static struct regulator_init_data max77686_enp32khz_data = {
+	.constraints = {
+		.name = "32KHZ_PMIC",
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.enabled	= 1,
+			.disabled	= 0,
+		},
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_enp32khz),
+	.consumer_supplies = max77686_enp32khz,
+};
+
+static struct max77686_regulator_data max77686_regulators[] = {
+	{MAX77686_BUCK1, &max77686_buck1_data,},
+	{MAX77686_BUCK2, &max77686_buck2_data,},
+	{MAX77686_BUCK3, &max77686_buck3_data,},
+	{MAX77686_BUCK4, &max77686_buck4_data,},
+	{MAX77686_BUCK9, &max77686_buck9_data,},
+	{MAX77686_LDO3, &ldo3_init_data,},
+	{MAX77686_LDO5, &ldo5_init_data,},
+	{MAX77686_LDO8, &ldo8_init_data,},
+	{MAX77686_LDO9, &ldo9_init_data,},
+	{MAX77686_LDO10, &ldo10_init_data,},
+	{MAX77686_LDO11, &ldo11_init_data,},
+	{MAX77686_LDO12, &ldo12_init_data,},
+#if defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT) || \
+	defined(CONFIG_MACH_C1_KOR_LGT) || defined(CONFIG_MACH_C1)
+	{MAX77686_LDO13, &ldo13_init_data,},
+#endif
+	{MAX77686_LDO14, &ldo14_init_data,},
+	{MAX77686_LDO17, &ldo17_init_data,},
+	{MAX77686_LDO18, &ldo18_init_data,},
+	{MAX77686_LDO19, &ldo19_init_data,},
+	{MAX77686_LDO21, &ldo21_init_data,},
+	{MAX77686_LDO23, &ldo23_init_data,},
+	{MAX77686_LDO24, &ldo24_init_data,},
+	{MAX77686_LDO25, &ldo25_init_data,},
+	{MAX77686_LDO26, &ldo26_init_data,},
+	{MAX77686_P32KH, &max77686_enp32khz_data,},
+};
+
+struct max77686_opmode_data max77686_opmode_data[MAX77686_REG_MAX] = {
+	[MAX77686_LDO3] = {MAX77686_LDO3, MAX77686_OPMODE_NORMAL},
+	[MAX77686_LDO8] = {MAX77686_LDO8, MAX77686_OPMODE_STANDBY},
+	[MAX77686_LDO10] = {MAX77686_LDO10, MAX77686_OPMODE_STANDBY},
+	[MAX77686_LDO11] = {MAX77686_LDO11, MAX77686_OPMODE_STANDBY},
+	[MAX77686_LDO12] = {MAX77686_LDO12, MAX77686_OPMODE_STANDBY},
+#if defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT) || \
+	defined(CONFIG_MACH_C1_KOR_LGT) || defined(CONFIG_MACH_C1)
+	[MAX77686_LDO13] = {MAX77686_LDO13, MAX77686_OPMODE_NORMAL},
+#endif
+	[MAX77686_LDO14] = {MAX77686_LDO14, MAX77686_OPMODE_STANDBY},
+	[MAX77686_BUCK1] = {MAX77686_BUCK1, MAX77686_OPMODE_STANDBY},
+	[MAX77686_BUCK2] = {MAX77686_BUCK2, MAX77686_OPMODE_STANDBY},
+	[MAX77686_BUCK3] = {MAX77686_BUCK3, MAX77686_OPMODE_STANDBY},
+	[MAX77686_BUCK4] = {MAX77686_BUCK4, MAX77686_OPMODE_STANDBY},
+};
+
+struct max77686_platform_data exynos4_max77686_info = {
+	.num_regulators = ARRAY_SIZE(max77686_regulators),
+	.regulators = max77686_regulators,
+	.irq_gpio	= GPIO_PMIC_IRQ,
+	.irq_base	= IRQ_BOARD_PMIC_START,
+	.wakeup		= 1,
+
+	.opmode_data = max77686_opmode_data,
+	.ramp_rate = MAX77686_RAMP_RATE_27MV,
+	.wtsr_smpl = MAX77686_WTSR_ENABLE | MAX77686_SMPL_ENABLE,
+
+	.buck234_gpio_dvs = {
+		/* Use DVS2 register of each bucks to supply stable power
+		 * after sudden reset */
+		{GPIO_PMIC_DVS1, 1},
+		{GPIO_PMIC_DVS2, 0},
+		{GPIO_PMIC_DVS3, 0},
+	},
+	.buck234_gpio_selb = {
+		GPIO_BUCK2_SEL,
+		GPIO_BUCK3_SEL,
+		GPIO_BUCK4_SEL,
+	},
+	.buck2_voltage[0] = 1100000,	/* 1.1V */
+	.buck2_voltage[1] = 1100000,	/* 1.1V */
+	.buck2_voltage[2] = 1100000,	/* 1.1V */
+	.buck2_voltage[3] = 1100000,	/* 1.1V */
+	.buck2_voltage[4] = 1100000,	/* 1.1V */
+	.buck2_voltage[5] = 1100000,	/* 1.1V */
+	.buck2_voltage[6] = 1100000,	/* 1.1V */
+	.buck2_voltage[7] = 1100000,	/* 1.1V */
+
+	.buck3_voltage[0] = 1100000,	/* 1.1V */
+	.buck3_voltage[1] = 1000000,	/* 1.0V */
+	.buck3_voltage[2] = 1100000,	/* 1.1V */
+	.buck3_voltage[3] = 1100000,	/* 1.1V */
+	.buck3_voltage[4] = 1100000,	/* 1.1V */
+	.buck3_voltage[5] = 1100000,	/* 1.1V */
+	.buck3_voltage[6] = 1100000,	/* 1.1V */
+	.buck3_voltage[7] = 1100000,	/* 1.1V */
+
+	.buck4_voltage[0] = 1100000,	/* 1.1V */
+	.buck4_voltage[1] = 1000000,	/* 1.0V */
+	.buck4_voltage[2] = 1100000,	/* 1.1V */
+	.buck4_voltage[3] = 1100000,	/* 1.1V */
+	.buck4_voltage[4] = 1100000,	/* 1.1V */
+	.buck4_voltage[5] = 1100000,	/* 1.1V */
+	.buck4_voltage[6] = 1100000,	/* 1.1V */
+	.buck4_voltage[7] = 1100000,	/* 1.1V */
+};
+
+void midas_power_init(void)
+{
+	printk(KERN_INFO "%s\n", __func__);
+}
+#endif /* CONFIG_REGULATOR_MAX77686 */
+
+void midas_power_set_muic_pdata(void *pdata, int gpio)
+{
+	gpio_request(gpio, "AP_PMIC_IRQ");
+	s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
+	s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+
+#ifdef CONFIG_REGULATOR_MAX8997
+	exynos4_max8997_info.muic = pdata;
+#endif
+}
+
+void midas_power_gpio_init(void)
+{
+#ifdef CONFIG_REGULATOR_MAX8997
+	int gpio;
+
+	gpio = EXYNOS4212_GPJ1(1);
+	gpio_request(gpio, "BUCK_SET1");
+	s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+
+	gpio = EXYNOS4212_GPJ1(2);
+	gpio_request(gpio, "BUCK_SET2");
+	s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+
+	gpio = EXYNOS4_GPL0(0);
+	gpio_request(gpio, "BUCK_SET3");
+	s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+#endif
+}
+
+#ifdef CONFIG_MFD_MAX77693
+static struct regulator_consumer_supply safeout1_supply[] = {
+	REGULATOR_SUPPLY("safeout1", NULL),
+};
+
+static struct regulator_consumer_supply safeout2_supply[] = {
+	REGULATOR_SUPPLY("safeout2", NULL),
+};
+
+static struct regulator_consumer_supply charger_supply[] = {
+	REGULATOR_SUPPLY("vinchg1", "charger-manager.0"),
+	REGULATOR_SUPPLY("vinchg1", NULL),
+};
+
+static struct regulator_init_data safeout1_init_data = {
+	.constraints	= {
+		.name		= "safeout1 range",
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.always_on	= 0,
+		.boot_on	= 1,
+		.state_mem	= {
+			.enabled = 1,
+		},
+	},
+	.num_consumer_supplies	= ARRAY_SIZE(safeout1_supply),
+	.consumer_supplies	= safeout1_supply,
+};
+
+static struct regulator_init_data safeout2_init_data = {
+	.constraints	= {
+		.name		= "safeout2 range",
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.always_on	= 0,
+		.boot_on	= 0,
+		.state_mem	= {
+			.enabled = 1,
+		},
+	},
+	.num_consumer_supplies	= ARRAY_SIZE(safeout2_supply),
+	.consumer_supplies	= safeout2_supply,
+};
+
+static struct regulator_init_data charger_init_data = {
+	.constraints	= {
+		.name		= "CHARGER",
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS |
+		REGULATOR_CHANGE_CURRENT,
+		.boot_on	= 1,
+		.min_uA		= 60000,
+		.max_uA		= 2580000,
+	},
+	.num_consumer_supplies	= ARRAY_SIZE(charger_supply),
+	.consumer_supplies	= charger_supply,
+};
+
+struct max77693_regulator_data max77693_regulators[] = {
+	{MAX77693_ESAFEOUT1, &safeout1_init_data,},
+	{MAX77693_ESAFEOUT2, &safeout2_init_data,},
+	{MAX77693_CHARGER, &charger_init_data,},
+};
+
+#if defined(CONFIG_MACH_SLP_PQ)
+/* this initcall replace ldo24 from VDD 2.2 to VDD 1.8 for evt1.1 board. */
+static int __init regulator_init_with_rev(void)
+{
+	/* SLP PQ Promixa evt1.1 */
+	if (system_rev != 3) {
+		ldo24_supply[0].supply = "touch_1.8v";
+		ldo24_supply[0].dev_name = NULL;
+
+		memcpy(&ldo24_init_data, &ldo24_pq11_init_data,
+		       sizeof(struct regulator_init_data));
+	}
+	return 0;
+}
+
+postcore_initcall(regulator_init_with_rev);
+#endif /* CONFIG_MACH_SLP_PQ */
+#endif /* CONFIG_MFD_MAX77693 */
+
+#if defined(CONFIG_REGULATOR_S5M8767)
+/* S5M8767 Regulator */
+
+#ifdef CONFIG_SND_SOC_WM8994
+static struct regulator_consumer_supply ldo3_supply[] = {
+	REGULATOR_SUPPLY("AVDD2", NULL),
+	REGULATOR_SUPPLY("CPVDD", NULL),
+	REGULATOR_SUPPLY("DBVDD1", NULL),
+	REGULATOR_SUPPLY("DBVDD2", NULL),
+	REGULATOR_SUPPLY("DBVDD3", NULL),
+};
+#endif
+
+static struct regulator_consumer_supply ldo8_supply[] = {
+	REGULATOR_SUPPLY("vmipi_1.0v", NULL),
+	REGULATOR_SUPPLY("VDD10", "s5p-mipi-dsim.0"),
+};
+
+static struct regulator_consumer_supply ldo9_supply[] = {
+	REGULATOR_SUPPLY("cam_isp_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo10_supply[] = {
+	REGULATOR_SUPPLY("vt_cam_dvdd_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo13_supply[] = {
+	REGULATOR_SUPPLY("vmipi_1.8v", NULL),
+	REGULATOR_SUPPLY("VDD18", "s5p-mipi-dsim.0"),
+};
+
+static struct regulator_consumer_supply ldo19_supply[] = {
+	REGULATOR_SUPPLY("cam_af_2.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo20_supply[] = {
+	REGULATOR_SUPPLY("vlcd_3.0v", NULL),
+	REGULATOR_SUPPLY("VCI", "s6e8aa0"),
+};
+
+static struct regulator_consumer_supply ldo21_supply[] = {
+	REGULATOR_SUPPLY("vmotor", NULL),
+};
+
+static struct regulator_consumer_supply ldo22_supply[] = {
+	REGULATOR_SUPPLY("cam_sensor_a2.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo23_supply[] = {
+	REGULATOR_SUPPLY("vtf_2.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo24_supply[] = {
+	REGULATOR_SUPPLY("touch", NULL),
+};
+
+static struct regulator_consumer_supply ldo25_supply[] = {
+	REGULATOR_SUPPLY("cam_sensor_core_1.2v", NULL),
+};
+
+static struct regulator_consumer_supply ldo26_supply[] = {
+	REGULATOR_SUPPLY("cam_isp_sensor_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo27_supply[] = {
+	REGULATOR_SUPPLY("vt_cam_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo28_supply[] = {
+	REGULATOR_SUPPLY("3_touch_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply s5m8767_buck1[] = {
+	REGULATOR_SUPPLY("vdd_mif", NULL),
+	REGULATOR_SUPPLY("vdd_mif", "exynos4212-busfreq"),
+};
+
+static struct regulator_consumer_supply s5m8767_buck2 =
+	REGULATOR_SUPPLY("vdd_arm", NULL);
+
+static struct regulator_consumer_supply s5m8767_buck3[] = {
+	REGULATOR_SUPPLY("vdd_int", NULL),
+	REGULATOR_SUPPLY("vdd_int", "exynos4212-busfreq"),
+};
+
+static struct regulator_consumer_supply s5m8767_buck4[] = {
+	REGULATOR_SUPPLY("vdd_g3d", NULL),
+	REGULATOR_SUPPLY("vdd_g3d", "mali_dev.0"),
+};
+
+static struct regulator_consumer_supply s5m8767_buck6 =
+	REGULATOR_SUPPLY("cam_isp_core_1.2v", NULL);
+
+static struct regulator_consumer_supply s5m8767_enp32khz[] = {
+	REGULATOR_SUPPLY("lpo_in", "bcm47511"),
+	REGULATOR_SUPPLY("lpo", "bcm4334_bluetooth"),
+};
+
+#define REGULATOR_INIT(_ldo, _name, _min_uV, _max_uV, _always_on, _ops_mask, \
+		       _disabled)					\
+	static struct regulator_init_data _ldo##_init_data = {		\
+		.constraints = {					\
+			.name = _name,					\
+			.min_uV = _min_uV,				\
+			.max_uV = _max_uV,				\
+			.always_on	= _always_on,			\
+			.boot_on	= _always_on,			\
+			.apply_uV	= 1,				\
+			.valid_ops_mask = _ops_mask,			\
+			.state_mem = {					\
+				.disabled	= _disabled,		\
+				.enabled	= !(_disabled),		\
+			}						\
+		},							\
+		.num_consumer_supplies = ARRAY_SIZE(_ldo##_supply),	\
+		.consumer_supplies = &_ldo##_supply[0],			\
+	};
+
+REGULATOR_INIT(ldo3, "VCC_1.8V_AP", 1800000, 1800000, 1, 0, 0);
+REGULATOR_INIT(ldo8, "VMIPI_1.0V", 1000000, 1000000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo9, "CAM_ISP_1.8V", 1800000, 1800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo10, "VT_CAM_DVDD_1.8V", 1800000, 1800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo13, "VMIPI_1.8V", 1800000, 1800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo19, "CAM_AF_2.8V", 2800000, 2800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo20, "VCC_3.0V_LCD", 3000000, 3000000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo21, "VCC_MOTOR_3.0V", 3000000, 3000000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo22, "CAM_SENSOR_A2.8V", 2800000, 2800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo23, "VTF_2.8V", 2800000, 2800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo24, "TSP_AVDD_3.3V", 3300000, 3300000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo25, "CAM_SENSOR_CORE_1.2V", 1200000, 1200000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo26, "CAM_ISP_SENSOR_1.8V", 1800000, 1800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo27, "VT_CAM_1.8V", 1800000, 1800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo28, "3_TOUCH_1.8V", 1800000, 1800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+
+static struct regulator_init_data s5m8767_buck1_data = {
+	.constraints = {
+		.name = "vdd_mif range",
+		.min_uV = 850000,
+		.max_uV = 1100000,
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(s5m8767_buck1),
+	.consumer_supplies = s5m8767_buck1,
+};
+
+static struct regulator_init_data s5m8767_buck2_data = {
+	.constraints = {
+		.name = "vdd_arm range",
+		.min_uV = 850000,
+		.max_uV = 1500000,
+		.apply_uV = 1,
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &s5m8767_buck2,
+};
+
+static struct regulator_init_data s5m8767_buck3_data = {
+	.constraints = {
+		.name = "vdd_int range",
+		.min_uV = 850000,
+		.max_uV = 1300000,
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(s5m8767_buck3),
+	.consumer_supplies = s5m8767_buck3,
+};
+
+static struct regulator_init_data s5m8767_buck4_data = {
+	.constraints = {
+		.name = "vdd_g3d range",
+		.min_uV = 850000,
+		.max_uV = 1150000,
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+		REGULATOR_CHANGE_STATUS,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(s5m8767_buck4),
+	.consumer_supplies = s5m8767_buck4,
+};
+
+static struct regulator_init_data s5m8767_buck6_data = {
+	.constraints = {
+		.name = "CAM_ISP_CORE_1.2V",
+		.min_uV = 1000000,
+		.max_uV = 1200000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+		REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.disabled = 1,
+		},
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &s5m8767_buck6,
+};
+
+static struct regulator_init_data s5m8767_enp32khz_data = {
+	.constraints = {
+		.name = "32KHZ_PMIC",
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.enabled	= 1,
+			.disabled	= 0,
+		},
+	},
+	.num_consumer_supplies = ARRAY_SIZE(s5m8767_enp32khz),
+	.consumer_supplies = s5m8767_enp32khz,
+};
+
+static struct s5m_regulator_data s5m8767_regulators[] = {
+	{S5M8767_BUCK1, &s5m8767_buck1_data,},
+	{S5M8767_BUCK2, &s5m8767_buck2_data,},
+	{S5M8767_BUCK3, &s5m8767_buck3_data,},
+	{S5M8767_BUCK4, &s5m8767_buck4_data,},
+	{S5M8767_BUCK6, &s5m8767_buck6_data,},
+	{S5M8767_LDO3, &ldo3_init_data,},
+	{S5M8767_LDO8, &ldo8_init_data,},
+	{S5M8767_LDO9, &ldo9_init_data,},
+	{S5M8767_LDO10, &ldo10_init_data,},
+	{S5M8767_LDO13, &ldo13_init_data,},
+	{S5M8767_LDO19, &ldo19_init_data,},
+	{S5M8767_LDO20, &ldo20_init_data,},
+	{S5M8767_LDO21, &ldo21_init_data,},
+	{S5M8767_LDO22, &ldo22_init_data,},
+	{S5M8767_LDO23, &ldo23_init_data,},
+	{S5M8767_LDO24, &ldo24_init_data,},
+	{S5M8767_LDO25, &ldo25_init_data,},
+	{S5M8767_LDO26, &ldo26_init_data,},
+	{S5M8767_LDO27, &ldo27_init_data,},
+	{S5M8767_LDO28, &ldo28_init_data,},
+};
+
+struct s5m_opmode_data s5m8767_opmode_data[S5M8767_REG_MAX] = {
+	[S5M8767_BUCK1] = {S5M8767_BUCK1, S5M_OPMODE_STANDBY},
+	[S5M8767_BUCK2] = {S5M8767_BUCK2, S5M_OPMODE_STANDBY},
+	[S5M8767_BUCK3] = {S5M8767_BUCK3, S5M_OPMODE_STANDBY},
+	[S5M8767_BUCK4] = {S5M8767_BUCK4, S5M_OPMODE_STANDBY},
+	[S5M8767_BUCK6] = {S5M8767_BUCK6, S5M_OPMODE_STANDBY},
+	[S5M8767_LDO3] = {S5M8767_LDO3, S5M_OPMODE_NORMAL},
+	[S5M8767_LDO8] = {S5M8767_LDO8, S5M_OPMODE_NORMAL},
+	[S5M8767_LDO9] = {S5M8767_LDO9, S5M_OPMODE_NORMAL},
+	[S5M8767_LDO10] = {S5M8767_LDO10, S5M_OPMODE_NORMAL},
+	[S5M8767_LDO19] = {S5M8767_LDO19, S5M_OPMODE_NORMAL},
+	[S5M8767_LDO20] = {S5M8767_LDO20, S5M_OPMODE_NORMAL},
+	[S5M8767_LDO21] = {S5M8767_LDO21, S5M_OPMODE_NORMAL},
+	[S5M8767_LDO22] = {S5M8767_LDO22, S5M_OPMODE_NORMAL},
+	[S5M8767_LDO23] = {S5M8767_LDO23, S5M_OPMODE_STANDBY},
+	[S5M8767_LDO24] = {S5M8767_LDO24, S5M_OPMODE_NORMAL},
+	[S5M8767_LDO25] = {S5M8767_LDO25, S5M_OPMODE_NORMAL},
+	[S5M8767_LDO26] = {S5M8767_LDO26, S5M_OPMODE_NORMAL},
+	[S5M8767_LDO27] = {S5M8767_LDO27, S5M_OPMODE_NORMAL},
+	[S5M8767_LDO28] = {S5M8767_LDO28, S5M_OPMODE_NORMAL},
+};
+
+struct s5m_platform_data exynos4_s5m8767_info = {
+	.device_type	= S5M8767X,
+	.num_regulators = ARRAY_SIZE(s5m8767_regulators),
+	.regulators = s5m8767_regulators,
+	.buck2_ramp_enable	= true,
+	.buck3_ramp_enable	= true,
+	.buck4_ramp_enable	= true,
+	.irq_gpio	= GPIO_PMIC_IRQ,
+	.irq_base	= IRQ_BOARD_PMIC_START,
+	.wakeup		= 1,
+
+	.opmode_data = s5m8767_opmode_data,
+	.wtsr_smpl		= 1,
+
+	.buck2_voltage[0] = 1100000,	/* 1.1V */
+	.buck2_voltage[1] = 1100000,	/* 1.1V */
+	.buck2_voltage[2] = 1100000,	/* 1.1V */
+	.buck2_voltage[3] = 1100000,	/* 1.1V */
+	.buck2_voltage[4] = 1100000,	/* 1.1V */
+	.buck2_voltage[5] = 1100000,	/* 1.1V */
+	.buck2_voltage[6] = 1100000,	/* 1.1V */
+	.buck2_voltage[7] = 1100000,	/* 1.1V */
+
+	.buck3_voltage[0] = 1100000,	/* 1.1V */
+	.buck3_voltage[1] = 1100000,	/* 1.1V */
+	.buck3_voltage[2] = 1100000,	/* 1.1V */
+	.buck3_voltage[3] = 1100000,	/* 1.1V */
+	.buck3_voltage[4] = 1100000,	/* 1.1V */
+	.buck3_voltage[5] = 1100000,	/* 1.1V */
+	.buck3_voltage[6] = 1100000,	/* 1.1V */
+	.buck3_voltage[7] = 1100000,	/* 1.1V */
+
+	.buck4_voltage[0] = 1100000,	/* 1.1V */
+	.buck4_voltage[1] = 1100000,	/* 1.1V */
+	.buck4_voltage[2] = 1100000,	/* 1.1V */
+	.buck4_voltage[3] = 1100000,	/* 1.1V */
+	.buck4_voltage[4] = 1100000,	/* 1.1V */
+	.buck4_voltage[5] = 1100000,	/* 1.1V */
+	.buck4_voltage[6] = 1100000,	/* 1.1V */
+	.buck4_voltage[7] = 1100000,	/* 1.1V */
+
+	.buck_ramp_delay = 10,
+	.buck_default_idx	= 3,
+
+	.buck_gpios[0]		= GPIO_BUCK2_SEL,
+	.buck_gpios[1]		= GPIO_BUCK3_SEL,
+	.buck_gpios[2]		= GPIO_BUCK4_SEL,
+};
+
+void midas_power_init(void)
+{
+#ifdef CONFIG_MACH_S2PLUS
+	ldo8_init_data.constraints.always_on = 1;
+	ldo13_init_data.constraints.always_on = 1;
+#else
+	ldo8_init_data.constraints.always_on = 1;
+	ldo10_init_data.constraints.always_on = 1;
+#endif
+}
+
+/* End of S5M8767 */
+#endif
diff --git a/arch/arm/mach-exynos/midas-sensor.c b/arch/arm/mach-exynos/midas-sensor.c
new file mode 100644
index 0000000..6c8385c
--- /dev/null
+++ b/arch/arm/mach-exynos/midas-sensor.c
@@ -0,0 +1,428 @@
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/sensor/sensors_core.h>
+#include <linux/sensor/ak8975.h>
+#include <linux/sensor/k3dh.h>
+#include <linux/sensor/gp2a.h>
+#include <linux/sensor/lsm330dlc_accel.h>
+#include <linux/sensor/lsm330dlc_gyro.h>
+#include <linux/sensor/lps331ap.h>
+#include <linux/sensor/cm36651.h>
+#include <linux/sensor/cm3663.h>
+#include <linux/sensor/bh1721.h>
+
+#include <plat/gpio-cfg.h>
+#include <mach/regs-gpio.h>
+#include <mach/gpio.h>
+#include "midas.h"
+
+static int accel_get_position(void);
+
+static struct accel_platform_data accel_pdata = {
+	.accel_get_position = accel_get_position,
+	.axis_adjust = true,
+};
+
+static struct i2c_board_info i2c_devs1[] __initdata = {
+#ifdef CONFIG_SENSORS_LSM330DLC
+	{
+		I2C_BOARD_INFO("lsm330dlc_accel", (0x32 >> 1)),
+		.platform_data = &accel_pdata,
+	},
+	{
+		I2C_BOARD_INFO("lsm330dlc_gyro", (0xD6 >> 1)),
+	},
+#elif defined(CONFIG_SENSORS_K3DH)
+	{
+		I2C_BOARD_INFO("k3dh", 0x19),
+		.platform_data	= &accel_pdata,
+	},
+#endif
+};
+
+static int accel_get_position(void)
+{
+	int position = 0;
+
+#if defined(CONFIG_MACH_C1VZW) /* C1_SPR */
+	if (system_rev == 1)
+		position = 3; /* top/lower-left */
+	else
+		position = 2; /* top/lower-right */
+#elif defined(CONFIG_MACH_C1CTC)
+		position = 2; /* top/lower-right */
+#elif defined(CONFIG_MACH_M0_CMCC)
+	if (system_rev == 2)
+		position = 0; /* top/upper-left */
+	else
+		position = 2; /* top/lower-right */
+#elif defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT)
+	if (system_rev >= 6)
+		position = 6; /* bottom/lower-right */
+	else
+		position = 3; /* top/lower-left */
+#elif defined(CONFIG_MACH_C1_KOR_LGT)
+	if (system_rev >= 6)
+		position = 2; /* top/lower-right */
+	else if (system_rev == 5)
+		position = 4; /* bottom/upper-left */
+	else
+		position = 3; /* top/lower-left */
+#elif defined(CONFIG_MACH_S2PLUS)
+	position = 3; /* top/lower-left */
+#elif defined(CONFIG_MACH_P4NOTE)
+	position = 4; /* bottom/upper-left */
+#elif defined(CONFIG_MACH_M0)
+	if (system_rev == 3 || system_rev == 0)
+		position = 6; /* bottom/lower-right */
+	else if (system_rev == 1 || system_rev == 2\
+		|| system_rev == 4 || system_rev == 5)
+		position = 0; /* top/upper-left */
+	else
+		position = 2; /* top/lower-right */
+#elif defined(CONFIG_MACH_C1)
+	if (system_rev == 3 || system_rev == 0)
+		position = 7; /* bottom/lower-left */
+	else if (system_rev == 2)
+		position = 3; /* top/lower-left */
+	else
+		position = 2; /* top/lower-right */
+#else /* Common */
+	position = 2; /* top/lower-right */
+#endif
+	return position;
+}
+
+#if defined(CONFIG_SENSORS_LSM330DLC) || \
+	defined(CONFIG_SENSORS_K3DH)
+static int accel_gpio_init(void)
+{
+	int ret = gpio_request(GPIO_ACC_INT, "accelerometer_irq");
+
+	pr_info("%s\n", __func__);
+
+	if (ret) {
+		pr_err("%s, Failed to request gpio lsm330dlc_accel_irq(%d)\n",
+			__func__, ret);
+		return ret;
+	}
+
+	/* Accelerometer sensor interrupt pin initialization */
+	s3c_gpio_cfgpin(GPIO_ACC_INT, S3C_GPIO_INPUT);
+	gpio_set_value(GPIO_ACC_INT, 2);
+	s3c_gpio_setpull(GPIO_ACC_INT, S3C_GPIO_PULL_NONE);
+	s5p_gpio_set_drvstr(GPIO_ACC_INT, S5P_GPIO_DRVSTR_LV1);
+	i2c_devs1[0].irq = gpio_to_irq(GPIO_ACC_INT);
+
+	return ret;
+}
+#endif
+
+#ifdef CONFIG_SENSORS_LSM330DLC
+static int gyro_gpio_init(void)
+{
+	int ret = gpio_request(GPIO_GYRO_INT, "lsm330dlc_gyro_irq");
+
+	pr_info("%s\n", __func__);
+
+	if (ret) {
+		pr_err("%s, Failed to request gpio lsm330dlc_gyro_irq(%d)\n",
+			__func__, ret);
+		return ret;
+	}
+
+	ret = gpio_request(GPIO_GYRO_DE, "lsm330dlc_gyro_data_enable");
+
+	if (ret) {
+		pr_err("%s, Failed to request gpio lsm330dlc_gyro_data_enable(%d)\n",
+			__func__, ret);
+		return ret;
+	}
+
+	/* Gyro sensor interrupt pin initialization */
+#if 0
+	s5p_register_gpio_interrupt(GPIO_GYRO_INT);
+	s3c_gpio_cfgpin(GPIO_GYRO_INT, S3C_GPIO_SFN(0xF));
+#else
+	s3c_gpio_cfgpin(GPIO_GYRO_INT, S3C_GPIO_INPUT);
+#endif
+	gpio_set_value(GPIO_GYRO_INT, 2);
+	s3c_gpio_setpull(GPIO_GYRO_INT, S3C_GPIO_PULL_DOWN);
+	s5p_gpio_set_drvstr(GPIO_GYRO_INT, S5P_GPIO_DRVSTR_LV1);
+#if 0
+	i2c_devs1[1].irq = gpio_to_irq(GPIO_GYRO_INT); /* interrupt */
+#else
+	i2c_devs1[1].irq = -1; /* polling */
+#endif
+
+	/* Gyro sensor data enable pin initialization */
+	s3c_gpio_cfgpin(GPIO_GYRO_DE, S3C_GPIO_OUTPUT);
+	gpio_set_value(GPIO_GYRO_DE, 0);
+	s3c_gpio_setpull(GPIO_GYRO_DE, S3C_GPIO_PULL_DOWN);
+	s5p_gpio_set_drvstr(GPIO_GYRO_DE, S5P_GPIO_DRVSTR_LV1);
+
+	return ret;
+}
+#endif
+
+#if defined(CONFIG_SENSORS_GP2A) || defined(CONFIG_SENSORS_CM36651) || \
+	defined(CONFIG_SENSORS_CM3663)
+static int proximity_leda_on(bool onoff)
+{
+	pr_info("%s, onoff = %d\n", __func__, onoff);
+
+	gpio_set_value(GPIO_PS_ALS_EN, onoff);
+
+	return 0;
+}
+
+static int optical_gpio_init(void)
+{
+	int ret = gpio_request(GPIO_PS_ALS_EN, "optical_power_supply_on");
+
+	pr_info("%s\n", __func__);
+
+	if (ret) {
+		pr_err("%s, Failed to request gpio optical power supply(%d)\n",
+			__func__, ret);
+		return ret;
+	}
+
+	/* configuring for gp2a gpio for LEDA power */
+	s3c_gpio_cfgpin(GPIO_PS_ALS_EN, S3C_GPIO_OUTPUT);
+	gpio_set_value(GPIO_PS_ALS_EN, 0);
+	s3c_gpio_setpull(GPIO_PS_ALS_EN, S3C_GPIO_PULL_NONE);
+	return ret;
+}
+#endif
+
+#if defined(CONFIG_SENSORS_CM36651)
+/* Depends window, threshold is needed to be set */
+static u8 cm36651_get_threshold(void)
+{
+	u8 threshold = 17;
+
+	/* Add model config and threshold here. */
+#if defined(CONFIG_MACH_M0)
+	if (system_rev >= 12)
+		threshold = 15;
+#elif defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT) ||\
+	defined(CONFIG_MACH_C1_KOR_LGT)
+	if (system_rev >= 6)
+		threshold = 13;
+#elif defined(CONFIG_MACH_C1VZW)
+	if (system_rev >= 11)
+		threshold = 13;
+#elif defined(CONFIG_MACH_C1)
+	if (system_rev >= 7)
+		threshold = 13;
+#endif
+
+	return threshold;
+}
+
+static struct cm36651_platform_data cm36651_pdata = {
+	.cm36651_led_on = proximity_leda_on,
+	.cm36651_get_threshold = cm36651_get_threshold,
+	.irq = GPIO_PS_ALS_INT,
+};
+#endif
+
+#if defined(CONFIG_SENSORS_CM3663)
+static struct cm3663_platform_data cm3663_pdata = {
+	.proximity_power = proximity_leda_on,
+};
+#endif
+
+#if defined(CONFIG_SENSORS_GP2A)
+static struct gp2a_platform_data gp2a_pdata = {
+	.gp2a_led_on	= proximity_leda_on,
+	.p_out = GPIO_PS_ALS_INT,
+};
+
+static struct platform_device opt_gp2a = {
+	.name = "gp2a-opt",
+	.id = -1,
+	.dev = {
+		.platform_data = &gp2a_pdata,
+	},
+};
+#endif
+
+static struct i2c_board_info i2c_devs9_emul[] __initdata = {
+#if defined(CONFIG_SENSORS_GP2A)
+	{
+		I2C_BOARD_INFO("gp2a", (0x72 >> 1)),
+	},
+#elif defined(CONFIG_SENSORS_CM36651)
+	{
+		I2C_BOARD_INFO("cm36651", (0x30 >> 1)),
+		.platform_data = &cm36651_pdata,
+	},
+#elif defined(CONFIG_SENSORS_CM3663)
+	{
+		I2C_BOARD_INFO("cm3663", (0x20)),
+		.irq = GPIO_PS_ALS_INT,
+		.platform_data = &cm3663_pdata,
+	},
+#elif defined(CONFIG_SENSORS_BH1721)
+	{
+		I2C_BOARD_INFO("bh1721fvc", 0x23),
+	},
+#endif
+};
+
+#ifdef CONFIG_SENSORS_AK8975C
+static struct akm8975_platform_data akm8975_pdata = {
+	.gpio_data_ready_int = GPIO_MSENSOR_INT,
+};
+
+static struct i2c_board_info i2c_devs10_emul[] __initdata = {
+	{
+		I2C_BOARD_INFO("ak8975", 0x0C),
+		.platform_data = &akm8975_pdata,
+	},
+};
+
+static int ak8975c_gpio_init(void)
+{
+	int ret = gpio_request(GPIO_MSENSOR_INT, "gpio_akm_int");
+
+	pr_info("%s\n", __func__);
+
+	if (ret) {
+		pr_err("%s, Failed to request gpio akm_int.(%d)\n",
+			__func__, ret);
+		return ret;
+	}
+
+	s5p_register_gpio_interrupt(GPIO_MSENSOR_INT);
+	s3c_gpio_setpull(GPIO_MSENSOR_INT, S3C_GPIO_PULL_DOWN);
+	s3c_gpio_cfgpin(GPIO_MSENSOR_INT, S3C_GPIO_SFN(0xF));
+	i2c_devs10_emul[0].irq = gpio_to_irq(GPIO_MSENSOR_INT);
+	return ret;
+}
+#endif
+
+#ifdef CONFIG_SENSORS_LPS331
+static int lps331_gpio_init(void)
+{
+	int ret = gpio_request(GPIO_BARO_INT, "lps331_irq");
+
+	pr_info("%s\n", __func__);
+
+	if (ret) {
+		pr_err("%s, Failed to request gpio lps331_irq(%d)\n",
+			__func__, ret);
+		return ret;
+	}
+
+	s3c_gpio_cfgpin(GPIO_BARO_INT, S3C_GPIO_INPUT);
+	gpio_set_value(GPIO_BARO_INT, 2);
+	s3c_gpio_setpull(GPIO_BARO_INT, S3C_GPIO_PULL_NONE);
+	s5p_gpio_set_drvstr(GPIO_BARO_INT, S5P_GPIO_DRVSTR_LV1);
+	return ret;
+}
+
+static struct lps331ap_platform_data lps331ap_pdata = {
+	.irq =	GPIO_BARO_INT,
+};
+
+static struct i2c_board_info i2c_devs11_emul[] __initdata = {
+	{
+		I2C_BOARD_INFO("lps331ap", 0x5D),
+		.platform_data = &lps331ap_pdata,
+	},
+};
+#endif
+
+static int __init midas_sensor_init(void)
+{
+	int ret = 0;
+
+	/* Gyro & Accelerometer Sensor */
+#if defined(CONFIG_SENSORS_LSM330DLC)
+	ret = accel_gpio_init();
+	if (ret < 0) {
+		pr_err("%s, accel_gpio_init fail(err=%d)\n", __func__, ret);
+		return ret;
+	}
+	ret = gyro_gpio_init();
+	if (ret < 0) {
+		pr_err("%s, gyro_gpio_init(err=%d)\n", __func__, ret);
+		return ret;
+	}
+#elif defined(CONFIG_SENSORS_K3DH)
+	ret = accel_gpio_init();
+	if (ret < 0) {
+		pr_err("%s, accel_gpio_init fail(err=%d)\n", __func__, ret);
+		return ret;
+	}
+#endif
+	ret = i2c_add_devices(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
+	if (ret < 0) {
+		pr_err("%s, i2c1 adding i2c fail(err=%d)\n", __func__, ret);
+		return ret;
+	}
+
+	/* Optical Sensor */
+#if defined(CONFIG_SENSORS_GP2A) || defined(CONFIG_SENSORS_CM36651) || \
+	defined(CONFIG_SENSORS_CM3663)
+	ret = optical_gpio_init();
+	if (ret) {
+		pr_err("%s, optical_gpio_init(err=%d)\n", __func__, ret);
+		return ret;
+	}
+	ret = i2c_add_devices(9, i2c_devs9_emul, ARRAY_SIZE(i2c_devs9_emul));
+	if (ret < 0) {
+		pr_err("%s, i2c9 adding i2c fail(err=%d)\n", __func__, ret);
+		return ret;
+	}
+#elif defined(CONFIG_SENSORS_BH1721)
+	ret = i2c_add_devices(9, i2c_devs9_emul, ARRAY_SIZE(i2c_devs9_emul));
+	if (ret < 0) {
+		pr_err("%s, i2c9 adding i2c fail(err=%d)\n", __func__, ret);
+		return ret;
+	}
+#endif
+
+#if defined(CONFIG_SENSORS_GP2A)
+	ret = platform_device_register(&opt_gp2a);
+	if (ret < 0) {
+		pr_err("%s, failed to register opt_gp2a(err=%d)\n",
+			__func__, ret);
+		return ret;
+	}
+#endif
+
+	/* Magnetic Sensor */
+#ifdef CONFIG_SENSORS_AK8975C
+	ret = ak8975c_gpio_init();
+	if (ret < 0) {
+		pr_err("%s, ak8975c_gpio_init fail(err=%d)\n", __func__, ret);
+		return ret;
+	}
+	ret = i2c_add_devices(10, i2c_devs10_emul, ARRAY_SIZE(i2c_devs10_emul));
+	if (ret < 0) {
+		pr_err("%s, i2c10 adding i2c fail(err=%d)\n", __func__, ret);
+		return ret;
+	}
+#endif
+
+	/* Pressure Sensor */
+#ifdef CONFIG_SENSORS_LPS331
+	ret = lps331_gpio_init();
+	if (ret < 0) {
+		pr_err("%s, ak8975c_gpio_init fail(err=%d)\n", __func__, ret);
+		return ret;
+	}
+	ret = i2c_add_devices(11, i2c_devs11_emul, ARRAY_SIZE(i2c_devs11_emul));
+	if (ret < 0) {
+		pr_err("%s, i2c1 adding i2c fail(err=%d)\n", __func__, ret);
+		return ret;
+	}
+#endif
+	return ret;
+}
+module_init(midas_sensor_init);
diff --git a/arch/arm/mach-exynos/midas-sound.c b/arch/arm/mach-exynos/midas-sound.c
new file mode 100644
index 0000000..80d2d45
--- /dev/null
+++ b/arch/arm/mach-exynos/midas-sound.c
@@ -0,0 +1,365 @@
+/*
+ * midas-sound.c - Sound Management of MIDAS Project
+ *
+ *  Copyright (C) 2012 Samsung Electrnoics
+ *  JS Park <aitdark.park@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/i2c.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/i2c-gpio.h>
+#include <mach/irqs.h>
+#include <mach/pmu.h>
+#include <plat/iic.h>
+
+#include <plat/gpio-cfg.h>
+#ifdef CONFIG_ARCH_EXYNOS5
+#include <mach/gpio-p10.h>
+#else
+#include <mach/gpio-midas.h>
+#endif
+
+#ifdef CONFIG_SND_SOC_WM8994
+#include <linux/mfd/wm8994/pdata.h>
+#include <linux/mfd/wm8994/gpio.h>
+#endif
+
+#ifdef CONFIG_FM34_WE395
+#include <linux/i2c/fm34_we395.h>
+#endif
+
+#ifdef CONFIG_AUDIENCE_ES305
+#include <linux/i2c/es305.h>
+#endif
+
+static bool midas_snd_mclk_enabled;
+
+#ifdef CONFIG_ARCH_EXYNOS5
+#define I2C_NUM_2MIC	4
+#define I2C_NUM_CODEC	7
+#define SET_PLATDATA_2MIC(i2c_pd)	s3c_i2c4_set_platdata(i2c_pd)
+#define SET_PLATDATA_CODEC(i2c_pd)	s3c_i2c7_set_platdata(i2c_pd)
+#else /* for CONFIG_ARCH_EXYNOS4 */
+#define I2C_NUM_2MIC	6
+#define I2C_NUM_CODEC	4
+#define SET_PLATDATA_2MIC(i2c_pd)	s3c_i2c6_set_platdata(i2c_pd)
+#define SET_PLATDATA_CODEC(i2c_pd)	s3c_i2c4_set_platdata(i2c_pd)
+#endif
+
+static DEFINE_SPINLOCK(midas_snd_spinlock);
+
+void midas_snd_set_mclk(bool on, bool forced)
+{
+	static int use_cnt;
+
+	spin_lock(&midas_snd_spinlock);
+
+	midas_snd_mclk_enabled = on;
+
+	if (midas_snd_mclk_enabled) {
+		if (use_cnt++ == 0 || forced) {
+			printk(KERN_INFO "Sound: enabled mclk\n");
+#ifdef CONFIG_ARCH_EXYNOS5
+			exynos5_pmu_xclkout_set(midas_snd_mclk_enabled,
+							XCLKOUT_XXTI);
+#else /* for CONFIG_ARCH_EXYNOS4 */
+			exynos4_pmu_xclkout_set(midas_snd_mclk_enabled,
+							XCLKOUT_XUSBXTI);
+#endif
+			mdelay(10);
+		}
+	} else {
+		if ((--use_cnt <= 0) || forced) {
+			printk(KERN_INFO "Sound: disabled mclk\n");
+#ifdef CONFIG_ARCH_EXYNOS5
+			exynos5_pmu_xclkout_set(midas_snd_mclk_enabled,
+							XCLKOUT_XXTI);
+#else /* for CONFIG_ARCH_EXYNOS4 */
+			exynos4_pmu_xclkout_set(midas_snd_mclk_enabled,
+							XCLKOUT_XUSBXTI);
+#endif
+			use_cnt = 0;
+		}
+	}
+
+	spin_unlock(&midas_snd_spinlock);
+
+	printk(KERN_INFO "Sound: state: %d, use_cnt: %d\n",
+					midas_snd_mclk_enabled, use_cnt);
+}
+
+bool midas_snd_get_mclk(void)
+{
+	return midas_snd_mclk_enabled;
+}
+
+#ifdef CONFIG_SND_SOC_WM8994
+/* vbatt_devices */
+static struct regulator_consumer_supply vbatt_supplies[] = {
+	REGULATOR_SUPPLY("LDO1VDD", NULL),
+	REGULATOR_SUPPLY("SPKVDD1", NULL),
+	REGULATOR_SUPPLY("SPKVDD2", NULL),
+};
+
+static struct regulator_init_data vbatt_initdata = {
+	.constraints = {
+		.always_on = 1,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(vbatt_supplies),
+	.consumer_supplies = vbatt_supplies,
+};
+
+static struct fixed_voltage_config vbatt_config = {
+	.init_data = &vbatt_initdata,
+	.microvolts = 5000000,
+	.supply_name = "VBATT",
+	.gpio = -EINVAL,
+};
+
+struct platform_device vbatt_device = {
+	.name = "reg-fixed-voltage",
+	.id = -1,
+	.dev = {
+		.platform_data = &vbatt_config,
+	},
+};
+
+/* wm1811 ldo1 */
+static struct regulator_consumer_supply wm1811_ldo1_supplies[] = {
+	REGULATOR_SUPPLY("AVDD1", NULL),
+};
+
+static struct regulator_init_data wm1811_ldo1_initdata = {
+	.constraints = {
+		.name = "WM1811 LDO1",
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(wm1811_ldo1_supplies),
+	.consumer_supplies = wm1811_ldo1_supplies,
+};
+
+/* wm1811 ldo2 */
+static struct regulator_consumer_supply wm1811_ldo2_supplies[] = {
+	REGULATOR_SUPPLY("DCVDD", NULL),
+};
+
+static struct regulator_init_data wm1811_ldo2_initdata = {
+	.constraints = {
+		.name = "WM1811 LDO2",
+		.always_on = true, /* Actually status changed by LDO1 */
+	},
+	.num_consumer_supplies = ARRAY_SIZE(wm1811_ldo2_supplies),
+	.consumer_supplies = wm1811_ldo2_supplies,
+};
+
+static struct wm8994_drc_cfg drc_value[] = {
+	{
+		.name = "voice call DRC",
+		.regs[0] = 0x009B,
+		.regs[1] = 0x0844,
+		.regs[2] = 0x00E8,
+		.regs[3] = 0x0210,
+		.regs[4] = 0x0000,
+	},
+#if defined(CONFIG_MACH_C1_KOR_LGT)
+	{
+		.name = "voice call DRC",
+		.regs[0] = 0x008c,
+		.regs[1] = 0x0253,
+		.regs[2] = 0x0028,
+		.regs[3] = 0x028a,
+		.regs[4] = 0x0000,
+	},
+#endif
+};
+
+static struct wm8994_pdata wm1811_pdata = {
+	.gpio_defaults = {
+		[0] = WM8994_GP_FN_IRQ,	  /* GPIO1 IRQ output, CMOS mode */
+		[7] = WM8994_GPN_DIR | WM8994_GP_FN_PIN_SPECIFIC, /* DACDAT3 */
+		[8] = WM8994_CONFIGURE_GPIO |
+		      WM8994_GP_FN_PIN_SPECIFIC, /* ADCDAT3 */
+		[9] = WM8994_CONFIGURE_GPIO |\
+		      WM8994_GP_FN_PIN_SPECIFIC, /* LRCLK3 */
+		[10] = WM8994_CONFIGURE_GPIO |\
+		       WM8994_GP_FN_PIN_SPECIFIC, /* BCLK3 */
+	},
+
+	.irq_base = IRQ_BOARD_CODEC_START,
+
+	/* The enable is shared but assign it to LDO1 for software */
+	.ldo = {
+		{
+			.enable = GPIO_WM8994_LDO,
+			.init_data = &wm1811_ldo1_initdata,
+		},
+		{
+			.init_data = &wm1811_ldo2_initdata,
+		},
+	},
+	/* Apply DRC Value */
+	.drc_cfgs = drc_value,
+	.num_drc_cfgs = ARRAY_SIZE(drc_value),
+
+	/* Support external capacitors*/
+	.jd_ext_cap = 1,
+
+	/* Regulated mode at highest output voltage */
+	.micbias = {0x2f, 0x27},
+
+	.micd_lvl_sel = 0xFF,
+
+	.ldo_ena_always_driven = true,
+	.ldo_ena_delay = 30000,
+#ifdef CONFIG_TARGET_LOCALE_KOR
+	.lineout2_diff = 0,
+#endif
+#ifdef CONFIG_MACH_C1
+	.lineout1fb = 0,
+#else
+	.lineout1fb = 1,
+#endif
+#if defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_C1_KOR_SKT) || \
+	defined(CONFIG_MACH_C1_KOR_KT) || defined(CONFIG_MACH_C1_KOR_LGT) || \
+	defined(CONFIG_MACH_P4NOTE) || defined(CONFIG_MACH_GC1)
+	.lineout2fb = 0,
+#else
+	.lineout2fb = 1,
+#endif
+};
+
+static struct i2c_board_info i2c_wm1811[] __initdata = {
+	{
+		I2C_BOARD_INFO("wm1811", (0x34 >> 1)),	/* Audio CODEC */
+		.platform_data = &wm1811_pdata,
+		.irq = IRQ_EINT(30),
+	},
+};
+
+#endif
+
+#ifdef CONFIG_FM34_WE395
+static struct fm34_platform_data fm34_we395_pdata = {
+	.gpio_pwdn = GPIO_FM34_PWDN,
+	.gpio_rst = GPIO_FM34_RESET,
+	.gpio_bp = GPIO_FM34_BYPASS,
+	.set_mclk = midas_snd_set_mclk,
+};
+#ifdef CONFIG_MACH_C1_KOR_LGT
+static struct fm34_platform_data fm34_we395_pdata_rev05 = {
+	.gpio_pwdn = GPIO_FM34_PWDN,
+	.gpio_rst = GPIO_FM34_RESET_05,
+	.gpio_bp = GPIO_FM34_BYPASS_05,
+	.set_mclk = midas_snd_set_mclk,
+};
+#endif
+static struct i2c_board_info i2c_2mic[] __initdata = {
+	{
+		I2C_BOARD_INFO("fm34_we395", (0xC0 >> 1)), /* 2MIC */
+		.platform_data = &fm34_we395_pdata,
+	},
+};
+
+#if defined(CONFIG_MACH_C1_KOR_LGT) || defined(CONFIG_MACH_C1VZW)
+static struct i2c_gpio_platform_data gpio_i2c_fm34 = {
+	.sda_pin = GPIO_FM34_SDA,
+	.scl_pin = GPIO_FM34_SCL,
+};
+
+struct platform_device s3c_device_fm34 = {
+	.name = "i2c-gpio",
+	.id = I2C_NUM_2MIC,
+	.dev.platform_data = &gpio_i2c_fm34,
+};
+#endif
+#endif
+
+#ifdef CONFIG_AUDIENCE_ES305
+static struct es305_platform_data es305_pdata = {
+	.gpio_wakeup = GPIO_ES305_WAKEUP,
+	.gpio_reset = GPIO_ES305_RESET,
+	.set_mclk = midas_snd_set_mclk,
+};
+
+static struct i2c_board_info i2c_2mic[] __initdata = {
+	{
+		I2C_BOARD_INFO("audience_es305", 0x3E), /* 2MIC */
+		.platform_data = &es305_pdata,
+	},
+};
+#endif
+
+static struct platform_device *midas_sound_devices[] __initdata = {
+#if defined(CONFIG_MACH_C1_KOR_LGT) || defined(CONFIG_MACH_C1VZW)
+#ifdef CONFIG_FM34_WE395
+	&s3c_device_fm34,
+#endif
+#endif
+};
+
+void __init midas_sound_init(void)
+{
+	printk(KERN_INFO "Sound: start %s\n", __func__);
+
+	platform_add_devices(midas_sound_devices,
+		ARRAY_SIZE(midas_sound_devices));
+
+#ifdef CONFIG_ARCH_EXYNOS5
+#ifndef CONFIG_MACH_P10_LTE_00_BD
+	i2c_wm1811[0].irq = IRQ_EINT(29);
+#endif
+	SET_PLATDATA_CODEC(NULL);
+	i2c_register_board_info(I2C_NUM_CODEC, i2c_wm1811,
+					ARRAY_SIZE(i2c_wm1811));
+#else /* for CONFIG_ARCH_EXYNOS4 */
+#ifdef CONFIG_MACH_P4NOTE
+	i2c_wm1811[0].irq = 0;
+	SET_PLATDATA_CODEC(NULL);
+	i2c_register_board_info(I2C_NUM_CODEC, i2c_wm1811,
+					ARRAY_SIZE(i2c_wm1811));
+
+#else
+	if (system_rev != 3 && system_rev >= 0) {
+		SET_PLATDATA_CODEC(NULL);
+		i2c_register_board_info(I2C_NUM_CODEC, i2c_wm1811,
+						ARRAY_SIZE(i2c_wm1811));
+	}
+#endif
+#endif/* CONFIG_ARCH_EXYNOS5 */
+
+#ifdef CONFIG_FM34_WE395
+	midas_snd_set_mclk(true, false);
+	SET_PLATDATA_2MIC(NULL);
+
+#if defined(CONFIG_MACH_C1_KOR_LGT)
+	if (system_rev > 5)
+		i2c_2mic[0].platform_data = &fm34_we395_pdata_rev05;
+#endif
+
+	i2c_register_board_info(I2C_NUM_2MIC, i2c_2mic, ARRAY_SIZE(i2c_2mic));
+#endif
+
+
+#ifdef CONFIG_AUDIENCE_ES305
+	midas_snd_set_mclk(true, false);
+	SET_PLATDATA_2MIC(NULL);
+	i2c_register_board_info(I2C_NUM_2MIC, i2c_2mic, ARRAY_SIZE(i2c_2mic));
+#endif
+}
diff --git a/arch/arm/mach-exynos/midas-thermistor.c b/arch/arm/mach-exynos/midas-thermistor.c
new file mode 100644
index 0000000..999a56e
--- /dev/null
+++ b/arch/arm/mach-exynos/midas-thermistor.c
@@ -0,0 +1,600 @@
+/*
+ * midas-thermistor.c - thermistor of MIDAS Project
+ *
+ * Copyright (C) 2011 Samsung Electrnoics
+ * SangYoung Son <hello.son@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <mach/midas-thermistor.h>
+#ifdef CONFIG_SEC_THERMISTOR
+#include <mach/sec_thermistor.h>
+#endif
+
+#ifdef CONFIG_S3C_ADC
+#if defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_P4NOTE)
+static struct adc_table_data ap_adc_temper_table_battery[] = {
+	{  204,	 800 },
+	{  210,	 790 },
+	{  216,	 780 },
+	{  223,	 770 },
+	{  230,	 760 },
+	{  237,	 750 },
+	{  244,	 740 },
+	{  252,	 730 },
+	{  260,	 720 },
+	{  268,	 710 },
+	{  276,	 700 },
+	{  285,	 690 },
+	{  294,	 680 },
+	{  303,	 670 },
+	{  312,	 660 },
+	{  322,	 650 },
+	{  332,	 640 },
+	{  342,	 630 },
+	{  353,	 620 },
+	{  364,	 610 },
+	{  375,	 600 },
+	{  387,	 590 },
+	{  399,	 580 },
+	{  411,	 570 },
+	{  423,	 560 },
+	{  436,	 550 },
+	{  450,	 540 },
+	{  463,	 530 },
+	{  477,	 520 },
+	{  492,	 510 },
+	{  507,	 500 },
+	{  522,	 490 },
+	{  537,	 480 },
+	{  553,	 470 },
+	{  569,	 460 },
+	{  586,	 450 },
+	{  603,	 440 },
+	{  621,	 430 },
+	{  638,	 420 },
+	{  657,	 410 },
+	{  675,	 400 },
+	{  694,	 390 },
+	{  713,	 380 },
+	{  733,	 370 },
+	{  753,	 360 },
+	{  773,	 350 },
+	{  794,	 340 },
+	{  815,	 330 },
+	{  836,	 320 },
+	{  858,	 310 },
+	{  880,	 300 },
+	{  902,	 290 },
+	{  924,	 280 },
+	{  947,	 270 },
+	{  969,	 260 },
+	{  992,	 250 },
+	{ 1015,	 240 },
+	{ 1039,	 230 },
+	{ 1062,	 220 },
+	{ 1086,	 210 },
+	{ 1109,	 200 },
+	{ 1133,	 190 },
+	{ 1156,	 180 },
+	{ 1180,	 170 },
+	{ 1204,	 160 },
+	{ 1227,	 150 },
+	{ 1250,	 140 },
+	{ 1274,	 130 },
+	{ 1297,	 120 },
+	{ 1320,	 110 },
+	{ 1343,	 100 },
+	{ 1366,	  90 },
+	{ 1388,	  80 },
+	{ 1410,	  70 },
+	{ 1432,	  60 },
+	{ 1454,	  50 },
+	{ 1475,	  40 },
+	{ 1496,	  30 },
+	{ 1516,	  20 },
+	{ 1536,	  10 },
+	{ 1556,	   0 },
+	{ 1576,	 -10 },
+	{ 1595,	 -20 },
+	{ 1613,	 -30 },
+	{ 1631,	 -40 },
+	{ 1649,	 -50 },
+	{ 1666,	 -60 },
+	{ 1683,	 -70 },
+	{ 1699,  -80 },
+	{ 1714,  -90 },
+	{ 1730, -100 },
+	{ 1744, -110 },
+	{ 1759, -120 },
+	{ 1773, -130 },
+	{ 1786, -140 },
+	{ 1799, -150 },
+	{ 1811, -160 },
+	{ 1823, -170 },
+	{ 1835, -180 },
+	{ 1846, -190 },
+	{ 1856, -200 },
+};
+#elif defined(CONFIG_MACH_C1)
+#if defined(CONFIG_TARGET_LOCALE_KOR)
+static struct adc_table_data ap_adc_temper_table_battery[] = {
+	{  178,	 800 },
+	{  186,	 790 },
+	{  193,	 780 },
+	{  198,	 770 },
+	{  204,	 760 },
+	{  210,	 750 },
+	{  220,	 740 },
+	{  226,	 730 },
+	{  232,	 720 },
+	{  247,	 710 },
+	{  254,	 700 },
+	{  261,	 690 },
+	{  270,	 680 },
+	{  278,	 670 },
+	{  285,	 660 },
+	{  292,	 650 },
+	{  304,	 640 },
+	{  319,	 630 },
+	{  325,	 620 },
+	{  331,	 610 },
+	{  343,	 600 },
+	{  354,	 590 },
+	{  373,	 580 },
+	{  387,	 570 },
+	{  392,	 560 },
+	{  408,	 550 },
+	{  422,	 540 },
+	{  433,	 530 },
+	{  452,	 520 },
+	{  466,	 510 },
+	{  479,	 500 },
+	{  497,	 490 },
+	{  510,	 480 },
+	{  529,	 470 },
+	{  545,	 460 },
+	{  562,	 450 },
+	{  578,	 440 },
+	{  594,	 430 },
+	{  620,	 420 },
+	{  632,	 410 },
+	{  651,	 400 },
+	{  663,	 390 },
+	{  681,	 380 },
+	{  705,	 370 },
+	{  727,	 360 },
+	{  736,	 350 },
+	{  778,	 340 },
+	{  793,	 330 },
+	{  820,	 320 },
+	{  834,	 310 },
+	{  859,	 300 },
+	{  872,	 290 },
+	{  891,	 280 },
+	{  914,	 270 },
+	{  939,	 260 },
+	{  951,	 250 },
+	{  967,	 240 },
+	{  999,	 230 },
+	{ 1031,	 220 },
+	{ 1049,	 210 },
+	{ 1073,	 200 },
+	{ 1097,	 190 },
+	{ 1128,	 180 },
+	{ 1140,	 170 },
+	{ 1171,	 160 },
+	{ 1188,	 150 },
+	{ 1198,	 140 },
+	{ 1223,	 130 },
+	{ 1236,	 120 },
+	{ 1274,	 110 },
+	{ 1290,	 100 },
+	{ 1312,	  90 },
+	{ 1321,	  80 },
+	{ 1353,	  70 },
+	{ 1363,	  60 },
+	{ 1404,	  50 },
+	{ 1413,	  40 },
+	{ 1444,	  30 },
+	{ 1461,	  20 },
+	{ 1470,	  10 },
+	{ 1516,	   0 },
+	{ 1522,	 -10 },
+	{ 1533,	 -20 },
+	{ 1540,	 -30 },
+	{ 1558,	 -40 },
+	{ 1581,	 -50 },
+	{ 1595,	 -60 },
+	{ 1607,	 -70 },
+	{ 1614,  -80 },
+	{ 1627,  -90 },
+	{ 1655, -100 },
+	{ 1664, -110 },
+	{ 1670, -120 },
+	{ 1676, -130 },
+	{ 1692, -140 },
+	{ 1713, -150 },
+	{ 1734, -160 },
+	{ 1746, -170 },
+	{ 1789, -180 },
+	{ 1805, -190 },
+	{ 1824, -200 },
+};
+#else
+static struct adc_table_data ap_adc_temper_table_battery[] = {
+	{ 305,  650 },
+	{ 566,  430 },
+	{ 1494,   0 },
+	{ 1571, -50 },
+};
+#endif
+#elif defined(CONFIG_MACH_S2PLUS)
+static struct adc_table_data ap_adc_temper_table_battery[] = {
+	{ 305,  650 },
+	{ 566,  430 },
+	{ 1494,   0 },
+	{ 1571, -50 },
+};
+#else	/* sample */
+static struct adc_table_data ap_adc_temper_table_battery[] = {
+	{ 305,  650 },
+	{ 566,  430 },
+	{ 1494,   0 },
+	{ 1571, -50 },
+};
+#endif
+
+int convert_adc(int adc_data, int channel)
+{
+	int adc_value;
+	int low, mid, high;
+	struct adc_table_data *temper_table = NULL;
+	pr_debug("%s\n", __func__);
+
+	low = mid = high = 0;
+	switch (channel) {
+	case 1:
+		temper_table = ap_adc_temper_table_battery;
+		high = ARRAY_SIZE(ap_adc_temper_table_battery) - 1;
+		break;
+	case 2:
+		temper_table = ap_adc_temper_table_battery;
+		high = ARRAY_SIZE(ap_adc_temper_table_battery) - 1;
+		break;
+	default:
+		pr_info("%s: not exist temper table for ch(%d)\n", __func__,
+							channel);
+		return -EINVAL;
+		break;
+	}
+
+	/* Out of table range */
+	if (adc_data <= temper_table[low].adc) {
+		adc_value = temper_table[low].value;
+		return adc_value;
+	} else if (adc_data >= temper_table[high].adc) {
+		adc_value = temper_table[high].value;
+		return adc_value;
+	}
+
+	while (low <= high) {
+		mid = (low + high) / 2;
+		if (temper_table[mid].adc > adc_data)
+			high = mid - 1;
+		else if (temper_table[mid].adc < adc_data)
+			low = mid + 1;
+		else
+			break;
+	}
+	adc_value = temper_table[mid].value;
+
+	/* high resolution */
+	if (adc_data < temper_table[mid].adc)
+		adc_value = temper_table[mid].value +
+			((temper_table[mid-1].value - temper_table[mid].value) *
+			(temper_table[mid].adc - adc_data) /
+			(temper_table[mid].adc - temper_table[mid-1].adc));
+	else
+		adc_value = temper_table[mid].value -
+			((temper_table[mid].value - temper_table[mid+1].value) *
+			(adc_data - temper_table[mid].adc) /
+			(temper_table[mid+1].adc - temper_table[mid].adc));
+
+	pr_debug("%s: adc data(%d), adc value(%d)\n", __func__,
+					adc_data, adc_value);
+	return adc_value;
+
+}
+#endif
+
+#ifdef CONFIG_SEC_THERMISTOR
+static struct sec_therm_adc_table temper_table_ap[] = {
+	{196,	700},
+	{211,	690},
+	{242,	685},
+	{249,	680},
+	{262,	670},
+	{275,	660},
+	{288,	650},
+	{301,	640},
+	{314,	630},
+	{328,	620},
+	{341,	610},
+	{354,	600},
+	{366,	590},
+	{377,	580},
+	{389,	570},
+	{404,	560},
+	{419,	550},
+	{434,	540},
+	{452,	530},
+	{469,	520},
+	{487,	510},
+	{498,	500},
+	{509,	490},
+	{520,	480},
+	{529,	460},
+	{538,	470},
+	{547,	450},
+	{556,	440},
+	{564,	430},
+	{573,	420},
+	{581,	410},
+	{590,	400},
+	{615,	390},
+	{640,	380},
+	{665,	370},
+	{690,	360},
+	{715,	350},
+	{736,	340},
+	{758,	330},
+	{779,	320},
+	{801,	310},
+	{822,	300},
+};
+
+/* when the next level is same as prev, returns -1 */
+static int get_midas_siop_level(int temp)
+{
+	static int prev_temp = 400;
+	static int prev_level = 0;
+	int level = -1;
+
+#if defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT) || \
+	defined(CONFIG_MACH_C1_KOR_LGT)
+	if (temp > prev_temp) {
+		if (temp >= 490)
+			level = 4;
+		else if (temp >= 480)
+			level = 3;
+		else if (temp >= 450)
+			level = 2;
+		else if (temp >= 420)
+			level = 1;
+		else
+			level = 0;
+	} else {
+		if (temp < 400)
+			level = 0;
+		else if (temp < 420)
+			level = 1;
+		else if (temp < 450)
+			level = 2;
+		else if (temp < 480)
+			level = 3;
+		else
+			level = 4;
+
+		if (level > prev_level)
+			level = prev_level;
+	}
+#elif defined(CONFIG_MACH_P4NOTE)
+	if (temp > prev_temp) {
+		if (temp >= 620)
+			level = 4;
+		else if (temp >= 610)
+			level = 3;
+		else if (temp >= 580)
+			level = 2;
+		else if (temp >= 550)
+			level = 1;
+		else
+			level = 0;
+	} else {
+		if (temp < 520)
+			level = 0;
+		else if (temp < 550)
+			level = 1;
+		else if (temp < 580)
+			level = 2;
+		else if (temp < 610)
+			level = 3;
+		else
+			level = 4;
+
+		if (level > prev_level)
+			level = prev_level;
+	}
+#else
+	if (temp > prev_temp) {
+		if (temp >= 540)
+			level = 4;
+		else if (temp >= 530)
+			level = 3;
+		else if (temp >= 480)
+			level = 2;
+		else if (temp >= 440)
+			level = 1;
+		else
+			level = 0;
+	} else {
+		if (temp < 410)
+			level = 0;
+		else if (temp < 440)
+			level = 1;
+		else if (temp < 480)
+			level = 2;
+		else if (temp < 530)
+			level = 3;
+		else
+			level = 4;
+
+		if (level > prev_level)
+			level = prev_level;
+	}
+#endif
+
+	prev_temp = temp;
+	if (prev_level == level)
+		return -1;
+
+	prev_level = level;
+
+	return level;
+}
+
+static struct sec_therm_platform_data sec_therm_pdata = {
+	.adc_channel	= 1,
+	.adc_arr_size	= ARRAY_SIZE(temper_table_ap),
+	.adc_table	= temper_table_ap,
+	.polling_interval = 30 * 1000, /* msecs */
+	.get_siop_level = get_midas_siop_level,
+};
+
+struct platform_device sec_device_thermistor = {
+	.name = "sec-thermistor",
+	.id = -1,
+	.dev.platform_data = &sec_therm_pdata,
+};
+#endif
+
+#ifdef CONFIG_STMPE811_ADC
+/* temperature table for ADC ch7 */
+static struct adc_table_data temper_table_battery[] = {
+	{	1856, -20	},
+	{	1846, -19	},
+	{	1835, -18	},
+	{	1823, -17	},
+	{	1811, -16	},
+	{	1799, -15	},
+	{	1786, -14	},
+	{	1773, -13	},
+	{	1759, -12	},
+	{	1744, -11	},
+	{	1730, -10	},
+	{	1714, -9	},
+	{	1699, -8	},
+	{	1683, -7	},
+	{	1666, -6	},
+	{	1649, -5	},
+	{	1631, -4	},
+	{	1613, -3	},
+	{	1595, -2	},
+	{	1576, -1	},
+	{	1556, 0		},
+	{	1536, 1		},
+	{	1516, 2		},
+	{	1496, 3		},
+	{	1475, 4		},
+	{	1454, 5		},
+	{	1432, 6		},
+	{	1410, 7		},
+	{	1388, 8		},
+	{	1366, 9		},
+	{	1343, 10	},
+	{	1320, 11	},
+	{	1297, 12	},
+	{	1274, 13	},
+	{	1250, 14	},
+	{	1227, 15	},
+	{	1204, 16	},
+	{	1180, 17	},
+	{	1156, 18	},
+	{	1133, 19	},
+	{	1109, 20	},
+	{	1086, 21	},
+	{	1062, 22	},
+	{	1039, 23	},
+	{	1015, 24	},
+	{	992,  25	},
+	{	969,  26	},
+	{	947,  27	},
+	{	924,  28	},
+	{	902,  29	},
+	{	880,  30	},
+	{	858,  31	},
+	{	836,  32	},
+	{	815,  33	},
+	{	794,  34	},
+	{	773,  35	},
+	{	753,  36	},
+	{	733,  37	},
+	{	713,  38	},
+	{	694,  39	},
+	{	675,  40	},
+	{	657,  41	},
+	{	638,  42	},
+	{	621,  43	},
+	{	603,  44	},
+	{	586,  45	},
+	{	569,  46	},
+	{	553,  47	},
+	{	537,  48	},
+	{	522,  49	},
+	{	507,  50	},
+	{	492,  51	},
+	{	477,  52	},
+	{	463,  53	},
+	{	450,  54	},
+	{	436,  55	},
+	{	423,  56	},
+	{	411,  57	},
+	{	399,  58	},
+	{	387,  59	},
+	{	375,  60	},
+	{	364,  61	},
+	{	353,  62	},
+	{	342,  63	},
+	{	332,  64	},
+	{	322,  65	},
+	{	312,  66	},
+	{	303,  67	},
+	{	294,  68	},
+	{	285,  69	},
+	{	276,  70	},
+	{	268,  71	},
+	{	260,  72	},
+	{	252,  73	},
+	{	244,  74	},
+	{	237,  75	},
+	{	230,  76	},
+	{	223,  77	},
+	{	216,  78	},
+	{	210,  79	},
+	{	204,  80	},
+};
+
+struct stmpe811_platform_data stmpe811_pdata = {
+	.adc_table_ch4 = temper_table_battery,
+	.table_size_ch4 = ARRAY_SIZE(temper_table_battery),
+	.adc_table_ch7 = temper_table_battery,
+	.table_size_ch7 = ARRAY_SIZE(temper_table_battery),
+
+	.irq_gpio = GPIO_ADC_INT,
+};
+#endif
+
diff --git a/arch/arm/mach-exynos/midas-tsp.c b/arch/arm/mach-exynos/midas-tsp.c
new file mode 100644
index 0000000..e3361c6
--- /dev/null
+++ b/arch/arm/mach-exynos/midas-tsp.c
@@ -0,0 +1,1095 @@
+/*
+ * linux/arch/arm/mach-exynos/midas-tsp.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/i2c.h>
+
+#include <linux/err.h>
+#include <linux/gpio.h>
+#if defined(CONFIG_TOUCHSCREEN_ATMEL_MXT224_U1)
+#include <linux/delay.h>
+#include <linux/i2c/mxt224_u1.h>
+#elif defined(CONFIG_TOUCHSCREEN_MELFAS_GC)
+#include <linux/platform_data/mms_ts_gc.h>
+#else
+#include <linux/platform_data/mms_ts.h>
+#endif
+#include <linux/regulator/consumer.h>
+#include <plat/gpio-cfg.h>
+
+#ifdef CONFIG_CPU_FREQ_GOV_ONDEMAND_FLEXRATE
+#include <linux/cpufreq.h>
+#endif
+
+#if defined(CONFIG_TOUCHSCREEN_ATMEL_MXT224_U1)
+/* mxt224 TSP */
+extern bool is_cable_attached;
+
+static struct charging_status_callbacks {
+	void (*tsp_set_charging_cable) (int type);
+} charging_cbs;
+
+void tsp_register_callback(void *function)
+{
+	charging_cbs.tsp_set_charging_cable = function;
+}
+
+void tsp_read_ta_status(void *ta_status)
+{
+	*(bool *) ta_status = is_cable_attached;
+}
+
+static void mxt224_power_on(void)
+{
+	struct regulator *regulator;
+
+	regulator = regulator_get(NULL, "touch");
+	if (IS_ERR(regulator))
+		return;
+
+	regulator_enable(regulator);
+	printk(KERN_INFO "[TSP] melfas power on\n");
+
+	regulator_put(regulator);
+
+	mdelay(70);
+	s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_NONE);
+	s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_SFN(0xf));
+	mdelay(40);
+	printk(KERN_INFO "mxt224_power_on is finished\n");
+}
+
+EXPORT_SYMBOL(mxt224_power_on);
+
+static void mxt224_power_off(void)
+{
+	struct regulator *regulator;
+
+	s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_DOWN);
+
+	regulator = regulator_get(NULL, "touch");
+	if (IS_ERR(regulator))
+		return;
+
+	regulator_disable(regulator);
+
+	regulator_put(regulator);
+
+	printk(KERN_INFO "mxt224_power_off is finished\n");
+}
+
+EXPORT_SYMBOL(mxt224_power_off);
+
+/*
+  Configuration for MXT224
+*/
+#define MXT224_THRESHOLD_BATT		40
+#define MXT224_THRESHOLD_BATT_INIT		55
+#define MXT224_THRESHOLD_CHRG		70
+#define MXT224_NOISE_THRESHOLD_BATT		30
+#define MXT224_NOISE_THRESHOLD_CHRG		40
+#define MXT224_MOVFILTER_BATT		11
+#define MXT224_MOVFILTER_CHRG		46
+#define MXT224_ATCHCALST		9
+#define MXT224_ATCHCALTHR		30
+
+static u8 t7_config[] = { GEN_POWERCONFIG_T7,
+	48,			/* IDLEACQINT */
+	255,			/* ACTVACQINT */
+	25			/* ACTV2IDLETO: 25 * 200ms = 5s */
+};
+
+static u8 t8_config[] = { GEN_ACQUISITIONCONFIG_T8,
+	10, 0, 5, 1, 0, 0, MXT224_ATCHCALST, MXT224_ATCHCALTHR
+};				/*byte 3: 0 */
+
+static u8 t9_config[] = { TOUCH_MULTITOUCHSCREEN_T9,
+	131, 0, 0, 19, 11, 0, 32, MXT224_THRESHOLD_BATT, 2, 1,
+	0,
+	15,			/* MOVHYSTI */
+	1, MXT224_MOVFILTER_BATT, MXT224_MAX_MT_FINGERS, 5, 40, 10, 31, 3,
+	223, 1, 0, 0, 0, 0, 143, 55, 143, 90, 18
+};
+
+static u8 t18_config[] = { SPT_COMCONFIG_T18,
+	0, 1
+};
+
+static u8 t20_config[] = { PROCI_GRIPFACESUPPRESSION_T20,
+	7, 0, 0, 0, 0, 0, 0, 30, 20, 4, 15, 10
+};
+
+static u8 t22_config[] = { PROCG_NOISESUPPRESSION_T22,
+	143, 0, 0, 0, 0, 0, 0, 3, MXT224_NOISE_THRESHOLD_BATT, 0, 0, 29, 34, 39,
+	49, 58, 3
+};
+
+static u8 t28_config[] = { SPT_CTECONFIG_T28,
+	0, 0, 3, 16, 19, 60
+};
+static u8 end_config[] = { RESERVED_T255 };
+
+static const u8 *mxt224_config[] = {
+	t7_config,
+	t8_config,
+	t9_config,
+	t18_config,
+	t20_config,
+	t22_config,
+	t28_config,
+	end_config,
+};
+
+/*
+  Configuration for MXT224-E
+*/
+#define MXT224E_THRESHOLD_BATT		50
+#define MXT224E_THRESHOLD_CHRG		40
+#define MXT224E_CALCFG_BATT		0x42
+#define MXT224E_CALCFG_CHRG		0x52
+#define MXT224E_ATCHFRCCALTHR_NORMAL		40
+#define MXT224E_ATCHFRCCALRATIO_NORMAL		55
+#define MXT224E_GHRGTIME_BATT		27
+#define MXT224E_GHRGTIME_CHRG		22
+#define MXT224E_ATCHCALST		4
+#define MXT224E_ATCHCALTHR		35
+#define MXT224E_BLEN_BATT		32
+#define MXT224E_BLEN_CHRG		16
+#define MXT224E_MOVFILTER_BATT		46
+#define MXT224E_MOVFILTER_CHRG		46
+#define MXT224E_ACTVSYNCSPERX_NORMAL		32
+#define MXT224E_NEXTTCHDI_NORMAL		0
+
+#if defined(CONFIG_TARGET_LOCALE_NAATT)
+static u8 t7_config_e[] = { GEN_POWERCONFIG_T7,
+	48, 255, 25
+};
+
+static u8 t8_config_e[] = { GEN_ACQUISITIONCONFIG_T8,
+	27, 0, 5, 1, 0, 0, 8, 8, 8, 180
+};
+
+/* MXT224E_0V5_CONFIG */
+/* NEXTTCHDI added */
+static u8 t9_config_e[] = { TOUCH_MULTITOUCHSCREEN_T9,
+	139, 0, 0, 19, 11, 0, 32, 50, 2, 1,
+	10, 3, 1, 11, MXT224_MAX_MT_FINGERS, 5, 40, 10, 31, 3,
+	223, 1, 10, 10, 10, 10, 143, 40, 143, 80,
+	18, 15, 50, 50, 2
+};
+
+static u8 t15_config_e[] = { TOUCH_KEYARRAY_T15,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t18_config_e[] = { SPT_COMCONFIG_T18,
+	0, 0
+};
+
+static u8 t23_config_e[] = { TOUCH_PROXIMITY_T23,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t25_config_e[] = { SPT_SELFTEST_T25,
+	0, 0, 188, 52, 124, 21, 188, 52, 124, 21, 0, 0, 0, 0
+};
+
+static u8 t40_config_e[] = { PROCI_GRIPSUPPRESSION_T40,
+	0, 0, 0, 0, 0
+};
+
+static u8 t42_config_e[] = { PROCI_TOUCHSUPPRESSION_T42,
+	0, 32, 120, 100, 0, 0, 0, 0
+};
+
+static u8 t46_config_e[] = { SPT_CTECONFIG_T46,
+	0, 3, 16, 35, 0, 0, 1, 0
+};
+
+static u8 t47_config_e[] = { PROCI_STYLUS_T47,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*MXT224E_0V5_CONFIG */
+static u8 t48_config_e[] = { PROCG_NOISESUPPRESSION_T48,
+	3, 4, 72, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	6, 6, 0, 0, 100, 4, 64, 10, 0, 20, 5, 0, 38, 0, 5,
+	0, 0, 0, 0, 0, 0, 32, 50, 2, 3, 1, 11, 10, 5, 40, 10, 10,
+	10, 10, 143, 40, 143, 80, 18, 15, 2
+};
+
+static u8 t48_config_chrg_e[] = { PROCG_NOISESUPPRESSION_T48,
+	1, 4, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	6, 6, 0, 0, 100, 4, 64, 10, 0, 20, 5, 0, 38, 0, 20,
+	0, 0, 0, 0, 0, 0, 16, 70, 2, 5, 2, 46, 10, 5, 40, 10, 0,
+	10, 10, 143, 40, 143, 80, 18, 15, 2
+};
+
+#elif defined(CONFIG_MACH_U1_NA_SPR_EPIC2_REV00)
+static u8 t7_config_e[] = { GEN_POWERCONFIG_T7,
+	48, 255, 15
+};
+
+static u8 t8_config_e[] = { GEN_ACQUISITIONCONFIG_T8,
+	27, 0, 5, 1, 0, 0, 4, 35, 40, 55
+};
+
+static u8 t9_config_e[] = { TOUCH_MULTITOUCHSCREEN_T9,
+	131, 0, 0, 19, 11, 0, 32, 50, 2, 7,
+	10, 3, 1, 46, MXT224_MAX_MT_FINGERS, 5, 40, 10, 31, 3,
+	223, 1, 10, 10, 10, 10, 143, 40, 143, 80,
+	18, 15, 50, 50, 2
+};
+
+static u8 t15_config_e[] = { TOUCH_KEYARRAY_T15,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t18_config_e[] = { SPT_COMCONFIG_T18,
+	0, 0
+};
+
+static u8 t23_config_e[] = { TOUCH_PROXIMITY_T23,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t25_config_e[] = { SPT_SELFTEST_T25,
+	0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t40_config_e[] = { PROCI_GRIPSUPPRESSION_T40,
+	0, 0, 0, 0, 0
+};
+
+static u8 t42_config_e[] = { PROCI_TOUCHSUPPRESSION_T42,
+	0, 32, 120, 100, 0, 0, 0, 0
+};
+
+static u8 t46_config_e[] = { SPT_CTECONFIG_T46,
+	0, 3, 16, 48, 0, 0, 1, 0, 0
+};
+
+static u8 t47_config_e[] = { PROCI_STYLUS_T47,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t48_config_e[] = { PROCG_NOISESUPPRESSION_T48,
+	3, 4, 64, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 6, 6, 0, 0, 100, 4, 64,
+	10, 0, 20, 5, 0, 38, 0, 5, 0, 0,
+	0, 0, 0, 0, 32, 50, 2, 3, 1, 46,
+	10, 5, 40, 10, 10, 10, 10, 143, 40, 143,
+	80, 18, 15, 2
+};
+
+static u8 t48_config_chrg_e[] = { PROCG_NOISESUPPRESSION_T48,
+	1, 4, 80, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 6, 6, 0, 0, 100, 4, 64,
+	10, 0, 20, 5, 0, 38, 0, 20, 0, 0,
+	0, 0, 0, 0, 16, 70, 2, 5, 2, 46,
+	10, 5, 40, 10, 0, 10, 10, 143, 40, 143,
+	80, 18, 15, 2
+};
+#else
+
+static u8 t7_config_e[] = { GEN_POWERCONFIG_T7,
+	48,			/* IDLEACQINT */
+	255,			/* ACTVACQINT */
+	25			/* ACTV2IDLETO: 25 * 200ms = 5s */
+};
+
+static u8 t8_config_e[] = { GEN_ACQUISITIONCONFIG_T8,
+	MXT224E_GHRGTIME_BATT, 0, 5, 1, 0, 0,
+	MXT224E_ATCHCALST, MXT224E_ATCHCALTHR,
+	MXT224E_ATCHFRCCALTHR_NORMAL,
+	MXT224E_ATCHFRCCALRATIO_NORMAL
+};
+
+/* MXT224E_0V5_CONFIG */
+/* NEXTTCHDI added */
+#ifdef CONFIG_TARGET_LOCALE_NA
+#ifdef CONFIG_MACH_U1_NA_USCC_REV05
+static u8 t9_config_e[] = { TOUCH_MULTITOUCHSCREEN_T9,
+	139, 0, 0, 19, 11, 0, MXT224E_BLEN_BATT, MXT224E_THRESHOLD_BATT, 2, 1,
+	10,
+	10,			/* MOVHYSTI */
+	1, MXT224E_MOVFILTER_BATT, MXT224_MAX_MT_FINGERS, 5, 40, 10, 31, 3,
+	223, 1, 10, 10, 10, 10, 143, 40, 143, 80,
+	18, 15, 50, 50, 0
+};
+
+#else
+static u8 t9_config_e[] = { TOUCH_MULTITOUCHSCREEN_T9,
+	139, 0, 0, 19, 11, 0, MXT224E_BLEN_BATT, MXT224E_THRESHOLD_BATT, 2, 1,
+	10,
+	10,			/* MOVHYSTI */
+	1, MXT224E_MOVFILTER_BATT, MXT224_MAX_MT_FINGERS, 5, 40, 10, 31, 3,
+	223, 1, 10, 10, 10, 10, 143, 40, 143, 80,
+	18, 15, 50, 50, 2
+};
+#endif
+#else
+static u8 t9_config_e[] = { TOUCH_MULTITOUCHSCREEN_T9,
+	139, 0, 0, 19, 11, 0, MXT224E_BLEN_BATT, MXT224E_THRESHOLD_BATT, 2, 1,
+	10,
+	15,			/* MOVHYSTI */
+	1, MXT224E_MOVFILTER_BATT, MXT224_MAX_MT_FINGERS, 5, 40, 10, 31, 3,
+	223, 1, 10, 10, 10, 10, 143, 40, 143, 80,
+	18, 15, 50, 50, MXT224E_NEXTTCHDI_NORMAL
+};
+#endif
+
+static u8 t15_config_e[] = { TOUCH_KEYARRAY_T15,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t18_config_e[] = { SPT_COMCONFIG_T18,
+	0, 0
+};
+
+static u8 t23_config_e[] = { TOUCH_PROXIMITY_T23,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t25_config_e[] = { SPT_SELFTEST_T25,
+	0, 0, 0, 0, 0, 0, 0, 0
+};
+
+#ifdef CONFIG_MACH_U1_NA_USCC_REV05
+static u8 t38_config_e[] = { SPT_USERDATA_T38,
+	0, 1, 13, 19, 44, 0, 0, 0
+};
+#else
+static u8 t38_config_e[] = { SPT_USERDATA_T38,
+	0, 1, 14, 23, 44, 0, 0, 0
+};
+#endif
+
+static u8 t40_config_e[] = { PROCI_GRIPSUPPRESSION_T40,
+	0, 0, 0, 0, 0
+};
+
+static u8 t42_config_e[] = { PROCI_TOUCHSUPPRESSION_T42,
+	0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t46_config_e[] = { SPT_CTECONFIG_T46,
+	0, 3, 16, MXT224E_ACTVSYNCSPERX_NORMAL, 0, 0, 1, 0, 0
+};
+
+static u8 t47_config_e[] = { PROCI_STYLUS_T47,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*MXT224E_0V5_CONFIG */
+#ifdef CONFIG_TARGET_LOCALE_NA
+#ifdef CONFIG_MACH_U1_NA_USCC_REV05
+static u8 t48_config_chrg_e[] = { PROCG_NOISESUPPRESSION_T48,
+	3, 132, 0x52, 0, 0, 0, 0, 0, 10, 15,
+	0, 0, 0, 6, 6, 0, 0, 64, 4, 64,
+	10, 0, 10, 5, 0, 19, 0, 20, 0, 0,
+	0, 0, 0, 0, 0, 40, 2,	/*blen=0,threshold=50 */
+	10,			/* MOVHYSTI */
+	1, 47,
+	10, 5, 40, 240, 245, 10, 10, 148, 50, 143,
+	80, 18, 10, 0
+};
+
+static u8 t48_config_e[] = { PROCG_NOISESUPPRESSION_T48,
+	3, 132, 0x40, 0, 0, 0, 0, 0, 10, 15,
+	0, 0, 0, 6, 6, 0, 0, 64, 4, 64,
+	10, 0, 20, 5, 0, 38, 0, 5, 0, 0,	/*byte 27 original value 20 */
+	0, 0, 0, 0, 32, MXT224E_THRESHOLD, 2,
+	10,
+	1, 46,
+	MXT224_MAX_MT_FINGERS, 5, 40, 10, 0, 10, 10, 143, 40, 143,
+	80, 18, 15, 0
+};
+#else
+static u8 t48_config_chrg_e[] = { PROCG_NOISESUPPRESSION_T48,
+	1, 4, 0x50, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 6, 6, 0, 0, 100, 4, 64,
+	10, 0, 20, 5, 0, 38, 0, 20, 0, 0,
+	0, 0, 0, 0, 0, 40, 2,	/*blen=0,threshold=50 */
+	10,			/* MOVHYSTI */
+	1, 15,
+	10, 5, 40, 240, 245, 10, 10, 148, 50, 143,
+	80, 18, 10, 2
+};
+
+static u8 t48_config_e[] = { PROCG_NOISESUPPRESSION_T48,
+	1, 4, 0x40, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 6, 6, 0, 0, 100, 4, 64,
+	10, 0, 20, 5, 0, 38, 0, 5, 0, 0,	/*byte 27 original value 20 */
+	0, 0, 0, 0, 32, 50, 2,
+	10,
+	1, 46,
+	MXT224_MAX_MT_FINGERS, 5, 40, 10, 0, 10, 10, 143, 40, 143,
+	80, 18, 15, 2
+};
+#endif /*CONFIG_MACH_U1_NA_USCC_REV05 */
+#else
+static u8 t48_config_chrg_e[] = { PROCG_NOISESUPPRESSION_T48,
+	3, 132, MXT224E_CALCFG_CHRG, 0, 0, 0, 0, 0, 10, 15,
+	0, 0, 0, 6, 6, 0, 0, 64, 4, 64,
+	10, 0, 9, 5, 0, 15, 0, 20, 0, 0,
+	0, 0, 0, 0, 0, MXT224E_THRESHOLD_CHRG, 2,
+	15,			/* MOVHYSTI */
+	1, 47,
+	MXT224_MAX_MT_FINGERS, 5, 40, 235, 235, 10, 10, 160, 50, 143,
+	80, 18, 10, 0
+};
+
+static u8 t48_config_e[] = { PROCG_NOISESUPPRESSION_T48,
+	3, 132, MXT224E_CALCFG_BATT, 0, 0, 0, 0, 0, 10, 15,
+	0, 0, 0, 6, 6, 0, 0, 48, 4, 48,
+	10, 0, 10, 5, 0, 20, 0, 5, 0, 0,	/*byte 27 original value 20 */
+	0, 0, 0, 0, 32, MXT224E_THRESHOLD_BATT, 2,
+	15,
+	1, 46,
+	MXT224_MAX_MT_FINGERS, 5, 40, 10, 10, 10, 10, 143, 40, 143,
+	80, 18, 15, 0
+};
+#endif /*CONFIG_TARGET_LOCALE_NA */
+#endif /*CONFIG_TARGET_LOCALE_NAATT */
+
+static u8 end_config_e[] = { RESERVED_T255 };
+
+static const u8 *mxt224e_config[] = {
+	t7_config_e,
+	t8_config_e,
+	t9_config_e,
+	t15_config_e,
+	t18_config_e,
+	t23_config_e,
+	t25_config_e,
+	t38_config_e,
+	t40_config_e,
+	t42_config_e,
+	t46_config_e,
+	t47_config_e,
+	t48_config_e,
+	end_config_e,
+};
+
+static struct mxt224_platform_data mxt224_data = {
+	.max_finger_touches = MXT224_MAX_MT_FINGERS,
+	.gpio_read_done = GPIO_TSP_INT,
+	.config = mxt224_config,
+	.config_e = mxt224e_config,
+	.t48_config_batt_e = t48_config_e,
+	.t48_config_chrg_e = t48_config_chrg_e,
+	.min_x = 0,
+	.max_x = 479,
+	.min_y = 0,
+	.max_y = 799,
+	.min_z = 0,
+	.max_z = 255,
+	.min_w = 0,
+	.max_w = 30,
+	.atchcalst = MXT224_ATCHCALST,
+	.atchcalsthr = MXT224_ATCHCALTHR,
+	.tchthr_batt = MXT224_THRESHOLD_BATT,
+	.tchthr_batt_init = MXT224_THRESHOLD_BATT_INIT,
+	.tchthr_charging = MXT224_THRESHOLD_CHRG,
+	.noisethr_batt = MXT224_NOISE_THRESHOLD_BATT,
+	.noisethr_charging = MXT224_NOISE_THRESHOLD_CHRG,
+	.movfilter_batt = MXT224_MOVFILTER_BATT,
+	.movfilter_charging = MXT224_MOVFILTER_CHRG,
+	.atchcalst_e = MXT224E_ATCHCALST,
+	.atchcalsthr_e = MXT224E_ATCHCALTHR,
+	.tchthr_batt_e = MXT224E_THRESHOLD_BATT,
+	.tchthr_charging_e = MXT224E_THRESHOLD_CHRG,
+	.calcfg_batt_e = MXT224E_CALCFG_BATT,
+	.calcfg_charging_e = MXT224E_CALCFG_CHRG,
+	.atchfrccalthr_e = MXT224E_ATCHFRCCALTHR_NORMAL,
+	.atchfrccalratio_e = MXT224E_ATCHFRCCALRATIO_NORMAL,
+	.chrgtime_batt_e = MXT224E_GHRGTIME_BATT,
+	.chrgtime_charging_e = MXT224E_GHRGTIME_CHRG,
+	.blen_batt_e = MXT224E_BLEN_BATT,
+	.blen_charging_e = MXT224E_BLEN_CHRG,
+	.movfilter_batt_e = MXT224E_MOVFILTER_BATT,
+	.movfilter_charging_e = MXT224E_MOVFILTER_CHRG,
+	.actvsyncsperx_e = MXT224E_ACTVSYNCSPERX_NORMAL,
+	.nexttchdi_e = MXT224E_NEXTTCHDI_NORMAL,
+	.power_on = mxt224_power_on,
+	.power_off = mxt224_power_off,
+	.register_cb = tsp_register_callback,
+	.read_ta_status = tsp_read_ta_status,
+};
+
+void mxt224_set_touch_i2c(void)
+{
+	s3c_gpio_cfgpin(GPIO_TSP_SDA_18V, S3C_GPIO_SFN(3));
+	s3c_gpio_setpull(GPIO_TSP_SDA_18V, S3C_GPIO_PULL_UP);
+	s3c_gpio_cfgpin(GPIO_TSP_SCL_18V, S3C_GPIO_SFN(3));
+	s3c_gpio_setpull(GPIO_TSP_SCL_18V, S3C_GPIO_PULL_UP);
+	gpio_free(GPIO_TSP_SDA_18V);
+	gpio_free(GPIO_TSP_SCL_18V);
+	s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_SFN(0xf));
+	/* s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); */
+	s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_NONE);
+}
+
+void mxt224_set_touch_i2c_to_gpio(void)
+{
+	int ret;
+	s3c_gpio_cfgpin(GPIO_TSP_SDA_18V, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TSP_SDA_18V, S3C_GPIO_PULL_UP);
+	s3c_gpio_cfgpin(GPIO_TSP_SCL_18V, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TSP_SCL_18V, S3C_GPIO_PULL_UP);
+	ret = gpio_request(GPIO_TSP_SDA_18V, "GPIO_TSP_SDA");
+	if (ret)
+		pr_err("failed to request gpio(GPIO_TSP_SDA)\n");
+	ret = gpio_request(GPIO_TSP_SCL_18V, "GPIO_TSP_SCL");
+	if (ret)
+		pr_err("failed to request gpio(GPIO_TSP_SCL)\n");
+}
+
+/* I2C3 */
+static struct i2c_board_info i2c_devs3[] __initdata = {
+	{
+	 I2C_BOARD_INFO(MXT224_DEV_NAME, 0x4a),
+	 .platform_data = &mxt224_data},
+};
+
+#ifndef CONFIG_MACH_NEWTON_BD
+void midas_tsp_set_platdata(struct mxt224_platform_data *pdata)
+{
+	if (!pdata)
+		pdata = &mxt224_data;
+
+	i2c_devs3[0].platform_data = pdata;
+}
+#endif
+
+void __init midas_tsp_init(void)
+{
+#ifndef CONFIG_MACH_NEWTON_BD
+	int gpio;
+	int ret;
+	printk(KERN_INFO "[TSP] midas_tsp_init() is called\n");
+
+	/* TSP_INT: XEINT_4 */
+	gpio = GPIO_TSP_INT;
+	ret = gpio_request(gpio, "TSP_INT");
+	if (ret)
+		pr_err("failed to request gpio(TSP_INT)\n");
+	s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
+	/* s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); */
+	s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+
+	s5p_register_gpio_interrupt(gpio);
+	i2c_devs3[0].irq = gpio_to_irq(gpio);
+
+	printk(KERN_INFO "%s touch : %d\n", __func__, i2c_devs3[0].irq);
+#endif
+	i2c_register_board_info(3, i2c_devs3, ARRAY_SIZE(i2c_devs3));
+}
+
+#elif defined(CONFIG_TOUCHSCREEN_MELFAS_GC)
+
+static bool enabled;
+int melfas_power(int on)
+{
+	struct regulator *regulator_pwr;
+	struct regulator *regulator_vdd;
+	int ret = 0;
+
+	if (enabled == on) {
+		pr_err("melfas-ts : %s same state!", __func__);
+		return 0;
+	}
+
+	regulator_pwr = regulator_get(NULL, "touch");
+	regulator_vdd = regulator_get(NULL, "touch_1.8v");
+
+	if (IS_ERR(regulator_pwr)) {
+		pr_err("melfas-ts : %s regulator_pwr error!", __func__);
+		return PTR_ERR(regulator_pwr);
+	}
+	if (IS_ERR(regulator_vdd)) {
+		pr_err("melfas-ts : %s regulator_vdd error!", __func__);
+		return PTR_ERR(regulator_vdd);
+	}
+
+	if (on) {
+		regulator_enable(regulator_vdd);
+		regulator_enable(regulator_pwr);
+	} else {
+		if (regulator_is_enabled(regulator_pwr))
+			regulator_disable(regulator_pwr);
+		if (regulator_is_enabled(regulator_vdd))
+			regulator_disable(regulator_vdd);
+	}
+
+	if (regulator_is_enabled(regulator_pwr) == !!on &&
+		regulator_is_enabled(regulator_vdd) == !!on) {
+		pr_info("melfas-ts : %s %s", __func__, !!on ? "ON" : "OFF");
+		enabled = on;
+	} else {
+		pr_err("melfas-ts : regulator_is_enabled value error!");
+		ret = -1;
+	}
+
+	regulator_put(regulator_vdd);
+	regulator_put(regulator_pwr);
+
+	return ret;
+}
+
+int melfas_mux_fw_flash(bool to_gpios)
+{
+	pr_info("melfas-ts : %s:to_gpios=%d\n", __func__, to_gpios);
+
+	/* TOUCH_EN is always an output */
+	if (to_gpios) {
+		if (gpio_request(GPIO_TSP_SCL_18V, "GPIO_TSP_SCL"))
+			pr_err("failed to request gpio(GPIO_TSP_SCL)\n");
+		if (gpio_request(GPIO_TSP_SDA_18V, "GPIO_TSP_SDA"))
+			pr_err("failed to request gpio(GPIO_TSP_SDA)\n");
+
+		gpio_direction_output(GPIO_TSP_INT, 0);
+		s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_OUTPUT);
+		s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_NONE);
+
+		gpio_direction_output(GPIO_TSP_SCL_18V, 0);
+		s3c_gpio_cfgpin(GPIO_TSP_SCL_18V, S3C_GPIO_OUTPUT);
+		s3c_gpio_setpull(GPIO_TSP_SCL_18V, S3C_GPIO_PULL_NONE);
+
+		gpio_direction_output(GPIO_TSP_SDA_18V, 0);
+		s3c_gpio_cfgpin(GPIO_TSP_SDA_18V, S3C_GPIO_OUTPUT);
+		s3c_gpio_setpull(GPIO_TSP_SDA_18V, S3C_GPIO_PULL_NONE);
+
+	} else {
+		gpio_direction_output(GPIO_TSP_INT, 1);
+		gpio_direction_input(GPIO_TSP_INT);
+		s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_SFN(0xf));
+		/*s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_INPUT); */
+		s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_NONE);
+		/*S3C_GPIO_PULL_UP */
+
+		gpio_direction_output(GPIO_TSP_SCL_18V, 1);
+		gpio_direction_input(GPIO_TSP_SCL_18V);
+		s3c_gpio_cfgpin(GPIO_TSP_SCL_18V, S3C_GPIO_SFN(3));
+		s3c_gpio_setpull(GPIO_TSP_SCL_18V, S3C_GPIO_PULL_NONE);
+
+		gpio_direction_output(GPIO_TSP_SDA_18V, 1);
+		gpio_direction_input(GPIO_TSP_SDA_18V);
+		s3c_gpio_cfgpin(GPIO_TSP_SDA_18V, S3C_GPIO_SFN(3));
+		s3c_gpio_setpull(GPIO_TSP_SDA_18V, S3C_GPIO_PULL_NONE);
+
+		gpio_free(GPIO_TSP_SCL_18V);
+		gpio_free(GPIO_TSP_SDA_18V);
+	}
+	return 0;
+}
+
+struct tsp_callbacks *charger_callbacks;
+struct tsp_callbacks {
+	void (*inform_charger)(struct tsp_callbacks *, bool);
+};
+
+void tsp_charger_infom(bool en)
+{
+	if (charger_callbacks && charger_callbacks->inform_charger)
+		charger_callbacks->inform_charger(charger_callbacks, en);
+}
+
+static void melfas_register_callback(void *cb)
+{
+	charger_callbacks = cb;
+	pr_info("melfas-ts : melfas_register_callback");
+}
+
+static struct melfas_tsi_platform_data mms_ts_pdata = {
+	.max_x = 720,
+	.max_y = 1280,
+	.invert_x = 0,
+	.invert_y = 0,
+	.gpio_int = GPIO_TSP_INT,
+	.gpio_scl = GPIO_TSP_SCL_18V,
+	.gpio_sda = GPIO_TSP_SDA_18V,
+	.power = melfas_power,
+	.mux_fw_flash = melfas_mux_fw_flash,
+	.config_fw_version = "GC_Me_0000",
+	.register_cb = melfas_register_callback,
+};
+
+static struct i2c_board_info i2c_devs3[] = {
+	{
+	 I2C_BOARD_INFO(MELFAS_TS_NAME, 0x48),
+	 .platform_data = &mms_ts_pdata},
+};
+
+void __init midas_tsp_set_platdata(struct melfas_tsi_platform_data *pdata)
+{
+	if (!pdata)
+		pdata = &mms_ts_pdata;
+
+	i2c_devs3[0].platform_data = pdata;
+}
+
+void __init midas_tsp_init(void)
+{
+	int gpio;
+	int ret;
+	pr_info("melfas-ts : GC TSP init() is called");
+
+	/* TSP_INT: XEINT_4 */
+	gpio = GPIO_TSP_INT;
+	ret = gpio_request(gpio, "TSP_INT");
+	if (ret)
+		pr_err("melfas-ts : failed to request gpio(TSP_INT)");
+	s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
+	s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+
+	s5p_register_gpio_interrupt(gpio);
+	i2c_devs3[0].irq = gpio_to_irq(gpio);
+
+	pr_info("melfas-ts : %s touch : %d\n", __func__, i2c_devs3[0].irq);
+
+	i2c_register_board_info(3, i2c_devs3, ARRAY_SIZE(i2c_devs3));
+}
+
+#else /* CONFIG_TOUCHSCREEN_ATMEL_MXT224_U1 */
+
+/* MELFAS TSP */
+static bool enabled;
+int TSP_VDD_18V(int on)
+{
+	struct regulator *regulator;
+
+	if (enabled == on)
+		return 0;
+
+	regulator = regulator_get(NULL, "touch_1.8v");
+	if (IS_ERR(regulator))
+		return PTR_ERR(regulator);
+
+	if (on) {
+		regulator_enable(regulator);
+		/*printk(KERN_INFO "[TSP] melfas power on\n"); */
+	} else {
+		/*
+		 * TODO: If there is a case the regulator must be disabled
+		 * (e,g firmware update?), consider regulator_force_disable.
+		 */
+		if (regulator_is_enabled(regulator))
+			regulator_disable(regulator);
+	}
+
+	enabled = on;
+	regulator_put(regulator);
+
+	return 0;
+}
+
+int melfas_power(int on)
+{
+	struct regulator *regulator;
+	int ret;
+	if (enabled == on)
+		return 0;
+
+	regulator = regulator_get(NULL, "touch");
+	if (IS_ERR(regulator))
+		return PTR_ERR(regulator);
+
+	printk(KERN_DEBUG "[TSP] %s %s\n", __func__, on ? "on" : "off");
+
+	if (on) {
+		regulator_enable(regulator);
+#if defined(GPIO_OLED_DET)
+#if defined(CONFIG_MACH_SLP_PQ)
+		if (system_rev != 0x3)	/* M0_P_Rev0.0 */
+#endif
+		{	/*TODO: will remove after divide regulator */
+			ret = gpio_request(GPIO_OLED_DET, "OLED_DET");
+			if (ret)
+				pr_err("failed to request gpio(OLED_DET)\n");
+			s3c_gpio_setpull(GPIO_OLED_DET, S3C_GPIO_PULL_NONE);
+			s3c_gpio_cfgpin(GPIO_OLED_DET, S3C_GPIO_SFN(0xf));
+			gpio_free(GPIO_OLED_DET);
+
+			TSP_VDD_18V(1);
+		}
+#endif
+	} else {
+		/*
+		 * TODO: If there is a case the regulator must be disabled
+		 * (e,g firmware update?), consider regulator_force_disable.
+		 */
+		if (regulator_is_enabled(regulator)) {
+			regulator_disable(regulator);
+#if defined(GPIO_OLED_DET)
+#if defined(CONFIG_MACH_SLP_PQ)
+			if (system_rev != 0x3)	/* M0_P_Rev0.0 */
+#endif
+			{	/*TODO: will remove after divide regulator */
+				ret = gpio_request(GPIO_OLED_DET, "OLED_DET");
+				if (ret)
+					pr_err
+					    ("failed to request gpio(OLED_DET)\n");
+				s3c_gpio_cfgpin(GPIO_OLED_DET, S3C_GPIO_OUTPUT);
+				s3c_gpio_setpull(GPIO_OLED_DET,
+						 S3C_GPIO_PULL_NONE);
+				gpio_direction_output(GPIO_OLED_DET,
+						      GPIO_LEVEL_LOW);
+				gpio_free(GPIO_OLED_DET);
+
+				TSP_VDD_18V(0);
+			}
+#endif
+		}
+	}
+
+	enabled = on;
+	regulator_put(regulator);
+
+	return 0;
+}
+
+int is_melfas_vdd_on(void)
+{
+	int ret;
+	/* 3.3V */
+	static struct regulator *regulator;
+
+	if (!regulator) {
+		regulator = regulator_get(NULL, "touch");
+		if (IS_ERR(regulator)) {
+			ret = PTR_ERR(regulator);
+			pr_err("could not get touch, rc = %d\n", ret);
+			return ret;
+		}
+/*
+		ret = regulator_set_voltage(regulator, 3300000, 3300000);
+		if (ret) {
+			pr_err("%s: unable to set ldo17 voltage to 3.3V\n",
+			       __func__);
+			return ret;
+		} */
+	}
+
+	if (regulator_is_enabled(regulator))
+		return 1;
+	else
+		return 0;
+}
+
+int melfas_mux_fw_flash(bool to_gpios)
+{
+	pr_info("%s:to_gpios=%d\n", __func__, to_gpios);
+
+	/* TOUCH_EN is always an output */
+	if (to_gpios) {
+		if (gpio_request(GPIO_TSP_SCL_18V, "GPIO_TSP_SCL"))
+			pr_err("failed to request gpio(GPIO_TSP_SCL)\n");
+		if (gpio_request(GPIO_TSP_SDA_18V, "GPIO_TSP_SDA"))
+			pr_err("failed to request gpio(GPIO_TSP_SDA)\n");
+
+		gpio_direction_output(GPIO_TSP_INT, 0);
+		s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_OUTPUT);
+		s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_NONE);
+
+		gpio_direction_output(GPIO_TSP_SCL_18V, 0);
+		s3c_gpio_cfgpin(GPIO_TSP_SCL_18V, S3C_GPIO_OUTPUT);
+		s3c_gpio_setpull(GPIO_TSP_SCL_18V, S3C_GPIO_PULL_NONE);
+
+		gpio_direction_output(GPIO_TSP_SDA_18V, 0);
+		s3c_gpio_cfgpin(GPIO_TSP_SDA_18V, S3C_GPIO_OUTPUT);
+		s3c_gpio_setpull(GPIO_TSP_SDA_18V, S3C_GPIO_PULL_NONE);
+
+	} else {
+		gpio_direction_output(GPIO_TSP_INT, 1);
+		gpio_direction_input(GPIO_TSP_INT);
+		s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_SFN(0xf));
+		/*s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_INPUT); */
+		s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_NONE);
+		/*S3C_GPIO_PULL_UP */
+
+		gpio_direction_output(GPIO_TSP_SCL_18V, 1);
+		gpio_direction_input(GPIO_TSP_SCL_18V);
+		s3c_gpio_cfgpin(GPIO_TSP_SCL_18V, S3C_GPIO_SFN(3));
+		s3c_gpio_setpull(GPIO_TSP_SCL_18V, S3C_GPIO_PULL_NONE);
+
+		gpio_direction_output(GPIO_TSP_SDA_18V, 1);
+		gpio_direction_input(GPIO_TSP_SDA_18V);
+		s3c_gpio_cfgpin(GPIO_TSP_SDA_18V, S3C_GPIO_SFN(3));
+		s3c_gpio_setpull(GPIO_TSP_SDA_18V, S3C_GPIO_PULL_NONE);
+
+		gpio_free(GPIO_TSP_SCL_18V);
+		gpio_free(GPIO_TSP_SDA_18V);
+	}
+	return 0;
+}
+
+void melfas_set_touch_i2c(void)
+{
+	s3c_gpio_cfgpin(GPIO_TSP_SDA_18V, S3C_GPIO_SFN(3));
+	s3c_gpio_setpull(GPIO_TSP_SDA_18V, S3C_GPIO_PULL_UP);
+	s3c_gpio_cfgpin(GPIO_TSP_SCL_18V, S3C_GPIO_SFN(3));
+	s3c_gpio_setpull(GPIO_TSP_SCL_18V, S3C_GPIO_PULL_UP);
+	gpio_free(GPIO_TSP_SDA_18V);
+	gpio_free(GPIO_TSP_SCL_18V);
+	s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_SFN(0xf));
+	/* s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); */
+	s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_NONE);
+}
+
+void melfas_set_touch_i2c_to_gpio(void)
+{
+	int ret;
+	s3c_gpio_cfgpin(GPIO_TSP_SDA_18V, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TSP_SDA_18V, S3C_GPIO_PULL_UP);
+	s3c_gpio_cfgpin(GPIO_TSP_SCL_18V, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TSP_SCL_18V, S3C_GPIO_PULL_UP);
+	ret = gpio_request(GPIO_TSP_SDA_18V, "GPIO_TSP_SDA");
+	if (ret)
+		pr_err("failed to request gpio(GPIO_TSP_SDA)\n");
+	ret = gpio_request(GPIO_TSP_SCL_18V, "GPIO_TSP_SCL");
+	if (ret)
+		pr_err("failed to request gpio(GPIO_TSP_SCL)\n");
+
+}
+
+int get_lcd_type;
+void __init midas_tsp_set_lcdtype(int lcd_type)
+{
+	get_lcd_type = lcd_type;
+}
+
+int melfas_get_lcdtype(void)
+{
+	return get_lcd_type;
+}
+struct tsp_callbacks *charger_callbacks;
+struct tsp_callbacks {
+	void (*inform_charger)(struct tsp_callbacks *, bool);
+};
+
+void tsp_charger_infom(bool en)
+{
+	if (charger_callbacks && charger_callbacks->inform_charger)
+		charger_callbacks->inform_charger(charger_callbacks, en);
+}
+
+static void melfas_register_callback(void *cb)
+{
+	charger_callbacks = cb;
+	pr_debug("[TSP] melfas_register_callback\n");
+}
+
+static struct melfas_tsi_platform_data mms_ts_pdata = {
+	.max_x = 720,
+	.max_y = 1280,
+#if !defined(CONFIG_MACH_C1) && !defined(CONFIG_MACH_C1VZW) && \
+		!defined(CONFIG_MACH_M0) && \
+		!defined(CONFIG_MACH_M3) && \
+		!defined(CONFIG_MACH_P4NOTE)
+	.invert_x = 720,
+	.invert_y = 1280,
+#else
+	.invert_x = 0,
+	.invert_y = 0,
+#endif
+	.gpio_int = GPIO_TSP_INT,
+	.gpio_scl = GPIO_TSP_SCL_18V,
+	.gpio_sda = GPIO_TSP_SDA_18V,
+	.power = melfas_power,
+	.mux_fw_flash = melfas_mux_fw_flash,
+	.is_vdd_on = is_melfas_vdd_on,
+	.config_fw_version = "I9300_Me_0507",
+/*	.set_touch_i2c		= melfas_set_touch_i2c, */
+/*	.set_touch_i2c_to_gpio	= melfas_set_touch_i2c_to_gpio, */
+	.lcd_type = melfas_get_lcdtype,
+	.register_cb = melfas_register_callback,
+};
+
+static struct i2c_board_info i2c_devs3[] = {
+	{
+	 I2C_BOARD_INFO(MELFAS_TS_NAME, 0x48),
+	 .platform_data = &mms_ts_pdata},
+};
+
+void __init midas_tsp_set_platdata(struct melfas_tsi_platform_data *pdata)
+{
+	if (!pdata)
+		pdata = &mms_ts_pdata;
+
+	i2c_devs3[0].platform_data = pdata;
+}
+
+void __init midas_tsp_init(void)
+{
+	int gpio;
+	int ret;
+	printk(KERN_INFO "[TSP] midas_tsp_init() is called\n");
+
+	/* TSP_INT: XEINT_4 */
+	gpio = GPIO_TSP_INT;
+	ret = gpio_request(gpio, "TSP_INT");
+	if (ret)
+		pr_err("failed to request gpio(TSP_INT)\n");
+	s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
+	/* s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); */
+	s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+
+	s5p_register_gpio_interrupt(gpio);
+	i2c_devs3[0].irq = gpio_to_irq(gpio);
+
+	printk(KERN_INFO "%s touch : %d\n", __func__, i2c_devs3[0].irq);
+
+	i2c_register_board_info(3, i2c_devs3, ARRAY_SIZE(i2c_devs3));
+}
+#endif /* CONFIG_TOUCHSCREEN_ATMEL_MXT224_U1 */
+
+/*
+ * Flexrate supports reducing cpufreq ondemand polling rate
+ * based on the user input events including touch events.
+ * This reduces response time if the touch event triggers tasks that require
+ * heavy CPU loads and does not incur unnecessary CPUFreq-up if the touch
+ * event does not trigger such tasks.
+ */
+#ifdef CONFIG_CPU_FREQ_GOV_ONDEMAND_FLEXRATE
+static void flexrate_work(struct work_struct *work)
+{
+	cpufreq_ondemand_flexrate_request(10000, 10);
+}
+
+#include <linux/pm_qos_params.h>
+static struct pm_qos_request_list busfreq_qos;
+static void flexrate_qos_cancel(struct work_struct *work)
+{
+	pm_qos_update_request(&busfreq_qos, 0);
+}
+
+static DECLARE_WORK(flex_work, flexrate_work);
+static DECLARE_DELAYED_WORK(busqos_work, flexrate_qos_cancel);
+
+void midas_tsp_request_qos(void *data)
+{
+	if (!work_pending(&flex_work))
+		schedule_work_on(0, &flex_work);
+
+	/* Guarantee that the bus runs at >= 266MHz */
+	if (!pm_qos_request_active(&busfreq_qos))
+		pm_qos_add_request(&busfreq_qos, PM_QOS_BUS_DMA_THROUGHPUT,
+				   266000);
+	else {
+		cancel_delayed_work_sync(&busqos_work);
+		pm_qos_update_request(&busfreq_qos, 266000);
+	}
+
+	/* Cancel the QoS request after 1/10 sec */
+	schedule_delayed_work_on(0, &busqos_work, HZ / 5);
+}
+#endif
diff --git a/arch/arm/mach-exynos/midas.h b/arch/arm/mach-exynos/midas.h
new file mode 100644
index 0000000..62df16e
--- /dev/null
+++ b/arch/arm/mach-exynos/midas.h
@@ -0,0 +1,35 @@
+/*
+ * arch/arm/mach-exynos/midas.h
+ */
+
+#ifndef __MIDAS_H__
+#define __MIDAS_H__
+
+static inline int i2c_add_devices(int busnum, struct i2c_board_info *infos,
+				  int size)
+{
+	struct i2c_adapter *i2c_adap;
+	int i;
+	i2c_adap = i2c_get_adapter(busnum);
+	if (!i2c_adap) {
+		pr_err("%s: ERROR i2c bus %d not found\n", __func__, busnum);
+		return -ENODEV;
+	}
+
+	for (i = 0; i < size; i++) {
+		struct i2c_client *client = i2c_new_device(i2c_adap, infos + i);
+		if (client)
+			dev_info(&client->dev, "%s - added %s successfully\n",
+				 __func__, infos[i].type);
+		else
+			dev_err(&i2c_adap->dev,
+				"%s - added %s at bus i2c bus %d failed\n",
+				__func__, infos[i].type, busnum);
+
+	}
+	i2c_put_adapter(i2c_adap);
+
+	return 0;
+}
+
+#endif
diff --git a/arch/arm/mach-exynos/naples-camera.c b/arch/arm/mach-exynos/naples-camera.c
new file mode 100644
index 0000000..f2f83cf
--- /dev/null
+++ b/arch/arm/mach-exynos/naples-camera.c
@@ -0,0 +1,860 @@
+/*
+ * linux/arch/arm/mach-exynos/naples-naples.c
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/gpio.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+
+#include <linux/regulator/machine.h>
+
+#include <plat/devs.h>
+#include <plat/csis.h>
+#include <plat/pd.h>
+#include <plat/gpio-cfg.h>
+
+#include <media/exynos_flite.h>
+
+#include <media/s5k4ecgx_platform.h>
+#include <media/db8131m_platform.h>
+
+struct class *camera_class;
+struct device *s5k4ecgx_dev; /*sys/class/camera/rear*/
+struct device *db8131m_dev; /*sys/class/camera/front*/
+
+/* flash_type: FLASH[0], TORCH[1] */
+static int max77693_led_ctrl(int ctrl)
+{
+	int ret = 0;
+
+	pr_info("%s, flash_type[%d]", __func__, ctrl);
+
+	/* Flash TORCH_EN(FLASHEN) */
+	ret = gpio_request(GPIO_TORCH_EN, "GPJ1");
+	if (ret) {
+		pr_err("fail to request gpio(GPIO_TORCH_EN)");
+		return ret;
+	}
+
+	/* Flash TORCH_SET(TORCHEN) */
+	ret = gpio_request(GPIO_TORCH_SET, "GPJ1");
+	if (ret) {
+		pr_err("faile to request gpio(GPIO_TORCH_SET)");
+		return ret;
+	}
+
+	if (ctrl == CAM_FLASH_ON)
+		/* FLSH mode */
+		ret = gpio_direction_output(GPIO_TORCH_EN, 1);
+	else if (ctrl == CAM_FLASH_TORCH)
+		/* TORCH mode */
+		ret = gpio_direction_output(GPIO_TORCH_SET, 1);
+	else {
+		ret = gpio_direction_output(GPIO_TORCH_EN, 0);
+		ret |= gpio_direction_output(GPIO_TORCH_SET, 0);
+	}
+
+	gpio_free(GPIO_TORCH_EN);
+	gpio_free(GPIO_TORCH_SET);
+
+	if (unlikely((ret) < 0)) {					\
+		pr_err("fail to %s: err = %d", "Flash control", ret);	\
+	}
+
+	return ret;
+}
+
+#if defined(CONFIG_VIDEO_FIMC)
+/*
+ * External camera reset
+ * Because the most of cameras take i2c bus signal, so that
+ * you have to reset at the boot time for other i2c slave devices.
+ * This function also called at fimc_init_camera()
+ * Do optimization for cameras on your platform.
+ */
+int s3c_csis_power(int enable)
+{
+	struct regulator *regulator;
+	int ret = 0;
+
+	/* mipi_1.1v ,mipi_1.8v are always powered-on.
+	 * If they are off, we then power them on.
+	 */
+	if (enable) {
+		/* VMIPI_1.0V */
+		regulator = regulator_get(NULL, "vmipi_1.0v");
+		if (IS_ERR(regulator))
+			goto error_out;
+		if (!regulator_is_enabled(regulator)) {
+			pr_warn("%s: vmipi_1.1v is off. so ON",
+			       __func__);
+			ret = regulator_enable(regulator);
+		}
+		regulator_put(regulator);
+
+		/* VMIPI_1.8V */
+		regulator = regulator_get(NULL, "vmipi_1.8v");
+		if (IS_ERR(regulator))
+			goto error_out;
+		if (!regulator_is_enabled(regulator)) {
+			pr_warn("%s: vmipi_1.8v is off. so ON",
+			       __func__);
+			ret = regulator_enable(regulator);
+		}
+		regulator_put(regulator);
+		pr_warn("%s: vmipi_1.0v and vmipi_1.8v were ON",
+		       __func__);
+	}
+
+	return 0;
+
+error_out:
+	pr_err("%s: ERROR: failed to check mipi-power", __func__);
+	return 0;
+}
+
+#ifdef WRITEBACK_ENABLED
+static int get_i2c_busnum_writeback(void)
+{
+	return 0;
+}
+
+static struct i2c_board_info __initdata writeback_i2c_info = {
+	I2C_BOARD_INFO("WriteBack", 0x0),
+};
+
+static struct s3c_platform_camera writeback = {
+	.id		= CAMERA_WB,
+	.fmt		= ITU_601_YCBCR422_8BIT,
+	.order422	= CAM_ORDER422_8BIT_CBYCRY,
+	.get_i2c_busnum = get_i2c_busnum_writeback,
+	.info		= &writeback_i2c_info,
+	.pixelformat	= V4L2_PIX_FMT_YUV444,
+	.line_length	= 800,
+	.width		= 480,
+	.height		= 800,
+	.window		= {
+		.left	= 0,
+		.top	= 0,
+		.width	= 480,
+		.height	= 800,
+	},
+
+	.initialized	= 0,
+};
+#endif
+
+#define CAM_CHECK_ERR_RET(x, msg)					\
+	if (unlikely((x) < 0)) {					\
+		pr_err("fail to %s: err = %d", msg, x);	\
+		return x;						\
+	}
+#define CAM_CHECK_ERR(x, msg)						\
+	if (unlikely((x) < 0)) {					\
+		pr_err("fail to %s: err = %d", msg, x);	\
+	}
+
+static int s5k4ecgx_gpio_request(void)
+{
+	int ret = 0;
+
+	ret = gpio_request(GPIO_5M_CAM_RESET, "GPF1");
+	if (ret) {
+		pr_err("faile to request gpio(GPIO_5M_CAM_RESET)");
+		return ret;
+	}
+
+	ret = gpio_request(GPIO_5M_CAM_nSTBY, "GPM0");
+	if (ret) {
+		pr_err("faile to request gpio(GPIO_5M_CAM_nSTBY)");
+		return ret;
+	}
+
+	return ret;
+}
+
+static int s5k4ecgx_power_on(void)
+{
+	struct regulator *regulator;
+	int ret = 0;
+
+	pr_debug("%s: in", __func__);
+
+	s5k4ecgx_gpio_request();
+
+	/* CAM_SENSOR_IO_1.8V */
+	regulator = regulator_get(NULL, "cam_sensor_io_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "enable cam_sensor_io_1.8v");
+
+	/* CAM_SENSOR_A2.8V */
+	regulator = regulator_get(NULL, "cam_sensor_a2.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "enable cam_sensor_a2.8v");
+
+	/* CAM_DVDD_1.5V(1.3M Core 1.8V) */
+	regulator = regulator_get(NULL, "cam_dvdd_1.5v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "enable cam_dvdd_1.5v");
+
+	/* MCLK */
+	ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_SFN(2));
+	CAM_CHECK_ERR_RET(ret, "cfg mclk");
+	s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_NONE);
+
+	/* CAM_ISP_CORE_1.2V */
+	regulator = regulator_get(NULL, "cam_isp_core_1.2v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "enable cam_isp_core_1.2v");
+
+	/* VT_CAM_nSTBY(1.3M EN) LOW */
+	ret = gpio_request(GPIO_VT_CAM_nSTBY, "GPM0");
+	if (ret) {
+		pr_err("faile to request gpio(GPIO_VT_CAM_nSTBY)");
+		return ret;
+	}
+	ret = gpio_direction_output(GPIO_VT_CAM_nSTBY, 0);
+	CAM_CHECK_ERR_RET(ret, "low VT_CAM_nSTBY");
+
+	/* CAM_VT_nRST(1.3M RESET) LOW */
+	ret = gpio_request(GPIO_CAM_VT_nRST, "GPM1");
+	if (ret) {
+		pr_err("faile to request gpio(GPIO_CAM_VT_nRST)");
+		return ret;
+	}
+	ret = gpio_direction_output(GPIO_CAM_VT_nRST, 0);
+	CAM_CHECK_ERR_RET(ret, "low CAM_VT_nRST");
+
+	/* CAM_AF_2.8V */
+	regulator = regulator_get(NULL, "cam_af_2.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "enable cam_af_2.8v");
+
+	mdelay(1);		/* 10us */
+
+	/* 5M_CAM_nSTBY(5M STBY) */
+	ret = gpio_direction_output(GPIO_5M_CAM_nSTBY, 1);
+	CAM_CHECK_ERR_RET(ret, "high 5M_CAM_nSTBY");
+
+	mdelay(1);		/* 15us */
+
+	/* 5M_CAM_RESET(5M RESET) */
+	ret = gpio_direction_output(GPIO_5M_CAM_RESET, 1);
+	CAM_CHECK_ERR_RET(ret, "high 5M_CAM_RESET");
+
+	mdelay(1);		/* 60us */
+
+	gpio_free(GPIO_VT_CAM_nSTBY);
+	gpio_free(GPIO_CAM_VT_nRST);
+	gpio_free(GPIO_5M_CAM_nSTBY);
+	gpio_free(GPIO_5M_CAM_RESET);
+
+	return ret;
+}
+
+static int s5k4ecgx_power_down(void)
+{
+	struct regulator *regulator;
+	int ret = 0;
+
+	pr_debug("%s: in", __func__);
+
+	s5k4ecgx_gpio_request();
+
+	/* VT_CAM_nSTBY(1.3M EN) LOW */
+	ret = gpio_request(GPIO_VT_CAM_nSTBY, "GPM0");
+	if (ret) {
+		pr_err("faile to request gpio(GPIO_VT_CAM_nSTBY)");
+		return ret;
+	}
+	ret = gpio_direction_output(GPIO_VT_CAM_nSTBY, 0);
+	CAM_CHECK_ERR_RET(ret, "low VT_CAM_nSTBY");
+
+	/* CAM_VT_nRST(1.3M RESET) LOW */
+	ret = gpio_request(GPIO_CAM_VT_nRST, "GPM1");
+	if (ret) {
+		pr_err("faile to request gpio(GPIO_CAM_VT_nRST)");
+		return ret;
+	}
+	ret = gpio_direction_output(GPIO_CAM_VT_nRST, 0);
+	CAM_CHECK_ERR_RET(ret, "low CAM_VT_nRST");
+
+	/* 5M_CAM_RESET(5M RESET) LOW */
+	ret = gpio_direction_output(GPIO_5M_CAM_RESET, 0);
+	CAM_CHECK_ERR_RET(ret, "low 5M_CAM_RESET");
+
+	mdelay(1);		/* 50us */
+
+	/* MCLK */
+	ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_DOWN);
+	CAM_CHECK_ERR(ret, "cfg mclk");
+
+	/* 5M_CAM_nSTBY(5M STBY) LOW */
+	ret = gpio_direction_output(GPIO_5M_CAM_nSTBY, 0);
+	CAM_CHECK_ERR_RET(ret, "low 5M_CAM_nSTBY");
+
+	/* CAM_AF_2.8V */
+	regulator = regulator_get(NULL, "cam_af_2.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "disable cam_af_2.8v");
+
+	/* CAM_DVDD_1.5V(1.3M Core 1.8V) */
+	regulator = regulator_get(NULL, "cam_dvdd_1.5v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "disable cam_dvdd_1.5v");
+
+	/* CAM_SENSOR_IO_1.8V */
+	regulator = regulator_get(NULL, "cam_sensor_io_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "disable cam_sensor_io_1.8v");
+
+	/* CAM_SENSOR_A2.8V */
+	regulator = regulator_get(NULL, "cam_sensor_a2.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "disable cam_sensor_a2.8v");
+
+	/* CAM_ISP_CORE_1.2V */
+	regulator = regulator_get(NULL, "cam_isp_core_1.2v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "disable cam_isp_core_1.2v");
+
+	gpio_free(GPIO_VT_CAM_nSTBY);
+	gpio_free(GPIO_CAM_VT_nRST);
+	gpio_free(GPIO_5M_CAM_RESET);
+	gpio_free(GPIO_5M_CAM_nSTBY);
+
+	return ret;
+}
+
+static int s5k4ecgx_power(int enable)
+{
+	int ret = 0;
+
+	pr_info("%s %s", __func__, enable ? "on" : "down");
+
+	if (enable) {
+		ret = s5k4ecgx_power_on();
+
+		if (unlikely(ret))
+			goto error_out;
+	} else
+		ret = s5k4ecgx_power_down();
+
+	ret = s3c_csis_power(enable);
+
+error_out:
+	return ret;
+}
+
+static int s5k4ecgx_get_i2c_busnum(void)
+{
+	/* HW I2C Num 0 */
+	return 0;
+}
+
+static const char *s5k4ecgx_get_clk_name(void)
+{
+	return "sclk_cam0";
+}
+
+static struct s5k4ecgx_platform_data s5k4ecgx_plat = {
+	.default_width = 640,
+	.default_height = 480,
+	.pixelformat = V4L2_PIX_FMT_UYVY,
+	.freq = 24000000,
+	.is_mipi = 1,
+	.flash_ctrl = max77693_led_ctrl,
+};
+
+static struct i2c_board_info s5k4ecgx_i2c_info = {
+	I2C_BOARD_INFO("S5K4ECGX", 0xAC >> 1),
+	.platform_data = &s5k4ecgx_plat,
+};
+
+static struct s3c_platform_camera s5k4ecgx = {
+	.id = CAMERA_CSI_C,
+	.type = CAM_TYPE_MIPI,
+	.fmt = MIPI_CSI_YCBCR422_8BIT, /*ITU_601_YCBCR422_8BIT,*/
+	.order422 = CAM_ORDER422_8BIT_CBYCRY,
+	.mipi_lanes = 2,
+	.mipi_settle = 12, /* only CONFIG_MIPI_CSI_ADV_FEATURE */
+	.mipi_align = 32, /* only CONFIG_MIPI_CSI_ADV_FEATURE */
+
+	.get_i2c_busnum = s5k4ecgx_get_i2c_busnum,
+	.get_clk_name = s5k4ecgx_get_clk_name,
+	.info = &s5k4ecgx_i2c_info,
+	.pixelformat = V4L2_PIX_FMT_VYUY,
+	.srclk_name = "xusbxti",
+	.clk_rate = 24000000,
+	.line_length = 640,
+	.width = 640,
+	.height = 480,
+	.window = {
+		.left = 0,
+		.top = 0,
+		.width = 640,
+		.height = 480,
+	},
+
+	/* Polarity */
+	.inv_pclk = 0,
+	.inv_vsync = 1,
+	.inv_href = 0,
+	.inv_hsync = 0,
+	.reset_camera = 0,
+	.initialized = 0,
+	.cam_power = s5k4ecgx_power,
+};
+
+
+static int db8131m_gpio_request(void)
+{
+	int ret = 0;
+
+	ret = gpio_request(GPIO_VT_CAM_nSTBY, "GPM0");
+	if (ret) {
+		pr_err("faile to request gpio(GPIO_VT_CAM_nSTBY)");
+		return ret;
+	}
+
+	ret = gpio_request(GPIO_CAM_VT_nRST, "GPM1");
+	if (ret) {
+		pr_err("faile to request gpio(GPIO_CAM_VT_nRST)");
+		return ret;
+	}
+
+	ret = gpio_request(GPIO_VT_CAM_ID, "GPF1");
+	if (ret) {
+		pr_err("faile to request gpio(GPIO_VT_CAM_ID)");
+		return ret;
+	}
+
+	return ret;
+}
+
+static int db8131m_power_on(void)
+{
+	struct regulator *regulator;
+	int ret = 0;
+
+	pr_debug("%s: in", __func__);
+
+	db8131m_gpio_request();
+
+	/* 5M_CAM_nSTBY(5M STBY) LOW */
+	ret = gpio_request(GPIO_5M_CAM_nSTBY, "GPM0");
+	if (ret) {
+		pr_err("faile to request gpio(GPIO_5M_CAM_nSTBY)");
+		return ret;
+	}
+	ret = gpio_direction_output(GPIO_5M_CAM_nSTBY, 0);
+	CAM_CHECK_ERR_RET(ret, "low 5M_CAM_nSTBY");
+
+	/* 5M_CAM_RESET(5M RESET) LOW */
+	ret = gpio_request(GPIO_5M_CAM_RESET, "GPF1");
+	if (ret) {
+		pr_err("faile to request gpio(GPIO_5M_CAM_RESET)");
+		return ret;
+	}
+	ret = gpio_direction_output(GPIO_5M_CAM_RESET, 0);
+	CAM_CHECK_ERR_RET(ret, "low 5M_CAM_RESET");
+
+	/* VT_CAM_1.8V(VDDIO) */
+	regulator = regulator_get(NULL, "vt_cam_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "enable vt_cam_1.8v");
+
+	/* CAM_SENSOR_A2.8V */
+	regulator = regulator_get(NULL, "cam_sensor_a2.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "enable cam_sensor_a2.8v");
+
+	/* CAM_DVDD_1.5V(1.3M Core 1.8V) */
+	regulator = regulator_get(NULL, "cam_dvdd_1.5v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "enable cam_dvdd_1.5v");
+
+	/* CAM_ISP_CORE_1.2V ENABLE */
+	regulator = regulator_get(NULL, "cam_isp_core_1.2v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	ret = regulator_enable(regulator);
+	CAM_CHECK_ERR_RET(ret, "enable cam_isp_core_1.2v");
+
+	mdelay(2);		/* 1ms */
+
+	/* CAM_ISP_CORE_1.2V DISABLE */
+	ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "disable cam_isp_core_1.2v");
+
+	/* VT_CAM_nSTBY(1.3M EN) EN */
+	ret = gpio_direction_output(GPIO_VT_CAM_nSTBY, 1);
+	CAM_CHECK_ERR_RET(ret, "high VT_CAM_nSTBY");
+
+	/* MCLK */
+	ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_SFN(2));
+	CAM_CHECK_ERR_RET(ret, "cfg mclk");
+	s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_NONE);
+
+	mdelay(1);		/* 20us */
+
+	/* CAM_VT_nRST(1.3M RESET) EN */
+	ret = gpio_direction_output(GPIO_CAM_VT_nRST, 1);
+	CAM_CHECK_ERR_RET(ret, "high CAM_VT_nRST");
+
+	mdelay(5);		/* 70000 cycle */
+
+	gpio_free(GPIO_5M_CAM_nSTBY);
+	gpio_free(GPIO_5M_CAM_RESET);
+	gpio_free(GPIO_VT_CAM_nSTBY);
+	gpio_free(GPIO_CAM_VT_nRST);
+	gpio_free(GPIO_VT_CAM_ID);
+
+	return ret;
+}
+
+static int db8131m_power_down(void)
+{
+	struct regulator *regulator;
+	int ret = 0;
+
+	pr_debug("%s: in", __func__);
+
+	db8131m_gpio_request();
+
+	/* VT_CAM_nSTBY(1.3M EN) DIS */
+	ret = gpio_direction_output(GPIO_VT_CAM_nSTBY, 0);
+	CAM_CHECK_ERR_RET(ret, "low VT_CAM_nSTBY");
+
+	/* CAM_VT_nRST(1.3M RESET) DIS */
+	ret = gpio_direction_output(GPIO_CAM_VT_nRST, 0);
+	CAM_CHECK_ERR_RET(ret, "low CAM_VT_nRST");
+
+	/* MCLK */
+	ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_DOWN);
+	CAM_CHECK_ERR(ret, "cfg mclk");
+
+	/* CAM_DVDD_1.5V(1.3M Core 1.8V) */
+	regulator = regulator_get(NULL, "cam_dvdd_1.5v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "disable cam_dvdd_1.5v");
+
+	/* CAM_SENSOR_A2.8V */
+	regulator = regulator_get(NULL, "cam_sensor_a2.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "disable cam_sensor_a2.8v");
+
+	/* VT_CAM_1.8V(VDDIO) */
+	regulator = regulator_get(NULL, "vt_cam_1.8v");
+	if (IS_ERR(regulator))
+		return -ENODEV;
+	if (regulator_is_enabled(regulator))
+		ret = regulator_force_disable(regulator);
+	regulator_put(regulator);
+	CAM_CHECK_ERR_RET(ret, "disable vt_cam_1.8v");
+
+	gpio_free(GPIO_VT_CAM_nSTBY);
+	gpio_free(GPIO_CAM_VT_nRST);
+	gpio_free(GPIO_VT_CAM_ID);
+
+	return ret;
+}
+
+static int db8131m_power(int enable)
+{
+	int ret = 0;
+
+	pr_err("%s %s", __func__, enable ? "on" : "down");
+
+	if (enable) {
+		ret = db8131m_power_on();
+
+		if (unlikely(ret))
+			goto error_out;
+	} else
+		ret = db8131m_power_down();
+
+	ret = s3c_csis_power(enable);
+
+error_out:
+	return ret;
+}
+
+static int db8131m_get_i2c_busnum(void)
+{
+	/* SW gpio I2C Num 20 */
+	return 20; /*I2C_VTCAM*/
+}
+
+static const char *db8131m_get_clk_name(void)
+{
+	return "sclk_cam0";
+}
+
+static struct s5k4ecgx_platform_data db8131m_plat = {
+	.default_width = 640,
+	.default_height = 480,
+	.pixelformat = V4L2_PIX_FMT_UYVY,
+	.freq = 24000000,
+	.is_mipi = 1,
+};
+
+static struct i2c_board_info db8131m_i2c_info = {
+	I2C_BOARD_INFO("DB8131M", 0x8A >> 1),
+	.platform_data = &db8131m_plat,
+};
+
+static struct s3c_platform_camera db8131m = {
+	.id = CAMERA_CSI_D,
+	.type = CAM_TYPE_MIPI,
+	.fmt = MIPI_CSI_YCBCR422_8BIT, /*ITU_601_YCBCR422_8BIT,*/
+	.order422 = CAM_ORDER422_8BIT_CBYCRY,
+	.mipi_lanes = 1,
+	.mipi_settle = 12, /* only CONFIG_MIPI_CSI_ADV_FEATURE */
+	.mipi_align = 32, /* only CONFIG_MIPI_CSI_ADV_FEATURE */
+
+	.get_i2c_busnum = db8131m_get_i2c_busnum,
+	.get_clk_name	= db8131m_get_clk_name,
+	.info = &db8131m_i2c_info,
+	.pixelformat = V4L2_PIX_FMT_UYVY,
+	.srclk_name = "xusbxti",
+	.clk_rate = 24000000,
+	.line_length = 640,
+	.width = 640,
+	.height = 480,
+	.window = {
+		.left = 0,
+		.top = 0,
+		.width = 640,
+		.height = 480,
+	},
+
+	/* Polarity */
+	.inv_pclk = 0,
+	.inv_vsync = 0,
+	.inv_href = 0,
+	.inv_hsync = 0,
+	.reset_camera = 0,
+	.initialized = 0,
+	.cam_power = db8131m_power,
+};
+
+/* Interface setting */
+static struct s3c_platform_fimc fimc_plat = {
+	.default_cam = CAMERA_CSI_C,
+#ifdef WRITEBACK_ENABLED
+	.default_cam = CAMERA_WB,
+#endif
+	.camera = {
+		&s5k4ecgx, /* 5M CAM */
+		&db8131m, /* 1.3M CAM */
+#ifdef WRITEBACK_ENABLED
+		&writeback,
+#endif
+	},
+	.hw_ver		= 0x51,
+};
+#endif /* CONFIG_VIDEO_FIMC */
+
+static ssize_t s5k4ecgx_camera_rear_flash(struct device *dev,
+	struct device_attribute *attr, const char *buf,
+	size_t count)
+{
+	int err = 0;
+
+	if (buf[0] == '0')
+		err = max77693_led_ctrl(CAM_FLASH_OFF);
+	else
+		err = max77693_led_ctrl(CAM_FLASH_TORCH);
+
+	if (err < 0)
+		pr_err("failed to s5k4ecgx_camera_rear_flash!\n");
+
+	return count;
+}
+
+ssize_t s5k4ecgx_camera_type_show(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	char *cam_type;
+	pr_info("%s\n", __func__);
+
+	cam_type = "SLSI_S5K4ECGX";
+
+	return sprintf(buf, "%s\n", cam_type);
+}
+
+static ssize_t s5k4ecgx_camera_rear_camfw_show(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	char *fw_type;
+	pr_info("%s\n", __func__);
+
+	fw_type = "fw is not supported";
+
+	return sprintf(buf, "%s\n", fw_type);
+}
+static DEVICE_ATTR(rear_flash, S_IWUSR | S_IWGRP, NULL,
+		s5k4ecgx_camera_rear_flash);
+static DEVICE_ATTR(rear_camtype, S_IRUGO,
+	s5k4ecgx_camera_type_show, NULL);
+static DEVICE_ATTR(rear_camfw, S_IRUGO,
+	s5k4ecgx_camera_rear_camfw_show, NULL);
+
+ssize_t db8131m_camera_type_show(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	char *cam_type;
+	pr_info("%s\n", __func__);
+
+	cam_type = "Dongbu_DB8131M";
+
+	return sprintf(buf, "%s\n", cam_type);
+}
+
+static ssize_t db8131m_camera_rear_camfw_show(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	char *fw_type;
+	pr_info("%s\n", __func__);
+
+	fw_type = "fw is not supported";
+
+	return sprintf(buf, "%s\n", fw_type);
+}
+static DEVICE_ATTR(front_camtype, S_IRUGO,
+	db8131m_camera_type_show, NULL);
+static DEVICE_ATTR(front_camfw, S_IRUGO,
+	db8131m_camera_rear_camfw_show, NULL);
+
+void __init midas_camera_init(void)
+{
+#ifdef CONFIG_VIDEO_FIMC
+	s3c_fimc0_set_platdata(&fimc_plat);
+	s3c_fimc1_set_platdata(&fimc_plat);
+	s3c_fimc2_set_platdata(NULL);
+	s3c_fimc3_set_platdata(NULL);
+#ifdef CONFIG_EXYNOS_DEV_PD
+	s3c_device_fimc0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+	s3c_device_fimc1.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+	s3c_device_fimc2.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+	s3c_device_fimc3.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+#endif
+#ifdef CONFIG_VIDEO_FIMC_MIPI
+	s3c_csis0_set_platdata(NULL);
+	s3c_csis1_set_platdata(NULL);
+#ifdef CONFIG_EXYNOS_DEV_PD
+	s3c_device_csis0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+	s3c_device_csis1.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+#endif
+#endif
+#endif /* CONFIG_VIDEO_FIMC */
+
+	camera_class = class_create(THIS_MODULE, "camera");
+
+	if (!s5k4ecgx_dev) {
+		s5k4ecgx_dev = device_create(camera_class,
+				NULL, 0, NULL, "rear");
+		if (IS_ERR(s5k4ecgx_dev)) {
+			pr_err("s5k4ecgx_dev : failed to create device!\n");
+		} else {
+			if (device_create_file(s5k4ecgx_dev,
+				&dev_attr_rear_flash) < 0) {
+				pr_err("failed to create device file, %s\n",
+					dev_attr_rear_flash.attr.name);
+			}
+			if (device_create_file(s5k4ecgx_dev,
+				&dev_attr_rear_camtype)
+					< 0) {
+				pr_err("failed to create device file, %s\n",
+					dev_attr_rear_camtype.attr.name);
+			}
+			if (device_create_file(s5k4ecgx_dev,
+				&dev_attr_rear_camfw) < 0) {
+				pr_err("failed to create device file, %s\n",
+					dev_attr_rear_camfw.attr.name);
+			}
+		}
+	}
+	if (!db8131m_dev) {
+		db8131m_dev = device_create(camera_class,
+				NULL, 0, NULL, "front");
+		if (IS_ERR(db8131m_dev)) {
+			pr_err("db8131m_dev : failed to create device!\n");
+		} else {
+			if (device_create_file(db8131m_dev,
+				&dev_attr_front_camtype)
+					< 0) {
+				pr_err("failed to create device file, %s\n",
+					dev_attr_front_camtype.attr.name);
+			}
+			if (device_create_file(db8131m_dev,
+				&dev_attr_front_camfw) < 0) {
+				pr_err("failed to create device file, %s\n",
+					dev_attr_front_camfw.attr.name);
+			}
+		}
+	}
+}
diff --git a/arch/arm/mach-exynos/naples-gpio.c b/arch/arm/mach-exynos/naples-gpio.c
new file mode 100644
index 0000000..145197c
--- /dev/null
+++ b/arch/arm/mach-exynos/naples-gpio.c
@@ -0,0 +1,1424 @@
+/*
+ *  linux/arch/arm/mach-exynos/naples-gpio.c
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * EXYNOS - GPIO setting in set board
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/gpio.h>
+#include <linux/serial_core.h>
+#include <plat/devs.h>
+#include <plat/gpio-cfg.h>
+#include <plat/regs-serial.h>
+#include <mach/gpio-naples.h>
+#include <plat/cpu.h>
+#include <mach/pmu.h>
+
+static struct gpio_init_data {
+	uint num;
+	uint cfg;
+	uint val;
+	uint pud;
+	uint drv;
+};
+
+/* this is sample code for midas board */
+static struct gpio_init_data midas_init_gpios[] = {
+	{EXYNOS4_GPD0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* CODEC_SDA_1.8V */
+	{EXYNOS4_GPD0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* CODEC_SCL_1.8V */
+#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) || \
+	defined(CONFIG_MACH_M3) || defined(CONFIG_MACH_C1CTC)
+	{EXYNOS4_GPD1(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* NFC_SDA_1.8V */
+	{EXYNOS4_GPD1(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* NFC_SCL_1.8V */
+#endif
+	{EXYNOS4_GPD1(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* GSENSE_SDA_1.8V */
+	{EXYNOS4_GPD1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* GSENSE_SCL_1.8V */
+
+	{EXYNOS4_GPX0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* EAR_DET */
+	{EXYNOS4_GPX0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* PS_ALS_INT */
+	{EXYNOS4_GPX0(7), S3C_GPIO_SFN(0xF), S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* AP_PMIC_IRQ */
+
+	{EXYNOS4_GPX1(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* NFC_IRQ */
+
+	{EXYNOS4_GPX2(0), S3C_GPIO_SFN(2), S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* VOL_UP */
+	{EXYNOS4_GPX2(1), S3C_GPIO_SFN(2), S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* VOL_DOWN */
+	{EXYNOS4_GPX2(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* FUEL_ALERT */
+	{EXYNOS4_GPX2(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* ADC_INT */
+	{EXYNOS4_GPX2(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* BT_HOST_WAKEUP */
+
+	{EXYNOS4_GPX3(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WPC_INT */
+	{EXYNOS4_GPX3(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* BT_WAKE */
+
+	{EXYNOS4212_GPJ0(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_ZERO,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV4}, /* WLAN_EN */
+	{EXYNOS4_GPK3(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_CMD */
+	{EXYNOS4_GPK3(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(0) */
+	{EXYNOS4_GPK3(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(1) */
+	{EXYNOS4_GPK3(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(2) */
+	{EXYNOS4_GPK3(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(3) */
+
+};
+
+/* this table only for midas board */
+static unsigned int exynos4_sleep_gpio_table_common[][3] = {
+	{EXYNOS4_GPA0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+	{EXYNOS4_GPA0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+
+	{EXYNOS4_GPA1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPB(0),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(1),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(2),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(3),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(4),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPB(5),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+	{EXYNOS4_GPB(6),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPB(7),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPC0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPC0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPC0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPC0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPC0(4),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPC1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPC1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPC1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPC1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPC1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPD0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPD0(1),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPD0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPD0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPD1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPD1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPD1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPD1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPF0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPF0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPF1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) || \
+	defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_M3) || \
+	defined(CONFIG_MACH_SLP_NAPLES)
+	/* GPF1(6) M0, C1 PDA_ACTIVE, let cp know AP sleep status*/
+	{EXYNOS4_GPF1(6),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4_GPF1(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+	{EXYNOS4_GPF1(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPF2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF2(3),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_DOWN}, /*UART_SEL*/
+	{EXYNOS4_GPF2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF2(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF2(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPF3(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF3(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF3(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF3(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF3(4),  S3C_GPIO_SLP_OUT1,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF3(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPK0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPK1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK1(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPK2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPK3(0),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPK3(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPL0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#if defined(CONFIG_MACH_S2PLUS)
+	{EXYNOS4_GPL0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+#else
+	{EXYNOS4_GPL0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL0(3),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+#endif
+	{EXYNOS4_GPL0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPL0(5),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL0(6),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL0(7),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+#if defined(CONFIG_MACH_S2PLUS)
+	{EXYNOS4_GPL1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+#else
+	{EXYNOS4_GPL1(0),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+#endif
+	{EXYNOS4_GPL1(2),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPL2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPL2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPL2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) || \
+	defined(CONFIG_MACH_M3) || defined(CONFIG_MACH_C1CTC)
+	/* GLP2(4) CMC_CPU_RESET, hold high */
+	{EXYNOS4_GPL2(4),  S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* NC */
+#else
+	{EXYNOS4_GPL2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+	{EXYNOS4_GPL2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL2(6),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL2(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+#if defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_SLP_NAPLES) || \
+	defined(CONFIG_MACH_JENGA) || defined(CONFIG_MACH_S2PLUS)
+	/* GPX3(2) M0 CP_PMU_RESET, hold high */
+	{EXYNOS4_GPX3(2),  S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE},
+#else
+#endif
+
+	{EXYNOS4_GPY0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPY1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPY3(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY3(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY3(4),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+#if defined(CONFIG_MACH_S2PLUS)
+	{EXYNOS4_GPY3(5),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4_GPY3(5),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+#endif
+	{EXYNOS4_GPY3(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY3(7),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPY4(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+#if defined(CONFIG_MACH_S2PLUS)
+	/* GPY4(2) S2Plus PDA_ACTIVE, let cp know AP sleep status*/
+	{EXYNOS4_GPY4(2),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4_GPY4(2),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+#endif
+	{EXYNOS4_GPY4(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+#if defined(CONFIG_MACH_S2PLUS)
+	{EXYNOS4_GPY4(5),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(6),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(7),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4_GPY4(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY4(6),  S3C_GPIO_SLP_OUT1,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(7),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+#endif
+
+	{EXYNOS4_GPY5(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY5(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY5(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY5(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY5(4),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	/* PMIC_DVS1(Q) / NC(D) */
+	{EXYNOS4_GPY5(5),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+	/* PMIC_DVS2(Q) / NC(D) */
+	{EXYNOS4_GPY5(6),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+	/* PMIC_DVS3(Q) / NC(D) */
+	{EXYNOS4_GPY5(7),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+
+	/* BUCK2_SEL(Q) / NC(D) */
+	{EXYNOS4_GPY6(0),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY6(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	/* BUCK3_SEL(Q) / NC(D) */
+	{EXYNOS4_GPY6(3),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+	/* BUCK4_SEL(Q) / NC(D) */
+	{EXYNOS4_GPY6(4),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY6(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+	{EXYNOS4_GPY6(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPZ(0),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPZ(1),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPZ(2),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPZ(3),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPZ(4),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPZ(5),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPZ(6),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+};
+
+static unsigned int exynos4210_sleep_gpio_table[][3] = {
+	{EXYNOS4210_GPE0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4210_GPE1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE1(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE1(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4210_GPE2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4210_GPE3(0),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE3(1),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE3(2),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE3(3),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE3(4),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE3(5),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE3(6),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE3(7),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4210_GPE4(0),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE4(1),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE4(2),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE4(3),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE4(4),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE4(5),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE4(6),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE4(7),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4210_GPJ0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPJ0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPJ0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPJ0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPJ0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPJ0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPJ0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPJ0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4210_GPJ1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPJ1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPJ1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPJ1(3),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPJ1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+};
+
+static unsigned int exynos4212_sleep_gpio_table[][3] = {
+	{EXYNOS4212_GPJ0(0),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4212_GPJ0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPJ0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPJ0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPJ0(4),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+#if defined(CONFIG_MACH_S2PLUS)
+	{EXYNOS4212_GPJ0(5),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4212_GPJ0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+#endif
+	{EXYNOS4212_GPJ0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPJ0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPJ1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4212_GPJ1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPJ1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPJ1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPJ1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPM0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPM1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM1(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPM2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPM2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPM3(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM3(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM3(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#if defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_SLP_PQ) || \
+	defined(CONFIG_MACH_JENGA) || defined(CONFIG_MACH_S2PLUS) || \
+	defined(CONFIG_MACH_SLP_NAPLES)
+	/* GPM3(3) M0, CP_RESET_REQ hold high */
+	{EXYNOS4212_GPM3(3),  S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_DOWN},
+#else
+	{EXYNOS4212_GPM3(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+	{EXYNOS4212_GPM3(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM3(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	/* ISP_TXD */
+	{EXYNOS4212_GPM3(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM3(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	/* ISP_RXD */
+
+	{EXYNOS4212_GPM4(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM4(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM4(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	/* VT_CAM_SCL */
+	{EXYNOS4212_GPM4(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	/* VT_CAM_SDA */
+	{EXYNOS4212_GPM4(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#if defined(CONFIG_MACH_S2PLUS)
+	{EXYNOS4212_GPM4(5),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	/* MICBAS_EN */
+	{EXYNOS4212_GPM4(6),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	/* SUB_MICBIAS_EN */
+#else
+	{EXYNOS4212_GPM4(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM4(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+	{EXYNOS4212_GPM4(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPV0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPV1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPV2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPV3(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPV4(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV4(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+};
+
+static unsigned int exynos4212_sleep_gpio_table_c2c[][3] = {
+	{EXYNOS4212_GPJ0(0),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4212_GPJ0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPJ0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPJ0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPJ0(4),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4212_GPJ0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPJ0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPJ0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPJ1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4212_GPJ1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPJ1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPJ1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPJ1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPM0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPM1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM1(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPM2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPM2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPM3(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM3(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM3(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM3(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM3(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM3(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	/* ISP_TXD */
+	{EXYNOS4212_GPM3(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM3(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	/* ISP_RXD */
+
+	{EXYNOS4212_GPM4(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM4(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM4(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	/* VT_CAM_SCL */
+	{EXYNOS4212_GPM4(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	/* VT_CAM_SDA */
+	{EXYNOS4212_GPM4(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM4(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM4(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM4(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPV0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPV1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPV2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPV3(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPV4(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV4(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+};
+
+/*
+ * M0 GPIO Init Table
+ */
+static struct gpio_init_data m0_init_gpios[] = {
+	{EXYNOS4_GPA1(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4_GPA1(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+
+	{EXYNOS4_GPD0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPD0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1},
+#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) || \
+	defined(CONFIG_MACH_C1CTC)
+	{EXYNOS4_GPD1(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* NFC_SDA_1.8V */
+	{EXYNOS4_GPD1(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* NFC_SCL_1.8V */
+#endif
+	{EXYNOS4_GPD1(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* GSENSE_SDA_1.8V */
+	{EXYNOS4_GPD1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* GSENSE_SCL_1.8V */
+
+	{EXYNOS4_GPX0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* EAR_DET */
+	{EXYNOS4_GPX0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* PS_ALS_INT */
+	{EXYNOS4_GPX0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPX0(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPX0(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPX0(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+
+	{EXYNOS4_GPX0(7), S3C_GPIO_SFN(0xF), S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* AP_PMIC_IRQ */
+
+	{EXYNOS4_GPX1(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPX1(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* NFC_IRQ */
+
+	{EXYNOS4_GPX2(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPX2(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPX2(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* FUEL_ALERT */
+	{EXYNOS4_GPX2(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* ADC_INT */
+	{EXYNOS4_GPX2(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* BT_HOST_WAKEUP */
+
+	{EXYNOS4_GPX3(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WPC_INT */
+	{EXYNOS4_GPX3(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* BT_WAKE */
+	{EXYNOS4_GPX3(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+
+	{EXYNOS4212_GPJ0(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_ZERO,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV4}, /* WLAN_EN */
+	{EXYNOS4_GPK3(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_CMD */
+	{EXYNOS4_GPK3(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(0) */
+	{EXYNOS4_GPK3(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(1) */
+	{EXYNOS4_GPK3(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(2) */
+	{EXYNOS4_GPK3(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(3) */
+
+	{EXYNOS4_GPY0(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4_GPY0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4_GPY0(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4_GPY0(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4_GPY1(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4_GPY1(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4_GPY1(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4_GPY1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4_GPY2(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+
+	{EXYNOS4212_GPJ1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV3}, /* CAM_MCLK */
+};
+
+/*
+ * M0 GPIO Sleep Table
+ */
+static unsigned int m0_sleep_gpio_table[][3] = {
+	{EXYNOS4_GPA0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+	{EXYNOS4_GPA0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+
+	{EXYNOS4_GPA1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPB(0),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(1),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(2),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(3),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(4),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPB(5),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+	{EXYNOS4_GPB(6),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPB(7),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPC0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPC0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPC0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPC0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPC0(4),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPC1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPC1(1),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* FM_RST */
+	{EXYNOS4_GPC1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPC1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPC1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPD0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPD0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPD0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPD0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPD1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPD1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPD1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPD1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPF0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPF0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPF0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPF0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPF0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPF0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPF1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW)
+	/* CMC221 Active States */
+	{EXYNOS4_GPF1(1),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_DOWN}, /* NC */
+#else
+	{EXYNOS4_GPF1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+	{EXYNOS4_GPF1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPF1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) || \
+	defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_SLP_NAPLES)
+	/* GPF1(6) M0, C1 PDA_ACTIVE, let cp know AP sleep status*/
+	{EXYNOS4_GPF1(6),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4_GPF1(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+	{EXYNOS4_GPF1(7),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NC */
+
+	{EXYNOS4_GPF2(0),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPF2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF2(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF2(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPF3(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPF3(1),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPF3(2),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPF3(3),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPF3(4),  S3C_GPIO_SLP_OUT1,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF3(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPK0(0),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	/* NAND_CLK */
+	{EXYNOS4_GPK0(1),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	/* NAND_CMD */
+	{EXYNOS4_GPK0(2),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* eMMC_EN */
+	{EXYNOS4_GPK0(3),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	/* NAND_D(0) */
+	{EXYNOS4_GPK0(4),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	/* NAND_D(1) */
+	{EXYNOS4_GPK0(5),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	/* NAND_D(2) */
+	{EXYNOS4_GPK0(6),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	/* NAND_D(3) */
+
+	{EXYNOS4_GPK1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK1(3),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	/* NAND_D(4) */
+	{EXYNOS4_GPK1(4),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	/* NAND_D(5) */
+	{EXYNOS4_GPK1(5),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	/* NAND_D(6) */
+	{EXYNOS4_GPK1(6),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	/* NAND_D(7) */
+
+	{EXYNOS4_GPK2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPK3(0),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPK3(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPL0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPL0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL0(3),  S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL0(4),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* NC */
+/*	{EXYNOS4_GPL0(5),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE}, */
+	{EXYNOS4_GPL0(6),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+/*	{EXYNOS4_GPL0(7),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE}, */
+
+	{EXYNOS4_GPL1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+/*	{EXYNOS4_GPL1(2),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE}, */
+
+	{EXYNOS4_GPL2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPL2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPL2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) || \
+	defined(CONFIG_MACH_C1CTC)
+	/* GLP2(4) CMC_CPU_RESET, hold high */
+	{EXYNOS4_GPL2(4),  S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* NC */
+#else
+	{EXYNOS4_GPL2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+	{EXYNOS4_GPL2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL2(6),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL2(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPY0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPY0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPY0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPY1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY2(0),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* TF_EN */
+	{EXYNOS4_GPY2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPY3(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY3(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY3(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY3(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY3(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY3(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY3(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY3(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPY4(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY4(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY4(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY4(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY4(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY4(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY4(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY4(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPY5(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPY6(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPZ(0),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPZ(1),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPZ(2),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPZ(3),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPZ(4),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPZ(5),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPZ(6),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	/* Exynos4212 specific gpio */
+	{EXYNOS4212_GPJ0(0),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4212_GPJ0(1),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_DOWN},/*USB_SEL*/
+	{EXYNOS4212_GPJ0(2),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	{EXYNOS4212_GPJ0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPJ0(4),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+#if defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_C1) ||\
+	defined(CONFIG_MACH_C1VZW) || defined(CONFIG_MACH_C1ATT) ||\
+	defined(CONFIG_MACH_S2PLUS)
+	/* GPIO_PS_ALS_EN */
+	{EXYNOS4212_GPJ0(5),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4212_GPJ0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+	{EXYNOS4212_GPJ0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPJ0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPJ1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPJ1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPJ1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPJ1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPJ1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPM0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPM1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4212_GPM1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4212_GPM1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4212_GPM1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4212_GPM1(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPM2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4212_GPM2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4212_GPM2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPM2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPM3(0),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4212_GPM3(1),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4212_GPM3(2),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* NC */
+#if defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_SLP_NAPLES)
+	/* GPM3(3) M0, CP_RESET_REQ hold high */
+	{EXYNOS4212_GPM3(3),  S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4212_GPM3(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+	{EXYNOS4212_GPM3(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM3(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	/* ISP_TXD */
+	{EXYNOS4212_GPM3(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM3(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	/* ISP_RXD */
+
+	{EXYNOS4212_GPM4(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM4(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM4(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	/* VT_CAM_SCL */
+	{EXYNOS4212_GPM4(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	/* VT_CAM_SDA */
+	{EXYNOS4212_GPM4(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM4(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM4(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM4(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPV0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPV1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPV2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPV3(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPV4(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV4(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+}; /* m0_sleep_gpio_table */
+
+/*
+ * S2Plus GPIO Sleep Table
+ */
+static unsigned int s2plus_sleep_gpio_table[][3] = {
+	{EXYNOS4_GPA0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+	{EXYNOS4_GPA0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+
+	{EXYNOS4_GPA1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPB(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPB(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPB(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPB(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPC0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPC0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPC0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPC0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPC0(4), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPC1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPC1(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* FM_RST */
+	{EXYNOS4_GPC1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPC1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPC1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPD0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPD0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPD0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPD0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPD1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPD1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPD1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPD1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPF0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF1(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF1(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF3(4), S3C_GPIO_SLP_OUT1,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK0(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	/* NAND_CLK */
+	{EXYNOS4_GPK0(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	/* NAND_CMD */
+	{EXYNOS4_GPK0(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	/* eMMC_EN */
+	{EXYNOS4_GPK0(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	/* NAND_D(0) */
+	{EXYNOS4_GPK0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	/* NAND_D(1) */
+	{EXYNOS4_GPK0(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	/* NAND_D(2) */
+	{EXYNOS4_GPK0(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	/* NAND_D(3) */
+	{EXYNOS4_GPK1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK1(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	/* NAND_D(4) */
+	{EXYNOS4_GPK1(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	/* NAND_D(5) */
+	{EXYNOS4_GPK1(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	/* NAND_D(6) */
+	{EXYNOS4_GPK1(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	/* NAND_D(7) */
+	{EXYNOS4_GPK2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPK3(0), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPK3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPL0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPL0(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL0(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL0(3), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL0(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPL0(6), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPL1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPL2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL2(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL2(6), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPY0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPY0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPY0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPY1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY2(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* TF_EN */
+	{EXYNOS4_GPY2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPY3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY3(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPY4(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPY5(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPY6(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPZ(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPZ(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPZ(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPZ(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPZ(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPZ(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPZ(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	/* Exynos4212 specific gpio */
+	{EXYNOS4212_GPJ0(0),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4212_GPJ0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPJ0(2),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	{EXYNOS4212_GPJ0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPJ0(4),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4212_GPJ0(5),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	{EXYNOS4212_GPJ0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPJ0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPJ1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPJ1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPJ1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPJ1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPJ1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPM0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(6),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	{EXYNOS4212_GPM0(7),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4212_GPM1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4212_GPM1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4212_GPM1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4212_GPM1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4212_GPM1(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPM2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4212_GPM2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4212_GPM2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPM2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPM3(0),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4212_GPM3(1),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4212_GPM3(2),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* NC */
+	/* GPM3(3) M0, CP_RESET_REQ hold high */
+	{EXYNOS4212_GPM3(3),  S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE},
+	{EXYNOS4212_GPM3(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM3(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	/* ISP_TXD */
+	{EXYNOS4212_GPM3(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM3(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	/* ISP_RXD */
+
+	{EXYNOS4212_GPM4(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM4(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM4(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	/* VT_CAM_SCL */
+	{EXYNOS4212_GPM4(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	/* VT_CAM_SDA */
+	{EXYNOS4212_GPM4(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM4(5),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	{EXYNOS4212_GPM4(6),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	{EXYNOS4212_GPM4(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4212_GPV0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPV1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPV2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPV3(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPV4(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV4(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+}; /* S2Plus_sleep_gpio_table */
+
+
+static void config_sleep_gpio_table(int array_size,
+				    unsigned int (*gpio_table)[3])
+{
+	u32 i, gpio;
+
+	for (i = 0; i < array_size; i++) {
+		gpio = gpio_table[i][0];
+		s3c_gpio_slp_cfgpin(gpio, gpio_table[i][1]);
+		s3c_gpio_slp_setpull_updown(gpio, gpio_table[i][2]);
+	}
+}
+
+/* To save power consumption, gpio pin set before enterling sleep */
+void midas_config_sleep_gpio_table(void)
+{
+#ifdef CONFIG_NAPLES_COMMON
+	config_sleep_gpio_table(ARRAY_SIZE(m0_sleep_gpio_table),
+			m0_sleep_gpio_table);
+#else
+	config_sleep_gpio_table(ARRAY_SIZE(exynos4_sleep_gpio_table_common),
+			exynos4_sleep_gpio_table_common);
+
+	if (!soc_is_exynos4210()) {
+		if (exynos4_is_c2c_use()) {
+			config_sleep_gpio_table(
+				ARRAY_SIZE(exynos4212_sleep_gpio_table_c2c),
+				exynos4212_sleep_gpio_table_c2c);
+		} else {
+			config_sleep_gpio_table(
+				ARRAY_SIZE(exynos4212_sleep_gpio_table),
+				exynos4212_sleep_gpio_table);
+		}
+	} else {
+		config_sleep_gpio_table(ARRAY_SIZE(exynos4210_sleep_gpio_table),
+			exynos4210_sleep_gpio_table);
+	}
+#endif
+}
+
+/* Intialize gpio set in midas board */
+void midas_config_gpio_table(void)
+{
+	u32 i, gpio;
+
+	pr_debug("%s\n", __func__);
+
+	for (i = 0; i < ARRAY_SIZE(m0_init_gpios); i++) {
+		gpio = m0_init_gpios[i].num;
+		if (gpio <= EXYNOS4212_GPV4(1)) {
+			s3c_gpio_cfgpin(gpio, m0_init_gpios[i].cfg);
+			s3c_gpio_setpull(gpio, m0_init_gpios[i].pud);
+
+			if (m0_init_gpios[i].val != S3C_GPIO_SETPIN_NONE)
+				gpio_set_value(gpio, m0_init_gpios[i].val);
+
+			s5p_gpio_set_drvstr(gpio, m0_init_gpios[i].drv);
+		}
+	}
+}
diff --git a/arch/arm/mach-exynos/naples-power.c b/arch/arm/mach-exynos/naples-power.c
new file mode 100644
index 0000000..caed0c4
--- /dev/null
+++ b/arch/arm/mach-exynos/naples-power.c
@@ -0,0 +1,1118 @@
+/*
+ * naples-power.c - Power Management of MIDAS Project
+ *
+ *  Copyright (C) 2012 Samsung Electrnoics
+ *  Chiwoong Byun <woong.byun@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/i2c.h>
+#include <linux/regulator/machine.h>
+#include <plat/gpio-cfg.h>
+#include <mach/gpio-naples.h>
+#include <mach/irqs.h>
+
+#include <linux/mfd/max8997.h>
+#include <linux/mfd/max77686.h>
+#include <linux/mfd/max77693.h>
+
+#if defined(CONFIG_REGULATOR_S5M8767)
+#include <linux/mfd/s5m87xx/s5m-pmic.h>
+#include <linux/mfd/s5m87xx/s5m-core.h>
+#endif
+
+#ifdef CONFIG_REGULATOR_MAX8997
+/* MOTOR */
+#ifdef CONFIG_VIBETONZ
+static void max8997_motor_init(void)
+{
+	gpio_request(GPIO_VIBTONE_EN, "VIBTONE_EN");
+	s3c_gpio_cfgpin(GPIO_VIBTONE_EN, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_VIBTONE_EN, S3C_GPIO_PULL_NONE);
+}
+
+static void max8997_motor_en(bool en)
+{
+	gpio_direction_output(GPIO_VIBTONE_EN, en);
+}
+
+static struct max8997_motor_data max8997_motor = {
+	.max_timeout = 10000,
+	.duty = 44000,
+	.period = 44642,
+	.reg2 = MOTOR_LRA | EXT_PWM | DIVIDER_128,
+	.init_hw = max8997_motor_init,
+	.motor_en = max8997_motor_en,
+	.pwm_id = 1,
+};
+#endif
+
+/* max8997 */
+static struct regulator_consumer_supply ldo1_supply[] = {
+	REGULATOR_SUPPLY("vmipi_1.8v", NULL),
+	REGULATOR_SUPPLY("VDD18", "s5p-mipi-dsim"),
+};
+
+#ifdef CONFIG_SND_SOC_WM8994
+static struct regulator_consumer_supply ldo6_supply[] = {
+	REGULATOR_SUPPLY("AVDD2", NULL),
+	REGULATOR_SUPPLY("CPVDD", NULL),
+	REGULATOR_SUPPLY("DBVDD1", NULL),
+	REGULATOR_SUPPLY("DBVDD2", NULL),
+	REGULATOR_SUPPLY("DBVDD3", NULL),
+};
+#endif
+
+static struct regulator_consumer_supply ldo7_supply[] = {
+	REGULATOR_SUPPLY("cam_sensor_core_1.2v", NULL),
+};
+
+static struct regulator_consumer_supply ldo8_supply[] = {
+	REGULATOR_SUPPLY("votg_3.0v", NULL),
+};
+
+static struct regulator_consumer_supply ldo11_supply[] = {
+	REGULATOR_SUPPLY("vmipi_1.0v", NULL),
+	REGULATOR_SUPPLY("VDD10", "s5p-mipi-dsim"),
+};
+
+static struct regulator_consumer_supply ldo13_supply[] = {
+	REGULATOR_SUPPLY("vlcd_3.3v", NULL),
+	REGULATOR_SUPPLY("VCI", "s6e8aa0"),
+};
+
+static struct regulator_consumer_supply ldo14_supply[] = {
+	REGULATOR_SUPPLY("vcc_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo15_supply[] = {
+	REGULATOR_SUPPLY("vlcd_2.2v", NULL),
+	REGULATOR_SUPPLY("VDD3", "s6e8aa0"),
+};
+
+static struct regulator_consumer_supply ldo12_supply[] = {
+	REGULATOR_SUPPLY("vt_cam_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo16_supply[] = {
+	REGULATOR_SUPPLY("cam_isp_sensor_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo17_supply[] = {
+	REGULATOR_SUPPLY("cam_af_2.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo18_supply[] = {
+	REGULATOR_SUPPLY("touch", NULL),
+};
+
+static struct regulator_consumer_supply max8997_buck1 =
+	REGULATOR_SUPPLY("vdd_arm", NULL);
+
+static struct regulator_consumer_supply max8997_buck2[] = {
+	REGULATOR_SUPPLY("vdd_int", NULL),
+	REGULATOR_SUPPLY("vdd_int", "exynos4412-busfreq"),
+};
+
+static struct regulator_consumer_supply max8997_buck3 =
+	REGULATOR_SUPPLY("vdd_g3d", NULL);
+
+static struct regulator_consumer_supply max8997_buck4 =
+	REGULATOR_SUPPLY("cam_isp_core_1.2v", NULL);
+
+#define REGULATOR_INIT(_ldo, _name, _min_uV, _max_uV, _always_on, _ops_mask, \
+		       _disabled)					\
+	static struct regulator_init_data _ldo##_init_data = {		\
+		.constraints = {					\
+			.name	= _name,				\
+			.min_uV = _min_uV,				\
+			.max_uV = _max_uV,				\
+			.always_on	= _always_on,			\
+			.boot_on	= _always_on,			\
+			.apply_uV	= 1,				\
+			.valid_ops_mask = _ops_mask,			\
+			.state_mem = {					\
+				.disabled	= _disabled,		\
+				.enabled	= !(_disabled),		\
+			}						\
+		},							\
+		.num_consumer_supplies = ARRAY_SIZE(_ldo##_supply),	\
+		.consumer_supplies = &_ldo##_supply[0],			\
+	};
+
+REGULATOR_INIT(ldo1, "VMIPI_1.8V", 1800000, 1800000, 1,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo6, "VCC_1.8V_AP", 1800000, 1800000, 1, 0, 0);
+REGULATOR_INIT(ldo7, "CAM_SENSOR_CORE_1.2V", 1200000, 1200000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo8, "VUOTG_3.0V", 3000000, 3000000, 1,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo11, "VMIPI_1.0V", 1000000, 1000000, 1,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo12, "VT_CAM_1.8V", 1800000, 1800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo13, "VCC_3.3V_LCD", 3300000, 3300000, 1,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo14, "VCC_1.8V_IO", 1800000, 1800000, 1,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo15, "VDD_2.2V_LCD", 2200000, 2200000, 1,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo16, "CAM_ISP_SENSOR_1.8V", 1800000, 1800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo17, "CAM_AF_2.8V", 2800000, 2800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo18, "TSP_AVDD_3.3V", 3300000, 3300000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+
+static struct regulator_init_data max8997_buck1_data = {
+	.constraints	= {
+		.name	= "vdd_arm range",
+		.min_uV	= 950000,
+		.max_uV	= 1100000,
+		.always_on = 1,
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+		.state_mem = {
+			.disabled = 1,
+		},
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &max8997_buck1,
+};
+
+static struct regulator_init_data max8997_buck2_data = {
+	.constraints	= {
+		.name	= "vdd_int range",
+		.min_uV	= 900000,
+		.max_uV	= 1100000,
+		.always_on = 1,
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+		.state_mem = {
+			.disabled = 1,
+		},
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max8997_buck2),
+	.consumer_supplies = max8997_buck2,
+};
+
+static struct regulator_init_data max8997_buck3_data = {
+	.constraints	= {
+		.name	= "vdd_g3d range",
+		.min_uV	= 950000,
+		.max_uV	= 1150000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+		REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.disabled = 1,
+		},
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &max8997_buck3,
+};
+
+static struct regulator_init_data max8997_buck4_data = {
+	.constraints	= {
+		.name	= "CAM_ISP_CORE_1.2V",
+		.min_uV	= 1200000,
+		.max_uV	= 1200000,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.disabled = 1,
+		},
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &max8997_buck4,
+};
+
+static struct max8997_regulator_data max8997_regulators[] = {
+	{ MAX8997_BUCK1, &max8997_buck1_data, },
+	{ MAX8997_BUCK2, &max8997_buck2_data, },
+	{ MAX8997_BUCK3, &max8997_buck3_data, },
+	{ MAX8997_BUCK4, &max8997_buck4_data, },
+	{ MAX8997_LDO1, &ldo1_init_data, },
+	{ MAX8997_LDO6, &ldo6_init_data, },
+	{ MAX8997_LDO7, &ldo7_init_data, },
+	{ MAX8997_LDO8, &ldo8_init_data, },
+	{ MAX8997_LDO11, &ldo11_init_data, },
+	{ MAX8997_LDO12, &ldo12_init_data, },
+	{ MAX8997_LDO13, &ldo13_init_data, },
+	{ MAX8997_LDO14, &ldo14_init_data, },
+	{ MAX8997_LDO15, &ldo15_init_data, },
+	{ MAX8997_LDO16, &ldo16_init_data, },
+	{ MAX8997_LDO17, &ldo17_init_data, },
+	{ MAX8997_LDO18, &ldo18_init_data, },
+};
+
+struct max8997_platform_data exynos4_max8997_info = {
+	.irq_base = IRQ_BOARD_PMIC_START,
+	.num_regulators = ARRAY_SIZE(max8997_regulators),
+	.regulators = max8997_regulators,
+	.buck1_max_vol = 1100000,
+	.buck2_max_vol = 1100000,
+	.buck5_max_vol = 1100000,
+	.buck_set1 = EXYNOS4212_GPJ1(1),
+	.buck_set2 = EXYNOS4212_GPJ1(2),
+	.buck_set3 = EXYNOS4_GPL0(0),
+#ifdef CONFIG_VIBETONZ
+	.motor = &max8997_motor,
+#endif
+};
+#elif defined(CONFIG_REGULATOR_MAX77686)
+/* max77686 */
+
+#ifdef CONFIG_SND_SOC_WM8994
+static struct regulator_consumer_supply ldo3_supply[] = {
+	REGULATOR_SUPPLY("AVDD2", NULL),
+	REGULATOR_SUPPLY("CPVDD", NULL),
+	REGULATOR_SUPPLY("DBVDD1", NULL),
+	REGULATOR_SUPPLY("DBVDD2", NULL),
+	REGULATOR_SUPPLY("DBVDD3", NULL),
+};
+#else
+static struct regulator_consumer_supply ldo3_supply[] = {};
+#endif
+
+static struct regulator_consumer_supply ldo5_supply[] = {
+	REGULATOR_SUPPLY("vcc_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo8_supply[] = {
+	REGULATOR_SUPPLY("vmipi_1.0v", NULL),
+	REGULATOR_SUPPLY("VDD10", "s5p-mipi-dsim.0"),
+};
+
+static struct regulator_consumer_supply ldo9_supply[] = {
+	REGULATOR_SUPPLY("cam_dvdd_1.5v", NULL),
+};
+
+static struct regulator_consumer_supply ldo10_supply[] = {
+	REGULATOR_SUPPLY("vmipi_1.8v", NULL),
+	REGULATOR_SUPPLY("VDD18", "s5p-mipi-dsim.0"),
+};
+
+static struct regulator_consumer_supply ldo11_supply[] = {
+	REGULATOR_SUPPLY("vabb1_1.9v", NULL),
+};
+
+static struct regulator_consumer_supply ldo12_supply[] = {
+	REGULATOR_SUPPLY("votg_3.0v", NULL),
+};
+
+static struct regulator_consumer_supply ldo14_supply[] = {
+	REGULATOR_SUPPLY("vabb2_1.9v", NULL),
+};
+
+static struct regulator_consumer_supply ldo17_supply[] = {
+	REGULATOR_SUPPLY("cam_sensor_core_1.2v", NULL),
+};
+
+static struct regulator_consumer_supply ldo18_supply[] = {
+	REGULATOR_SUPPLY("cam_sensor_io_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo19_supply[] = {
+	REGULATOR_SUPPLY("vt_cam_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo21_supply[] = {
+	REGULATOR_SUPPLY("vtf_2.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo23_supply[] = {
+	REGULATOR_SUPPLY("touch", NULL),
+};
+
+static struct regulator_consumer_supply ldo24_supply[] = {
+	REGULATOR_SUPPLY("touch_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo25_supply[] = {
+	REGULATOR_SUPPLY("vcc_3.0v_lcd", NULL),
+	REGULATOR_SUPPLY("VCI", "s6e39a0x02"),
+};
+
+static struct regulator_consumer_supply ldo26_supply[] = {
+	REGULATOR_SUPPLY("vmotor", NULL),
+};
+
+static struct regulator_consumer_supply max77686_buck1[] = {
+	REGULATOR_SUPPLY("vdd_mif", NULL),
+	REGULATOR_SUPPLY("vdd_mif", "exynos4412-busfreq"),
+};
+
+static struct regulator_consumer_supply max77686_buck2 =
+	REGULATOR_SUPPLY("vdd_arm", NULL);
+
+static struct regulator_consumer_supply max77686_buck3[] = {
+	REGULATOR_SUPPLY("vdd_int", NULL),
+	REGULATOR_SUPPLY("vdd_int", "exynoss4412-busfreq"),
+};
+
+static struct regulator_consumer_supply max77686_buck4[] = {
+	REGULATOR_SUPPLY("vdd_g3d", NULL),
+	REGULATOR_SUPPLY("vdd_g3d", "mali_dev.0"),
+};
+
+static struct regulator_consumer_supply max77686_buck9 =
+	REGULATOR_SUPPLY("cam_isp_core_1.2v", NULL);
+
+static struct regulator_consumer_supply max77686_enp32khz[] = {
+	REGULATOR_SUPPLY("lpo_in", "bcm47511"),
+	REGULATOR_SUPPLY("lpo", "bcm4334_bluetooth"),
+};
+
+#define REGULATOR_INIT(_ldo, _name, _min_uV, _max_uV, _always_on, _ops_mask, \
+		       _disabled)					\
+	static struct regulator_init_data _ldo##_init_data = {		\
+		.constraints = {					\
+			.name = _name,					\
+			.min_uV = _min_uV,				\
+			.max_uV = _max_uV,				\
+			.always_on	= _always_on,			\
+			.boot_on	= _always_on,			\
+			.apply_uV	= 1,				\
+			.valid_ops_mask = _ops_mask,			\
+			.state_mem = {					\
+				.disabled	= _disabled,		\
+				.enabled	= !(_disabled),		\
+			}						\
+		},							\
+		.num_consumer_supplies = ARRAY_SIZE(_ldo##_supply),	\
+		.consumer_supplies = &_ldo##_supply[0],			\
+	};
+
+REGULATOR_INIT(ldo3, "VCC_1.8V_AP", 1800000, 1800000, 1, 0, 0);
+REGULATOR_INIT(ldo5, "VCC_1.8V_IO", 1800000, 1800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo8, "VMIPI_1.0V", 1000000, 1000000, 1,
+	       REGULATOR_CHANGE_STATUS, 0);
+REGULATOR_INIT(ldo9, "CAM_DVDD_1.5V", 1500000, 1500000, 0,
+			REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo10, "VMIPI_1.8V", 1800000, 1800000, 1,
+	       REGULATOR_CHANGE_STATUS, 0);
+REGULATOR_INIT(ldo11, "VABB1_1.9V", 1900000, 1900000, 1,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo12, "VUOTG_3.0V", 3000000, 3000000, 1,
+	       REGULATOR_CHANGE_STATUS, 0);
+REGULATOR_INIT(ldo14, "VABB2_1.9V", 1900000, 1900000, 1,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo17, "CAM_SENSOR_CORE_1.2V", 1200000, 1200000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo18, "CAM_SENSOR_IO_1.8V", 1800000, 1800000, 0,
+			REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo19, "VT_CAM_1.8V", 1800000, 1800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo21, "VTF_2.8V", 2800000, 2800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo23, "TSP_AVDD_2.8V", 2800000, 2800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo24, "VDD_1.8V_TSP", 1800000, 1800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo25, "VCC_3.3V_LCD", 3300000, 3300000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo26, "VCC_MOTOR_3.0V", 3000000, 3000000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+
+#if defined(CONFIG_MACH_SLP_PQ)
+static struct regulator_init_data ldo24_pq11_init_data = {
+	.constraints = {
+		.name = "VDD_1.8V_TSP",
+		.min_uV = 1800000,
+		.max_uV = 1800000,
+		.always_on = 0,
+		.boot_on = 0,
+		.apply_uV = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.enabled	= 0,
+			.disabled	= 1,
+		}
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = ldo24_supply,
+};
+#endif
+
+static struct regulator_init_data max77686_buck1_data = {
+	.constraints = {
+		.name = "vdd_mif range",
+		.min_uV = 850000,
+		.max_uV = 1100000,
+		.always_on = 1,
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_buck1),
+	.consumer_supplies = max77686_buck1,
+};
+
+static struct regulator_init_data max77686_buck2_data = {
+	.constraints = {
+		.name = "vdd_arm range",
+		.min_uV = 850000,
+		.max_uV = 1500000,
+		.apply_uV = 1,
+		.always_on = 1,
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &max77686_buck2,
+};
+
+static struct regulator_init_data max77686_buck3_data = {
+	.constraints = {
+		.name = "vdd_int range",
+		.min_uV = 850000,
+		.max_uV = 1300000,
+		.always_on = 1,
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_buck3),
+	.consumer_supplies = max77686_buck3,
+};
+
+static struct regulator_init_data max77686_buck4_data = {
+	.constraints = {
+		.name = "vdd_g3d range",
+		.min_uV = 850000,
+		.max_uV = 1150000,
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+		REGULATOR_CHANGE_STATUS,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_buck4),
+	.consumer_supplies = max77686_buck4,
+};
+
+static struct regulator_init_data max77686_buck9_data = {
+	.constraints = {
+		.name = "CAM_ISP_CORE_1.2V",
+		.min_uV = 1000000,
+		.max_uV = 1200000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+		REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.disabled = 1,
+		},
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &max77686_buck9,
+};
+
+static struct regulator_init_data max77686_enp32khz_data = {
+	.constraints = {
+		.name = "32KHZ_PMIC",
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.enabled	= 1,
+			.disabled	= 0,
+		},
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_enp32khz),
+	.consumer_supplies = max77686_enp32khz,
+};
+
+static struct max77686_regulator_data max77686_regulators[] = {
+	{MAX77686_BUCK1, &max77686_buck1_data,},
+	{MAX77686_BUCK2, &max77686_buck2_data,},
+	{MAX77686_BUCK3, &max77686_buck3_data,},
+	{MAX77686_BUCK4, &max77686_buck4_data,},
+	{MAX77686_BUCK9, &max77686_buck9_data,},
+	{MAX77686_LDO3, &ldo3_init_data,},
+	{MAX77686_LDO5, &ldo5_init_data,},
+	{MAX77686_LDO8, &ldo8_init_data,},
+	{MAX77686_LDO9, &ldo9_init_data,},
+	{MAX77686_LDO10, &ldo10_init_data,},
+	{MAX77686_LDO11, &ldo11_init_data,},
+	{MAX77686_LDO12, &ldo12_init_data,},
+	{MAX77686_LDO14, &ldo14_init_data,},
+	{MAX77686_LDO17, &ldo17_init_data,},
+	{MAX77686_LDO18, &ldo18_init_data,},
+	{MAX77686_LDO19, &ldo19_init_data,},
+	{MAX77686_LDO21, &ldo21_init_data,},
+	{MAX77686_LDO23, &ldo23_init_data,},
+	{MAX77686_LDO24, &ldo24_init_data,},
+	{MAX77686_LDO25, &ldo25_init_data,},
+	{MAX77686_LDO26, &ldo26_init_data,},
+	{MAX77686_P32KH, &max77686_enp32khz_data,},
+};
+
+struct max77686_opmode_data max77686_opmode_data[MAX77686_REG_MAX] = {
+	[MAX77686_LDO3] = {MAX77686_LDO3, MAX77686_OPMODE_NORMAL},
+	[MAX77686_LDO12] = {MAX77686_LDO12, MAX77686_OPMODE_STANDBY},
+	[MAX77686_BUCK1] = {MAX77686_BUCK1, MAX77686_OPMODE_STANDBY},
+	[MAX77686_BUCK2] = {MAX77686_BUCK2, MAX77686_OPMODE_STANDBY},
+	[MAX77686_BUCK3] = {MAX77686_BUCK3, MAX77686_OPMODE_STANDBY},
+	[MAX77686_BUCK4] = {MAX77686_BUCK4, MAX77686_OPMODE_STANDBY},
+};
+
+struct max77686_platform_data exynos4_max77686_info = {
+	.num_regulators = ARRAY_SIZE(max77686_regulators),
+	.regulators = max77686_regulators,
+	.irq_gpio	= GPIO_PMIC_IRQ,
+	.irq_base	= IRQ_BOARD_PMIC_START,
+	.wakeup		= 1,
+
+	.opmode_data = max77686_opmode_data,
+	.ramp_rate = MAX77686_RAMP_RATE_27MV,
+
+	.buck234_gpio_dvs = {
+		GPIO_PMIC_DVS1,
+		GPIO_PMIC_DVS2,
+		GPIO_PMIC_DVS3,
+	},
+	.buck234_gpio_selb = {
+		GPIO_BUCK2_SEL,
+		GPIO_BUCK3_SEL,
+		GPIO_BUCK4_SEL,
+	},
+	.buck2_voltage[0] = 1100000,	/* 1.1V */
+	.buck2_voltage[1] = 1100000,	/* 1.1V */
+	.buck2_voltage[2] = 1100000,	/* 1.1V */
+	.buck2_voltage[3] = 1100000,	/* 1.1V */
+	.buck2_voltage[4] = 1100000,	/* 1.1V */
+	.buck2_voltage[5] = 1100000,	/* 1.1V */
+	.buck2_voltage[6] = 1100000,	/* 1.1V */
+	.buck2_voltage[7] = 1100000,	/* 1.1V */
+
+	.buck3_voltage[0] = 1100000,	/* 1.1V */
+	.buck3_voltage[1] = 1100000,	/* 1.1V */
+	.buck3_voltage[2] = 1100000,	/* 1.1V */
+	.buck3_voltage[3] = 1100000,	/* 1.1V */
+	.buck3_voltage[4] = 1100000,	/* 1.1V */
+	.buck3_voltage[5] = 1100000,	/* 1.1V */
+	.buck3_voltage[6] = 1100000,	/* 1.1V */
+	.buck3_voltage[7] = 1100000,	/* 1.1V */
+
+	.buck4_voltage[0] = 1100000,	/* 1.1V */
+	.buck4_voltage[1] = 1100000,	/* 1.1V */
+	.buck4_voltage[2] = 1100000,	/* 1.1V */
+	.buck4_voltage[3] = 1100000,	/* 1.1V */
+	.buck4_voltage[4] = 1100000,	/* 1.1V */
+	.buck4_voltage[5] = 1100000,	/* 1.1V */
+	.buck4_voltage[6] = 1100000,	/* 1.1V */
+	.buck4_voltage[7] = 1100000,	/* 1.1V */
+};
+
+void midas_power_init(void)
+{
+#if defined(CONFIG_MACH_M0)
+	if (system_rev == 0 || system_rev == 3)
+#elif defined(CONFIG_MACH_C1)
+		if (system_rev <= 1 || system_rev == 3)
+#elif defined(CONFIG_MACH_C1VZW)
+			if (system_rev == 0)
+#endif
+				ldo8_init_data.constraints.always_on = 1;
+	ldo10_init_data.constraints.always_on = 1;
+}
+#endif /* CONFIG_REGULATOR_MAX77686 */
+
+void midas_power_set_muic_pdata(void *pdata, int gpio)
+{
+	gpio_request(gpio, "AP_PMIC_IRQ");
+	s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
+	s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+
+#ifdef CONFIG_REGULATOR_MAX8997
+	exynos4_max8997_info.muic = pdata;
+#endif
+}
+
+void midas_power_gpio_init(void)
+{
+#ifdef CONFIG_REGULATOR_MAX8997
+	int gpio;
+
+	gpio = EXYNOS4212_GPJ1(1);
+	gpio_request(gpio, "BUCK_SET1");
+	s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+
+	gpio = EXYNOS4212_GPJ1(2);
+	gpio_request(gpio, "BUCK_SET2");
+	s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+
+	gpio = EXYNOS4_GPL0(0);
+	gpio_request(gpio, "BUCK_SET3");
+	s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+#endif
+}
+
+#ifdef CONFIG_MFD_MAX77693
+static struct regulator_consumer_supply safeout1_supply[] = {
+	REGULATOR_SUPPLY("safeout1", NULL),
+};
+
+static struct regulator_consumer_supply safeout2_supply[] = {
+	REGULATOR_SUPPLY("safeout2", NULL),
+};
+
+static struct regulator_consumer_supply charger_supply[] = {
+	REGULATOR_SUPPLY("vinchg1", "charger-manager.0"),
+};
+
+static struct regulator_init_data safeout1_init_data = {
+	.constraints	= {
+		.name		= "safeout1 range",
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.always_on	= 0,
+		.boot_on	= 1,
+		.state_mem	= {
+			.enabled = 1,
+		},
+	},
+	.num_consumer_supplies	= ARRAY_SIZE(safeout1_supply),
+	.consumer_supplies	= safeout1_supply,
+};
+
+static struct regulator_init_data safeout2_init_data = {
+	.constraints	= {
+		.name		= "safeout2 range",
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.always_on	= 0,
+		.boot_on	= 0,
+		.state_mem	= {
+			.enabled = 1,
+		},
+	},
+	.num_consumer_supplies	= ARRAY_SIZE(safeout2_supply),
+	.consumer_supplies	= safeout2_supply,
+};
+
+static struct regulator_init_data charger_init_data = {
+	.constraints	= {
+		.name		= "CHARGER",
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS |
+		REGULATOR_CHANGE_CURRENT,
+		.boot_on	= 1,
+		.min_uA		= 60000,
+		.max_uA		= 2580000,
+	},
+	.num_consumer_supplies	= ARRAY_SIZE(charger_supply),
+	.consumer_supplies	= charger_supply,
+};
+
+struct max77693_regulator_data max77693_regulators[] = {
+	{MAX77693_ESAFEOUT1, &safeout1_init_data,},
+	{MAX77693_ESAFEOUT2, &safeout2_init_data,},
+	{MAX77693_CHARGER, &charger_init_data,},
+};
+
+#if defined(CONFIG_MACH_SLP_PQ)
+/* this initcall replace ldo24 from VDD 2.2 to VDD 1.8 for evt1.1 board. */
+static int __init regulator_init_with_rev(void)
+{
+	/* SLP PQ Promixa evt1.1 */
+	if (system_rev != 3) {
+		ldo24_supply[0].supply = "touch_1.8v";
+		ldo24_supply[0].dev_name = NULL;
+
+		memcpy(&ldo24_init_data, &ldo24_pq11_init_data,
+		       sizeof(struct regulator_init_data));
+	}
+	return 0;
+}
+
+postcore_initcall(regulator_init_with_rev);
+#endif /* CONFIG_MACH_SLP_PQ */
+#endif /* CONFIG_MFD_MAX77693 */
+
+#if defined(CONFIG_REGULATOR_S5M8767)
+/* S5M8767 Regulator */
+
+static struct regulator_consumer_supply ldo1_supply[] = { };
+
+static struct regulator_consumer_supply ldo2_supply[] = { };
+
+#ifdef CONFIG_SND_SOC_WM8994
+static struct regulator_consumer_supply ldo3_supply[] = {
+	REGULATOR_SUPPLY("AVDD2", NULL),
+	REGULATOR_SUPPLY("CPVDD", NULL),
+	REGULATOR_SUPPLY("DBVDD1", NULL),
+	REGULATOR_SUPPLY("DBVDD2", NULL),
+	REGULATOR_SUPPLY("DBVDD3", NULL),
+};
+#else
+static struct regulator_consumer_supply ldo3_supply[] = {};
+#endif
+
+static struct regulator_consumer_supply ldo5_supply[] = { };
+
+static struct regulator_consumer_supply ldo6_supply[] = { };
+
+static struct regulator_consumer_supply ldo8_supply[] = {
+	REGULATOR_SUPPLY("vmipi_1.0v", NULL),
+	REGULATOR_SUPPLY("VDD10", "s5p-mipi-dsim.0"),
+};
+
+static struct regulator_consumer_supply ldo9_supply[] = {
+	REGULATOR_SUPPLY("cam_isp_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo10_supply[] = {
+	REGULATOR_SUPPLY("cam_dvdd_1.5v", NULL),
+};
+
+static struct regulator_consumer_supply ldo11_supply[] = {
+	REGULATOR_SUPPLY("vabb1_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo12_supply[] = {
+	REGULATOR_SUPPLY("votg_3.0v", NULL),
+};
+
+static struct regulator_consumer_supply ldo13_supply[] = {
+	REGULATOR_SUPPLY("vmipi_1.8v", NULL),
+	REGULATOR_SUPPLY("VDD18", "s5p-mipi-dsim.0"),
+};
+
+static struct regulator_consumer_supply ldo14_supply[] = {
+	REGULATOR_SUPPLY("vabb2_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo15_supply[] = { };
+
+static struct regulator_consumer_supply ldo16_supply[] = { };
+
+static struct regulator_consumer_supply ldo17_supply[] = { };
+
+static struct regulator_consumer_supply ldo19_supply[] = {
+	REGULATOR_SUPPLY("cam_af_2.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo20_supply[] = {
+	REGULATOR_SUPPLY("vcc_3.0v_lcd", NULL),
+	REGULATOR_SUPPLY("VCI", "s6e39a0x"),
+};
+
+static struct regulator_consumer_supply ldo21_supply[] = {
+	REGULATOR_SUPPLY("vmotor", NULL),
+};
+
+static struct regulator_consumer_supply ldo22_supply[] = {
+	REGULATOR_SUPPLY("cam_sensor_a2.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo23_supply[] = {
+	REGULATOR_SUPPLY("vtf_2.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo24_supply[] = {
+	REGULATOR_SUPPLY("touch", NULL),
+};
+
+static struct regulator_consumer_supply ldo25_supply[] = {
+	REGULATOR_SUPPLY("cam_sensor_core_1.2v", NULL),
+};
+
+static struct regulator_consumer_supply ldo26_supply[] = {
+	REGULATOR_SUPPLY("cam_sensor_io_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo27_supply[] = {
+	REGULATOR_SUPPLY("vt_cam_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo28_supply[] = {
+	REGULATOR_SUPPLY("touch_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply s5m8767_buck1[] = {
+	REGULATOR_SUPPLY("vdd_mif", NULL),
+	REGULATOR_SUPPLY("vdd_mif", "exynos4212-busfreq"),
+};
+
+static struct regulator_consumer_supply s5m8767_buck2 =
+	REGULATOR_SUPPLY("vdd_arm", NULL);
+
+static struct regulator_consumer_supply s5m8767_buck3[] = {
+	REGULATOR_SUPPLY("vdd_int", NULL),
+	REGULATOR_SUPPLY("vdd_int", "exynos4212-busfreq"),
+};
+
+static struct regulator_consumer_supply s5m8767_buck4[] = {
+	REGULATOR_SUPPLY("vdd_g3d", NULL),
+	REGULATOR_SUPPLY("vdd_g3d", "mali_dev.0"),
+};
+
+static struct regulator_consumer_supply s5m8767_buck6 =
+	REGULATOR_SUPPLY("cam_isp_core_1.2v", NULL);
+
+static struct regulator_consumer_supply s5m8767_enp32khz[] = {
+	REGULATOR_SUPPLY("lpo_in", "bcm47511"),
+	REGULATOR_SUPPLY("lpo", "bcm4334_bluetooth"),
+};
+
+#define REGULATOR_INIT(_ldo, _name, _min_uV, _max_uV, _always_on, _ops_mask, \
+		       _disabled)					\
+	static struct regulator_init_data _ldo##_init_data = {		\
+		.constraints = {					\
+			.name = _name,					\
+			.min_uV = _min_uV,				\
+			.max_uV = _max_uV,				\
+			.always_on	= _always_on,			\
+			.boot_on	= _always_on,			\
+			.apply_uV	= 1,				\
+			.valid_ops_mask = _ops_mask,			\
+			.state_mem = {					\
+				.disabled	= _disabled,		\
+				.enabled	= !(_disabled),		\
+			}						\
+		},							\
+		.num_consumer_supplies = ARRAY_SIZE(_ldo##_supply),	\
+		.consumer_supplies = &_ldo##_supply[0],			\
+	};
+REGULATOR_INIT(ldo1, "VALIVE_1.0V_AP", 1000000, 1000000, 1, 0, 0);
+REGULATOR_INIT(ldo2, "VM1M2_1.2V_AP", 1200000, 1200000, 1, 0, 0);
+REGULATOR_INIT(ldo3, "VCC_1.8V_AP", 1800000, 1800000, 1, 0, 0);
+REGULATOR_INIT(ldo5, "VDDQ_MMC_2.8V", 2800000, 2800000, 1, 0, 0);
+REGULATOR_INIT(ldo6, "VMPLL_1.0V_AP", 1000000, 1000000, 1, 0, 0);
+REGULATOR_INIT(ldo8, "VMIPI_1.0V", 1000000, 1000000, 0,
+	       REGULATOR_CHANGE_STATUS, 0);
+REGULATOR_INIT(ldo9, "CAM_ISP_1.8V", 1800000, 1800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo10, "VT_CAM_DVDD_1.5V", 1500000, 1500000, 0,
+	       REGULATOR_CHANGE_STATUS, 0);
+REGULATOR_INIT(ldo11, "VABB1_1.8V", 1800000, 1800000, 1,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo12, "VUOTG_3.0V", 3000000, 3000000, 1,
+	       REGULATOR_CHANGE_STATUS, 0);
+REGULATOR_INIT(ldo13, "VMIPI_1.8V", 1800000, 1800000, 0,
+	       REGULATOR_CHANGE_STATUS, 0);
+REGULATOR_INIT(ldo14, "VABB2_1.8V", 1800000, 1800000, 1,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo15, "VHSIC_1.0V_AP", 1000000, 1000000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo16, "VHSIC_1.8V_AP", 1800000, 1800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo17, "VCC_2.8V_AP", 2800000, 2800000, 1, 0, 0);
+REGULATOR_INIT(ldo19, "CAM_AF_2.8V", 2800000, 2800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo20, "VCC_3.0V_LCD", 3300000, 3300000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo21, "VCC_MOTOR_3.0V", 3000000, 3000000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo22, "CAM_SENSOR_A2.8V", 2800000, 2800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo23, "VTF_2.8V", 2800000, 2800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo24, "TSP_AVDD_2.8V", 2800000, 2800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo25, "CAM_SENSOR_CORE_1.2V", 1200000, 1200000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo26, "CAM_ISP_SENSOR_1.8V", 1800000, 1800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo27, "VT_CAM_1.8V", 1800000, 1800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo28, "TSP_VDD_1.8V", 1800000, 1800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+
+static struct regulator_init_data s5m8767_buck1_data = {
+	.constraints = {
+		.name = "vdd_mif range",
+		.min_uV = 850000,
+		.max_uV = 1100000,
+		.always_on = 1,
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(s5m8767_buck1),
+	.consumer_supplies = s5m8767_buck1,
+};
+
+static struct regulator_init_data s5m8767_buck2_data = {
+	.constraints = {
+		.name = "vdd_arm range",
+		.min_uV = 850000,
+		.max_uV = 1500000,
+		.apply_uV = 1,
+		.always_on = 1,
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &s5m8767_buck2,
+};
+
+static struct regulator_init_data s5m8767_buck3_data = {
+	.constraints = {
+		.name = "vdd_int range",
+		.min_uV = 850000,
+		.max_uV = 1300000,
+		.always_on = 1,
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(s5m8767_buck3),
+	.consumer_supplies = s5m8767_buck3,
+};
+
+static struct regulator_init_data s5m8767_buck4_data = {
+	.constraints = {
+		.name = "vdd_g3d range",
+		.min_uV = 850000,
+		.max_uV = 1150000,
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+		REGULATOR_CHANGE_STATUS,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(s5m8767_buck4),
+	.consumer_supplies = s5m8767_buck4,
+};
+
+static struct regulator_init_data s5m8767_buck6_data = {
+	.constraints = {
+		.name = "CAM_ISP_CORE_1.2V",
+		.min_uV = 1000000,
+		.max_uV = 1200000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+		REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.disabled = 1,
+		},
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &s5m8767_buck6,
+};
+
+static struct regulator_init_data s5m8767_enp32khz_data = {
+	.constraints = {
+		.name = "32KHZ_PMIC",
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.enabled	= 1,
+			.disabled	= 0,
+		},
+	},
+	.num_consumer_supplies = ARRAY_SIZE(s5m8767_enp32khz),
+	.consumer_supplies = s5m8767_enp32khz,
+};
+
+static struct s5m_regulator_data s5m8767_regulators[] = {
+	{S5M8767_BUCK1, &s5m8767_buck1_data,},
+	{S5M8767_BUCK2, &s5m8767_buck2_data,},
+	{S5M8767_BUCK3, &s5m8767_buck3_data,},
+	{S5M8767_BUCK4, &s5m8767_buck4_data,},
+	{S5M8767_BUCK6, &s5m8767_buck6_data,},
+	{S5M8767_LDO1, &ldo1_init_data,},
+	{S5M8767_LDO2, &ldo2_init_data,},
+	{S5M8767_LDO3, &ldo3_init_data,},
+	{S5M8767_LDO5, &ldo5_init_data,},
+	{S5M8767_LDO6, &ldo6_init_data,},
+	{S5M8767_LDO8, &ldo8_init_data,},
+	{S5M8767_LDO9, &ldo9_init_data,},
+	{S5M8767_LDO10, &ldo10_init_data,},
+	{S5M8767_LDO11, &ldo11_init_data,},
+	{S5M8767_LDO12, &ldo12_init_data,},
+	{S5M8767_LDO13, &ldo13_init_data,},
+	{S5M8767_LDO14, &ldo14_init_data,},
+	{S5M8767_LDO15, &ldo15_init_data,},
+	{S5M8767_LDO16, &ldo16_init_data,},
+	{S5M8767_LDO17, &ldo17_init_data,},
+	{S5M8767_LDO19, &ldo19_init_data,},
+	{S5M8767_LDO20, &ldo20_init_data,},
+	{S5M8767_LDO21, &ldo21_init_data,},
+	{S5M8767_LDO22, &ldo22_init_data,},
+	{S5M8767_LDO23, &ldo23_init_data,},
+	{S5M8767_LDO24, &ldo24_init_data,},
+	{S5M8767_LDO25, &ldo25_init_data,},
+	{S5M8767_LDO26, &ldo26_init_data,},
+	{S5M8767_LDO27, &ldo27_init_data,},
+	{S5M8767_LDO28, &ldo28_init_data,},
+};
+
+struct s5m_opmode_data s5m8767_opmode_data[S5M8767_REG_MAX] = {
+	[S5M8767_LDO3] = {S5M8767_LDO3, S5M_OPMODE_NORMAL},
+	[S5M8767_LDO12] = {S5M8767_LDO12, S5M_OPMODE_STANDBY},
+	[S5M8767_BUCK1] = {S5M8767_BUCK1, S5M_OPMODE_STANDBY},
+	[S5M8767_BUCK2] = {S5M8767_BUCK2, S5M_OPMODE_STANDBY},
+	[S5M8767_BUCK3] = {S5M8767_BUCK3, S5M_OPMODE_STANDBY},
+	[S5M8767_BUCK4] = {S5M8767_BUCK4, S5M_OPMODE_STANDBY},
+};
+
+struct s5m_platform_data exynos4_s5m8767_info = {
+	.device_type	= S5M8767X,
+	.num_regulators = ARRAY_SIZE(s5m8767_regulators),
+	.regulators = s5m8767_regulators,
+	.irq_gpio	= GPIO_PMIC_IRQ,
+	.irq_base	= IRQ_BOARD_PMIC_START,
+	.wakeup		= 1,
+
+	.opmode_data = s5m8767_opmode_data,
+
+	.buck2_voltage[0] = 1100000,	/* 1.1V */
+	.buck2_voltage[1] = 1100000,	/* 1.1V */
+	.buck2_voltage[2] = 1100000,	/* 1.1V */
+	.buck2_voltage[3] = 1100000,	/* 1.1V */
+	.buck2_voltage[4] = 1100000,	/* 1.1V */
+	.buck2_voltage[5] = 1100000,	/* 1.1V */
+	.buck2_voltage[6] = 1100000,	/* 1.1V */
+	.buck2_voltage[7] = 1100000,	/* 1.1V */
+
+	.buck3_voltage[0] = 1100000,	/* 1.1V */
+	.buck3_voltage[1] = 1100000,	/* 1.1V */
+	.buck3_voltage[2] = 1100000,	/* 1.1V */
+	.buck3_voltage[3] = 1100000,	/* 1.1V */
+	.buck3_voltage[4] = 1100000,	/* 1.1V */
+	.buck3_voltage[5] = 1100000,	/* 1.1V */
+	.buck3_voltage[6] = 1100000,	/* 1.1V */
+	.buck3_voltage[7] = 1100000,	/* 1.1V */
+
+	.buck4_voltage[0] = 1100000,	/* 1.1V */
+	.buck4_voltage[1] = 1100000,	/* 1.1V */
+	.buck4_voltage[2] = 1100000,	/* 1.1V */
+	.buck4_voltage[3] = 1100000,	/* 1.1V */
+	.buck4_voltage[4] = 1100000,	/* 1.1V */
+	.buck4_voltage[5] = 1100000,	/* 1.1V */
+	.buck4_voltage[6] = 1100000,	/* 1.1V */
+	.buck4_voltage[7] = 1100000,	/* 1.1V */
+
+	.buck_ramp_delay = 10,
+	.buck_default_idx	= 3,
+
+	.buck_gpios[0]		= GPIO_BUCK2_SEL,
+	.buck_gpios[1]		= GPIO_BUCK3_SEL,
+	.buck_gpios[2]		= GPIO_BUCK4_SEL,
+/*
+	.buck234_gpio_dvs = {
+		GPIO_PMIC_DVS1,
+		GPIO_PMIC_DVS2,
+		GPIO_PMIC_DVS3,
+	},
+	.buck234_gpio_selb = {
+		GPIO_BUCK2_SEL,
+		GPIO_BUCK3_SEL,
+		GPIO_BUCK4_SEL,
+	},
+*/
+};
+
+void midas_power_init(void)
+{
+	ldo8_init_data.constraints.always_on = 1;
+	ldo10_init_data.constraints.always_on = 1;
+}
+
+/* End of S5M8767 */
+#endif
diff --git a/arch/arm/mach-exynos/naples-tsp.c b/arch/arm/mach-exynos/naples-tsp.c
new file mode 100644
index 0000000..b83de4c
--- /dev/null
+++ b/arch/arm/mach-exynos/naples-tsp.c
@@ -0,0 +1,317 @@
+/*
+ * linux/arch/arm/mach-exynos/naples-tsp.c
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/i2c.h>
+#include <linux/err.h>
+#include <linux/gpio.h>
+#include <linux/regulator/consumer.h>
+#include <plat/gpio-cfg.h>
+#include <linux/delay.h>
+#include <mach/naples-tsp.h>
+#ifdef CONFIG_TOUCHSCREEN_ATMEL_MXT224
+#include <linux/i2c/mxt224.h>
+#define TSP_IRQ_READY_DELAY 45
+/*-------------MXT224  TOUCH DRIVER by Xtopher----------*/
+
+#define MXT224_MAX_MT_FINGERS 10
+/*
+  Configuration for MXT224-E
+*/
+#define MXT224E_THRESHOLD_BATT		50
+#define MXT224E_THRESHOLD_CHRG		40
+#define MXT224E_CALCFG_BATT		0x42
+#define MXT224E_CALCFG_CHRG		0x52
+#define MXT224E_ATCHFRCCALTHR_NORMAL		40
+#define MXT224E_ATCHFRCCALRATIO_NORMAL		55
+#define MXT224E_GHRGTIME_BATT		27
+#define MXT224E_GHRGTIME_CHRG		22
+#define MXT224E_ATCHCALST		4
+#define MXT224E_ATCHCALTHR		35
+#define MXT224E_BLEN_BATT		32
+#define MXT224E_BLEN_CHRG		16
+#define MXT224E_MOVFILTER_BATT		46
+#define MXT224E_MOVFILTER_CHRG		46
+#define MXT224E_ACTVSYNCSPERX_NORMAL		32
+#define MXT224E_NEXTTCHDI_NORMAL		0
+
+static u8 t7_config_e[] = {GEN_POWERCONFIG_T7,
+				48,		/* IDLEACQINT */
+				255,	/* ACTVACQINT */
+				25/* ACTV2IDLETO: 25 * 200ms = 5s */};
+static u8 t8_config_e[] = {GEN_ACQUISITIONCONFIG_T8,
+				27, 0, 5, 1, 0, 0, 5, 35, 40, 55};
+
+/* NEXTTCHDI added */
+static u8 t9_config_e[] = {TOUCH_MULTITOUCHSCREEN_T9,
+				139, 0, 0, 19, 11, 0, 32, 50, 2, 0,
+				10,
+				15,	/* MOVHYSTI */
+				1, 46, MXT224_MAX_MT_FINGERS, 5, 40, 10, 191, 3,
+				27, 2, 10, 10, 10, 10, 143, 40, 143, 80,
+				18, 15, 50, 50, 3};
+
+static u8 t15_config_e[] = {TOUCH_KEYARRAY_T15, 0, 0, 0, 0,
+	0, 0, 0, 0, 0, 0, 0};
+static u8 t18_config_e[] = {SPT_COMCONFIG_T18, 0, 0};
+static u8 t23_config_e[] = {TOUCH_PROXIMITY_T23, 0, 0, 0, 0,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+static u8 t25_config_e[] = {SPT_SELFTEST_T25, 0, 0, 0, 0, 0, 0,
+	0, 0};
+static u8 t40_config_e[] = {PROCI_GRIPSUPPRESSION_T40, 0, 0,
+	0, 0, 0};
+static u8 t42_config_e[] = {PROCI_TOUCHSUPPRESSION_T42, 0,
+	0, 0, 0, 0, 0, 0, 0};
+static u8 t46_config_e[] = {SPT_CTECONFIG_T46, 0, 3, 24, 32, 0,
+	0, 1, 0, 0};
+static u8 t47_config_e[] = {PROCI_STYLUS_T47, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0};
+
+static u8 t38_config_e[] = {SPT_USERDATA_T38, 0, 1, 15, 19, 45, 40, 0, 0};
+
+static u8 t48_config_chrg_e[] = {PROCG_NOISESUPPRESSION_T48,
+	3, 132, 0x52, 0, 0, 0, 0, 0, 10, 15,
+	0, 0, 0, 6, 6, 0, 0, 64, 4, 64,
+	10, 0, 9, 5, 0, 15, 0, 20, 0, 0,
+	0, 0, 0, 0, 0, 40, 2,/*blen=0,threshold=50*/
+	15,/* MOVHYSTI */
+	1, 47,/* MoveFilter 46->47, for chargeing*/
+	10, 5, 40, 240, 245, 10, 10, 148, 50, 143,
+	80, 18, 15, 0};
+
+static u8 t48_config_e[] = {PROCG_NOISESUPPRESSION_T48,
+	3, 132, 0x40, 0, 0, 0, 0, 0, 10, 15,
+	0, 0, 0, 6, 6, 0, 0, 48, 4, 48,
+	10, 0, 10, 5, 0, 20, 0, 5, 0, 0,  /*byte 27 original value 20*/
+	0, 0, 0, 0, 32, 50, 2,
+	15, 1, 46,
+	MXT224_MAX_MT_FINGERS, 5, 40, 10, 10,
+	10, 10, 143, 40, 143,
+	80, 18, 15, 0};
+
+static u8 end_config_e[] = {RESERVED_T255};
+
+static const u8 *mxt224e_config[] = {
+	t7_config_e,
+	t8_config_e,
+	t9_config_e,
+	t15_config_e,
+	t18_config_e,
+	t23_config_e,
+	t25_config_e,
+	t40_config_e,
+	t42_config_e,
+	t46_config_e,
+	t47_config_e,
+	t48_config_e,
+	t38_config_e,
+	end_config_e,
+};
+/*
+  Configuration for MXT224
+*/
+#define MXT224_THRESHOLD_BATT		40
+#define MXT224_THRESHOLD_BATT_INIT		55
+#define MXT224_THRESHOLD_CHRG		70
+#define MXT224_NOISE_THRESHOLD_BATT		30
+#define MXT224_NOISE_THRESHOLD_CHRG		40
+#define MXT224_MOVFILTER_BATT		11
+#define MXT224_MOVFILTER_CHRG		46
+#define MXT224_ATCHCALST		9
+#define MXT224_ATCHCALTHR		30
+
+static u8 t7_config[] = { GEN_POWERCONFIG_T7,
+	48,			/* IDLEACQINT */
+	255,			/* ACTVACQINT */
+	25			/* ACTV2IDLETO: 25 * 200ms = 5s */
+};
+
+static u8 t8_config[] = { GEN_ACQUISITIONCONFIG_T8,
+	10, 0, 5, 1, 0, 0, MXT224_ATCHCALST, MXT224_ATCHCALTHR
+};				/*byte 3: 0 */
+
+static u8 t9_config[] = { TOUCH_MULTITOUCHSCREEN_T9,
+	131, 0, 0, 19, 11, 0, 32, MXT224_THRESHOLD_BATT, 2, 0,
+	0,
+	15,			/* MOVHYSTI */
+	1, MXT224_MOVFILTER_BATT, MXT224_MAX_MT_FINGERS, 5, 40, 10, 191, 3,
+	27, 2, 0, 0, 0, 0, 143, 55, 143, 90, 18
+};
+
+static u8 t18_config[] = { SPT_COMCONFIG_T18,
+	0, 1
+};
+
+static u8 t20_config[] = { PROCI_GRIPFACESUPPRESSION_T20,
+	7, 0, 0, 0, 0, 0, 0, 30, 20, 4, 15, 10
+};
+
+static u8 t22_config[] = { PROCG_NOISESUPPRESSION_T22,
+	143, 0, 0, 0, 0, 0, 0, 3, MXT224_NOISE_THRESHOLD_BATT, 0, 0, 29, 34, 39,
+	49, 58, 3
+};
+
+static u8 t28_config[] = { SPT_CTECONFIG_T28,
+			   0, 0, 3, 16, 19, 60
+};
+static u8 end_config[] = { RESERVED_T255 };
+
+static const u8 *mxt224_config[] = {
+	t7_config,
+	t8_config,
+	t9_config,
+	t18_config,
+	t20_config,
+	t22_config,
+	t28_config,
+	end_config,
+};
+
+struct mxt224_callbacks *charger_callbacks;
+void tsp_charger_infom(bool en)
+{
+	if (charger_callbacks && charger_callbacks->inform_charger)
+		charger_callbacks->inform_charger(charger_callbacks, en);
+	pr_debug("[TSP] %s - %s\n", __func__,
+		en ? "on" : "off");
+}
+
+void tsp_register_callback(struct mxt224_callbacks *cb)
+{
+	charger_callbacks = cb;
+}
+
+void tsp_read_ta_status(void *ta_status)
+{
+	*(bool *)ta_status = is_cable_attached;
+}
+
+static int TSP_VDD_1_8V(int on)
+{
+	struct regulator *regulator;
+
+	regulator = regulator_get(NULL, "touch_1.8v");
+	if (IS_ERR(regulator))
+		return PTR_ERR(regulator);
+
+	if (on) {
+		regulator_enable(regulator);
+		pr_info("[TSP] Atmel power on\n");
+	} else {
+		/*
+		 * TODO: If there is a case the regulator must be disabled
+		 * (e,g firmware update?), consider regulator_force_disable.
+		 */
+		if (regulator_is_enabled(regulator))
+			regulator_disable(regulator);
+	}
+	regulator_put(regulator);
+
+	return 0;
+}
+
+static void mxt224_power_on(void)
+{
+
+	struct regulator *regulator;
+
+	regulator = regulator_get(NULL, "touch");
+	if (IS_ERR(regulator))
+		return ;
+	regulator_enable(regulator);
+	TSP_VDD_1_8V(1);
+	regulator_put(regulator);
+	msleep(TSP_IRQ_READY_DELAY);
+	pr_info("mxt224_power_on is finished\n");
+}
+
+static void mxt224_power_off(void)
+{
+	struct regulator *regulator;
+	regulator = regulator_get(NULL, "touch");
+	if (IS_ERR(regulator))
+		return ;
+
+	regulator_disable(regulator);
+	TSP_VDD_1_8V(0);
+	regulator_put(regulator);
+	msleep(TSP_IRQ_READY_DELAY);
+	pr_info("mxt224_power_off is finished\n");
+}
+
+static struct mxt224_platform_data mxt224_data = {
+	.max_finger_touches = MXT224_MAX_MT_FINGERS,
+	.gpio_read_done = GPIO_TSP_INT,
+	.config = mxt224_config,
+	.config_e = mxt224e_config,
+	.t48_config_batt_e = t48_config_e,
+	.t48_config_chrg_e = t48_config_chrg_e,
+	.min_x = 0,
+	.max_x = 540,
+	.min_y = 0,
+	.max_y = 960,
+	.min_z = 0,
+	.max_z = 255,
+	.min_w = 0,
+	.max_w = 30,
+	.atchcalst = MXT224_ATCHCALST,
+	.atchcalsthr = MXT224_ATCHCALTHR,
+	.tchthr_batt = MXT224_THRESHOLD_BATT,
+	.tchthr_batt_init = MXT224_THRESHOLD_BATT_INIT,
+	.tchthr_charging = MXT224_THRESHOLD_CHRG,
+	.noisethr_batt = MXT224_NOISE_THRESHOLD_BATT,
+	.noisethr_charging = MXT224_NOISE_THRESHOLD_CHRG,
+	.movfilter_batt = MXT224_MOVFILTER_BATT,
+	.movfilter_charging = MXT224_MOVFILTER_CHRG,
+	.atchcalst_e = MXT224E_ATCHCALST,
+	.atchcalsthr_e = MXT224E_ATCHCALTHR,
+	.tchthr_batt_e = MXT224E_THRESHOLD_BATT,
+	.tchthr_charging_e = MXT224E_THRESHOLD_CHRG,
+	.calcfg_batt_e = MXT224E_CALCFG_BATT,
+	.calcfg_charging_e = MXT224E_CALCFG_CHRG,
+	.atchfrccalthr_e = MXT224E_ATCHFRCCALTHR_NORMAL,
+	.atchfrccalratio_e = MXT224E_ATCHFRCCALRATIO_NORMAL,
+	.chrgtime_batt_e = MXT224E_GHRGTIME_BATT,
+	.chrgtime_charging_e = MXT224E_GHRGTIME_CHRG,
+	.blen_batt_e = MXT224E_BLEN_BATT,
+	.blen_charging_e = MXT224E_BLEN_CHRG,
+	.movfilter_batt_e = MXT224E_MOVFILTER_BATT,
+	.movfilter_charging_e = MXT224E_MOVFILTER_CHRG,
+	.actvsyncsperx_e = MXT224E_ACTVSYNCSPERX_NORMAL,
+	.nexttchdi_e = MXT224E_NEXTTCHDI_NORMAL,
+	.power_on = mxt224_power_on,
+	.power_off = mxt224_power_off,
+	.register_cb = tsp_register_callback,
+	.read_ta_status = tsp_read_ta_status,
+};
+
+static struct i2c_board_info i2c_devs3[] __initdata = {
+	{
+		I2C_BOARD_INFO(MXT224_DEV_NAME, 0x4A),
+		.platform_data = &mxt224_data
+	}
+};
+
+void __init naples_tsp_init(void)
+{
+	int gpio;
+	pr_info("[TSP] naples_tsp_init() is called\n");
+
+	/* TSP_INT: XEINT_4 */
+	gpio = GPIO_TSP_INT;
+	s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
+	/* s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); */
+	s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+
+	s5p_register_gpio_interrupt(gpio);
+	i2c_devs3[0].irq = gpio_to_irq(gpio);
+	i2c_register_board_info(3, i2c_devs3,
+		ARRAY_SIZE(i2c_devs3));
+}
+#endif
diff --git a/arch/arm/mach-exynos/p10-battery.c b/arch/arm/mach-exynos/p10-battery.c
new file mode 100644
index 0000000..e578b55
--- /dev/null
+++ b/arch/arm/mach-exynos/p10-battery.c
@@ -0,0 +1,511 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/i2c.h>
+#include <linux/i2c-gpio.h>
+#include <linux/gpio.h>
+
+#include <mach/gpio-p10.h>
+#include <mach/regs-pmu.h>	/* S5P_INFORMX */
+
+#include <plat/gpio-cfg.h>
+
+#ifdef CONFIG_STMPE811_ADC
+#include <linux/stmpe811-adc.h>
+#endif
+
+#if defined(CONFIG_BATTERY_SAMSUNG_P1X)
+#include <linux/battery/sec_battery.h>
+#include <linux/battery/sec_fuelgauge.h>
+#include <linux/battery/sec_charger.h>
+
+#define SEC_BATTERY_PMIC_NAME ""
+#define SEC_FUELGAUGE_I2C_ID 9
+#define SEC_CHARGER_I2C_ID 10
+
+static bool sec_bat_adc_none_init(struct platform_device *pdev) { return true; }
+static bool sec_bat_adc_none_exit(void) { return true; }
+static int sec_bat_adc_none_read(unsigned int channel) { return 0; }
+
+static bool sec_bat_adc_ap_init(struct platform_device *pdev) { return true; }
+static bool sec_bat_adc_ap_exit(void) { return true; }
+static int sec_bat_adc_ap_read(unsigned int channel) { return 0; }
+
+/* CHECK ME */
+#define SMTPE811_CHANNEL_ADC_CHECK_1	6
+#define SMTPE811_CHANNEL_VICHG		4	/* Not supported in P10 */
+
+static bool sec_bat_adc_ic_init(struct platform_device *pdev) { return true; }
+static bool sec_bat_adc_ic_exit(void) { return true; }
+static int sec_bat_adc_ic_read(unsigned int channel)
+{
+	int data = 0;
+	int max_voltage = 3300;
+
+	switch (channel) {
+	case SEC_BAT_ADC_CHANNEL_CABLE_CHECK:
+		data = stmpe811_get_adc_data(SMTPE811_CHANNEL_ADC_CHECK_1);
+		data = data * max_voltage / 4095;	/* 4096 ? */
+		break;
+	}
+
+	return data;
+}
+
+static bool sec_bat_gpio_init(void)
+{
+#if defined(CONFIG_MACH_P10_LTE_00_BD) || defined(CONFIG_MACH_P10_WIFI_00_BD)
+	s3c_gpio_cfgpin(GPIO_TA_nCONNECTED, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_TA_nCONNECTED, S3C_GPIO_PULL_NONE);
+#else
+	/* IRQ to detect cable insertion and removal */
+	s3c_gpio_cfgpin(GPIO_TA_INT, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_TA_INT, S3C_GPIO_PULL_NONE);
+#endif
+
+	return true;
+}
+
+static bool sec_fg_gpio_init(void)
+{
+	/* IRQ to detect low battery from fuel gauge */
+	s3c_gpio_cfgpin(GPIO_FUEL_ALERT, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_FUEL_ALERT, S3C_GPIO_PULL_UP);
+
+	return true;
+}
+
+static bool sec_chg_gpio_init(void)
+{
+	s3c_gpio_cfgpin(GPIO_TA_EN, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TA_EN, S3C_GPIO_PULL_UP);
+/*	gpio_set_value(GPIO_TA_EN, 1); */
+
+	s3c_gpio_cfgpin(GPIO_TA_nCHG, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_TA_nCHG, S3C_GPIO_PULL_UP);
+
+#if defined(CONFIG_MACH_P10_LTE_00_BD) || defined(CONFIG_MACH_P10_WIFI_00_BD)
+	/* GPIO_CHG_INT not supported */
+#else
+	/* IRQ to detect charger status change */
+	s3c_gpio_cfgpin(GPIO_CHG_INT, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_CHG_INT, S3C_GPIO_PULL_UP);
+#endif
+
+	return true;
+}
+
+static bool sec_bat_is_lpm(void)
+{
+	u32 val = __raw_readl(S5P_INFORM2);
+
+	pr_info("%s: LP charging: (INFORM2) 0x%x\n", __func__, val);
+
+	if (val == 0x1)
+		return true;
+
+	return false;
+}
+
+static void sec_bat_initial_check(void)
+{
+	struct power_supply *psy = power_supply_get_by_name("battery");
+	union power_supply_propval value;
+	int ret = 0;
+
+	value.intval = gpio_get_value(GPIO_TA_nCONNECTED);
+	pr_debug("%s: %d\n", __func__, value.intval);
+
+	ret = psy->set_property(psy, POWER_SUPPLY_PROP_ONLINE, &value);
+	if (ret) {
+		pr_err("%s: fail to set power_suppy ONLINE property(%d)\n",
+			__func__, ret);
+	}
+}
+
+static bool sec_bat_check_jig_status(void)
+{
+	/* TODO: */
+	return false;
+}
+
+static void sec_bat_switch_to_check(void)
+{
+	pr_debug("%s\n", __func__);
+
+	s3c_gpio_cfgpin(GPIO_USB_SEL1, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_USB_SEL1, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_USB_SEL1, 0);
+
+	mdelay(300);
+}
+
+static void sec_bat_switch_to_normal(void)
+{
+	pr_debug("%s\n", __func__);
+
+	s3c_gpio_cfgpin(GPIO_USB_SEL1, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_USB_SEL1, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_USB_SEL1, 1);
+}
+
+static int current_cable_type = POWER_SUPPLY_TYPE_BATTERY;
+
+static int sec_bat_check_cable_callback(void)
+{
+	return current_cable_type;
+}
+
+static bool sec_bat_check_cable_result_callback(
+				int cable_type)
+{
+	current_cable_type = cable_type;
+
+	switch (cable_type) {
+	case POWER_SUPPLY_TYPE_USB:
+		pr_info("%s set vbus applied\n",
+			__func__);
+		break;
+	case POWER_SUPPLY_TYPE_BATTERY:
+		pr_info("%s set vbus cut\n",
+			__func__);
+		break;
+	case POWER_SUPPLY_TYPE_MAINS:
+	default:
+		pr_err("%s cable type (%d)\n",
+			__func__, cable_type);
+		return false;
+	}
+
+	return true;
+}
+
+/* callback for battery check
+ * return : bool
+ * true - battery detected, false battery NOT detected
+ */
+static bool sec_bat_check_callback(void) { return true; }
+static bool sec_bat_check_result_callback(void) { return true; }
+
+/* callback for OVP/UVLO check
+ * return : int
+ * battery health
+ */
+static int sec_bat_ovp_uvlo_callback(void)
+{
+	int health;
+	health = POWER_SUPPLY_HEALTH_GOOD;
+
+	return health;
+}
+
+static bool sec_bat_ovp_uvlo_result_callback(int health) { return true; }
+
+/*
+ * val.intval : temperature
+ */
+static bool sec_bat_get_temperature_callback(
+		enum power_supply_property psp,
+		union power_supply_propval *val) { return true; }
+
+static bool sec_fg_fuelalert_process(bool is_fuel_alerted) { return true; }
+
+/* ADC region should be exclusive */
+static sec_bat_adc_region_t cable_adc_value_table[] = {
+	{ 0,	500 },	/* POWER_SUPPLY_TYPE_BATTERY */
+	{ 0,	0 },	/* POWER_SUPPLY_TYPE_UPS */
+	{ 1000,	1500 },	/* POWER_SUPPLY_TYPE_MAINS */
+	{ 0,	0 },	/* POWER_SUPPLY_TYPE_USB */
+	{ 0,	0 },	/* POWER_SUPPLY_TYPE_OTG */
+	{ 0,	0 },	/* POWER_SUPPLY_TYPE_DOCK */
+	{ 0,	0 },	/* POWER_SUPPLY_TYPE_MISC */
+};
+
+/* charging current (mA, 0 - NOT supported) */
+/* matching with power_supply_type in power_supply.h */
+static sec_charging_current_t charging_current_table[] = {
+	{0,	0,	0,	0},	/* POWER_SUPPLY_TYPE_BATTERY */
+	{0,	0,	0,	0},	/* POWER_SUPPLY_TYPE_UPS */
+	{2000,	2000,	256,	0},	/* POWER_SUPPLY_TYPE_MAINS */
+	{500,	500,	256,	0},	/* POWER_SUPPLY_TYPE_USB */
+	{500,	500,	256,	0},	/* POWER_SUPPLY_TYPE_USB_DCP */
+	{500,	500,	256,	0},	/* POWER_SUPPLY_TYPE_USB_CDP */
+	{500,	500,	256,	0},	/* POWER_SUPPLY_TYPE_USB_ACA */
+	{0,	0,	0,	0},	/* POWER_SUPPLY_TYPE_OTG */
+	{0,	0,	0,	0},	/* POWER_SUPPLY_TYPE_DOCK */
+	{500,	500,	256,	0},	/* POWER_SUPPLY_TYPE_MISC */
+	{0,	0,	0,	0},	/* POWER_SUPPLY_TYPE_WIRELESS */
+};
+
+/* unit: seconds */
+static int polling_time_table[] = {
+	10,	/* BASIC */
+	30,	/* CHARGING */
+	30,	/* DISCHARGING */
+	30,	/* NOT_CHARGING */
+	300,	/* SLEEP */
+};
+
+/* for MAX17050, MAX17047 */
+static struct battery_data_t p10_battery_data[] = {
+	/* SDI battery data */
+	{
+		.Capacity = 0x2008,
+		.low_battery_comp_voltage = 3600,
+		.low_battery_table = {
+			/* range, slope, offset */
+			{-5000,	0,	0},	/* dummy for top limit */
+			{-1250, 0,	3320},
+			{-750, 97,	3451},
+			{-100, 96,	3461},
+			{0, 0,	3456},
+		},
+		.temp_adjust_table = {
+			/* range, slope, offset */
+			{47000, 122,	8950},
+			{60000, 200,	51000},
+			{100000, 0,	0},	/* dummy for top limit */
+		},
+		.type_str = "SDI",
+	}
+};
+
+static sec_battery_platform_data_t sec_battery_pdata = {
+	/* NO NEED TO BE CHANGED */
+	.initial_check = sec_bat_initial_check,
+	.bat_gpio_init = sec_bat_gpio_init,
+	.fg_gpio_init = sec_fg_gpio_init,
+	.chg_gpio_init = sec_chg_gpio_init,
+
+	.is_lpm = sec_bat_is_lpm,
+	.check_jig_status = sec_bat_check_jig_status,
+	.check_cable_callback =
+		sec_bat_check_cable_callback,
+	.cable_switch_check = sec_bat_switch_to_check,
+	.cable_switch_normal = sec_bat_switch_to_normal,
+	.check_cable_result_callback =
+		sec_bat_check_cable_result_callback,
+	.check_battery_callback =
+		sec_bat_check_callback,
+	.check_battery_result_callback =
+		sec_bat_check_result_callback,
+	.ovp_uvlo_callback = sec_bat_ovp_uvlo_callback,
+	.ovp_uvlo_result_callback =
+		sec_bat_ovp_uvlo_result_callback,
+	.fuelalert_process = sec_fg_fuelalert_process,
+	.get_temperature_callback =
+		sec_bat_get_temperature_callback,
+
+	.adc_api[SEC_BATTERY_ADC_TYPE_NONE] = {
+		.init = sec_bat_adc_none_init,
+		.exit = sec_bat_adc_none_exit,
+		.read = sec_bat_adc_none_read
+		},
+	.adc_api[SEC_BATTERY_ADC_TYPE_AP] = {
+		.init = sec_bat_adc_ap_init,
+		.exit = sec_bat_adc_ap_exit,
+		.read = sec_bat_adc_ap_read
+		},
+	.adc_api[SEC_BATTERY_ADC_TYPE_IC] = {
+		.init = sec_bat_adc_ic_init,
+		.exit = sec_bat_adc_ic_exit,
+		.read = sec_bat_adc_ic_read
+		},
+	.cable_adc_value = cable_adc_value_table,
+	.charging_current = charging_current_table,
+	.polling_time = polling_time_table,
+	/* NO NEED TO BE CHANGED */
+
+	.pmic_name = SEC_BATTERY_PMIC_NAME,
+
+	.adc_check_count = 7,
+	.adc_type = {
+		SEC_BATTERY_ADC_TYPE_IC,	/* CABLE_CHECK */
+		SEC_BATTERY_ADC_TYPE_NONE,	/* BAT_CHECK */
+		SEC_BATTERY_ADC_TYPE_NONE,	/* TEMP */
+		SEC_BATTERY_ADC_TYPE_NONE,	/* TEMP_AMB */
+		SEC_BATTERY_ADC_TYPE_NONE,	/* FULL_CHECK */
+	},
+
+	/* Battery */
+	.vendor = "SDI SDI",
+	.technology = POWER_SUPPLY_TECHNOLOGY_LION,
+	.battery_data = (void *)p10_battery_data,
+	.bat_gpio_ta_nconnected = GPIO_TA_nCONNECTED,
+	.bat_polarity_ta_nconnected = 1,	/* active HIGH */
+	.bat_irq = IRQ_EINT(0),	/* GPIO_TA_INT */
+	.bat_irq_attr =
+		IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
+	.cable_check_type =
+		SEC_BATTERY_CABLE_CHECK_NOUSBCHARGE |
+		SEC_BATTERY_CABLE_CHECK_INT,
+	.cable_source_type = SEC_BATTERY_CABLE_SOURCE_ADC,
+
+	.event_check = false,
+	.event_waiting_time = 60,
+
+	/* Monitor setting */
+	.polling_type = SEC_BATTERY_MONITOR_ALARM,
+	.monitor_initial_count = 3,
+
+	/* Battery check */
+	.battery_check_type = SEC_BATTERY_CHECK_NONE,
+	.check_count = 3,
+
+	/* Battery check by ADC */
+	.check_adc_max = 0,
+	.check_adc_min = 0,
+
+	/* OVP/UVLO check */
+	.ovp_uvlo_check_type = SEC_BATTERY_OVP_UVLO_CHGINT,
+
+	/* Temperature check */
+	.thermal_source = SEC_BATTERY_THERMAL_SOURCE_FG,
+
+	.temp_check_type = SEC_BATTERY_TEMP_CHECK_TEMP,
+	.temp_check_count = 3,
+	.temp_high_threshold_event = 650,
+	.temp_high_recovery_event = 450,
+	.temp_low_threshold_event = 0,
+	.temp_low_recovery_event = -50,
+	.temp_high_threshold_normal = 470,
+	.temp_high_recovery_normal = 400,
+	.temp_low_threshold_normal = 0,
+	.temp_low_recovery_normal = -30,
+	.temp_high_threshold_lpm = 600,
+	.temp_high_recovery_lpm = 420,
+	.temp_low_threshold_lpm = 2,
+	.temp_low_recovery_lpm = -30,
+
+	.full_check_type = SEC_BATTERY_FULLCHARGED_CHGGPIO,
+	.full_check_count = 3,
+	.full_check_adc_1st = 26500,	/* CHECK ME */
+	.full_check_adc_2nd = 25800,	/* CHECK ME */
+	.chg_gpio_full_check = GPIO_TA_nCHG,	/* STAT of bq24191 */
+	.chg_polarity_full_check = 1,
+	.full_condition_type =
+		SEC_BATTERY_FULL_CONDITION_SOC |
+		SEC_BATTERY_FULL_CONDITION_OCV,
+	.full_condition_soc = 99,
+	.full_condition_ocv = 4170,
+
+	.recharge_condition_type =
+		SEC_BATTERY_RECHARGE_CONDITION_SOC |
+		SEC_BATTERY_RECHARGE_CONDITION_VCELL,
+	.recharge_condition_soc = 98,
+	.recharge_condition_avgvcell = 4150,
+	.recharge_condition_vcell = 4150,
+
+	.charging_total_time = 6 * 60 * 60,
+	.recharging_total_time = 90 * 60,
+	.charging_reset_time = 10 * 60,
+
+	/* Fuel Gauge */
+	.fg_irq = IRQ_EINT(19),	/* GPIO_FUEL_ALERT */
+	.fg_irq_attr = IRQF_TRIGGER_LOW | IRQF_ONESHOT,
+	.fuel_alert_soc = 1,
+	.repeated_fuelalert = false,
+	.capacity_calculation_type =
+		SEC_FUELGAUGE_CAPACITY_TYPE_RAW,
+		/* SEC_FUELGAUGE_CAPACITY_TYPE_SCALE | */
+		/* SEC_FUELGAUGE_CAPACITY_TYPE_ATOMIC, */
+	.capacity_max = 1000,
+	.capacity_min = 0,
+
+	/* Charger */
+	.chg_gpio_en = GPIO_TA_EN,
+	.chg_polarity_en = 0,	/* active LOW charge enable */
+	.chg_gpio_status = GPIO_TA_nCHG,
+	.chg_polarity_status = 0,
+#if defined(CONFIG_MACH_P10_LTE_00_BD) || defined(CONFIG_MACH_P10_WIFI_00_BD)
+	.chg_irq = 0,
+	.chg_irq_attr = 0,
+#else
+	.chg_irq = IRQ_EINT(4),	/* GPIO_CHG_INT */
+	.chg_irq_attr = IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
+#endif
+	.chg_float_voltage = 4200,
+};
+
+static struct platform_device sec_device_battery = {
+	.name = "sec-battery",
+	.id = -1,
+	.dev.platform_data = &sec_battery_pdata,
+};
+
+static struct i2c_gpio_platform_data gpio_i2c_data_fuelgauge = {
+	.sda_pin = GPIO_FUEL_SDA_18V,
+	.scl_pin = GPIO_FUEL_SCL_18V,
+};
+
+struct platform_device sec_device_fuelgauge = {
+	.name = "i2c-gpio",
+	.id = SEC_FUELGAUGE_I2C_ID,
+	.dev.platform_data = &gpio_i2c_data_fuelgauge,
+};
+
+static struct i2c_board_info sec_brdinfo_fuelgauge[] __initdata = {
+	{
+		I2C_BOARD_INFO("sec-fuelgauge",
+			SEC_FUELGAUGE_I2C_SLAVEADDR),
+		.platform_data	= &sec_battery_pdata,
+	},
+};
+
+static struct i2c_gpio_platform_data gpio_i2c_data_charger = {
+	.sda_pin = GPIO_CHG_SDA_18V,
+	.scl_pin = GPIO_CHG_SCL_18V,
+};
+
+struct platform_device sec_device_charger = {
+	.name = "i2c-gpio",
+	.id = SEC_CHARGER_I2C_ID,
+	.dev.platform_data = &gpio_i2c_data_charger,
+};
+
+static struct i2c_board_info sec_brdinfo_charger[] __initdata = {
+	{
+		I2C_BOARD_INFO("sec-charger",
+			SEC_CHARGER_I2C_SLAVEADDR),
+		.platform_data	= &sec_battery_pdata,
+	},
+};
+
+static struct platform_device *sec_battery_devices[] __initdata = {
+	&sec_device_charger,
+	&sec_device_fuelgauge,
+	&sec_device_battery,
+};
+
+void __init p10_battery_init(void)
+{
+	platform_add_devices(
+		sec_battery_devices,
+		ARRAY_SIZE(sec_battery_devices));
+
+	i2c_register_board_info(
+		SEC_CHARGER_I2C_ID,
+		sec_brdinfo_charger,
+		ARRAY_SIZE(sec_brdinfo_charger));
+
+	i2c_register_board_info(
+		SEC_FUELGAUGE_I2C_ID,
+		sec_brdinfo_fuelgauge,
+		ARRAY_SIZE(sec_brdinfo_fuelgauge));
+}
+#endif	/* CONFIG_BATTERY_SAMSUNG_P1X */
diff --git a/arch/arm/mach-exynos/p10-gpio.c b/arch/arm/mach-exynos/p10-gpio.c
new file mode 100644
index 0000000..3e6c9d3
--- /dev/null
+++ b/arch/arm/mach-exynos/p10-gpio.c
@@ -0,0 +1,580 @@
+/*
+ *  linux/arch/arm/mach-exynos/p10-gpio.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * EXYNOS - GPIO setting in set board
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/gpio.h>
+#include <linux/serial_core.h>
+#include <plat/devs.h>
+#include <plat/gpio-cfg.h>
+#include <plat/regs-serial.h>
+#include <mach/gpio-midas.h>
+#include <plat/cpu.h>
+#include <mach/pmu.h>
+
+struct gpio_init_data {
+	uint num;
+	uint cfg;
+	uint val;
+	uint pud;
+	uint drv;
+};
+
+extern int s3c_gpio_slp_cfgpin(unsigned int pin, unsigned int config);
+extern int s3c_gpio_slp_setpull_updown(unsigned int pin, unsigned int config);
+
+/* this is sample code for p10 board */
+static struct gpio_init_data p10_init_gpios[] = {
+
+	/* BT_UART_RXD */
+	{EXYNOS5_GPA0(0), S3C_GPIO_SFN(2), 2, S3C_GPIO_PULL_UP},
+	/* BT_UART_TXD */
+	{EXYNOS5_GPA0(1), S3C_GPIO_SFN(2), 2, S3C_GPIO_PULL_NONE},
+	/* BT_UART_CTS */
+	{EXYNOS5_GPA0(2), S3C_GPIO_SFN(2), 2, S3C_GPIO_PULL_NONE},
+	/* BT_UART_RTS */
+	{EXYNOS5_GPA0(3), S3C_GPIO_SFN(2), 2, S3C_GPIO_PULL_NONE},
+
+	/* UART switch: configure as output */
+	{EXYNOS5_GPE0(5), S3C_GPIO_OUTPUT, 2, S3C_GPIO_PULL_NONE},
+	/* USB switch: configure as output */
+	{EXYNOS5_GPH0(1), S3C_GPIO_OUTPUT, 2, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS5_GPB2(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* CODEC_SDA_1.8V */
+	{EXYNOS5_GPB2(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* CODEC_SCL_1.8V */
+
+	{EXYNOS5_GPX0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* DET_3.5 */
+	{EXYNOS5_GPX0(2), S3C_GPIO_SFN(0xF), S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* AP_PMIC_IRQ */
+
+	{EXYNOS5_GPX2(0), S3C_GPIO_SFN(2), S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* VOL_UP */
+	{EXYNOS5_GPX2(1), S3C_GPIO_SFN(2), S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* VOL_DOWN */
+	{EXYNOS5_GPX2(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* ADC_INT */
+	{EXYNOS5_GPX2(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* BT_HOST_WAKE */
+};
+
+/* Initialize gpio set in p10 board */
+void p10_config_gpio_table(void)
+{
+	u32 i, gpio;
+
+	printk(KERN_DEBUG "%s\n", __func__);
+
+	for (i = 0; i < ARRAY_SIZE(p10_init_gpios); i++) {
+		gpio = p10_init_gpios[i].num;
+		s3c_gpio_cfgpin(gpio, p10_init_gpios[i].cfg);
+		s3c_gpio_setpull(gpio, p10_init_gpios[i].pud);
+
+		if (p10_init_gpios[i].val != S3C_GPIO_SETPIN_NONE)
+			gpio_set_value(gpio, p10_init_gpios[i].val);
+
+		s5p_gpio_set_drvstr(gpio, p10_init_gpios[i].drv);
+	}
+}
+
+/* this table only for p10 board */
+static unsigned int exynos5_sleep_gpio_table[][3] = {
+	{EXYNOS4_GPA0(0),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_UP},	/* BT_UART_RXD */
+	{EXYNOS4_GPA0(1),  S3C_GPIO_SLP_OUT1,
+		S3C_GPIO_PULL_NONE},	/* BT_UART_TXD */
+	{EXYNOS4_GPA0(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* BT_UART_CTS */
+	{EXYNOS4_GPA0(3),  S3C_GPIO_SLP_OUT1,
+		S3C_GPIO_PULL_NONE},	/* BT_UART_RTS */
+	{EXYNOS4_GPA0(4),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* GPS_UART_RXD */
+	{EXYNOS4_GPA0(5),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* GPS_UART_TXD */
+	{EXYNOS4_GPA0(6),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* GPS_UART_CTS */
+	{EXYNOS4_GPA0(7),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* GPS_UART_RTS */
+
+	{EXYNOS4_GPA1(0),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* AP_RXD */
+	{EXYNOS4_GPA1(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* AP_TXD */
+	{EXYNOS4_GPA1(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* TSP_SDA_1.8V */
+	{EXYNOS4_GPA1(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* TSP_SCL_1.8V */
+	{EXYNOS4_GPA1(4),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* AP_FLM_RXD */
+	{EXYNOS4_GPA1(5),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* AP_FLM_TXD */
+
+	{EXYNOS5_GPA2(0),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* CHG_SDA_1.8V */
+	{EXYNOS5_GPA2(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* CHG_SCL_1.8V */
+	{EXYNOS5_GPA2(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* AP_PMIC_SDA */
+	{EXYNOS5_GPA2(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* AP_PMIC_SCL */
+	{EXYNOS5_GPA2(4),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* 5M_SPI_CLK */
+	{EXYNOS5_GPA2(5),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* 5M_SPI_CS */
+	{EXYNOS5_GPA2(6),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* 5M_SPI_DI */
+	{EXYNOS5_GPA2(7),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* 5M_SPI_DO */
+
+	{EXYNOS5_GPB0(0),   S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* AP_CP_INT */
+	{EXYNOS5_GPB0(1),   S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* CMC221_CPU_RST */
+	{EXYNOS5_GPB0(2),   S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* CMC_SPI_CLK_REQ */
+	{EXYNOS5_GPB0(3),   S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPB0(4),   S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+
+	{EXYNOS5_GPB1(0),   S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* BARO_INT */
+	{EXYNOS5_GPB1(1),   S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPB1(2),   S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPB1(3),   S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPB1(4),   S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+
+	{EXYNOS5_GPB2(0),   S3C_GPIO_SLP_OUT0,
+		S3C_GPIO_PULL_NONE},	/* LCD_PWM_IN_1.8V */
+	{EXYNOS5_GPB2(1),   S3C_GPIO_SLP_OUT0,
+		S3C_GPIO_PULL_NONE},	/* MOTOR_PWM */
+	{EXYNOS5_GPB2(2),   S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* CODEC_SDA_1.8V */
+	{EXYNOS5_GPB2(3),   S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* CODEC_SCL_1.8V */
+
+	{EXYNOS5_GPB3(0),   S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* MHL_DSDA_1.8V */
+	{EXYNOS5_GPB3(1),   S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* MHL_DSCL_1.8V */
+	{EXYNOS5_GPB3(2),   S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* GSENSE_SDA_1.8V */
+	{EXYNOS5_GPB3(3),   S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/*  GSENSE_SCL_1.8V */
+
+	{EXYNOS5_GPC0(0),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NAND_CLK */
+	{EXYNOS5_GPC0(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NAND_CMD */
+	{EXYNOS5_GPC0(2),  S3C_GPIO_SLP_OUT0,
+		S3C_GPIO_PULL_NONE},	/* eMMC_EN */
+	{EXYNOS5_GPC0(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NAND_D(0) */
+	{EXYNOS5_GPC0(4),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NAND_D(1) */
+	{EXYNOS5_GPC0(5),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NAND_D(2) */
+	{EXYNOS5_GPC0(6),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NAND_D(3) */
+
+	{EXYNOS5_GPC1(0),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPC1(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPC1(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPC1(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NAND_D(4) */
+	{EXYNOS5_GPC1(4),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NAND_D(5) */
+	{EXYNOS5_GPC1(5),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NAND_D(6) */
+	{EXYNOS5_GPC1(6),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NAND_D(7) */
+
+	{EXYNOS5_GPC2(0),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* T_FLASH_CLK */
+	{EXYNOS5_GPC2(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* T_FLASH_CMD */
+	{EXYNOS5_GPC2(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPC2(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* T_FLASH_D(0) */
+	{EXYNOS5_GPC2(4),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* T_FLASH_D(1) */
+	{EXYNOS5_GPC2(5),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* T_FLASH_D(2) */
+	{EXYNOS5_GPC2(6),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* T_FLASH_D(3) */
+
+	{EXYNOS5_GPC3(0),  S3C_GPIO_SLP_OUT0,
+		S3C_GPIO_PULL_NONE},	/* WLAN_SDIO_CLK */
+	{EXYNOS5_GPC3(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},		/* WLAN_SDIO_CMD */
+	{EXYNOS5_GPC3(2),  S3C_GPIO_SLP_OUT0,
+		S3C_GPIO_PULL_NONE},	/* OTG_EN */
+	{EXYNOS5_GPC3(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* WLAN_SDIO_D(0) */
+	{EXYNOS5_GPC3(4),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* WLAN_SDIO_D(1) */
+	{EXYNOS5_GPC3(5),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* WLAN_SDIO_D(2) */
+	{EXYNOS5_GPC3(6),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* WLAN_SDIO_D(3) */
+
+	{EXYNOS5_GPD0(0),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* FUEL_SDA_1.8V */
+	{EXYNOS5_GPD0(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* FUEL_SCL_1.8V */
+	{EXYNOS5_GPD0(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* BSENSE_SDA_1.8V */
+	{EXYNOS5_GPD0(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* BSENSE_SCL_1.8V */
+	{EXYNOS5_GPD0(4),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* MHL_SDA_1.8V */
+	{EXYNOS5_GPD0(5),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* MHL_SCL_1.8V */
+	{EXYNOS5_GPD0(6),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* LCDP_SCL__1.8V */
+	{EXYNOS5_GPD0(7),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* LCDP_SDA__1.8V */
+
+	{EXYNOS5_GPD1(0),  S3C_GPIO_SLP_OUT0,
+		S3C_GPIO_PULL_NONE},	/* HDMI_EN */
+	{EXYNOS5_GPD1(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPD1(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* MOTOR_SDA_1.8V */
+	{EXYNOS5_GPD1(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* MOTOR_SCL_1.8V */
+	{EXYNOS5_GPD1(4),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* LCD_ID */
+	{EXYNOS5_GPD1(5),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* CMC_PMIC_PWRON */
+	{EXYNOS5_GPD1(6),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NFC_EN, NC */
+	{EXYNOS5_GPD1(7),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NFC_FIRMWARE, NC */
+
+	{EXYNOS5_GPE0(0),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* CIS_nRST */
+	{EXYNOS5_GPE0(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* CHG_SDA_1.8V */
+	{EXYNOS5_GPE0(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* CHG_SCL_1.8V */
+	{EXYNOS5_GPE0(3),  S3C_GPIO_SLP_OUT0,
+		S3C_GPIO_PULL_NONE},	/* PDA_ACTIVE */
+	{EXYNOS5_GPE0(4),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* ACCESSORY_CHECK */
+	{EXYNOS5_GPE0(5),  S3C_GPIO_SLP_PREV,
+		S3C_GPIO_PULL_NONE},	/* UART_SEL */
+	{EXYNOS5_GPE0(6),  S3C_GPIO_SLP_PREV,
+		S3C_GPIO_PULL_NONE},	/* GPS_nRST */
+	{EXYNOS5_GPE0(7),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* ISP_TXD */
+
+	{EXYNOS5_GPE1(0),  S3C_GPIO_SLP_PREV,
+		S3C_GPIO_PULL_NONE},	/* GPS_EN */
+	{EXYNOS5_GPE1(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* ISP_RXD */
+
+	{EXYNOS5_GPF0(0),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* 5M_CAM_SDA_1.8V */
+	{EXYNOS5_GPF0(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* 5M_CAM_SCL_1.8V */
+	{EXYNOS5_GPF0(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* VT_CAM_SDA_1.8V */
+	{EXYNOS5_GPF0(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* VT_CAM_SCL_1.8V */
+
+	{EXYNOS5_GPF1(0),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPF1(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPF1(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPF1(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+
+	{EXYNOS5_GPG0(0),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* ALS_SDA_1.8V */
+	{EXYNOS5_GPG0(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/*ALS_SCL_1.8V */
+	{EXYNOS5_GPG0(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* USB3.0_EN */
+	{EXYNOS5_GPG0(3),  S3C_GPIO_SLP_PREV,
+		S3C_GPIO_PULL_NONE},	/* FM34_PWDN */
+	{EXYNOS5_GPG0(4),  S3C_GPIO_SLP_PREV,
+		S3C_GPIO_PULL_NONE},	/* FM34_RESET */
+	{EXYNOS5_GPG0(6),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* MHL_INT */
+	{EXYNOS5_GPG0(7),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* MHL_RST */
+
+	{EXYNOS5_GPG1(0),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* CAM_FLASH_EN */
+	{EXYNOS5_GPG1(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* CAM_FLASH_SET */
+	{EXYNOS5_GPG1(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* TOUCH_CHG */
+	{EXYNOS5_GPG1(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* TOUCH_RESET */
+	{EXYNOS5_GPG1(4),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* TA_nCHG */
+	{EXYNOS5_GPG1(5),  S3C_GPIO_SLP_PREV,
+		S3C_GPIO_PULL_NONE},	/* TA_EN */
+	{EXYNOS5_GPG1(6),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* CAM_VT_nRST */
+	{EXYNOS5_GPG1(7),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+
+	{EXYNOS5_GPG2(0),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPG2(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* VTCAM_MCLK */
+
+	{EXYNOS5_GPH0(0),  S3C_GPIO_SLP_PREV,
+		S3C_GPIO_PULL_NONE},	/* WLAN_EN */
+	{EXYNOS5_GPH0(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* USB_SEL1 */
+	{EXYNOS5_GPH0(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPH0(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* CAM_MCLK */
+
+	{EXYNOS5_GPH1(0),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPH1(1),  S3C_GPIO_SLP_PREV,
+		S3C_GPIO_PULL_NONE},	/* CODEC_LDO_EN */
+	{EXYNOS5_GPH1(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* LIGHT_nINT */
+	{EXYNOS5_GPH1(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* BT_WAKE */
+	{EXYNOS5_GPH1(4),  S3C_GPIO_SLP_PREV,
+		S3C_GPIO_PULL_NONE},	/* FM34_BYPASS */
+	{EXYNOS5_GPH1(5),  S3C_GPIO_SLP_PREV,
+		S3C_GPIO_PULL_NONE},	/* ACCESSORY_EN */
+	{EXYNOS5_GPH1(6),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPH1(7),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* LCD_EN */
+
+	{EXYNOS5_GPV0(0),  S3C_GPIO_SLP_OUT0,
+		S3C_GPIO_PULL_NONE},	/* BUCK4_SEL */
+	{EXYNOS5_GPV0(1),  S3C_GPIO_SLP_OUT0,
+		S3C_GPIO_PULL_NONE},	/* BUCK3_SEL */
+	{EXYNOS5_GPV0(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* 5M_CORE_EN */
+	{EXYNOS5_GPV0(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* CAM_IO_EN */
+	{EXYNOS5_GPV0(4),  S3C_GPIO_SLP_OUT0,
+		S3C_GPIO_PULL_NONE},	/* BUCK2_SEL */
+	{EXYNOS5_GPV0(5),  S3C_GPIO_SLP_OUT0,
+		S3C_GPIO_PULL_NONE},	/* PMIC_DVS3 */
+	{EXYNOS5_GPV0(6),  S3C_GPIO_SLP_OUT0,
+		S3C_GPIO_PULL_NONE},	/* PMIC_DVS2 */
+	{EXYNOS5_GPV0(7),  S3C_GPIO_SLP_OUT0,
+		S3C_GPIO_PULL_NONE},	/* PMIC_DVS1 */
+
+	{EXYNOS5_GPV1(0),  S3C_GPIO_SLP_PREV,
+		S3C_GPIO_PULL_NONE},	/* WLAN_WAKE */
+	{EXYNOS5_GPV1(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* HW_REV3 */
+	{EXYNOS5_GPV1(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* HW_REV2 */
+	{EXYNOS5_GPV1(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* HW_REV1 */
+	{EXYNOS5_GPV1(4),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* HW_REV0 */
+	{EXYNOS5_GPV1(5),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPV1(6),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPV1(7),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+
+	{EXYNOS5_GPV2(0),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPV2(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPV2(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPV2(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPV2(4),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* HUM_SCL_1.8V */
+	{EXYNOS5_GPV2(5),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* HUM_SDA_1.8V */
+	{EXYNOS5_GPV2(6),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* MSENSE_SCL_1.8V */
+	{EXYNOS5_GPV2(7),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* MSENSE_SDA_1.8V */
+
+	{EXYNOS5_GPV3(0),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* ADC_SCL_1.8V */
+	{EXYNOS5_GPV3(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_NONE},	/* ADC_SDA_1.8V */
+	{EXYNOS5_GPV3(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPV3(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPV3(4),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPV3(5),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPV3(6),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPV3(7),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+
+	{EXYNOS5_GPY0(0),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_CSN */
+	{EXYNOS5_GPY0(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPY0(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPY0(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPY0(4),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_REN */
+	{EXYNOS5_GPY0(5),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_WEN */
+
+	{EXYNOS5_GPY1(0),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPY1(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPY1(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPY1(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+
+	{EXYNOS5_GPY2(0),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* TF_EN */
+	{EXYNOS5_GPY2(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPY2(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPY2(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPY2(4),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPY2(5),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+
+	{EXYNOS5_GPY3(0),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_A(0) */
+	{EXYNOS5_GPY3(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_A(1) */
+	{EXYNOS5_GPY3(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_A(2) */
+	{EXYNOS5_GPY3(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_A(3) */
+	{EXYNOS5_GPY3(4),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_A(4) */
+	{EXYNOS5_GPY3(5),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_A(5) */
+	{EXYNOS5_GPY3(6),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_A(6) */
+	{EXYNOS5_GPY3(7),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_A(7) */
+
+	{EXYNOS5_GPY4(0),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_A(8) */
+	{EXYNOS5_GPY4(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_A(9) */
+	{EXYNOS5_GPY4(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_A(10) */
+	{EXYNOS5_GPY4(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_A(11) */
+	{EXYNOS5_GPY4(4),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_A(12) */
+	{EXYNOS5_GPY4(5),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_A(13) */
+	{EXYNOS5_GPY4(6),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPY4(7),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+
+	{EXYNOS5_GPY5(0),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_D(0) */
+	{EXYNOS5_GPY5(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_D(1) */
+	{EXYNOS5_GPY5(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_D(2) */
+	{EXYNOS5_GPY5(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_D(3) */
+	{EXYNOS5_GPY5(4),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_D(4) */
+	{EXYNOS5_GPY5(5),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_D(5) */
+	{EXYNOS5_GPY5(6),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_D(6) */
+	{EXYNOS5_GPY5(7),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_D(7) */
+
+	{EXYNOS5_GPY6(0),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_D(8) */
+	{EXYNOS5_GPY6(1),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_D(9) */
+	{EXYNOS5_GPY6(2),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_D(10) */
+	{EXYNOS5_GPY6(3),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_D(11) */
+	{EXYNOS5_GPY6(4),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_D(12) */
+	{EXYNOS5_GPY6(5),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_D(13) */
+	{EXYNOS5_GPY6(6),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_D(14) */
+	{EXYNOS5_GPY6(7),  S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* DPRAM_D(15) */
+
+	{EXYNOS5_GPZ(0),   S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* MM_I2S_CLK */
+	{EXYNOS5_GPZ(1),   S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPZ(2),   S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* MM_I2S_SYNC */
+	{EXYNOS5_GPZ(3),   S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* MM_I2S_DI */
+	{EXYNOS5_GPZ(4),   S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* MM_I2S_DO */
+	{EXYNOS5_GPZ(5),   S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS5_GPZ(6),   S3C_GPIO_SLP_INPUT,
+		S3C_GPIO_PULL_DOWN},	/* NC */
+};
+
+static void config_sleep_gpio_table(int array_size,
+				    unsigned int (*gpio_table)[3])
+{
+	u32 i, gpio;
+
+	for (i = 0; i < array_size; i++) {
+		gpio = gpio_table[i][0];
+		s3c_gpio_slp_cfgpin(gpio, gpio_table[i][1]);
+		s3c_gpio_slp_setpull_updown(gpio, gpio_table[i][2]);
+	}
+}
+
+/* To save power consumption, gpio pin set before enterling sleep */
+void p10_config_sleep_gpio_table(void)
+{
+	config_sleep_gpio_table(ARRAY_SIZE(exynos5_sleep_gpio_table),
+			exynos5_sleep_gpio_table);
+}
diff --git a/arch/arm/mach-exynos/p10-input.c b/arch/arm/mach-exynos/p10-input.c
new file mode 100644
index 0000000..0e781a2
--- /dev/null
+++ b/arch/arm/mach-exynos/p10-input.c
@@ -0,0 +1,347 @@
+/*
+ *  arch/arm/mach-exynos/p4-input.c
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/i2c.h>
+#include <linux/err.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <plat/gpio-cfg.h>
+#include <plat/iic.h>
+
+#if defined(CONFIG_TOUCHSCREEN_ATMEL_MXT1664S)
+#include <linux/i2c/mxt1664s.h>
+#endif
+
+#if defined(CONFIG_KEYBOARD_GPIO)
+#include <mach/sec_debug.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#endif
+
+#define GPIO_TOUCH_EN	EXYNOS5_GPD1(1)
+
+#if defined(CONFIG_TOUCHSCREEN_ATMEL_MXT1664S)
+
+static int ts_power_on(void)
+{
+	struct regulator *regulator;
+
+	/* touch reset pin */
+	s3c_gpio_cfgpin(GPIO_TOUCH_RESET, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TOUCH_RESET, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TOUCH_RESET, 0);
+
+	/* touch xvdd en pin */
+	s3c_gpio_cfgpin(GPIO_TOUCH_EN, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TOUCH_EN, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TOUCH_EN, 0);
+
+	regulator = regulator_get(NULL, "touch_vdd_1.8v");
+	if (IS_ERR(regulator)) {
+		printk(KERN_ERR "[TSP]ts_power_on : regulator_get failed\n");
+		return -EIO;
+	}
+
+	regulator_enable(regulator);
+	regulator_put(regulator);
+
+	regulator = regulator_get(NULL, "touch_avdd");
+	if (IS_ERR(regulator)) {
+		printk(KERN_ERR "[TSP]ts_power_on : regulator_get failed\n");
+		return -EIO;
+	}
+	regulator_enable(regulator);
+	regulator_put(regulator);
+
+	/* enable touch xvdd */
+	gpio_set_value(GPIO_TOUCH_EN, 1);
+
+	/* reset ic */
+	mdelay(1);
+	gpio_set_value(GPIO_TOUCH_RESET, 1);
+
+	/* touch interrupt pin */
+	/* s3c_gpio_cfgpin(GPIO_TOUCH_CHG, S3C_GPIO_INPUT); */
+
+	s3c_gpio_cfgpin(GPIO_TOUCH_CHG, S3C_GPIO_SFN(0xf));
+	s3c_gpio_setpull(GPIO_TOUCH_CHG, S3C_GPIO_PULL_NONE);
+
+	msleep(MXT_1664S_HW_RESET_TIME);
+
+	printk(KERN_ERR "mxt_power_on is finished\n");
+
+	return 0;
+}
+
+static int ts_power_off(void)
+{
+	struct regulator *regulator;
+
+	regulator = regulator_get(NULL, "touch_avdd");
+	if (IS_ERR(regulator)) {
+		printk(KERN_ERR "[TSP]ts_power_off : regulator_get failed\n");
+		return -EIO;
+	}
+
+	if (regulator_is_enabled(regulator))
+		regulator_force_disable(regulator);
+
+	regulator_put(regulator);
+
+	/* CAUTION : EVT1 board has CHG_INT problem
+	* so it need a workaround code to ensure charging during sleep mode
+	*/
+	if (system_rev != 2) {
+		regulator = regulator_get(NULL, "touch_vdd_1.8v");
+		if (IS_ERR(regulator)) {
+			printk(KERN_ERR "[TSP]ts_power_on : regulator_get failed\n");
+			return -EIO;
+		}
+
+		if (regulator_is_enabled(regulator))
+			regulator_force_disable(regulator);
+
+		regulator_put(regulator);
+	}
+
+	/* touch interrupt pin */
+	s3c_gpio_cfgpin(GPIO_TOUCH_CHG, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(GPIO_TOUCH_CHG, S3C_GPIO_PULL_NONE);
+
+	/* touch reset pin */
+	s3c_gpio_cfgpin(GPIO_TOUCH_RESET, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TOUCH_RESET, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TOUCH_RESET, 0);
+
+	/* touch xvdd en pin */
+	s3c_gpio_cfgpin(GPIO_TOUCH_EN, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TOUCH_EN, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TOUCH_EN, 0);
+
+	printk(KERN_ERR "mxt_power_off is finished\n");
+
+	return 0;
+}
+
+/*
+	Configuration for MXT1664-S
+*/
+#define MXT1664S_MAX_MT_FINGERS	10
+#define MXT1664S_BLEN_BATT 208
+#define MXT1664S_CHRGTIME_BATT  130
+#define MXT1664S_THRESHOLD_BATT	70
+
+static u8 t7_config_s[] = { GEN_POWERCONFIG_T7,
+	255, 255, 50, 3
+};
+
+static u8 t8_config_s[] = { GEN_ACQUISITIONCONFIG_T8,
+	MXT1664S_CHRGTIME_BATT, 0, 10, 10, 0, 0, 20, 35, 0, 0
+};
+
+static u8 t9_config_s[] = { TOUCH_MULTITOUCHSCREEN_T9,
+	139, 0, 0, 32, 52, 0, MXT1664S_BLEN_BATT, MXT1664S_THRESHOLD_BATT, 2, 1,
+	0, 5, 2, 0, MXT1664S_MAX_MT_FINGERS, 10, 20, 20, 63, 6,
+	255, 9, 0, 0, 0, 0, 0, 0, 0, 0,
+	15, 15, 42, 42, 0, 0
+};
+
+static u8 t15_config_s[] = { TOUCH_KEYARRAY_T15,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	0
+};
+
+static u8 t18_config_s[] = { SPT_COMCONFIG_T18,
+	0, 0
+};
+
+static u8 t24_config_s[] = {
+	PROCI_ONETOUCHGESTUREPROCESSOR_T24,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t25_config_s[] = {
+	SPT_SELFTEST_T25,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 0, 200
+};
+
+static u8 t27_config_s[] = {
+	PROCI_TWOTOUCHGESTUREPROCESSOR_T27,
+	0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 t40_config_s[] = { PROCI_GRIPSUPPRESSION_T40,
+	0, 0, 0, 0, 0
+};
+
+static u8 t42_config_s[] = { PROCI_TOUCHSUPPRESSION_T42,
+	0, 60, 100, 60, 0, 20, 0, 0, 0, 0
+};
+
+static u8 t43_config_s[] = { SPT_DIGITIZER_T43,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	0
+};
+
+static u8 t46_config_s[] = { SPT_CTECONFIG_T46,
+	4, 0, 24, 24, 0, 0, 2, 0, 0, 0,
+	0
+};
+
+static u8 t47_config_s[] = { PROCI_STYLUS_T47,
+	73, 20, 45, 4, 5, 30, 1, 120, 3, 32,
+	0, 0, 15, 0, 32, 230, 0, 0, 0, 0
+};
+
+static u8 t55_config_s[] = {ADAPTIVE_T55,
+	0, 0, 0, 0, 0, 0
+};
+
+static u8 t56_config_s[] = {PROCI_SHIELDLESS_T56,
+	1, 0, 1, 24, 28, 28, 28, 28, 28, 28,
+	28, 28, 28, 28, 28, 28, 28, 28, 28, 28,
+	28, 28, 28, 28, 28, 28, 28, 28, 28, 28,
+	28, 28, 28, 28, 28, 28, 2, 16, 0, 2,
+	0, 5, 0, 0, 0, 0, 0, 0, 0, 0,
+	0
+};
+
+static u8 t57_config_s[] = {PROCI_EXTRATOUCHSCREENDATA_T57,
+	226, 25, 0
+};
+
+static u8 t61_config_s[] = {SPT_TIMER_T61,
+	0, 0, 0, 0, 0
+};
+
+static u8 t62_config_s[] = {PROCG_NOISESUPPRESSION_T62,
+	3, 0, 0, 23, 2, 0, 0, 0, 50, 0,
+	0, 0, 0, 0, 5, 0, 10, 3, 5, 144,
+	50, 20, 48, 20, 100, 16, 16, 4, 255, 0,
+	0, 0, 0, 0, 176, 80, 2, 5, 1, 48,
+	10, 20, 30, 0, 0, 0, 0, 0, 0, 0,
+	0, 16, 10, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 0
+};
+static u8 end_config_s[] = { RESERVED_T255 };
+
+static const u8 *MXT1644S_config[] = {
+	t7_config_s,
+	t8_config_s,
+	t9_config_s,
+	t15_config_s,
+	t18_config_s,
+	t24_config_s,
+	t25_config_s,
+	t27_config_s,
+	t40_config_s,
+	t42_config_s,
+	t43_config_s,
+	t46_config_s,
+	t47_config_s,
+	t55_config_s,
+	t56_config_s,
+	t57_config_s,
+	t61_config_s,
+	t62_config_s,
+	end_config_s,
+};
+
+static struct mxt_platform_data mxt_data = {
+	.max_finger_touches = MXT1664S_MAX_MT_FINGERS,
+	.gpio_read_done = GPIO_TOUCH_CHG,
+	.min_x = 0,
+	.max_x = 2559,
+	.min_y = 0,
+	.max_y = 1599,
+	.min_z = 0,
+	.max_z = 255,
+	.min_w = 0,
+	.max_w = 255,
+	.config = MXT1644S_config,
+	.power_on = ts_power_on,
+	.power_off = ts_power_off,
+	.boot_address = 0x26,
+};
+#endif
+
+static struct i2c_board_info i2c_devs3[] __initdata = {
+	{
+		I2C_BOARD_INFO(MXT_DEV_NAME, 0x4A),
+		.platform_data = &mxt_data,
+	}
+};
+
+void __init p10_tsp_init(void)
+{
+	int gpio;
+
+	gpio = GPIO_TOUCH_CHG;
+	gpio_request(gpio, "TSP_INT");
+	s3c_gpio_cfgpin(gpio, S3C_GPIO_INPUT);
+	s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+	s5p_register_gpio_interrupt(GPIO_TOUCH_CHG);
+	i2c_devs3[0].irq = gpio_to_irq(gpio);
+
+	s3c_i2c3_set_platdata(NULL);
+	i2c_register_board_info(3, i2c_devs3, ARRAY_SIZE(i2c_devs3));
+
+	printk(KERN_ERR "%s touch : %d\n", __func__, i2c_devs3[0].irq);
+}
+
+#if defined(CONFIG_KEYBOARD_GPIO)
+#if defined(CONFIG_SEC_DEBUG)
+#define GPIO_KEYS(_code, _gpio, _active_low, _iswake, _hook)	\
+	{							\
+		.code = _code,					\
+		.gpio = _gpio,					\
+		.active_low = _active_low,			\
+		.type = EV_KEY,					\
+		.wakeup = _iswake,				\
+		.debounce_interval = 10,			\
+		.isr_hook = _hook,				\
+		.value = 1					\
+	}
+
+struct gpio_keys_button p10_buttons[] = {
+	GPIO_KEYS(KEY_VOLUMEUP, GPIO_VOL_UP,
+		  1, 0, sec_debug_check_crash_key),
+	GPIO_KEYS(KEY_VOLUMEDOWN, GPIO_VOL_DOWN,
+		  1, 0, sec_debug_check_crash_key),
+	GPIO_KEYS(KEY_POWER, GPIO_nPOWER,
+		  1, 1, sec_debug_check_crash_key),
+};
+#endif
+
+struct gpio_keys_platform_data p10_gpiokeys_platform_data = {
+	p10_buttons,
+	ARRAY_SIZE(p10_buttons),
+};
+
+static struct platform_device p10_keypad = {
+	.name	= "gpio-keys",
+	.dev	= {
+		.platform_data = &p10_gpiokeys_platform_data,
+	},
+};
+#endif
+
+void __init p10_key_init(void)
+{
+#if defined(CONFIG_KEYBOARD_GPIO)
+	platform_device_register(&p10_keypad);
+#endif
+}
+
diff --git a/arch/arm/mach-exynos/p10-mhl.c b/arch/arm/mach-exynos/p10-mhl.c
new file mode 100644
index 0000000..cb36311
--- /dev/null
+++ b/arch/arm/mach-exynos/p10-mhl.c
@@ -0,0 +1,130 @@
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/i2c-gpio.h>
+#include <linux/irq.h>
+#include <linux/delay.h>
+#include <linux/sii9234.h>
+
+#include <plat/gpio-cfg.h>
+#include <mach/regs-gpio.h>
+#include <mach/gpio.h>
+#include "midas.h"
+
+#ifdef CONFIG_SAMSUNG_MHL
+#define I2C_BUS_ID_MHL	15
+static void sii9234_cfg_gpio(void)
+{
+	printk(KERN_INFO "%s()\n", __func__);
+
+	/* AP_MHL_SDA */
+	s3c_gpio_cfgpin(GPIO_MHL_SDA_18V, S3C_GPIO_SFN(0x0));
+	s3c_gpio_setpull(GPIO_MHL_SDA_18V, S3C_GPIO_PULL_NONE);
+
+	/* AP_MHL_SCL */
+	s3c_gpio_cfgpin(GPIO_MHL_SCL_18V, S3C_GPIO_SFN(0x1));
+	s3c_gpio_setpull(GPIO_MHL_SCL_18V, S3C_GPIO_PULL_NONE);
+
+
+	gpio_request(GPIO_MHL_INT, "MHL_INT");
+	s5p_register_gpio_interrupt(GPIO_MHL_INT);
+	s3c_gpio_setpull(GPIO_MHL_INT, S3C_GPIO_PULL_DOWN);
+	irq_set_irq_type(MHL_INT_IRQ, IRQ_TYPE_EDGE_RISING);
+	s3c_gpio_cfgpin(GPIO_MHL_INT, GPIO_MHL_INT_AF);
+
+	s3c_gpio_cfgpin(GPIO_HDMI_EN, S3C_GPIO_OUTPUT);	/* HDMI_EN */
+	gpio_set_value(GPIO_HDMI_EN, GPIO_LEVEL_LOW);
+	s3c_gpio_setpull(GPIO_HDMI_EN, S3C_GPIO_PULL_NONE);
+
+	s3c_gpio_cfgpin(GPIO_MHL_RST, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_MHL_RST, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_MHL_RST, GPIO_LEVEL_LOW);
+}
+
+static void sii9234_power_onoff(bool on)
+{
+	printk(KERN_INFO "%s(%d)\n", __func__, on);
+
+	if (on) {
+		/* To avoid floating state of the HPD pin *
+		 * in the absence of external pull-up     */
+		s3c_gpio_setpull(GPIO_HDMI_HPD, S3C_GPIO_PULL_NONE);
+		gpio_set_value(GPIO_HDMI_EN, GPIO_LEVEL_HIGH);
+
+		s3c_gpio_setpull(GPIO_MHL_SCL_18V, S3C_GPIO_PULL_DOWN);
+		s3c_gpio_setpull(GPIO_MHL_SCL_18V, S3C_GPIO_PULL_NONE);
+
+		/* sii9234_unmaks_interrupt(); // - need to add */
+		/* VCC_SUB_2.0V is always on */
+	} else {
+		gpio_set_value(GPIO_MHL_RST, GPIO_LEVEL_LOW);
+		usleep_range(10000, 20000);
+		gpio_set_value(GPIO_MHL_RST, GPIO_LEVEL_HIGH);
+
+		/* To avoid floating state of the HPD pin *
+		 * in the absence of external pull-up     */
+		s3c_gpio_setpull(GPIO_HDMI_HPD, S3C_GPIO_PULL_DOWN);
+		gpio_set_value(GPIO_HDMI_EN, GPIO_LEVEL_LOW);
+
+		gpio_set_value(GPIO_MHL_RST, GPIO_LEVEL_LOW);
+	}
+}
+
+static void sii9234_reset(void)
+{
+	printk(KERN_INFO "%s()\n", __func__);
+
+	s3c_gpio_cfgpin(GPIO_MHL_RST, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_MHL_RST, S3C_GPIO_PULL_NONE);
+
+
+	gpio_set_value(GPIO_MHL_RST, GPIO_LEVEL_LOW);
+	usleep_range(10000, 20000);
+	gpio_set_value(GPIO_MHL_RST, GPIO_LEVEL_HIGH);
+}
+
+
+
+static struct sii9234_platform_data sii9234_pdata = {
+	.init = sii9234_cfg_gpio,
+	.mhl_sel = NULL,
+	.hw_onoff = sii9234_power_onoff,
+	.hw_reset = sii9234_reset,
+	.enable_vbus = NULL,
+	.vbus_present = NULL,
+};
+
+static struct i2c_board_info __initdata i2c_devs_sii9234[] = {
+	{
+		I2C_BOARD_INFO("sii9234_mhl_tx", 0x72>>1),
+		.platform_data = &sii9234_pdata,
+	},
+	{
+		I2C_BOARD_INFO("sii9234_tpi", 0x7A>>1),
+		.platform_data = &sii9234_pdata,
+	},
+	{
+		I2C_BOARD_INFO("sii9234_hdmi_rx", 0x92>>1),
+		.platform_data = &sii9234_pdata,
+	},
+	{
+		I2C_BOARD_INFO("sii9234_cbus", 0xC8>>1),
+		.platform_data = &sii9234_pdata,
+	},
+};
+
+static struct i2c_board_info i2c_dev_hdmi_ddc __initdata = {
+	I2C_BOARD_INFO("s5p_ddc", (0x74 >> 1)),
+};
+
+static int __init p10_mhl_init(void)
+{
+	i2c_add_devices(I2C_BUS_ID_MHL, i2c_devs_sii9234,
+			ARRAY_SIZE(i2c_devs_sii9234));
+
+	i2c_add_devices(sii9234_pdata.ddc_i2c_num, &i2c_dev_hdmi_ddc, 1);
+
+	return 0;
+}
+module_init(p10_mhl_init);
+#endif
diff --git a/arch/arm/mach-exynos/p10-switch.c b/arch/arm/mach-exynos/p10-switch.c
new file mode 100644
index 0000000..977b6e5
--- /dev/null
+++ b/arch/arm/mach-exynos/p10-switch.c
@@ -0,0 +1,239 @@
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/semaphore.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+#include <plat/gpio-cfg.h>
+#include <mach/gpio.h>
+#include <mach/usb_switch.h>
+
+struct device *sec_switch_dev;
+
+enum usb_path_t current_path = USB_PATH_NONE;
+
+static struct semaphore usb_switch_sem;
+
+static bool usb_connected;
+
+static ssize_t show_usb_sel(struct device *dev,
+			    struct device_attribute *attr, char *buf)
+{
+	const char *mode;
+
+	if (current_path & USB_PATH_CP) {
+		/* CP */
+		mode = "MODEM";
+	} else {
+		/* AP */
+		mode = "PDA";
+	}
+
+	pr_info("%s: %s\n", __func__, mode);
+
+	return sprintf(buf, "%s\n", mode);
+}
+
+static ssize_t store_usb_sel(struct device *dev,
+			     struct device_attribute *attr,
+			     const char *buf, size_t count)
+{
+	pr_info("%s: %s\n", __func__, buf);
+
+	if (!strncasecmp(buf, "PDA", 3)) {
+		usb_switch_lock();
+		usb_switch_clr_path(USB_PATH_CP);
+		usb_switch_unlock();
+	} else if (!strncasecmp(buf, "MODEM", 5)) {
+		usb_switch_lock();
+		usb_switch_set_path(USB_PATH_CP);
+		usb_switch_unlock();
+	} else {
+		pr_err("%s: wrong usb_sel value(%s)!!\n", __func__, buf);
+		return -EINVAL;
+	}
+
+	return count;
+}
+
+static ssize_t show_uart_sel(struct device *dev,
+			     struct device_attribute *attr, char *buf)
+{
+	int val_sel;
+	const char *mode;
+
+	val_sel = gpio_get_value(GPIO_UART_SEL);
+
+	if (val_sel == 0) {
+		/* CP */
+		mode = "CP";
+	} else {
+		/* AP */
+		mode = "AP";
+	}
+
+	pr_info("%s: %s\n", __func__, mode);
+
+	return sprintf(buf, "%s\n", mode);
+}
+
+static ssize_t store_uart_sel(struct device *dev,
+			      struct device_attribute *attr,
+			      const char *buf, size_t count)
+{
+	int uart_sel = -1;
+
+	pr_info("%s: %s\n", __func__, buf);
+
+	if (!strncasecmp(buf, "AP", 2)) {
+		uart_sel = 1;
+	} else if (!strncasecmp(buf, "CP", 2)) {
+		uart_sel = 0;
+	} else {
+		pr_err("%s: wrong uart_sel value(%s)!!\n", __func__, buf);
+		return -EINVAL;
+	}
+
+	/* 1 for AP, 0 for CP */
+	gpio_set_value(GPIO_UART_SEL, uart_sel);
+
+	return count;
+}
+
+static ssize_t show_usb_state(struct device *dev,
+			     struct device_attribute *attr, char *buf)
+{
+	const char *state;
+
+	if (usb_connected)
+		state = "USB_STATE_CONFIGURED";
+	else
+		state = "USB_STATE_NOTCONFIGURED";
+
+	pr_info("%s: %s\n", __func__, state);
+
+	return sprintf(buf, "%s\n", state);
+}
+
+static DEVICE_ATTR(usb_sel, 0664, show_usb_sel, store_usb_sel);
+static DEVICE_ATTR(uart_sel, 0664, show_uart_sel, store_uart_sel);
+static DEVICE_ATTR(usb_state, S_IRUGO, show_usb_state, NULL);
+
+static struct attribute *px_switch_attributes[] = {
+	&dev_attr_usb_sel.attr,
+	&dev_attr_uart_sel.attr,
+	&dev_attr_usb_state.attr,
+	NULL
+};
+
+static const struct attribute_group px_switch_group = {
+	.attrs = px_switch_attributes,
+};
+
+void set_usb_connection_state(bool connected)
+{
+	pr_info("%s: set %s\n", __func__, (connected ? "True" : "False"));
+
+	if (usb_connected != connected) {
+		usb_connected = connected;
+
+		pr_info("%s: send \"usb_state\" sysfs_notify\n", __func__);
+		sysfs_notify(&sec_switch_dev->kobj, NULL, "usb_state");
+	}
+}
+
+static void usb_apply_path(enum usb_path_t path)
+{
+	pr_info("%s: current gpio before changing : sel1:%d\n",
+	       __func__, gpio_get_value(GPIO_USB_SEL1));
+	pr_info("%s: target path %x\n", __func__, path);
+
+	if (path & USB_PATH_ADCCHECK) {
+		gpio_set_value(GPIO_USB_SEL1, 0);
+		return;
+	}
+
+	/* default : AP */
+	gpio_set_value(GPIO_USB_SEL1, 1);
+	return;
+
+}
+
+/*
+  Typical usage of usb switch:
+
+  usb_switch_lock();  (alternatively from hard/soft irq context)
+  ( or usb_switch_trylock() )
+  ...
+  usb_switch_set_path(USB_PATH_ADCCHECK);
+  ...
+  usb_switch_set_path(USB_PATH_TA);
+  ...
+  usb_switch_unlock(); (this restores previous usb switch settings)
+*/
+void usb_switch_set_path(enum usb_path_t path)
+{
+	pr_info("%s: %x current_path before changing\n",
+		__func__, current_path);
+
+	current_path |= path;
+	usb_apply_path(current_path);
+}
+
+void usb_switch_clr_path(enum usb_path_t path)
+{
+	pr_info("%s: %x current_path before changing\n",
+		__func__, current_path);
+
+	current_path &= ~path;
+	usb_apply_path(current_path);
+}
+
+int usb_switch_lock(void)
+{
+	return down_interruptible(&usb_switch_sem);
+}
+
+int usb_switch_trylock(void)
+{
+	return down_trylock(&usb_switch_sem);
+}
+
+void usb_switch_unlock(void)
+{
+	up(&usb_switch_sem);
+}
+
+static int __init usb_switch_init(void)
+{
+	int ret;
+
+	gpio_request(GPIO_USB_SEL1, "GPIO_USB_SEL1");
+	gpio_request(GPIO_UART_SEL, "GPIO_UART_SEL");
+
+	gpio_export(GPIO_USB_SEL1, 1);
+	gpio_export(GPIO_UART_SEL, 1);
+
+	BUG_ON(!sec_class);
+	sec_switch_dev = device_create(sec_class, NULL, 0, NULL, "switch");
+
+	BUG_ON(!sec_switch_dev);
+	gpio_export_link(sec_switch_dev, "GPIO_USB_SEL1", GPIO_USB_SEL1);
+	gpio_export_link(sec_switch_dev, "GPIO_UART_SEL", GPIO_UART_SEL);
+
+	/*init_MUTEX(&usb_switch_sem);*/
+	sema_init(&usb_switch_sem, 1);
+
+	/* create sysfs group */
+	ret = sysfs_create_group(&sec_switch_dev->kobj, &px_switch_group);
+	if (ret) {
+		pr_err("failed to create px switch attribute group\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+device_initcall(usb_switch_init);
diff --git a/arch/arm/mach-exynos/p10-wlan.h b/arch/arm/mach-exynos/p10-wlan.h
new file mode 100644
index 0000000..4c71e83
--- /dev/null
+++ b/arch/arm/mach-exynos/p10-wlan.h
@@ -0,0 +1,13 @@
+/*
+ * arch/arm/mach-s5pv210/u1.h
+ */
+
+#ifndef __P10_H__
+#define __P10_H__
+
+extern int s3c_gpio_slp_cfgpin(unsigned int pin, unsigned int config);
+extern int s3c_gpio_slp_setpull_updown(unsigned int pin, unsigned int config);
+
+extern int brcm_wlan_init(void);
+
+#endif
diff --git a/arch/arm/mach-exynos/p2-gpio.c b/arch/arm/mach-exynos/p2-gpio.c
new file mode 100644
index 0000000..9a7de23
--- /dev/null
+++ b/arch/arm/mach-exynos/p2-gpio.c
@@ -0,0 +1,574 @@
+#include <linux/gpio.h>
+#include <linux/serial_core.h>
+#include <plat/devs.h>
+#include <plat/gpio-cfg.h>
+#include <plat/regs-serial.h>
+#include <mach/gpio.h>
+#include "px.h"
+
+struct gpio_init_data {
+	uint num;
+	uint cfg;
+	uint val;
+	uint pud;
+	uint drv;
+};
+
+static struct gpio_init_data p2_init_gpios[] = {
+	{
+		.num	= EXYNOS4_GPD0(2),	/* MSENSOR_MHL_SDA_2.8V */
+		.cfg	= S3C_GPIO_INPUT,
+		.val	= S3C_GPIO_SETPIN_NONE,
+		.pud	= S3C_GPIO_PULL_NONE,
+		.drv	= S5P_GPIO_DRVSTR_LV1,
+	}, {
+		.num	= EXYNOS4_GPD0(3),	/* MSENSOR_MHL_SCL_2.8V */
+		.cfg	= S3C_GPIO_INPUT,
+		.val	= S3C_GPIO_SETPIN_NONE,
+		.pud	= S3C_GPIO_PULL_NONE,
+		.drv	= S5P_GPIO_DRVSTR_LV1,
+	},  {
+		.num	= EXYNOS4_GPD1(2),	/* SENSE_SDA_2.8V */
+		.cfg	= S3C_GPIO_INPUT,
+		.val	= S3C_GPIO_SETPIN_NONE,
+		.pud	= S3C_GPIO_PULL_NONE,
+		.drv	= S5P_GPIO_DRVSTR_LV1,
+	}, {
+		.num	= EXYNOS4_GPD1(3),	/* SENSE_SCL_2.8V */
+		.cfg	= S3C_GPIO_INPUT,
+		.val	= S3C_GPIO_SETPIN_NONE,
+		.pud	= S3C_GPIO_PULL_NONE,
+		.drv	= S5P_GPIO_DRVSTR_LV1,
+	}, {
+		.num	= EXYNOS4_GPK2(2),	/* PS_ALS_SDA_2.8V */
+		.cfg	= S3C_GPIO_INPUT,
+		.val	= S3C_GPIO_SETPIN_NONE,
+		.pud	= S3C_GPIO_PULL_NONE,
+		.drv	= S5P_GPIO_DRVSTR_LV1,
+	}, {
+		.num	= EXYNOS4_GPK3(2),	/* PS_ALS_SCL_2.8V */
+		.cfg	= S3C_GPIO_INPUT,
+		.val	= S3C_GPIO_SETPIN_NONE,
+		.pud	= S3C_GPIO_PULL_NONE,
+		.drv	= S5P_GPIO_DRVSTR_LV1,
+	}, {	/* GPY0 */
+		.num	= EXYNOS4_GPY0(0),
+		.cfg	= S3C_GPIO_INPUT,
+		.val	= S3C_GPIO_SETPIN_NONE,
+		.pud	= S3C_GPIO_PULL_DOWN,
+		.drv	= S5P_GPIO_DRVSTR_LV1,
+	}, {
+		.num	= EXYNOS4_GPY0(1),
+		.cfg	= S3C_GPIO_INPUT,
+		.val	= S3C_GPIO_SETPIN_NONE,
+		.pud	= S3C_GPIO_PULL_DOWN,
+		.drv	= S5P_GPIO_DRVSTR_LV1,
+	}, {
+		.num	= EXYNOS4_GPY0(2),
+		.cfg	= S3C_GPIO_INPUT,
+		.val	= S3C_GPIO_SETPIN_NONE,
+		.pud	= S3C_GPIO_PULL_DOWN,
+		.drv	= S5P_GPIO_DRVSTR_LV1,
+	}, {
+		.num	= EXYNOS4_GPY0(3),
+		.cfg	= S3C_GPIO_INPUT,
+		.val	= S3C_GPIO_SETPIN_NONE,
+		.pud	= S3C_GPIO_PULL_DOWN,
+		.drv	= S5P_GPIO_DRVSTR_LV1,
+	}, {
+		.num	= EXYNOS4_GPY0(4),
+		.cfg	= S3C_GPIO_INPUT,
+		.val	= S3C_GPIO_SETPIN_NONE,
+		.pud	= S3C_GPIO_PULL_DOWN,
+		.drv	= S5P_GPIO_DRVSTR_LV1,
+	}, {
+		.num	= EXYNOS4_GPY0(5),
+		.cfg	= S3C_GPIO_INPUT,
+		.val	= S3C_GPIO_SETPIN_NONE,
+		.pud	= S3C_GPIO_PULL_DOWN,
+		.drv	= S5P_GPIO_DRVSTR_LV1,
+	}, {	/* GPY1 */
+		.num	= EXYNOS4_GPY1(0),
+		.cfg	= S3C_GPIO_INPUT,
+		.val	= S3C_GPIO_SETPIN_NONE,
+		.pud	= S3C_GPIO_PULL_DOWN,
+		.drv	= S5P_GPIO_DRVSTR_LV1,
+	}, {
+		.num	= EXYNOS4_GPY1(1),
+		.cfg	= S3C_GPIO_INPUT,
+		.val	= S3C_GPIO_SETPIN_NONE,
+		.pud	= S3C_GPIO_PULL_DOWN,
+		.drv	= S5P_GPIO_DRVSTR_LV1,
+	}, {
+		.num	= EXYNOS4_GPY1(2),
+		.cfg	= S3C_GPIO_INPUT,
+		.val	= S3C_GPIO_SETPIN_NONE,
+		.pud	= S3C_GPIO_PULL_DOWN,
+		.drv	= S5P_GPIO_DRVSTR_LV1,
+	}, {
+		.num	= EXYNOS4_GPY1(3),
+		.cfg	= S3C_GPIO_INPUT,
+		.val	= S3C_GPIO_SETPIN_NONE,
+		.pud	= S3C_GPIO_PULL_DOWN,
+		.drv	= S5P_GPIO_DRVSTR_LV1,
+	}, {	/* GPY2 */
+		.num	= EXYNOS4_GPY2(0),
+		.cfg	= S3C_GPIO_INPUT,
+		.val	= S3C_GPIO_SETPIN_NONE,
+		.pud	= S3C_GPIO_PULL_DOWN,
+		.drv	= S5P_GPIO_DRVSTR_LV1,
+	}, {
+		.num	= EXYNOS4_GPY2(1),
+		.cfg	= S3C_GPIO_INPUT,
+		.val	= S3C_GPIO_SETPIN_NONE,
+		.pud	= S3C_GPIO_PULL_DOWN,
+		.drv	= S5P_GPIO_DRVSTR_LV1,
+	}, {
+		.num	= EXYNOS4_GPY2(2),
+		.cfg	= S3C_GPIO_INPUT,
+		.val	= S3C_GPIO_SETPIN_NONE,
+		.pud	= S3C_GPIO_PULL_DOWN,
+		.drv	= S5P_GPIO_DRVSTR_LV1,
+	}, {
+		.num	= EXYNOS4_GPY2(3),
+		.cfg	= S3C_GPIO_INPUT,
+		.val	= S3C_GPIO_SETPIN_NONE,
+		.pud	= S3C_GPIO_PULL_DOWN,
+		.drv	= S5P_GPIO_DRVSTR_LV1,
+	}, {
+		.num	= EXYNOS4_GPY2(4),
+		.cfg	= S3C_GPIO_INPUT,
+		.val	= S3C_GPIO_SETPIN_NONE,
+		.pud	= S3C_GPIO_PULL_DOWN,
+		.drv	= S5P_GPIO_DRVSTR_LV1,
+	}, {
+		.num	= EXYNOS4_GPY2(5),
+		.cfg	= S3C_GPIO_INPUT,
+		.val	= S3C_GPIO_SETPIN_NONE,
+		.pud	= S3C_GPIO_PULL_DOWN,
+		.drv	= S5P_GPIO_DRVSTR_LV1,
+	}, {	/* GPY3 */
+		.num	= EXYNOS4_GPY3(1),
+		.cfg	= S3C_GPIO_INPUT,
+		.val	= S3C_GPIO_SETPIN_NONE,
+		.pud	= S3C_GPIO_PULL_DOWN,
+		.drv	= S5P_GPIO_DRVSTR_LV1,
+	}, {
+		.num	= EXYNOS4_GPY3(3),
+		.cfg	= S3C_GPIO_INPUT,
+		.val	= S3C_GPIO_SETPIN_NONE,
+		.pud	= S3C_GPIO_PULL_DOWN,
+		.drv	= S5P_GPIO_DRVSTR_LV1,
+	}, {	/* GPY4 */
+		.num	= EXYNOS4_GPY4(4),
+		.cfg	= S3C_GPIO_INPUT,
+		.val	= S3C_GPIO_SETPIN_NONE,
+		.pud	= S3C_GPIO_PULL_DOWN,
+		.drv	= S5P_GPIO_DRVSTR_LV1,
+	}, {	/* GPY6 */
+		.num	= EXYNOS4_GPY6(0),
+		.cfg	= S3C_GPIO_INPUT,
+		.val	= S3C_GPIO_SETPIN_NONE,
+		.pud	= S3C_GPIO_PULL_DOWN,
+		.drv	= S5P_GPIO_DRVSTR_LV1,
+	}, {
+		.num	= EXYNOS4_GPY6(2),
+		.cfg	= S3C_GPIO_INPUT,
+		.val	= S3C_GPIO_SETPIN_NONE,
+		.pud	= S3C_GPIO_PULL_DOWN,
+		.drv	= S5P_GPIO_DRVSTR_LV1,
+	}, {
+		.num	= EXYNOS4_GPY6(3),
+		.cfg	= S3C_GPIO_INPUT,
+		.val	= S3C_GPIO_SETPIN_NONE,
+		.pud	= S3C_GPIO_PULL_DOWN,
+		.drv	= S5P_GPIO_DRVSTR_LV1,
+	}, {
+		.num	= EXYNOS4_GPY6(4),
+		.cfg	= S3C_GPIO_INPUT,
+		.val	= S3C_GPIO_SETPIN_NONE,
+		.pud	= S3C_GPIO_PULL_DOWN,
+		.drv	= S5P_GPIO_DRVSTR_LV1,
+	}, {
+		.num	= EXYNOS4_GPY6(5),
+		.cfg	= S3C_GPIO_INPUT,
+		.val	= S3C_GPIO_SETPIN_NONE,
+		.pud	= S3C_GPIO_PULL_DOWN,
+		.drv	= S5P_GPIO_DRVSTR_LV1,
+	},
+	/* BT UART */
+	{GPIO_BT_RXD, S3C_GPIO_SFN(2), 2, S3C_GPIO_PULL_UP},
+	{GPIO_BT_TXD, S3C_GPIO_SFN(2), 2, S3C_GPIO_PULL_NONE},
+	{GPIO_BT_CTS, S3C_GPIO_SFN(2), 2, S3C_GPIO_PULL_NONE},
+	{GPIO_BT_RTS, S3C_GPIO_SFN(2), 2, S3C_GPIO_PULL_NONE},
+	/* GPS UART */
+	{GPIO_GPS_RXD, S3C_GPIO_SFN(2), 2, S3C_GPIO_PULL_UP},
+	{GPIO_GPS_TXD, S3C_GPIO_SFN(2), 2, S3C_GPIO_PULL_NONE},
+	{GPIO_GPS_CTS, S3C_GPIO_SFN(2), 2, S3C_GPIO_PULL_NONE},
+	{GPIO_GPS_RTS, S3C_GPIO_SFN(2), 2, S3C_GPIO_PULL_NONE},
+	{GPIO_GPS_PWR_EN, S3C_GPIO_OUTPUT, 0, S3C_GPIO_PULL_NONE},
+
+	/* UART switch: configure as output */
+	{GPIO_UART_SEL, S3C_GPIO_OUTPUT, 2, S3C_GPIO_PULL_NONE},
+
+	/* USB switch: configure as output */
+	{GPIO_USB_SEL1, S3C_GPIO_OUTPUT, 2, S3C_GPIO_PULL_NONE},
+	{GPIO_USB_SEL2, S3C_GPIO_OUTPUT, 2, S3C_GPIO_PULL_NONE},
+	{GPIO_USB_SEL3, S3C_GPIO_OUTPUT, 2, S3C_GPIO_PULL_NONE},
+
+	/* JIG On */
+	{GPIO_IF_CON_SENSE, S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_NONE},
+
+	/* 30PIN CONNECTOR */
+	{GPIO_DOCK_INT, S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_NONE},
+
+	/* MIC */
+	{GPIO_EAR_MIC_BIAS_EN, S3C_GPIO_OUTPUT, 0, S3C_GPIO_PULL_NONE},
+
+	/*** GPX ***/
+	{GPIO_GYRO_INT,		S3C_GPIO_INPUT,  2, S3C_GPIO_PULL_NONE},
+/* REMOTE_SENSE_IRQ */
+	{EXYNOS4_GPX0(2),	S3C_GPIO_INPUT,  2, S3C_GPIO_PULL_NONE},
+	{GPIO_ACCESSORY_INT,	S3C_GPIO_INPUT,  2, S3C_GPIO_PULL_NONE},
+	{GPIO_MSENSE_INT,	S3C_GPIO_INPUT,  2, S3C_GPIO_PULL_NONE},
+	{GPIO_FUEL_ALERT,	S3C_GPIO_INPUT,  2, S3C_GPIO_PULL_NONE},
+	/* {GPIO_BT_HOST_WAKE, S3C_GPIO_INPUT,  2, S3C_GPIO_PULL_NONE}, */
+	{GPIO_DET_35,		S3C_GPIO_INPUT,  2, S3C_GPIO_PULL_NONE},
+	{GPIO_USB_OTG_EN,	S3C_GPIO_OUTPUT, 0, S3C_GPIO_PULL_NONE},
+	/* T_FLASH_DETECT */
+	{EXYNOS4_GPX3(4),	S3C_GPIO_INPUT,  2, S3C_GPIO_PULL_NONE},
+	/* TA_nCONNECTED */
+	{EXYNOS4_GPX3(5),	S3C_GPIO_INPUT,  2, S3C_GPIO_PULL_NONE},
+	{GPIO_HDMI_HPD,		S3C_GPIO_INPUT,  2, S3C_GPIO_PULL_NONE},
+};
+
+void p2_config_gpio_table(void)
+{
+	u32 i, gpio;
+	u32 gps_gpio1, gps_gpio2;
+
+	printk(KERN_DEBUG "%s\n", __func__);
+
+	for (i = 0; i < ARRAY_SIZE(p2_init_gpios); i++) {
+		gpio = p2_init_gpios[i].num;
+		s3c_gpio_cfgpin(gpio, p2_init_gpios[i].cfg);
+		s3c_gpio_setpull(gpio, p2_init_gpios[i].pud);
+
+		if (p2_init_gpios[i].val != S3C_GPIO_SETPIN_NONE)
+			gpio_set_value(gpio, p2_init_gpios[i].val);
+
+		s5p_gpio_set_drvstr(gpio, p2_init_gpios[i].drv);
+	}
+	/* Set GPIO_GPS_nRST 2.8V Domain for HW rev 05 above
+	 * Set GPIO_GPS_nRST 1.8V Domain for HW rev 04 under
+	 */
+	if (system_rev >= 5) {
+		gps_gpio1 = GPIO_GPS_nRST_28V;
+		gps_gpio2 = GPIO_GPS_nRST; /* NC */
+	} else {
+		gps_gpio1 = GPIO_GPS_nRST;
+		gps_gpio2 = GPIO_GPS_nRST_28V; /* NC */
+	}
+
+	gpio_set_value(gps_gpio1, 1);
+	s3c_gpio_cfgpin(gps_gpio1, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(gps_gpio1, S3C_GPIO_PULL_UP);
+	s5p_gpio_set_drvstr(gps_gpio1, 0);
+
+	gpio_set_value(gps_gpio2, 0);
+	s3c_gpio_cfgpin(gps_gpio2, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(gps_gpio2, S3C_GPIO_PULL_NONE);
+}
+
+/* this table only for p2 board */
+static unsigned int p2_sleep_gpio_table[][3] = {
+	{EXYNOS4_GPA0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+	{EXYNOS4_GPA0(1),  S3C_GPIO_SLP_OUT1,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA0(3),  S3C_GPIO_SLP_OUT1,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPA0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPA1(0),  S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_UP},
+	{EXYNOS4_GPA1(1),  S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_UP},
+	{EXYNOS4_GPA1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA1(5),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPB(0),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPB(1),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPB(2),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(3),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	/* IRDA_nINT */
+	{EXYNOS4_GPB(4),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	/* IRDA_nRST */
+	{EXYNOS4_GPB(5),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPB(6),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(7),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPC0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPC0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPC0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPC0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPC0(4),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPC1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPC1(1),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPC1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPC1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPC1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPD0(0),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPD0(1),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPD0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPD0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPD1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPD1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPD1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPD1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4210_GPE0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4210_GPE1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE1(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE1(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4210_GPE2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4210_GPE3(0),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE3(1),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE3(2),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE3(3),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE3(4),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE3(5),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE3(6),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE3(7),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4210_GPE4(0),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE4(1),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE4(2),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE4(3),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE4(4),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE4(5),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE4(6),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE4(7),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPF0(0),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF0(1),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF0(2),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF0(3),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF0(4),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF0(5),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF0(6),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF0(7),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPF1(0),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF1(1),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF1(2),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF1(3),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF1(4),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF1(5),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF1(6),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF1(7),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPF2(0),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF2(1),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF2(2),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF2(3),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF2(4),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF2(5),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF2(6),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF2(7),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPF3(0),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF3(1),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF3(2),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF3(3),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF3(4),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF3(5),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4210_GPJ0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPJ0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPJ0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPJ0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPJ0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPJ0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPJ0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPJ0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4210_GPJ1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPJ1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPJ1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPJ1(3),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPJ1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPK0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK0(2),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	/* IRDA_SCL_2.8V */
+	{EXYNOS4_GPK1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK1(1),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	/* IRDA_SDA_2.8V */
+	{EXYNOS4_GPK1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK1(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPK2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPK3(0),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+	{EXYNOS4_GPK3(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+	{EXYNOS4_GPK3(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+	{EXYNOS4_GPK3(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+	{EXYNOS4_GPK3(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+
+	{EXYNOS4_GPL0(0),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL0(1),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL0(2),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	/* GPS_nRST 2.8V */
+	{EXYNOS4_GPL0(3),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL0(4),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL0(5),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL0(6),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL0(7),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPL1(0),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL1(1),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL1(2),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPL2(0),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL2(1),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL2(2),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL2(4),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPL2(6),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL2(7),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPY0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPY1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPY2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	/* MHL_SDA_1.8V */
+	{EXYNOS4_GPY3(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	/* MHL_SCL_1.8V */
+	{EXYNOS4_GPY3(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY3(4),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(5),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(6),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	/* USB_SEL2 */
+	{EXYNOS4_GPY3(7),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPY4(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	/* GPIO_PDA_ACTIVE */
+	{EXYNOS4_GPY4(2),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	/* V_ACCESSORY_5V CHECK */
+	{EXYNOS4_GPY4(4),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	/* USB_SEL3 */
+	{EXYNOS4_GPY4(5),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	/* GPIO_CP_REQ_RESET */
+	{EXYNOS4_GPY4(6),  S3C_GPIO_SLP_OUT1,  S3C_GPIO_PULL_NONE},
+	/* GPIO_UART_SEL */
+	{EXYNOS4_GPY4(7),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+
+	/* HW_REV0 */
+	{EXYNOS4_GPY5(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	/* HW_REV1 */
+	{EXYNOS4_GPY5(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	/* HW_REV2 */
+	{EXYNOS4_GPY5(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	/* HW_REV3 */
+	{EXYNOS4_GPY5(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	/* GPS_nRST */
+	{EXYNOS4_GPY5(4),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY5(5),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY5(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY5(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPY6(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	/* ACCESSORY_EN */
+	{EXYNOS4_GPY6(1),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY6(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY6(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY6(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY6(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY6(6),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE}, /* TA_EN */
+	{EXYNOS4_GPY6(7),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPZ(0),   S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPZ(1),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPZ(2),   S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPZ(3),   S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPZ(4),   S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPZ(5),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPZ(6),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+};
+
+static void config_sleep_gpio_table(int array_size,
+				    unsigned int (*gpio_table)[3])
+{
+	u32 i, gpio;
+
+	for (i = 0; i < array_size; i++) {
+		gpio = gpio_table[i][0];
+		s3c_gpio_slp_cfgpin(gpio, gpio_table[i][1]);
+		s3c_gpio_slp_setpull_updown(gpio, gpio_table[i][2]);
+	}
+}
+
+void p2_config_sleep_gpio_table(void)
+{
+	config_sleep_gpio_table(ARRAY_SIZE(p2_sleep_gpio_table),
+			p2_sleep_gpio_table);
+}
diff --git a/arch/arm/mach-exynos/p4-gpio.c b/arch/arm/mach-exynos/p4-gpio.c
new file mode 100644
index 0000000..3b691cb
--- /dev/null
+++ b/arch/arm/mach-exynos/p4-gpio.c
@@ -0,0 +1,488 @@
+#include <linux/gpio.h>
+#include <linux/serial_core.h>
+#include <plat/devs.h>
+#include <plat/gpio-cfg.h>
+#include <plat/regs-serial.h>
+#include <mach/gpio.h>
+#include "px.h"
+
+struct gpio_init_data {
+	uint num;
+	uint cfg;
+	uint val;
+	uint pud;
+	uint drv;
+};
+
+static struct gpio_init_data p4_init_gpios[] = {
+	{
+		.num	= EXYNOS4_GPD0(2),	/* MSENSOR_MHL_SDA_2.8V */
+		.cfg	= S3C_GPIO_INPUT,
+		.val	= S3C_GPIO_SETPIN_NONE,
+		.pud	= S3C_GPIO_PULL_NONE,
+		.drv	= S5P_GPIO_DRVSTR_LV1,
+	}, {
+		.num	= EXYNOS4_GPD0(3),	/* MSENSOR_MHL_SCL_2.8V */
+		.cfg	= S3C_GPIO_INPUT,
+		.val	= S3C_GPIO_SETPIN_NONE,
+		.pud	= S3C_GPIO_PULL_NONE,
+		.drv	= S5P_GPIO_DRVSTR_LV1,
+	},  {
+		.num	= EXYNOS4_GPD1(2),	/* SENSE_SDA_2.8V */
+		.cfg	= S3C_GPIO_INPUT,
+		.val	= S3C_GPIO_SETPIN_NONE,
+		.pud	= S3C_GPIO_PULL_NONE,
+		.drv	= S5P_GPIO_DRVSTR_LV1,
+	}, {
+		.num	= EXYNOS4_GPD1(3),	/* SENSE_SCL_2.8V */
+		.cfg	= S3C_GPIO_INPUT,
+		.val	= S3C_GPIO_SETPIN_NONE,
+		.pud	= S3C_GPIO_PULL_NONE,
+		.drv	= S5P_GPIO_DRVSTR_LV1,
+	}, {
+		.num	= EXYNOS4_GPK2(2),	/* PS_ALS_SDA_2.8V */
+		.cfg	= S3C_GPIO_INPUT,
+		.val	= S3C_GPIO_SETPIN_NONE,
+		.pud	= S3C_GPIO_PULL_NONE,
+		.drv	= S5P_GPIO_DRVSTR_LV1,
+	}, {
+		.num	= EXYNOS4_GPK3(2),	/* PS_ALS_SCL_2.8V */
+		.cfg	= S3C_GPIO_INPUT,
+		.val	= S3C_GPIO_SETPIN_NONE,
+		.pud	= S3C_GPIO_PULL_NONE,
+		.drv	= S5P_GPIO_DRVSTR_LV1,
+	},
+	/* BT UART */
+	{GPIO_BT_RXD, S3C_GPIO_SFN(2), 2, S3C_GPIO_PULL_UP},
+	{GPIO_BT_TXD, S3C_GPIO_SFN(2), 2, S3C_GPIO_PULL_NONE},
+	{GPIO_BT_CTS, S3C_GPIO_SFN(2), 2, S3C_GPIO_PULL_NONE},
+	{GPIO_BT_RTS, S3C_GPIO_SFN(2), 2, S3C_GPIO_PULL_NONE},
+	/* GPS UART */
+	{GPIO_GPS_RXD, S3C_GPIO_SFN(2), 2, S3C_GPIO_PULL_UP},
+	{GPIO_GPS_TXD, S3C_GPIO_SFN(2), 2, S3C_GPIO_PULL_NONE},
+	{GPIO_GPS_CTS, S3C_GPIO_SFN(2), 2, S3C_GPIO_PULL_NONE},
+	{GPIO_GPS_RTS, S3C_GPIO_SFN(2), 2, S3C_GPIO_PULL_NONE},
+	{GPIO_GPS_nRST, S3C_GPIO_OUTPUT, 1, S3C_GPIO_PULL_UP},
+	{GPIO_GPS_PWR_EN, S3C_GPIO_OUTPUT, 0, S3C_GPIO_PULL_NONE},
+
+	/* UART switch: configure as output */
+	{GPIO_UART_SEL, S3C_GPIO_OUTPUT, 2, S3C_GPIO_PULL_NONE},
+
+	/* USB switch: configure as output */
+	{GPIO_USB_SEL1, S3C_GPIO_OUTPUT, 2, S3C_GPIO_PULL_NONE},
+	{GPIO_USB_SEL2, S3C_GPIO_OUTPUT, 2, S3C_GPIO_PULL_NONE},
+	{GPIO_USB_SEL3, S3C_GPIO_OUTPUT, 2, S3C_GPIO_PULL_NONE},
+
+	/* JIG On */
+	{GPIO_IF_CON_SENSE, S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_NONE},
+
+	/* 30PIN CONNECTOR */
+	{GPIO_DOCK_INT, S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_NONE},
+
+	/* MIC */
+	{GPIO_EAR_MIC_BIAS_EN, S3C_GPIO_OUTPUT, 0, S3C_GPIO_PULL_NONE},
+
+	/*** GPX ***/
+	{GPIO_GYRO_INT,		S3C_GPIO_INPUT,  2, S3C_GPIO_PULL_NONE},
+	{GPIO_REMOTE_SENSE_IRQ, S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_NONE},
+#ifdef CONFIG_SEC_MODEM
+	{GPIO_SIM_DETECT, S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_NONE},
+#else
+	{GPIO_SIM_DETECT, S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+#endif
+	{GPIO_ACCESSORY_INT,	S3C_GPIO_INPUT,  2, S3C_GPIO_PULL_NONE},
+	{GPIO_MSENSE_INT,	S3C_GPIO_INPUT,  2, S3C_GPIO_PULL_NONE},
+	{GPIO_FUEL_ALERT,	S3C_GPIO_INPUT,  2, S3C_GPIO_PULL_NONE},
+	/* {GPIO_BT_HOST_WAKE, S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_NONE}, */
+	{GPIO_DET_35,		S3C_GPIO_INPUT,  2, S3C_GPIO_PULL_NONE},
+	{GPIO_USB_OTG_EN,	S3C_GPIO_OUTPUT, 0, S3C_GPIO_PULL_NONE},
+	/* T_FLASH_DETECT */
+	{EXYNOS4_GPX3(4),	S3C_GPIO_INPUT,  2, S3C_GPIO_PULL_NONE},
+	/* TA_nCONNECTED */
+	{EXYNOS4_GPX3(5),	S3C_GPIO_INPUT,  2, S3C_GPIO_PULL_NONE},
+	{GPIO_HDMI_HPD,		S3C_GPIO_INPUT,  2, S3C_GPIO_PULL_NONE},
+
+	/* NC */
+	{EXYNOS4_GPY0(0), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY0(1), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY0(2), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY0(3), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY0(4), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY0(5), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPY1(0), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY1(1), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY1(2), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY1(3), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPY2(0), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY2(1), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY2(2), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY2(3), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY2(4), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY2(5), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPY3(1), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY3(3), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPY5(4), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(6), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(7), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPY6(2), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(3), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+
+#ifdef CONFIG_SEC_MODEM /* NC Pin for RF version */
+	{GPIO_IPC_RXD, S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{GPIO_IPC_TXD, S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+#else /* NC Pin for WIFI version */
+	{EXYNOS4_GPY3(6), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY4(2), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{GPIO_PHONE_ON, S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{GPIO_IPC_SLAVE_WAKEUP, S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{GPIO_IPC_HOST_WAKEUP,	S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{GPIO_CP_DUMP_INT,	S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{GPIO_SUSPEND_REQUEST,	S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{GPIO_CP_RST,		S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{GPIO_PHONE_ACTIVE, S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{GPIO_ACTIVE_STATE, S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{GPIO_CP_REQ_RESET, S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+#endif
+};
+
+void p4_config_gpio_table(void)
+{
+	u32 i, gpio;
+
+	printk(KERN_DEBUG "%s\n", __func__);
+
+	for (i = 0; i < ARRAY_SIZE(p4_init_gpios); i++) {
+		gpio = p4_init_gpios[i].num;
+		s3c_gpio_cfgpin(gpio, p4_init_gpios[i].cfg);
+		s3c_gpio_setpull(gpio, p4_init_gpios[i].pud);
+
+		if (p4_init_gpios[i].val != S3C_GPIO_SETPIN_NONE)
+			gpio_set_value(gpio, p4_init_gpios[i].val);
+
+		s5p_gpio_set_drvstr(gpio, p4_init_gpios[i].drv);
+	}
+}
+
+/* this table only for c1 board */
+static unsigned int p4_sleep_gpio_table[][3] = {
+	{EXYNOS4_GPA0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+	{EXYNOS4_GPA0(1),  S3C_GPIO_SLP_OUT1,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA0(3),  S3C_GPIO_SLP_OUT1,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPA0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPA1(0),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA1(1),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+#ifdef CONFIG_SEC_MODEM
+	{EXYNOS4_GPA1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA1(5),  S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+#else
+	{EXYNOS4_GPA1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA1(5),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+#endif
+
+	{EXYNOS4_GPB(0),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPB(1),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPB(2),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+	{EXYNOS4_GPB(3),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+	{EXYNOS4_GPB(4),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPB(5),   S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPB(6),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(7),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+#ifdef CONFIG_SEC_MODEM
+	{EXYNOS4_GPC0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4_GPC0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+#endif
+	{EXYNOS4_GPC0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#ifdef CONFIG_SEC_MODEM
+	{EXYNOS4_GPC0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPC0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPC0(4),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4_GPC0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPC0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPC0(4),  S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+#endif
+	{EXYNOS4_GPC1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+#ifdef CONFIG_SEC_MODEM
+	{EXYNOS4_GPC1(1),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4_GPC1(1),  S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+#endif
+	{EXYNOS4_GPC1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPC1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPC1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPD0(0),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPD0(1),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPD0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPD0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPD1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+	{EXYNOS4_GPD1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+	{EXYNOS4_GPD1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPD1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4210_GPE0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4210_GPE1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE1(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE1(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4210_GPE2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4210_GPE3(0),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE3(1),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE3(2),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE3(3),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE3(4),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE3(5),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE3(6),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE3(7),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4210_GPE4(0),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE4(1),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE4(2),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE4(3),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE4(4),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE4(5),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE4(6),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE4(7),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPF0(0),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF0(1),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF0(2),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF0(3),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF0(4),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF0(5),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF0(6),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF0(7),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPF1(0),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF1(1),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF1(2),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF1(3),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF1(4),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF1(5),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF1(6),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF1(7),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPF2(0),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF2(1),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF2(2),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF2(3),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF2(4),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF2(5),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF2(6),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF2(7),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPF3(0),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF3(1),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF3(2),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF3(3),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF3(4),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF3(5),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4210_GPJ0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPJ0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPJ0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPJ0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPJ0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPJ0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPJ0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPJ0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4210_GPJ1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPJ1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPJ1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPJ1(3),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPJ1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPK0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK0(2),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPK1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK1(1),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK1(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPK2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPK3(0),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+	{EXYNOS4_GPK3(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+	{EXYNOS4_GPK3(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+	{EXYNOS4_GPK3(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+	{EXYNOS4_GPK3(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+
+	{EXYNOS4_GPL0(0),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL0(1),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL0(2),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL0(3),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL0(4),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL0(5),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL0(6),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL0(7),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPL1(0),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL1(1),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL1(2),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPL2(0),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL2(1),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL2(2),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL2(4),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+	{EXYNOS4_GPL2(6),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL2(7),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPY0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPY1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPY2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	/* MHL_SDA_1.8V */
+	{EXYNOS4_GPY3(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	/* MHL_SCL_1.8V */
+	{EXYNOS4_GPY3(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY3(4),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+#ifdef CONFIG_SEC_MODEM
+	{EXYNOS4_GPY3(5),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(6),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4_GPY3(5),  S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY3(6),  S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+#endif
+	/* USB_SEL2 */
+	{EXYNOS4_GPY3(7),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPY4(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	/* GPIO_PDA_ACTIVE */
+#ifdef CONFIG_SEC_MODEM
+	{EXYNOS4_GPY4(2),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4_GPY4(2),  S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+#endif
+	{EXYNOS4_GPY4(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	/* V_ACCESSORY_5V CHECK */
+	{EXYNOS4_GPY4(4),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	/* USB_SEL3 */
+	{EXYNOS4_GPY4(5),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+#ifdef CONFIG_SEC_MODEM
+	/* GPIO_CP_REQ_RESET */
+	{EXYNOS4_GPY4(6),  S3C_GPIO_SLP_OUT1,  S3C_GPIO_PULL_NONE},
+#else
+	/* GPIO_CP_REQ_RESET */
+	{EXYNOS4_GPY4(6),  S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+#endif
+	/* GPIO_UART_SEL */
+	{EXYNOS4_GPY4(7),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+
+	/* HW_REV0 */
+	{EXYNOS4_GPY5(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	/* HW_REV1 */
+	{EXYNOS4_GPY5(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	/* HW_REV2 */
+	{EXYNOS4_GPY5(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	/* HW_REV3 */
+	{EXYNOS4_GPY5(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY5(4),  S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY5(5),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY5(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY5(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPY6(0),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	/* ACCESSORY_EN */
+	{EXYNOS4_GPY6(1),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY6(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY6(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY6(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+	{EXYNOS4_GPY6(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY6(6),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE}, /* TA_EN */
+	{EXYNOS4_GPY6(7),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPZ(0),   S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPZ(1),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPZ(2),   S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPZ(3),   S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPZ(4),   S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPZ(5),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPZ(6),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+};
+
+static void config_sleep_gpio_table(int array_size,
+				    unsigned int (*gpio_table)[3])
+{
+	u32 i, gpio;
+
+	for (i = 0; i < array_size; i++) {
+		gpio = gpio_table[i][0];
+		s3c_gpio_slp_cfgpin(gpio, gpio_table[i][1]);
+		s3c_gpio_slp_setpull_updown(gpio, gpio_table[i][2]);
+	}
+}
+
+void p4_config_sleep_gpio_table(void)
+{
+	config_sleep_gpio_table(ARRAY_SIZE(p4_sleep_gpio_table),
+			p4_sleep_gpio_table);
+}
diff --git a/arch/arm/mach-exynos/p4-input.c b/arch/arm/mach-exynos/p4-input.c
new file mode 100644
index 0000000..1420f41
--- /dev/null
+++ b/arch/arm/mach-exynos/p4-input.c
@@ -0,0 +1,378 @@
+/*
+ *  arch/arm/mach-exynos/p4-input.c
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/i2c.h>
+#include <linux/err.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <plat/gpio-cfg.h>
+#include <plat/iic.h>
+
+#if defined(CONFIG_RMI4_I2C)
+#include <linux/rmi.h>
+static int synaptics_tsp_pre_suspend(const void *pm_data)
+{
+	if (NULL == pm_data)
+		return -1;
+	printk(KERN_DEBUG "[TSP] %s\n", __func__);
+
+	s3c_gpio_cfgpin(GPIO_TSP_SDA_18V, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TSP_SDA_18V, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TSP_SDA_18V, 0);
+	s3c_gpio_cfgpin(GPIO_TSP_SCL_18V, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TSP_SCL_18V, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TSP_SCL_18V, 0);
+
+	s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TSP_INT, 0);
+	s3c_gpio_cfgpin(GPIO_TSP_RST, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TSP_RST, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TSP_RST, 0);
+	s3c_gpio_cfgpin(GPIO_TSP_LDO_ON, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TSP_LDO_ON, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TSP_LDO_ON, 0);
+
+	return 0;
+}
+
+static int synaptics_tsp_post_resume(const void *pm_data)
+{
+	if (NULL == pm_data)
+		return -1;
+	printk(KERN_DEBUG "[TSP] %s\n", __func__);
+
+	s3c_gpio_cfgpin(GPIO_TSP_SDA_18V, S3C_GPIO_SFN(0x3));
+	s3c_gpio_setpull(GPIO_TSP_SDA_18V, S3C_GPIO_PULL_UP);
+	s3c_gpio_cfgpin(GPIO_TSP_SCL_18V, S3C_GPIO_SFN(0x3));
+	s3c_gpio_setpull(GPIO_TSP_SCL_18V, S3C_GPIO_PULL_UP);
+
+	s3c_gpio_cfgpin(GPIO_TSP_LDO_ON, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TSP_LDO_ON, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TSP_LDO_ON, 1);
+	s3c_gpio_cfgpin(GPIO_TSP_RST, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TSP_RST, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TSP_RST, 1);
+	s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_NONE);
+	s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_SFN(0xf));
+
+	return 0;
+}
+
+static void synaptics_tsp_reset(void)
+{
+	printk(KERN_DEBUG "[TSP] %s\n", __func__);
+	s3c_gpio_cfgpin(GPIO_TSP_RST, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TSP_RST, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TSP_RST, 0);
+	msleep(100);
+	gpio_set_value(GPIO_TSP_RST, 1);
+}
+
+static struct rmi_device_platform_data synaptics_pdata = {
+	.driver_name = "rmi-generic",
+	.sensor_name = "s7301",
+	.attn_gpio = GPIO_TSP_INT,
+	.attn_polarity = RMI_ATTN_ACTIVE_LOW,
+	.axis_align = { },
+	.pm_data = NULL,
+	.pre_suspend = synaptics_tsp_pre_suspend,
+	.post_resume = synaptics_tsp_post_resume,
+	.hw_reset = synaptics_tsp_reset,
+};
+#endif	/* CONFIG_RMI4_I2C */
+
+#if defined(CONFIG_TOUCHSCREEN_SYNAPTICS_S7301)
+#include <linux/synaptics_s7301.h>
+static bool have_tsp_ldo;
+static struct charger_callbacks *charger_callbacks;
+
+void synaptics_ts_charger_infom(bool en)
+{
+	if (charger_callbacks && charger_callbacks->inform_charger)
+		charger_callbacks->inform_charger(charger_callbacks, en);
+}
+
+static void synaptics_ts_register_callback(struct charger_callbacks *cb)
+{
+	charger_callbacks = cb;
+	printk(KERN_DEBUG "[TSP] %s\n", __func__);
+}
+
+static int synaptics_ts_set_power(bool en)
+{
+	if (!have_tsp_ldo)
+		return -1;
+	printk(KERN_DEBUG "[TSP] %s(%d)\n", __func__, en);
+
+	if (en) {
+		s3c_gpio_cfgpin(GPIO_TSP_SDA_18V, S3C_GPIO_SFN(0x3));
+		s3c_gpio_setpull(GPIO_TSP_SDA_18V, S3C_GPIO_PULL_UP);
+		s3c_gpio_cfgpin(GPIO_TSP_SCL_18V, S3C_GPIO_SFN(0x3));
+		s3c_gpio_setpull(GPIO_TSP_SCL_18V, S3C_GPIO_PULL_UP);
+
+		s3c_gpio_cfgpin(GPIO_TSP_LDO_ON, S3C_GPIO_OUTPUT);
+		s3c_gpio_setpull(GPIO_TSP_LDO_ON, S3C_GPIO_PULL_NONE);
+		gpio_set_value(GPIO_TSP_LDO_ON, 1);
+		s3c_gpio_cfgpin(GPIO_TSP_RST, S3C_GPIO_OUTPUT);
+		s3c_gpio_setpull(GPIO_TSP_RST, S3C_GPIO_PULL_NONE);
+		gpio_set_value(GPIO_TSP_RST, 1);
+		s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_NONE);
+		s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_SFN(0xf));
+	} else {
+		s3c_gpio_cfgpin(GPIO_TSP_SDA_18V, S3C_GPIO_OUTPUT);
+		s3c_gpio_setpull(GPIO_TSP_SDA_18V, S3C_GPIO_PULL_NONE);
+		gpio_set_value(GPIO_TSP_SDA_18V, 0);
+		s3c_gpio_cfgpin(GPIO_TSP_SCL_18V, S3C_GPIO_OUTPUT);
+		s3c_gpio_setpull(GPIO_TSP_SCL_18V, S3C_GPIO_PULL_NONE);
+		gpio_set_value(GPIO_TSP_SCL_18V, 0);
+
+		s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_OUTPUT);
+		s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_NONE);
+		gpio_set_value(GPIO_TSP_INT, 0);
+		s3c_gpio_cfgpin(GPIO_TSP_RST, S3C_GPIO_OUTPUT);
+		s3c_gpio_setpull(GPIO_TSP_RST, S3C_GPIO_PULL_NONE);
+		gpio_set_value(GPIO_TSP_RST, 0);
+		s3c_gpio_cfgpin(GPIO_TSP_LDO_ON, S3C_GPIO_OUTPUT);
+		s3c_gpio_setpull(GPIO_TSP_LDO_ON, S3C_GPIO_PULL_NONE);
+		gpio_set_value(GPIO_TSP_LDO_ON, 0);
+	}
+
+	return 0;
+}
+
+static void synaptics_ts_reset(void)
+{
+	printk(KERN_DEBUG "[TSP] %s\n", __func__);
+	s3c_gpio_cfgpin(GPIO_TSP_RST, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_TSP_RST, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_TSP_RST, 0);
+	msleep(100);
+	gpio_set_value(GPIO_TSP_RST, 1);
+}
+
+static struct synaptics_platform_data synaptics_ts_pdata = {
+	.gpio_attn = GPIO_TSP_INT,
+	.max_x = 1279,
+	.max_y = 799,
+	.max_pressure = 255,
+	.max_width = 100,
+	.x_line = 27,
+	.y_line = 42,
+	.set_power = synaptics_ts_set_power,
+	.hw_reset = synaptics_ts_reset,
+	.register_cb = synaptics_ts_register_callback,
+};
+#endif	/* CONFIG_TOUCHSCREEN_SYNAPTICS_S7301 */
+
+static struct i2c_board_info i2c_devs3[] __initdata = {
+	{
+#if defined(CONFIG_RMI4_I2C)
+		I2C_BOARD_INFO(SYNAPTICS_RMI_NAME,
+			SYNAPTICS_RMI_ADDR),
+		.platform_data = &synaptics_pdata,
+#endif	/* CONFIG_RMI4_I2C */
+#if defined(CONFIG_TOUCHSCREEN_SYNAPTICS_S7301)
+		I2C_BOARD_INFO(SYNAPTICS_TS_NAME,
+			SYNAPTICS_TS_ADDR),
+		.platform_data = &synaptics_ts_pdata,
+#endif	/* CONFIG_TOUCHSCREEN_SYNAPTICS_S7301 */
+	},
+};
+
+void __init p4_tsp_init(u32 system_rev)
+{
+	int gpio;
+
+	printk(KERN_DEBUG "[TSP] %s rev : %u\n",
+		__func__, system_rev);
+
+	gpio = GPIO_TSP_RST;
+	gpio_request(gpio, "TSP_RST");
+	gpio_direction_output(gpio, 1);
+	gpio_export(gpio, 0);
+
+	gpio = GPIO_TSP_LDO_ON;
+	gpio_request(gpio, "TSP_LDO_ON");
+	gpio_direction_output(gpio, 1);
+	gpio_export(gpio, 0);
+
+	gpio = GPIO_TSP_INT;
+	gpio_request(gpio, "TSP_INT");
+
+	s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
+	s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+	s5p_register_gpio_interrupt(gpio);
+	i2c_devs3[0].irq = gpio_to_irq(gpio);
+	if (1 <= system_rev)
+#if defined(CONFIG_RMI4_I2C)
+		synaptics_pdata.pm_data =
+			(char *)synaptics_pdata.sensor_name;
+#else
+		have_tsp_ldo = true;
+#endif
+
+#ifdef CONFIG_S3C_DEV_I2C3
+	s3c_i2c3_set_platdata(NULL);
+	i2c_register_board_info(3, i2c_devs3,
+		ARRAY_SIZE(i2c_devs3));
+#endif
+}
+
+#if defined(CONFIG_EPEN_WACOM_G5SP)
+#include <linux/wacom_i2c.h>
+static struct wacom_g5_callbacks *wacom_callbacks;
+static int wacom_init_hw(void);
+static int wacom_suspend_hw(void);
+static int wacom_resume_hw(void);
+static int wacom_early_suspend_hw(void);
+static int wacom_late_resume_hw(void);
+static int wacom_reset_hw(void);
+static void wacom_register_callbacks(struct wacom_g5_callbacks *cb);
+
+static struct wacom_g5_platform_data wacom_platform_data = {
+	.x_invert = 0,
+	.y_invert = 0,
+	.xy_switch = 0,
+	.gpio_pendct = GPIO_PEN_PDCT_18V,
+	.init_platform_hw = wacom_init_hw,
+	.suspend_platform_hw = wacom_suspend_hw,
+	.resume_platform_hw = wacom_resume_hw,
+	.early_suspend_platform_hw = wacom_early_suspend_hw,
+	.late_resume_platform_hw = wacom_late_resume_hw,
+	.reset_platform_hw = wacom_reset_hw,
+	.register_cb = wacom_register_callbacks,
+};
+
+static struct i2c_board_info i2c_devs6[] __initdata = {
+	{
+		I2C_BOARD_INFO("wacom_g5sp_i2c", 0x56),
+		.platform_data = &wacom_platform_data,
+	},
+};
+
+static void wacom_register_callbacks(struct wacom_g5_callbacks *cb)
+{
+	wacom_callbacks = cb;
+};
+
+static int wacom_init_hw(void)
+{
+	int ret;
+	ret = gpio_request(GPIO_PEN_LDO_EN, "PEN_LDO_EN");
+	if (ret) {
+		printk(KERN_ERR "[E-PEN] faile to request gpio(GPIO_PEN_LDO_EN)\n");
+		return ret;
+	}
+	s3c_gpio_cfgpin(GPIO_PEN_LDO_EN, S3C_GPIO_SFN(0x1));
+	s3c_gpio_setpull(GPIO_PEN_LDO_EN, S3C_GPIO_PULL_NONE);
+	gpio_direction_output(GPIO_PEN_LDO_EN, 1);
+
+	ret = gpio_request(GPIO_PEN_PDCT_18V, "PEN_PDCT");
+	if (ret) {
+		printk(KERN_ERR "[E-PEN] faile to request gpio(GPIO_PEN_PDCT_18V)\n");
+		return ret;
+	}
+	s3c_gpio_cfgpin(GPIO_PEN_PDCT_18V, S3C_GPIO_SFN(0xf));
+	s3c_gpio_setpull(GPIO_PEN_PDCT_18V, S3C_GPIO_PULL_UP);
+
+	ret = gpio_request(GPIO_PEN_IRQ_18V, "PEN_IRQ");
+	if (ret) {
+		printk(KERN_ERR "[E-PEN] faile to request gpio(GPIO_PEN_IRQ_18V)\n");
+		return ret;
+	}
+	s3c_gpio_cfgpin(GPIO_PEN_IRQ_18V, S3C_GPIO_SFN(0xf));
+	s3c_gpio_setpull(GPIO_PEN_IRQ_18V, S3C_GPIO_PULL_DOWN);
+	s5p_register_gpio_interrupt(GPIO_PEN_IRQ_18V);
+	i2c_devs6[0].irq = gpio_to_irq(GPIO_PEN_IRQ_18V);
+	return 0;
+}
+
+static int wacom_suspend_hw(void)
+{
+	return wacom_early_suspend_hw();
+}
+
+static int wacom_resume_hw(void)
+{
+	return wacom_late_resume_hw();
+}
+
+static int wacom_early_suspend_hw(void)
+{
+	gpio_set_value(GPIO_PEN_LDO_EN, 0);
+	return 0;
+}
+
+static int wacom_late_resume_hw(void)
+{
+	gpio_set_value(GPIO_PEN_LDO_EN, 1);
+	return 0;
+}
+
+static int wacom_reset_hw(void)
+{
+	return 0;
+}
+
+void __init p4_wacom_init(void)
+{
+	wacom_init_hw();
+#ifdef CONFIG_S3C_DEV_I2C6
+	s3c_i2c6_set_platdata(NULL);
+	i2c_register_board_info(6, i2c_devs6, ARRAY_SIZE(i2c_devs6));
+#endif
+}
+#endif	/* CONFIG_EPEN_WACOM_G5SP */
+
+#if defined(CONFIG_KEYBOARD_GPIO)
+#include <mach/sec_debug.h>
+#include <linux/gpio_keys.h>
+#define GPIO_KEYS(_code, _gpio, _active_low, _iswake, _hook)	\
+{							\
+	.code = _code,					\
+	.gpio = _gpio,					\
+	.active_low = _active_low,			\
+	.type = EV_KEY,					\
+	.wakeup = _iswake,				\
+	.debounce_interval = 10,			\
+	.isr_hook = _hook,				\
+	.value = 1					\
+}
+
+struct gpio_keys_button p4_buttons[] = {
+	GPIO_KEYS(KEY_VOLUMEUP, GPIO_VOL_UP,
+		  1, 1, sec_debug_check_crash_key),
+	GPIO_KEYS(KEY_VOLUMEDOWN, GPIO_VOL_DOWN,
+		  1, 1, sec_debug_check_crash_key),
+	GPIO_KEYS(KEY_POWER, GPIO_nPOWER,
+		  1, 1, sec_debug_check_crash_key),
+};
+
+struct gpio_keys_platform_data p4_gpiokeys_platform_data = {
+	p4_buttons,
+	ARRAY_SIZE(p4_buttons),
+};
+
+static struct platform_device p4_keypad = {
+	.name	= "gpio-keys",
+	.dev	= {
+		.platform_data = &p4_gpiokeys_platform_data,
+	},
+};
+#endif
+void __init p4_key_init(void)
+{
+#if defined(CONFIG_KEYBOARD_GPIO)
+	platform_device_register(&p4_keypad);
+#endif
+}
+
diff --git a/arch/arm/mach-exynos/p4note-gpio.c b/arch/arm/mach-exynos/p4note-gpio.c
new file mode 100644
index 0000000..b28cc00
--- /dev/null
+++ b/arch/arm/mach-exynos/p4note-gpio.c
@@ -0,0 +1,587 @@
+/*
+ *  linux/arch/arm/mach-exynos/midas-gpio.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * EXYNOS - GPIO setting in set board
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/gpio.h>
+#include <linux/serial_core.h>
+#include <plat/devs.h>
+#include <plat/gpio-cfg.h>
+#include <plat/regs-serial.h>
+#include <mach/gpio-midas.h>
+#include <plat/cpu.h>
+#include <mach/pmu.h>
+
+struct gpio_init_data {
+	uint num;
+	uint cfg;
+	uint val;
+	uint pud;
+	uint drv;
+};
+
+extern int s3c_gpio_slp_cfgpin(unsigned int pin, unsigned int config);
+extern int s3c_gpio_slp_setpull_updown(unsigned int pin, unsigned int config);
+
+#ifdef CONFIG_MIDAS_COMMON
+/*
+ * P4NOTE GPIO Init Table
+ */
+static struct gpio_init_data p4note_init_gpios[] = {
+#if defined(CONFIG_SEC_MODEM)
+	{EXYNOS4_GPA1(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4_GPA1(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+#endif
+
+	{EXYNOS4_GPD0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPD0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPD1(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPD1(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPD1(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* GSENSE_SDA_1.8V */
+	{EXYNOS4_GPD1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* GSENSE_SCL_1.8V */
+
+	{EXYNOS4_GPX0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* ADC_IC_INT */
+	{EXYNOS4_GPX0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* PS_ALS_INT */
+	{EXYNOS4_GPX0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* DET_3.5 */
+	{EXYNOS4_GPX0(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* DOCK_INT */
+	{EXYNOS4_GPX0(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* REMOTE_SENSE_IRQ */
+	{EXYNOS4_GPX0(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* GYRO_INT */
+
+	{EXYNOS4_GPX0(7), S3C_GPIO_SFN(0xF), S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* AP_PMIC_IRQ */
+
+	{EXYNOS4_GPX1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* ACCESSORY_INT */
+	{EXYNOS4_GPX1(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* TA_INT */
+	{EXYNOS4_GPX1(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* OVP_FLAG */
+#if defined(CONFIG_SEC_MODEM)
+	{EXYNOS4_GPX1(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* SIM_DETECT */
+#endif
+
+	{EXYNOS4_GPX2(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPX2(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPX2(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* FUEL_ALERT */
+	{EXYNOS4_GPX2(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* BT_HOST_WAKEUP */
+	{EXYNOS4_GPX2(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* nPower */
+
+	{EXYNOS4_GPX3(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* IF_CON_SENSE */
+	{EXYNOS4_GPX3(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* BT_WAKE */
+#if defined(CONFIG_SEC_MODEM)
+	{EXYNOS4_GPX3(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* CP_PMU_RST */
+#endif
+	{EXYNOS4_GPX3(5), S3C_GPIO_SFN(0xF), S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* V_ACCESSORY_5V */
+
+	{EXYNOS4_GPK1(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4_GPK1(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4_GPK1(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+
+	{EXYNOS4_GPK3(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_CMD */
+	{EXYNOS4_GPK3(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(0) */
+	{EXYNOS4_GPK3(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(1) */
+	{EXYNOS4_GPK3(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(2) */
+	{EXYNOS4_GPK3(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(3) */
+
+#if !defined(CONFIG_SEC_MODEM)
+	{EXYNOS4212_GPM0(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+#endif
+	{EXYNOS4212_GPM3(0), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* PMIC_DVS1 */
+
+	{EXYNOS4_GPY0(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4_GPY0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4_GPY1(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4_GPY1(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4_GPY1(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4_GPY1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4_GPY2(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+
+	{EXYNOS4212_GPJ1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* CAM_MCLK */
+	{EXYNOS4212_GPM2(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* VTCAM_MCLK */
+};
+
+/*
+ * P4NOTE GPIO Sleep Table
+ */
+static unsigned int p4note_sleep_gpio_table[][3] = {
+	{EXYNOS4_GPA0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(1),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+	{EXYNOS4_GPA0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+
+	{EXYNOS4_GPA1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+#if defined(CONFIG_SEC_MODEM)
+	{EXYNOS4_GPA1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC(IPC_RXD) */
+	{EXYNOS4_GPA1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC(IPC_TXD) */
+#else
+	{EXYNOS4_GPA1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* IPC_RXD */
+	/*
+	 * UART3-TXD : It should be pulled up during sleep, if this uart is
+	 * used for PC connection like a factory command program.
+	 * Otherwise, a PC might get null characters like noise.
+	 * In addition, LPA mode is also applied to this comment, because
+	 * LPA mode invokes this GPIO sleep configuration.
+	 */
+	{EXYNOS4_GPA1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, /* IPC_TXD */
+#endif
+
+	{EXYNOS4_GPB(0),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(1),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(2),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(3),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(4),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPB(5),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPB(6),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPB(7),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPC0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* REC_PCM_CLK(NC) */
+	{EXYNOS4_GPC0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPC0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* REC_PCM_SYNC(NC) */
+	{EXYNOS4_GPC0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* REC_PCM_IN(NC) */
+	{EXYNOS4_GPC0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* REC_PCM_OUT(NC) */
+#if defined(CONFIG_SEC_MODEM_M0_TD)
+	{EXYNOS4_GPC1(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4_GPC1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, /* PEN_PDCT */
+#endif
+	{EXYNOS4_GPC1(1),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* PEN_LDO_EN */
+
+	{EXYNOS4_GPC1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, /* PEN_IRQ_1.8V */
+	{EXYNOS4_GPC1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, /* PEN_SDA_1.8V */
+	{EXYNOS4_GPC1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, /* PEN_SCL_1.8V */
+
+	{EXYNOS4_GPD0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPD0(1),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LED_BACKLIGHT_PWM */
+	{EXYNOS4_GPD0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPD0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPD1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* 3M_SDA_1.8V */
+	{EXYNOS4_GPD1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* 3M_SCL_1.8V */
+	{EXYNOS4_GPD1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPD1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPF0(0),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LCD_HSYNC */
+	{EXYNOS4_GPF0(1),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LCD_VSYNC */
+	{EXYNOS4_GPF0(2),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LCD_DE */
+	{EXYNOS4_GPF0(3),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LCD_PCLK */
+	{EXYNOS4_GPF0(4),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LCD_D */
+	{EXYNOS4_GPF0(5),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LCD_D */
+	{EXYNOS4_GPF0(6),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LCD_D */
+	{EXYNOS4_GPF0(7),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LCD_D */
+
+	{EXYNOS4_GPF1(0),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LCD_D */
+	{EXYNOS4_GPF1(1),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LCD_D */
+	{EXYNOS4_GPF1(2),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LCD_D */
+	{EXYNOS4_GPF1(3),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LCD_D */
+	{EXYNOS4_GPF1(4),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LCD_D */
+	{EXYNOS4_GPF1(5),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LCD_D */
+	{EXYNOS4_GPF1(6),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LCD_D */
+	{EXYNOS4_GPF1(7),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LCD_D */
+
+	{EXYNOS4_GPF2(0),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LCD_D */
+	{EXYNOS4_GPF2(1),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LCD_D */
+	{EXYNOS4_GPF2(2),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LCD_D */
+	{EXYNOS4_GPF2(3),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LCD_D */
+	{EXYNOS4_GPF2(4),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LCD_D */
+	{EXYNOS4_GPF2(5),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LCD_D */
+	{EXYNOS4_GPF2(6),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LCD_D */
+	{EXYNOS4_GPF2(7),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LCD_D */
+
+	{EXYNOS4_GPF3(0),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LCD_D */
+	{EXYNOS4_GPF3(1),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LCD_D */
+	{EXYNOS4_GPF3(2),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LCD_D */
+	{EXYNOS4_GPF3(3),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LCD_D */
+	{EXYNOS4_GPF3(4),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* MHL_RST */
+	{EXYNOS4_GPF3(5),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* MHL_INT */
+
+	{EXYNOS4_GPK0(0),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_CLK */
+	{EXYNOS4_GPK0(1),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_CMD */
+	{EXYNOS4_GPK0(2),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* eMMC_EN */
+	{EXYNOS4_GPK0(3),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(0) */
+	{EXYNOS4_GPK0(4),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(1) */
+	{EXYNOS4_GPK0(5),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(2) */
+	{EXYNOS4_GPK0(6),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(3) */
+
+	{EXYNOS4_GPK1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPK1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK1(3),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(4) */
+	{EXYNOS4_GPK1(4),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(5) */
+	{EXYNOS4_GPK1(5),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(6) */
+	{EXYNOS4_GPK1(6),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(7) */
+
+	{EXYNOS4_GPK2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPK2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPK3(0),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPK3(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+#if defined(CONFIG_SEC_MODEM)
+	{EXYNOS4_GPL0(0),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* ACTIVE_STATE_HSIC */
+#else
+	{EXYNOS4_GPL0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+	{EXYNOS4_GPL0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* PS_ALS_SCL_1.8V */
+	{EXYNOS4_GPL0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* PS_ALS_SDA_1.8V */
+	{EXYNOS4_GPL0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC(IRDA_CONTROL) */
+	{EXYNOS4_GPL0(4),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* HDMI_EN */
+/*	{EXYNOS4_GPL0(5),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE}, */
+	{EXYNOS4_GPL0(6),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+/*	{EXYNOS4_GPL0(7),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE}, */
+
+#if defined(CONFIG_SEC_MODEM)
+	{EXYNOS4_GPL1(0),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* PDA_ACTIVE */
+#else
+	{EXYNOS4_GPL1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+	{EXYNOS4_GPL1(1),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* 3M_nRST */
+/*	{EXYNOS4_GPL1(2),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE}, */
+
+	{EXYNOS4_GPL2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPL2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPL2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW)
+	/* GLP2(4) CMC_CPU_RESET, hold high */
+	{EXYNOS4_GPL2(4),  S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* NC */
+#else
+	{EXYNOS4_GPL2(4),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* MOTOR_EN */
+#endif
+	{EXYNOS4_GPL2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CP_ON(NC) */
+	{EXYNOS4_GPL2(6),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL2(7),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* UART_SEL */
+
+	{EXYNOS4_GPY0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPY0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPY0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* USB_SEL0 */
+	{EXYNOS4_GPY0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* USB_SEL1 */
+
+	{EXYNOS4_GPY1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},	/* NC */
+	{EXYNOS4_GPY1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY2(0),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* TF_EN */
+	{EXYNOS4_GPY2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPY3(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY3(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY3(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY3(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY3(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY3(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY3(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY3(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPY4(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY4(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY4(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY4(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY4(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY4(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY4(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY4(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPY5(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPY6(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPZ(0),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPZ(1),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPZ(2),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPZ(3),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPZ(4),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPZ(5),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPZ(6),   S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	/* Exynos4212 specific gpio */
+	{EXYNOS4212_GPJ0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_PCLK */
+	{EXYNOS4212_GPJ0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_VSYNC */
+	{EXYNOS4212_GPJ0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_HSYNC */
+	{EXYNOS4212_GPJ0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_D */
+	{EXYNOS4212_GPJ0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_D */
+	{EXYNOS4212_GPJ0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_D */
+	{EXYNOS4212_GPJ0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_D */
+	{EXYNOS4212_GPJ0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_D */
+
+	{EXYNOS4212_GPJ1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_D */
+	{EXYNOS4212_GPJ1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_D */
+	{EXYNOS4212_GPJ1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_D */
+	{EXYNOS4212_GPJ1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_MCLK */
+	{EXYNOS4212_GPJ1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPM0(0),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* MICBIAS_EN */
+	{EXYNOS4212_GPM0(1),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LED_BACKLIGHT_RESET */
+	{EXYNOS4212_GPM0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* TA_nCHG */
+	{EXYNOS4212_GPM0(4),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* TSP_RST */
+	{EXYNOS4212_GPM0(5),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LVDS_nSHDN */
+	{EXYNOS4212_GPM0(6),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* 3M_nSTBY */
+#if defined(CONFIG_SEC_MODEM)
+	{EXYNOS4212_GPM0(7),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* USB_SEL_CP */
+#else
+	{EXYNOS4212_GPM0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+
+	{EXYNOS4212_GPM1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* MOTOR_I2C_SDA */
+	{EXYNOS4212_GPM1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* MOTOR_I2C_SCL */
+	{EXYNOS4212_GPM1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* HW_REV0 */
+	{EXYNOS4212_GPM1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* HW_REV1 */
+	{EXYNOS4212_GPM1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* HW_REV2 */
+	{EXYNOS4212_GPM1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* HW_REV3 */
+	{EXYNOS4212_GPM1(6),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* 2M_nRST */
+
+	{EXYNOS4212_GPM2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4212_GPM2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4212_GPM2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPM2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* SUSPEND_REQUEST_HSIC(NC) */
+
+	{EXYNOS4212_GPM3(0),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* PMIC_DVS1 */
+	{EXYNOS4212_GPM3(1),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* PMIC_DVS2 */
+	{EXYNOS4212_GPM3(2),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* PMIC_DVS3 */
+#if defined(CONFIG_SEC_MODEM)
+	{EXYNOS4212_GPM3(3),  S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* RESET_REQ_N */
+#else
+	{EXYNOS4212_GPM3(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+	{EXYNOS4212_GPM3(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* AP_DUMP_INT(NC) */
+	{EXYNOS4212_GPM3(5),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* WLAN_EN */
+	{EXYNOS4212_GPM3(6),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CAM_MOVIE_EN */
+	{EXYNOS4212_GPM3(7),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* CAM_FLASH_EN */
+
+	{EXYNOS4212_GPM4(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* ADC_I2C_SCL_1.8V */
+	{EXYNOS4212_GPM4(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* ADC_I2C_SDA_1.8V */
+	{EXYNOS4212_GPM4(2),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* TA_ENABLE */
+	{EXYNOS4212_GPM4(3),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* 2M_nSTBY */
+	{EXYNOS4212_GPM4(4),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE}, /* CODEC_LDO_EN */
+	{EXYNOS4212_GPM4(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM4(6),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* USB_OTG_EN */
+	{EXYNOS4212_GPM4(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* MSENSE_INT */
+
+	{EXYNOS4212_GPV0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPV1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV1(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPV2(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV2(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPV3(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV3(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4212_GPV4(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4212_GPV4(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+}; /* p4note_sleep_gpio_table */
+
+/*
+ * P4NOTE Rev0.9 GPIO Sleep Table
+ */
+static unsigned int p4note_sleep_gpio_table_rev09[][3] = {
+	{EXYNOS4212_GPJ0(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPJ0(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPJ0(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPJ0(3),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* EAR_MICBIAS_EN */
+	{EXYNOS4212_GPJ0(4),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* TA_ENABLE */
+	{EXYNOS4212_GPJ0(5),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* CAM_EN2 */
+	{EXYNOS4212_GPJ0(6),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* CAM_EN1 */
+	{EXYNOS4212_GPJ0(7),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* 5M_nSTBY */
+
+	{EXYNOS4212_GPJ1(0),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* VT_CAM_nRST */
+	{EXYNOS4212_GPJ1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPJ1(2),  S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* LINEOUT_EN */
+	{EXYNOS4212_GPJ1(3),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* 5M_MCLK */
+
+	{EXYNOS4212_GPM0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM1(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4212_GPM2(2),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* VT_CAM_MCLK */
+	{EXYNOS4212_GPM4(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* VT_CAM_SCL_1.8V */
+	{EXYNOS4212_GPM4(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* VT_CAM_SDA_1.8V */
+	{EXYNOS4212_GPM4(5),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* TSP_LDO_ON */
+};
+
+struct p4note_sleep_table {
+	unsigned int (*ptr)[3];
+	int size;
+};
+
+#define GPIO_TABLE(_ptr) \
+	{.ptr = _ptr, \
+	.size = ARRAY_SIZE(_ptr)} \
+
+ #define GPIO_TABLE_NULL \
+	{.ptr = NULL, \
+	.size = 0} \
+
+static struct p4note_sleep_table p4note_sleep_table[] = {
+	GPIO_TABLE(p4note_sleep_gpio_table),			/* Rev0.8(0x0) */
+	GPIO_TABLE(p4note_sleep_gpio_table_rev09),		/* Rev0.9(0x1) */
+};
+#endif /* CONFIG_MIDAS_COMMON */
+
+static void config_sleep_gpio_table(int array_size,
+				    unsigned int (*gpio_table)[3])
+{
+	u32 i, gpio;
+
+	for (i = 0; i < array_size; i++) {
+		gpio = gpio_table[i][0];
+		s3c_gpio_slp_cfgpin(gpio, gpio_table[i][1]);
+		s3c_gpio_slp_setpull_updown(gpio, gpio_table[i][2]);
+	}
+}
+
+#ifdef CONFIG_MIDAS_COMMON
+void p4note_config_sleep_gpio_table(void)
+{
+	int i;
+	int index = min(ARRAY_SIZE(p4note_sleep_table), system_rev + 1);
+
+	for (i = 0; i < index; i++) {
+		if (p4note_sleep_table[i].ptr == NULL)
+			continue;
+
+		config_sleep_gpio_table(p4note_sleep_table[i].size,
+				p4note_sleep_table[i].ptr);
+	}
+}
+#endif
+
+/* To save power consumption, gpio pin set before enterling sleep */
+void midas_config_sleep_gpio_table(void)
+{
+	p4note_config_sleep_gpio_table();
+}
+
+/* Intialize gpio set in midas board */
+void midas_config_gpio_table(void)
+{
+	u32 i, gpio;
+
+	printk(KERN_DEBUG "%s\n", __func__);
+
+	for (i = 0; i < ARRAY_SIZE(p4note_init_gpios); i++) {
+		gpio = p4note_init_gpios[i].num;
+		if (gpio <= EXYNOS4212_GPV4(1)) {
+			s3c_gpio_cfgpin(gpio, p4note_init_gpios[i].cfg);
+			s3c_gpio_setpull(gpio, p4note_init_gpios[i].pud);
+
+			if (p4note_init_gpios[i].val != S3C_GPIO_SETPIN_NONE)
+				gpio_set_value(gpio, p4note_init_gpios[i].val);
+
+			s5p_gpio_set_drvstr(gpio, p4note_init_gpios[i].drv);
+		}
+	}
+}
diff --git a/arch/arm/mach-exynos/p4note-jack.c b/arch/arm/mach-exynos/p4note-jack.c
new file mode 100644
index 0000000..2a4d0df
--- /dev/null
+++ b/arch/arm/mach-exynos/p4note-jack.c
@@ -0,0 +1,126 @@
+/* arch/arm/mach-exynos/p4note-jack.c
+ *
+ * Copyright (C) 2012 Samsung Electronics Co, Ltd
+ *
+ * Based on mach-exynos/mach-p4notepq.c
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <mach/gpio-midas.h>
+#include <linux/input.h>
+#include <linux/platform_device.h>
+#include <linux/sec_jack.h>
+
+static void sec_set_jack_micbias(bool on)
+{
+	gpio_set_value(GPIO_EAR_MIC_BIAS_EN, on);
+}
+
+static struct sec_jack_zone sec_jack_zones[] = {
+	{
+		/* adc == 0, unstable zone, default to 3pole if it stays
+		 * in this range for 300ms (15ms delays, 20 samples)
+		 */
+		.adc_high = 0,
+		.delay_ms = 15,
+		.check_count = 20,
+		.jack_type = SEC_HEADSET_3POLE,
+	},
+	{
+		/* 0 < adc <= 1200, unstable zone, default to 3pole if it stays
+		 * in this range for 300ms (15ms delays, 20 samples)
+		 */
+		.adc_high = 1200,
+		.delay_ms = 10,
+		.check_count = 80,
+		.jack_type = SEC_HEADSET_3POLE,
+	},
+	{
+		/* 1200 < adc <= 2600, unstable zone, default to 4pole if it
+		 * stays in this range for 800ms (10ms delays, 80 samples)
+		 */
+		.adc_high = 2600,
+		.delay_ms = 10,
+		.check_count = 10,
+		.jack_type = SEC_HEADSET_4POLE,
+	},
+	{
+		/* 2600 < adc <= 3800, 3 pole zone, default to 3pole if it
+		 * stays in this range for 100ms (10ms delays, 10 samples)
+		 */
+		.adc_high = 3800,
+		.delay_ms = 10,
+		.check_count = 5,
+		.jack_type = SEC_HEADSET_4POLE,
+	},
+	{
+		/* adc > 3800, unstable zone, default to 3pole if it stays
+		 * in this range for two seconds (10ms delays, 200 samples)
+		 */
+		.adc_high = 0x7fffffff,
+		.delay_ms = 10,
+		.check_count = 200,
+		.jack_type = SEC_HEADSET_3POLE,
+	},
+};
+
+/* To support 3-buttons earjack */
+static struct sec_jack_buttons_zone sec_jack_buttons_zones[] = {
+	{
+		/* 0 <= adc <=190, stable zone */
+		.code = KEY_MEDIA,
+		.adc_low = 0,
+		.adc_high = 190,
+	},
+	{
+		/* 191 <= adc <= 420, stable zone */
+		.code = KEY_VOLUMEUP,
+		.adc_low = 191,
+		.adc_high = 420,
+	},
+	{
+		/* 421 <= adc <= 860, stable zone */
+		.code = KEY_VOLUMEDOWN,
+		.adc_low = 421,
+		.adc_high = 860,
+	},
+};
+
+static struct sec_jack_platform_data sec_jack_data = {
+	.set_micbias_state = sec_set_jack_micbias,
+	.zones = sec_jack_zones,
+	.num_zones = ARRAY_SIZE(sec_jack_zones),
+	.buttons_zones = sec_jack_buttons_zones,
+	.num_buttons_zones = ARRAY_SIZE(sec_jack_buttons_zones),
+	.det_gpio = GPIO_DET_35,
+	.send_end_gpio = GPIO_EAR_SEND_END,
+};
+
+static struct platform_device sec_device_jack = {
+	.name = "sec_jack",
+	.id = 1,		/* will be used also for gpio_event id */
+	.dev.platform_data = &sec_jack_data,
+};
+void __init p4note_jack_init(void)
+{
+	/* Ear Microphone BIAS */
+	int err;
+	err = gpio_request(GPIO_EAR_MIC_BIAS_EN, "EAR MIC");
+	if (err) {
+		pr_err(KERN_ERR "GPIO_EAR_MIC_BIAS_EN GPIO set error!\n");
+		return;
+	}
+	gpio_direction_output(GPIO_EAR_MIC_BIAS_EN, 1);
+	gpio_set_value(GPIO_EAR_MIC_BIAS_EN, 0);
+	gpio_free(GPIO_EAR_MIC_BIAS_EN);
+
+	platform_device_register(&sec_device_jack);
+}
diff --git a/arch/arm/mach-exynos/p4note-power.c b/arch/arm/mach-exynos/p4note-power.c
new file mode 100644
index 0000000..14769a6
--- /dev/null
+++ b/arch/arm/mach-exynos/p4note-power.c
@@ -0,0 +1,1112 @@
+/*
+ * midas-power.c - Power Management of MIDAS Project
+ *
+ *  Copyright (C) 2011 Samsung Electrnoics
+ *  Chiwoong Byun <woong.byun@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/i2c.h>
+#include <linux/regulator/machine.h>
+#include <plat/gpio-cfg.h>
+#include <mach/gpio-midas.h>
+#include <mach/irqs.h>
+
+#include <linux/mfd/max8997.h>
+#include <linux/mfd/max77686.h>
+#include <linux/mfd/max77693.h>
+
+#if defined(CONFIG_REGULATOR_S5M8767)
+#include <linux/mfd/s5m87xx/s5m-pmic.h>
+#include <linux/mfd/s5m87xx/s5m-core.h>
+#endif
+
+#ifdef CONFIG_REGULATOR_MAX8997
+/* MOTOR */
+#ifdef CONFIG_VIBETONZ
+static void max8997_motor_init(void)
+{
+	gpio_request(GPIO_VIBTONE_EN, "VIBTONE_EN");
+	s3c_gpio_cfgpin(GPIO_VIBTONE_EN, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_VIBTONE_EN, S3C_GPIO_PULL_NONE);
+}
+
+static void max8997_motor_en(bool en)
+{
+	gpio_direction_output(GPIO_VIBTONE_EN, en);
+}
+
+static struct max8997_motor_data max8997_motor = {
+	.max_timeout = 10000,
+	.duty = 44000,
+	.period = 44642,
+	.reg2 = MOTOR_LRA | EXT_PWM | DIVIDER_128,
+	.init_hw = max8997_motor_init,
+	.motor_en = max8997_motor_en,
+	.pwm_id = 1,
+};
+#endif
+
+/* max8997 */
+static struct regulator_consumer_supply ldo1_supply[] = {
+	REGULATOR_SUPPLY("vmipi_1.8v", NULL),
+	REGULATOR_SUPPLY("VDD18", "s5p-mipi-dsim"),
+};
+
+#ifdef CONFIG_SND_SOC_WM8994
+static struct regulator_consumer_supply ldo6_supply[] = {
+	REGULATOR_SUPPLY("AVDD2", NULL),
+	REGULATOR_SUPPLY("CPVDD", NULL),
+	REGULATOR_SUPPLY("DBVDD1", NULL),
+	REGULATOR_SUPPLY("DBVDD2", NULL),
+	REGULATOR_SUPPLY("DBVDD3", NULL),
+};
+#endif
+
+static struct regulator_consumer_supply ldo7_supply[] = {
+	REGULATOR_SUPPLY("cam_sensor_core_1.2v", NULL),
+};
+
+static struct regulator_consumer_supply ldo8_supply[] = {
+	REGULATOR_SUPPLY("votg_3.0v", NULL),
+};
+
+static struct regulator_consumer_supply ldo11_supply[] = {
+	REGULATOR_SUPPLY("vmipi_1.0v", NULL),
+	REGULATOR_SUPPLY("VDD10", "s5p-mipi-dsim"),
+};
+
+static struct regulator_consumer_supply ldo13_supply[] = {
+	REGULATOR_SUPPLY("vlcd_3.3v", NULL),
+	REGULATOR_SUPPLY("VCI", "s6e8aa0"),
+};
+
+static struct regulator_consumer_supply ldo14_supply[] = {
+	REGULATOR_SUPPLY("vcc_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo15_supply[] = {
+	REGULATOR_SUPPLY("vlcd_2.2v", NULL),
+	REGULATOR_SUPPLY("VDD3", "s6e8aa0"),
+};
+
+static struct regulator_consumer_supply ldo12_supply[] = {
+	REGULATOR_SUPPLY("vt_cam_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo16_supply[] = {
+	REGULATOR_SUPPLY("cam_isp_sensor_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo17_supply[] = {
+	REGULATOR_SUPPLY("cam_af_2.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo18_supply[] = {
+	REGULATOR_SUPPLY("touch", NULL),
+};
+
+static struct regulator_consumer_supply max8997_buck1 =
+	REGULATOR_SUPPLY("vdd_arm", NULL);
+
+static struct regulator_consumer_supply max8997_buck2[] = {
+	REGULATOR_SUPPLY("vdd_int", NULL),
+	REGULATOR_SUPPLY("vdd_int", "exynos4412-busfreq"),
+};
+
+static struct regulator_consumer_supply max8997_buck3 =
+	REGULATOR_SUPPLY("vdd_g3d", NULL);
+
+static struct regulator_consumer_supply max8997_buck4 =
+	REGULATOR_SUPPLY("cam_isp_core_1.2v", NULL);
+
+#define REGULATOR_INIT(_ldo, _name, _min_uV, _max_uV, _always_on, _ops_mask, \
+		       _disabled)					\
+	static struct regulator_init_data _ldo##_init_data = {		\
+		.constraints = {					\
+			.name	= _name,				\
+			.min_uV = _min_uV,				\
+			.max_uV = _max_uV,				\
+			.always_on	= _always_on,			\
+			.boot_on	= _always_on,			\
+			.apply_uV	= 1,				\
+			.valid_ops_mask = _ops_mask,			\
+			.state_mem = {					\
+				.disabled	= _disabled,		\
+				.enabled	= !(_disabled),		\
+			}						\
+		},							\
+		.num_consumer_supplies = ARRAY_SIZE(_ldo##_supply),	\
+		.consumer_supplies = &_ldo##_supply[0],			\
+	};
+
+REGULATOR_INIT(ldo1, "VMIPI_1.8V", 1800000, 1800000, 1,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo6, "VCC_1.8V_AP", 1800000, 1800000, 1, 0, 0);
+REGULATOR_INIT(ldo7, "CAM_SENSOR_CORE_1.2V", 1200000, 1200000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo8, "VUOTG_3.0V", 3000000, 3000000, 1,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo11, "VMIPI_1.0V", 1000000, 1000000, 1,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo12, "VT_CAM_1.8V", 1800000, 1800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo13, "VCC_3.3V_LCD", 3300000, 3300000, 1,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo14, "VCC_1.8V_IO", 1800000, 1800000, 1,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo15, "VDD_2.2V_LCD", 2200000, 2200000, 1,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo16, "CAM_ISP_SENSOR_1.8V", 1800000, 1800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo17, "CAM_AF_2.8V", 2800000, 2800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo18, "TSP_AVDD_3.3V", 3300000, 3300000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+
+static struct regulator_init_data max8997_buck1_data = {
+	.constraints	= {
+		.name	= "vdd_arm range",
+		.min_uV	= 950000,
+		.max_uV	= 1100000,
+		.always_on = 1,
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+		.state_mem = {
+			.disabled = 1,
+		},
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &max8997_buck1,
+};
+
+static struct regulator_init_data max8997_buck2_data = {
+	.constraints	= {
+		.name	= "vdd_int range",
+		.min_uV	= 900000,
+		.max_uV	= 1100000,
+		.always_on = 1,
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+		.state_mem = {
+			.disabled = 1,
+		},
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max8997_buck2),
+	.consumer_supplies = max8997_buck2,
+};
+
+static struct regulator_init_data max8997_buck3_data = {
+	.constraints	= {
+		.name	= "vdd_g3d range",
+		.min_uV	= 950000,
+		.max_uV	= 1150000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+		REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.disabled = 1,
+		},
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &max8997_buck3,
+};
+
+static struct regulator_init_data max8997_buck4_data = {
+	.constraints	= {
+		.name	= "CAM_ISP_CORE_1.2V",
+		.min_uV	= 1200000,
+		.max_uV	= 1200000,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.disabled = 1,
+		},
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &max8997_buck4,
+};
+
+static struct max8997_regulator_data max8997_regulators[] = {
+	{ MAX8997_BUCK1, &max8997_buck1_data, },
+	{ MAX8997_BUCK2, &max8997_buck2_data, },
+	{ MAX8997_BUCK3, &max8997_buck3_data, },
+	{ MAX8997_BUCK4, &max8997_buck4_data, },
+	{ MAX8997_LDO1, &ldo1_init_data, },
+	{ MAX8997_LDO6, &ldo6_init_data, },
+	{ MAX8997_LDO7, &ldo7_init_data, },
+	{ MAX8997_LDO8, &ldo8_init_data, },
+	{ MAX8997_LDO11, &ldo11_init_data, },
+	{ MAX8997_LDO12, &ldo12_init_data, },
+	{ MAX8997_LDO13, &ldo13_init_data, },
+	{ MAX8997_LDO14, &ldo14_init_data, },
+	{ MAX8997_LDO15, &ldo15_init_data, },
+	{ MAX8997_LDO16, &ldo16_init_data, },
+	{ MAX8997_LDO17, &ldo17_init_data, },
+	{ MAX8997_LDO18, &ldo18_init_data, },
+};
+
+struct max8997_platform_data exynos4_max8997_info = {
+	.irq_base = IRQ_BOARD_PMIC_START,
+	.num_regulators = ARRAY_SIZE(max8997_regulators),
+	.regulators = max8997_regulators,
+	.buck1_max_vol = 1100000,
+	.buck2_max_vol = 1100000,
+	.buck5_max_vol = 1100000,
+	.buck_set1 = EXYNOS4212_GPJ1(1),
+	.buck_set2 = EXYNOS4212_GPJ1(2),
+	.buck_set3 = EXYNOS4_GPL0(0),
+#ifdef CONFIG_VIBETONZ
+	.motor = &max8997_motor,
+#endif
+};
+#elif defined(CONFIG_REGULATOR_MAX77686)
+/* max77686 */
+
+#ifdef CONFIG_SND_SOC_WM8994
+static struct regulator_consumer_supply ldo3_supply[] = {
+	REGULATOR_SUPPLY("AVDD2", NULL),
+	REGULATOR_SUPPLY("CPVDD", NULL),
+	REGULATOR_SUPPLY("DBVDD1", NULL),
+	REGULATOR_SUPPLY("DBVDD2", NULL),
+	REGULATOR_SUPPLY("DBVDD3", NULL),
+};
+#else
+static struct regulator_consumer_supply ldo3_supply[] = {};
+#endif
+
+static struct regulator_consumer_supply ldo5_supply[] = {
+	REGULATOR_SUPPLY("vcc_1.8v", NULL),
+	REGULATOR_SUPPLY("touchkey", NULL), /*touchkey*/
+};
+
+static struct regulator_consumer_supply ldo8_supply[] = {
+	REGULATOR_SUPPLY("vmipi_1.0v", NULL),
+	REGULATOR_SUPPLY("VDD10", "s5p-mipi-dsim.0"),
+	REGULATOR_SUPPLY("vdd", "exynos4-hdmi"),
+	REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"),
+};
+
+static struct regulator_consumer_supply ldo9_supply[] = {
+	REGULATOR_SUPPLY("cam_isp_mipi_1.2v", NULL),
+};
+
+static struct regulator_consumer_supply ldo10_supply[] = {
+	REGULATOR_SUPPLY("vmipi_1.8v", NULL),
+	REGULATOR_SUPPLY("VDD18", "s5p-mipi-dsim.0"),
+	REGULATOR_SUPPLY("vdd_osc", "exynos4-hdmi"),
+};
+
+static struct regulator_consumer_supply ldo11_supply[] = {
+	REGULATOR_SUPPLY("vabb1_1.9v", NULL),
+};
+
+static struct regulator_consumer_supply ldo12_supply[] = {
+	REGULATOR_SUPPLY("votg_3.0v", NULL),
+};
+
+#if defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT) || \
+	defined(CONFIG_MACH_C1_KOR_LGT)
+static struct regulator_consumer_supply ldo13_supply[] = {
+	REGULATOR_SUPPLY("vusbhub_osc_1.8v", NULL),
+};
+#endif
+
+static struct regulator_consumer_supply ldo14_supply[] = {
+	REGULATOR_SUPPLY("vabb2_1.9v", NULL),
+};
+
+static struct regulator_consumer_supply ldo18_supply[] = {
+	REGULATOR_SUPPLY("cam_io_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo19_supply[] = {
+	REGULATOR_SUPPLY("vt_core_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo21_supply[] = {
+	REGULATOR_SUPPLY("vtf_2.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo23_supply[] = {
+	REGULATOR_SUPPLY("vdd_adc_3.3v", NULL),
+};
+
+static struct regulator_consumer_supply ldo24_supply[] = {
+	REGULATOR_SUPPLY("cam_a2.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo25_supply[] = {
+	REGULATOR_SUPPLY("vled_3.3v", NULL),
+	REGULATOR_SUPPLY("VCI", "s6e8aa0"),
+};
+
+static struct regulator_consumer_supply ldo26_supply[] = {
+	REGULATOR_SUPPLY("3mp_af_2.8v", NULL),
+};
+
+static struct regulator_consumer_supply max77686_buck1[] = {
+	REGULATOR_SUPPLY("vdd_mif", NULL),
+	REGULATOR_SUPPLY("vdd_mif", "exynos4412-busfreq"),
+};
+
+static struct regulator_consumer_supply max77686_buck2 =
+	REGULATOR_SUPPLY("vdd_arm", NULL);
+
+static struct regulator_consumer_supply max77686_buck3[] = {
+	REGULATOR_SUPPLY("vdd_int", NULL),
+	REGULATOR_SUPPLY("vdd_int", "exynoss4412-busfreq"),
+};
+
+static struct regulator_consumer_supply max77686_buck4[] = {
+	REGULATOR_SUPPLY("vdd_g3d", NULL),
+	REGULATOR_SUPPLY("vdd_g3d", "mali_dev.0"),
+};
+
+static struct regulator_consumer_supply max77686_buck9 =
+	REGULATOR_SUPPLY("3mp_core_1.2v", NULL);
+
+static struct regulator_consumer_supply max77686_enp32khz[] = {
+	REGULATOR_SUPPLY("lpo_in", "bcm47511"),
+	REGULATOR_SUPPLY("lpo", "bcm4334_bluetooth"),
+};
+
+#define REGULATOR_INIT(_ldo, _name, _min_uV, _max_uV, _always_on, _ops_mask, \
+		       _disabled)					\
+	static struct regulator_init_data _ldo##_init_data = {		\
+		.constraints = {					\
+			.name = _name,					\
+			.min_uV = _min_uV,				\
+			.max_uV = _max_uV,				\
+			.always_on	= _always_on,			\
+			.boot_on	= _always_on,			\
+			.apply_uV	= 1,				\
+			.valid_ops_mask = _ops_mask,			\
+			.state_mem = {					\
+				.disabled	= _disabled,		\
+				.enabled	= !(_disabled),		\
+			}						\
+		},							\
+		.num_consumer_supplies = ARRAY_SIZE(_ldo##_supply),	\
+		.consumer_supplies = &_ldo##_supply[0],			\
+	};
+
+REGULATOR_INIT(ldo3, "VCC_1.8V_AP", 1800000, 1800000, 1, 0, 0);
+REGULATOR_INIT(ldo5, "VCC_1.8V_IO", 1800000, 1800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo8, "VMIPI_1.0V", 1000000, 1000000, 1,
+	       REGULATOR_CHANGE_STATUS, 0);
+REGULATOR_INIT(ldo9, "CAM_ISP_MIPI_1.2V", 1200000, 1200000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo10, "VMIPI_1.8V", 1800000, 1800000, 1,
+	       REGULATOR_CHANGE_STATUS, 0);
+REGULATOR_INIT(ldo11, "VABB1_1.9V", 1950000, 1950000, 1,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo12, "VUOTG_3.0V", 3000000, 3000000, 1,
+	       REGULATOR_CHANGE_STATUS, 0);
+#if defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT) || \
+	defined(CONFIG_MACH_C1_KOR_LGT)
+REGULATOR_INIT(ldo13, "VUSBHUB_OSC_1.8V", 1800000, 1800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+#endif
+REGULATOR_INIT(ldo14, "VABB2_1.9V", 1950000, 1950000, 1,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo18, "CAM_IO_1.8V", 1800000, 1800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo19, "VT_CORE_1.8V", 1800000, 1800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo21, "VTF_2.8V", 2800000, 2800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo23, "VDD_ADC_3.3V", 3300000, 3300000, 1,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo24, "CAM_A2.8V", 2800000, 2800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+#if defined(CONFIG_TARGET_LOCALE_USA)
+REGULATOR_INIT(ldo25, "VLED_3.3V", 3300000, 3300000, 1,
+	       REGULATOR_CHANGE_STATUS, 1);
+#else
+REGULATOR_INIT(ldo25, "VLED_3.3V", 3300000, 3300000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+#endif
+REGULATOR_INIT(ldo26, "3MP_AF_2.8V", 2800000, 2800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+
+#if defined(CONFIG_MACH_SLP_PQ)
+static struct regulator_init_data ldo24_pq11_init_data = {
+	.constraints = {
+		.name = "VDD_1.8V_TSP",
+		.min_uV = 1800000,
+		.max_uV = 1800000,
+		.always_on = 0,
+		.boot_on = 0,
+		.apply_uV = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.enabled	= 0,
+			.disabled	= 1,
+		}
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = ldo24_supply,
+};
+#endif
+
+static struct regulator_init_data max77686_buck1_data = {
+	.constraints = {
+		.name = "vdd_mif range",
+		.min_uV = 850000,
+#ifdef CONFIG_SLP
+		.max_uV = 1100000,
+#else
+		.max_uV = 1050000,
+#endif
+		.always_on = 1,
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_buck1),
+	.consumer_supplies = max77686_buck1,
+};
+
+static struct regulator_init_data max77686_buck2_data = {
+	.constraints = {
+		.name = "vdd_arm range",
+		.min_uV = 850000,
+		.max_uV = 1500000,
+		.apply_uV = 1,
+		.always_on = 1,
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &max77686_buck2,
+};
+
+static struct regulator_init_data max77686_buck3_data = {
+	.constraints = {
+		.name = "vdd_int range",
+		.min_uV = 850000,
+#ifdef CONFIG_SLP
+		.max_uV = 1150000,
+#else
+		.max_uV = 1100000,
+#endif
+		.always_on = 1,
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_buck3),
+	.consumer_supplies = max77686_buck3,
+};
+
+static struct regulator_init_data max77686_buck4_data = {
+	.constraints = {
+		.name = "vdd_g3d range",
+		.min_uV = 850000,
+#ifdef CONFIG_SLP
+		.max_uV = 1100000,
+#else
+		.max_uV = 1075000,
+#endif
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+		REGULATOR_CHANGE_STATUS,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_buck4),
+	.consumer_supplies = max77686_buck4,
+};
+
+static struct regulator_init_data max77686_buck9_data = {
+	.constraints = {
+		.name = "3MP_CORE_1.2V",
+		.min_uV = 1200000,
+		.max_uV = 1200000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+		REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.disabled = 1,
+		},
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &max77686_buck9,
+};
+
+static struct regulator_init_data max77686_enp32khz_data = {
+	.constraints = {
+		.name = "32KHZ_PMIC",
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.enabled	= 1,
+			.disabled	= 0,
+		},
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_enp32khz),
+	.consumer_supplies = max77686_enp32khz,
+};
+
+static struct max77686_regulator_data max77686_regulators[] = {
+	{MAX77686_BUCK1, &max77686_buck1_data,},
+	{MAX77686_BUCK2, &max77686_buck2_data,},
+	{MAX77686_BUCK3, &max77686_buck3_data,},
+	{MAX77686_BUCK4, &max77686_buck4_data,},
+	{MAX77686_BUCK9, &max77686_buck9_data,},
+	{MAX77686_LDO3, &ldo3_init_data,},
+	{MAX77686_LDO5, &ldo5_init_data,},
+	{MAX77686_LDO8, &ldo8_init_data,},
+	{MAX77686_LDO9, &ldo9_init_data,},
+	{MAX77686_LDO10, &ldo10_init_data,},
+	{MAX77686_LDO11, &ldo11_init_data,},
+	{MAX77686_LDO12, &ldo12_init_data,},
+#if defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT) || \
+	defined(CONFIG_MACH_C1_KOR_LGT)
+	{MAX77686_LDO13, &ldo13_init_data,},
+#endif
+	{MAX77686_LDO14, &ldo14_init_data,},
+	{MAX77686_LDO18, &ldo18_init_data,},
+	{MAX77686_LDO19, &ldo19_init_data,},
+	{MAX77686_LDO21, &ldo21_init_data,},
+	{MAX77686_LDO23, &ldo23_init_data,},
+	{MAX77686_LDO24, &ldo24_init_data,},
+	{MAX77686_LDO25, &ldo25_init_data,},
+	{MAX77686_LDO26, &ldo26_init_data,},
+	{MAX77686_P32KH, &max77686_enp32khz_data,},
+};
+
+struct max77686_opmode_data max77686_opmode_data[MAX77686_REG_MAX] = {
+	[MAX77686_LDO3] = {MAX77686_LDO3, MAX77686_OPMODE_NORMAL},
+	[MAX77686_LDO8] = {MAX77686_LDO8, MAX77686_OPMODE_STANDBY},
+	[MAX77686_LDO10] = {MAX77686_LDO10, MAX77686_OPMODE_STANDBY},
+	[MAX77686_LDO11] = {MAX77686_LDO11, MAX77686_OPMODE_STANDBY},
+	[MAX77686_LDO12] = {MAX77686_LDO12, MAX77686_OPMODE_STANDBY},
+#if defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT) || \
+	defined(CONFIG_MACH_C1_KOR_LGT)
+	[MAX77686_LDO13] = {MAX77686_LDO13, MAX77686_OPMODE_NORMAL},
+#endif
+	[MAX77686_LDO14] = {MAX77686_LDO14, MAX77686_OPMODE_STANDBY},
+	[MAX77686_BUCK1] = {MAX77686_BUCK1, MAX77686_OPMODE_STANDBY},
+	[MAX77686_BUCK2] = {MAX77686_BUCK2, MAX77686_OPMODE_STANDBY},
+	[MAX77686_BUCK3] = {MAX77686_BUCK3, MAX77686_OPMODE_STANDBY},
+	[MAX77686_BUCK4] = {MAX77686_BUCK4, MAX77686_OPMODE_STANDBY},
+};
+
+struct max77686_platform_data exynos4_max77686_info = {
+	.num_regulators = ARRAY_SIZE(max77686_regulators),
+	.regulators = max77686_regulators,
+	.irq_gpio	= GPIO_PMIC_IRQ,
+	.irq_base	= IRQ_BOARD_PMIC_START,
+	.wakeup		= 1,
+
+	.opmode_data = max77686_opmode_data,
+	.ramp_rate = MAX77686_RAMP_RATE_27MV,
+
+	.buck234_gpio_dvs = {
+		/* Use DVS2 register of each bucks to supply stable power
+		 * after sudden reset */
+		{GPIO_PMIC_DVS1, 1},
+		{GPIO_PMIC_DVS2, 0},
+		{GPIO_PMIC_DVS3, 0},
+	},
+	.buck234_gpio_selb = {
+		GPIO_BUCK2_SEL,
+		GPIO_BUCK3_SEL,
+		GPIO_BUCK4_SEL,
+	},
+	.buck2_voltage[0] = 1100000,	/* 1.1V */
+	.buck2_voltage[1] = 1100000,	/* 1.1V */
+	.buck2_voltage[2] = 1100000,	/* 1.1V */
+	.buck2_voltage[3] = 1100000,	/* 1.1V */
+	.buck2_voltage[4] = 1100000,	/* 1.1V */
+	.buck2_voltage[5] = 1100000,	/* 1.1V */
+	.buck2_voltage[6] = 1100000,	/* 1.1V */
+	.buck2_voltage[7] = 1100000,	/* 1.1V */
+
+	.buck3_voltage[0] = 1100000,	/* 1.1V */
+	.buck3_voltage[1] = 1000000,	/* 1.0V */
+	.buck3_voltage[2] = 1100000,	/* 1.1V */
+	.buck3_voltage[3] = 1100000,	/* 1.1V */
+	.buck3_voltage[4] = 1100000,	/* 1.1V */
+	.buck3_voltage[5] = 1100000,	/* 1.1V */
+	.buck3_voltage[6] = 1100000,	/* 1.1V */
+	.buck3_voltage[7] = 1100000,	/* 1.1V */
+
+	.buck4_voltage[0] = 1100000,	/* 1.1V */
+	.buck4_voltage[1] = 1000000,	/* 1.0V */
+	.buck4_voltage[2] = 1100000,	/* 1.1V */
+	.buck4_voltage[3] = 1100000,	/* 1.1V */
+	.buck4_voltage[4] = 1100000,	/* 1.1V */
+	.buck4_voltage[5] = 1100000,	/* 1.1V */
+	.buck4_voltage[6] = 1100000,	/* 1.1V */
+	.buck4_voltage[7] = 1100000,	/* 1.1V */
+};
+
+void midas_power_init(void)
+{
+	printk(KERN_INFO "%s\n", __func__);
+
+#if defined(CONFIG_C1_KOR_SKT) || defined(CONFIG_C1_KOR_KT) || \
+	defined(CONFIG_C1_KOR_LGT)
+	if (system_rev >= 0x6)
+		ldo13_init_data.constraints.always_on = 1;
+#endif
+}
+#endif /* CONFIG_REGULATOR_MAX77686 */
+
+void midas_power_set_muic_pdata(void *pdata, int gpio)
+{
+	gpio_request(gpio, "AP_PMIC_IRQ");
+	s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
+	s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+
+#ifdef CONFIG_REGULATOR_MAX8997
+	exynos4_max8997_info.muic = pdata;
+#endif
+}
+
+void midas_power_gpio_init(void)
+{
+#ifdef CONFIG_REGULATOR_MAX8997
+	int gpio;
+
+	gpio = EXYNOS4212_GPJ1(1);
+	gpio_request(gpio, "BUCK_SET1");
+	s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+
+	gpio = EXYNOS4212_GPJ1(2);
+	gpio_request(gpio, "BUCK_SET2");
+	s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+
+	gpio = EXYNOS4_GPL0(0);
+	gpio_request(gpio, "BUCK_SET3");
+	s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+#endif
+}
+
+#ifdef CONFIG_MFD_MAX77693
+static struct regulator_consumer_supply safeout1_supply[] = {
+	REGULATOR_SUPPLY("safeout1", NULL),
+};
+
+static struct regulator_consumer_supply safeout2_supply[] = {
+	REGULATOR_SUPPLY("safeout2", NULL),
+};
+
+static struct regulator_consumer_supply charger_supply[] = {
+	REGULATOR_SUPPLY("vinchg1", "charger-manager.0"),
+	REGULATOR_SUPPLY("vinchg1", NULL),
+};
+
+static struct regulator_init_data safeout1_init_data = {
+	.constraints	= {
+		.name		= "safeout1 range",
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.always_on	= 0,
+		.boot_on	= 1,
+		.state_mem	= {
+			.enabled = 1,
+		},
+	},
+	.num_consumer_supplies	= ARRAY_SIZE(safeout1_supply),
+	.consumer_supplies	= safeout1_supply,
+};
+
+static struct regulator_init_data safeout2_init_data = {
+	.constraints	= {
+		.name		= "safeout2 range",
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.always_on	= 0,
+		.boot_on	= 0,
+		.state_mem	= {
+			.enabled = 1,
+		},
+	},
+	.num_consumer_supplies	= ARRAY_SIZE(safeout2_supply),
+	.consumer_supplies	= safeout2_supply,
+};
+
+static struct regulator_init_data charger_init_data = {
+	.constraints	= {
+		.name		= "CHARGER",
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS |
+		REGULATOR_CHANGE_CURRENT,
+		.boot_on	= 1,
+		.min_uA		= 60000,
+		.max_uA		= 2580000,
+	},
+	.num_consumer_supplies	= ARRAY_SIZE(charger_supply),
+	.consumer_supplies	= charger_supply,
+};
+
+struct max77693_regulator_data max77693_regulators[] = {
+	{MAX77693_ESAFEOUT1, &safeout1_init_data,},
+	{MAX77693_ESAFEOUT2, &safeout2_init_data,},
+	{MAX77693_CHARGER, &charger_init_data,},
+};
+
+#if defined(CONFIG_MACH_SLP_PQ)
+/* this initcall replace ldo24 from VDD 2.2 to VDD 1.8 for evt1.1 board. */
+static int __init regulator_init_with_rev(void)
+{
+	/* SLP PQ Promixa evt1.1 */
+	if (system_rev != 3) {
+		ldo24_supply[0].supply = "touch_1.8v";
+		ldo24_supply[0].dev_name = NULL;
+
+		memcpy(&ldo24_init_data, &ldo24_pq11_init_data,
+		       sizeof(struct regulator_init_data));
+	}
+	return 0;
+}
+
+postcore_initcall(regulator_init_with_rev);
+#endif /* CONFIG_MACH_SLP_PQ */
+#endif /* CONFIG_MFD_MAX77693 */
+
+#if defined(CONFIG_REGULATOR_S5M8767)
+/* S5M8767 Regulator */
+
+#ifdef CONFIG_SND_SOC_WM8994
+static struct regulator_consumer_supply ldo3_supply[] = {
+	REGULATOR_SUPPLY("AVDD2", NULL),
+	REGULATOR_SUPPLY("CPVDD", NULL),
+	REGULATOR_SUPPLY("DBVDD1", NULL),
+	REGULATOR_SUPPLY("DBVDD2", NULL),
+	REGULATOR_SUPPLY("DBVDD3", NULL),
+};
+#endif
+
+static struct regulator_consumer_supply ldo8_supply[] = {
+	REGULATOR_SUPPLY("vmipi_1.0v", NULL),
+	REGULATOR_SUPPLY("VDD10", "s5p-mipi-dsim.0"),
+};
+
+static struct regulator_consumer_supply ldo9_supply[] = {
+	REGULATOR_SUPPLY("cam_isp_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo10_supply[] = {
+	REGULATOR_SUPPLY("vt_cam_dvdd_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo13_supply[] = {
+	REGULATOR_SUPPLY("vmipi_1.8v", NULL),
+	REGULATOR_SUPPLY("VDD18", "s5p-mipi-dsim.0"),
+};
+
+static struct regulator_consumer_supply ldo19_supply[] = {
+	REGULATOR_SUPPLY("cam_af_2.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo20_supply[] = {
+	REGULATOR_SUPPLY("vlcd_3.0v", NULL),
+	REGULATOR_SUPPLY("VCI", "s6e8aa0"),
+};
+
+static struct regulator_consumer_supply ldo21_supply[] = {
+	REGULATOR_SUPPLY("vmotor", NULL),
+};
+
+static struct regulator_consumer_supply ldo22_supply[] = {
+	REGULATOR_SUPPLY("cam_sensor_a2.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo23_supply[] = {
+	REGULATOR_SUPPLY("vtf_2.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo24_supply[] = {
+	REGULATOR_SUPPLY("touch", NULL),
+};
+
+static struct regulator_consumer_supply ldo25_supply[] = {
+	REGULATOR_SUPPLY("cam_sensor_core_1.2v", NULL),
+};
+
+static struct regulator_consumer_supply ldo26_supply[] = {
+	REGULATOR_SUPPLY("cam_isp_sensor_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo27_supply[] = {
+	REGULATOR_SUPPLY("vt_cam_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply ldo28_supply[] = {
+	REGULATOR_SUPPLY("3_touch_1.8v", NULL),
+};
+
+static struct regulator_consumer_supply s5m8767_buck1[] = {
+	REGULATOR_SUPPLY("vdd_mif", NULL),
+	REGULATOR_SUPPLY("vdd_mif", "exynos4212-busfreq"),
+};
+
+static struct regulator_consumer_supply s5m8767_buck2 =
+	REGULATOR_SUPPLY("vdd_arm", NULL);
+
+static struct regulator_consumer_supply s5m8767_buck3[] = {
+	REGULATOR_SUPPLY("vdd_int", NULL),
+	REGULATOR_SUPPLY("vdd_int", "exynos4212-busfreq"),
+};
+
+static struct regulator_consumer_supply s5m8767_buck4[] = {
+	REGULATOR_SUPPLY("vdd_g3d", NULL),
+	REGULATOR_SUPPLY("vdd_g3d", "mali_dev.0"),
+};
+
+static struct regulator_consumer_supply s5m8767_buck6 =
+	REGULATOR_SUPPLY("cam_isp_core_1.2v", NULL);
+
+static struct regulator_consumer_supply s5m8767_enp32khz[] = {
+	REGULATOR_SUPPLY("lpo_in", "bcm47511"),
+	REGULATOR_SUPPLY("lpo", "bcm4334_bluetooth"),
+};
+
+#define REGULATOR_INIT(_ldo, _name, _min_uV, _max_uV, _always_on, _ops_mask, \
+		       _disabled)					\
+	static struct regulator_init_data _ldo##_init_data = {		\
+		.constraints = {					\
+			.name = _name,					\
+			.min_uV = _min_uV,				\
+			.max_uV = _max_uV,				\
+			.always_on	= _always_on,			\
+			.boot_on	= _always_on,			\
+			.apply_uV	= 1,				\
+			.valid_ops_mask = _ops_mask,			\
+			.state_mem = {					\
+				.disabled	= _disabled,		\
+				.enabled	= !(_disabled),		\
+			}						\
+		},							\
+		.num_consumer_supplies = ARRAY_SIZE(_ldo##_supply),	\
+		.consumer_supplies = &_ldo##_supply[0],			\
+	};
+
+REGULATOR_INIT(ldo3, "VCC_1.8V_AP", 1800000, 1800000, 1, 0, 0);
+REGULATOR_INIT(ldo8, "VMIPI_1.0V", 1000000, 1000000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo9, "CAM_ISP_1.8V", 1800000, 1800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo10, "VT_CAM_DVDD_1.8V", 1800000, 1800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo13, "VMIPI_1.8V", 1800000, 1800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo19, "CAM_AF_2.8V", 2800000, 2800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo20, "VCC_3.0V_LCD", 3000000, 3000000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo21, "VCC_MOTOR_3.0V", 3000000, 3000000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo22, "CAM_SENSOR_A2.8V", 2800000, 2800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo23, "VTF_2.8V", 2800000, 2800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo24, "TSP_AVDD_3.3V", 3300000, 3300000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo25, "CAM_SENSOR_CORE_1.2V", 1200000, 1200000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo26, "CAM_ISP_SENSOR_1.8V", 1800000, 1800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo27, "VT_CAM_1.8V", 1800000, 1800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+REGULATOR_INIT(ldo28, "3_TOUCH_1.8V", 1800000, 1800000, 0,
+	       REGULATOR_CHANGE_STATUS, 1);
+
+static struct regulator_init_data s5m8767_buck1_data = {
+	.constraints = {
+		.name = "vdd_mif range",
+		.min_uV = 850000,
+		.max_uV = 1100000,
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(s5m8767_buck1),
+	.consumer_supplies = s5m8767_buck1,
+};
+
+static struct regulator_init_data s5m8767_buck2_data = {
+	.constraints = {
+		.name = "vdd_arm range",
+		.min_uV = 850000,
+		.max_uV = 1500000,
+		.apply_uV = 1,
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &s5m8767_buck2,
+};
+
+static struct regulator_init_data s5m8767_buck3_data = {
+	.constraints = {
+		.name = "vdd_int range",
+		.min_uV = 850000,
+		.max_uV = 1300000,
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(s5m8767_buck3),
+	.consumer_supplies = s5m8767_buck3,
+};
+
+static struct regulator_init_data s5m8767_buck4_data = {
+	.constraints = {
+		.name = "vdd_g3d range",
+		.min_uV = 850000,
+		.max_uV = 1150000,
+		.boot_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+		REGULATOR_CHANGE_STATUS,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(s5m8767_buck4),
+	.consumer_supplies = s5m8767_buck4,
+};
+
+static struct regulator_init_data s5m8767_buck6_data = {
+	.constraints = {
+		.name = "CAM_ISP_CORE_1.2V",
+		.min_uV = 1000000,
+		.max_uV = 1200000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+		REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.disabled = 1,
+		},
+	},
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &s5m8767_buck6,
+};
+
+static struct regulator_init_data s5m8767_enp32khz_data = {
+	.constraints = {
+		.name = "32KHZ_PMIC",
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.enabled	= 1,
+			.disabled	= 0,
+		},
+	},
+	.num_consumer_supplies = ARRAY_SIZE(s5m8767_enp32khz),
+	.consumer_supplies = s5m8767_enp32khz,
+};
+
+static struct s5m_regulator_data s5m8767_regulators[] = {
+	{S5M8767_BUCK1, &s5m8767_buck1_data,},
+	{S5M8767_BUCK2, &s5m8767_buck2_data,},
+	{S5M8767_BUCK3, &s5m8767_buck3_data,},
+	{S5M8767_BUCK4, &s5m8767_buck4_data,},
+	{S5M8767_BUCK6, &s5m8767_buck6_data,},
+	{S5M8767_LDO3, &ldo3_init_data,},
+	{S5M8767_LDO8, &ldo8_init_data,},
+	{S5M8767_LDO9, &ldo9_init_data,},
+	{S5M8767_LDO10, &ldo10_init_data,},
+	{S5M8767_LDO13, &ldo13_init_data,},
+	{S5M8767_LDO19, &ldo19_init_data,},
+	{S5M8767_LDO20, &ldo20_init_data,},
+	{S5M8767_LDO21, &ldo21_init_data,},
+	{S5M8767_LDO22, &ldo22_init_data,},
+	{S5M8767_LDO23, &ldo23_init_data,},
+	{S5M8767_LDO24, &ldo24_init_data,},
+	{S5M8767_LDO25, &ldo25_init_data,},
+	{S5M8767_LDO26, &ldo26_init_data,},
+	{S5M8767_LDO27, &ldo27_init_data,},
+	{S5M8767_LDO28, &ldo28_init_data,},
+};
+
+struct s5m_opmode_data s5m8767_opmode_data[S5M8767_REG_MAX] = {
+	[S5M8767_BUCK1] = {S5M8767_BUCK1, S5M_OPMODE_STANDBY},
+	[S5M8767_BUCK2] = {S5M8767_BUCK2, S5M_OPMODE_STANDBY},
+	[S5M8767_BUCK3] = {S5M8767_BUCK3, S5M_OPMODE_STANDBY},
+	[S5M8767_BUCK4] = {S5M8767_BUCK4, S5M_OPMODE_STANDBY},
+	[S5M8767_BUCK6] = {S5M8767_BUCK6, S5M_OPMODE_STANDBY},
+	[S5M8767_LDO3] = {S5M8767_LDO3, S5M_OPMODE_NORMAL},
+	[S5M8767_LDO8] = {S5M8767_LDO8, S5M_OPMODE_NORMAL},
+	[S5M8767_LDO9] = {S5M8767_LDO9, S5M_OPMODE_NORMAL},
+	[S5M8767_LDO10] = {S5M8767_LDO10, S5M_OPMODE_NORMAL},
+	[S5M8767_LDO19] = {S5M8767_LDO19, S5M_OPMODE_NORMAL},
+	[S5M8767_LDO20] = {S5M8767_LDO20, S5M_OPMODE_NORMAL},
+	[S5M8767_LDO21] = {S5M8767_LDO21, S5M_OPMODE_NORMAL},
+	[S5M8767_LDO22] = {S5M8767_LDO22, S5M_OPMODE_NORMAL},
+	[S5M8767_LDO23] = {S5M8767_LDO23, S5M_OPMODE_STANDBY},
+	[S5M8767_LDO24] = {S5M8767_LDO24, S5M_OPMODE_NORMAL},
+	[S5M8767_LDO25] = {S5M8767_LDO25, S5M_OPMODE_NORMAL},
+	[S5M8767_LDO26] = {S5M8767_LDO26, S5M_OPMODE_NORMAL},
+	[S5M8767_LDO27] = {S5M8767_LDO27, S5M_OPMODE_NORMAL},
+	[S5M8767_LDO28] = {S5M8767_LDO28, S5M_OPMODE_NORMAL},
+};
+
+struct s5m_platform_data exynos4_s5m8767_info = {
+	.device_type	= S5M8767X,
+	.num_regulators = ARRAY_SIZE(s5m8767_regulators),
+	.regulators = s5m8767_regulators,
+	.buck2_ramp_enable	= true,
+	.buck3_ramp_enable	= true,
+	.buck4_ramp_enable	= true,
+	.irq_gpio	= GPIO_PMIC_IRQ,
+	.irq_base	= IRQ_BOARD_PMIC_START,
+	.wakeup		= 1,
+
+	.opmode_data = s5m8767_opmode_data,
+	.wtsr_smpl		= 1,
+
+	.buck2_voltage[0] = 1100000,	/* 1.1V */
+	.buck2_voltage[1] = 1100000,	/* 1.1V */
+	.buck2_voltage[2] = 1100000,	/* 1.1V */
+	.buck2_voltage[3] = 1100000,	/* 1.1V */
+	.buck2_voltage[4] = 1100000,	/* 1.1V */
+	.buck2_voltage[5] = 1100000,	/* 1.1V */
+	.buck2_voltage[6] = 1100000,	/* 1.1V */
+	.buck2_voltage[7] = 1100000,	/* 1.1V */
+
+	.buck3_voltage[0] = 1100000,	/* 1.1V */
+	.buck3_voltage[1] = 1100000,	/* 1.1V */
+	.buck3_voltage[2] = 1100000,	/* 1.1V */
+	.buck3_voltage[3] = 1100000,	/* 1.1V */
+	.buck3_voltage[4] = 1100000,	/* 1.1V */
+	.buck3_voltage[5] = 1100000,	/* 1.1V */
+	.buck3_voltage[6] = 1100000,	/* 1.1V */
+	.buck3_voltage[7] = 1100000,	/* 1.1V */
+
+	.buck4_voltage[0] = 1100000,	/* 1.1V */
+	.buck4_voltage[1] = 1100000,	/* 1.1V */
+	.buck4_voltage[2] = 1100000,	/* 1.1V */
+	.buck4_voltage[3] = 1100000,	/* 1.1V */
+	.buck4_voltage[4] = 1100000,	/* 1.1V */
+	.buck4_voltage[5] = 1100000,	/* 1.1V */
+	.buck4_voltage[6] = 1100000,	/* 1.1V */
+	.buck4_voltage[7] = 1100000,	/* 1.1V */
+
+	.buck_ramp_delay = 10,
+	.buck_default_idx	= 3,
+
+	.buck_gpios[0]		= GPIO_BUCK2_SEL,
+	.buck_gpios[1]		= GPIO_BUCK3_SEL,
+	.buck_gpios[2]		= GPIO_BUCK4_SEL,
+};
+
+void midas_power_init(void)
+{
+#ifdef CONFIG_MACH_S2PLUS
+	ldo8_init_data.constraints.always_on = 1;
+	ldo13_init_data.constraints.always_on = 1;
+#else
+	ldo8_init_data.constraints.always_on = 1;
+	ldo10_init_data.constraints.always_on = 1;
+#endif
+}
+
+/* End of S5M8767 */
+#endif
diff --git a/arch/arm/mach-exynos/p8-gpio.c b/arch/arm/mach-exynos/p8-gpio.c
new file mode 100644
index 0000000..135ec85
--- /dev/null
+++ b/arch/arm/mach-exynos/p8-gpio.c
@@ -0,0 +1,515 @@
+#include <linux/gpio.h>
+#include <linux/serial_core.h>
+#include <plat/devs.h>
+#include <plat/gpio-cfg.h>
+#include <plat/regs-serial.h>
+#include <mach/gpio.h>
+#include "px.h"
+
+struct gpio_init_data {
+	uint num;
+	uint cfg;
+	uint val;
+	uint pud;
+	uint drv;
+};
+
+static struct gpio_init_data p8_init_gpios[] = {
+	{
+		.num	= EXYNOS4_GPD0(2),	/* MSENSOR_MHL_SDA_2.8V */
+		.cfg	= S3C_GPIO_INPUT,
+		.val	= S3C_GPIO_SETPIN_NONE,
+		.pud	= S3C_GPIO_PULL_NONE,
+		.drv	= S5P_GPIO_DRVSTR_LV1,
+	}, {
+		.num	= EXYNOS4_GPD0(3),	/* MSENSOR_MHL_SCL_2.8V */
+		.cfg	= S3C_GPIO_INPUT,
+		.val	= S3C_GPIO_SETPIN_NONE,
+		.pud	= S3C_GPIO_PULL_NONE,
+		.drv	= S5P_GPIO_DRVSTR_LV1,
+	},  {
+		.num	= EXYNOS4_GPD1(2),	/* SENSE_SDA_2.8V */
+		.cfg	= S3C_GPIO_INPUT,
+		.val	= S3C_GPIO_SETPIN_NONE,
+		.pud	= S3C_GPIO_PULL_NONE,
+		.drv	= S5P_GPIO_DRVSTR_LV1,
+	}, {
+		.num	= EXYNOS4_GPD1(3),	/* SENSE_SCL_2.8V */
+		.cfg	= S3C_GPIO_INPUT,
+		.val	= S3C_GPIO_SETPIN_NONE,
+		.pud	= S3C_GPIO_PULL_NONE,
+		.drv	= S5P_GPIO_DRVSTR_LV1,
+	}, {
+		.num	= EXYNOS4_GPK2(2),	/* PS_ALS_SDA_2.8V */
+		.cfg	= S3C_GPIO_INPUT,
+		.val	= S3C_GPIO_SETPIN_NONE,
+		.pud	= S3C_GPIO_PULL_NONE,
+		.drv	= S5P_GPIO_DRVSTR_LV1,
+	}, {
+		.num	= EXYNOS4_GPK3(2),	/* PS_ALS_SCL_2.8V */
+		.cfg	= S3C_GPIO_INPUT,
+		.val	= S3C_GPIO_SETPIN_NONE,
+		.pud	= S3C_GPIO_PULL_NONE,
+		.drv	= S5P_GPIO_DRVSTR_LV1,
+	}, {
+		.num	= EXYNOS4210_GPJ1(3),	/* GPIO_CAM_MCLK */
+		.cfg	= S3C_GPIO_INPUT,
+		.val	= S3C_GPIO_SETPIN_NONE,
+		.pud	= S3C_GPIO_PULL_DOWN,
+		.drv	= S5P_GPIO_DRVSTR_LV3,
+	}, {
+		.num	= EXYNOS4_GPB(4),	/* GPIO_IRDA_nINT */
+		.cfg	= S3C_GPIO_OUTPUT,
+		.val	= S3C_GPIO_SETPIN_ZERO,
+		.pud	= S3C_GPIO_PULL_NONE,
+		.drv	= S5P_GPIO_DRVSTR_LV2,
+	}, {
+		.num	= EXYNOS4_GPX0(4), /*TA_nCHG*/
+		.cfg	= S3C_GPIO_INPUT,
+		.val	= S3C_GPIO_SETPIN_NONE,
+		.pud	= S3C_GPIO_PULL_UP,
+		.drv	= S5P_GPIO_DRVSTR_LV4,
+	},
+	/* BT UART */
+	{GPIO_BT_RXD, S3C_GPIO_SFN(2), 2, S3C_GPIO_PULL_UP},
+	{GPIO_BT_TXD, S3C_GPIO_SFN(2), 2, S3C_GPIO_PULL_NONE},
+	{GPIO_BT_CTS, S3C_GPIO_SFN(2), 2, S3C_GPIO_PULL_NONE},
+	{GPIO_BT_RTS, S3C_GPIO_SFN(2), 2, S3C_GPIO_PULL_NONE},
+	/* GPS UART */
+	{GPIO_GPS_RXD, S3C_GPIO_SFN(2), 2, S3C_GPIO_PULL_UP},
+	{GPIO_GPS_TXD, S3C_GPIO_SFN(2), 2, S3C_GPIO_PULL_NONE},
+	{GPIO_GPS_CTS, S3C_GPIO_SFN(2), 2, S3C_GPIO_PULL_NONE},
+	{GPIO_GPS_RTS, S3C_GPIO_SFN(2), 2, S3C_GPIO_PULL_NONE},
+	{GPIO_GPS_nRST, S3C_GPIO_OUTPUT, 1, S3C_GPIO_PULL_UP},
+	{GPIO_GPS_PWR_EN, S3C_GPIO_OUTPUT, 0, S3C_GPIO_PULL_NONE},
+
+	/* UART switch: configure as output */
+	{GPIO_UART_SEL, S3C_GPIO_OUTPUT, 2, S3C_GPIO_PULL_NONE},
+
+	/* USB switch: configure as output */
+	{GPIO_USB_SEL1, S3C_GPIO_OUTPUT, 2, S3C_GPIO_PULL_NONE},
+	{GPIO_USB_SEL2, S3C_GPIO_OUTPUT, 2, S3C_GPIO_PULL_NONE},
+	{GPIO_USB_SEL3, S3C_GPIO_OUTPUT, 2, S3C_GPIO_PULL_NONE},
+
+	/* JIG On */
+	{GPIO_IF_CON_SENSE, S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_NONE},
+
+	/* 30PIN CONNECTOR */
+	{GPIO_DOCK_INT, S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_NONE},
+
+	/* MIC */
+	{GPIO_EAR_MIC_BIAS_EN, S3C_GPIO_OUTPUT, 0, S3C_GPIO_PULL_NONE},
+
+	/* TSP */
+	{GPIO_TSP_VENDOR, S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_NONE},
+
+	/*** GPX ***/
+	{GPIO_GYRO_INT, S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_NONE},
+	{GPIO_PS_VOUT_WAKE, S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_NONE},
+	/* REMOTE_SENSE_IRQ */
+	{EXYNOS4_GPX0(2), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_UP},
+	{GPIO_ACCESSORY_INT, S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_NONE},
+	{GPIO_MSENSE_INT, S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_NONE},
+	{GPIO_FUEL_ALERT, S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_NONE},
+	/* {GPIO_BT_HOST_WAKE, S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_NONE}, */
+	{GPIO_DET_35, S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_NONE},
+	{GPIO_USB_OTG_EN, S3C_GPIO_OUTPUT, 0, S3C_GPIO_PULL_NONE},
+	/* T_FLASH_DETECT */
+	{EXYNOS4_GPX3(4), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_NONE},
+	/* TA_nCONNECTED */
+	{EXYNOS4_GPX3(5), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_NONE},
+	{GPIO_HDMI_HPD, S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_NONE},
+
+	/* NC */
+	{EXYNOS4_GPY0(0), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY0(1), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY0(2), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY0(3), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY0(4), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY0(5), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPY1(0), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY1(1), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY1(2), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY1(3), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPY2(0), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY2(1), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY2(2), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY2(3), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY2(4), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY2(5), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPY3(1), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY3(3), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPY6(0), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(2), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(3), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY6(4), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+
+
+	/* for WIFI version */
+#ifndef CONFIG_LINK_DEVICE_HSIC
+	{GPIO_PHONE_ON,		S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{GPIO_SIM_DETECT,	S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{GPIO_IPC_SLAVE_WAKEUP, S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{GPIO_IPC_HOST_WAKEUP,	S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{GPIO_CP_DUMP_INT,	S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{GPIO_SUSPEND_REQUEST,	S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{GPIO_CP_RST,		S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{GPIO_PHONE_ACTIVE,	S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{GPIO_ACTIVE_STATE,	S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{GPIO_PDA_ACTIVE,	S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+	{GPIO_CP_REQ_RESET,	S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},
+#endif
+};
+
+void p8_config_gpio_table(void)
+{
+	u32 i, gpio;
+
+	printk(KERN_DEBUG "%s\n", __func__);
+
+	for (i = 0; i < ARRAY_SIZE(p8_init_gpios); i++) {
+		gpio = p8_init_gpios[i].num;
+		s3c_gpio_cfgpin(gpio, p8_init_gpios[i].cfg);
+		s3c_gpio_setpull(gpio, p8_init_gpios[i].pud);
+
+		if (p8_init_gpios[i].val != S3C_GPIO_SETPIN_NONE)
+			gpio_set_value(gpio, p8_init_gpios[i].val);
+
+		s5p_gpio_set_drvstr(gpio, p8_init_gpios[i].drv);
+	}
+}
+
+/* this table only for c1 board */
+static unsigned int p8_sleep_gpio_table[][3] = {
+	{ EXYNOS4_GPA0(0),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_UP},
+	{ EXYNOS4_GPA0(1),  S3C_GPIO_SLP_OUT1,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4_GPA0(2),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPA0(3),  S3C_GPIO_SLP_OUT1,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4_GPA0(4),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPA0(5),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPA0(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{ EXYNOS4_GPA0(7),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{ EXYNOS4_GPA1(0),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_UP},
+	{ EXYNOS4_GPA1(1),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_UP},
+	{ EXYNOS4_GPA1(2),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4_GPA1(3),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4_GPA1(4),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4_GPA1(5),  S3C_GPIO_SLP_OUT0,	S3C_GPIO_PULL_NONE},
+
+	{ EXYNOS4_GPB(0),   S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPB(1),   S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPB(2),   S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPB(3),   S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPB(4),   S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPB(5),   S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPB(6),   S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4_GPB(7),   S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_NONE},
+
+	{ EXYNOS4_GPC0(0),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4_GPC0(1),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{ EXYNOS4_GPC0(2),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPC0(3),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPC0(4),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+
+	{ EXYNOS4_GPC1(0),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},	/* NC */
+	{ EXYNOS4_GPC1(1),  S3C_GPIO_SLP_OUT0,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4_GPC1(2),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},	/* NC */
+	{ EXYNOS4_GPC1(3),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4_GPC1(4),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_NONE},
+
+	{ EXYNOS4_GPD0(0),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},	/* NC */
+	{ EXYNOS4_GPD0(1),  S3C_GPIO_SLP_OUT0,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4_GPD0(2),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4_GPD0(3),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_NONE},
+
+	{ EXYNOS4_GPD1(0),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4_GPD1(1),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4_GPD1(2),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4_GPD1(3),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_NONE},
+
+	/* NC */
+	{ EXYNOS4210_GPE0(0),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4210_GPE0(1),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	/* NC */
+	{ EXYNOS4210_GPE0(2),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	/* NC */
+	{ EXYNOS4210_GPE0(3),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	/* NC */
+	{ EXYNOS4210_GPE0(4),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+
+	{ EXYNOS4210_GPE1(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},	/* NC */
+	{ EXYNOS4210_GPE1(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},	/* NC */
+	{ EXYNOS4210_GPE1(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},	/* NC */
+	{ EXYNOS4210_GPE1(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},	/* NC */
+	/* NC */
+	{ EXYNOS4210_GPE1(4),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	/* NC */
+	{ EXYNOS4210_GPE1(5),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	/* NC */
+	{ EXYNOS4210_GPE1(6),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	/* NC */
+	{ EXYNOS4210_GPE1(7),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+
+	/* NC */
+	{ EXYNOS4210_GPE2(0),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	/* NC */
+	{ EXYNOS4210_GPE2(1),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	/* NC */
+	{ EXYNOS4210_GPE2(2),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	/* NC */
+	{ EXYNOS4210_GPE2(3),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	/* NC */
+	{ EXYNOS4210_GPE2(4),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	/* NC */
+	{ EXYNOS4210_GPE2(5),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+
+	{ EXYNOS4210_GPE3(0),  S3C_GPIO_SLP_OUT0,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4210_GPE3(1),  S3C_GPIO_SLP_OUT0,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4210_GPE3(2),  S3C_GPIO_SLP_OUT0,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4210_GPE3(3),  S3C_GPIO_SLP_OUT0,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4210_GPE3(4),  S3C_GPIO_SLP_OUT0,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4210_GPE3(5),  S3C_GPIO_SLP_OUT0,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4210_GPE3(6),  S3C_GPIO_SLP_OUT0,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4210_GPE3(7),  S3C_GPIO_SLP_OUT0,	S3C_GPIO_PULL_NONE},
+
+	{ EXYNOS4210_GPE4(0),  S3C_GPIO_SLP_OUT0,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4210_GPE4(1),  S3C_GPIO_SLP_OUT0,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4210_GPE4(2),  S3C_GPIO_SLP_OUT0,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4210_GPE4(3),  S3C_GPIO_SLP_OUT0,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4210_GPE4(4),  S3C_GPIO_SLP_OUT0,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4210_GPE4(5),  S3C_GPIO_SLP_OUT0,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4210_GPE4(6),  S3C_GPIO_SLP_OUT0,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4210_GPE4(7),  S3C_GPIO_SLP_OUT0,	S3C_GPIO_PULL_NONE},
+
+	{ EXYNOS4_GPF0(0),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	/* AMOLED_RESET_1.8V */
+	{ EXYNOS4_GPF0(1),  S3C_GPIO_SLP_OUT0,	S3C_GPIO_PULL_NONE},
+	/* PANEL_CRACK_DET_1.8V */
+	{ EXYNOS4_GPF0(2),  S3C_GPIO_SLP_OUT0,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4_GPF0(3),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPF0(4),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPF0(5),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPF0(6),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPF0(7),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+
+	{ EXYNOS4_GPF1(0),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPF1(1),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPF1(2),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPF1(3),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPF1(4),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPF1(5),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPF1(6),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPF1(7),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+
+	{ EXYNOS4_GPF2(0),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPF2(1),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPF2(2),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPF2(3),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPF2(4),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPF2(5),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPF2(6),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPF2(7),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+
+	{ EXYNOS4_GPF3(0),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPF3(1),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPF3(2),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPF3(3),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPF3(4),  S3C_GPIO_SLP_OUT0,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4_GPF3(5),  S3C_GPIO_SLP_OUT0,	S3C_GPIO_PULL_NONE},
+
+	/* NC */
+	{ EXYNOS4210_GPJ0(0),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	/* NC */
+	{ EXYNOS4210_GPJ0(1),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	/* NC */
+	{ EXYNOS4210_GPJ0(2),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	/* NC */
+	{ EXYNOS4210_GPJ0(3),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	/* NC */
+	{ EXYNOS4210_GPJ0(4),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	/* NC */
+	{ EXYNOS4210_GPJ0(5),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	/* NC */
+	{ EXYNOS4210_GPJ0(6),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	/* NC */
+	{ EXYNOS4210_GPJ0(7),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+
+	/* NC */
+	{ EXYNOS4210_GPJ1(0),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	/* NC */
+	{ EXYNOS4210_GPJ1(1),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	/* NC */
+	{ EXYNOS4210_GPJ1(2),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4210_GPJ1(3),  S3C_GPIO_SLP_OUT0,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4210_GPJ1(4),  S3C_GPIO_SLP_OUT0,	S3C_GPIO_PULL_NONE},
+
+	{ EXYNOS4_GPK0(0),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPK0(1),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPK0(2),  S3C_GPIO_SLP_OUT0,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4_GPK0(3),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPK0(4),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPK0(5),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPK0(6),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+
+	{ EXYNOS4_GPK1(0),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPK1(1),  S3C_GPIO_SLP_OUT0,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4_GPK1(2),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPK1(3),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPK1(4),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPK1(5),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPK1(6),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+
+	{ EXYNOS4_GPK2(0),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPK2(1),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPK2(2),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4_GPK2(3),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPK2(4),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPK2(5),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPK2(6),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+
+	{ EXYNOS4_GPK3(0),  S3C_GPIO_SLP_OUT0,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4_GPK3(1),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_UP},
+	{ EXYNOS4_GPK3(2),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4_GPK3(3),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_UP},
+	{ EXYNOS4_GPK3(4),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_UP},
+	{ EXYNOS4_GPK3(5),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_UP},
+	{ EXYNOS4_GPK3(6),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_UP},
+
+	{ EXYNOS4_GPL0(0),  S3C_GPIO_SLP_PREV,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4_GPL0(1),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{ EXYNOS4_GPL0(2),  S3C_GPIO_SLP_OUT0,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4_GPL0(3),  S3C_GPIO_SLP_OUT0,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4_GPL0(4),  S3C_GPIO_SLP_PREV,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4_GPL0(5),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	/* WLAN_EN2 */
+	{ EXYNOS4_GPL0(6),  S3C_GPIO_SLP_PREV,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4_GPL0(7),  S3C_GPIO_SLP_OUT0,	S3C_GPIO_PULL_NONE},
+
+	{ EXYNOS4_GPL1(0),  S3C_GPIO_SLP_PREV,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4_GPL1(1),  S3C_GPIO_SLP_OUT0,	S3C_GPIO_PULL_NONE},
+	/* WLAN_EN */
+	{ EXYNOS4_GPL1(2),  S3C_GPIO_SLP_OUT1,	S3C_GPIO_PULL_NONE},
+
+	{ EXYNOS4_GPL2(0),  S3C_GPIO_SLP_OUT0,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4_GPL2(1),  S3C_GPIO_SLP_OUT0,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4_GPL2(2),  S3C_GPIO_SLP_OUT0,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4_GPL2(3),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4_GPL2(4),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN}, /* NC */
+	{ EXYNOS4_GPL2(5),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN}, /* NC */
+	{ EXYNOS4_GPL2(6),  S3C_GPIO_SLP_PREV,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4_GPL2(7),  S3C_GPIO_SLP_OUT0,	S3C_GPIO_PULL_NONE},
+
+	{ EXYNOS4_GPX0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, /* TA_nCHG */
+
+	{ EXYNOS4_GPY0(0),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN}, /* NC */
+	{ EXYNOS4_GPY0(1),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN}, /* NC */
+	{ EXYNOS4_GPY0(2),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN}, /* NC */
+	{ EXYNOS4_GPY0(3),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN}, /* NC */
+	{ EXYNOS4_GPY0(4),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN}, /* NC */
+	{ EXYNOS4_GPY0(5),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{ EXYNOS4_GPY1(0),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN}, /* NC */
+	{ EXYNOS4_GPY1(1),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN}, /* NC */
+	{ EXYNOS4_GPY1(2),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN}, /* NC */
+	{ EXYNOS4_GPY1(3),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{ EXYNOS4_GPY2(0),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN}, /* NC */
+	{ EXYNOS4_GPY2(1),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN}, /* NC */
+	{ EXYNOS4_GPY2(2),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN}, /* NC */
+	{ EXYNOS4_GPY2(3),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN}, /* NC */
+	{ EXYNOS4_GPY2(4),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN}, /* NC */
+	{ EXYNOS4_GPY2(5),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN}, /* NC */
+
+	/* MHL_SDA_1.8V */
+	{ EXYNOS4_GPY3(0),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4_GPY3(1),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN}, /* NC */
+	/* MHL_SCL_1.8V */
+	{ EXYNOS4_GPY3(2),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4_GPY3(3),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN}, /* NC */
+	{ EXYNOS4_GPY3(4),  S3C_GPIO_SLP_PREV,	S3C_GPIO_PULL_NONE},
+#ifndef CONFIG_LINK_DEVICE_HSIC
+	{ EXYNOS4_GPY3(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+#else
+	/* GPIO_ACTIVE_STATE, EHCI on/off state to CP */
+	{ EXYNOS4_GPY3(5),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+#endif
+	{ EXYNOS4_GPY3(6),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	/* USB_SEL2 */
+	{ EXYNOS4_GPY3(7),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+
+	{ EXYNOS4_GPY4(0),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4_GPY4(1),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_NONE},
+#ifndef CONFIG_LINK_DEVICE_HSIC
+	{ EXYNOS4_GPY4(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+#else
+	/* GPIO_PDA_ACTIVE, AP Sleep, LPA state to CP */
+	{ EXYNOS4_GPY4(2),  S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+#endif
+	{ EXYNOS4_GPY4(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	/* V_ACCESSORY_5V CHECK */
+	{ EXYNOS4_GPY4(4),  S3C_GPIO_SLP_PREV,	S3C_GPIO_PULL_NONE},
+	/* USB_SEL3 */
+	{ EXYNOS4_GPY4(5),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+#ifndef CONFIG_LINK_DEVICE_HSIC
+	{ EXYNOS4_GPY4(6),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+#else
+	/* GPIO_CP_REQ_RESET */
+	{ EXYNOS4_GPY4(6),  S3C_GPIO_SLP_OUT1,	S3C_GPIO_PULL_NONE},
+#endif
+	/* GPIO_UART_SEL */
+	{ EXYNOS4_GPY4(7),  S3C_GPIO_SLP_PREV,	S3C_GPIO_PULL_NONE},
+
+	/* HW_REV0 */
+	{ EXYNOS4_GPY5(0),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_NONE},
+	/* HW_REV1 */
+	{ EXYNOS4_GPY5(1),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_NONE},
+	/* HW_REV2 */
+	{ EXYNOS4_GPY5(2),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_NONE},
+	/* HW_REV3 */
+	{ EXYNOS4_GPY5(3),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4_GPY5(4),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_DOWN},
+	{ EXYNOS4_GPY5(5),  S3C_GPIO_SLP_PREV,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4_GPY5(6),  S3C_GPIO_SLP_INPUT,	S3C_GPIO_PULL_NONE},
+	{ EXYNOS4_GPY5(7),  S3C_GPIO_SLP_OUT0,	S3C_GPIO_PULL_NONE},
+
+	{ EXYNOS4_GPY6(0),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	/* ACCESSORY_EN */
+	{ EXYNOS4_GPY6(1),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{ EXYNOS4_GPY6(2),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{ EXYNOS4_GPY6(3),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{ EXYNOS4_GPY6(4),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{ EXYNOS4_GPY6(5),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{ EXYNOS4_GPY6(6),  S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE}, /* TA_EN */
+	{ EXYNOS4_GPY6(7),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+
+	{ EXYNOS4_GPZ(0),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{ EXYNOS4_GPZ(1),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},	/* NC */
+	{ EXYNOS4_GPZ(2),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{ EXYNOS4_GPZ(3),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{ EXYNOS4_GPZ(4),  S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{ EXYNOS4_GPZ(5),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},	/* NC */
+	{ EXYNOS4_GPZ(6),  S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},	/* NC */
+};
+
+static void config_sleep_gpio_table(int array_size,
+				    unsigned int (*gpio_table)[3])
+{
+	u32 i, gpio;
+
+	for (i = 0; i < array_size; i++) {
+		gpio = gpio_table[i][0];
+		s3c_gpio_slp_cfgpin(gpio, gpio_table[i][1]);
+		s3c_gpio_slp_setpull_updown(gpio, gpio_table[i][2]);
+	}
+}
+
+void p8_config_sleep_gpio_table(void)
+{
+	config_sleep_gpio_table(ARRAY_SIZE(p8_sleep_gpio_table),
+			p8_sleep_gpio_table);
+}
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
new file mode 100644
index 0000000..88b791a
--- /dev/null
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -0,0 +1,285 @@
+/* linux/arch/arm/mach-exynos/platsmp.c
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
+ *
+ *  Copyright (C) 2002 ARM Ltd.
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/jiffies.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+
+#include <asm/cacheflush.h>
+#include <asm/hardware/gic.h>
+#include <asm/smp_scu.h>
+#include <asm/unified.h>
+
+#include <mach/hardware.h>
+#include <mach/regs-clock.h>
+#include <mach/regs-pmu.h>
+#include <mach/smc.h>
+
+#include <plat/cpu.h>
+#include <plat/exynos4.h>
+#ifdef CONFIG_SEC_WATCHDOG_RESET
+#include <plat/regs-watchdog.h>
+#endif
+
+extern void exynos_secondary_startup(void);
+extern unsigned int gic_bank_offset;
+
+struct _cpu_boot_info {
+	void __iomem *power_base;
+	void __iomem *boot_base;
+};
+
+struct _cpu_boot_info cpu_boot_info[NR_CPUS];
+
+/*
+ * control for which core is the next to come out of the secondary
+ * boot "holding pen"
+ */
+volatile int pen_release = -1;
+
+/*
+ * Write pen_release in a way that is guaranteed to be visible to all
+ * observers, irrespective of whether they're taking part in coherency
+ * or not.  This is necessary for the hotplug code to work reliably.
+ */
+static void write_pen_release(int val)
+{
+	pen_release = val;
+	smp_wmb();
+	__cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
+	outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
+}
+
+static void __iomem *scu_base_addr(void)
+{
+	if (soc_is_exynos5210() || soc_is_exynos5250())
+		return 0;
+
+	return (void __iomem *)(S5P_VA_SCU);
+}
+
+static DEFINE_SPINLOCK(boot_lock);
+
+void __cpuinit platform_secondary_init(unsigned int cpu)
+{
+	void __iomem *dist_base = S5P_VA_GIC_DIST +
+				 (gic_bank_offset * cpu);
+	void __iomem *cpu_base = S5P_VA_GIC_CPU +
+				(gic_bank_offset * cpu);
+
+	/* Enable the full line of zero */
+	if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412())
+		enable_cache_foz();
+
+	/*
+	 * if any interrupts are already enabled for the primary
+	 * core (e.g. timer irq), then they will not have been enabled
+	 * for us: do so
+	 */
+	gic_secondary_init_base(0, dist_base, cpu_base);
+
+	/*
+	 * let the primary processor know we're out of the
+	 * pen, then head off into the C entry point
+	 */
+	write_pen_release(-1);
+
+	/*
+	 * Synchronise with the boot thread.
+	 */
+	spin_lock(&boot_lock);
+	spin_unlock(&boot_lock);
+}
+
+static int exynos_power_up_cpu(unsigned int cpu)
+{
+	unsigned int timeout;
+	unsigned int val;
+	void __iomem *power_base = cpu_boot_info[cpu].power_base;
+
+	val = __raw_readl(power_base);
+	if (!(val & S5P_CORE_LOCAL_PWR_EN)) {
+		__raw_writel(S5P_CORE_LOCAL_PWR_EN, power_base);
+
+		/* wait max 10 ms until cpu is on */
+		timeout = 10;
+		while (timeout) {
+			val = __raw_readl(power_base + 0x4);
+
+			if ((val & S5P_CORE_LOCAL_PWR_EN) == S5P_CORE_LOCAL_PWR_EN)
+				break;
+
+			mdelay(1);
+			timeout--;
+		}
+
+		if (timeout == 0) {
+			printk(KERN_ERR "cpu%d power up failed", cpu);
+			return -ETIMEDOUT;
+		}
+	}
+
+	return 0;
+}
+
+int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+	unsigned long timeout;
+	int ret;
+#ifdef CONFIG_SEC_WATCHDOG_RESET
+	unsigned int tmp_wtcon;
+#endif
+
+	/*
+	 * Set synchronisation state between this boot processor
+	 * and the secondary one
+	 */
+	spin_lock(&boot_lock);
+
+#ifdef CONFIG_SEC_WATCHDOG_RESET
+	tmp_wtcon = __raw_readl(S3C2410_WTCON);
+#endif
+
+	ret = exynos_power_up_cpu(cpu);
+	if (ret) {
+		spin_unlock(&boot_lock);
+		return ret;
+	}
+
+	/*
+	 * The secondary processor is waiting to be released from
+	 * the holding pen - release it, then wait for it to flag
+	 * that it has been released by resetting pen_release.
+	 *
+	 * Note that "pen_release" is the hardware CPU ID, whereas
+	 * "cpu" is Linux's internal ID.
+	 */
+	write_pen_release(cpu);
+
+	/*
+	 * Send the secondary CPU a soft interrupt, thereby causing
+	 * the boot monitor to read the system wide flags register,
+	 * and branch to the address found there.
+	 */
+	timeout = jiffies + (1 * HZ);
+	while (time_before(jiffies, timeout)) {
+		smp_rmb();
+
+		__raw_writel(BSYM(virt_to_phys(exynos_secondary_startup)),
+			cpu_boot_info[cpu].boot_base);
+
+#ifdef CONFIG_ARM_TRUSTZONE
+		if (soc_is_exynos4412())
+			exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
+		else
+			exynos_smc(SMC_CMD_CPU1BOOT, 0, 0, 0);
+#endif
+		smp_send_reschedule(cpu);
+
+		if (pen_release == -1)
+			break;
+
+		udelay(10);
+	}
+
+#ifdef CONFIG_SEC_WATCHDOG_RESET
+	__raw_writel(tmp_wtcon, S3C2410_WTCON);
+#endif
+
+	/*
+	 * now the secondary core is starting up let it run its
+	 * calibrations, then wait for it to finish
+	 */
+	spin_unlock(&boot_lock);
+
+	return pen_release != -1 ? -ENOSYS : 0;
+}
+
+static inline unsigned long exynos5_get_core_count(void)
+{
+	u32 val;
+
+	/* Read L2 control register */
+	asm volatile("mrc p15, 1, %0, c9, c0, 2" : "=r"(val));
+
+	/* core count : [25:24] of L2 control register + 1 */
+	val = ((val >> 24) & 3) + 1;
+
+	return val;
+}
+
+/*
+ * Initialise the CPU possible map early - this describes the CPUs
+ * which may be present or become present in the system.
+ */
+void __init smp_init_cpus(void)
+{
+	unsigned int i, ncores;
+
+	void __iomem *scu_base = scu_base_addr();
+
+	ncores = scu_base ? scu_get_core_count(scu_base) :
+			    exynos5_get_core_count();
+
+	/* sanity check */
+	if (ncores > NR_CPUS) {
+		printk(KERN_WARNING
+		       "EXYNOS: no. of cores (%d) greater than configured "
+		       "maximum of %d - clipping\n",
+		       ncores, NR_CPUS);
+		ncores = NR_CPUS;
+	}
+
+	for (i = 0; i < ncores; i++)
+		set_cpu_possible(i, true);
+
+	set_smp_cross_call(gic_raise_softirq);
+}
+
+void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+{
+	int i;
+
+	/*
+	 * Initialise the present map, which describes the set of CPUs
+	 * actually populated at the present time.
+	 */
+	for (i = 0; i < max_cpus; i++)
+		set_cpu_present(i, true);
+
+	if (scu_base_addr())
+		scu_enable(scu_base_addr());
+	else
+		flush_cache_all();
+
+	/* Set up secondary boot base and core power cofiguration base address */
+	for (i = 1; i < max_cpus; i++) {
+#ifdef CONFIG_ARM_TRUSTZONE
+		cpu_boot_info[i].boot_base = S5P_VA_SYSRAM_NS + 0x1C;
+#else
+		if (soc_is_exynos4210() && (samsung_rev() >= EXYNOS4210_REV_1_1))
+			cpu_boot_info[i].boot_base = S5P_INFORM5;
+		else
+			cpu_boot_info[i].boot_base = S5P_VA_SYSRAM;
+#endif
+		if (soc_is_exynos4412())
+			cpu_boot_info[i].boot_base += (0x4 * i);
+		cpu_boot_info[i].power_base = S5P_ARM_CORE_CONFIGURATION(i);
+	}
+}
diff --git a/arch/arm/mach-exynos/pm-exynos4.c b/arch/arm/mach-exynos/pm-exynos4.c
new file mode 100644
index 0000000..e24e519
--- /dev/null
+++ b/arch/arm/mach-exynos/pm-exynos4.c
@@ -0,0 +1,613 @@
+/* linux/arch/arm/mach-exynos/pm-exynos4.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS4210 - Power Management support
+ *
+ * Based on arch/arm/mach-s3c2410/pm.c
+ * Copyright (c) 2006 Simtec Electronics
+ *	Ben Dooks <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/suspend.h>
+#include <linux/syscore_ops.h>
+#include <linux/io.h>
+#include <linux/regulator/machine.h>
+
+#if defined(CONFIG_MACH_M0_CTC)
+#include <linux/mfd/max77693.h>
+#endif
+
+#include <asm/cacheflush.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/cputype.h>
+#include <asm/smp_scu.h>
+
+#include <plat/cpu.h>
+#include <plat/pm.h>
+#include <plat/regs-srom.h>
+
+#include <mach/regs-irq.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-clock.h>
+#include <mach/regs-pmu.h>
+#include <mach/pm-core.h>
+#include <mach/pmu.h>
+#include <mach/smc.h>
+#include <mach/gpio.h>
+
+void (*exynos4_sleep_gpio_table_set)(void);
+
+#ifdef CONFIG_ARM_TRUSTZONE
+#define REG_INFORM0	       (S5P_VA_SYSRAM_NS + 0x8)
+#define REG_INFORM1	       (S5P_VA_SYSRAM_NS + 0xC)
+#else
+#define REG_INFORM0	       (S5P_INFORM0)
+#define REG_INFORM1	       (S5P_INFORM1)
+#endif
+
+static struct sleep_save exynos4_set_clksrc[] = {
+	{ .reg = EXYNOS4_CLKSRC_MASK_TOP			, .val = 0x00000001, },
+	{ .reg = EXYNOS4_CLKSRC_MASK_CAM			, .val = 0x11111111, },
+	{ .reg = EXYNOS4_CLKSRC_MASK_TV				, .val = 0x00000111, },
+	{ .reg = EXYNOS4_CLKSRC_MASK_LCD0			, .val = 0x00001111, },
+	{ .reg = EXYNOS4_CLKSRC_MASK_MAUDIO			, .val = 0x00000001, },
+	{ .reg = EXYNOS4_CLKSRC_MASK_FSYS			, .val = 0x01011111, },
+	{ .reg = EXYNOS4_CLKSRC_MASK_PERIL0			, .val = 0x01111111, },
+	{ .reg = EXYNOS4_CLKSRC_MASK_PERIL1			, .val = 0x01110111, },
+	{ .reg = EXYNOS4_CLKSRC_MASK_DMC			, .val = 0x00010000, },
+};
+
+static struct sleep_save exynos4210_set_clksrc[] = {
+	{ .reg = EXYNOS4_CLKSRC_MASK_LCD1			, .val = 0x00001111, },
+};
+
+static struct sleep_save exynos4_core_save[] = {
+	/* GIC side */
+	SAVE_ITEM(S5P_VA_GIC_CPU + 0x000),
+	SAVE_ITEM(S5P_VA_GIC_CPU + 0x004),
+	SAVE_ITEM(S5P_VA_GIC_CPU + 0x008),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x000),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x004),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x100),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x104),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x108),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x300),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x304),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x308),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x400),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x404),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x408),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x40C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x410),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x414),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x418),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x41C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x420),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x424),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x428),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x42C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x430),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x434),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x438),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x43C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x440),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x444),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x448),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x44C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x450),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x454),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x458),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x45C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x460),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x464),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x468),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x46C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x470),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x474),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x478),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x47C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x480),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x484),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x488),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x48C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x490),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x494),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x498),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x49C),
+
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x800),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x804),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x808),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x80C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x810),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x814),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x818),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x81C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x820),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x824),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x828),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x82C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x830),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x834),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x838),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x83C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x840),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x844),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x848),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x84C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x850),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x854),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x858),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x85C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x860),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x864),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x868),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x86C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x870),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x874),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x878),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x87C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x880),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x884),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x888),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x88C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x890),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x894),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x898),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x89C),
+
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0xC00),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0xC04),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0xC08),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0xC0C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0xC10),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0xC14),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0xC18),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0xC1C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0xC20),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0xC24),
+
+	SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x000),
+	SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x010),
+	SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x020),
+	SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x030),
+	SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x040),
+	SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x050),
+	SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x060),
+	SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x070),
+	SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x080),
+	SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x090),
+};
+
+static struct sleep_save exynos4_regs_save[] = {
+	/* Common GPIO Part1 */
+	SAVE_ITEM(S5P_VA_GPIO + 0x700),
+	SAVE_ITEM(S5P_VA_GPIO + 0x704),
+	SAVE_ITEM(S5P_VA_GPIO + 0x708),
+	SAVE_ITEM(S5P_VA_GPIO + 0x70C),
+	SAVE_ITEM(S5P_VA_GPIO + 0x710),
+	SAVE_ITEM(S5P_VA_GPIO + 0x714),
+	SAVE_ITEM(S5P_VA_GPIO + 0x718),
+	SAVE_ITEM(S5P_VA_GPIO + 0x730),
+	SAVE_ITEM(S5P_VA_GPIO + 0x734),
+	SAVE_ITEM(S5P_VA_GPIO + 0x738),
+	SAVE_ITEM(S5P_VA_GPIO + 0x73C),
+	SAVE_ITEM(S5P_VA_GPIO + 0x900),
+	SAVE_ITEM(S5P_VA_GPIO + 0x904),
+	SAVE_ITEM(S5P_VA_GPIO + 0x908),
+	SAVE_ITEM(S5P_VA_GPIO + 0x90C),
+	SAVE_ITEM(S5P_VA_GPIO + 0x910),
+	SAVE_ITEM(S5P_VA_GPIO + 0x914),
+	SAVE_ITEM(S5P_VA_GPIO + 0x918),
+	SAVE_ITEM(S5P_VA_GPIO + 0x930),
+	SAVE_ITEM(S5P_VA_GPIO + 0x934),
+	SAVE_ITEM(S5P_VA_GPIO + 0x938),
+	SAVE_ITEM(S5P_VA_GPIO + 0x93C),
+	/* Common GPIO Part2 */
+	SAVE_ITEM(S5P_VA_GPIO2 + 0x708),
+	SAVE_ITEM(S5P_VA_GPIO2 + 0x70C),
+	SAVE_ITEM(S5P_VA_GPIO2 + 0x710),
+	SAVE_ITEM(S5P_VA_GPIO2 + 0x714),
+	SAVE_ITEM(S5P_VA_GPIO2 + 0x718),
+	SAVE_ITEM(S5P_VA_GPIO2 + 0x71C),
+	SAVE_ITEM(S5P_VA_GPIO2 + 0x720),
+	SAVE_ITEM(S5P_VA_GPIO2 + 0x908),
+	SAVE_ITEM(S5P_VA_GPIO2 + 0x90C),
+	SAVE_ITEM(S5P_VA_GPIO2 + 0x910),
+	SAVE_ITEM(S5P_VA_GPIO2 + 0x914),
+	SAVE_ITEM(S5P_VA_GPIO2 + 0x918),
+	SAVE_ITEM(S5P_VA_GPIO2 + 0x91C),
+	SAVE_ITEM(S5P_VA_GPIO2 + 0x920),
+};
+
+static struct sleep_save exynos4210_regs_save[] = {
+	/* SROM side */
+	SAVE_ITEM(S5P_SROM_BW),
+	SAVE_ITEM(S5P_SROM_BC0),
+	SAVE_ITEM(S5P_SROM_BC1),
+	SAVE_ITEM(S5P_SROM_BC2),
+	SAVE_ITEM(S5P_SROM_BC3),
+	/* GPIO Part1 */
+	SAVE_ITEM(S5P_VA_GPIO + 0x71C),
+	SAVE_ITEM(S5P_VA_GPIO + 0x720),
+	SAVE_ITEM(S5P_VA_GPIO + 0x724),
+	SAVE_ITEM(S5P_VA_GPIO + 0x728),
+	SAVE_ITEM(S5P_VA_GPIO + 0x72C),
+	SAVE_ITEM(S5P_VA_GPIO + 0x91C),
+	SAVE_ITEM(S5P_VA_GPIO + 0x920),
+	SAVE_ITEM(S5P_VA_GPIO + 0x924),
+	SAVE_ITEM(S5P_VA_GPIO + 0x928),
+	SAVE_ITEM(S5P_VA_GPIO + 0x92C),
+	/* GPIO Part2 */
+	SAVE_ITEM(S5P_VA_GPIO2 + 0x700),
+	SAVE_ITEM(S5P_VA_GPIO2 + 0x704),
+	SAVE_ITEM(S5P_VA_GPIO2 + 0x900),
+	SAVE_ITEM(S5P_VA_GPIO2 + 0x904),
+};
+
+
+static struct sleep_save exynos4x12_regs_save[] = {
+	/* SROM side */
+	SAVE_ITEM(S5P_SROM_BW),
+	SAVE_ITEM(S5P_SROM_BC0),
+	SAVE_ITEM(S5P_SROM_BC1),
+	SAVE_ITEM(S5P_SROM_BC2),
+	SAVE_ITEM(S5P_SROM_BC3),
+	/* GPIO Part1 */
+	SAVE_ITEM(S5P_VA_GPIO + 0x740),
+	SAVE_ITEM(S5P_VA_GPIO + 0x744),
+	SAVE_ITEM(S5P_VA_GPIO + 0x940),
+	SAVE_ITEM(S5P_VA_GPIO + 0x944),
+	/* GPIO Part2 */
+	SAVE_ITEM(S5P_VA_GPIO2 + 0x724),
+	SAVE_ITEM(S5P_VA_GPIO2 + 0x728),
+	SAVE_ITEM(S5P_VA_GPIO2 + 0x72C),
+	SAVE_ITEM(S5P_VA_GPIO2 + 0x730),
+	SAVE_ITEM(S5P_VA_GPIO2 + 0x734),
+	SAVE_ITEM(S5P_VA_GPIO2 + 0x924),
+	SAVE_ITEM(S5P_VA_GPIO2 + 0x928),
+	SAVE_ITEM(S5P_VA_GPIO2 + 0x92C),
+	SAVE_ITEM(S5P_VA_GPIO2 + 0x930),
+	SAVE_ITEM(S5P_VA_GPIO2 + 0x934),
+	/* GPIO Part3 */
+	SAVE_ITEM(S5P_VA_GPIO3 + 0x700),
+	SAVE_ITEM(S5P_VA_GPIO3 + 0x900),
+	/* GPIO Part4 */
+	SAVE_ITEM(S5P_VA_GPIO4 + 0x700),
+	SAVE_ITEM(S5P_VA_GPIO4 + 0x704),
+	SAVE_ITEM(S5P_VA_GPIO4 + 0x708),
+	SAVE_ITEM(S5P_VA_GPIO4 + 0x70C),
+	SAVE_ITEM(S5P_VA_GPIO4 + 0x710),
+	SAVE_ITEM(S5P_VA_GPIO4 + 0x900),
+	SAVE_ITEM(S5P_VA_GPIO4 + 0x904),
+	SAVE_ITEM(S5P_VA_GPIO4 + 0x908),
+	SAVE_ITEM(S5P_VA_GPIO4 + 0x90C),
+	SAVE_ITEM(S5P_VA_GPIO4 + 0x910),
+};
+
+#if defined(CONFIG_CACHE_L2X0)
+static struct sleep_save exynos4_l2cc_save[] = {
+	SAVE_ITEM(S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL),
+	SAVE_ITEM(S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL),
+	SAVE_ITEM(S5P_VA_L2CC + L2X0_PREFETCH_CTRL),
+	SAVE_ITEM(S5P_VA_L2CC + L2X0_POWER_CTRL),
+	SAVE_ITEM(S5P_VA_L2CC + L2X0_AUX_CTRL),
+};
+#endif
+
+void exynos4_cpu_suspend(void)
+{
+	unsigned int tmp;
+
+	if (soc_is_exynos4210()) {
+		/* eMMC power off delay (hidden register)
+		 * 0x10020988 => 0: 300msec, 1: 6msec
+		 */
+		__raw_writel(1, S5P_PMUREG(0x0988));
+	}
+
+	if ((!soc_is_exynos4210()) && (exynos4_is_c2c_use())) {
+		/* Gating CLK_IEM_APC & Enable CLK_SSS */
+		tmp = __raw_readl(EXYNOS4_CLKGATE_IP_DMC);
+		tmp &= ~(0x1 << 17);
+		tmp |= (0x1 << 4);
+		__raw_writel(tmp, EXYNOS4_CLKGATE_IP_DMC);
+
+		/* Set MAX divider for PWI */
+		tmp = __raw_readl(EXYNOS4_CLKDIV_DMC1);
+		tmp |= (0xF << 8);
+		__raw_writel(tmp, EXYNOS4_CLKDIV_DMC1);
+
+		/* Set clock source for PWI */
+		tmp = __raw_readl(EXYNOS4_CLKSRC_DMC);
+		tmp &= ~EXYNOS4_CLKSRC_DMC_MASK;
+		tmp |= ((0x6 << 16)|(0x1 << 12));
+		__raw_writel(tmp, EXYNOS4_CLKSRC_DMC);
+	}
+
+	outer_flush_all();
+
+	/* Disable the full line of zero */
+	disable_cache_foz();
+#ifdef CONFIG_ARM_TRUSTZONE
+	exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
+#else
+	/* issue the standby signal into the pm unit. */
+	cpu_do_idle();
+#endif
+}
+
+static int exynos4_pm_prepare(void)
+{
+	int ret = 0;
+
+#if defined(CONFIG_REGULATOR)
+	ret = regulator_suspend_prepare(PM_SUSPEND_MEM);
+#endif
+
+	return ret;
+}
+
+static void __maybe_unused exynos4_pm_finish(void)
+{
+#if defined(CONFIG_REGULATOR)
+	regulator_suspend_finish();
+#endif
+}
+
+static void exynos4_cpu_prepare(void)
+{
+	if (exynos4_sleep_gpio_table_set)
+		exynos4_sleep_gpio_table_set();
+
+	/* Set value of power down register for sleep mode */
+
+	exynos4_sys_powerdown_conf(SYS_SLEEP);
+	__raw_writel(S5P_CHECK_SLEEP, REG_INFORM1);
+
+	/* ensure at least INFORM0 has the resume address */
+
+	__raw_writel(virt_to_phys(s3c_cpu_resume), REG_INFORM0);
+
+	/* Before enter central sequence mode, clock src register have to set */
+
+	s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc));
+
+	if (soc_is_exynos4210())
+		s3c_pm_do_restore_core(exynos4210_set_clksrc, ARRAY_SIZE(exynos4210_set_clksrc));
+}
+
+static int exynos4_pm_add(struct sys_device *sysdev)
+{
+	pm_cpu_prep = exynos4_cpu_prepare;
+	pm_cpu_sleep = exynos4_cpu_suspend;
+
+	pm_prepare = exynos4_pm_prepare;
+#ifdef CONFIG_SLP
+	pm_finish = exynos4_pm_finish;
+#endif
+
+	return 0;
+}
+
+static struct sysdev_driver exynos4_pm_driver = {
+	.add		= exynos4_pm_add,
+};
+
+static __init int exynos4_pm_drvinit(void)
+{
+	unsigned int tmp;
+
+	s3c_pm_init();
+
+	/* All wakeup disable */
+
+	tmp = __raw_readl(S5P_WAKEUP_MASK);
+	tmp |= ((0xFF << 8) | (0x1F << 1));
+	__raw_writel(tmp, S5P_WAKEUP_MASK);
+
+	/* Disable XXTI pad in system level normal mode */
+	__raw_writel(0x0, S5P_XXTI_CONFIGURATION);
+
+	return sysdev_driver_register(&exynos4_sysclass, &exynos4_pm_driver);
+}
+arch_initcall(exynos4_pm_drvinit);
+
+static int exynos4_pm_suspend(void)
+{
+	unsigned long tmp;
+
+	if (!exynos4_is_c2c_use())
+		s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
+
+	s3c_pm_do_save(exynos4_regs_save, ARRAY_SIZE(exynos4_regs_save));
+	if (soc_is_exynos4210())
+		s3c_pm_do_save(exynos4210_regs_save,
+					ARRAY_SIZE(exynos4210_regs_save));
+	else
+		s3c_pm_do_save(exynos4x12_regs_save,
+					ARRAY_SIZE(exynos4x12_regs_save));
+
+	s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
+
+	/* Setting Central Sequence Register for power down mode */
+
+	tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+	tmp &= ~(S5P_CENTRAL_LOWPWR_CFG);
+	__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+
+	/* When enter sleep mode, USE_DELAYED_RESET_ASSERTION have to disable */
+	if (!soc_is_exynos4210())
+		exynos4_reset_assert_ctrl(0);
+
+	if (!soc_is_exynos4210()) {
+		tmp = S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0;
+		__raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
+
+		if (exynos4_is_c2c_use()) {
+			tmp = __raw_readl(S5P_WAKEUP_MASK_COREBLK);
+			tmp &= ~(1 << 20);
+			__raw_writel(tmp, S5P_WAKEUP_MASK_COREBLK);
+			tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION_COREBLK);
+			tmp &= ~S5P_CENTRAL_SEQ_COREBLK_CONF;
+			__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION_COREBLK);
+		}
+	}
+
+	return 0;
+}
+
+#if !defined(CONFIG_CPU_EXYNOS4210)
+#define CHECK_POINT printk(KERN_DEBUG "%s:%d\n", __func__, __LINE__)
+#else
+#define CHECK_POINT
+#endif
+
+static void exynos4_pm_resume(void)
+{
+	unsigned long tmp;
+
+	/* If PMU failed while entering sleep mode, WFI will be
+	 * ignored by PMU and then exiting cpu_do_idle().
+	 * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
+	 * in this situation.
+	 */
+	tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+	if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
+		tmp |= S5P_CENTRAL_LOWPWR_CFG;
+		__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+		/* No need to perform below restore code */
+		pr_info("%s: early_wakeup\n", __func__);
+		goto early_wakeup;
+	}
+
+	/* For release retention */
+
+	__raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
+	__raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
+	__raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
+	__raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
+	__raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
+	__raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
+	__raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
+
+	s3c_pm_do_restore(exynos4_regs_save, ARRAY_SIZE(exynos4_regs_save));
+	if (soc_is_exynos4210())
+		s3c_pm_do_restore(exynos4210_regs_save,
+					ARRAY_SIZE(exynos4210_regs_save));
+	else
+		s3c_pm_do_restore(exynos4x12_regs_save,
+					ARRAY_SIZE(exynos4x12_regs_save));
+
+#if defined(CONFIG_MACH_M0_CTC)
+{
+	if (max7693_muic_cp_usb_state()) {
+		if (system_rev < 11) {
+			gpio_direction_output(GPIO_USB_BOOT_EN, 1);
+		} else if (system_rev == 11) {
+			gpio_direction_output(GPIO_USB_BOOT_EN, 1);
+			gpio_direction_output(GPIO_USB_BOOT_EN_REV06, 1);
+		} else {
+			gpio_direction_output(GPIO_USB_BOOT_EN_REV06, 1);
+		}
+	}
+}
+#endif
+
+	CHECK_POINT;
+
+	if (!exynos4_is_c2c_use())
+		s3c_pm_do_restore_core(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
+	else {
+		if (!soc_is_exynos4210()) {
+			/* Gating CLK_SSS */
+			tmp = __raw_readl(EXYNOS4_CLKGATE_IP_DMC);
+			tmp &= ~(0x1 << 4);
+			__raw_writel(tmp, EXYNOS4_CLKGATE_IP_DMC);
+		}
+	}
+
+	/* For the suspend-again to check the value */
+	s3c_suspend_wakeup_stat = __raw_readl(S5P_WAKEUP_STAT);
+
+	CHECK_POINT;
+
+	if ((__raw_readl(S5P_WAKEUP_STAT) == 0) && soc_is_exynos4412()) {
+		__raw_writel(0, S5P_EINT_PEND(0));
+		__raw_writel(0, S5P_EINT_PEND(1));
+		__raw_writel(0, S5P_EINT_PEND(2));
+		__raw_writel(0, S5P_EINT_PEND(3));
+		__raw_writel(0x01010001, S5P_ARM_CORE_OPTION(0));
+		__raw_writel(0x00000001, S5P_ARM_CORE_OPTION(1));
+		__raw_writel(0x00000001, S5P_ARM_CORE_OPTION(2));
+		__raw_writel(0x00000001, S5P_ARM_CORE_OPTION(3));
+	}
+
+	scu_enable(S5P_VA_SCU);
+
+	CHECK_POINT;
+
+#ifdef CONFIG_CACHE_L2X0
+#ifdef CONFIG_ARM_TRUSTZONE
+	/*
+	 * Restore for Outer cache
+	 */
+	exynos_smc(SMC_CMD_L2X0SETUP1, exynos4_l2cc_save[0].val,
+				       exynos4_l2cc_save[1].val,
+				       exynos4_l2cc_save[2].val);
+
+	CHECK_POINT;
+
+	exynos_smc(SMC_CMD_L2X0SETUP2,
+			L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
+			0x7C470001, 0xC200FFFF);
+
+	CHECK_POINT;
+
+	exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0);
+
+	CHECK_POINT;
+
+	exynos_smc(SMC_CMD_L2X0CTRL, 1, 0, 0);
+#else
+	s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
+	outer_inv_all();
+	/* enable L2X0*/
+	writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL);
+#endif
+	/* Enable the full line of zero */
+	enable_cache_foz();
+#endif
+
+	CHECK_POINT;
+
+early_wakeup:
+	if (!soc_is_exynos4210())
+		exynos4_reset_assert_ctrl(1);
+
+	CHECK_POINT;
+
+	/* Clear Check mode */
+	__raw_writel(0x0, REG_INFORM1);
+
+	return;
+}
+
+static struct syscore_ops exynos4_pm_syscore_ops = {
+	.suspend	= exynos4_pm_suspend,
+	.resume		= exynos4_pm_resume,
+};
+
+static __init int exynos4_pm_syscore_init(void)
+{
+	register_syscore_ops(&exynos4_pm_syscore_ops);
+	return 0;
+}
+arch_initcall(exynos4_pm_syscore_init);
diff --git a/arch/arm/mach-exynos/pm-exynos5.c b/arch/arm/mach-exynos/pm-exynos5.c
new file mode 100644
index 0000000..933ee08
--- /dev/null
+++ b/arch/arm/mach-exynos/pm-exynos5.c
@@ -0,0 +1,466 @@
+/* linux/arch/arm/mach-exynos/pm-exynos5.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS5 - Power Management support
+ *
+ * Based on arch/arm/mach-s3c2410/pm.c
+ * Copyright (c) 2006 Simtec Electronics
+ *	Ben Dooks <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/suspend.h>
+#include <linux/syscore_ops.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+
+#include <asm/cacheflush.h>
+
+#include <plat/cpu.h>
+#include <plat/pm.h>
+#include <plat/bts.h>
+
+#include <mach/regs-irq.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-clock.h>
+#include <mach/regs-pmu5.h>
+#include <mach/pm-core.h>
+#include <mach/pmu.h>
+#include <mach/smc.h>
+
+#include <mach/map-exynos5.h>
+
+void (*exynos5_sleep_gpio_table_set)(void);
+
+#ifdef CONFIG_ARM_TRUSTZONE
+#define REG_INFORM0            (S5P_VA_SYSRAM_NS + 0x8)
+#define REG_INFORM1            (S5P_VA_SYSRAM_NS + 0xC)
+#else
+#define REG_INFORM0            (EXYNOS5_INFORM0)
+#define REG_INFORM1            (EXYNOS5_INFORM1)
+#endif
+
+static struct sleep_save exynos5_set_clksrc[] = {
+	{ .reg = EXYNOS5_CLKSRC_MASK_TOP		, .val = 0xffffffff, },
+	{ .reg = EXYNOS5_CLKSRC_MASK_GSCL		, .val = 0xffffffff, },
+	{ .reg = EXYNOS5_CLKSRC_MASK_DISP1_0		, .val = 0xffffffff, },
+	{ .reg = EXYNOS5_CLKSRC_MASK_MAUDIO		, .val = 0xffffffff, },
+	{ .reg = EXYNOS5_CLKSRC_MASK_FSYS		, .val = 0xffffffff, },
+	{ .reg = EXYNOS5_CLKSRC_MASK_PERIC0		, .val = 0xffffffff, },
+	{ .reg = EXYNOS5_CLKSRC_MASK_PERIC1		, .val = 0xffffffff, },
+	{ .reg = EXYNOS5_CLKSRC_MASK_ISP		, .val = 0xffffffff, },
+};
+
+static struct sleep_save exynos5_core_save[] = {
+	/* GIC side */
+	SAVE_ITEM(S5P_VA_GIC_CPU + 0x000),
+	SAVE_ITEM(S5P_VA_GIC_CPU + 0x004),
+	SAVE_ITEM(S5P_VA_GIC_CPU + 0x008),
+	SAVE_ITEM(S5P_VA_GIC_CPU + 0x00C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x000),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x004),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x100),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x104),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x108),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x10C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x110),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x300),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x304),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x308),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x30C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x310),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x400),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x404),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x408),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x40C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x410),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x414),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x418),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x41C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x420),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x424),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x428),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x42C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x430),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x434),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x438),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x43C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x440),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x444),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x448),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x44C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x450),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x454),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x458),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x45C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x460),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x464),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x468),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x46C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x470),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x474),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x478),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x47C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x480),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x484),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x488),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x48C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x490),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x494),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x498),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x49C),
+
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x800),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x804),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x808),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x80C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x810),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x814),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x818),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x81C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x820),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x824),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x828),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x82C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x830),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x834),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x838),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x83C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x840),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x844),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x848),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x84C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x850),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x854),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x858),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x85C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x860),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x864),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x868),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x86C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x870),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x874),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x878),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x87C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x880),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x884),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x888),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x88C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x890),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x894),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x898),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x89C),
+
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0xC00),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0xC04),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0xC08),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0xC0C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0xC10),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0xC14),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0xC18),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0xC1C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0xC20),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0xC24),
+
+	SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x000),
+	SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x010),
+	SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x020),
+	SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x030),
+	SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x040),
+	SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x050),
+	SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x060),
+	SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x070),
+
+	SAVE_ITEM(S3C_VA_SYS + 0x234),
+};
+
+static struct sleep_save exynos5_regs_save[] = {
+	/* Common GPIO Part1 */
+        SAVE_ITEM(S5P_VA_GPIO + 0x700),
+        SAVE_ITEM(S5P_VA_GPIO + 0x704),
+        SAVE_ITEM(S5P_VA_GPIO + 0x708),
+        SAVE_ITEM(S5P_VA_GPIO + 0x70C),
+        SAVE_ITEM(S5P_VA_GPIO + 0x710),
+        SAVE_ITEM(S5P_VA_GPIO + 0x714),
+        SAVE_ITEM(S5P_VA_GPIO + 0x718),
+        SAVE_ITEM(S5P_VA_GPIO + 0x71C),
+        SAVE_ITEM(S5P_VA_GPIO + 0x720),
+        SAVE_ITEM(S5P_VA_GPIO + 0x724),
+        SAVE_ITEM(S5P_VA_GPIO + 0x728),
+        SAVE_ITEM(S5P_VA_GPIO + 0x72C),
+        SAVE_ITEM(S5P_VA_GPIO + 0x730),
+        SAVE_ITEM(S5P_VA_GPIO + 0x900),
+        SAVE_ITEM(S5P_VA_GPIO + 0x904),
+        SAVE_ITEM(S5P_VA_GPIO + 0x908),
+        SAVE_ITEM(S5P_VA_GPIO + 0x90C),
+        SAVE_ITEM(S5P_VA_GPIO + 0x910),
+        SAVE_ITEM(S5P_VA_GPIO + 0x914),
+        SAVE_ITEM(S5P_VA_GPIO + 0x918),
+        SAVE_ITEM(S5P_VA_GPIO + 0x91C),
+        SAVE_ITEM(S5P_VA_GPIO + 0x920),
+        SAVE_ITEM(S5P_VA_GPIO + 0x924),
+        SAVE_ITEM(S5P_VA_GPIO + 0x928),
+        SAVE_ITEM(S5P_VA_GPIO + 0x92C),
+        SAVE_ITEM(S5P_VA_GPIO + 0x930),
+	/* Common GPIO Part2 */
+        SAVE_ITEM(S5P_VA_GPIO2 + 0x700),
+        SAVE_ITEM(S5P_VA_GPIO2 + 0x704),
+        SAVE_ITEM(S5P_VA_GPIO2 + 0x708),
+        SAVE_ITEM(S5P_VA_GPIO2 + 0x70C),
+        SAVE_ITEM(S5P_VA_GPIO2 + 0x710),
+        SAVE_ITEM(S5P_VA_GPIO2 + 0x714),
+        SAVE_ITEM(S5P_VA_GPIO2 + 0x718),
+        SAVE_ITEM(S5P_VA_GPIO2 + 0x71C),
+        SAVE_ITEM(S5P_VA_GPIO2 + 0x720),
+        SAVE_ITEM(S5P_VA_GPIO2 + 0x900),
+        SAVE_ITEM(S5P_VA_GPIO2 + 0x904),
+        SAVE_ITEM(S5P_VA_GPIO2 + 0x908),
+        SAVE_ITEM(S5P_VA_GPIO2 + 0x90C),
+        SAVE_ITEM(S5P_VA_GPIO2 + 0x910),
+        SAVE_ITEM(S5P_VA_GPIO2 + 0x914),
+        SAVE_ITEM(S5P_VA_GPIO2 + 0x918),
+        SAVE_ITEM(S5P_VA_GPIO2 + 0x91C),
+        SAVE_ITEM(S5P_VA_GPIO2 + 0x920),
+};
+
+void exynos5_cpu_suspend(void)
+{
+	unsigned int tmp;
+
+	/* Disable wakeup by EXT_GIC */
+	tmp = __raw_readl(EXYNOS5_WAKEUP_MASK);
+	tmp |= EXYNOS5_DEFAULT_WAKEUP_MACK;
+	__raw_writel(tmp, EXYNOS5_WAKEUP_MASK);
+
+	/*
+	 * GPS LPI mask.
+	 */
+	if (samsung_rev() < EXYNOS5250_REV_1_0)
+		__raw_writel(0x10000, EXYNOS5_GPS_LPI);
+
+	if (samsung_rev() >= EXYNOS5250_REV_1_0)
+		exynos4_reset_assert_ctrl(0);
+
+#ifdef CONFIG_ARM_TRUSTZONE
+	exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
+#else
+	/* issue the standby signal into the pm unit. */
+	cpu_do_idle();
+#endif
+}
+
+static void exynos5_pm_prepare(void)
+{
+	unsigned int tmp;
+
+	if (exynos5_sleep_gpio_table_set)
+		exynos5_sleep_gpio_table_set();
+
+	if (samsung_rev() < EXYNOS5250_REV_1_0) {
+		/* Disable USE_RETENTION of JPEG_MEM_OPTION */
+		tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
+		tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
+		__raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
+	}
+
+	if (samsung_rev() >= EXYNOS5250_REV_1_0) {
+		tmp = __raw_readl(EXYNOS5_ARM_L2_OPTION);
+		tmp &= ~(1 << 4);
+		__raw_writel(tmp, EXYNOS5_ARM_L2_OPTION);
+	}
+
+	/* Set value of power down register for sleep mode */
+	exynos5_sys_powerdown_conf(SYS_SLEEP);
+	__raw_writel(S5P_CHECK_SLEEP, REG_INFORM1);
+
+	/* ensure at least INFORM0 has the resume address */
+	__raw_writel(virt_to_phys(s3c_cpu_resume), REG_INFORM0);
+
+	if (exynos4_is_c2c_use()) {
+		tmp = __raw_readl(EXYNOS5_INTRAM_MEM_OPTION);
+		tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
+		__raw_writel(tmp, EXYNOS5_INTRAM_MEM_OPTION);
+	}
+
+	s3c_pm_do_restore_core(exynos5_set_clksrc, ARRAY_SIZE(exynos5_set_clksrc));
+}
+
+static int exynos5_pm_add(struct sys_device *sysdev)
+{
+	pm_cpu_prep = exynos5_pm_prepare;
+	pm_cpu_sleep = exynos5_cpu_suspend;
+
+	return 0;
+}
+
+static struct sysdev_driver exynos5_pm_driver = {
+	.add		= exynos5_pm_add,
+};
+
+static __init int exynos5_pm_drvinit(void)
+{
+	s3c_pm_init();
+
+	return sysdev_driver_register(&exynos5_sysclass, &exynos5_pm_driver);
+}
+arch_initcall(exynos5_pm_drvinit);
+
+bool isp_pwr_off;
+
+static int exynos5_pm_suspend(void)
+{
+	unsigned long tmp;
+	u32 timeout;
+
+	s3c_pm_do_save(exynos5_core_save, ARRAY_SIZE(exynos5_core_save));
+
+	s3c_pm_do_save(exynos5_regs_save, ARRAY_SIZE(exynos5_regs_save));
+
+	if (samsung_rev() < EXYNOS5250_REV_1_0) {
+		if (!(__raw_readl(EXYNOS5_ISP_STATUS) & S5P_INT_LOCAL_PWR_EN)) {
+			isp_pwr_off = true;
+			/*
+			 * Before enter suspend, ISP power domain should be on
+			 */
+			__raw_writel(S5P_INT_LOCAL_PWR_EN,
+					EXYNOS5_ISP_CONFIGURATION);
+			timeout = 1000;
+
+			while (!(__raw_readl(EXYNOS5_ISP_STATUS) & S5P_INT_LOCAL_PWR_EN)) {
+				if (timeout == 0) {
+					printk(KERN_ERR "ISP power domain can not on\n");
+				}
+				timeout--;
+				udelay(1);
+			}
+		}
+	}
+
+	tmp = __raw_readl(EXYNOS5_CENTRAL_SEQ_CONFIGURATION);
+	tmp &= ~(EXYNOS5_CENTRAL_LOWPWR_CFG);
+	__raw_writel(tmp, EXYNOS5_CENTRAL_SEQ_CONFIGURATION);
+
+	tmp = __raw_readl(EXYNOS5_CENTRAL_SEQ_OPTION);
+
+	tmp = (EXYNOS5_USE_STANDBYWFI_ARM_CORE0 |
+		EXYNOS5_USE_STANDBYWFE_ARM_CORE0);
+
+	__raw_writel(tmp, EXYNOS5_CENTRAL_SEQ_OPTION);
+
+	return 0;
+}
+
+static void exynos5_pm_resume(void)
+{
+	unsigned long tmp, srctmp;
+	u32 timeout;
+
+	if (samsung_rev() >= EXYNOS5250_REV_1_0)
+		exynos4_reset_assert_ctrl(1);
+
+	/* If PMU failed while entering sleep mode, WFI will be
+	 * ignored by PMU and then exiting cpu_do_idle().
+	 * EXYNOS5_CENTRAL_SEQ_CONFIGURATION bit will not be set
+	 * automatically in this situation.
+	 */
+	tmp = __raw_readl(EXYNOS5_CENTRAL_SEQ_CONFIGURATION);
+
+	if (!(tmp & EXYNOS5_CENTRAL_LOWPWR_CFG)) {
+		tmp |= EXYNOS5_CENTRAL_LOWPWR_CFG;
+		__raw_writel(tmp, EXYNOS5_CENTRAL_SEQ_CONFIGURATION);
+		/* No need to perform below restore code */
+		goto early_wakeup;
+	}
+
+	if ((samsung_rev() < EXYNOS5250_REV_1_0) && isp_pwr_off) {
+		srctmp = __raw_readl(EXYNOS5_CLKSRC_TOP3);
+		/*
+		 * To ISP power domain off,
+		 * first, ISP_ARM power domain be off.
+		 */
+		if ((__raw_readl(EXYNOS5_ISP_ARM_STATUS) & 0x1)) {
+			/* Disable ISP_ARM */
+			timeout = __raw_readl(EXYNOS5_ISP_ARM_OPTION);
+			timeout &= ~EXYNOS5_ISP_ARM_ENABLE;
+			__raw_writel(timeout, EXYNOS5_ISP_ARM_OPTION);
+
+			/* ISP_ARM power off */
+			__raw_writel(0x0, EXYNOS5_ISP_ARM_CONFIGURATION);
+
+			timeout = 1000;
+
+			while (__raw_readl(EXYNOS5_ISP_ARM_STATUS) & 0x1) {
+				if (timeout == 0) {
+					printk(KERN_ERR "ISP_ARM power domain can not off\n");
+					return;
+				}
+				timeout--;
+				udelay(1);
+			}
+			/* CMU_RESET_ISP_ARM off */
+			__raw_writel(0x0, EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG);
+		}
+
+		__raw_writel(0x0, EXYNOS5_ISP_CONFIGURATION);
+
+		/* Wait max 1ms */
+		timeout = 1000;
+		while (__raw_readl(EXYNOS5_ISP_STATUS) & S5P_INT_LOCAL_PWR_EN) {
+			if (timeout == 0) {
+				printk(KERN_ERR "Power domain ISP disable failed.\n");
+				return;
+			}
+			timeout--;
+			udelay(1);
+		}
+
+		__raw_writel(srctmp, EXYNOS5_CLKSRC_TOP3);
+
+		isp_pwr_off = false;
+	}
+
+	/* For release retention */
+	__raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_MAU_OPTION);
+	__raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_GPIO_OPTION);
+	__raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_UART_OPTION);
+	__raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_MMCA_OPTION);
+	__raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_MMCB_OPTION);
+	__raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_EBIA_OPTION);
+	__raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_EBIB_OPTION);
+	__raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_SPI_OPTION);
+	
+	/* For Retention release on GPV block */
+	__raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_OPTION);
+
+	/* Disable CPU_nIRQ[0:1] */
+	tmp = ((0x1 << 8) | (0x1 << 0));
+	__raw_writel(tmp, S5P_VA_COMBINER_BASE + 0x54);
+
+	bts_enable(PD_TOP);
+
+	s3c_pm_do_restore(exynos5_regs_save, ARRAY_SIZE(exynos5_regs_save));
+
+	s3c_pm_do_restore_core(exynos5_core_save, ARRAY_SIZE(exynos5_core_save));
+
+early_wakeup:
+	__raw_writel(0x0, REG_INFORM1);
+}
+
+static struct syscore_ops exynos5_pm_syscore_ops = {
+	.suspend	= exynos5_pm_suspend,
+	.resume		= exynos5_pm_resume,
+};
+
+static __init int exynos5_pm_syscore_init(void)
+{
+	register_syscore_ops(&exynos5_pm_syscore_ops);
+
+	return 0;
+}
+arch_initcall(exynos5_pm_syscore_init);
diff --git a/arch/arm/mach-exynos/pm-hotplug.c b/arch/arm/mach-exynos/pm-hotplug.c
new file mode 100644
index 0000000..d82503d
--- /dev/null
+++ b/arch/arm/mach-exynos/pm-hotplug.c
@@ -0,0 +1,225 @@
+/* linux/arch/arm/mach-s5pv310/pm-hotplug.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * S5PV310 - Dynamic CPU hotpluging
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/ioport.h>
+#include <linux/delay.h>
+#include <linux/serial_core.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/cpu.h>
+#include <linux/percpu.h>
+#include <linux/ktime.h>
+#include <linux/tick.h>
+#include <linux/kernel_stat.h>
+#include <linux/sched.h>
+#include <linux/suspend.h>
+#include <linux/reboot.h>
+
+#include <plat/map-base.h>
+#include <plat/gpio-cfg.h>
+
+#include <mach/regs-gpio.h>
+#include <mach/regs-irq.h>
+#include <linux/gpio.h>
+#include <linux/cpufreq.h>
+
+#define CPUMON 1
+
+#define CHECK_DELAY	(.5*HZ)
+#define TRANS_LOAD_L	20
+#define TRANS_LOAD_H	50
+
+#define HOTPLUG_UNLOCKED 0
+#define HOTPLUG_LOCKED 1
+
+static struct workqueue_struct *hotplug_wq;
+
+static struct delayed_work hotplug_work;
+
+static unsigned int hotpluging_rate = CHECK_DELAY;
+module_param_named(rate, hotpluging_rate, uint, 0644);
+static unsigned int user_lock;
+module_param_named(lock, user_lock, uint, 0644);
+static unsigned int trans_load_l = TRANS_LOAD_L;
+module_param_named(loadl, trans_load_l, uint, 0644);
+static unsigned int trans_load_h = TRANS_LOAD_H;
+module_param_named(loadh, trans_load_h, uint, 0644);
+
+struct cpu_time_info {
+	cputime64_t prev_cpu_idle;
+	cputime64_t prev_cpu_wall;
+	unsigned int load;
+};
+
+static DEFINE_PER_CPU(struct cpu_time_info, hotplug_cpu_time);
+
+/* mutex can be used since hotplug_timer does not run in
+   timer(softirq) context but in process context */
+static DEFINE_MUTEX(hotplug_lock);
+
+static void hotplug_timer(struct work_struct *work)
+{
+	unsigned int i, avg_load = 0, load = 0;
+	unsigned int cur_freq;
+
+	mutex_lock(&hotplug_lock);
+
+	if (user_lock == 1)
+		goto no_hotplug;
+
+	for_each_online_cpu(i) {
+		struct cpu_time_info *tmp_info;
+		cputime64_t cur_wall_time, cur_idle_time;
+		unsigned int idle_time, wall_time;
+
+		tmp_info = &per_cpu(hotplug_cpu_time, i);
+
+		cur_idle_time = get_cpu_idle_time_us(i, &cur_wall_time);
+
+		idle_time = (unsigned int)cputime64_sub(cur_idle_time,
+						tmp_info->prev_cpu_idle);
+		tmp_info->prev_cpu_idle = cur_idle_time;
+
+		wall_time = (unsigned int)cputime64_sub(cur_wall_time,
+						tmp_info->prev_cpu_wall);
+		tmp_info->prev_cpu_wall = cur_wall_time;
+
+		if (wall_time < idle_time)
+			goto no_hotplug;
+
+		tmp_info->load = 100 * (wall_time - idle_time) / wall_time;
+
+		load += tmp_info->load;
+	}
+
+	avg_load = load / num_online_cpus();
+
+	cur_freq = cpufreq_get(0);
+
+	if (((avg_load < trans_load_l) || (cur_freq <= 200 * 1000)) &&
+	    (cpu_online(1) == 1)) {
+		printk(KERN_INFO "cpu1 turning off!\n");
+		cpu_down(1);
+#if CPUMON
+		printk(KERN_ERR "CPUMON D %d\n", avg_load);
+#endif
+		printk(KERN_INFO "cpu1 off end!\n");
+		hotpluging_rate = CHECK_DELAY;
+	} else if (((avg_load > trans_load_h) && (cur_freq > 200 * 1000)) &&
+		   (cpu_online(1) == 0)) {
+		printk(KERN_INFO "cpu1 turning on!\n");
+		cpu_up(1);
+#if CPUMON
+		printk(KERN_ERR "CPUMON U %d\n", avg_load);
+#endif
+		printk(KERN_INFO "cpu1 on end!\n");
+		hotpluging_rate = CHECK_DELAY * 4;
+	}
+ no_hotplug:
+
+	queue_delayed_work_on(0, hotplug_wq, &hotplug_work, hotpluging_rate);
+
+	mutex_unlock(&hotplug_lock);
+}
+
+static int exynos4_pm_hotplug_notifier_event(struct notifier_block *this,
+					     unsigned long event, void *ptr)
+{
+	static unsigned user_lock_saved;
+
+	switch (event) {
+	case PM_SUSPEND_PREPARE:
+		mutex_lock(&hotplug_lock);
+		user_lock_saved = user_lock;
+		user_lock = 1;
+		pr_info("%s: saving pm_hotplug lock %x\n",
+			__func__, user_lock_saved);
+		mutex_unlock(&hotplug_lock);
+		return NOTIFY_OK;
+	case PM_POST_RESTORE:
+	case PM_POST_SUSPEND:
+		mutex_lock(&hotplug_lock);
+		pr_info("%s: restoring pm_hotplug lock %x\n",
+			__func__, user_lock_saved);
+		user_lock = user_lock_saved;
+		mutex_unlock(&hotplug_lock);
+		return NOTIFY_OK;
+	}
+	return NOTIFY_DONE;
+}
+
+static struct notifier_block exynos4_pm_hotplug_notifier = {
+	.notifier_call = exynos4_pm_hotplug_notifier_event,
+};
+
+static int hotplug_reboot_notifier_call(struct notifier_block *this,
+					unsigned long code, void *_cmd)
+{
+	mutex_lock(&hotplug_lock);
+	pr_err("%s: disabling pm hotplug\n", __func__);
+	user_lock = 1;
+	mutex_unlock(&hotplug_lock);
+
+	return NOTIFY_DONE;
+}
+
+static struct notifier_block hotplug_reboot_notifier = {
+	.notifier_call = hotplug_reboot_notifier_call,
+};
+
+static int __init exynos4_pm_hotplug_init(void)
+{
+	printk(KERN_INFO "EXYNOS4 PM-hotplug init function\n");
+	/* hotplug_wq = create_workqueue("dynamic hotplug"); */
+	hotplug_wq = alloc_workqueue("dynamic hotplug", 0, 0);
+	if (!hotplug_wq) {
+		printk(KERN_ERR "Creation of hotplug work failed\n");
+		return -EFAULT;
+	}
+
+	INIT_DELAYED_WORK(&hotplug_work, hotplug_timer);
+
+	queue_delayed_work_on(0, hotplug_wq, &hotplug_work, 60 * HZ);
+
+	register_pm_notifier(&exynos4_pm_hotplug_notifier);
+	register_reboot_notifier(&hotplug_reboot_notifier);
+
+	return 0;
+}
+
+late_initcall(exynos4_pm_hotplug_init);
+
+static struct platform_device exynos4_pm_hotplug_device = {
+	.name = "exynos4-dynamic-cpu-hotplug",
+	.id = -1,
+};
+
+static int __init exynos4_pm_hotplug_device_init(void)
+{
+	int ret;
+
+	ret = platform_device_register(&exynos4_pm_hotplug_device);
+
+	if (ret) {
+		printk(KERN_ERR "failed at(%d)\n", __LINE__);
+		return ret;
+	}
+
+	printk(KERN_INFO "exynos4_pm_hotplug_device_init: %d\n", ret);
+
+	return ret;
+}
+
+late_initcall(exynos4_pm_hotplug_device_init);
diff --git a/arch/arm/mach-exynos/pmu-exynos4.c b/arch/arm/mach-exynos/pmu-exynos4.c
new file mode 100644
index 0000000..d0b4fbd
--- /dev/null
+++ b/arch/arm/mach-exynos/pmu-exynos4.c
@@ -0,0 +1,447 @@
+/* linux/arch/arm/mach-exynos/pmu-exynos4.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * EXYNOS4210 - CPU PMU(Power Management Unit) support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/kernel.h>
+
+#include <mach/regs-clock.h>
+#include <mach/pmu.h>
+#include <mach/regs-pmu.h>
+
+#include <plat/cpu.h>
+
+static struct exynos4_pmu_conf *exynos4_pmu_config;
+
+static unsigned int entry_cnt;
+
+static struct exynos4_pmu_conf exynos4210_pmu_config[] = {
+	/* { .reg = address, .val = { AFTR, LPA, SLEEP } */
+	{ S5P_ARM_CORE0_SYS,			{ 0, 0, 2 } },
+	{ S5P_DIS_IRQ_ARM_CORE0_LOCAL_SYS,	{ 0, 0, 0 } },
+	{ S5P_DIS_IRQ_ARM_CORE0_CENTRAL_SYS,	{ 0, 0, 0 } },
+	{ S5P_ARM_CORE1_SYS,			{ 0, 0, 2 } },
+	{ S5P_DIS_IRQ_ARM_CORE1_LOCAL_SYS,	{ 0, 0, 0 } },
+	{ S5P_DIS_IRQ_ARM_CORE1_CENTRAL_SYS,	{ 0, 0, 0 } },
+	{ S5P_ARM_COMMON_SYS,			{ 0, 0, 2 } },
+	{ S5P_ARM_L2_0_SYS,			{ 2, 2, 3 } },
+	{ S5P_ARM_L2_1_SYS,			{ 2, 2, 3 } },
+	{ S5P_CMU_ACLKSTOP_SYS,			{ 1, 0, 0 } },
+	{ S5P_CMU_SCLKSTOP_SYS,			{ 1, 0, 0 } },
+	{ S5P_CMU_RESET_SYS,			{ 1, 1, 0 } },
+	{ S5P_APLL_SYSCLK_SYS,			{ 1, 0, 0 } },
+	{ S5P_MPLL_SYSCLK_SYS,			{ 1, 0, 0 } },
+	{ S5P_VPLL_SYSCLK_SYS,			{ 1, 0, 0 } },
+	{ S5P_EPLL_SYSCLK_SYS,			{ 1, 1, 0 } },
+	{ S5P_CMU_CLKSTOP_GPS_ALIVE_SYS,	{ 1, 1, 0 } },
+	{ S5P_CMU_RESET_GPSALIVE_SYS,		{ 1, 1, 0 } },
+	{ S5P_CMU_CLKSTOP_CAM_SYS,		{ 1, 1, 0 } },
+	{ S5P_CMU_CLKSTOP_TV_SYS,		{ 1, 1, 0 } },
+	{ S5P_CMU_CLKSTOP_MFC_SYS,		{ 1, 1, 0 } },
+	{ S5P_CMU_CLKSTOP_G3D_SYS,		{ 1, 1, 0 } },
+	{ S5P_CMU_CLKSTOP_LCD0_SYS,		{ 1, 1, 0 } },
+	{ S5P_CMU_CLKSTOP_LCD1_SYS,		{ 1, 1, 0 } },
+	{ S5P_CMU_CLKSTOP_MAUDIO_SYS,		{ 1, 1, 0 } },
+	{ S5P_CMU_CLKSTOP_GPS_SYS,		{ 1, 1, 0 } },
+	{ S5P_CMU_RESET_CAM_SYS,		{ 1, 1, 0 } },
+	{ S5P_CMU_RESET_TV_SYS,			{ 1, 1, 0 } },
+	{ S5P_CMU_RESET_MFC_SYS,		{ 1, 1, 0 } },
+	{ S5P_CMU_RESET_G3D_SYS,		{ 1, 1, 0 } },
+	{ S5P_CMU_RESET_LCD0_SYS,		{ 1, 1, 0 } },
+	{ S5P_CMU_RESET_LCD1_SYS,		{ 1, 1, 0 } },
+	{ S5P_CMU_RESET_MAUDIO_SYS,		{ 1, 1, 0 } },
+	{ S5P_CMU_RESET_GPS_SYS,		{ 1, 1, 0 } },
+	{ S5P_TOP_BUS_SYS,			{ 3, 0, 0 } },
+	{ S5P_TOP_RETENTION_SYS,		{ 1, 0, 1 } },
+	{ S5P_TOP_PWR_SYS,			{ 3, 0, 3 } },
+	{ S5P_LOGIC_RESET_SYS,			{ 1, 1, 0 } },
+	{ S5P_ONENAND_MEM_SYS,			{ 3, 0, 0 } },
+	{ S5P_MODIMIF_MEM_SYS,			{ 3, 0, 0 } },
+	{ S5P_G2D_ACP_MEM_SYS,			{ 3, 0, 0 } },
+	{ S5P_USBOTG_MEM_SYS,			{ 3, 0, 0 } },
+	{ S5P_SDMMC_MEM_SYS,			{ 3, 0, 0 } },
+	{ S5P_CSSYS_MEM_SYS,			{ 3, 0, 0 } },
+	{ S5P_SECSS_MEM_SYS,			{ 3, 0, 0 } },
+	{ S5P_PCIE_MEM_SYS,			{ 3, 0, 0 } },
+	{ S5P_SATA_MEM_SYS,			{ 3, 0, 0 } },
+	{ S5P_PAD_RETENTION_DRAM_SYS,		{ 1, 0, 0 } },
+	{ S5P_PAD_RETENTION_MAUDIO_SYS,		{ 1, 1, 0 } },
+	{ S5P_PAD_RETENTION_GPIO_SYS,		{ 1, 0, 0 } },
+	{ S5P_PAD_RETENTION_UART_SYS,		{ 1, 0, 0 } },
+	{ S5P_PAD_RETENTION_MMCA_SYS,		{ 1, 0, 0 } },
+	{ S5P_PAD_RETENTION_MMCB_SYS,		{ 1, 0, 0 } },
+	{ S5P_PAD_RETENTION_EBIA_SYS,		{ 1, 0, 0 } },
+	{ S5P_PAD_RETENTION_EBIB_SYS,		{ 1, 0, 0 } },
+	{ S5P_PAD_ISOLATION_SYS,		{ 1, 0, 0 } },
+	{ S5P_PAD_ALV_SEL_SYS,			{ 1, 0, 0 } },
+	{ S5P_XXTI_SYS,				{ 1, 1, 0 } },
+	{ S5P_EXT_REGULATOR_SYS,		{ 1, 1, 0 } },
+	{ S5P_GPIO_MODE_SYS,			{ 1, 0, 0 } },
+	{ S5P_GPIO_MODE_MAUDIO_SYS,		{ 1, 1, 0 } },
+	{ S5P_CAM_SYS,				{ 7, 0, 0 } },
+	{ S5P_TV_SYS,				{ 7, 0, 0 } },
+	{ S5P_MFC_SYS,				{ 7, 0, 0 } },
+	{ S5P_G3D_SYS,				{ 7, 0, 0 } },
+	{ S5P_LCD0_SYS,				{ 7, 0, 0 } },
+	{ S5P_LCD1_SYS,				{ 7, 0, 0 } },
+	{ S5P_MAUDIO_SYS,			{ 7, 7, 0 } },
+	{ S5P_GPS_SYS,				{ 7, 0, 0 } },
+	{ S5P_GPS_ALIVE_SYS,			{ 7, 0, 0 } },
+	{ S5P_XUSBXTI_SYS,			{ 1, 1, 0 } },
+};
+
+static struct exynos4_pmu_conf exynos4212_pmu_config[] = {
+	{ S5P_ARM_CORE0_SYS,			{ 0, 0, 2 } },
+	{ S5P_DIS_IRQ_ARM_CORE0_LOCAL_SYS,	{ 0, 0, 0 } },
+	{ S5P_DIS_IRQ_ARM_CORE0_CENTRAL_SYS,	{ 0, 0, 0 } },
+	{ S5P_ARM_CORE1_SYS,			{ 0, 0, 2 } },
+	{ S5P_DIS_IRQ_ARM_CORE1_LOCAL_SYS,	{ 0, 0, 0 } },
+	{ S5P_DIS_IRQ_ARM_CORE1_CENTRAL_SYS,	{ 0, 0, 0 } },
+	{ S5P_ISP_ARM_SYS,			{ 1, 0, 0 } },
+	{ S5P_DIS_IRQ_ISP_ARM_LOCAL_SYS,	{ 0, 0, 0 } },
+	{ S5P_DIS_IRQ_ISP_ARM_CENTRAL_SYS,	{ 1, 0, 0 } },
+	{ S5P_ARM_COMMON_SYS,			{ 0, 0, 2 } },
+	{ S5P_ARM_L2_0_SYS,			{ 0, 0, 3 } },
+	{ S5P_ARM_L2_0_OPTION,			{ 0x10, 0x10, 0 } },
+	{ S5P_ARM_L2_1_SYS,			{ 0, 0, 3 } },
+	{ S5P_ARM_L2_1_OPTION,			{ 0x10, 0x10, 0 } },
+	{ S5P_CMU_ACLKSTOP_SYS,			{ 1, 0, 0 } },
+	{ S5P_CMU_SCLKSTOP_SYS,			{ 1, 0, 0 } },
+	{ S5P_CMU_RESET_SYS,			{ 1, 1, 0 } },
+	{ S5P_DRAM_FREQ_DOWN_SYS,		{ 1, 1, 1 } },
+	{ S5P_DDRPHY_DLLOFF_SYS,		{ 1, 1, 1 } },
+	{ S5P_LPDDR_PHY_DLL_LOCK_SYS,		{ 1, 1, 1 } },
+	{ S5P_CMU_ACLKSTOP_COREBLK_SYS,		{ 1, 0, 0 } },
+	{ S5P_CMU_SCLKSTOP_COREBLK_SYS,		{ 1, 0, 0 } },
+	{ S5P_CMU_RESET_COREBLK_SYS,		{ 1, 1, 0 } },
+	{ S5P_APLL_SYSCLK_SYS,			{ 1, 0, 0 } },
+	{ S5P_MPLL_SYSCLK_SYS,			{ 1, 0, 0 } },
+	{ S5P_VPLL_SYSCLK_SYS,			{ 1, 0, 0 } },
+	{ S5P_EPLL_SYSCLK_SYS,			{ 1, 1, 0 } },
+	{ S5P_MPLLUSER_SYSCLK_SYS,		{ 1, 0, 0 } },
+	{ S5P_CMU_CLKSTOP_GPS_ALIVE_SYS,	{ 1, 0, 0 } },
+	{ S5P_CMU_RESET_GPSALIVE_SYS,		{ 1, 0, 0 } },
+	{ S5P_CMU_CLKSTOP_CAM_SYS,		{ 1, 0, 0 } },
+	{ S5P_CMU_CLKSTOP_TV_SYS,		{ 1, 0, 0 } },
+	{ S5P_CMU_CLKSTOP_MFC_SYS,		{ 1, 0, 0 } },
+	{ S5P_CMU_CLKSTOP_G3D_SYS,		{ 1, 0, 0 } },
+	{ S5P_CMU_CLKSTOP_LCD0_SYS,		{ 1, 0, 0 } },
+	{ S5P_CMU_CLKSTOP_ISP_SYS,		{ 1, 0, 0 } },
+	{ S5P_CMU_CLKSTOP_MAUDIO_SYS,		{ 1, 0, 0 } },
+	{ S5P_CMU_CLKSTOP_GPS_SYS,		{ 0, 0, 0 } },
+
+	{ S5P_CMU_RESET_CAM_SYS,		{ 1, 0, 0 } },
+	{ S5P_CMU_RESET_TV_SYS,			{ 1, 0, 0 } },
+	{ S5P_CMU_RESET_MFC_SYS,		{ 1, 0, 0 } },
+	{ S5P_CMU_RESET_G3D_SYS,		{ 1, 0, 0 } },
+	{ S5P_CMU_RESET_LCD0_SYS,		{ 1, 0, 0 } },
+	{ S5P_CMU_RESET_ISP_SYS,		{ 0, 0, 0 } },
+	{ S5P_CMU_RESET_MAUDIO_SYS,		{ 1, 1, 0 } },
+	{ S5P_CMU_RESET_GPS_SYS,		{ 1, 0, 0 } },
+	{ S5P_TOP_BUS_SYS,			{ 3, 0, 0 } },
+	{ S5P_TOP_RETENTION_SYS,		{ 1, 0, 1 } },
+	{ S5P_TOP_PWR_SYS,			{ 3, 0, 3 } },
+	{ S5P_TOP_BUS_COREBLK_SYS,		{ 3, 0, 0 } },
+	{ S5P_TOP_RETENTION_COREBLK_SYS,	{ 1, 0, 1 } },
+	{ S5P_TOP_PWR_COREBLK_SYS,		{ 3, 0, 3 } },
+	{ S5P_LOGIC_RESET_SYS,			{ 1, 1, 0 } },
+	{ S5P_OSCCLK_GATE_SYS,			{ 1, 0, 1 } },
+	{ S5P_LOGIC_RESET_COREBLK_SYS,		{ 1, 1, 0 } },
+	{ S5P_OSCCLK_GATE_COREBLK_SYS,		{ 1, 0, 1 } },
+	{ S5P_ONENAND_MEM_SYS,			{ 3, 0, 0 } },
+	{ S5P_ONENAND_MEM_OPTION,		{ 0x10, 0x10, 0 } },
+	{ S5P_HSI_MEM_SYS,			{ 3, 0, 0 } },
+	{ S5P_HSI_MEM_OPTION,			{ 0x10, 0x10, 0 } },
+	{ S5P_G2D_ACP_MEM_SYS,			{ 3, 0, 0 } },
+	{ S5P_G2D_ACP_MEM_OPTION,		{ 0x10, 0x10, 0 } },
+	{ S5P_USBOTG_MEM_SYS,			{ 3, 0, 0 } },
+	{ S5P_USBOTG_MEM_OPTION,		{ 0x10, 0x10, 0 } },
+	{ S5P_SDMMC_MEM_SYS,			{ 3, 0, 0 } },
+	{ S5P_SDMMC_MEM_OPTION,			{ 0x10, 0x10, 0 } },
+	{ S5P_CSSYS_MEM_SYS,			{ 3, 0, 0 } },
+	{ S5P_CSSYS_MEM_OPTION,			{ 0x10, 0x10, 0 } },
+	{ S5P_SECSS_MEM_SYS,			{ 3, 0, 0 } },
+	{ S5P_SECSS_MEM_OPTION,			{ 0x10, 0x10, 0 } },
+	{ S5P_ROTATOR_MEM_SYS,			{ 3, 0, 0 } },
+	{ S5P_ROTATOR_MEM_OPTION,		{ 0x10, 0x10, 0 } },
+	{ S5P_PAD_RETENTION_DRAM_SYS,		{ 1, 0, 0 } },
+	{ S5P_PAD_RETENTION_MAUDIO_SYS,		{ 1, 1, 0 } },
+	{ S5P_PAD_RETENTION_GPIO_SYS,		{ 1, 0, 0 } },
+	{ S5P_PAD_RETENTION_UART_SYS,		{ 1, 0, 0 } },
+	{ S5P_PAD_RETENTION_MMCA_SYS,		{ 1, 0, 0 } },
+	{ S5P_PAD_RETENTION_MMCB_SYS,		{ 1, 0, 0 } },
+	{ S5P_PAD_RETENTION_EBIA_SYS,		{ 1, 0, 0 } },
+	{ S5P_PAD_RETENTION_EBIB_SYS,		{ 1, 0, 0 } },
+	{ S5P_PAD_RETENTION_GPIO_COREBLK_SYS,	{ 1, 0, 0 } },
+	{ S5P_PAD_ISOLATION_SYS,		{ 1, 0, 0 } },
+	{ S5P_PAD_ISOLATION_COREBLK_SYS,	{ 1, 0, 0 } },
+	{ S5P_PAD_ALV_SEL_SYS,			{ 1, 0, 0 } },
+	{ S5P_XXTI_SYS,				{ 1, 1, 0 } },
+	{ S5P_EXT_REGULATOR_SYS,		{ 1, 1, 0 } },
+	{ S5P_GPIO_MODE_SYS,			{ 1, 0, 0 } },
+	{ S5P_GPIO_MODE_COREBLK_SYS,		{ 1, 0, 0 } },
+	{ S5P_GPIO_MODE_MAUDIO_SYS,		{ 1, 1, 0 } },
+	{ S5P_TOP_ASB_RESET_SYS,		{ 1, 1, 1 } },
+	{ S5P_TOP_ASB_ISOLATION_SYS,		{ 1, 0, 1 } },
+	{ S5P_CAM_SYS,				{ 7, 0, 0 } },
+	{ S5P_TV_SYS,				{ 7, 0, 0 } },
+	{ S5P_MFC_SYS,				{ 7, 0, 0 } },
+	{ S5P_G3D_SYS,				{ 7, 0, 0 } },
+	{ S5P_LCD0_SYS,				{ 7, 0, 0 } },
+	{ S5P_ISP_SYS,				{ 7, 0, 0 } },
+	{ S5P_MAUDIO_SYS,			{ 7, 7, 0 } },
+	{ S5P_GPS_SYS,				{ 7, 0, 0 } },
+	{ S5P_GPS_ALIVE_SYS,			{ 7, 0, 0 } },
+	{ S5P_CMU_SYSCLK_ISP_SYS,		{ 0, 0, 0 } },
+	{ S5P_CMU_SYSCLK_GPS_SYS,		{ 1, 0, 0 } },
+	{ S5P_XUSBXTI_SYS,			{ 1, 1, 0 } },
+};
+
+static struct exynos4_pmu_conf exynos4412_pmu_config[] = {
+	{ S5P_ARM_CORE0_SYS,			{ 0, 0, 2 } },
+	{ S5P_ARM_CORE1_SYS,			{ 0, 0, 2 } },
+	{ S5P_ARM_CORE2_SYS,			{ 0, 0, 2 } },
+	{ S5P_ARM_CORE3_SYS,			{ 0, 0, 2 } },
+	{ S5P_ISP_ARM_SYS,			{ 1, 0, 0 } },
+	{ S5P_DIS_IRQ_ISP_ARM_LOCAL_SYS,	{ 0, 0, 0 } },
+	{ S5P_DIS_IRQ_ISP_ARM_CENTRAL_SYS,	{ 1, 0, 0 } },
+	{ S5P_ARM_COMMON_SYS,			{ 0, 0, 2 } },
+	{ S5P_ARM_L2_0_SYS,			{ 0, 0, 3 } },
+	{ S5P_ARM_L2_0_OPTION,			{ 0x10, 0x10, 0 } },
+	{ S5P_ARM_L2_1_SYS,			{ 0, 0, 3 } },
+	{ S5P_ARM_L2_1_OPTION,			{ 0x10, 0x10, 0 } },
+	{ S5P_CMU_ACLKSTOP_SYS,			{ 1, 0, 0 } },
+	{ S5P_CMU_SCLKSTOP_SYS,			{ 1, 0, 0 } },
+	{ S5P_CMU_RESET_SYS,			{ 1, 1, 0 } },
+	{ S5P_CMU_ACLKSTOP_COREBLK_SYS,		{ 1, 0, 0 } },
+	{ S5P_CMU_SCLKSTOP_COREBLK_SYS,		{ 1, 0, 0 } },
+	{ S5P_CMU_RESET_COREBLK_SYS,		{ 1, 1, 0 } },
+	{ S5P_APLL_SYSCLK_SYS,			{ 1, 0, 0 } },
+	{ S5P_MPLL_SYSCLK_SYS,			{ 1, 0, 0 } },
+	{ S5P_VPLL_SYSCLK_SYS,			{ 1, 0, 0 } },
+	{ S5P_EPLL_SYSCLK_SYS,			{ 1, 1, 0 } },
+	{ S5P_MPLLUSER_SYSCLK_SYS,		{ 1, 0, 0 } },
+	{ S5P_CMU_CLKSTOP_GPS_ALIVE_SYS,	{ 1, 0, 0 } },
+	{ S5P_CMU_RESET_GPSALIVE_SYS,		{ 1, 0, 0 } },
+	{ S5P_CMU_CLKSTOP_CAM_SYS,		{ 1, 0, 0 } },
+	{ S5P_CMU_CLKSTOP_TV_SYS,		{ 1, 0, 0 } },
+	{ S5P_CMU_CLKSTOP_MFC_SYS,		{ 1, 0, 0 } },
+	{ S5P_CMU_CLKSTOP_G3D_SYS,		{ 1, 0, 0 } },
+	{ S5P_CMU_CLKSTOP_LCD0_SYS,		{ 1, 0, 0 } },
+	{ S5P_CMU_CLKSTOP_ISP_SYS,		{ 1, 0, 0 } },
+	{ S5P_CMU_CLKSTOP_MAUDIO_SYS,		{ 1, 0, 0 } },
+	{ S5P_CMU_CLKSTOP_GPS_SYS,		{ 1, 0, 0 } },
+	{ S5P_CMU_RESET_CAM_SYS,		{ 1, 0, 0 } },
+	{ S5P_CMU_RESET_TV_SYS,			{ 1, 0, 0 } },
+	{ S5P_CMU_RESET_MFC_SYS,		{ 1, 0, 0 } },
+	{ S5P_CMU_RESET_G3D_SYS,		{ 1, 0, 0 } },
+	{ S5P_CMU_RESET_LCD0_SYS,		{ 1, 0, 0 } },
+	{ S5P_CMU_RESET_ISP_SYS,		{ 0, 0, 0 } },
+	{ S5P_CMU_RESET_MAUDIO_SYS,		{ 1, 0, 0 } },
+	{ S5P_CMU_RESET_GPS_SYS,		{ 1, 0, 0 } },
+	{ S5P_TOP_BUS_SYS,			{ 3, 0, 0 } },
+	{ S5P_TOP_RETENTION_SYS,		{ 1, 0, 1 } },
+	{ S5P_TOP_PWR_SYS,			{ 3, 0, 3 } },
+	{ S5P_TOP_BUS_COREBLK_SYS,		{ 3, 0, 0 } },
+	{ S5P_TOP_RETENTION_COREBLK_SYS,	{ 1, 0, 1 } },
+	{ S5P_TOP_PWR_COREBLK_SYS,		{ 3, 0, 3 } },
+	{ S5P_LOGIC_RESET_SYS,			{ 1, 1, 0 } },
+	{ S5P_OSCCLK_GATE_SYS,			{ 1, 0, 1 } },
+	{ S5P_LOGIC_RESET_COREBLK_SYS,		{ 1, 1, 0 } },
+	{ S5P_OSCCLK_GATE_COREBLK_SYS,		{ 1, 0, 1 } },
+	{ S5P_HSI_MEM_SYS,			{ 3, 0, 0 } },
+	{ S5P_HSI_MEM_OPTION,			{ 0x10, 0x10, 0 } },
+	{ S5P_G2D_ACP_MEM_SYS,			{ 3, 0, 0 } },
+	{ S5P_G2D_ACP_MEM_OPTION,		{ 0x10, 0x10, 0 } },
+	{ S5P_USBOTG_MEM_SYS,			{ 3, 0, 0 } },
+	{ S5P_USBOTG_MEM_OPTION,		{ 0x10, 0x10, 0 } },
+	{ S5P_SDMMC_MEM_SYS,			{ 3, 0, 0 } },
+	{ S5P_SDMMC_MEM_OPTION,			{ 0x10, 0x10, 0 } },
+	{ S5P_CSSYS_MEM_SYS,			{ 3, 0, 0 } },
+	{ S5P_CSSYS_MEM_OPTION,			{ 0x10, 0x10, 0 } },
+	{ S5P_SECSS_MEM_SYS,			{ 3, 0, 0 } },
+	{ S5P_SECSS_MEM_OPTION,			{ 0x10, 0x10, 0 } },
+	{ S5P_ROTATOR_MEM_SYS,			{ 3, 0, 0 } },
+	{ S5P_ROTATOR_MEM_OPTION,		{ 0x10, 0x10, 0 } },
+	{ S5P_PAD_RETENTION_DRAM_SYS,		{ 1, 0, 0 } },
+	{ S5P_PAD_RETENTION_MAUDIO_SYS,		{ 1, 1, 0 } },
+	{ S5P_PAD_RETENTION_GPIO_SYS,		{ 1, 0, 0 } },
+	{ S5P_PAD_RETENTION_UART_SYS,		{ 1, 0, 0 } },
+	{ S5P_PAD_RETENTION_MMCA_SYS,		{ 1, 0, 0 } },
+	{ S5P_PAD_RETENTION_MMCB_SYS,		{ 1, 0, 0 } },
+	{ S5P_PAD_RETENTION_EBIA_SYS,		{ 1, 0, 0 } },
+	{ S5P_PAD_RETENTION_EBIB_SYS,		{ 1, 0, 0 } },
+	{ S5P_PAD_RETENTION_GPIO_COREBLK_SYS,	{ 1, 0, 0 } },
+	{ S5P_PAD_ISOLATION_SYS,		{ 1, 0, 0 } },
+	{ S5P_PAD_ISOLATION_COREBLK_SYS,	{ 1, 0, 0 } },
+	{ S5P_PAD_ALV_SEL_SYS,			{ 1, 0, 0 } },
+	{ S5P_XXTI_SYS,				{ 1, 1, 0 } },
+	{ S5P_EXT_REGULATOR_SYS,		{ 1, 1, 0 } },
+	{ S5P_GPIO_MODE_SYS,			{ 1, 0, 0 } },
+	{ S5P_GPIO_MODE_COREBLK_SYS,		{ 1, 0, 0 } },
+	{ S5P_GPIO_MODE_MAUDIO_SYS,		{ 1, 1, 0 } },
+	{ S5P_TOP_ASB_RESET_SYS,		{ 1, 1, 1 } },
+	{ S5P_TOP_ASB_ISOLATION_SYS,		{ 1, 0, 1 } },
+	{ S5P_CAM_SYS,				{ 7, 0, 0 } },
+	{ S5P_TV_SYS,				{ 7, 0, 0 } },
+	{ S5P_MFC_SYS,				{ 7, 0, 0 } },
+	{ S5P_G3D_SYS,				{ 7, 0, 0 } },
+	{ S5P_LCD0_SYS,				{ 7, 0, 0 } },
+	{ S5P_ISP_SYS,				{ 7, 0, 0 } },
+	{ S5P_MAUDIO_SYS,			{ 7, 7, 0 } },
+	{ S5P_GPS_SYS,				{ 7, 0, 0 } },
+	{ S5P_GPS_ALIVE_SYS,			{ 7, 0, 0 } },
+	{ S5P_CMU_SYSCLK_ISP_SYS,		{ 1, 0, 0 } },
+	{ S5P_CMU_SYSCLK_GPS_SYS,		{ 1, 0, 0 } },
+	{ S5P_XUSBXTI_SYS,			{ 1, 1, 0 } },
+};
+
+static struct exynos4_pmu_conf exynos4x12_c2c_pmu_conf[] = {
+	{ S5P_CMU_RESET_COREBLK_SYS,		{ 1, 1, 1 } },
+	{ S5P_MPLLUSER_SYSCLK_SYS,		{ 1, 0, 0 } },
+	{ S5P_TOP_RETENTION_COREBLK_SYS,	{ 1, 0, 0 } },
+	{ S5P_TOP_PWR_COREBLK_SYS,		{ 3, 0, 0 } },
+	{ S5P_LOGIC_RESET_COREBLK_SYS,		{ 1, 1, 1 } },
+	{ S5P_OSCCLK_GATE_COREBLK_SYS,		{ 1, 0, 0 } },
+	{ S5P_PAD_RETENTION_GPIO_COREBLK_SYS,	{ 1, 1, 1 } },
+	{ S5P_TOP_ASB_RESET_SYS,		{ 1, 1, 0 } },
+	{ S5P_TOP_ASB_ISOLATION_SYS,		{ 1, 0, 0 } },
+};
+
+static struct exynos4_pmu_conf exynos4212_c2c_pmu_conf[] = {
+	{ S5P_LPDDR_PHY_DLL_LOCK_SYS,		{ 1, 0, 0 } },
+};
+
+static struct exynos4_c2c_pmu_conf exynos4_config_for_c2c[] = {
+	/* Register Address	       Value */
+	{ S5P_TOP_BUS_COREBLK_SYS,      0x0},
+	{ S5P_TOP_PWR_COREBLK_SYS,      0x0},
+	{ S5P_MPLL_SYSCLK_SYS,          0x0},
+#ifdef CONFIG_MACH_SMDK4212
+	{ S5P_XUSBXTI_SYS,              0x0},
+#endif
+};
+
+void exynos4_pmu_xclkout_set(unsigned int enable, enum xclkout_select source)
+{
+	unsigned int tmp;
+
+	if (enable) {
+		tmp = __raw_readl(S5P_PMU_DEBUG);
+		/* CLKOUT enable */
+		tmp &= ~(0xF << S5P_PMU_CLKOUT_SEL_SHIFT | S5P_CLKOUT_DISABLE);
+		tmp |= (source << S5P_PMU_CLKOUT_SEL_SHIFT);
+		__raw_writel(tmp, S5P_PMU_DEBUG);
+	} else {
+		tmp = __raw_readl(S5P_PMU_DEBUG);
+		tmp |= S5P_CLKOUT_DISABLE; /* CLKOUT disable */
+		__raw_writel(tmp, S5P_PMU_DEBUG);
+	}
+	printk(KERN_DEBUG "pmu_debug: 0x%08x\n", __raw_readl(S5P_PMU_DEBUG));
+}
+EXPORT_SYMBOL_GPL(exynos4_pmu_xclkout_set);
+
+void exynos4_sys_powerdown_xusbxti_control(unsigned int enable)
+{
+	unsigned int count = entry_cnt;
+
+	if (enable)
+		exynos4_pmu_config[count - 1].val[SYS_SLEEP] = 0x1;
+	else
+		exynos4_pmu_config[count - 1].val[SYS_SLEEP] = 0x0;
+
+	printk(KERN_DEBUG "xusbxti_control: %ld\n",
+			exynos4_pmu_config[count - 1].val[SYS_SLEEP]);
+}
+EXPORT_SYMBOL_GPL(exynos4_sys_powerdown_xusbxti_control);
+
+void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
+{
+	unsigned int count = entry_cnt;
+	unsigned int tmp;
+
+	for (; count > 0; count--)
+		__raw_writel(exynos4_pmu_config[count - 1].val[mode],
+				exynos4_pmu_config[count - 1].reg);
+
+	if ((!soc_is_exynos4210()) && (exynos4_is_c2c_use())) {
+		for (count = 0 ; count < ARRAY_SIZE(exynos4x12_c2c_pmu_conf) ; count++)
+			__raw_writel(exynos4x12_c2c_pmu_conf[count].val[mode],
+					exynos4x12_c2c_pmu_conf[count].reg);
+
+		if (soc_is_exynos4212())
+			__raw_writel(exynos4212_c2c_pmu_conf[0].val[mode],
+					exynos4212_c2c_pmu_conf[0].reg);
+
+		for (count = 0 ; count < ARRAY_SIZE(exynos4_config_for_c2c) ; count++) {
+			tmp = __raw_readl(exynos4_config_for_c2c[count].reg);
+			tmp |= exynos4_config_for_c2c[count].val;
+			__raw_writel(tmp, exynos4_config_for_c2c[count].reg);
+		}
+	}
+}
+
+void exynos4_c2c_request_pwr_mode(enum c2c_pwr_mode mode)
+{
+	exynos4_config_for_c2c[0].val = 0x3;
+
+	switch (mode) {
+	/* If C2C mode is MAXIMAL LATENCY */
+	case MAX_LATENCY:
+		exynos4_config_for_c2c[1].val = 0x0;
+		if (soc_is_exynos4412() && (samsung_rev() < EXYNOS4412_REV_1_0))
+			exynos4_config_for_c2c[2].val = 0x1;
+		else
+			exynos4_config_for_c2c[2].val = 0x0;
+#ifdef CONFIG_MACH_SMDK4212
+		exynos4_config_for_c2c[3].val = 0x0;
+#endif
+		break;
+	/* If C2C mode is Minimal or Short LATENCY */
+	default:
+		exynos4_config_for_c2c[1].val = 0x3;
+		exynos4_config_for_c2c[2].val = 0x1;
+#ifdef CONFIG_MACH_SMDK4212
+		exynos4_config_for_c2c[3].val = 0x1;
+#endif
+		break;
+	}
+}
+
+static int __init exynos4_pmu_init(void)
+{
+	unsigned int i;
+
+	if(!soc_is_exynos4210())
+		exynos4_reset_assert_ctrl(1);
+
+	if (soc_is_exynos4210()) {
+		exynos4_pmu_config = exynos4210_pmu_config;
+		entry_cnt = ARRAY_SIZE(exynos4210_pmu_config);
+		printk(KERN_INFO "%s: PMU supports 4210(%d)\n",
+					__func__, entry_cnt);
+	} else if (soc_is_exynos4212()) {
+		exynos4_pmu_config = exynos4212_pmu_config;
+		entry_cnt = ARRAY_SIZE(exynos4212_pmu_config);
+		printk(KERN_INFO "%s: PMU supports 4212(%d)\n",
+					__func__, entry_cnt);
+	} else if (soc_is_exynos4412()) {
+		exynos4_pmu_config = exynos4412_pmu_config;
+		entry_cnt = ARRAY_SIZE(exynos4412_pmu_config);
+		printk(KERN_INFO "%s: PMU supports 4412(%d)\n",
+					__func__, entry_cnt);
+	} else {
+		printk(KERN_INFO "%s: PMU not supported\n", __func__);
+	}
+
+	return 0;
+}
+arch_initcall(exynos4_pmu_init);
diff --git a/arch/arm/mach-exynos/pmu-exynos5.c b/arch/arm/mach-exynos/pmu-exynos5.c
new file mode 100644
index 0000000..27ff96c
--- /dev/null
+++ b/arch/arm/mach-exynos/pmu-exynos5.c
@@ -0,0 +1,298 @@
+/* linux/arch/arm/mach-exynos/pmu-exynos5.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * EXYNOS5 - CPU PMU(Power Management Unit) support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/kernel.h>
+
+#include <mach/regs-clock.h>
+#include <mach/regs-pmu5.h>
+#include <mach/pmu.h>
+
+#include <plat/cpu.h>
+
+static struct exynos4_pmu_conf *exynos5_pmu_config;
+
+static unsigned int entry_cnt;
+
+static struct exynos4_pmu_conf exynos52xx_pmu_config[] = {
+	/* { .reg = address, .val = { AFTR, LPA, SLEEP } */
+	{ EXYNOS5_ARM_CORE0_SYS_PWR_REG,			{ 0x0, 0x0, 0x2} },
+	{ EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_ARM_CORE1_SYS_PWR_REG,			{ 0x0, 0x0, 0x2} },
+	{ EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_FSYS_ARM_SYS_PWR_REG,				{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG,		{ 0x1, 0x1, 0x1} },
+	{ EXYNOS5_ISP_ARM_SYS_PWR_REG,				{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_ARM_COMMON_SYS_PWR_REG,			{ 0x0, 0x0, 0x2} },
+	{ EXYNOS5_ARM_L2_SYS_PWR_REG,				{ 0x0, 0x0, 0x3} },
+	{ EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_CMU_RESET_SYS_PWR_REG,			{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG,			{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG,			{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG,			{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG,			{ 0x1, 0x1, 0x1} },
+	{ EXYNOS5_APLL_SYSCLK_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG,			{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_TOP_BUS_SYS_PWR_REG,				{ 0x3, 0x0, 0x0} },
+	{ EXYNOS5_TOP_RETENTION_SYS_PWR_REG,			{ 0x1, 0x0, 0x1} },
+	{ EXYNOS5_TOP_PWR_SYS_PWR_REG,				{ 0x3, 0x0, 0x3} },
+	{ EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG,			{ 0x3, 0x0, 0x0} },
+	{ EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG,		{ 0x1, 0x0, 0x1} },
+	{ EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG,			{ 0x3, 0x0, 0x3} },
+	{ EXYNOS5_LOGIC_RESET_SYS_PWR_REG,			{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_OSCCLK_GATE_SYS_PWR_REG,			{ 0x1, 0x0, 0x1} },
+	{ EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG,		{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG,		{ 0x1, 0x0, 0x1} },
+	{ EXYNOS5_USBOTG_MEM_SYS_PWR_REG,			{ 0x3, 0x0, 0x0} },
+	{ EXYNOS5_G2D_MEM_SYS_PWR_REG,				{ 0x3, 0x0, 0x0} },
+	{ EXYNOS5_USBDRD_MEM_SYS_PWR_REG,			{ 0x3, 0x0, 0x0} },
+	{ EXYNOS5_SDMMC_MEM_SYS_PWR_REG,			{ 0x3, 0x0, 0x0} },
+	{ EXYNOS5_CSSYS_MEM_SYS_PWR_REG,			{ 0x3, 0x0, 0x0} },
+	{ EXYNOS5_SECSS_MEM_SYS_PWR_REG,			{ 0x3, 0x0, 0x0} },
+	{ EXYNOS5_ROTATOR_MEM_SYS_PWR_REG,			{ 0x3, 0x0, 0x0} },
+	{ EXYNOS5_INTRAM_MEM_SYS_PWR_REG,			{ 0x3, 0x0, 0x0} },
+	{ EXYNOS5_INTROM_MEM_SYS_PWR_REG,			{ 0x3, 0x0, 0x0} },
+	{ EXYNOS5_JPEG_MEM_SYS_PWR_REG,				{ 0x3, 0x0, 0x0} },
+	{ EXYNOS5_HSI_MEM_SYS_PWR_REG,				{ 0x3, 0x0, 0x0} },
+	{ EXYNOS5_MCUIOP_MEM_SYS_PWR_REG,			{ 0x3, 0x0, 0x0} },
+	{ EXYNOS5_SATA_MEM_SYS_PWR_REG,				{ 0x3, 0x0, 0x0} },
+	{ EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG,		{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG,	{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_PAD_ISOLATION_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_EXT_REGULATOR_SYS_PWR_REG,			{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_GPIO_MODE_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG,			{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG,			{ 0x1, 0x1, 0x1} },
+	{ EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG,		{ 0x1, 0x0, 0x1} },
+	{ EXYNOS5_GSCL_SYS_PWR_REG,				{ 0x7, 0x0, 0x0} },
+	{ EXYNOS5_ISP_SYS_PWR_REG,				{ 0x7, 0x0, 0x0} },
+	{ EXYNOS5_MFC_SYS_PWR_REG,				{ 0x7, 0x0, 0x0} },
+	{ EXYNOS5_G3D_SYS_PWR_REG,				{ 0x7, 0x0, 0x0} },
+	{ EXYNOS5_DISP1_SYS_PWR_REG,				{ 0x7, 0x0, 0x0} },
+	{ EXYNOS5_MAU_SYS_PWR_REG,				{ 0x7, 0x7, 0x0} },
+	{ EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG,			{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG,			{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG,			{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_XXTI_SYS_PWR_REG,				{ 0x1, 0x1, 0x0} },
+};
+
+static struct exynos4_pmu_conf exynos52xx_pmu_config_gps[] = {
+	/* { .reg = address, .val = { AFTR, LPA, SLEEP } */
+	{ EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG,			{ 0x1, 0x0, 0x1} },
+	{ EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG,			{ 0x1, 0x0, 0x1} },
+	{ EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG,		{ 0x1, 0x0, 0x1} },
+	{ EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG,		{ 0x1, 0x0, 0x1} },
+	{ EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG,			{ 0x1, 0x1, 0x1} },
+	{ EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG,			{ 0x1, 0x1, 0x1} },
+	{ EXYNOS5_GPS_SYS_PWR_REG,				{ 0x7, 0x0, 0x0} },
+	{ EXYNOS5_CMU_CLKSTOP_GPS_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_CMU_SYSCLK_GPS_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_CMU_RESET_GPS_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_XXTI_SYS_PWR_REG,				{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_ARM_L2_SYS_PWR_REG,				{ 0x3, 0x3, 0x3} },
+};
+
+static struct exynos4_pmu_conf exynos52xx_pmu_c2c_config[] = {
+	/* { .reg = address, .val = { AFTR, LPA, SLEEP } */
+	{ EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG,			{ 0x1, 0x1, 0x1} },
+	{ EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG,			{ 0x3, 0x0, 0x0} },
+	{ EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG,		{ 0x1, 0x1, 0x1} },
+	{ EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG,			{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+};
+
+void __iomem *list_both_cnt_feed[] = {
+	EXYNOS5_ARM_CORE0_OPTION,
+	EXYNOS5_ARM_CORE1_OPTION,
+	EXYNOS5_ARM_COMMON_OPTION,
+	EXYNOS5_GSCL_OPTION,
+	EXYNOS5_ISP_OPTION,
+	EXYNOS5_MFC_OPTION,
+	EXYNOS5_G3D_OPTION,
+	EXYNOS5_DISP1_OPTION,
+	EXYNOS5_MAU_OPTION,
+	EXYNOS5_TOP_PWR_OPTION,
+	EXYNOS5_TOP_PWR_SYSMEM_OPTION,
+};
+
+void __iomem *list_diable_wfi_wfe[] = {
+	EXYNOS5_ARM_CORE1_OPTION,
+	EXYNOS5_FSYS_ARM_OPTION,
+	EXYNOS5_ISP_ARM_OPTION,
+};
+
+static void exynos5_init_pmu(void)
+{
+	unsigned int i;
+	unsigned int tmp;
+
+	/*
+	 * Enable both SC_FEEDBACK and SC_COUNTER
+	 */
+	for (i = 0 ; i < ARRAY_SIZE(list_both_cnt_feed) ; i++) {
+		tmp = __raw_readl(list_both_cnt_feed[i]);
+		tmp |= (EXYNOS5_USE_SC_FEEDBACK |
+			EXYNOS5_USE_SC_COUNTER);
+		__raw_writel(tmp, list_both_cnt_feed[i]);
+	}
+
+	if (samsung_rev() < EXYNOS5250_REV_1_0) {
+		tmp = __raw_readl(EXYNOS5_GPS_OPTION);
+		tmp |= (EXYNOS5_USE_SC_FEEDBACK |
+			EXYNOS5_USE_SC_COUNTER);
+		__raw_writel(tmp, EXYNOS5_GPS_OPTION);
+	}
+
+	/*
+	 * SKIP_DEACTIVATE_ACEACP_IN_PWDN_BITFIELD Enable
+	 * MANUAL_L2RSTDISABLE_CONTROL_BITFIELD Enable
+	 */
+	if (samsung_rev() < EXYNOS5250_REV_1_0) {
+		tmp = __raw_readl(EXYNOS5_ARM_COMMON_OPTION);
+		tmp |= (EXYNOS5_MANUAL_L2RSTDISABLE_CONTROL |
+			EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN);
+		__raw_writel(tmp, EXYNOS5_ARM_COMMON_OPTION);
+	} else {
+		tmp = __raw_readl(EXYNOS5_ARM_COMMON_OPTION);
+		tmp |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
+		__raw_writel(tmp, EXYNOS5_ARM_COMMON_OPTION);
+	}
+
+	/*
+	 * Disable WFI/WFE on XXX_OPTION
+	 */
+	for (i = 0 ; i < ARRAY_SIZE(list_diable_wfi_wfe) ; i++) {
+		tmp = __raw_readl(list_diable_wfi_wfe[i]);
+		tmp &= ~(EXYNOS5_OPTION_USE_STANDBYWFE |
+			 EXYNOS5_OPTION_USE_STANDBYWFI);
+		__raw_writel(tmp, list_diable_wfi_wfe[i]);
+	}
+}
+
+void exynos5_pmu_xclkout_set(unsigned int enable, enum xclkout_select source)
+{
+	unsigned int tmp;
+
+	if (enable) {
+		tmp = __raw_readl(S5P_PMU_DEBUG);
+		/* CLKOUT enable */
+		tmp &= ~ (0xF << S5P_PMU_CLKOUT_SEL_SHIFT | S5P_CLKOUT_DISABLE);
+		tmp |= (source << S5P_PMU_CLKOUT_SEL_SHIFT);
+		__raw_writel(tmp, S5P_PMU_DEBUG);
+	} else {
+		tmp = __raw_readl(S5P_PMU_DEBUG);
+		/* CLKOUT disable */
+		tmp |= S5P_CLKOUT_DISABLE;
+		__raw_writel(tmp, S5P_PMU_DEBUG);
+	}
+
+	printk(KERN_DEBUG "pmu_debug: 0x%08x\n", __raw_readl(S5P_PMU_DEBUG));
+}
+EXPORT_SYMBOL_GPL(exynos5_pmu_xclkout_set);
+
+void exynos5_sys_powerdown_xxti_control(unsigned int enable)
+{
+	unsigned int count = entry_cnt;
+
+	if (enable)
+		exynos5_pmu_config[count - 1].val[SYS_SLEEP] = 0x1;
+	else
+		exynos5_pmu_config[count - 1].val[SYS_SLEEP] = 0x0;
+
+	printk(KERN_DEBUG "xxti_control: %ld\n",
+			exynos5_pmu_config[count - 1].val[SYS_SLEEP]);
+}
+EXPORT_SYMBOL_GPL(exynos5_sys_powerdown_xxti_control);
+
+
+void exynos5_sys_powerdown_conf(enum sys_powerdown mode)
+{
+	unsigned int count = entry_cnt;
+	unsigned int i;
+
+	exynos5_init_pmu();
+
+	for (; count > 0; count--)
+		__raw_writel(exynos5_pmu_config[count - 1].val[mode],
+				exynos5_pmu_config[count - 1].reg);
+
+	if (samsung_rev() < EXYNOS5250_REV_1_0) {
+		for (i = 0; i < ARRAY_SIZE(exynos52xx_pmu_config_gps); i++) {
+			__raw_writel(exynos52xx_pmu_config_gps[i].val[mode],
+					exynos52xx_pmu_config_gps[i].reg);
+		}
+
+	}
+
+	if ((mode != SYS_AFTR) && (exynos4_is_c2c_use())) {
+		pr_info("%s power mode enter with C2C Enabling\n"
+				, (mode == SYS_LPA) ? "LPA" : "SLEEP");
+
+		for (i = 0; i < ARRAY_SIZE(exynos52xx_pmu_c2c_config); i++) {
+			__raw_writel(exynos52xx_pmu_c2c_config[i].val[mode],
+					exynos52xx_pmu_c2c_config[i].reg);
+		}
+	}
+}
+
+static int __init exynos5_pmu_init(void)
+{
+	exynos5_pmu_config = exynos52xx_pmu_config;
+	entry_cnt = ARRAY_SIZE(exynos52xx_pmu_config);
+	printk(KERN_INFO "%s: PMU supports 52XX(%d)\n"
+				, __func__, entry_cnt);
+
+	return 0;
+}
+arch_initcall(exynos5_pmu_init);
diff --git a/arch/arm/mach-exynos/ppc.c b/arch/arm/mach-exynos/ppc.c
new file mode 100644
index 0000000..8c97b1a
--- /dev/null
+++ b/arch/arm/mach-exynos/ppc.c
@@ -0,0 +1,74 @@
+/* linux/arch/arm/mach-exynos/ppc.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * EXYNOS4 - PPMU support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/ppmu.h>
+
+void exynos4_ppc_reset(struct exynos4_ppmu_hw *ppmu)
+{
+	void __iomem *ppmu_base = ppmu->hw_base;
+	int i;
+
+	__raw_writel(0x8000000f, ppmu_base + 0xf010);
+	__raw_writel(0x8000000f, ppmu_base + 0xf050);
+	__raw_writel(0x6, ppmu_base + 0xf000);
+	__raw_writel(0x0, ppmu_base + 0xf100);
+
+	ppmu->ccnt = 0;
+	for (i = 0; i < NUMBER_OF_COUNTER; i++)
+		ppmu->count[i] = 0;
+}
+
+void exynos4_ppc_setevent(struct exynos4_ppmu_hw *ppmu,
+				  unsigned int evt)
+{
+	void __iomem *ppmu_base = ppmu->hw_base;
+
+	ppmu->event[0] = evt;
+
+	__raw_writel(((evt << 12) | 0x1), ppmu_base + 0xfc);
+}
+
+void exynos4_ppc_start(struct exynos4_ppmu_hw *ppmu)
+{
+	void __iomem *ppmu_base = ppmu->hw_base;
+
+	__raw_writel(0x1, ppmu_base + 0xf000);
+}
+
+void exynos4_ppc_stop(struct exynos4_ppmu_hw *ppmu)
+{
+	void __iomem *ppmu_base = ppmu->hw_base;
+
+	__raw_writel(0x0, ppmu_base + 0xf000);
+}
+
+unsigned long long exynos4_ppc_update(struct exynos4_ppmu_hw *ppmu)
+{
+	void __iomem *ppmu_base = ppmu->hw_base;
+	unsigned int i;
+
+	ppmu->ccnt = __raw_readl(ppmu_base + 0xf100);
+
+	for (i = 0; i < NUMBER_OF_COUNTER; i++)
+		ppmu->count[i] =
+			__raw_readl(ppmu_base + (0xf110 + (0x10 * i)));
+
+	return 0;
+}
+
diff --git a/arch/arm/mach-exynos/ppmu.c b/arch/arm/mach-exynos/ppmu.c
new file mode 100644
index 0000000..44d606c
--- /dev/null
+++ b/arch/arm/mach-exynos/ppmu.c
@@ -0,0 +1,194 @@
+/* linux/arch/arm/mach-exynos/ppmu.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * EXYNOS4 - CPU PPMU support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/list.h>
+#include <linux/math64.h>
+#include <linux/device.h>
+
+#include <plat/cpu.h>
+
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/ppmu.h>
+
+static LIST_HEAD(ppmu_list);
+
+unsigned long long ppmu_load[PPMU_END];
+unsigned long long ppmu_load_detail[2][PPMU_END];
+
+void exynos4_ppmu_reset(struct exynos4_ppmu_hw *ppmu)
+{
+	void __iomem *ppmu_base = ppmu->hw_base;
+	int i;
+
+	__raw_writel(0x3 << 1, ppmu_base);
+	__raw_writel(0x8000000f, ppmu_base + PPMU_CNTENS);
+
+	if (soc_is_exynos4210())
+		for (i = 0; i < NUMBER_OF_COUNTER; i++) {
+			__raw_writel(0x0, ppmu_base + DEVT0_ID + (i * DEVT_ID_OFFSET));
+			__raw_writel(0x0, ppmu_base + DEVT0_IDMSK + (i * DEVT_ID_OFFSET));
+		}
+}
+
+void exynos4_ppmu_setevent(struct exynos4_ppmu_hw *ppmu,
+				unsigned int evt_num)
+{
+	void __iomem *ppmu_base = ppmu->hw_base;
+	__raw_writel(ppmu->event[evt_num], ppmu_base + PPMU_BEVT0SEL + (evt_num * PPMU_BEVTSEL_OFFSET));
+}
+
+void exynos4_ppmu_start(struct exynos4_ppmu_hw *ppmu)
+{
+	void __iomem *ppmu_base = ppmu->hw_base;
+	__raw_writel(0x1, ppmu_base);
+}
+
+void exynos4_ppmu_stop(struct exynos4_ppmu_hw *ppmu)
+{
+	void __iomem *ppmu_base = ppmu->hw_base;
+	__raw_writel(0x0, ppmu_base);
+}
+
+unsigned long long exynos4_ppmu_update(struct exynos4_ppmu_hw *ppmu, int ch)
+{
+	void __iomem *ppmu_base = ppmu->hw_base;
+	unsigned long long total = 0;
+
+	ppmu->ccnt = __raw_readl(ppmu_base + PPMU_CCNT);
+
+	if (ppmu->ccnt == 0)
+		ppmu->ccnt = MAX_CCNT;
+
+	if (ch >= NUMBER_OF_COUNTER || ppmu->event[ch] == 0)
+		return 0;
+
+	if (ch == 3 && !soc_is_exynos4210())
+		total = (((u64)__raw_readl(ppmu_base + PMCNT_OFFSET(ch)) << 8) |
+				__raw_readl(ppmu_base + PMCNT_OFFSET(ch + 1)));
+	else
+		total = __raw_readl(ppmu_base + PMCNT_OFFSET(ch));
+
+	if (total > ppmu->ccnt)
+		total = ppmu->ccnt;
+
+	ppmu_load_detail[0][ppmu->id] = total * ppmu->weight;
+	ppmu_load_detail[1][ppmu->id] = ppmu->ccnt;
+	return div64_u64((total * ppmu->weight * 100), ppmu->ccnt);
+}
+
+void ppmu_start(struct device *dev)
+{
+	struct exynos4_ppmu_hw *ppmu;
+
+	list_for_each_entry(ppmu, &ppmu_list, node)
+		if (ppmu->dev == dev)
+			exynos4_ppmu_start(ppmu);
+}
+
+void ppmu_update(struct device *dev, int ch)
+{
+	struct exynos4_ppmu_hw *ppmu;
+
+	list_for_each_entry(ppmu, &ppmu_list, node)
+		if (ppmu->dev == dev) {
+			exynos4_ppmu_stop(ppmu);
+			ppmu_load[ppmu->id] = exynos4_ppmu_update(ppmu, ch);
+			exynos4_ppmu_reset(ppmu);
+		}
+}
+
+void ppmu_reset(struct device *dev)
+{
+	struct exynos4_ppmu_hw *ppmu;
+	int i;
+
+	list_for_each_entry(ppmu, &ppmu_list, node) {
+		if (ppmu->dev == dev) {
+			exynos4_ppmu_stop(ppmu);
+			for (i = 0; i < NUMBER_OF_COUNTER; i++)
+				if (ppmu->event[i] != 0)
+					exynos4_ppmu_setevent(ppmu, i);
+			exynos4_ppmu_reset(ppmu);
+		}
+	}
+}
+
+void ppmu_init(struct exynos4_ppmu_hw *ppmu, struct device *dev)
+{
+	void __iomem *ppmu_base = ppmu->hw_base;
+	int i;
+
+	ppmu->dev = dev;
+	list_add(&ppmu->node, &ppmu_list);
+
+	if (soc_is_exynos4210())
+		for (i = 0; i < NUMBER_OF_COUNTER; i++) {
+			__raw_writel(0x0, ppmu_base + DEVT0_ID + (i * DEVT_ID_OFFSET));
+			__raw_writel(0x0, ppmu_base + DEVT0_IDMSK + (i * DEVT_ID_OFFSET));
+		}
+
+	for (i = 0; i < NUMBER_OF_COUNTER; i++)
+		if (ppmu->event[i] != 0)
+			exynos4_ppmu_setevent(ppmu, i);
+}
+
+struct exynos4_ppmu_hw exynos_ppmu[] = {
+	[PPMU_DMC0] = {
+		.id = PPMU_DMC0,
+		.hw_base = S5P_VA_PPMU_DMC0,
+		.event[3] = RDWR_DATA_COUNT,
+		.weight = DEFAULT_WEIGHT,
+	},
+	[PPMU_DMC1] = {
+		.id = PPMU_DMC1,
+		.hw_base = S5P_VA_PPMU_DMC1,
+		.event[3] = RDWR_DATA_COUNT,
+		.weight = DEFAULT_WEIGHT,
+	},
+	[PPMU_CPU] = {
+		.id = PPMU_CPU,
+		.hw_base = S5P_VA_PPMU_CPU,
+		.event[3] = RDWR_DATA_COUNT,
+		.weight = DEFAULT_WEIGHT,
+	},
+#ifdef CONFIG_ARCH_EXYNOS5
+	[PPMU_DDR_C] = {
+		.id = PPMU_DDR_C,
+		.hw_base = S5P_VA_PPMU_DDR_C,
+		.event[3] = RDWR_DATA_COUNT,
+		.weight = DEFAULT_WEIGHT,
+	},
+	[PPMU_DDR_R1] = {
+		.id = PPMU_DDR_R1,
+		.hw_base = S5P_VA_PPMU_DDR_R1,
+		.event[3] = RDWR_DATA_COUNT,
+		.weight = DEFAULT_WEIGHT,
+	},
+	[PPMU_DDR_L] = {
+		.id = PPMU_DDR_L,
+		.hw_base = S5P_VA_PPMU_DDR_L,
+		.event[3] = RDWR_DATA_COUNT,
+		.weight = DEFAULT_WEIGHT,
+	},
+	[PPMU_RIGHT0_BUS] = {
+		.id = PPMU_RIGHT0_BUS,
+		.hw_base = S5P_VA_PPMU_RIGHT0_BUS,
+		.event[3] = RDWR_DATA_COUNT,
+		.weight = DEFAULT_WEIGHT,
+	},
+#endif
+};
diff --git a/arch/arm/mach-exynos/px-switch.c b/arch/arm/mach-exynos/px-switch.c
new file mode 100644
index 0000000..90772ed
--- /dev/null
+++ b/arch/arm/mach-exynos/px-switch.c
@@ -0,0 +1,435 @@
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/semaphore.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+#include <plat/gpio-cfg.h>
+#include <mach/gpio.h>
+#include <mach/usb_switch.h>
+
+struct device *sec_switch_dev;
+
+enum usb_path_t current_path = USB_PATH_NONE;
+
+static struct semaphore usb_switch_sem;
+
+static bool usb_connected;
+
+static ssize_t show_usb_sel(struct device *dev,
+			    struct device_attribute *attr, char *buf)
+{
+	const char *mode;
+
+	if (current_path & USB_PATH_CP) {
+		/* CP */
+		mode = "MODEM";
+	} else {
+		/* AP */
+		mode = "PDA";
+	}
+
+	pr_info("%s: %s\n", __func__, mode);
+
+	return sprintf(buf, "%s\n", mode);
+}
+
+static ssize_t store_usb_sel(struct device *dev,
+			     struct device_attribute *attr,
+			     const char *buf, size_t count)
+{
+	pr_info("%s: %s\n", __func__, buf);
+
+	if (!strncasecmp(buf, "PDA", 3)) {
+		usb_switch_lock();
+		usb_switch_clr_path(USB_PATH_CP);
+		usb_switch_unlock();
+	} else if (!strncasecmp(buf, "MODEM", 5)) {
+		usb_switch_lock();
+		usb_switch_set_path(USB_PATH_CP);
+		usb_switch_unlock();
+	} else {
+		pr_err("%s: wrong usb_sel value(%s)!!\n", __func__, buf);
+		return -EINVAL;
+	}
+
+	return count;
+}
+
+static ssize_t show_uart_sel(struct device *dev,
+			     struct device_attribute *attr, char *buf)
+{
+	int val_sel;
+	const char *mode;
+
+	val_sel = gpio_get_value(GPIO_UART_SEL);
+
+	if (val_sel == 0) {
+		/* CP */
+		mode = "CP";
+	} else {
+		/* AP */
+		mode = "AP";
+	}
+
+	pr_info("%s: %s\n", __func__, mode);
+
+	return sprintf(buf, "%s\n", mode);
+}
+
+static ssize_t store_uart_sel(struct device *dev,
+			      struct device_attribute *attr,
+			      const char *buf, size_t count)
+{
+	int uart_sel = -1;
+
+	pr_info("%s: %s\n", __func__, buf);
+
+	if (!strncasecmp(buf, "AP", 2)) {
+		uart_sel = 1;
+	} else if (!strncasecmp(buf, "CP", 2)) {
+		uart_sel = 0;
+	} else {
+		pr_err("%s: wrong uart_sel value(%s)!!\n", __func__, buf);
+		return -EINVAL;
+	}
+
+	/* 1 for AP, 0 for CP */
+	gpio_set_value(GPIO_UART_SEL, uart_sel);
+
+	return count;
+}
+
+static ssize_t show_usb_state(struct device *dev,
+			     struct device_attribute *attr, char *buf)
+{
+	const char *state;
+
+	if (usb_connected)
+		state = "USB_STATE_CONFIGURED";
+	else
+		state = "USB_STATE_NOTCONFIGURED";
+
+	pr_info("%s: %s\n", __func__, state);
+
+	return sprintf(buf, "%s\n", state);
+}
+
+static DEVICE_ATTR(usb_sel, 0664, show_usb_sel, store_usb_sel);
+static DEVICE_ATTR(uart_sel, 0664, show_uart_sel, store_uart_sel);
+static DEVICE_ATTR(usb_state, S_IRUGO, show_usb_state, NULL);
+
+static struct attribute *px_switch_attributes[] = {
+	&dev_attr_usb_sel.attr,
+	&dev_attr_uart_sel.attr,
+	&dev_attr_usb_state.attr,
+	NULL
+};
+
+static const struct attribute_group px_switch_group = {
+	.attrs = px_switch_attributes,
+};
+
+void set_usb_connection_state(bool connected)
+{
+	pr_info("%s: set %s\n", __func__, (connected ? "True" : "False"));
+
+	if (usb_connected != connected) {
+		usb_connected = connected;
+
+		pr_info("%s: send \"usb_state\" sysfs_notify\n", __func__);
+		sysfs_notify(&sec_switch_dev->kobj, NULL, "usb_state");
+	}
+}
+
+static void pmic_safeout2(int onoff)
+{
+#if !defined(CONFIG_MACH_P4NOTE)
+	struct regulator *regulator;
+
+	regulator = regulator_get(NULL, "safeout2");
+	BUG_ON(IS_ERR_OR_NULL(regulator));
+
+	if (onoff) {
+		if (!regulator_is_enabled(regulator)) {
+			regulator_enable(regulator);
+		} else {
+			pr_info("%s: onoff:%d No change in safeout2\n",
+			       __func__, onoff);
+		}
+	} else {
+		if (regulator_is_enabled(regulator)) {
+			regulator_force_disable(regulator);
+		} else {
+			pr_info("%s: onoff:%d No change in safeout2\n",
+			       __func__, onoff);
+		}
+	}
+
+	regulator_put(regulator);
+#else
+	if (onoff) {
+		if (!gpio_get_value(GPIO_USB_SEL_CP)) {
+			gpio_set_value(GPIO_USB_SEL_CP, onoff);
+		} else {
+			pr_info("%s: onoff:%d No change in safeout2\n",
+			       __func__, onoff);
+		}
+	} else {
+		if (gpio_get_value(GPIO_USB_SEL_CP)) {
+			gpio_set_value(GPIO_USB_SEL_CP, onoff);
+		} else {
+			pr_info("%s: onoff:%d No change in safeout2\n",
+			       __func__, onoff);
+		}
+	}
+#endif
+}
+
+static void usb_apply_path(enum usb_path_t path)
+{
+#if defined(CONFIG_MACH_P4NOTE)
+	pr_info("%s: current gpio before changing : sel0:%d sel1:%d sel_cp:%d\n",
+	       __func__, gpio_get_value(GPIO_USB_SEL0),
+	       gpio_get_value(GPIO_USB_SEL1), gpio_get_value(GPIO_USB_SEL_CP));
+	pr_info("%s: target path %x\n", __func__, path);
+#else
+	pr_info("%s: current gpio before changing : sel1:%d sel2:%d sel3:%d\n",
+	       __func__, gpio_get_value(GPIO_USB_SEL1),
+	       gpio_get_value(GPIO_USB_SEL2), gpio_get_value(GPIO_USB_SEL3));
+	pr_info("%s: target path %x\n", __func__, path);
+#endif
+
+	/* following checks are ordered according to priority */
+	if (path & USB_PATH_ADCCHECK) {
+#if defined(CONFIG_MACH_P4NOTE)
+		gpio_set_value(GPIO_USB_SEL0, 1);
+		gpio_set_value(GPIO_USB_SEL1, 0);
+#else
+		gpio_set_value(GPIO_USB_SEL1, 0);
+		gpio_set_value(GPIO_USB_SEL2, 1);
+		gpio_set_value(GPIO_USB_SEL3, 1);
+#endif
+		goto out_nochange;
+	}
+	if (path & USB_PATH_CP) {
+		pr_info("DEBUG: set USB path to CP\n");
+#if defined(CONFIG_MACH_P4NOTE)
+		gpio_set_value(GPIO_USB_SEL0, 0);
+		gpio_set_value(GPIO_USB_SEL1, 1);
+#else
+		gpio_set_value(GPIO_USB_SEL1, 0);
+		gpio_set_value(GPIO_USB_SEL2, 0);
+		gpio_set_value(GPIO_USB_SEL3, 1);
+#endif
+		mdelay(3);
+		goto out_cp;
+	}
+#if defined(CONFIG_MACH_P4NOTE)
+	if (path & USB_PATH_AP) {
+		gpio_set_value(GPIO_USB_SEL0, 1);
+		gpio_set_value(GPIO_USB_SEL1, 1);
+		goto out_ap;
+	}
+#else
+	if (path & USB_PATH_OTG) {
+		gpio_set_value(GPIO_USB_SEL1, 1);
+		/* don't care SEL2 */
+		gpio_set_value(GPIO_USB_SEL3, 1);
+		goto out_ap;
+	}
+	if (path & USB_PATH_HOST) {
+#ifndef CONFIG_MACH_P8LTE
+		gpio_set_value(GPIO_USB_SEL1, 1);
+#endif
+		/* don't care SEL2 */
+		gpio_set_value(GPIO_USB_SEL3, 0);
+		goto out_ap;
+	}
+#endif
+
+	/* default */
+#if defined(CONFIG_MACH_P4NOTE)
+	gpio_set_value(GPIO_USB_SEL0, 1);
+	gpio_set_value(GPIO_USB_SEL1, 1);
+#else
+	gpio_set_value(GPIO_USB_SEL1, 1);
+#ifdef CONFIG_MACH_P8LTE
+	gpio_set_value(GPIO_USB_SEL2, 1);
+#else
+	gpio_set_value(GPIO_USB_SEL2, 0);
+#endif
+	gpio_set_value(GPIO_USB_SEL3, 1);
+#endif
+
+out_ap:
+	pr_info("%s: %x safeout2 off\n", __func__, path);
+	pmic_safeout2(0);
+	goto sysfs_noti;
+
+out_cp:
+	pr_info("%s: %x safeout2 on\n", __func__, path);
+	pmic_safeout2(1);
+	goto sysfs_noti;
+
+out_nochange:
+	pr_info("%s: %x safeout2 no change\n", __func__, path);
+	return;
+
+sysfs_noti:
+	pr_info("%s: send \"usb_sel\" sysfs_notify\n", __func__);
+	sysfs_notify(&sec_switch_dev->kobj, NULL, "usb_sel");
+	return;
+}
+
+/*
+  Typical usage of usb switch:
+
+  usb_switch_lock();  (alternatively from hard/soft irq context)
+  ( or usb_switch_trylock() )
+  ...
+  usb_switch_set_path(USB_PATH_ADCCHECK);
+  ...
+  usb_switch_set_path(USB_PATH_TA);
+  ...
+  usb_switch_unlock(); (this restores previous usb switch settings)
+*/
+void usb_switch_set_path(enum usb_path_t path)
+{
+	pr_info("%s: %x current_path before changing\n",
+		__func__, current_path);
+
+	current_path |= path;
+	usb_apply_path(current_path);
+}
+
+void usb_switch_clr_path(enum usb_path_t path)
+{
+	pr_info("%s: %x current_path before changing\n",
+		__func__, current_path);
+
+	current_path &= ~path;
+	usb_apply_path(current_path);
+}
+
+int usb_switch_lock(void)
+{
+	return down_interruptible(&usb_switch_sem);
+}
+
+int usb_switch_trylock(void)
+{
+	return down_trylock(&usb_switch_sem);
+}
+
+void usb_switch_unlock(void)
+{
+	up(&usb_switch_sem);
+}
+
+#ifdef CONFIG_MACH_P4NOTE
+static void init_gpio(void)
+{
+	s3c_gpio_cfgpin(GPIO_USB_SEL0, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_USB_SEL0, S3C_GPIO_PULL_NONE);
+
+	s3c_gpio_cfgpin(GPIO_USB_SEL1, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_USB_SEL1, S3C_GPIO_PULL_NONE);
+
+	s3c_gpio_cfgpin(GPIO_USB_SEL_CP, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_USB_SEL_CP, S3C_GPIO_PULL_NONE);
+
+	s3c_gpio_cfgpin(GPIO_UART_SEL, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_UART_SEL, S3C_GPIO_PULL_NONE);
+}
+#endif
+
+static int __init usb_switch_init(void)
+{
+	int ret;
+
+#if defined(CONFIG_MACH_P4NOTE)
+	gpio_request(GPIO_USB_SEL0, "GPIO_USB_SEL0");
+	gpio_request(GPIO_USB_SEL1, "GPIO_USB_SEL1");
+	gpio_request(GPIO_USB_SEL_CP, "GPIO_USB_SEL_CP");
+	gpio_request(GPIO_UART_SEL, "GPIO_UART_SEL");
+#else
+	gpio_request(GPIO_USB_SEL1, "GPIO_USB_SEL1");
+	gpio_request(GPIO_USB_SEL2, "GPIO_USB_SEL2");
+	gpio_request(GPIO_USB_SEL3, "GPIO_USB_SEL3");
+#ifdef CONFIG_MACH_P8LTE
+	gpio_request(GPIO_UART_SEL1, "GPIO_UART_SEL1");
+	gpio_request(GPIO_UART_SEL2, "GPIO_UART_SEL2");
+#else
+	gpio_request(GPIO_UART_SEL, "GPIO_UART_SEL");
+#endif
+#endif
+
+#if defined(CONFIG_MACH_P4NOTE)
+	gpio_export(GPIO_USB_SEL0, 1);
+	gpio_export(GPIO_USB_SEL1, 1);
+	gpio_export(GPIO_USB_SEL_CP, 1);
+	gpio_export(GPIO_UART_SEL, 1);
+#else
+	gpio_export(GPIO_USB_SEL1, 1);
+	gpio_export(GPIO_USB_SEL2, 1);
+	gpio_export(GPIO_USB_SEL3, 1);
+#ifdef CONFIG_MACH_P8LTE
+	gpio_export(GPIO_UART_SEL1, 1);
+	gpio_export(GPIO_UART_SEL2, 1);
+#else
+	gpio_export(GPIO_UART_SEL, 1);
+#endif
+#endif
+
+	BUG_ON(!sec_class);
+	sec_switch_dev = device_create(sec_class, NULL, 0, NULL, "switch");
+
+	BUG_ON(!sec_switch_dev);
+#if defined(CONFIG_MACH_P4NOTE)
+	gpio_export_link(sec_switch_dev, "GPIO_USB_SEL0", GPIO_USB_SEL0);
+	gpio_export_link(sec_switch_dev, "GPIO_USB_SEL1", GPIO_USB_SEL1);
+	gpio_export_link(sec_switch_dev, "GPIO_USB_SEL_CP", GPIO_USB_SEL_CP);
+	gpio_export_link(sec_switch_dev, "GPIO_UART_SEL", GPIO_UART_SEL);
+#else
+	gpio_export_link(sec_switch_dev, "GPIO_USB_SEL1", GPIO_USB_SEL1);
+	gpio_export_link(sec_switch_dev, "GPIO_USB_SEL2", GPIO_USB_SEL2);
+	gpio_export_link(sec_switch_dev, "GPIO_USB_SEL3", GPIO_USB_SEL3);
+#ifdef CONFIG_MACH_P8LTE
+	gpio_export_link(sec_switch_dev, "GPIO_UART_SEL1", GPIO_UART_SEL1);
+	gpio_export_link(sec_switch_dev, "GPIO_UART_SEL2", GPIO_UART_SEL2);
+#else
+	gpio_export_link(sec_switch_dev, "GPIO_UART_SEL", GPIO_UART_SEL);
+#endif
+#endif
+
+	/*init_MUTEX(&usb_switch_sem);*/
+	sema_init(&usb_switch_sem, 1);
+
+#ifdef CONFIG_MACH_P4NOTE
+	init_gpio();
+#endif
+
+#if !defined(CONFIG_MACH_P4NOTE)
+	if (!gpio_get_value(GPIO_USB_SEL1)) {
+#else
+	if ((!gpio_get_value(GPIO_USB_SEL0)) && (gpio_get_value(GPIO_USB_SEL1))) {
+#endif
+		usb_switch_lock();
+		usb_switch_set_path(USB_PATH_CP);
+		usb_switch_unlock();
+	}
+
+	/* create sysfs group */
+	ret = sysfs_create_group(&sec_switch_dev->kobj, &px_switch_group);
+	if (ret) {
+		pr_err("failed to create px switch attribute group\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+device_initcall(usb_switch_init);
diff --git a/arch/arm/mach-exynos/px.h b/arch/arm/mach-exynos/px.h
new file mode 100644
index 0000000..19cc144
--- /dev/null
+++ b/arch/arm/mach-exynos/px.h
@@ -0,0 +1,24 @@
+/*
+ * arch/arm/mach-exynos/px.h
+ */
+
+#ifndef __PX_H__
+#define __PX_H__
+
+extern int s3c_gpio_slp_cfgpin(unsigned int pin, unsigned int config);
+extern int s3c_gpio_slp_setpull_updown(unsigned int pin, unsigned int config);
+#if defined(CONFIG_MACH_P2)
+extern void p2_config_gpio_table(void);
+extern void p2_config_sleep_gpio_table(void);
+#elif defined(CONFIG_MACH_P8)
+extern void p8_config_gpio_table(void);
+extern void p8_config_sleep_gpio_table(void);
+#else /* CONFIG_MACH_P4) */
+extern void p4_config_gpio_table(void);
+extern void p4_config_sleep_gpio_table(void);
+#endif
+
+extern int brcm_wlan_init(void);
+extern void set_gps_uart_op(int onoff);
+
+#endif
diff --git a/arch/arm/mach-exynos/px_thermistor.h b/arch/arm/mach-exynos/px_thermistor.h
new file mode 100644
index 0000000..d3c7412
--- /dev/null
+++ b/arch/arm/mach-exynos/px_thermistor.h
@@ -0,0 +1,204 @@
+/*
+ * arch/arm/mach-s5pv310/px_thermistor.h
+ */
+
+#ifndef __PX_THERMISTOR_H__
+#define __PX_THERMISTOR_H__
+
+#if defined(CONFIG_MACH_P2)
+/* temperature table for ADC CH 7 */
+struct sec_therm_adc_table adc_temp_table[] = {
+	{  240,  700 },
+	{  291,  650 },
+	{  346,  600 },
+	{  405,  550 },
+	{  473,  500 },
+	{  492,  490 },
+	{  507,  480 },
+	{  526,  470 },
+	{  537,  460 },
+	{  555,  450 },
+	{  577,  440 },
+	{  595,  430 },
+	{  612,  420 },
+	{  631,  410 },
+	{  650,  400 },
+	{  746,  350 },
+	{  843,  300 },
+};
+#elif defined(CONFIG_MACH_P8)
+/* temperature table for ADC CH 7 */
+struct sec_therm_adc_table adc_temp_table[] = {
+	{  289,  700 },
+	{  332,  650 },
+	{  395,  600 },
+	{  459,  550 },
+	{  531,  500 },
+	{  537,  490 },
+	{  562,  480 },
+	{  579,  470 },
+	{  599,  460 },
+	{  615,  450 },
+	{  630,  440 },
+	{  651,  430 },
+	{  668,  420 },
+	{  685,  410 },
+	{  706,  400 },
+	{  793,  350 },
+	{  915,  300 },
+};
+#elif defined(CONFIG_MACH_P8LTE)
+/* temperature table for ADC CH 7 */
+struct sec_therm_adc_table adc_temp_table[] = {
+	{  203,  700 },
+	{  245,  650 },
+	{  295,  600 },
+	{  355,  550 },
+	{  418,  500 },
+	{  436,  490 },
+	{  451,  480 },
+	{  470,  470 },
+	{  485,  460 },
+	{  510,  450 },
+	{  526,  440 },
+	{  546,  430 },
+	{  560,  420 },
+	{  581,  410 },
+	{  596,  400 },
+	{  693,  350 },
+	{  710,  340 },
+	{  734,  330 },
+	{  750,  320 },
+	{  770,  310 },
+	{  792,  300 },
+};
+#elif defined(CONFIG_MACH_P4NOTE)
+/* temperature table for ADC CH 7 */
+struct sec_therm_adc_table adc_temp_table[] = {
+	{  276,  700 },
+	{  321,  650 },
+	{  394,  600 },
+	{  437,  550 },
+	{  505,  500 },
+	{  531,  490 },
+	{  534,  480 },
+	{  549,  470 },
+	{  573,  460 },
+	{  588,  450 },
+	{  610,  440 },
+	{  627,  430 },
+	{  650,  420 },
+	{  663,  410 },
+	{  687,  400 },
+	{  788,  350 },
+	{  903,  300 },
+};
+#else /* end of P2 */
+/* temperature table for ADC CH 7 */
+struct sec_therm_adc_table adc_temp_table[] = {
+	/* ADC, Temperature */
+	{  165,  800 },
+	{  173,  790 },
+	{  179,  780 },
+	{  185,  770 },
+	{  191,  760 },
+	{  197,  750 },
+	{  203,  740 },
+	{  209,  730 },
+	{  215,  720 },
+	{  221,  710 },
+	{  227,  700 },
+	{  236,  690 },
+	{  247,  680 },
+	{  258,  670 },
+	{  269,  660 },
+	{  281,  650 },
+	{  296,  640 },
+	{  311,  630 },
+	{  326,  620 },
+	{  341,  610 },
+	{  356,  600 },
+	{  372,  590 },
+	{  386,  580 },
+	{  400,  570 },
+	{  414,  560 },
+	{  428,  550 },
+	{  442,  540 },
+	{  456,  530 },
+	{  470,  520 },
+	{  484,  510 },
+	{  498,  500 },
+	{  508,  490 },
+	{  517,  480 },
+	{  526,  470 },
+	{  535,  460 },
+	{  544,  450 },
+	{  553,  440 },
+	{  562,  430 },
+	{  576,  420 },
+	{  594,  410 },
+	{  612,  400 },
+	{  630,  390 },
+	{  648,  380 },
+	{  666,  370 },
+	{  684,  360 },
+	{  702,  350 },
+	{  725,  340 },
+	{  749,  330 },
+	{  773,  320 },
+	{  797,  310 },
+	{  821,  300 },
+	{  847,  290 },
+	{  870,  280 },
+	{  893,  270 },
+	{  916,  260 },
+	{  939,  250 },
+	{  962,  240 },
+	{  985,  230 },
+	{ 1008,  220 },
+	{ 1031,  210 },
+	{ 1054,  200 },
+	{ 1081,  190 },
+	{ 1111,  180 },
+	{ 1141,  170 },
+	{ 1171,  160 },
+	{ 1201,  150 },
+	{ 1231,  140 },
+	{ 1261,  130 },
+	{ 1291,  120 },
+	{ 1321,  110 },
+	{ 1351,  100 },
+	{ 1358,   90 },
+	{ 1364,   80 },
+	{ 1370,   70 },
+	{ 1376,   60 },
+	{ 1382,   50 },
+	{ 1402,   40 },
+	{ 1422,   30 },
+	{ 1442,   20 },
+	{ 1462,   10 },
+	{ 1482,    0 },
+	{ 1519,  -10 },
+	{ 1528,  -20 },
+	{ 1546,  -30 },
+	{ 1563,  -40 },
+	{ 1587,  -50 },
+	{ 1601,  -60 },
+	{ 1614,  -70 },
+	{ 1625,  -80 },
+	{ 1641,  -90 },
+	{ 1663,  -100 },
+	{ 1680,  -110 },
+	{ 1695,  -120 },
+	{ 1710,  -130 },
+	{ 1725,  -140 },
+	{ 1740,  -150 },
+	{ 1755,  -160 },
+	{ 1770,  -170 },
+	{ 1785,  -180 },
+	{ 1800,  -190 },
+	{ 1815,  -200 },
+};
+#endif
+
+#endif /* __PX_THERMISTOR_H__ */
diff --git a/arch/arm/mach-exynos/q1-gpio.c b/arch/arm/mach-exynos/q1-gpio.c
new file mode 100644
index 0000000..829dfc1
--- /dev/null
+++ b/arch/arm/mach-exynos/q1-gpio.c
@@ -0,0 +1,441 @@
+#include <linux/gpio.h>
+#include <linux/serial_core.h>
+#include <plat/devs.h>
+#include <plat/gpio-cfg.h>
+#include <plat/regs-serial.h>
+#include <mach/gpio.h>
+#include "u1.h"
+
+struct gpio_init_data {
+	uint num;
+	uint cfg;
+	uint val;
+	uint pud;
+	uint drv;
+};
+
+static struct gpio_init_data q1_init_gpios[] = {
+	{EXYNOS4_GPC1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* CODEC_SDA_1.8V */
+	{EXYNOS4_GPC1(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* CODEC_SCL_1.8V */
+	{EXYNOS4_GPD0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* MHL_SDA_2.8V */
+	{EXYNOS4_GPD0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* MHL_SCL_2.8V */
+	{EXYNOS4_GPD1(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* 8M_CAM_SDA_2.8V */
+	{EXYNOS4_GPD1(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* 8M_CAM_SCL_2.8V */
+	{EXYNOS4_GPD1(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* SENSE_SDA_2.8V */
+	{EXYNOS4_GPD1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* SENSE_SCL_2.8V */
+	{EXYNOS4210_GPJ1(3), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV2}, /* CAM_MCLK */
+	{EXYNOS4_GPK1(1), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPK2(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* PS_ALS_SDA_2.8V */
+	{EXYNOS4_GPK3(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_CMD */
+	{EXYNOS4_GPK3(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* PS_ALS_SCL_2.8V */
+	{EXYNOS4_GPK3(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(0) */
+	{EXYNOS4_GPK3(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(1) */
+	{EXYNOS4_GPK3(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(2) */
+	{EXYNOS4_GPK3(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(3) */
+	{EXYNOS4_GPL2(4), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* MOTOR_EN */
+	{EXYNOS4_GPX0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* VOL_UP */
+	{EXYNOS4_GPX0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* VOL_DOWN */
+	{EXYNOS4_GPX0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* GPIO_BOOT_MODE */
+	{EXYNOS4_GPX1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPX1(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPX2(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* GPIO_FUEL_ALERT */
+	{EXYNOS4_GPX3(1), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPX3(2), S3C_GPIO_SFN(GPIO_DET_35_AF), S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* GPIO_DET_35 */
+	{EXYNOS4_GPX3(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPX3(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY0(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY0(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY0(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY1(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY1(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY1(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY2(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY2(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1,},
+	{EXYNOS4_GPY2(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY2(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY2(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY2(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY3(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY4(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY4(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY5(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY5(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY5(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY5(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY5(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY5(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY5(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY5(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY6(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY6(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY6(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY6(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY6(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY6(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY6(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY6(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+};
+
+/* this table only for q1 board */
+static unsigned int q1_sleep_gpio_table[][3] = {
+	{EXYNOS4_GPA0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+	{EXYNOS4_GPA0(1), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(3), S3C_GPIO_SLP_OUT1,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPA0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPA1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA1(1), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA1(2), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA1(3), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA1(5), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPB(0), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPB(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPB(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPB(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPC0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPC0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPC0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPC0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPC0(4), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPC1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+#if defined(CONFIG_SEC_MODEM_M0_TD)
+	{EXYNOS4_GPC1(1), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4_GPC1(1), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+#endif
+	{EXYNOS4_GPC1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPC1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPC1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPD0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPD0(1), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPD0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPD0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPD1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPD1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPD1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPD1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4210_GPE0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE0(1), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPE0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE0(3), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE0(4), S3C_GPIO_SLP_OUT1,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4210_GPE1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE1(4), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE1(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE1(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4210_GPE2(0), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE2(1), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE2(2), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE2(4), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE2(5), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4210_GPE3(0), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPE3(1), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPE3(2), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPE3(3), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPE3(4), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPE3(5), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPE3(6), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPE3(7), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4210_GPE4(0), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPE4(1), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPE4(2), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPE4(3), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPE4(4), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPE4(5), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPE4(6), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4210_GPE4(7), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPF0(0), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPF0(1), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPF0(2), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPF0(3), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPF0(4), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPF0(5), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPF0(6), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPF0(7), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPF1(0), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPF1(1), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPF1(2), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPF1(3), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPF1(4), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPF1(5), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPF1(6), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPF1(7), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPF2(0), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPF2(1), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPF2(2), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPF2(3), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPF2(4), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPF2(5), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPF2(6), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPF2(7), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPF3(0), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPF3(1), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPF3(2), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPF3(3), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPF3(4), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4210_GPJ0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPJ0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPJ0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPJ0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPJ0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPJ0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPJ0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPJ0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4210_GPJ1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPJ1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPJ1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPJ1(3), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPJ1(4), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPK0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPK1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK1(1), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK1(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPK2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPK3(0), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPL0(0), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL0(1), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPL0(3), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL0(4), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL0(5), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL0(6), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL0(7), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPL1(0), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPL1(2), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPL2(0), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL2(1), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL2(2), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPL2(4), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL2(6), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL2(7), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPY0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPY0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPY1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPY2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPY3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(1), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(3), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY3(5), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(6), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(7), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPY4(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(2), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(3), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY4(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY4(5), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(6), S3C_GPIO_SLP_OUT1,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(7), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPY5(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPY6(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY6(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY6(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY6(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY6(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY6(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY6(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY6(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPZ(0), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPZ(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPZ(2), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPZ(3), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPZ(4), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPZ(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPZ(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+};
+
+void u1_config_gpio_table(void)
+{
+	u32 i, gpio;
+
+	for (i = 0; i < ARRAY_SIZE(q1_init_gpios); i++) {
+		gpio = q1_init_gpios[i].num;
+		s3c_gpio_cfgpin(gpio, q1_init_gpios[i].cfg);
+		s3c_gpio_setpull(gpio, q1_init_gpios[i].pud);
+
+		if (q1_init_gpios[i].val != S3C_GPIO_SETPIN_NONE)
+			gpio_set_value(gpio, q1_init_gpios[i].val);
+
+		s5p_gpio_set_drvstr(gpio, q1_init_gpios[i].drv);
+	}
+}
+
+static void config_sleep_gpio_table(int array_size,
+				    unsigned int (*gpio_table)[3])
+{
+	u32 i, gpio;
+
+	for (i = 0; i < array_size; i++) {
+		gpio = gpio_table[i][0];
+		s3c_gpio_slp_cfgpin(gpio, gpio_table[i][1]);
+		s3c_gpio_slp_setpull_updown(gpio, gpio_table[i][2]);
+	}
+
+	/* GPX GPIO setting */
+	s3c_gpio_cfgpin(EXYNOS4_GPX1(7), S3C_GPIO_INPUT);
+	s3c_gpio_setpull(EXYNOS4_GPX1(7), S3C_GPIO_PULL_DOWN);
+}
+
+void u1_config_sleep_gpio_table(void)
+{
+	config_sleep_gpio_table(ARRAY_SIZE(q1_sleep_gpio_table),
+			q1_sleep_gpio_table);
+}
diff --git a/arch/arm/mach-exynos/reserve_mem-exynos4.c b/arch/arm/mach-exynos/reserve_mem-exynos4.c
new file mode 100644
index 0000000..23af3f7
--- /dev/null
+++ b/arch/arm/mach-exynos/reserve_mem-exynos4.c
@@ -0,0 +1,156 @@
+/* linux/arch/arm/mach-exynos/reserve_mem-exynos4.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * reserve_mem helper functions for EXYNOS4
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/mm.h>
+#include <linux/swap.h>
+#include <asm/setup.h>
+#include <linux/io.h>
+#include <mach/memory.h>
+#include <plat/media.h>
+#include <mach/media.h>
+
+struct s5p_media_device media_devs[] = {
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC0
+	{
+		.id = S5P_MDEV_MFC,
+		.name = "mfc",
+		.bank = 0,
+		.memsize = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC0 * SZ_1K,
+		.paddr = 0,
+	},
+#endif
+
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC1
+	{
+		.id = S5P_MDEV_MFC,
+		.name = "mfc",
+		.bank = 1,
+		.memsize = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC1 * SZ_1K,
+		.paddr = 0,
+	},
+#endif
+
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMD
+	{
+		.id = S5P_MDEV_FIMD,
+		.name = "fimd",
+		.bank = 1,
+		.memsize = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMD * SZ_1K,
+		.paddr = 0,
+	},
+#endif
+
+#ifdef CONFIG_MACH_U1
+#ifdef CONFIG_ANDROID_PMEM_MEMSIZE_PMEM
+	{
+		.id = S5P_MDEV_PMEM,
+		.name = "pmem",
+		.bank = 0,
+		.memsize = CONFIG_ANDROID_PMEM_MEMSIZE_PMEM * SZ_1K,
+		.paddr = 0,
+	},
+#endif
+
+#ifdef CONFIG_ANDROID_PMEM_MEMSIZE_PMEM_GPU1
+	{
+		.id = S5P_MDEV_PMEM_GPU1,
+		.name = "pmem_gpu1",
+		.bank = 0,
+		.memsize = CONFIG_ANDROID_PMEM_MEMSIZE_PMEM_GPU1 * SZ_1K,
+		.paddr = 0,
+	},
+#endif
+#endif
+
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC0
+	{
+		.id = S5P_MDEV_FIMC0,
+		.name = "fimc0",
+		.bank = 1,
+		.memsize = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC0 * SZ_1K,
+		.paddr = 0,
+	},
+#endif
+
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC1
+	{
+		.id = S5P_MDEV_FIMC1,
+		.name = "fimc1",
+		.bank = 1,
+		.memsize = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC1 * SZ_1K,
+		.paddr = 0,
+	},
+#endif
+
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC2
+	{
+		.id = S5P_MDEV_FIMC2,
+		.name = "fimc2",
+		.bank = 1,
+		.memsize = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC2 * SZ_1K,
+		.paddr = 0,
+	},
+#endif
+
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC3
+	{
+		.id = S5P_MDEV_FIMC3,
+		.name = "fimc3",
+		.bank = 1,
+		.memsize = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC3 * SZ_1K,
+		.paddr = 0,
+	},
+#endif
+
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_JPEG
+	{
+		.id = S5P_MDEV_JPEG,
+		.name = "jpeg",
+		.bank = 0,
+		.memsize = CONFIG_VIDEO_SAMSUNG_MEMSIZE_JPEG * SZ_1K,
+		.paddr = 0,
+	},
+#endif
+
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMG2D
+	{
+		.id = S5P_MDEV_FIMG2D,
+		.name = "fimg2d",
+		.bank = 0,
+		.memsize = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMG2D * SZ_1K,
+		.paddr = 0,
+	},
+#endif
+
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_TVOUT
+	{
+		.id = S5P_MDEV_TVOUT,
+		.name = "tvout",
+		.bank = 0,
+		.memsize = CONFIG_VIDEO_SAMSUNG_MEMSIZE_TVOUT * SZ_1K,
+		.paddr = 0,
+	},
+#endif
+
+#ifdef CONFIG_AUDIO_SAMSUNG_MEMSIZE_SRP
+	{
+		.id = S5P_MDEV_SRP,
+		.name = "srp",
+		.bank = 0,
+		.memsize = CONFIG_AUDIO_SAMSUNG_MEMSIZE_SRP * SZ_1K,
+		.paddr = 0,
+	},
+#endif
+};
+
+int nr_media_devs = (sizeof(media_devs) / sizeof(media_devs[0]));
+
diff --git a/arch/arm/mach-exynos/s2p-panel.c b/arch/arm/mach-exynos/s2p-panel.c
new file mode 100644
index 0000000..fdecf83c
--- /dev/null
+++ b/arch/arm/mach-exynos/s2p-panel.c
@@ -0,0 +1,1047 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/ld9040.h>
+
+#define SLEEPMSEC		0x1000
+#define ENDDEF			0x2000
+#define	DEFMASK			0xFF00
+#define COMMAND_ONLY		0xFE
+#define DATA_ONLY		0xFF
+
+static const unsigned short SEQ_INIT_DISPLAY_SETTING[] = {
+	/* USER_SETTING */
+	0xF0, 0x5A,
+	DATA_ONLY, 0x5A,
+	/* ACL ON */
+	0xC1, 0x4D,
+	DATA_ONLY, 0x96,	DATA_ONLY, 0x1D,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x01,	DATA_ONLY, 0xDF,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x03,	DATA_ONLY, 0x1F,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,	DATA_ONLY, 0x01,
+	DATA_ONLY, 0x08,	DATA_ONLY, 0x0F,	DATA_ONLY, 0x16,	DATA_ONLY, 0x1D,
+	DATA_ONLY, 0x24,	DATA_ONLY, 0x2A,	DATA_ONLY, 0x31,	DATA_ONLY, 0x38,
+	DATA_ONLY, 0x3F,	DATA_ONLY, 0x46,
+	/* PANEL CONDITION */
+	0xF8, 0x05,
+	DATA_ONLY, 0x5E,
+	DATA_ONLY, 0x96,
+	DATA_ONLY, 0x6B,
+	DATA_ONLY, 0x7D,
+	DATA_ONLY, 0x0D,
+	DATA_ONLY, 0x3F,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x32,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x07,
+	DATA_ONLY, 0x07,
+	DATA_ONLY, 0x20,
+	DATA_ONLY, 0x20,
+	DATA_ONLY, 0x20,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	/* DISPLAY_CONDITION */
+	0xF2, 0x02,
+	DATA_ONLY, 0x06,
+	DATA_ONLY, 0x0A,
+	DATA_ONLY, 0x10,
+	DATA_ONLY, 0x10,
+	/* GTCON */
+	0xF7, 0x09,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	/* MANPWR */
+	0xB0, 0x04,
+	/* PWR_CTRL */
+	0xF4, 0x0A,
+	DATA_ONLY, 0x87,
+	DATA_ONLY, 0x25,
+	DATA_ONLY, 0x6A,
+	DATA_ONLY, 0x44,
+	DATA_ONLY, 0x02,
+	DATA_ONLY, 0x88,
+	/* ELVSS_ON */
+	0xB1, 0x0D,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x16,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_INIT_ETC_SETTING[] = {
+	/* GAMMA_SET1 */
+	0xF9, 0x00,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x7B,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xC0,
+	DATA_ONLY, 0xA8,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA3,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xBD,
+	DATA_ONLY, 0xBF,
+	DATA_ONLY, 0xA6,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA4,
+	/* GAMMA_CTRL */
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	/* SLEEP OUT */
+	0x11, COMMAND_ONLY,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_USER_SETTING[] = {
+	0xF0, 0x5A,
+
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+static const unsigned short SEQ_ACL_ON[] = {
+	0xC1, 0x4D,
+
+	DATA_ONLY, 0x96,	DATA_ONLY, 0x1D,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x01,	DATA_ONLY, 0xDF,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x03,	DATA_ONLY, 0x1F,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,	DATA_ONLY, 0x01,
+	DATA_ONLY, 0x08,	DATA_ONLY, 0x0F,	DATA_ONLY, 0x16,	DATA_ONLY, 0x1D,
+	DATA_ONLY, 0x24,	DATA_ONLY, 0x2A,	DATA_ONLY, 0x31,	DATA_ONLY, 0x38,
+	DATA_ONLY, 0x3F,	DATA_ONLY, 0x46,
+
+	0xC0, 0x01,
+
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_ACL_OFF[] = {
+	0xC0, 0x00,
+
+	ENDDEF, 0x00
+};
+
+
+static const unsigned short SEQ_ACL_40P[] = {
+	0xC1, 0x4D,
+
+	DATA_ONLY, 0x96,	DATA_ONLY, 0x1D,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x01,	DATA_ONLY, 0xDF,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x03,	DATA_ONLY, 0x1F,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,	DATA_ONLY, 0x01,
+	DATA_ONLY, 0x06,	DATA_ONLY, 0x11,	DATA_ONLY, 0x1A,	DATA_ONLY, 0x20,
+	DATA_ONLY, 0x25,	DATA_ONLY, 0x29,	DATA_ONLY, 0x2D,	DATA_ONLY, 0x30,
+	DATA_ONLY, 0x33,	DATA_ONLY, 0x35,
+
+	0xC0, 0x01,
+
+	ENDDEF, 0x00
+};
+
+
+static const unsigned short SEQ_ACL_43P[] = {
+	0xC1, 0x4D,
+
+	DATA_ONLY, 0x96,	DATA_ONLY, 0x1D,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x01,	DATA_ONLY, 0xDF,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x03,	DATA_ONLY, 0x1F,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,	DATA_ONLY, 0x01,
+	DATA_ONLY, 0x07,	DATA_ONLY, 0x12,	DATA_ONLY, 0x1C,	DATA_ONLY, 0x23,
+	DATA_ONLY, 0x29,	DATA_ONLY, 0x2D,	DATA_ONLY, 0x31,	DATA_ONLY, 0x34,
+	DATA_ONLY, 0x37,	DATA_ONLY, 0x3A,
+
+	0xC0, 0x01,
+
+	ENDDEF, 0x00
+};
+
+
+
+
+static const unsigned short SEQ_ACL_45P[] = {
+	0xC1, 0x4D,
+
+	DATA_ONLY, 0x96,	DATA_ONLY, 0x1D,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x01,	DATA_ONLY, 0xDF,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x03,	DATA_ONLY, 0x1F,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,	DATA_ONLY, 0x01,
+	DATA_ONLY, 0x07,	DATA_ONLY, 0x13,	DATA_ONLY, 0x1E,	DATA_ONLY, 0x25,
+	DATA_ONLY, 0x2B,	DATA_ONLY, 0x30,	DATA_ONLY, 0x34,	DATA_ONLY, 0x37,
+	DATA_ONLY, 0x3A,	DATA_ONLY, 0x3D,
+
+	0xC0, 0x01,
+
+	ENDDEF, 0x00
+};
+
+
+static const unsigned short SEQ_ACL_47P[] = {
+	0xC1, 0x4D,
+
+	DATA_ONLY, 0x96,	DATA_ONLY, 0x1D,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x01,	DATA_ONLY, 0xDF,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x03,	DATA_ONLY, 0x1F,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,	DATA_ONLY, 0x01,
+	DATA_ONLY, 0x07,	DATA_ONLY, 0x14,	DATA_ONLY, 0x20,	DATA_ONLY, 0x28,
+	DATA_ONLY, 0x2E,	DATA_ONLY, 0x33,	DATA_ONLY, 0x37,	DATA_ONLY, 0x3B,
+	DATA_ONLY, 0x3E,	DATA_ONLY, 0x41,
+
+	0xC0, 0x01,
+
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_ACL_48P[] = {
+	0xC1, 0x4D,
+
+	DATA_ONLY, 0x96,	DATA_ONLY, 0x1D,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x01,	DATA_ONLY, 0xDF,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x03,	DATA_ONLY, 0x1F,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,	DATA_ONLY, 0x01,
+	DATA_ONLY, 0x08,	DATA_ONLY, 0x15,	DATA_ONLY, 0x20,	DATA_ONLY, 0x29,
+	DATA_ONLY, 0x2F,	DATA_ONLY, 0x34,	DATA_ONLY, 0x39,	DATA_ONLY, 0x3D,
+	DATA_ONLY, 0x40,	DATA_ONLY, 0x43,
+
+	0xC0, 0x01,
+
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_ACL_50P[] = {
+	0xC1, 0x4D,
+
+	DATA_ONLY, 0x96,	DATA_ONLY, 0x1D,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x01,	DATA_ONLY, 0xDF,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x03,	DATA_ONLY, 0x1F,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,	DATA_ONLY, 0x01,
+	DATA_ONLY, 0x08,	DATA_ONLY, 0x16,	DATA_ONLY, 0x22,	DATA_ONLY, 0x2B,
+	DATA_ONLY, 0x31,	DATA_ONLY, 0x37,	DATA_ONLY, 0x3B,	DATA_ONLY, 0x3F,
+	DATA_ONLY, 0x43,	DATA_ONLY, 0x46,
+
+	0xC0, 0x01,
+
+	ENDDEF, 0x00
+};
+
+static const unsigned short *ACL_cutoff_set[] = {
+	SEQ_ACL_OFF,
+	SEQ_ACL_40P,
+	SEQ_ACL_43P,
+	SEQ_ACL_45P,
+	SEQ_ACL_47P,
+	SEQ_ACL_48P,
+	SEQ_ACL_50P,
+};
+
+static const unsigned short SEQ_ELVSS_ON[] = {
+	0xB1, 0x0D,
+
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x16,
+	ENDDEF, 0x00
+};
+
+
+static const unsigned short SEQ_ELVSS_49[] = {
+	0xB2, 0x10,
+
+	DATA_ONLY, 0x10,
+	DATA_ONLY, 0x10,
+	DATA_ONLY, 0x10,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_ELVSS_41[] = {
+	0xB2, 0x17,
+	DATA_ONLY, 0x17,
+	DATA_ONLY, 0x17,
+	DATA_ONLY, 0x17,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_ELVSS_39[] = {
+	0xB2, 0x1A,
+	DATA_ONLY, 0x1A,
+	DATA_ONLY, 0x1A,
+	DATA_ONLY, 0x1A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_ELVSS_35[] = {
+	0xB2, 0x1E,
+	DATA_ONLY, 0x1E,
+	DATA_ONLY, 0x1E,
+	DATA_ONLY, 0x1E,
+	ENDDEF, 0x00
+};
+
+static const unsigned short *SEQ_ELVSS_set[] = {
+	SEQ_ELVSS_35,
+	SEQ_ELVSS_39,
+	SEQ_ELVSS_41,
+	SEQ_ELVSS_49,
+};
+
+static const unsigned short SEQ_GTCON[] = {
+	0xF7, 0x09,
+
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_PANEL_CONDITION[] = {
+	0xF8, 0x05,
+	DATA_ONLY, 0x5E,
+	DATA_ONLY, 0x96,
+	DATA_ONLY, 0x6B,
+	DATA_ONLY, 0x7D,
+	DATA_ONLY, 0x0D,
+	DATA_ONLY, 0x3F,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x32,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x07,
+	DATA_ONLY, 0x07,
+	DATA_ONLY, 0x20,
+	DATA_ONLY, 0x20,
+	DATA_ONLY, 0x20,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_GAMMA_SET1[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x7B,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xC0,
+	DATA_ONLY, 0xA8,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA3,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xBD,
+	DATA_ONLY, 0xBF,
+	DATA_ONLY, 0xA6,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA4,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_GAMMA_CTRL[] = {
+	0xFB, 0x02,
+
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_GAMMA_START[] = {
+	0xF9, COMMAND_ONLY,
+
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_APON[] = {
+	0xF3, 0x00,
+
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x0A,
+	DATA_ONLY, 0x02,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_DISPCTL[] = {
+	0xF2, 0x02,
+
+	DATA_ONLY, 0x06,
+	DATA_ONLY, 0x0A,
+	DATA_ONLY, 0x10,
+	DATA_ONLY, 0x10,
+	ENDDEF, 0x00
+};
+
+
+static const unsigned short SEQ_MANPWR[] = {
+	0xB0, 0x04,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_PWR_CTRL[] = {
+	0xF4, 0x0A,
+
+	DATA_ONLY, 0x87,
+	DATA_ONLY, 0x25,
+	DATA_ONLY, 0x6A,
+	DATA_ONLY, 0x44,
+	DATA_ONLY, 0x02,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_SLPOUT[] = {
+	0x11, COMMAND_ONLY,
+	SLEEPMSEC, 120,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_SLPIN[] = {
+	0x10, COMMAND_ONLY,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_DISPON[] = {
+	0x29, COMMAND_ONLY,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_DISPOFF[] = {
+	0x28, COMMAND_ONLY,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_VCI1_1ST_EN[] = {
+	0xF3, 0x10,
+
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x02,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_VL1_EN[] = {
+	0xF3, 0x11,
+
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x02,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_VL2_EN[] = {
+	0xF3, 0x13,
+
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x02,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_VCI1_2ND_EN[] = {
+	0xF3, 0x33,
+
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x02,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_VL3_EN[] = {
+	0xF3, 0x37,
+
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x02,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_VREG1_AMP_EN[] = {
+	0xF3, 0x37,
+
+	DATA_ONLY, 0x01,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x02,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_VGH_AMP_EN[] = {
+	0xF3, 0x37,
+
+	DATA_ONLY, 0x11,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x02,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_VGL_AMP_EN[] = {
+	0xF3, 0x37,
+
+	DATA_ONLY, 0x31,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x02,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_VMOS_AMP_EN[] = {
+	0xF3, 0x37,
+
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x03,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_VINT_AMP_EN[] = {
+	0xF3, 0x37,
+
+	DATA_ONLY, 0xF1,
+	/* DATA_ONLY, 0x71,	VMOS/VBL/VBH not used */
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x03,
+	/* DATA_ONLY, 0x02,	VMOS/VBL/VBH not used */
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_VBH_AMP_EN[] = {
+	0xF3, 0x37,
+
+	DATA_ONLY, 0xF9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x03,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_VBL_AMP_EN[] = {
+	0xF3, 0x37,
+
+	DATA_ONLY, 0xFD,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x03,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_GAM_AMP_EN[] = {
+	0xF3, 0x37,
+
+	DATA_ONLY, 0xFF,
+	/* DATA_ONLY, 0x73,	VMOS/VBL/VBH not used */
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x03,
+	/* DATA_ONLY, 0x02,	VMOS/VBL/VBH not used */
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_SD_AMP_EN[] = {
+	0xF3, 0x37,
+
+	DATA_ONLY, 0xFF,
+	/* DATA_ONLY, 0x73,	VMOS/VBL/VBH not used */
+	DATA_ONLY, 0x80,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x03,
+	/* DATA_ONLY, 0x02,	VMOS/VBL/VBH not used */
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_GLS_EN[] = {
+	0xF3, 0x37,
+
+	DATA_ONLY, 0xFF,
+	/* DATA_ONLY, 0x73,	VMOS/VBL/VBH not used */
+	DATA_ONLY, 0x81,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x03,
+	/* DATA_ONLY, 0x02,	VMOS/VBL/VBH not used */
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_ELS_EN[] = {
+	0xF3, 0x37,
+
+	DATA_ONLY, 0xFF,
+	/* DATA_ONLY, 0x73,	VMOS/VBL/VBH not used */
+	DATA_ONLY, 0x83,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x03,
+	/* DATA_ONLY, 0x02,	VMOS/VBL/VBH not used */
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_EL_ON[] = {
+	0xF3, 0x37,
+
+	DATA_ONLY, 0xFF,
+	/* DATA_ONLY, 0x73,	VMOS/VBL/VBH not used */
+	DATA_ONLY, 0x87,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x03,
+	/* DATA_ONLY, 0x02,	VMOS/VBL/VBH not used */
+	ENDDEF, 0x00
+};
+
+#define MAX_GAMMA_LEVEL		25
+#define GAMMA_TABLE_COUNT		21
+
+/* [U1] OCTA 4.27 XVGA - gamma value: 2.2 */
+
+static const unsigned int ld9040_22_300[] = {
+  0x00, 0xCA, 0xC4, 0xB8, 0xC6, 0x00, 0xAB
+, 0x00, 0xC3, 0xC1, 0xB4, 0xC0, 0x00, 0xD1
+, 0x00, 0xC6, 0xC2, 0xB1, 0xBF, 0x00, 0xDF
+};
+
+static const unsigned int ld9040_22_290[] = {
+  0x00, 0xCB, 0xC5, 0xB8, 0xC6, 0x00, 0xAA
+, 0x00, 0xC3, 0xC2, 0xB5, 0xC1, 0x00, 0xCF
+, 0x00, 0xC7, 0xC2, 0xB2, 0xBF, 0x00, 0xDE
+};
+
+static const unsigned int ld9040_22_280[] = {
+  0x00, 0xCC, 0xC5, 0xBA, 0xC6, 0x00, 0xA7
+, 0x00, 0xC3, 0xC1, 0xB6, 0xC2, 0x00, 0xCB
+, 0x00, 0xC7, 0xC2, 0xB4, 0xBF, 0x00, 0xDA
+};
+
+static const unsigned int ld9040_22_270[] = {
+  0x00, 0xCC, 0xC4, 0xBB, 0xC7, 0x00, 0xA3
+, 0x00, 0xC3, 0xC2, 0xB6, 0xC2, 0x00, 0xC8
+, 0x00, 0xC8, 0xC1, 0xB3, 0xC1, 0x00, 0xD6
+};
+static const unsigned int ld9040_22_260[] = {
+  0x00, 0xCD, 0xC5, 0xB6, 0xC8, 0x00, 0xA3
+, 0x00, 0xC3, 0xC3, 0xB6, 0xC3, 0x00, 0xC8
+, 0x00, 0xC8, 0xC3, 0xB4, 0xC2, 0x00, 0xD5
+};
+
+static const unsigned int ld9040_22_250[] = {
+  0x00, 0xCC, 0xC5, 0xBD, 0xCA, 0x00, 0xA0
+, 0x00, 0xC3, 0xC3, 0xB8, 0xC4, 0x00, 0xC4
+, 0x00, 0xC8, 0xC2, 0xB5, 0xC3, 0x00, 0xD2
+};
+
+static const unsigned int ld9040_22_240[] = {
+  0x00, 0xCC, 0xC5, 0xBD, 0xCA, 0x00, 0x9E
+, 0x00, 0xC4, 0xC4, 0xB8, 0xC4, 0x00, 0xC1
+, 0x00, 0xC9, 0xC3, 0xB6, 0xC2, 0x00, 0xCF
+};
+
+static const unsigned int ld9040_22_230[] = {
+  0x00, 0xCD, 0xC6, 0xBD, 0xCA, 0x00, 0x9B
+, 0x00, 0xC3, 0xC4, 0xB9, 0xC4, 0x00, 0xBE
+, 0x00, 0xCA, 0xC4, 0xB6, 0xC3, 0x00, 0xCB
+};
+
+static const unsigned int ld9040_22_220[] = {
+  0x00, 0xCD, 0xC6, 0xBD, 0xCC, 0x00, 0x98
+, 0x00, 0xC3, 0xC5, 0xB9, 0xC5, 0x00, 0xBA
+, 0x00, 0xC9, 0xC4, 0xB7, 0xC4, 0x00, 0xC7
+};
+
+static const unsigned int ld9040_22_210[] = {
+  0x00, 0xCE, 0xC7, 0xBD, 0xCC, 0x00, 0x95
+, 0x00, 0xC3, 0xC4, 0xBA, 0xC6, 0x00, 0xB7
+, 0x00, 0xCA, 0xC5, 0xB8, 0xC4, 0x00, 0xC3
+};
+
+static const unsigned int ld9040_22_200[] = {
+  0x00, 0xCF, 0xC7, 0xBE, 0xCD, 0x00, 0x92
+, 0x00, 0xC3, 0xC5, 0xBA, 0xC7, 0x00, 0xB3
+, 0x00, 0xCB, 0xC5, 0xB9, 0xC4, 0x00, 0xC0
+};
+
+static const unsigned int ld9040_22_190[] = {
+  0x00, 0xCE, 0xC8, 0xBF, 0xCD, 0x00, 0x8F
+, 0x00, 0xC3, 0xC5, 0xBA, 0xC8, 0x00, 0xAF
+, 0x00, 0xCA, 0xC5, 0xBA, 0xC5, 0x00, 0xBC
+};
+
+static const unsigned int ld9040_22_180[] = {
+  0x00, 0xCE, 0xC7, 0xC1, 0xCD, 0x00, 0x8C
+, 0x00, 0xC4, 0xC5, 0xBB, 0xC8, 0x00, 0xAC
+, 0x00, 0xCA, 0xC4, 0xBB, 0xC6, 0x00, 0xB8
+};
+
+static const unsigned int ld9040_22_170[] = {
+  0x00, 0xCE, 0xC7, 0xC1, 0xCF, 0x00, 0x88
+, 0x00, 0xC3, 0xC5, 0xBC, 0xCA, 0x00, 0xA7
+, 0x00, 0xCB, 0xC5, 0xBB, 0xC7, 0x00, 0xB3
+};
+
+static const unsigned int ld9040_22_160[] = {
+  0x00, 0xCE, 0xC9, 0xC1, 0xCF, 0x00, 0x85
+, 0x00, 0xC2, 0xC6, 0xBD, 0xCA, 0x00, 0xA3
+, 0x00, 0xCB, 0xC6, 0xBB, 0xC8, 0x00, 0xAF
+};
+
+static const unsigned int ld9040_22_150[] = {
+  0x00, 0xCF, 0xC9, 0xC1, 0xD1, 0x00, 0x82
+, 0x00, 0xC3, 0xC6, 0xBE, 0xCB, 0x00, 0x9F
+, 0x00, 0xCC, 0xC6, 0xBB, 0xC9, 0x00, 0xAB
+};
+
+static const unsigned int ld9040_22_140[] = {
+  0x00, 0xCF, 0xCA, 0xC1, 0xD0, 0x00, 0x7F
+, 0x00, 0xC3, 0xC6, 0xBF, 0xCB, 0x00, 0x9B
+, 0x00, 0xCC, 0xC8, 0xBD, 0xC9, 0x00, 0xA6
+};
+
+static const unsigned int ld9040_22_130[] = {
+  0x00, 0xCF, 0xCB, 0xC2, 0xD1, 0x00, 0x7B
+, 0x00, 0xC2, 0xC7, 0xBF, 0xCC, 0x00, 0x97
+, 0x00, 0xCC, 0xC8, 0xBE, 0xCB, 0x00, 0xA1
+};
+
+static const unsigned int ld9040_22_120[] = {
+  0x00, 0xD0, 0xCB, 0xC2, 0xD3, 0x00, 0x77
+, 0x00, 0xC2, 0xC8, 0xC0, 0xCD, 0x00, 0x92
+, 0x00, 0xCD, 0xC8, 0xBE, 0xCC, 0x00, 0x9C
+};
+
+static const unsigned int ld9040_22_110[] = {
+  0x00, 0xD0, 0xCB, 0xC3, 0xD3, 0x00, 0x74
+, 0x00, 0xC2, 0xC8, 0xC1, 0xCE, 0x00, 0x8D
+, 0x00, 0xCD, 0xC8, 0xBF, 0xCC, 0x00, 0x98
+};
+
+static const unsigned int ld9040_22_100[] = {
+  0x00, 0xD1, 0xCB, 0xC5, 0xD4, 0x00, 0x6F
+, 0x00, 0xC2, 0xC8, 0xC2, 0xCF, 0x00, 0x88
+, 0x00, 0xCE, 0xC9, 0xC0, 0xCE, 0x00, 0x92
+};
+
+static const unsigned int ld9040_22_90[] = {
+  0x00, 0xD2, 0xCA, 0xC5, 0xD4, 0x00, 0x6A
+, 0x00, 0xC0, 0xC8, 0xC2, 0xD0, 0x00, 0x82
+, 0x00, 0xCE, 0xC9, 0xC0, 0xCF, 0x00, 0x8B
+};
+
+static const unsigned int ld9040_22_80[] = {
+  0x00, 0xD2, 0xCB, 0xC6, 0xD7, 0x00, 0x65
+, 0x00, 0xC0, 0xC9, 0xC3, 0xD2, 0x00, 0x7C
+, 0x00, 0xCE, 0xCA, 0xC2, 0xD1, 0x00, 0x85
+};
+
+static const unsigned int ld9040_22_70[] = {
+  0x00, 0xD4, 0xCD, 0xC7, 0xD7, 0x00, 0x60
+, 0x00, 0xBC, 0xCB, 0xC4, 0xD3, 0x00, 0x76
+, 0x00, 0xCF, 0xCC, 0xC3, 0xD2, 0x00, 0x7F
+};
+
+static const unsigned int ld9040_22_60[] = {
+  0x00, 0xD5, 0xCD, 0xC8, 0xD7, 0x00, 0x5B
+, 0x00, 0xBA, 0xCA, 0xC5, 0xD4, 0x00, 0x71
+, 0x00, 0xD0, 0xCC, 0xC5, 0xD3, 0x00, 0x78
+};
+
+static const unsigned int ld9040_22_50[] = {
+  0x00, 0xD6, 0xCE, 0xCA, 0xD8, 0x00, 0x55
+, 0x00, 0xB9, 0xCA, 0xC6, 0xD6, 0x00, 0x69
+, 0x00, 0xD1, 0xCC, 0xC6, 0xD5, 0x00, 0x71
+};
+
+static const unsigned int ld9040_22_40[] = {
+  0x00, 0xD9, 0xCE, 0xCA, 0xD9, 0x00, 0x4F
+, 0x00, 0xB5, 0xCA, 0xC7, 0xD8, 0x00, 0x61
+, 0x00, 0xD2, 0xCE, 0xC6, 0xD6, 0x00, 0x69
+};
+
+static const unsigned int ld9040_22_30_dimming[] = {
+  0x00, 0xD9, 0xD3, 0xCC, 0xDA, 0x00, 0x46
+, 0x00, 0xB1, 0xC9, 0xC9, 0xD9, 0x00, 0x58
+, 0x00, 0xD2, 0xD0, 0xC9, 0xD8, 0x00, 0x5E
+};
+
+static const unsigned int *p22Gamma_set[] = {
+	ld9040_22_30_dimming,
+	ld9040_22_40,
+	ld9040_22_70,
+	ld9040_22_90,
+	ld9040_22_100,
+	ld9040_22_110,
+	ld9040_22_120,
+	ld9040_22_130,
+	ld9040_22_140,
+	ld9040_22_150,
+	ld9040_22_160,
+	ld9040_22_170,
+	ld9040_22_180,
+	ld9040_22_190,
+	ld9040_22_200,
+	ld9040_22_210,
+	ld9040_22_220,
+	ld9040_22_230,
+	ld9040_22_240,
+	ld9040_22_250,
+	ld9040_22_260,
+	ld9040_22_270,
+	ld9040_22_280,
+	ld9040_22_290,
+	ld9040_22_300,
+};
+
+/*  OCTA 4.52 XVGA - gamma value: 1.9 */
+static const unsigned int ld9040_19_300[] = {
+	0x00, 0xCD, 0xC8, 0xC0, 0xCC, 0x00, 0xAA,
+	0x00, 0xC9, 0xC7, 0xBA, 0xC6, 0x00, 0xD0,
+	0x00, 0xCA, 0xC5, 0xB8, 0xC6, 0x00, 0xDE
+};
+
+static const unsigned int ld9040_19_290[] = {
+	0x00, 0xCF, 0xC7, 0xC0, 0xCE, 0x00, 0xAB,
+	0x00, 0xCA, 0xC7, 0xBB, 0xC8, 0x00, 0xD0,
+	0x00, 0xCC, 0xC5, 0xB8, 0xC7, 0x00, 0xDF
+};
+
+static const unsigned int ld9040_19_280[] = {
+	0x00, 0xCF, 0xC9, 0xC0, 0xCD, 0x00, 0xA9,
+	0x00, 0xCA, 0xC8, 0xBC, 0xC8, 0x00, 0xCD,
+	0x00, 0xCB, 0xC7, 0xB9, 0xC6, 0x00, 0xDC
+};
+
+static const unsigned int ld9040_19_270[] = {
+	0x00, 0xD0, 0xCA, 0xC0, 0xCD, 0x00, 0xA7,
+	0x00, 0xCA, 0xC8, 0xBC, 0xC9, 0x00, 0xCA,
+	0x00, 0xCB, 0xC8, 0xBA, 0xC6, 0x00, 0xD9
+};
+
+static const unsigned int ld9040_19_260[] = {
+	0x00, 0xD0, 0xCA, 0xC1, 0xCD, 0x00, 0xA5,
+	0x00, 0xCA, 0xC7, 0xBE, 0xC9, 0x00, 0xC7,
+	0x00, 0xCC, 0xC7, 0xBB, 0xC7, 0x00, 0xD6
+};
+
+static const unsigned int ld9040_19_250[] = {
+	0x00, 0xD0, 0xCC, 0xC1, 0xCD, 0x00, 0xA2,
+	0x00, 0xCB, 0xC8, 0xBD, 0xCA, 0x00, 0xC4,
+	0x00, 0xCC, 0xC8, 0xBB, 0xC8, 0x00, 0xD2
+};
+
+static const unsigned int ld9040_19_240[] = {
+	0x00, 0xCF, 0xCB, 0xC2, 0xCE, 0x00, 0xA0,
+	0x00, 0xCB, 0xC8, 0xBE, 0xCA, 0x00, 0xC1,
+	0x00, 0xCB, 0xC8, 0xBC, 0xC8, 0x00, 0xCF
+};
+
+static const unsigned int ld9040_19_230[] = {
+	0x00, 0xCF, 0xCA, 0xC3, 0xD0, 0x00, 0x9C,
+	0x00, 0xCB, 0xC8, 0xBF, 0xCB, 0x00, 0xBD,
+	0x00, 0xCD, 0xC7, 0xBC, 0xCA, 0x00, 0xCA
+};
+
+static const unsigned int ld9040_19_220[] = {
+	0x00, 0xCF, 0xCB, 0xC4, 0xD0, 0x00, 0x99,
+	0x00, 0xCB, 0xCA, 0xBF, 0xCB, 0x00, 0xBA,
+	0x00, 0xCC, 0xC8, 0xBD, 0xCB, 0x00, 0xC6
+};
+
+static const unsigned int ld9040_19_210[] = {
+	0x00, 0xD0, 0xCA, 0xC4, 0xD1, 0x00, 0x96,
+	0x00, 0xCB, 0xC9, 0xC0, 0xCC, 0x00, 0xB6,
+	0x00, 0xCD, 0xC8, 0xBD, 0xCB, 0x00, 0xC3
+};
+
+static const unsigned int ld9040_19_200[] = {
+	0x00, 0xD1, 0xCB, 0xC4, 0xD2, 0x00, 0x93,
+	0x00, 0xCB, 0xCA, 0xC0, 0xCD, 0x00, 0xB2,
+	0x00, 0xCD, 0xCA, 0xBE, 0xCB, 0x00, 0xBF
+};
+
+
+static const unsigned int ld9040_19_190[] = {
+	0x00, 0xD1, 0xCC, 0xC5, 0xD2, 0x00, 0x90,
+	0x00, 0xCB, 0xCA, 0xC1, 0xCE, 0x00, 0xAE,
+	0x00, 0xCD, 0xCA, 0xC0, 0xCB, 0x00, 0xBB
+};
+
+
+static const unsigned int ld9040_19_180[] = {
+	0x00, 0xD2, 0xCC, 0xC5, 0xD2, 0x00, 0x8D,
+	0x00, 0xCC, 0xC9, 0xC2, 0xCE, 0x00, 0xAB,
+	0x00, 0xCD, 0xCA, 0xC0, 0xCC, 0x00, 0xB7
+};
+
+
+static const unsigned int ld9040_19_170[] = {
+	0x00, 0xD2, 0xCC, 0xC6, 0xD3, 0x00, 0x89,
+	0x00, 0xCC, 0xCA, 0xC2, 0xCF, 0x00, 0xA7,
+	0x00, 0xCE, 0xC9, 0xC1, 0xCE, 0x00, 0xB2
+};
+
+static const unsigned int ld9040_19_160[] = {
+	0x00, 0xD2, 0xCC, 0xC6, 0xD5, 0x00, 0x86,
+	0x00, 0xCC, 0xCB, 0xC2, 0xCF, 0x00, 0xA3,
+	0x00, 0xCF, 0xC9, 0xC0, 0xCF, 0x00, 0xAF
+};
+
+static const unsigned int ld9040_19_150[] = {
+	0x00, 0xD1, 0xCD, 0xC7, 0xD6, 0x00, 0x82,
+	0x00, 0xCB, 0xCC, 0xC4, 0xD0, 0x00, 0x9F,
+	0x00, 0xCE, 0xCA, 0xC1, 0xCF, 0x00, 0xAA
+};
+
+static const unsigned int ld9040_19_140[] = {
+	0x00, 0xD2, 0xCD, 0xC6, 0xD8, 0x00, 0x7E,
+	0x00, 0xCB, 0xCC, 0xC4, 0xD3, 0x00, 0x99,
+	0x00, 0xCF, 0xCB, 0xC1, 0xD1, 0x00, 0xA5
+};
+
+static const unsigned int ld9040_19_130[] = {
+	0x00, 0xD3, 0xCE, 0xC7, 0xD6, 0x00, 0x7B,
+	0x00, 0xCB, 0xCD, 0xC5, 0xD2, 0x00, 0x96,
+	0x00, 0xD0, 0xCD, 0xC3, 0xCF, 0x00, 0xA1
+};
+
+static const unsigned int ld9040_19_120[] = {
+	0x00, 0xD4, 0xCE, 0xC8, 0xD7, 0x00, 0x77,
+	0x00, 0xCB, 0xCD, 0xC6, 0xD3, 0x00, 0x91,
+	0x00, 0xD0, 0xCC, 0xC5, 0xD1, 0x00, 0x9B
+};
+
+static const unsigned int ld9040_19_110[] = {
+	0x00, 0xD4, 0xCF, 0xC9, 0xD6, 0x00, 0x74,
+	0x00, 0xCC, 0xCE, 0xC6, 0xD4, 0x00, 0x8C,
+	0x00, 0xCF, 0xCD, 0xC6, 0xD1, 0x00, 0x97
+};
+
+static const unsigned int ld9040_19_100[] = {
+	0x00, 0xD4, 0xCD, 0xCB, 0xD8, 0x00, 0x6F,
+	0x00, 0xCB, 0xCE, 0xC7, 0xD5, 0x00, 0x87,
+	0x00, 0xD0, 0xCD, 0xC5, 0xD4, 0x00, 0x91
+};
+
+static const unsigned int ld9040_19_90[] = {
+	0x00, 0xD6, 0xCF, 0xCA, 0xDA, 0x00, 0x6A,
+	0x00, 0xCB, 0xCF, 0xC8, 0xD7, 0x00, 0x81,
+	0x00, 0xD2, 0xCE, 0xC5, 0xD6, 0x00, 0x8B
+};
+
+
+static const unsigned int ld9040_19_80[] = {
+	0x00, 0xD7, 0xCF, 0xCB, 0xDA, 0x00, 0x66,
+	0x00, 0xCB, 0xCF, 0xCA, 0xD7, 0x00, 0x7C,
+	0x00, 0xD3, 0xCF, 0xC7, 0xD5, 0x00, 0x86
+};
+
+static const unsigned int ld9040_19_70[] = {
+	0x00, 0xD7, 0xD1, 0xCC, 0xDA, 0x00, 0x61,
+	0x00, 0xCA, 0xD0, 0xCA, 0xD8, 0x00, 0x77,
+	0x00, 0xD2, 0xD1, 0xC9, 0xD6, 0x00, 0x7F
+};
+
+static const unsigned int ld9040_19_60[] = {
+	0x00, 0xD9, 0xD0, 0xCD, 0xDA, 0x00, 0x5D,
+	0x00, 0xCC, 0xCF, 0xCB, 0xD9, 0x00, 0x70,
+	0x00, 0xD4, 0xD0, 0xCA, 0xD8, 0x00, 0x78
+};
+
+static const unsigned int ld9040_19_50[] = {
+	0x00, 0xD8, 0xD2, 0xCF, 0xDB, 0x00, 0x56,
+	0x00, 0xCA, 0xD1, 0xCC, 0xDB, 0x00, 0x69,
+	0x00, 0xD3, 0xD1, 0xCC, 0xDA, 0x00, 0x70
+};
+
+static const unsigned int ld9040_19_40[] = {
+	0x00, 0xDA, 0xD2, 0xD1, 0xDC, 0x00, 0x4F,
+	0x00, 0xC6, 0xD2, 0xCF, 0xDB, 0x00, 0x61,
+	0x00, 0xD4, 0xD2, 0xCE, 0xDB, 0x00, 0x68
+};
+
+static const unsigned int ld9040_19_30_dimming[] = {
+	0x00, 0xDC, 0xD5, 0xD2, 0xDE, 0x00, 0x46,
+	0x00, 0xC3, 0xD2, 0xCF, 0xDE, 0x00, 0x58,
+	0x00, 0xD3, 0xD4, 0xCF, 0xDD, 0x00, 0x5E
+};
+
+static const unsigned int *p19Gamma_set[] = {
+	ld9040_19_30_dimming,
+	ld9040_19_40,
+	ld9040_19_70,
+	ld9040_19_90,
+	ld9040_19_100,
+	ld9040_19_110,
+	ld9040_19_120,
+	ld9040_19_130,
+	ld9040_19_140,
+	ld9040_19_150,
+	ld9040_19_160,
+	ld9040_19_170,
+	ld9040_19_180,
+	ld9040_19_190,
+	ld9040_19_200,
+	ld9040_19_210,
+	ld9040_19_220,
+	ld9040_19_230,
+	ld9040_19_240,
+	ld9040_19_250,
+	ld9040_19_260,
+	ld9040_19_270,
+	ld9040_19_280,
+	ld9040_19_290,
+	ld9040_19_300,
+};
+
+struct ld9040_panel_data s2plus_panel_data = {
+	.seq_display_set = SEQ_INIT_DISPLAY_SETTING,
+	.seq_etc_set = SEQ_INIT_ETC_SETTING,
+	.seq_user_set = SEQ_USER_SETTING,
+	.seq_panelcondition_set = SEQ_PANEL_CONDITION,
+	.seq_displayctl_set = SEQ_DISPCTL,
+	.seq_gtcon_set = SEQ_GTCON,
+	.seq_manpwr_set = SEQ_MANPWR,
+	.seq_pwrctl_set = SEQ_PWR_CTRL,
+	.seq_gamma_set1 = SEQ_GAMMA_SET1,
+	.display_on = SEQ_DISPON,
+	.display_off = SEQ_DISPOFF,
+	.sleep_in = SEQ_SLPIN,
+	.sleep_out = SEQ_SLPOUT,
+	.gamma_start = SEQ_GAMMA_START,
+	.gamma_ctrl = SEQ_GAMMA_CTRL,
+	.gamma19_table = p19Gamma_set,
+	.gamma22_table = p22Gamma_set,
+	.acl_table = ACL_cutoff_set,
+	.elvss_table = SEQ_ELVSS_set,
+	.acl_on = SEQ_ACL_ON,
+	.elvss_on = SEQ_ELVSS_ON,
+	.gamma_table_size = ARRAY_SIZE(p22Gamma_set),
+};
+
+
diff --git a/arch/arm/mach-exynos/s2plus-panel.c b/arch/arm/mach-exynos/s2plus-panel.c
new file mode 100644
index 0000000..58dd374
--- /dev/null
+++ b/arch/arm/mach-exynos/s2plus-panel.c
@@ -0,0 +1,1672 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/ld9040.h>
+#include "s2plus-panel.h"
+
+
+static const unsigned short SEQ_SM2_ELVSS_44[] = {
+	0xB2, 0x15,
+	DATA_ONLY, 0x15,
+	DATA_ONLY, 0x15,
+	DATA_ONLY, 0x15,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_SM2_ELVSS_37[] = {
+	0xB2, 0x1C,
+	DATA_ONLY, 0x1C,
+	DATA_ONLY, 0x1C,
+	DATA_ONLY, 0x1C,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_SM2_ELVSS_34[] = {
+	0xB2, 0x1F,
+	DATA_ONLY, 0x1F,
+	DATA_ONLY, 0x1F,
+	DATA_ONLY, 0x1F,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_SM2_ELVSS_30[] = {
+	0xB2, 0x23,
+	DATA_ONLY, 0x23,
+	DATA_ONLY, 0x23,
+	DATA_ONLY, 0x23,
+	ENDDEF, 0x00
+};
+
+static const unsigned short *SEQ_SM2_ELVSS_set[] = {
+	SEQ_SM2_ELVSS_30,
+	SEQ_SM2_ELVSS_34,
+	SEQ_SM2_ELVSS_37,
+	SEQ_SM2_ELVSS_44,
+};
+
+
+static const unsigned short SEQ_PWR_CTRL[] = {
+	0xF4, 0x0A,
+
+	DATA_ONLY, 0x87,
+	DATA_ONLY, 0x25,
+	DATA_ONLY, 0x6A,
+	DATA_ONLY, 0x44,
+	DATA_ONLY, 0x02,
+	ENDDEF, 0x00
+};
+
+
+/* LD9040, 4.27", SM2 A1 Panel Gamma Data */
+static const unsigned short ld9040_sm2_a1_22_300[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA3,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xA6,
+	DATA_ONLY, 0xA6,
+	DATA_ONLY, 0x9F,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xA8,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xA3,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCE,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_22_290[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xA8,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA1,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xA6,
+	DATA_ONLY, 0xA7,
+	DATA_ONLY, 0xA0,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xA2,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCC,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_22_280[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA0,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xA6,
+	DATA_ONLY, 0xA8,
+	DATA_ONLY, 0xA2,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xA4,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCA,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_22_270[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xBD,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x9E,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xA6,
+	DATA_ONLY, 0xA8,
+	DATA_ONLY, 0xA3,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xA4,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC8,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_22_260[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xA8,
+	DATA_ONLY, 0xBD,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x9C,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xA5,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xA2,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xA4,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC5,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_22_250[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xBC,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x9A,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xA5,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xA4,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xA6,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC2,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_22_240[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xBE,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x96,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xA4,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xA4,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xA6,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xBE,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_22_230[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xBE,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x94,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xA4,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xA3,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xA6,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xBB,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_22_220[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xBE,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x91,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xA3,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xA4,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA6,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xA7,
+	DATA_ONLY, 0xBC,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB7,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_22_210[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xBF,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x8E,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xA3,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xA6,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA3,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xA8,
+	DATA_ONLY, 0xBC,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB4,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+
+static const unsigned short ld9040_sm2_a1_22_200[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xC0,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x8B,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xA2,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xA5,
+	DATA_ONLY, 0xBC,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA0,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xA7,
+	DATA_ONLY, 0xBC,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB1,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_22_190[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x88,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xA1,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xA6,
+	DATA_ONLY, 0xBD,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x9C,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xA8,
+	DATA_ONLY, 0xBD,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xAD,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_22_180[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x85,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xA0,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xA6,
+	DATA_ONLY, 0xBD,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x99,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xBE,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA9,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+
+static const unsigned short ld9040_sm2_a1_22_170[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x82,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0x9F,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xA6,
+	DATA_ONLY, 0xBE,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x95,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xBF,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA5,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_22_160[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x7F,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0x9D,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xA7,
+	DATA_ONLY, 0xBF,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x91,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xC0,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA1,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_22_150[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x7C,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0x9B,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xA8,
+	DATA_ONLY, 0xBF,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x8E,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x9D,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_22_140[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x78,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0x9B,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x89,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x99,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_22_130[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x75,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0x9A,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x86,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x95,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_22_120[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x71,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0x97,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x82,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x90,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_22_110[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x6D,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0x96,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x7D,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x8C,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+
+static const unsigned short ld9040_sm2_a1_22_100[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xA8,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x69,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0x93,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x79,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x87,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+
+static const unsigned short ld9040_sm2_a1_22_90[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xA7,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x65,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0x92,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x74,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x82,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+
+
+static const unsigned short ld9040_sm2_a1_22_80[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xA6,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x60,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0x8E,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x6F,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x7C,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+
+static const unsigned short ld9040_sm2_a1_22_70[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xA4,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x5B,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0x8C,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x69,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x76,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+
+static const unsigned short ld9040_sm2_a1_22_60[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0x9F,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x56,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0x89,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x63,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x6F,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_22_50[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0x9E,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x50,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0x88,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x5D,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x68,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_22_40[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0x96,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x49,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0x85,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x55,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x60,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_22_30_dimming[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0x81,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xCD,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x41,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0x80,
+	DATA_ONLY, 0xA7,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x4C,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x56,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+
+static const unsigned short ld9040_sm2_a1_19_300[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xBF,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA4,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xBE,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xBE,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCF,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_290[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA2,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xBF,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xC0,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCD,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_280[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA0,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xBF,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCA,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_270[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x9E,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xC0,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC8,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_260[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x9C,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xC0,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC5,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_250[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x99,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC1,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_240[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x96,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xBE,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_230[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x94,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xBB,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_220[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x91,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA6,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB7,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_210[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x8F,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA3,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB5,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_200[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xBC,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x8C,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA0,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB1,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_190[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xBC,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x89,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x9C,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xAD,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_180[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xBD,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x85,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x99,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA9,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_170[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xBE,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x82,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x95,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA5,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_160[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x7F,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x91,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA1,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_150[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0xBC,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x7C,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x8D,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x9D,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_140[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0xBC,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x79,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x89,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x99,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_130[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xBC,
+	DATA_ONLY, 0xBD,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x75,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x86,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x95,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_120[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0xBE,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x71,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x81,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x90,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_110[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xBE,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x6E,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x7D,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x8C,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_100[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xBE,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x6A,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x78,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x87,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_90[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xC0,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x66,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x74,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x82,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_80[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xCD,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x61,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xA7,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xCE,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x6E,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xCD,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x7C,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_70[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x5C,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xA4,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xCE,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x69,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xCD,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x75,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_60[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0xBC,
+	DATA_ONLY, 0xCF,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x55,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0x9F,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xD0,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x63,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xD0,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x6E,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_50[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0xBE,
+	DATA_ONLY, 0xCF,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x4F,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0x9B,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xCF,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x5D,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xD0,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x67,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_40[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0xBF,
+	DATA_ONLY, 0xD2,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x48,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0x97,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xD1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x55,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xD2,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x5F,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_30_dimming[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xA7,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0xC0,
+	DATA_ONLY, 0xD5,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x40,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0x93,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xD2,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x4C,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xD2,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x56,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+
+/* LD9040, 4.27", SM2 A1 Panel Gamma Table */
+static const unsigned short *psm2_a1_22Gamma_set[] = {
+	ld9040_sm2_a1_22_30_dimming,
+	ld9040_sm2_a1_22_40,
+	ld9040_sm2_a1_22_70,
+	ld9040_sm2_a1_22_90,
+	ld9040_sm2_a1_22_100,
+	ld9040_sm2_a1_22_110,
+	ld9040_sm2_a1_22_120,
+	ld9040_sm2_a1_22_130,
+	ld9040_sm2_a1_22_140,
+	ld9040_sm2_a1_22_150,
+	ld9040_sm2_a1_22_160,
+	ld9040_sm2_a1_22_170,
+	ld9040_sm2_a1_22_180,
+	ld9040_sm2_a1_22_190,
+	ld9040_sm2_a1_22_200,
+	ld9040_sm2_a1_22_210,
+	ld9040_sm2_a1_22_220,
+	ld9040_sm2_a1_22_230,
+	ld9040_sm2_a1_22_240,
+	ld9040_sm2_a1_22_250,
+	ld9040_sm2_a1_22_260,
+	ld9040_sm2_a1_22_270,
+	ld9040_sm2_a1_22_280,
+	ld9040_sm2_a1_22_290,
+	ld9040_sm2_a1_22_300,
+};
+
+static const unsigned short *psm2_a1_19Gamma_set[] = {
+	ld9040_sm2_a1_19_30_dimming,
+	ld9040_sm2_a1_19_40,
+	ld9040_sm2_a1_19_70,
+	ld9040_sm2_a1_19_90,
+	ld9040_sm2_a1_19_100,
+	ld9040_sm2_a1_19_110,
+	ld9040_sm2_a1_19_120,
+	ld9040_sm2_a1_19_130,
+	ld9040_sm2_a1_19_140,
+	ld9040_sm2_a1_19_150,
+	ld9040_sm2_a1_19_160,
+	ld9040_sm2_a1_19_170,
+	ld9040_sm2_a1_19_180,
+	ld9040_sm2_a1_19_190,
+	ld9040_sm2_a1_19_200,
+	ld9040_sm2_a1_19_210,
+	ld9040_sm2_a1_19_220,
+	ld9040_sm2_a1_19_230,
+	ld9040_sm2_a1_19_240,
+	ld9040_sm2_a1_19_250,
+	ld9040_sm2_a1_19_260,
+	ld9040_sm2_a1_19_270,
+	ld9040_sm2_a1_19_280,
+	ld9040_sm2_a1_19_290,
+	ld9040_sm2_a1_19_300,
+};
+
+
+struct ld9040_panel_data s2plus_panel_data = {
+	.seq_user_set = SEQ_USER_SETTING,
+	.seq_displayctl_set = SEQ_DISPCTL,
+	.seq_gtcon_set = SEQ_GTCON,
+	.seq_panelcondition_set = SEQ_PANEL_CONDITION,
+	.seq_pwrctl_set = SEQ_PWR_CTRL,
+	.display_on = SEQ_DISPON,
+	.display_off = SEQ_DISPOFF,
+	.sleep_in = SEQ_SLPIN,
+	.sleep_out = SEQ_SLPOUT,
+	.acl_on = SEQ_ACL_ON,
+	.acl_table = ACL_cutoff_set,
+	.elvss_on = SEQ_ELVSS_ON,
+	.elvss_table = SEQ_SM2_ELVSS_set,
+	.gamma19_table = psm2_a1_19Gamma_set,
+	.gamma22_table = psm2_a1_22Gamma_set,
+	.lcdtype = LCDTYPE_SM2_A1,
+};
diff --git a/arch/arm/mach-exynos/s2plus-panel.h b/arch/arm/mach-exynos/s2plus-panel.h
new file mode 100644
index 0000000..9640f8b
--- /dev/null
+++ b/arch/arm/mach-exynos/s2plus-panel.h
@@ -0,0 +1,215 @@
+/*
+ * arch/arm/mach-exynos/s2plus-panel.h
+ */
+
+#ifndef __S2PLUS_PANEL_H__
+#define __S2PLUS_PANEL_H__
+
+#define SLEEPMSEC		0x1000
+#define ENDDEF			0x2000
+#define	DEFMASK		0xFF00
+#define COMMAND_ONLY		0xFE
+#define DATA_ONLY		0xFF
+
+
+static const unsigned short SEQ_USER_SETTING[] = {
+	0xF0, 0x5A,
+
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_DISPCTL[] = {
+	0xF2, 0x02,
+
+	DATA_ONLY, 0x06,
+	DATA_ONLY, 0x0A,
+	DATA_ONLY, 0x10,
+	DATA_ONLY, 0x10,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_GTCON[] = {
+	0xF7, 0x09,
+
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_PANEL_CONDITION[] = {
+	0xF8, 0x05,
+	DATA_ONLY, 0x5E,
+	DATA_ONLY, 0x96,
+	DATA_ONLY, 0x6B,
+	DATA_ONLY, 0x7D,
+	DATA_ONLY, 0x0D,
+	DATA_ONLY, 0x3F,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x32,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x07,
+	DATA_ONLY, 0x05,
+	DATA_ONLY, 0x1F,
+	DATA_ONLY, 0x1F,
+	DATA_ONLY, 0x1F,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_SLPOUT[] = {
+	0x11, COMMAND_ONLY,
+	SLEEPMSEC, 120,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_SLPIN[] = {
+	0x10, COMMAND_ONLY,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_DISPON[] = {
+	0x29, COMMAND_ONLY,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_DISPOFF[] = {
+	0x28, COMMAND_ONLY,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_ELVSS_ON[] = {
+	0xB1, 0x0F,
+
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x16,
+	ENDDEF, 0x00
+};
+
+
+static const unsigned short SEQ_ACL_ON[] = {
+	0xC0, 0x01,
+
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_ACL_OFF[] = {
+	0xC0, 0x00,
+
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_ACL_40P[] = {
+	0xC1, 0x4D,
+
+	DATA_ONLY, 0x96,	DATA_ONLY, 0x1D,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x01,	DATA_ONLY, 0xDF,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x03,	DATA_ONLY, 0x1F,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,	DATA_ONLY, 0x01,
+	DATA_ONLY, 0x06,	DATA_ONLY, 0x11,	DATA_ONLY, 0x1A,	DATA_ONLY, 0x20,
+	DATA_ONLY, 0x25,	DATA_ONLY, 0x29,	DATA_ONLY, 0x2D,	DATA_ONLY, 0x30,
+	DATA_ONLY, 0x33,	DATA_ONLY, 0x35,
+
+	0xC0, 0x01,
+
+	ENDDEF, 0x00
+};
+
+
+static const unsigned short SEQ_ACL_43P[] = {
+	0xC1, 0x4D,
+
+	DATA_ONLY, 0x96,	DATA_ONLY, 0x1D,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x01,	DATA_ONLY, 0xDF,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x03,	DATA_ONLY, 0x1F,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,	DATA_ONLY, 0x01,
+	DATA_ONLY, 0x07,	DATA_ONLY, 0x12,	DATA_ONLY, 0x1C,	DATA_ONLY, 0x23,
+	DATA_ONLY, 0x29,	DATA_ONLY, 0x2D,	DATA_ONLY, 0x31,	DATA_ONLY, 0x34,
+	DATA_ONLY, 0x37,	DATA_ONLY, 0x3A,
+
+	0xC0, 0x01,
+
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_ACL_45P[] = {
+	0xC1, 0x4D,
+
+	DATA_ONLY, 0x96,	DATA_ONLY, 0x1D,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x01,	DATA_ONLY, 0xDF,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x03,	DATA_ONLY, 0x1F,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,	DATA_ONLY, 0x01,
+	DATA_ONLY, 0x07,	DATA_ONLY, 0x13,	DATA_ONLY, 0x1E,	DATA_ONLY, 0x25,
+	DATA_ONLY, 0x2B,	DATA_ONLY, 0x30,	DATA_ONLY, 0x34,	DATA_ONLY, 0x37,
+	DATA_ONLY, 0x3A,	DATA_ONLY, 0x3D,
+
+	0xC0, 0x01,
+
+	ENDDEF, 0x00
+};
+
+
+static const unsigned short SEQ_ACL_47P[] = {
+	0xC1, 0x4D,
+
+	DATA_ONLY, 0x96,	DATA_ONLY, 0x1D,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x01,	DATA_ONLY, 0xDF,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x03,	DATA_ONLY, 0x1F,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,	DATA_ONLY, 0x01,
+	DATA_ONLY, 0x07,	DATA_ONLY, 0x14,	DATA_ONLY, 0x20,	DATA_ONLY, 0x28,
+	DATA_ONLY, 0x2E,	DATA_ONLY, 0x33,	DATA_ONLY, 0x37,	DATA_ONLY, 0x3B,
+	DATA_ONLY, 0x3E,	DATA_ONLY, 0x41,
+
+	0xC0, 0x01,
+
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_ACL_48P[] = {
+	0xC1, 0x4D,
+
+	DATA_ONLY, 0x96,	DATA_ONLY, 0x1D,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x01,	DATA_ONLY, 0xDF,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x03,	DATA_ONLY, 0x1F,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,	DATA_ONLY, 0x01,
+	DATA_ONLY, 0x08,	DATA_ONLY, 0x15,	DATA_ONLY, 0x20,	DATA_ONLY, 0x29,
+	DATA_ONLY, 0x2F,	DATA_ONLY, 0x34,	DATA_ONLY, 0x39,	DATA_ONLY, 0x3D,
+	DATA_ONLY, 0x40,	DATA_ONLY, 0x43,
+
+	0xC0, 0x01,
+
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_ACL_50P[] = {
+	0xC1, 0x4D,
+
+	DATA_ONLY, 0x96,	DATA_ONLY, 0x1D,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x01,	DATA_ONLY, 0xDF,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x03,	DATA_ONLY, 0x1F,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,	DATA_ONLY, 0x01,
+	DATA_ONLY, 0x08,	DATA_ONLY, 0x16,	DATA_ONLY, 0x22,	DATA_ONLY, 0x2B,
+	DATA_ONLY, 0x31,	DATA_ONLY, 0x37,	DATA_ONLY, 0x3B,	DATA_ONLY, 0x3F,
+	DATA_ONLY, 0x43,	DATA_ONLY, 0x46,
+
+	0xC0, 0x01,
+
+	ENDDEF, 0x00
+};
+
+static const unsigned short *ACL_cutoff_set[] = {
+	SEQ_ACL_OFF,
+	SEQ_ACL_40P,
+	SEQ_ACL_43P,
+	SEQ_ACL_45P,
+	SEQ_ACL_47P,
+	SEQ_ACL_48P,
+	SEQ_ACL_50P,
+};
+
+#endif
diff --git a/arch/arm/mach-exynos/sec-common.c b/arch/arm/mach-exynos/sec-common.c
new file mode 100644
index 0000000..e099239
--- /dev/null
+++ b/arch/arm/mach-exynos/sec-common.c
@@ -0,0 +1,18 @@
+#include <linux/device.h>
+#include <linux/err.h>
+
+struct class *sec_class;
+EXPORT_SYMBOL(sec_class);
+
+static int __init midas_class_create(void)
+{
+	sec_class = class_create(THIS_MODULE, "sec");
+	if (IS_ERR(sec_class)) {
+		pr_err("Failed to create class(sec)!\n");
+		return PTR_ERR(sec_class);
+	}
+
+	return 0;
+}
+
+subsys_initcall(midas_class_create);
diff --git a/arch/arm/mach-exynos/sec-reboot.c b/arch/arm/mach-exynos/sec-reboot.c
new file mode 100644
index 0000000..075f107
--- /dev/null
+++ b/arch/arm/mach-exynos/sec-reboot.c
@@ -0,0 +1,133 @@
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <asm/io.h>
+#include <asm/cacheflush.h>
+#include <mach/system.h>
+#include <mach/regs-pmu.h>
+#include <mach/gpio.h>
+
+/* charger cable state */
+extern bool is_cable_attached;
+static void sec_power_off(void)
+{
+	int poweroff_try = 0;
+
+	local_irq_disable();
+
+	pr_emerg("%s : cable state=%d\n", __func__, is_cable_attached);
+
+	while (1) {
+		/* Check reboot charging */
+		if (is_cable_attached || (poweroff_try >= 5)) {
+			pr_emerg
+			    ("%s: charger connected(%d) or power"
+			     "off failed(%d), reboot!\n",
+			     __func__, is_cable_attached, poweroff_try);
+			writel(0x0, S5P_INFORM2);	/* To enter LP charging */
+
+			flush_cache_all();
+			outer_flush_all();
+			arch_reset(0, 0);
+
+			pr_emerg("%s: waiting for reboot\n", __func__);
+			while (1);
+		}
+
+		/* wait for power button release */
+		if (gpio_get_value(GPIO_nPOWER)) {
+			pr_emerg("%s: set PS_HOLD low\n", __func__);
+
+			/* power off code
+			 * PS_HOLD Out/High -->
+			 * Low PS_HOLD_CONTROL, R/W, 0x1002_330C
+			 */
+			writel(readl(S5P_PS_HOLD_CONTROL) & 0xFFFFFEFF,
+			       S5P_PS_HOLD_CONTROL);
+
+			++poweroff_try;
+			pr_emerg
+			    ("%s: Should not reach here! (poweroff_try:%d)\n",
+			     __func__, poweroff_try);
+		} else {
+			/* if power button is not released, wait and check TA again */
+			pr_info("%s: PowerButton is not released.\n", __func__);
+		}
+		mdelay(1000);
+	}
+}
+
+#define REBOOT_MODE_PREFIX	0x12345670
+#define REBOOT_MODE_NONE	0
+#define REBOOT_MODE_DOWNLOAD	1
+#define REBOOT_MODE_UPLOAD	2
+#define REBOOT_MODE_CHARGING	3
+#define REBOOT_MODE_RECOVERY	4
+#define REBOOT_MODE_FOTA	5
+#define REBOOT_MODE_FOTA_BL	6	/* update bootloader */
+
+#define REBOOT_SET_PREFIX	0xabc00000
+#define REBOOT_SET_DEBUG	0x000d0000
+#define REBOOT_SET_SWSEL	0x000e0000
+#define REBOOT_SET_SUD		0x000f0000
+
+static void sec_reboot(char str, const char *cmd)
+{
+	local_irq_disable();
+
+	pr_emerg("%s (%d, %s)\n", __func__, str, cmd ? cmd : "(null)");
+
+	writel(0x12345678, S5P_INFORM2);	/* Don't enter lpm mode */
+
+	if (!cmd) {
+		writel(REBOOT_MODE_PREFIX | REBOOT_MODE_NONE, S5P_INFORM3);
+	} else {
+		unsigned long value;
+		if (!strcmp(cmd, "fota"))
+			writel(REBOOT_MODE_PREFIX | REBOOT_MODE_FOTA,
+			       S5P_INFORM3);
+		else if (!strcmp(cmd, "fota_bl"))
+			writel(REBOOT_MODE_PREFIX | REBOOT_MODE_FOTA_BL,
+			       S5P_INFORM3);
+		else if (!strcmp(cmd, "recovery"))
+			writel(REBOOT_MODE_PREFIX | REBOOT_MODE_RECOVERY,
+			       S5P_INFORM3);
+		else if (!strcmp(cmd, "download"))
+			writel(REBOOT_MODE_PREFIX | REBOOT_MODE_DOWNLOAD,
+			       S5P_INFORM3);
+		else if (!strcmp(cmd, "upload"))
+			writel(REBOOT_MODE_PREFIX | REBOOT_MODE_UPLOAD,
+			       S5P_INFORM3);
+		else if (!strncmp(cmd, "debug", 5)
+			 && !kstrtoul(cmd + 5, 0, &value))
+			writel(REBOOT_SET_PREFIX | REBOOT_SET_DEBUG | value,
+			       S5P_INFORM3);
+		else if (!strncmp(cmd, "swsel", 5)
+			 && !kstrtoul(cmd + 5, 0, &value))
+			writel(REBOOT_SET_PREFIX | REBOOT_SET_SWSEL | value,
+			       S5P_INFORM3);
+		else if (!strncmp(cmd, "sud", 3)
+			 && !kstrtoul(cmd + 3, 0, &value))
+			writel(REBOOT_SET_PREFIX | REBOOT_SET_SUD | value,
+			       S5P_INFORM3);
+		else
+			writel(REBOOT_MODE_PREFIX | REBOOT_MODE_NONE,
+			       S5P_INFORM3);
+	}
+
+	flush_cache_all();
+	outer_flush_all();
+	arch_reset(0, 0);
+
+	pr_emerg("%s: waiting for reboot\n", __func__);
+	while (1);
+}
+
+static int __init sec_reboot_init(void)
+{
+	/* to support system shut down */
+	pm_power_off = sec_power_off;
+	arm_pm_restart = sec_reboot;
+	return 0;
+}
+
+subsys_initcall(sec_reboot_init);
diff --git a/arch/arm/mach-exynos/sec-switch.c b/arch/arm/mach-exynos/sec-switch.c
new file mode 100644
index 0000000..7b8726c
--- /dev/null
+++ b/arch/arm/mach-exynos/sec-switch.c
@@ -0,0 +1,513 @@
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi_gpio.h>
+#include <linux/gpio.h>
+#include <linux/gpio_keys.h>
+#include <linux/gpio_event.h>
+#include <plat/devs.h>
+#include <plat/gpio-cfg.h>
+#include <linux/i2c.h>
+#include <linux/i2c-gpio.h>
+#include <linux/input.h>
+#include <plat/udc-hs.h>
+/*#include <linux/mmc/host.h>*/
+#include <linux/regulator/machine.h>
+#include <linux/regulator/max8649.h>
+#include <linux/regulator/fixed.h>
+#include <linux/mfd/wm8994/pdata.h>
+#include <linux/mfd/max77693.h>
+#include <linux/mfd/max77693-private.h>
+#include <linux/mfd/max77686.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/gpio.h>
+
+#include <linux/power_supply.h>
+#include <linux/battery/samsung_battery.h>
+
+#include <linux/switch.h>
+#include <linux/sii9234.h>
+
+#ifdef CONFIG_USB_HOST_NOTIFY
+#include <linux/host_notify.h>
+#endif
+#include <linux/pm_runtime.h>
+#include <linux/usb.h>
+#include <linux/usb/hcd.h>
+
+#ifdef CONFIG_JACK_MON
+#include <linux/jack.h>
+#endif
+
+#ifdef CONFIG_MACH_SLP_NAPLES
+#include <mach/naples-tsp.h>
+#endif
+#ifdef CONFIG_MACH_MIDAS
+#include <linux/platform_data/mms_ts.h>
+#endif
+
+static struct switch_dev switch_dock = {
+	.name = "dock",
+};
+
+extern struct class *sec_class;
+
+struct device *switch_dev;
+EXPORT_SYMBOL(switch_dev);
+
+/* charger cable state */
+bool is_cable_attached;
+bool is_jig_attached;
+
+static ssize_t midas_switch_show_vbus(struct device *dev,
+				      struct device_attribute *attr, char *buf)
+{
+	int i;
+	struct regulator *regulator;
+
+	regulator = regulator_get(NULL, "safeout1");
+	if (IS_ERR(regulator)) {
+		pr_warn("%s: fail to get regulator\n", __func__);
+		return sprintf(buf, "UNKNOWN\n");
+	}
+	if (regulator_is_enabled(regulator))
+		i = sprintf(buf, "VBUS is enabled\n");
+	else
+		i = sprintf(buf, "VBUS is disabled\n");
+	regulator_put(regulator);
+
+	return i;
+}
+
+static ssize_t midas_switch_store_vbus(struct device *dev,
+				       struct device_attribute *attr,
+				       const char *buf, size_t count)
+{
+	int disable, ret, usb_mode;
+	struct regulator *regulator;
+	/* struct s3c_udc *udc = platform_get_drvdata(&s3c_device_usbgadget); */
+
+	if (!strncmp(buf, "0", 1))
+		disable = 0;
+	else if (!strncmp(buf, "1", 1))
+		disable = 1;
+	else {
+		pr_warn("%s: Wrong command\n", __func__);
+		return count;
+	}
+
+	pr_info("%s: disable=%d\n", __func__, disable);
+	usb_mode =
+	    disable ? USB_CABLE_DETACHED_WITHOUT_NOTI : USB_CABLE_ATTACHED;
+	/* ret = udc->change_usb_mode(usb_mode); */
+	ret = -1;
+	if (ret < 0)
+		pr_err("%s: fail to change mode!!!\n", __func__);
+
+	regulator = regulator_get(NULL, "safeout1");
+	if (IS_ERR(regulator)) {
+		pr_warn("%s: fail to get regulator\n", __func__);
+		return count;
+	}
+
+	if (disable) {
+		if (regulator_is_enabled(regulator))
+			regulator_force_disable(regulator);
+		if (!regulator_is_enabled(regulator))
+			regulator_enable(regulator);
+	} else {
+		if (!regulator_is_enabled(regulator))
+			regulator_enable(regulator);
+	}
+	regulator_put(regulator);
+
+	return count;
+}
+
+DEVICE_ATTR(disable_vbus, 0664, midas_switch_show_vbus,
+	    midas_switch_store_vbus);
+
+static int __init midas_sec_switch_init(void)
+{
+	int ret;
+	switch_dev = device_create(sec_class, NULL, 0, NULL, "switch");
+
+	if (IS_ERR(switch_dev))
+		pr_err("Failed to create device(switch)!\n");
+
+	ret = device_create_file(switch_dev, &dev_attr_disable_vbus);
+	if (ret)
+		pr_err("Failed to create device file(disable_vbus)!\n");
+
+	return 0;
+};
+
+int max77693_muic_charger_cb(enum cable_type_muic cable_type)
+{
+#ifdef CONFIG_BATTERY_MAX77693_CHARGER
+	struct power_supply *psy = power_supply_get_by_name("max77693-charger");
+	union power_supply_propval value;
+#endif
+	pr_info("%s: %d\n", __func__, cable_type);
+
+	switch (cable_type) {
+	case CABLE_TYPE_NONE_MUIC:
+	case CABLE_TYPE_OTG_MUIC:
+	case CABLE_TYPE_JIG_UART_OFF_MUIC:
+	case CABLE_TYPE_MHL_MUIC:
+		is_cable_attached = false;
+		break;
+	case CABLE_TYPE_USB_MUIC:
+	case CABLE_TYPE_JIG_USB_OFF_MUIC:
+	case CABLE_TYPE_JIG_USB_ON_MUIC:
+		is_cable_attached = true;
+		break;
+	case CABLE_TYPE_MHL_VB_MUIC:
+		is_cable_attached = true;
+		break;
+	case CABLE_TYPE_TA_MUIC:
+	case CABLE_TYPE_CARDOCK_MUIC:
+	case CABLE_TYPE_DESKDOCK_MUIC:
+	case CABLE_TYPE_SMARTDOCK_MUIC:
+	case CABLE_TYPE_JIG_UART_OFF_VB_MUIC:
+		is_cable_attached = true;
+		break;
+	default:
+		pr_err("%s: invalid type:%d\n", __func__, cable_type);
+		return -EINVAL;
+	}
+
+#ifdef CONFIG_BATTERY_MAX77693_CHARGER
+	if (!psy) {
+		pr_err("%s: fail to get max77693-charger psy\n", __func__);
+		return 0;
+	}
+
+	value.intval = cable_type;
+	psy->set_property(psy, POWER_SUPPLY_PROP_ONLINE, &value);
+#endif
+
+#if defined(CONFIG_MACH_SLP_NAPLES) || defined(CONFIG_MACH_MIDAS)
+#ifndef CONFIG_MACH_GC1
+	tsp_charger_infom(is_cable_attached);
+#endif
+#endif
+#ifdef CONFIG_JACK_MON
+	jack_event_handler("charger", is_cable_attached);
+#endif
+
+	return 0;
+}
+
+int max77693_get_jig_state(void)
+{
+	pr_info("%s: %d\n", __func__, is_jig_attached);
+	return is_jig_attached;
+}
+EXPORT_SYMBOL(max77693_get_jig_state);
+
+void max77693_set_jig_state(int jig_state)
+{
+	pr_info("%s: %d\n", __func__, jig_state);
+	is_jig_attached = jig_state;
+}
+
+/* usb cable call back function */
+void max77693_muic_usb_cb(u8 usb_mode)
+{
+	struct usb_gadget *gadget = platform_get_drvdata(&s3c_device_usbgadget);
+#ifdef CONFIG_USB_HOST_NOTIFY
+	struct host_notifier_platform_data *host_noti_pdata =
+	    host_notifier_device.dev.platform_data;
+#endif
+
+	pr_info("MUIC usb_cb:%d\n", usb_mode);
+	if (gadget) {
+		switch (usb_mode) {
+		case USB_CABLE_DETACHED:
+			pr_info("usb: muic: USB_CABLE_DETACHED(%d)\n",
+				usb_mode);
+			usb_gadget_vbus_disconnect(gadget);
+			break;
+		case USB_CABLE_ATTACHED:
+			pr_info("usb: muic: USB_CABLE_ATTACHED(%d)\n",
+				usb_mode);
+			usb_gadget_vbus_connect(gadget);
+			break;
+		default:
+			pr_info("usb: muic: invalid mode%d\n", usb_mode);
+		}
+	}
+
+	if (usb_mode == USB_OTGHOST_ATTACHED
+		|| usb_mode == USB_POWERED_HOST_ATTACHED) {
+#ifdef CONFIG_USB_HOST_NOTIFY
+		if (usb_mode == USB_OTGHOST_ATTACHED)
+			host_noti_pdata->booster(1);
+		else
+			host_noti_pdata->powered_booster(1);
+
+		host_noti_pdata->ndev.mode = NOTIFY_HOST_MODE;
+		if (host_noti_pdata->usbhostd_start)
+			host_noti_pdata->usbhostd_start();
+#endif
+#ifdef CONFIG_USB_EHCI_S5P
+		pm_runtime_get_sync(&s5p_device_ehci.dev);
+#endif
+#ifdef CONFIG_USB_OHCI_S5P
+		pm_runtime_get_sync(&s5p_device_ohci.dev);
+#endif
+	} else if (usb_mode == USB_OTGHOST_DETACHED
+		|| usb_mode == USB_POWERED_HOST_DETACHED) {
+#ifdef CONFIG_USB_OHCI_S5P
+		pm_runtime_put_sync(&s5p_device_ohci.dev);
+#endif
+#ifdef CONFIG_USB_EHCI_S5P
+		pm_runtime_put_sync(&s5p_device_ehci.dev);
+#endif
+#ifdef CONFIG_USB_HOST_NOTIFY
+		host_noti_pdata->ndev.mode = NOTIFY_NONE_MODE;
+		if (host_noti_pdata->usbhostd_stop)
+			host_noti_pdata->usbhostd_stop();
+		if (usb_mode == USB_OTGHOST_DETACHED)
+			host_noti_pdata->booster(0);
+		else
+			host_noti_pdata->powered_booster(0);
+#endif
+	}
+
+#ifdef CONFIG_JACK_MON
+	if (usb_mode == USB_OTGHOST_ATTACHED
+	|| usb_mode == USB_POWERED_HOST_ATTACHED)
+		jack_event_handler("host", USB_CABLE_ATTACHED);
+	else if (usb_mode == USB_OTGHOST_DETACHED
+	|| usb_mode == USB_POWERED_HOST_DETACHED)
+		jack_event_handler("host", USB_CABLE_DETACHED);
+	else if ((usb_mode == USB_CABLE_ATTACHED)
+		|| (usb_mode == USB_CABLE_DETACHED))
+		jack_event_handler("usb", usb_mode);
+#endif
+}
+
+/*extern void MHL_On(bool on);*/
+void max77693_muic_mhl_cb(int attached)
+{
+	pr_info("MUIC attached:%d\n", attached);
+	if (attached == MAX77693_MUIC_ATTACHED) {
+		/*MHL_On(1);*/ /* GPIO_LEVEL_HIGH */
+		pr_info("MHL Attached !!\n");
+#ifdef CONFIG_SAMSUNG_MHL
+#ifdef CONFIG_MACH_MIDAS
+		sii9234_wake_lock();
+#endif
+		mhl_onoff_ex(1);
+#endif
+	} else {
+		/*MHL_On(0);*/ /* GPIO_LEVEL_LOW */
+		pr_info("MHL Detached !!\n");
+#ifdef CONFIG_SAMSUNG_MHL
+		mhl_onoff_ex(false);
+#ifdef CONFIG_MACH_MIDAS
+		sii9234_wake_unlock();
+#endif
+#endif
+	}
+}
+
+bool max77693_muic_is_mhl_attached(void)
+{
+	int val;
+#ifdef CONFIG_SAMSUNG_USE_11PIN_CONNECTOR
+	val = max77693_muic_get_status1_adc1k_value();
+	pr_info("%s(1): %d\n", __func__, val);
+	return val;
+#else
+	const int err = -1;
+	int ret;
+
+	ret = gpio_request(GPIO_MHL_SEL, "MHL_SEL");
+	if (ret) {
+			pr_err("fail to request gpio %s\n", "GPIO_MHL_SEL");
+			return err;
+	}
+	val = gpio_get_value(GPIO_MHL_SEL);
+	pr_info("%s(2): %d\n", __func__, val);
+	gpio_free(GPIO_MHL_SEL);
+	return !!val;
+#endif
+}
+
+void max77693_muic_deskdock_cb(bool attached)
+{
+	pr_info("MUIC deskdock attached=%d\n", attached);
+	if (attached) {
+#ifdef CONFIG_JACK_MON
+		jack_event_handler("cradle", 1);
+#endif
+		switch_set_state(&switch_dock, 1);
+	} else {
+#ifdef CONFIG_JACK_MON
+		jack_event_handler("cradle", 0);
+#endif
+		switch_set_state(&switch_dock, 0);
+	}
+}
+
+void max77693_muic_cardock_cb(bool attached)
+{
+	pr_info("MUIC cardock attached=%d\n", attached);
+	pr_info("##MUIC [ %s ]- func : %s !!\n", __FILE__, __func__);
+	if (attached) {
+#ifdef CONFIG_JACK_MON
+		jack_event_handler("cradle", 2);
+#endif
+		switch_set_state(&switch_dock, 2);
+	} else {
+#ifdef CONFIG_JACK_MON
+		jack_event_handler("cradle", 0);
+#endif
+		switch_set_state(&switch_dock, 0);
+	}
+}
+
+void max77693_muic_init_cb(void)
+{
+	int ret;
+
+	/* for CarDock, DeskDock */
+	ret = switch_dev_register(&switch_dock);
+
+	pr_info("MUIC ret=%d\n", ret);
+
+	if (ret < 0)
+		pr_err("Failed to register dock switch. %d\n", ret);
+}
+
+int max77693_muic_cfg_uart_gpio(void)
+{
+	int uart_val, path;
+	pr_info("## MUIC func : %s ! please  path: (uart:%d - usb:%d)\n",
+		__func__, gpio_get_value(GPIO_UART_SEL),
+		gpio_get_value(GPIO_USB_SEL));
+	uart_val = gpio_get_value(GPIO_UART_SEL);
+	path = uart_val ? UART_PATH_AP : UART_PATH_CP;
+#ifdef CONFIG_LTE_VIA_SWITCH
+	if (path == UART_PATH_CP && !gpio_get_value(GPIO_LTE_VIA_UART_SEL))
+		path = UART_PATH_LTE;
+#endif
+	pr_info("##MUIC [ %s ]- func : %s! path:%d\n", __FILE__, __func__,
+		path);
+	return path;
+}
+
+void max77693_muic_jig_uart_cb(int path)
+{
+	pr_info("func:%s : (path=%d\n", __func__, path);
+	switch (path) {
+	case UART_PATH_AP:
+		gpio_set_value(GPIO_UART_SEL, GPIO_LEVEL_HIGH);
+		break;
+	case UART_PATH_CP:
+		gpio_set_value(GPIO_UART_SEL, GPIO_LEVEL_LOW);
+#ifdef CONFIG_LTE_VIA_SWITCH
+		gpio_set_value(GPIO_LTE_VIA_UART_SEL, GPIO_LEVEL_HIGH);
+#endif
+		break;
+#ifdef CONFIG_LTE_VIA_SWITCH
+	case UART_PATH_LTE:
+		gpio_set_value(GPIO_UART_SEL, GPIO_LEVEL_LOW);
+		gpio_set_value(GPIO_LTE_VIA_UART_SEL, GPIO_LEVEL_LOW);
+		break;
+#endif
+	default:
+		pr_info("func %s: invalid value!!\n", __func__);
+	}
+
+}
+
+#ifdef CONFIG_USB_HOST_NOTIFY
+int max77693_muic_host_notify_cb(int enable)
+{
+	struct host_notifier_platform_data *host_noti_pdata =
+	    host_notifier_device.dev.platform_data;
+
+	struct host_notify_dev *ndev = &host_noti_pdata->ndev;
+
+	if (!ndev) {
+		pr_err("%s: ndev is null.\n", __func__);
+		return -1;
+	}
+
+	ndev->booster = enable ? NOTIFY_POWER_ON : NOTIFY_POWER_OFF;
+	pr_info("%s: mode %d, enable %d\n", __func__, ndev->mode, enable);
+	return ndev->mode;
+}
+#endif
+
+int max77693_muic_set_safeout(int path)
+{
+	struct regulator *regulator;
+
+	pr_info("MUIC safeout path=%d\n", path);
+
+	if (path == CP_USB_MODE) {
+		regulator = regulator_get(NULL, "safeout1");
+		if (IS_ERR(regulator))
+			return -ENODEV;
+		if (regulator_is_enabled(regulator))
+			regulator_force_disable(regulator);
+		regulator_put(regulator);
+
+		regulator = regulator_get(NULL, "safeout2");
+		if (IS_ERR(regulator))
+			return -ENODEV;
+		if (!regulator_is_enabled(regulator))
+			regulator_enable(regulator);
+		regulator_put(regulator);
+	} else {
+		/* AP_USB_MODE || AUDIO_MODE */
+		regulator = regulator_get(NULL, "safeout1");
+		if (IS_ERR(regulator))
+			return -ENODEV;
+		if (!regulator_is_enabled(regulator))
+			regulator_enable(regulator);
+		regulator_put(regulator);
+
+		regulator = regulator_get(NULL, "safeout2");
+		if (IS_ERR(regulator))
+			return -ENODEV;
+		if (regulator_is_enabled(regulator))
+			regulator_force_disable(regulator);
+		regulator_put(regulator);
+	}
+
+	return 0;
+}
+
+struct max77693_muic_data max77693_muic = {
+	.usb_cb = max77693_muic_usb_cb,
+	.charger_cb = max77693_muic_charger_cb,
+	.mhl_cb = max77693_muic_mhl_cb,
+	.is_mhl_attached = max77693_muic_is_mhl_attached,
+	.set_safeout = max77693_muic_set_safeout,
+	.init_cb = max77693_muic_init_cb,
+	.deskdock_cb = max77693_muic_deskdock_cb,
+	.cardock_cb = max77693_muic_cardock_cb,
+#if !defined(CONFIG_MACH_GC1)
+	.cfg_uart_gpio = max77693_muic_cfg_uart_gpio,
+	.jig_uart_cb = max77693_muic_jig_uart_cb,
+#endif /* CONFIG_MACH_GC1 */
+#ifdef CONFIG_USB_HOST_NOTIFY
+	.host_notify_cb = max77693_muic_host_notify_cb,
+#else
+	.host_notify_cb = NULL,
+#endif
+#if !defined(CONFIG_MACH_GC1)
+	.gpio_usb_sel = GPIO_USB_SEL,
+#else
+	.gpio_usb_sel = -1,
+#endif /* CONFIG_MACH_GC1 */
+	.jig_state = max77693_set_jig_state,
+};
+
+device_initcall(midas_sec_switch_init);
diff --git a/arch/arm/mach-exynos/sec-switch_max8997.c b/arch/arm/mach-exynos/sec-switch_max8997.c
new file mode 100644
index 0000000..51f9c31
--- /dev/null
+++ b/arch/arm/mach-exynos/sec-switch_max8997.c
@@ -0,0 +1,496 @@
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi_gpio.h>
+#include <linux/gpio.h>
+#include <linux/gpio_keys.h>
+#include <linux/gpio_event.h>
+#include <plat/devs.h>
+#include <plat/gpio-cfg.h>
+#include <linux/i2c.h>
+#include <linux/i2c-gpio.h>
+#include <linux/input.h>
+#include <plat/udc-hs.h>
+/*#include <linux/mmc/host.h>*/
+#include <linux/regulator/machine.h>
+#include <linux/regulator/max8649.h>
+#include <linux/regulator/fixed.h>
+#include <linux/mfd/wm8994/pdata.h>
+#include <linux/mfd/max8997.h>
+#include <linux/mfd/max8997-private.h>
+/* #include <linux/mfd/max77686.h> */
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+
+#ifdef CONFIG_BATTERY_SAMSUNG
+#include <linux/power_supply.h>
+#include <linux/battery/samsung_battery.h>
+#endif
+#include <linux/switch.h>
+#include <linux/sii9234.h>
+
+#ifdef CONFIG_USB_HOST_NOTIFY
+#include <linux/host_notify.h>
+#endif
+#include <linux/pm_runtime.h>
+#include <linux/usb.h>
+#include <linux/usb/hcd.h>
+
+#ifdef CONFIG_JACK_MON
+#include <linux/jack.h>
+#endif
+
+#define MUIC_DEBUG 1
+#ifdef MUIC_DEBUG
+#define MUIC_PRINT_LOG()	\
+	pr_info("MUIC:[%s] func:%s\n", __FILE__, __func__);
+#else
+#define MUIC_PRINT_LOG()	{}
+#endif
+
+static struct switch_dev switch_dock = {
+	.name = "dock",
+};
+
+extern struct class *sec_class;
+
+struct device *switch_dev;
+EXPORT_SYMBOL(switch_dev);
+
+static int uart_switch_init(void);
+
+static ssize_t u1_switch_show_vbus(struct device *dev,
+				      struct device_attribute *attr, char *buf)
+{
+	int i;
+	struct regulator *regulator;
+
+	regulator = regulator_get(NULL, "safeout1");
+	if (IS_ERR(regulator)) {
+		pr_warn("%s: fail to get regulator\n", __func__);
+		return sprintf(buf, "UNKNOWN\n");
+	}
+	if (regulator_is_enabled(regulator))
+		i = sprintf(buf, "VBUS is enabled\n");
+	else
+		i = sprintf(buf, "VBUS is disabled\n");
+	MUIC_PRINT_LOG();
+	regulator_put(regulator);
+
+	return i;
+}
+
+static ssize_t u1_switch_store_vbus(struct device *dev,
+				       struct device_attribute *attr,
+				       const char *buf, size_t count)
+{
+	int disable, ret, usb_mode;
+	struct regulator *regulator;
+	/* struct s3c_udc *udc = platform_get_drvdata(&s3c_device_usbgadget); */
+
+	MUIC_PRINT_LOG();
+	if (!strncmp(buf, "0", 1))
+		disable = 0;
+	else if (!strncmp(buf, "1", 1))
+		disable = 1;
+	else {
+		pr_warn("%s: Wrong command\n", __func__);
+		return count;
+	}
+
+	pr_info("%s: disable=%d\n", __func__, disable);
+	usb_mode =
+	    disable ? USB_CABLE_DETACHED_WITHOUT_NOTI : USB_CABLE_ATTACHED;
+	/* ret = udc->change_usb_mode(usb_mode); */
+	ret = -1;
+	if (ret < 0)
+		pr_err("%s: fail to change mode!!!\n", __func__);
+
+	regulator = regulator_get(NULL, "safeout1");
+	if (IS_ERR(regulator)) {
+		pr_warn("%s: fail to get regulator\n", __func__);
+		return count;
+	}
+
+	if (disable) {
+		if (regulator_is_enabled(regulator))
+			regulator_force_disable(regulator);
+		if (!regulator_is_enabled(regulator))
+			regulator_enable(regulator);
+	} else {
+		if (!regulator_is_enabled(regulator))
+			regulator_enable(regulator);
+	}
+	regulator_put(regulator);
+
+	return count;
+}
+
+DEVICE_ATTR(disable_vbus, 0664, u1_switch_show_vbus,
+	    u1_switch_store_vbus);
+
+#ifdef CONFIG_TARGET_LOCALE_KOR
+#include "../../../drivers/usb/gadget/s3c_udc.h"
+/* usb access control for SEC DM */
+struct device *usb_lock;
+static int is_usb_locked;
+
+int u1_switch_get_usb_lock_state(void)
+{
+	return is_usb_locked;
+}
+EXPORT_SYMBOL(u1_switch_get_usb_lock_state);
+
+static ssize_t u1_switch_show_usb_lock(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	if (is_usb_locked)
+		return snprintf(buf, PAGE_SIZE, "USB_LOCK");
+	else
+		return snprintf(buf, PAGE_SIZE, "USB_UNLOCK");
+}
+
+static ssize_t u1_switch_store_usb_lock(struct device *dev,
+				struct device_attribute *attr,
+				const char *buf, size_t count)
+{
+	int lock;
+	struct s3c_udc *udc = platform_get_drvdata(&s3c_device_usbgadget);
+
+	if (!strncmp(buf, "0", 1))
+		lock = 0;
+	else if (!strncmp(buf, "1", 1))
+		lock = 1;
+	else {
+		pr_warn("%s: Wrong command\n", __func__);
+		return count;
+	}
+
+	if (IS_ERR_OR_NULL(udc))
+		return count;
+
+	pr_info("%s: lock=%d\n", __func__, lock);
+
+	if (lock != is_usb_locked) {
+		is_usb_locked = lock;
+
+		if (lock) {
+			if (udc->udc_enabled)
+				usb_gadget_vbus_disconnect(&udc->gadget);
+		}
+	}
+
+	return count;
+}
+
+static DEVICE_ATTR(enable, 0664,
+		   u1_switch_show_usb_lock, u1_switch_store_usb_lock);
+#endif
+
+static int __init u1_sec_switch_init(void)
+{
+	int ret;
+	switch_dev = device_create(sec_class, NULL, 0, NULL, "switch");
+
+	if (IS_ERR(switch_dev))
+		pr_err("Failed to create device(switch)!\n");
+
+	ret = device_create_file(switch_dev, &dev_attr_disable_vbus);
+	if (ret)
+		pr_err("Failed to create device file(disable_vbus)!\n");
+
+#ifdef CONFIG_TARGET_LOCALE_KOR
+	usb_lock = device_create(sec_class, switch_dev,
+				MKDEV(0, 0), NULL, ".usb_lock");
+
+	if (IS_ERR(usb_lock))
+		pr_err("Failed to create device (usb_lock)!\n");
+
+	if (device_create_file(usb_lock, &dev_attr_enable) < 0)
+		pr_err("Failed to create device file(.usblock/enable)!\n");
+#endif
+
+#if !defined(CONFIG_MACH_U1CAMERA_BD)
+	ret = uart_switch_init();
+	if (ret)
+		pr_err("Failed to create uart_switch\n");
+#endif /* CONFIG_MACH_U1CAMERA_BD */
+
+	return 0;
+};
+
+static int uart_switch_init(void)
+{
+	int ret, val;
+	MUIC_PRINT_LOG();
+
+	ret = gpio_request(GPIO_UART_SEL, "UART_SEL");
+	if (ret < 0) {
+		pr_err("Failed to request GPIO_UART_SEL!\n");
+		return -ENODEV;
+	}
+	s3c_gpio_setpull(GPIO_UART_SEL, S3C_GPIO_PULL_NONE);
+	val = gpio_get_value(GPIO_UART_SEL);
+	pr_info("##MUIC [ %s ]- func : %s !! val:-%d-\n", __FILE__, __func__,
+		val);
+	gpio_direction_output(GPIO_UART_SEL, val);
+
+	gpio_export(GPIO_UART_SEL, 1);
+
+	gpio_export_link(switch_dev, "uart_sel", GPIO_UART_SEL);
+
+	return 0;
+}
+
+#if 0
+int max77693_muic_charger_cb(enum cable_type_muic cable_type)
+{
+	MUIC_PRINT_LOG();
+	return 0;
+}
+
+#define RETRY_CNT_LIMIT 100
+/* usb cable call back function */
+void max77693_muic_usb_cb(u8 usb_mode)
+{
+	struct usb_gadget *gadget = platform_get_drvdata(&s3c_device_usbgadget);
+#ifdef CONFIG_USB_EHCI_S5P
+	struct usb_hcd *ehci_hcd = platform_get_drvdata(&s5p_device_ehci);
+#endif
+#ifdef CONFIG_USB_OHCI_S5P
+	struct usb_hcd *ohci_hcd = platform_get_drvdata(&s5p_device_ohci);
+#endif
+#ifdef CONFIG_USB_HOST_NOTIFY
+	struct host_notifier_platform_data *host_noti_pdata =
+	    host_notifier_device.dev.platform_data;
+#endif
+	int retry_cnt = 1;
+
+	pr_info("MUIC usb_cb:%d\n", usb_mode);
+	if (gadget) {
+		switch (usb_mode) {
+		case USB_CABLE_DETACHED:
+			pr_info("usb: muic: USB_CABLE_DETACHED(%d)\n",
+				usb_mode);
+			usb_gadget_vbus_disconnect(gadget);
+			break;
+		case USB_CABLE_ATTACHED:
+			pr_info("usb: muic: USB_CABLE_ATTACHED(%d)\n",
+				usb_mode);
+			usb_gadget_vbus_connect(gadget);
+			break;
+		default:
+			pr_info("usb: muic: invalid mode%d\n", usb_mode);
+		}
+	}
+
+	if (usb_mode == USB_OTGHOST_ATTACHED) {
+#ifdef CONFIG_USB_EHCI_S5P
+		pm_runtime_get_sync(&s5p_device_ehci.dev);
+#endif
+#ifdef CONFIG_USB_OHCI_S5P
+		pm_runtime_get_sync(&s5p_device_ohci.dev);
+#endif
+#ifdef CONFIG_USB_HOST_NOTIFY
+		host_noti_pdata->ndev.mode = NOTIFY_HOST_MODE;
+		if (host_noti_pdata->usbhostd_start)
+			host_noti_pdata->usbhostd_start();
+
+		host_noti_pdata->booster(1);
+#endif
+	} else if (usb_mode == USB_OTGHOST_DETACHED) {
+#ifdef CONFIG_USB_EHCI_S5P
+		pm_runtime_put_sync(&s5p_device_ehci.dev);
+		/* waiting for ehci root hub suspend is done */
+		while (ehci_hcd->state != HC_STATE_SUSPENDED) {
+			msleep(50);
+			if (retry_cnt++ > RETRY_CNT_LIMIT) {
+				printk(KERN_ERR "ehci suspend not completed\n");
+				break;
+			}
+		}
+#endif
+#ifdef CONFIG_USB_OHCI_S5P
+		pm_runtime_put_sync(&s5p_device_ohci.dev);
+		/* waiting for ohci root hub suspend is done */
+		while (ohci_hcd->state != HC_STATE_SUSPENDED) {
+			msleep(50);
+			if (retry_cnt++ > RETRY_CNT_LIMIT) {
+				printk(KERN_ERR
+				       "ohci suspend is not completed\n");
+				break;
+			}
+		}
+#endif
+#ifdef CONFIG_USB_HOST_NOTIFY
+		host_noti_pdata->ndev.mode = NOTIFY_NONE_MODE;
+		if (host_noti_pdata->usbhostd_stop)
+			host_noti_pdata->usbhostd_stop();
+
+		host_noti_pdata->booster(0);
+#endif
+	}
+
+#ifdef CONFIG_JACK_MON
+	if (usb_mode == USB_OTGHOST_ATTACHED)
+		jack_event_handler("host", USB_CABLE_ATTACHED);
+	else if (usb_mode == USB_OTGHOST_DETACHED)
+		jack_event_handler("host", USB_CABLE_DETACHED);
+	else if ((usb_mode == USB_CABLE_ATTACHED)
+		|| (usb_mode == USB_CABLE_DETACHED))
+		jack_event_handler("usb", usb_mode);
+#endif
+}
+
+/*extern void MHL_On(bool on);*/
+void max77693_muic_mhl_cb(int attached)
+{
+	MUIC_PRINT_LOG();
+	pr_info("MUIC attached:%d\n", attached);
+	if (attached == MAX77693_MUIC_ATTACHED) {
+		/*MHL_On(1);*/ /* GPIO_LEVEL_HIGH */
+		pr_info("MHL Attached !!\n");
+#ifdef	CONFIG_SAMSUNG_MHL
+		sii9234_mhl_detection_sched();
+#endif
+	} else {
+		/*MHL_On(0);*/ /* GPIO_LEVEL_LOW */
+		pr_info("MHL Detached !!\n");
+	}
+}
+
+bool max77693_muic_is_mhl_attached(void)
+{
+	int val;
+	MUIC_PRINT_LOG();
+	gpio_request(GPIO_MHL_SEL, "MHL_SEL");
+	val = gpio_get_value(GPIO_MHL_SEL);
+	pr_info("MUIC val:%d\n", val);
+	gpio_free(GPIO_MHL_SEL);
+
+	return !!val;
+}
+
+void max77693_muic_deskdock_cb(bool attached)
+{
+	MUIC_PRINT_LOG();
+	pr_info("MUIC deskdock attached=%d\n", attached);
+	if (attached)
+		switch_set_state(&switch_dock, 1);
+	else
+		switch_set_state(&switch_dock, 0);
+}
+
+void max77693_muic_cardock_cb(bool attached)
+{
+	MUIC_PRINT_LOG();
+	pr_info("MUIC cardock attached=%d\n", attached);
+	pr_info("##MUIC [ %s ]- func : %s !!\n", __FILE__, __func__);
+	if (attached)
+		switch_set_state(&switch_dock, 2);
+	else
+		switch_set_state(&switch_dock, 0);
+}
+
+void max77693_muic_init_cb(void)
+{
+	int ret;
+
+	/* for CarDock, DeskDock */
+	ret = switch_dev_register(&switch_dock);
+
+	MUIC_PRINT_LOG();
+	pr_info("MUIC ret=%d\n", ret);
+
+	if (ret < 0)
+		pr_err("Failed to register dock switch. %d\n", ret);
+}
+
+int max77693_muic_cfg_uart_gpio(void)
+{
+	int val, path;
+	pr_info("## MUIC func : %s ! please  path: (uart:%d - usb:%d)\n",
+		__func__, gpio_get_value(GPIO_UART_SEL),
+		gpio_get_value(GPIO_USB_SEL));
+	val = gpio_get_value(GPIO_UART_SEL);
+	path = val ? UART_PATH_AP : UART_PATH_CP;
+	pr_info("##MUIC [ %s ]- func : %s !! -- val:%d -- path:%d\n", __FILE__,
+		__func__, val, path);
+
+	return path;
+}
+
+void max77693_muic_jig_uart_cb(int path)
+{
+	int val;
+
+	val = path == UART_PATH_AP ? 1 : 0;
+	pr_info("##MUIC [ %s ]- func : %s !! -- val:%d\n", __FILE__, __func__,
+		val);
+	gpio_set_value(GPIO_UART_SEL, val);
+}
+
+int max77693_muic_host_notify_cb(int enable)
+{
+	MUIC_PRINT_LOG();
+	pr_info("MUIC host_noti enable=%d\n", enable);
+	return 0;
+}
+
+int max77693_muic_set_safeout(int path)
+{
+	struct regulator *regulator;
+
+	MUIC_PRINT_LOG();
+	pr_info("MUIC safeout path=%d\n", path);
+
+	if (path == CP_USB_MODE) {
+		regulator = regulator_get(NULL, "safeout1");
+		if (IS_ERR(regulator))
+			return -ENODEV;
+		if (regulator_is_enabled(regulator))
+			regulator_force_disable(regulator);
+		regulator_put(regulator);
+
+		regulator = regulator_get(NULL, "safeout2");
+		if (IS_ERR(regulator))
+			return -ENODEV;
+		if (!regulator_is_enabled(regulator))
+			regulator_enable(regulator);
+		regulator_put(regulator);
+	} else {
+		/* AP_USB_MODE || AUDIO_MODE */
+		regulator = regulator_get(NULL, "safeout1");
+		if (IS_ERR(regulator))
+			return -ENODEV;
+		if (!regulator_is_enabled(regulator))
+			regulator_enable(regulator);
+		regulator_put(regulator);
+
+		regulator = regulator_get(NULL, "safeout2");
+		if (IS_ERR(regulator))
+			return -ENODEV;
+		if (regulator_is_enabled(regulator))
+			regulator_force_disable(regulator);
+		regulator_put(regulator);
+	}
+
+	return 0;
+}
+
+struct max77693_muic_data max77693_muic = {
+	.usb_cb = max77693_muic_usb_cb,
+	.charger_cb = max77693_muic_charger_cb,
+	.mhl_cb = max77693_muic_mhl_cb,
+	.is_mhl_attached = max77693_muic_is_mhl_attached,
+	.set_safeout = max77693_muic_set_safeout,
+	.init_cb = max77693_muic_init_cb,
+	.deskdock_cb = max77693_muic_deskdock_cb,
+	.cardock_cb = max77693_muic_cardock_cb,
+	.cfg_uart_gpio = max77693_muic_cfg_uart_gpio,
+	.jig_uart_cb = max77693_muic_jig_uart_cb,
+	.host_notify_cb = max77693_muic_host_notify_cb,
+	.gpio_usb_sel = GPIO_USB_SEL,
+};
+#endif
+
+device_initcall(u1_sec_switch_init);
diff --git a/arch/arm/mach-exynos/sec_debug.c b/arch/arm/mach-exynos/sec_debug.c
new file mode 100644
index 0000000..2e19097
--- /dev/null
+++ b/arch/arm/mach-exynos/sec_debug.c
@@ -0,0 +1,1241 @@
+/*
+ *  sec_debug.c
+ *
+ */
+
+#include <linux/errno.h>
+#include <linux/ctype.h>
+#include <linux/notifier.h>
+#include <linux/reboot.h>
+#include <linux/input.h>
+#include <linux/delay.h>
+#include <mach/regs-pmu.h>
+#include <asm/cacheflush.h>
+#include <asm/io.h>
+#include <linux/sched.h>
+#include <linux/smp.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/uaccess.h>
+#include <linux/proc_fs.h>
+#include <linux/bootmem.h>
+#include <linux/kmsg_dump.h>
+#include <linux/kallsyms.h>
+#include <linux/ptrace.h>
+#include <linux/interrupt.h>
+#include <linux/kernel_stat.h>
+
+#include <plat/system-reset.h>
+#include <mach/sec_debug.h>
+#include <plat/map-base.h>
+#include <plat/map-s5p.h>
+#include <asm/mach/map.h>
+#include <plat/regs-watchdog.h>
+
+/* klaatu - schedule log */
+#ifdef CONFIG_SEC_DEBUG_SCHED_LOG
+#define SCHED_LOG_MAX 2048
+
+struct sched_log {
+	struct task_log {
+		unsigned long long time;
+		char comm[TASK_COMM_LEN];
+		pid_t pid;
+	} task[NR_CPUS][SCHED_LOG_MAX];
+	struct irq_log {
+		unsigned long long time;
+		int irq;
+		void *fn;
+		int en;
+	} irq[NR_CPUS][SCHED_LOG_MAX];
+	struct work_log {
+		unsigned long long time;
+		struct worker *worker;
+		struct work_struct *work;
+		work_func_t f;
+	} work[NR_CPUS][SCHED_LOG_MAX];
+};
+#endif				/* CONFIG_SEC_DEBUG_SCHED_LOG */
+
+#ifdef CONFIG_SEC_DEBUG_AUXILIARY_LOG
+#define AUX_LOG_CPU_CLOCK_MAX 64
+#define AUX_LOG_LOGBUF_LOCK_MAX 64
+#define AUX_LOG_LENGTH 128
+
+struct auxiliary_info {
+	unsigned long long time;
+	int cpu;
+	char log[AUX_LOG_LENGTH];
+};
+
+/* This structure will be modified if some other items added for log */
+struct auxiliary_log {
+	struct auxiliary_info CpuClockLog[AUX_LOG_CPU_CLOCK_MAX];
+	struct auxiliary_info LogBufLockLog[AUX_LOG_LOGBUF_LOCK_MAX];
+};
+
+#else
+#endif
+
+#ifdef CONFIG_SEC_DEBUG_SEMAPHORE_LOG
+#define SEMAPHORE_LOG_MAX 100
+struct sem_debug {
+	struct list_head list;
+	struct semaphore *sem;
+	struct task_struct *task;
+	pid_t pid;
+	int cpu;
+	/* char comm[TASK_COMM_LEN]; */
+};
+
+enum {
+	READ_SEM,
+	WRITE_SEM
+};
+
+#define RWSEMAPHORE_LOG_MAX 100
+struct rwsem_debug {
+	struct list_head list;
+	struct rw_semaphore *sem;
+	struct task_struct *task;
+	pid_t pid;
+	int cpu;
+	int direction;
+	/* char comm[TASK_COMM_LEN]; */
+};
+
+#endif	/* CONFIG_SEC_DEBUG_SEMAPHORE_LOG */
+
+/* layout of SDRAM
+	   0: magic (4B)
+      4~1023: panic string (1020B)
+ 1024~0x1000: panic dumper log
+      0x4000: copy of magic
+ */
+#define SEC_DEBUG_MAGIC_PA S5P_PA_SDRAM
+#define SEC_DEBUG_MAGIC_VA phys_to_virt(SEC_DEBUG_MAGIC_PA)
+
+enum sec_debug_upload_cause_t {
+	UPLOAD_CAUSE_INIT = 0xCAFEBABE,
+	UPLOAD_CAUSE_KERNEL_PANIC = 0x000000C8,
+	UPLOAD_CAUSE_FORCED_UPLOAD = 0x00000022,
+	UPLOAD_CAUSE_CP_ERROR_FATAL = 0x000000CC,
+	UPLOAD_CAUSE_USER_FAULT = 0x0000002F,
+	UPLOAD_CAUSE_HSIC_DISCONNECTED = 0x000000DD,
+};
+
+struct sec_debug_mmu_reg_t {
+	int SCTLR;
+	int TTBR0;
+	int TTBR1;
+	int TTBCR;
+	int DACR;
+	int DFSR;
+	int DFAR;
+	int IFSR;
+	int IFAR;
+	int DAFSR;
+	int IAFSR;
+	int PMRRR;
+	int NMRRR;
+	int FCSEPID;
+	int CONTEXT;
+	int URWTPID;
+	int UROTPID;
+	int POTPIDR;
+};
+
+/* ARM CORE regs mapping structure */
+struct sec_debug_core_t {
+	/* COMMON */
+	unsigned int r0;
+	unsigned int r1;
+	unsigned int r2;
+	unsigned int r3;
+	unsigned int r4;
+	unsigned int r5;
+	unsigned int r6;
+	unsigned int r7;
+	unsigned int r8;
+	unsigned int r9;
+	unsigned int r10;
+	unsigned int r11;
+	unsigned int r12;
+
+	/* SVC */
+	unsigned int r13_svc;
+	unsigned int r14_svc;
+	unsigned int spsr_svc;
+
+	/* PC & CPSR */
+	unsigned int pc;
+	unsigned int cpsr;
+
+	/* USR/SYS */
+	unsigned int r13_usr;
+	unsigned int r14_usr;
+
+	/* FIQ */
+	unsigned int r8_fiq;
+	unsigned int r9_fiq;
+	unsigned int r10_fiq;
+	unsigned int r11_fiq;
+	unsigned int r12_fiq;
+	unsigned int r13_fiq;
+	unsigned int r14_fiq;
+	unsigned int spsr_fiq;
+
+	/* IRQ */
+	unsigned int r13_irq;
+	unsigned int r14_irq;
+	unsigned int spsr_irq;
+
+	/* MON */
+	unsigned int r13_mon;
+	unsigned int r14_mon;
+	unsigned int spsr_mon;
+
+	/* ABT */
+	unsigned int r13_abt;
+	unsigned int r14_abt;
+	unsigned int spsr_abt;
+
+	/* UNDEF */
+	unsigned int r13_und;
+	unsigned int r14_und;
+	unsigned int spsr_und;
+
+};
+
+/* enable/disable sec_debug feature
+ * level = 0 when enable = 0 && enable_user = 0
+ * level = 1 when enable = 1 && enable_user = 0
+ * level = 0x10001 when enable = 1 && enable_user = 1
+ * The other cases are not considered
+ */
+union sec_debug_level_t sec_debug_level = { .en.kernel_fault = 1, };
+
+module_param_named(enable, sec_debug_level.en.kernel_fault, ushort, 0644);
+module_param_named(enable_user, sec_debug_level.en.user_fault, ushort, 0644);
+module_param_named(level, sec_debug_level.uint_val, uint, 0644);
+
+/* klaatu - schedule log */
+#ifdef CONFIG_SEC_DEBUG_SCHED_LOG
+static struct sched_log sec_debug_log __cacheline_aligned;
+/*
+static struct sched_log sec_debug_log[NR_CPUS][SCHED_LOG_MAX]
+	__cacheline_aligned;
+*/
+static atomic_t task_log_idx[NR_CPUS] = { ATOMIC_INIT(-1), ATOMIC_INIT(-1) };
+static atomic_t irq_log_idx[NR_CPUS] = { ATOMIC_INIT(-1), ATOMIC_INIT(-1) };
+static atomic_t work_log_idx[NR_CPUS] = { ATOMIC_INIT(-1), ATOMIC_INIT(-1) };
+static struct sched_log (*psec_debug_log) = (&sec_debug_log);
+/*
+static struct sched_log (*psec_debug_log)[NR_CPUS][SCHED_LOG_MAX]
+	= (&sec_debug_log);
+*/
+#ifdef CONFIG_SEC_DEBUG_IRQ_EXIT_LOG
+static unsigned long long gExcpIrqExitTime[NR_CPUS];
+#endif
+
+#ifdef CONFIG_SEC_DEBUG_AUXILIARY_LOG
+static struct auxiliary_log gExcpAuxLog	__cacheline_aligned;
+static struct auxiliary_log *gExcpAuxLogPtr;
+static atomic_t gExcpAuxCpuClockLogIdx = ATOMIC_INIT(-1);
+static atomic_t gExcpAuxLogBufLockLogIdx = ATOMIC_INIT(-1);
+#endif
+
+static int checksum_sched_log(void)
+{
+	int sum = 0, i;
+	for (i = 0; i < sizeof(sec_debug_log); i++)
+		sum += *((char *)&sec_debug_log + i);
+
+	return sum;
+}
+
+#ifdef CONFIG_SEC_DEBUG_SCHED_LOG_NONCACHED
+static void map_noncached_sched_log_buf(void)
+{
+	struct map_desc slog_buf_iodesc[] = {
+		{
+			.virtual = (unsigned long)S3C_VA_SLOG_BUF,
+			.length = 0x200000,
+			.type = MT_DEVICE
+		}
+	};
+
+	slog_buf_iodesc[0].pfn = __phys_to_pfn
+		((unsigned long)((virt_to_phys(&sec_debug_log)&0xfff00000)));
+	iotable_init(slog_buf_iodesc, ARRAY_SIZE(slog_buf_iodesc));
+	psec_debug_log = (void *)(S3C_VA_SLOG_BUF +
+		(((unsigned long)(&sec_debug_log))&0x000fffff));
+}
+#endif
+
+#ifdef CONFIG_SEC_DEBUG_AUXILIARY_LOG
+static void map_noncached_aux_log_buf(void)
+{
+	struct map_desc auxlog_buf_iodesc[] = {
+		{
+			.virtual = (unsigned long)S3C_VA_AUXLOG_BUF,
+			.length = 0x200000,
+			.type = MT_DEVICE
+		}
+	};
+
+	auxlog_buf_iodesc[0].pfn = __phys_to_pfn
+		((unsigned long)((virt_to_phys(&gExcpAuxLog)&0xfff00000)));
+	iotable_init(auxlog_buf_iodesc, ARRAY_SIZE(auxlog_buf_iodesc));
+	gExcpAuxLogPtr = (void *)(S3C_VA_AUXLOG_BUF +
+		(((unsigned long)(&gExcpAuxLog))&0x000fffff));
+}
+#endif
+
+#else
+static int checksum_sched_log(void)
+{
+	return 0;
+}
+#endif
+
+/* klaatu - semaphore log */
+#ifdef CONFIG_SEC_DEBUG_SEMAPHORE_LOG
+struct sem_debug sem_debug_free_head;
+struct sem_debug sem_debug_done_head;
+int sem_debug_free_head_cnt;
+int sem_debug_done_head_cnt;
+int sem_debug_init = 0;
+spinlock_t sem_debug_lock;
+
+/* rwsemaphore logging */
+struct rwsem_debug rwsem_debug_free_head;
+struct rwsem_debug rwsem_debug_done_head;
+int rwsem_debug_free_head_cnt;
+int rwsem_debug_done_head_cnt;
+int rwsem_debug_init = 0;
+spinlock_t rwsem_debug_lock;
+
+#endif /* CONFIG_SEC_DEBUG_SEMAPHORE_LOG */
+
+DEFINE_PER_CPU(struct sec_debug_core_t, sec_debug_core_reg);
+DEFINE_PER_CPU(struct sec_debug_mmu_reg_t, sec_debug_mmu_reg);
+DEFINE_PER_CPU(enum sec_debug_upload_cause_t, sec_debug_upload_cause);
+
+/* core reg dump function*/
+static inline void sec_debug_save_core_reg(struct sec_debug_core_t *core_reg)
+{
+	/* we will be in SVC mode when we enter this function. Collect
+	   SVC registers along with cmn registers. */
+	asm("str r0, [%0,#0]\n\t"	/* R0 is pushed first to core_reg */
+	    "mov r0, %0\n\t"		/* R0 will be alias for core_reg */
+	    "str r1, [r0,#4]\n\t"	/* R1 */
+	    "str r2, [r0,#8]\n\t"	/* R2 */
+	    "str r3, [r0,#12]\n\t"	/* R3 */
+	    "str r4, [r0,#16]\n\t"	/* R4 */
+	    "str r5, [r0,#20]\n\t"	/* R5 */
+	    "str r6, [r0,#24]\n\t"	/* R6 */
+	    "str r7, [r0,#28]\n\t"	/* R7 */
+	    "str r8, [r0,#32]\n\t"	/* R8 */
+	    "str r9, [r0,#36]\n\t"	/* R9 */
+	    "str r10, [r0,#40]\n\t"	/* R10 */
+	    "str r11, [r0,#44]\n\t"	/* R11 */
+	    "str r12, [r0,#48]\n\t"	/* R12 */
+	    /* SVC */
+	    "str r13, [r0,#52]\n\t"	/* R13_SVC */
+	    "str r14, [r0,#56]\n\t"	/* R14_SVC */
+	    "mrs r1, spsr\n\t"		/* SPSR_SVC */
+	    "str r1, [r0,#60]\n\t"
+	    /* PC and CPSR */
+	    "sub r1, r15, #0x4\n\t"	/* PC */
+	    "str r1, [r0,#64]\n\t"
+	    "mrs r1, cpsr\n\t"		/* CPSR */
+	    "str r1, [r0,#68]\n\t"
+	    /* SYS/USR */
+	    "mrs r1, cpsr\n\t"		/* switch to SYS mode */
+	    "and r1, r1, #0xFFFFFFE0\n\t"
+	    "orr r1, r1, #0x1f\n\t"
+	    "msr cpsr,r1\n\t"
+	    "str r13, [r0,#72]\n\t"	/* R13_USR */
+	    "str r14, [r0,#76]\n\t"	/* R14_USR */
+	    /* FIQ */
+	    "mrs r1, cpsr\n\t"		/* switch to FIQ mode */
+	    "and r1,r1,#0xFFFFFFE0\n\t"
+	    "orr r1,r1,#0x11\n\t"
+	    "msr cpsr,r1\n\t"
+	    "str r8, [r0,#80]\n\t"	/* R8_FIQ */
+	    "str r9, [r0,#84]\n\t"	/* R9_FIQ */
+	    "str r10, [r0,#88]\n\t"	/* R10_FIQ */
+	    "str r11, [r0,#92]\n\t"	/* R11_FIQ */
+	    "str r12, [r0,#96]\n\t"	/* R12_FIQ */
+	    "str r13, [r0,#100]\n\t"	/* R13_FIQ */
+	    "str r14, [r0,#104]\n\t"	/* R14_FIQ */
+	    "mrs r1, spsr\n\t"		/* SPSR_FIQ */
+	    "str r1, [r0,#108]\n\t"
+	    /* IRQ */
+	    "mrs r1, cpsr\n\t"		/* switch to IRQ mode */
+	    "and r1, r1, #0xFFFFFFE0\n\t"
+	    "orr r1, r1, #0x12\n\t"
+	    "msr cpsr,r1\n\t"
+	    "str r13, [r0,#112]\n\t"	/* R13_IRQ */
+	    "str r14, [r0,#116]\n\t"	/* R14_IRQ */
+	    "mrs r1, spsr\n\t"		/* SPSR_IRQ */
+	    "str r1, [r0,#120]\n\t"
+	    /* MON */
+	    "mrs r1, cpsr\n\t"		/* switch to monitor mode */
+	    "and r1, r1, #0xFFFFFFE0\n\t"
+	    "orr r1, r1, #0x16\n\t"
+	    "msr cpsr,r1\n\t"
+	    "str r13, [r0,#124]\n\t"	/* R13_MON */
+	    "str r14, [r0,#128]\n\t"	/* R14_MON */
+	    "mrs r1, spsr\n\t"		/* SPSR_MON */
+	    "str r1, [r0,#132]\n\t"
+	    /* ABT */
+	    "mrs r1, cpsr\n\t"		/* switch to Abort mode */
+	    "and r1, r1, #0xFFFFFFE0\n\t"
+	    "orr r1, r1, #0x17\n\t"
+	    "msr cpsr,r1\n\t"
+	    "str r13, [r0,#136]\n\t"	/* R13_ABT */
+	    "str r14, [r0,#140]\n\t"	/* R14_ABT */
+	    "mrs r1, spsr\n\t"		/* SPSR_ABT */
+	    "str r1, [r0,#144]\n\t"
+	    /* UND */
+	    "mrs r1, cpsr\n\t"		/* switch to undef mode */
+	    "and r1, r1, #0xFFFFFFE0\n\t"
+	    "orr r1, r1, #0x1B\n\t"
+	    "msr cpsr,r1\n\t"
+	    "str r13, [r0,#148]\n\t"	/* R13_UND */
+	    "str r14, [r0,#152]\n\t"	/* R14_UND */
+	    "mrs r1, spsr\n\t"		/* SPSR_UND */
+	    "str r1, [r0,#156]\n\t"
+	    /* restore to SVC mode */
+	    "mrs r1, cpsr\n\t"		/* switch to SVC mode */
+	    "and r1, r1, #0xFFFFFFE0\n\t"
+	    "orr r1, r1, #0x13\n\t"
+	    "msr cpsr,r1\n\t" :		/* output */
+	    : "r"(core_reg)		/* input */
+	    : "%r0", "%r1"		/* clobbered registers */
+	);
+
+	return;
+}
+
+static inline void sec_debug_save_mmu_reg(struct sec_debug_mmu_reg_t *mmu_reg)
+{
+	asm("mrc    p15, 0, r1, c1, c0, 0\n\t"	/* SCTLR */
+	    "str r1, [%0]\n\t"
+	    "mrc    p15, 0, r1, c2, c0, 0\n\t"	/* TTBR0 */
+	    "str r1, [%0,#4]\n\t"
+	    "mrc    p15, 0, r1, c2, c0,1\n\t"	/* TTBR1 */
+	    "str r1, [%0,#8]\n\t"
+	    "mrc    p15, 0, r1, c2, c0,2\n\t"	/* TTBCR */
+	    "str r1, [%0,#12]\n\t"
+	    "mrc    p15, 0, r1, c3, c0,0\n\t"	/* DACR */
+	    "str r1, [%0,#16]\n\t"
+	    "mrc    p15, 0, r1, c5, c0,0\n\t"	/* DFSR */
+	    "str r1, [%0,#20]\n\t"
+	    "mrc    p15, 0, r1, c6, c0,0\n\t"	/* DFAR */
+	    "str r1, [%0,#24]\n\t"
+	    "mrc    p15, 0, r1, c5, c0,1\n\t"	/* IFSR */
+	    "str r1, [%0,#28]\n\t"
+	    "mrc    p15, 0, r1, c6, c0,2\n\t"	/* IFAR */
+	    "str r1, [%0,#32]\n\t"
+	    /* Don't populate DAFSR and RAFSR */
+	    "mrc    p15, 0, r1, c10, c2,0\n\t"	/* PMRRR */
+	    "str r1, [%0,#44]\n\t"
+	    "mrc    p15, 0, r1, c10, c2,1\n\t"	/* NMRRR */
+	    "str r1, [%0,#48]\n\t"
+	    "mrc    p15, 0, r1, c13, c0,0\n\t"	/* FCSEPID */
+	    "str r1, [%0,#52]\n\t"
+	    "mrc    p15, 0, r1, c13, c0,1\n\t"	/* CONTEXT */
+	    "str r1, [%0,#56]\n\t"
+	    "mrc    p15, 0, r1, c13, c0,2\n\t"	/* URWTPID */
+	    "str r1, [%0,#60]\n\t"
+	    "mrc    p15, 0, r1, c13, c0,3\n\t"	/* UROTPID */
+	    "str r1, [%0,#64]\n\t"
+	    "mrc    p15, 0, r1, c13, c0,4\n\t"	/* POTPIDR */
+	    "str r1, [%0,#68]\n\t" :		/* output */
+	    : "r"(mmu_reg)			/* input */
+	    : "%r1", "memory"			/* clobbered register */
+	);
+}
+
+static inline void sec_debug_save_context(void)
+{
+	unsigned long flags;
+	local_irq_save(flags);
+	sec_debug_save_mmu_reg(&per_cpu(sec_debug_mmu_reg, smp_processor_id()));
+	sec_debug_save_core_reg(&per_cpu
+				(sec_debug_core_reg, smp_processor_id()));
+
+	pr_emerg("(%s) context saved(CPU:%d)\n", __func__, smp_processor_id());
+	local_irq_restore(flags);
+}
+
+static void sec_debug_set_upload_magic(unsigned magic, char *str)
+{
+	pr_emerg("(%s) %x\n", __func__, magic);
+
+	*(unsigned int *)SEC_DEBUG_MAGIC_VA = magic;
+	*(unsigned int *)(SEC_DEBUG_MAGIC_VA + 0x4000) = magic;
+
+	if (str)
+		strncpy((char *)SEC_DEBUG_MAGIC_VA + 4, str, SZ_1K - 4);
+
+	flush_cache_all();
+
+	outer_flush_all();
+}
+
+static int sec_debug_normal_reboot_handler(struct notifier_block *nb,
+					   unsigned long l, void *p)
+{
+	sec_debug_set_upload_magic(0x0, NULL);
+
+	return 0;
+}
+
+static void sec_debug_set_upload_cause(enum sec_debug_upload_cause_t type)
+{
+	per_cpu(sec_debug_upload_cause, smp_processor_id()) = type;
+
+	/* to check VDD_ALIVE / XnRESET issue */
+	__raw_writel(type, S5P_INFORM3);
+	__raw_writel(type, S5P_INFORM4);
+	__raw_writel(type, S5P_INFORM6);
+
+	pr_emerg("(%s) %x\n", __func__, type);
+}
+
+/*
+ * Called from dump_stack()
+ * This function call does not necessarily mean that a fatal error
+ * had occurred. It may be just a warning.
+ */
+static inline int sec_debug_dump_stack(void)
+{
+	if (!sec_debug_level.en.kernel_fault)
+		return -1;
+
+	sec_debug_save_context();
+
+	/* flush L1 from each core.
+	   L2 will be flushed later before reset. */
+	flush_cache_all();
+
+	return 0;
+}
+
+static inline void sec_debug_hw_reset(void)
+{
+	pr_emerg("(%s) %s\n", __func__, linux_banner);
+	pr_emerg("(%s) rebooting...\n", __func__);
+
+	flush_cache_all();
+
+	outer_flush_all();
+
+	arch_reset(0, 0);
+
+	while (1) ;
+}
+
+#ifdef CONFIG_SEC_WATCHDOG_RESET
+static inline void sec_debug_disable_watchdog(void)
+{
+	writel(0, S3C2410_WTCON);
+	pr_err("(%s) disable watchdog reset while printing log\n", __func__);
+}
+#endif
+
+static int sec_debug_panic_handler(struct notifier_block *nb,
+				   unsigned long l, void *buf)
+{
+	if (!sec_debug_level.en.kernel_fault)
+		return -1;
+
+	local_irq_disable();
+
+	sec_debug_set_upload_magic(0x66262564, buf);
+
+	if (!strcmp(buf, "User Fault"))
+		sec_debug_set_upload_cause(UPLOAD_CAUSE_USER_FAULT);
+	else if (!strcmp(buf, "Crash Key"))
+		sec_debug_set_upload_cause(UPLOAD_CAUSE_FORCED_UPLOAD);
+	else if (!strncmp(buf, "CP Crash", 8))
+		sec_debug_set_upload_cause(UPLOAD_CAUSE_CP_ERROR_FATAL);
+	else if (!strcmp(buf, "HSIC Disconnected"))
+		sec_debug_set_upload_cause(UPLOAD_CAUSE_HSIC_DISCONNECTED);
+	else
+		sec_debug_set_upload_cause(UPLOAD_CAUSE_KERNEL_PANIC);
+
+	pr_err("(%s) checksum_sched_log: %x\n", __func__, checksum_sched_log());
+
+#ifdef CONFIG_SEC_WATCHDOG_RESET
+	sec_debug_disable_watchdog();
+#endif
+	show_state();
+
+	sec_debug_dump_stack();
+	sec_debug_hw_reset();
+
+	return 0;
+}
+
+#ifdef CONFIG_SEC_DEBUG_FUPLOAD_DUMP_MORE
+static void dump_state_and_upload(void);
+#endif
+
+void sec_debug_check_crash_key(unsigned int code, int value)
+{
+	static bool volup_p;
+	static bool voldown_p;
+	static int loopcount;
+
+	if (!sec_debug_level.en.kernel_fault)
+		return;
+
+	/* Must be deleted later */
+#if defined(CONFIG_MACH_MIDAS) || defined(CONFIG_SLP)
+	pr_info("%s:key code(%d) value(%d)\n",
+		__func__, code, value);
+#endif
+
+	/* Enter Force Upload
+	 *  Hold volume down key first
+	 *  and then press power key twice
+	 *  and volume up key should not be pressed
+	 */
+	if (value) {
+		if (code == KEY_VOLUMEUP)
+			volup_p = true;
+		if (code == KEY_VOLUMEDOWN)
+			voldown_p = true;
+		if (!volup_p && voldown_p) {
+			if (code == KEY_POWER) {
+				pr_info
+				    ("%s: count for enter forced upload : %d\n",
+				     __func__, ++loopcount);
+				if (loopcount == 2) {
+#ifdef CONFIG_FB_S5P
+					read_lcd_register();
+#endif
+#ifdef CONFIG_SEC_DEBUG_FUPLOAD_DUMP_MORE
+					dump_state_and_upload();
+#else
+					panic("Crash Key");
+#endif
+				}
+			}
+		}
+	} else {
+		if (code == KEY_VOLUMEUP)
+			volup_p = false;
+		if (code == KEY_VOLUMEDOWN) {
+			loopcount = 0;
+			voldown_p = false;
+		}
+	}
+}
+
+static struct notifier_block nb_reboot_block = {
+	.notifier_call = sec_debug_normal_reboot_handler
+};
+
+static struct notifier_block nb_panic_block = {
+	.notifier_call = sec_debug_panic_handler,
+};
+
+static void sec_kmsg_dump(struct kmsg_dumper *dumper,
+			  enum kmsg_dump_reason reason, const char *s1,
+			  unsigned long l1, const char *s2, unsigned long l2)
+{
+	char *ptr = (char *)SEC_DEBUG_MAGIC_VA + SZ_1K;
+	int total_chars = SZ_4K - SZ_1K;
+	int total_lines = 50;
+	int last_chars; /* no of chars which fits in total_chars *and* in total_lines */
+
+	for (last_chars = 0;
+	     l2 && l2 > last_chars && total_lines > 0
+	     && total_chars > 0; ++last_chars, --total_chars) {
+		if (s2[l2 - last_chars] == '\n')
+			--total_lines;
+	}
+	s2 += (l2 - last_chars);
+	l2 = last_chars;
+
+	for (last_chars = 0;
+	     l1 && l1 > last_chars && total_lines > 0
+	     && total_chars > 0; ++last_chars, --total_chars) {
+		if (s1[l1 - last_chars] == '\n')
+			--total_lines;
+	}
+	s1 += (l1 - last_chars);
+	l1 = last_chars;
+
+	while (l1-- > 0)
+		*ptr++ = *s1++;
+	while (l2-- > 0)
+		*ptr++ = *s2++;
+}
+
+static struct kmsg_dumper sec_dumper = {
+	.dump = sec_kmsg_dump,
+};
+
+__init int sec_debug_init(void)
+{
+	if (!sec_debug_level.en.kernel_fault)
+		return -1;
+
+	sec_debug_set_upload_magic(0x66262564, NULL);
+	sec_debug_set_upload_cause(UPLOAD_CAUSE_INIT);
+
+#ifdef CONFIG_SEC_DEBUG_SCHED_LOG_NONCACHED
+	map_noncached_sched_log_buf();
+#endif
+
+#ifdef CONFIG_SEC_DEBUG_AUXILIARY_LOG
+	map_noncached_aux_log_buf();
+#endif
+
+	kmsg_dump_register(&sec_dumper);
+
+	register_reboot_notifier(&nb_reboot_block);
+
+	atomic_notifier_chain_register(&panic_notifier_list, &nb_panic_block);
+
+	return 0;
+}
+
+int get_sec_debug_level(void)
+{
+	return sec_debug_level.uint_val;
+}
+
+/* klaatu - schedule log */
+#ifdef CONFIG_SEC_DEBUG_SCHED_LOG
+void __sec_debug_task_log(int cpu, struct task_struct *task)
+{
+	unsigned i;
+
+	i = atomic_inc_return(&task_log_idx[cpu]) & (SCHED_LOG_MAX - 1);
+	psec_debug_log->task[cpu][i].time = cpu_clock(cpu);
+	strcpy(psec_debug_log->task[cpu][i].comm, task->comm);
+	psec_debug_log->task[cpu][i].pid = task->pid;
+}
+
+void __sec_debug_irq_log(unsigned int irq, void *fn, int en)
+{
+	int cpu = raw_smp_processor_id();
+	unsigned i;
+
+	i = atomic_inc_return(&irq_log_idx[cpu]) & (SCHED_LOG_MAX - 1);
+	psec_debug_log->irq[cpu][i].time = cpu_clock(cpu);
+	psec_debug_log->irq[cpu][i].irq = irq;
+	psec_debug_log->irq[cpu][i].fn = (void *)fn;
+	psec_debug_log->irq[cpu][i].en = en;
+}
+
+void __sec_debug_work_log(struct worker *worker,
+			  struct work_struct *work, work_func_t f)
+{
+	int cpu = raw_smp_processor_id();
+	unsigned i;
+
+	i = atomic_inc_return(&work_log_idx[cpu]) & (SCHED_LOG_MAX - 1);
+	psec_debug_log->work[cpu][i].time = cpu_clock(cpu);
+	psec_debug_log->work[cpu][i].worker = worker;
+	psec_debug_log->work[cpu][i].work = work;
+	psec_debug_log->work[cpu][i].f = f;
+}
+
+#ifdef CONFIG_SEC_DEBUG_IRQ_EXIT_LOG
+void sec_debug_irq_last_exit_log(void)
+{
+	int cpu = raw_smp_processor_id();
+	gExcpIrqExitTime[cpu] = cpu_clock(cpu);
+}
+#endif
+#endif /* CONFIG_SEC_DEBUG_SCHED_LOG */
+
+#ifdef CONFIG_SEC_DEBUG_AUXILIARY_LOG
+void sec_debug_aux_log(int idx, char *fmt, ...)
+{
+	va_list args;
+	char buf[128];
+	unsigned i;
+	int cpu = raw_smp_processor_id();
+
+	if (!gExcpAuxLogPtr)
+		return;
+
+	va_start(args, fmt);
+	vsnprintf(buf, sizeof(buf), fmt, args);
+	va_end(args);
+
+	switch (idx) {
+	case SEC_DEBUG_AUXLOG_CPU_BUS_CLOCK_CHANGE:
+		i = atomic_inc_return(&gExcpAuxCpuClockLogIdx)
+			& (AUX_LOG_CPU_CLOCK_MAX - 1);
+		(*gExcpAuxLogPtr).CpuClockLog[i].time = cpu_clock(cpu);
+		(*gExcpAuxLogPtr).CpuClockLog[i].cpu = cpu;
+		strncpy((*gExcpAuxLogPtr).CpuClockLog[i].log,
+			buf, AUX_LOG_LENGTH);
+		break;
+	case SEC_DEBUG_AUXLOG_LOGBUF_LOCK_CHANGE:
+		i = atomic_inc_return(&gExcpAuxLogBufLockLogIdx)
+			& (AUX_LOG_LOGBUF_LOCK_MAX - 1);
+		(*gExcpAuxLogPtr).LogBufLockLog[i].time = cpu_clock(cpu);
+		(*gExcpAuxLogPtr).LogBufLockLog[i].cpu = cpu;
+		strncpy((*gExcpAuxLogPtr).LogBufLockLog[i].log,
+			buf, AUX_LOG_LENGTH);
+		break;
+	default:
+		break;
+	}
+}
+#endif
+
+/* klaatu - semaphore log */
+#ifdef CONFIG_SEC_DEBUG_SEMAPHORE_LOG
+void debug_semaphore_init(void)
+{
+	int i = 0;
+	struct sem_debug *sem_debug = NULL;
+
+	spin_lock_init(&sem_debug_lock);
+	sem_debug_free_head_cnt = 0;
+	sem_debug_done_head_cnt = 0;
+
+	/* initialize list head of sem_debug */
+	INIT_LIST_HEAD(&sem_debug_free_head.list);
+	INIT_LIST_HEAD(&sem_debug_done_head.list);
+
+	for (i = 0; i < SEMAPHORE_LOG_MAX; i++) {
+		/* malloc semaphore */
+		sem_debug = kmalloc(sizeof(struct sem_debug), GFP_KERNEL);
+		/* add list */
+		list_add(&sem_debug->list, &sem_debug_free_head.list);
+		sem_debug_free_head_cnt++;
+	}
+
+	sem_debug_init = 1;
+}
+
+void debug_semaphore_down_log(struct semaphore *sem)
+{
+	struct list_head *tmp;
+	struct sem_debug *sem_dbg;
+	unsigned long flags;
+
+	if (!sem_debug_init)
+		return;
+
+	spin_lock_irqsave(&sem_debug_lock, flags);
+	list_for_each(tmp, &sem_debug_free_head.list) {
+		sem_dbg = list_entry(tmp, struct sem_debug, list);
+		sem_dbg->task = current;
+		sem_dbg->sem = sem;
+		/* strcpy(sem_dbg->comm,current->group_leader->comm); */
+		sem_dbg->pid = current->pid;
+		sem_dbg->cpu = smp_processor_id();
+		list_del(&sem_dbg->list);
+		list_add(&sem_dbg->list, &sem_debug_done_head.list);
+		sem_debug_free_head_cnt--;
+		sem_debug_done_head_cnt++;
+		break;
+	}
+	spin_unlock_irqrestore(&sem_debug_lock, flags);
+}
+
+void debug_semaphore_up_log(struct semaphore *sem)
+{
+	struct list_head *tmp;
+	struct sem_debug *sem_dbg;
+	unsigned long flags;
+
+	if (!sem_debug_init)
+		return;
+
+	spin_lock_irqsave(&sem_debug_lock, flags);
+	list_for_each(tmp, &sem_debug_done_head.list) {
+		sem_dbg = list_entry(tmp, struct sem_debug, list);
+		if (sem_dbg->sem == sem && sem_dbg->pid == current->pid) {
+			list_del(&sem_dbg->list);
+			list_add(&sem_dbg->list, &sem_debug_free_head.list);
+			sem_debug_free_head_cnt++;
+			sem_debug_done_head_cnt--;
+			break;
+		}
+	}
+	spin_unlock_irqrestore(&sem_debug_lock, flags);
+}
+
+/* rwsemaphore logging */
+void debug_rwsemaphore_init(void)
+{
+	int i = 0;
+	struct rwsem_debug *rwsem_debug = NULL;
+
+	spin_lock_init(&rwsem_debug_lock);
+	rwsem_debug_free_head_cnt = 0;
+	rwsem_debug_done_head_cnt = 0;
+
+	/* initialize list head of sem_debug */
+	INIT_LIST_HEAD(&rwsem_debug_free_head.list);
+	INIT_LIST_HEAD(&rwsem_debug_done_head.list);
+
+	for (i = 0; i < RWSEMAPHORE_LOG_MAX; i++) {
+		/* malloc semaphore */
+		rwsem_debug = kmalloc(sizeof(struct rwsem_debug), GFP_KERNEL);
+		/* add list */
+		list_add(&rwsem_debug->list, &rwsem_debug_free_head.list);
+		rwsem_debug_free_head_cnt++;
+	}
+
+	rwsem_debug_init = 1;
+}
+
+void debug_rwsemaphore_down_log(struct rw_semaphore *sem, int dir)
+{
+	struct list_head *tmp;
+	struct rwsem_debug *sem_dbg;
+	unsigned long flags;
+
+	if (!rwsem_debug_init)
+		return;
+
+	spin_lock_irqsave(&rwsem_debug_lock, flags);
+	list_for_each(tmp, &rwsem_debug_free_head.list) {
+		sem_dbg = list_entry(tmp, struct rwsem_debug, list);
+		sem_dbg->task = current;
+		sem_dbg->sem = sem;
+		/* strcpy(sem_dbg->comm,current->group_leader->comm); */
+		sem_dbg->pid = current->pid;
+		sem_dbg->cpu = smp_processor_id();
+		sem_dbg->direction = dir;
+		list_del(&sem_dbg->list);
+		list_add(&sem_dbg->list, &rwsem_debug_done_head.list);
+		rwsem_debug_free_head_cnt--;
+		rwsem_debug_done_head_cnt++;
+		break;
+	}
+	spin_unlock_irqrestore(&rwsem_debug_lock, flags);
+}
+
+void debug_rwsemaphore_up_log(struct rw_semaphore *sem)
+{
+	struct list_head *tmp;
+	struct rwsem_debug *sem_dbg;
+	unsigned long flags;
+
+	if (!rwsem_debug_init)
+		return;
+
+	spin_lock_irqsave(&rwsem_debug_lock, flags);
+	list_for_each(tmp, &rwsem_debug_done_head.list) {
+		sem_dbg = list_entry(tmp, struct rwsem_debug, list);
+		if (sem_dbg->sem == sem && sem_dbg->pid == current->pid) {
+			list_del(&sem_dbg->list);
+			list_add(&sem_dbg->list, &rwsem_debug_free_head.list);
+			rwsem_debug_free_head_cnt++;
+			rwsem_debug_done_head_cnt--;
+			break;
+		}
+	}
+	spin_unlock_irqrestore(&rwsem_debug_lock, flags);
+}
+#endif /* CONFIG_SEC_DEBUG_SEMAPHORE_LOG */
+
+#ifdef CONFIG_SEC_DEBUG_USER
+void sec_user_fault_dump(void)
+{
+	if (sec_debug_level.en.kernel_fault == 1
+	    && sec_debug_level.en.user_fault == 1)
+		panic("User Fault");
+}
+
+static int sec_user_fault_write(struct file *file, const char __user * buffer,
+				size_t count, loff_t * offs)
+{
+	char buf[100];
+
+	if (count > sizeof(buf) - 1)
+		return -EINVAL;
+	if (copy_from_user(buf, buffer, count))
+		return -EFAULT;
+	buf[count] = '\0';
+
+	if (strncmp(buf, "dump_user_fault", 15) == 0)
+		sec_user_fault_dump();
+
+	return count;
+}
+
+static const struct file_operations sec_user_fault_proc_fops = {
+	.write = sec_user_fault_write,
+};
+
+static int __init sec_debug_user_fault_init(void)
+{
+	struct proc_dir_entry *entry;
+
+	entry = proc_create("user_fault", S_IWUGO, NULL,
+			    &sec_user_fault_proc_fops);
+	if (!entry)
+		return -ENOMEM;
+	return 0;
+}
+
+device_initcall(sec_debug_user_fault_init);
+#endif
+
+int sec_debug_magic_init(void)
+{
+	if (reserve_bootmem(SEC_DEBUG_MAGIC_PA, SZ_4K, BOOTMEM_EXCLUSIVE)) {
+		pr_err("%s: failed reserving magic code area\n", __func__);
+		return -ENOMEM;
+	}
+
+	pr_info("%s: success reserving magic code area\n", __func__);
+	return 0;
+}
+
+#ifdef CONFIG_SEC_DEBUG_FUPLOAD_DUMP_MORE
+static void dump_one_task_info(struct task_struct *tsk, bool is_main)
+{
+	char state_array[] = {'R', 'S', 'D', 'T', 't', 'Z', 'X', 'x', 'K', 'W'};
+	unsigned char idx = 0;
+	unsigned int state = (tsk->state & TASK_REPORT) | tsk->exit_state;
+	unsigned long wchan;
+	unsigned long pc = 0;
+	char symname[KSYM_NAME_LEN];
+	int permitted;
+	struct mm_struct *mm;
+
+	permitted = ptrace_may_access(tsk, PTRACE_MODE_READ);
+	mm = get_task_mm(tsk);
+	if (mm) {
+		if (permitted)
+			pc = KSTK_EIP(tsk);
+	}
+
+	wchan = get_wchan(tsk);
+	if (lookup_symbol_name(wchan, symname) < 0) {
+		if (!ptrace_may_access(tsk, PTRACE_MODE_READ))
+			sprintf(symname, "_____");
+		else
+			sprintf(symname, "%lu", wchan);
+	}
+
+	while (state) {
+		idx++;
+		state >>= 1;
+	}
+
+	pr_info("%8d %8d %8d %16lld %c(%d) %3d  %08x %08x  %08x %c %16s [%s]\n",
+			tsk->pid, (int)(tsk->utime), (int)(tsk->stime),
+			tsk->se.exec_start, state_array[idx], (int)(tsk->state),
+			task_cpu(tsk), (int)wchan, (int)pc, (int)tsk,
+			is_main ? '*' : ' ', tsk->comm, symname);
+
+	if (tsk->state == TASK_RUNNING
+			|| tsk->state == TASK_UNINTERRUPTIBLE
+			|| tsk->mm == NULL) {
+		show_stack(tsk, NULL);
+		pr_info("\n");
+	}
+}
+
+static inline struct task_struct *get_next_thread(struct task_struct *tsk)
+{
+	return container_of(tsk->thread_group.next,
+				struct task_struct,
+				thread_group);
+}
+
+static void dump_all_task_info(void)
+{
+	struct task_struct *frst_tsk;
+	struct task_struct *curr_tsk;
+	struct task_struct *frst_thr;
+	struct task_struct *curr_thr;
+
+	pr_info("\n");
+	pr_info(" current proc : %d %s\n", current->pid, current->comm);
+	pr_info(" -------------------------------------------------------------------------------------------------------------\n");
+	pr_info("     pid      uTime    sTime      exec(ns)  stat  cpu   wchan   user_pc  task_struct          comm   sym_wchan\n");
+	pr_info(" -------------------------------------------------------------------------------------------------------------\n");
+
+	/* processes */
+	frst_tsk = &init_task;
+	curr_tsk = frst_tsk;
+	while (curr_tsk != NULL) {
+		dump_one_task_info(curr_tsk,  true);
+		/* threads */
+		if (curr_tsk->thread_group.next != NULL) {
+			frst_thr = get_next_thread(curr_tsk);
+			curr_thr = frst_thr;
+			if (frst_thr != curr_tsk) {
+				while (curr_thr != NULL) {
+					dump_one_task_info(curr_thr, false);
+					curr_thr = get_next_thread(curr_thr);
+					if (curr_thr == curr_tsk)
+						break;
+				}
+			}
+		}
+		curr_tsk = container_of(curr_tsk->tasks.next,
+					struct task_struct, tasks);
+		if (curr_tsk == frst_tsk)
+			break;
+	}
+	pr_info(" -----------------------------------------------------------------------------------\n");
+}
+
+#ifndef arch_irq_stat_cpu
+#define arch_irq_stat_cpu(cpu) 0
+#endif
+#ifndef arch_irq_stat
+#define arch_irq_stat() 0
+#endif
+#ifndef arch_idle_time
+#define arch_idle_time(cpu) 0
+#endif
+
+static void dump_cpu_stat(void)
+{
+	int i, j;
+	unsigned long jif;
+	cputime64_t user, nice, system, idle, iowait, irq, softirq, steal;
+	cputime64_t guest, guest_nice;
+	u64 sum = 0;
+	u64 sum_softirq = 0;
+	unsigned int per_softirq_sums[NR_SOFTIRQS] = {0};
+	struct timespec boottime;
+	unsigned int per_irq_sum;
+
+	char *softirq_to_name[NR_SOFTIRQS] = {
+	     "HI", "TIMER", "NET_TX", "NET_RX", "BLOCK", "BLOCK_IOPOLL",
+	     "TASKLET", "SCHED", "HRTIMER",  "RCU"
+	};
+
+	user = nice = system = idle = iowait = cputime64_zero;
+	irq = softirq = steal = cputime64_zero;
+	guest = guest_nice = cputime64_zero;
+
+	getboottime(&boottime);
+	jif = boottime.tv_sec;
+	for_each_possible_cpu(i) {
+		user = cputime64_add(user, kstat_cpu(i).cpustat.user);
+		nice = cputime64_add(nice, kstat_cpu(i).cpustat.nice);
+		system = cputime64_add(system, kstat_cpu(i).cpustat.system);
+		idle = cputime64_add(idle, kstat_cpu(i).cpustat.idle);
+		idle = cputime64_add(idle, arch_idle_time(i));
+		iowait = cputime64_add(iowait, kstat_cpu(i).cpustat.iowait);
+		irq = cputime64_add(irq, kstat_cpu(i).cpustat.irq);
+		softirq = cputime64_add(softirq, kstat_cpu(i).cpustat.softirq);
+
+		for_each_irq_nr(j) {
+			sum += kstat_irqs_cpu(j, i);
+		}
+		sum += arch_irq_stat_cpu(i);
+		for (j = 0; j < NR_SOFTIRQS; j++) {
+			unsigned int softirq_stat = kstat_softirqs_cpu(j, i);
+			per_softirq_sums[j] += softirq_stat;
+			sum_softirq += softirq_stat;
+		}
+	}
+	sum += arch_irq_stat();
+	pr_info("\n");
+	pr_info(" cpu     user:%llu  nice:%llu  system:%llu  idle:%llu  "
+		"iowait:%llu  irq:%llu  softirq:%llu %llu %llu " "%llu\n",
+			(unsigned long long)cputime64_to_clock_t(user),
+			(unsigned long long)cputime64_to_clock_t(nice),
+			(unsigned long long)cputime64_to_clock_t(system),
+			(unsigned long long)cputime64_to_clock_t(idle),
+			(unsigned long long)cputime64_to_clock_t(iowait),
+			(unsigned long long)cputime64_to_clock_t(irq),
+			(unsigned long long)cputime64_to_clock_t(softirq),
+			(unsigned long long)0,	/* steal */
+			(unsigned long long)0,	/* guest */
+			(unsigned long long)0);	/* guest_nice */
+	pr_info(" -----------------------------------------------------------------------------------\n");
+	for_each_online_cpu(i) {
+		/* Copy values here to work around gcc-2.95.3, gcc-2.96 */
+		user = kstat_cpu(i).cpustat.user;
+		nice = kstat_cpu(i).cpustat.nice;
+		system = kstat_cpu(i).cpustat.system;
+		idle = kstat_cpu(i).cpustat.idle;
+		idle = cputime64_add(idle, arch_idle_time(i));
+		iowait = kstat_cpu(i).cpustat.iowait;
+		irq = kstat_cpu(i).cpustat.irq;
+		softirq = kstat_cpu(i).cpustat.softirq;
+		/* steal = kstat_cpu(i).cpustat.steal; */
+		/* guest = kstat_cpu(i).cpustat.guest; */
+		/* guest_nice = kstat_cpu(i).cpustat.guest_nice; */
+		pr_info(" cpu %d   user:%llu  nice:%llu  system:%llu  "
+			"idle:%llu  iowait:%llu  irq:%llu  softirq:%llu "
+			"%llu %llu " "%llu\n",
+			i,
+			(unsigned long long)cputime64_to_clock_t(user),
+			(unsigned long long)cputime64_to_clock_t(nice),
+			(unsigned long long)cputime64_to_clock_t(system),
+			(unsigned long long)cputime64_to_clock_t(idle),
+			(unsigned long long)cputime64_to_clock_t(iowait),
+			(unsigned long long)cputime64_to_clock_t(irq),
+			(unsigned long long)cputime64_to_clock_t(softirq),
+			(unsigned long long)0,	/* steal */
+			(unsigned long long)0,	/* guest */
+			(unsigned long long)0);	/* guest_nice */
+	}
+	pr_info(" -----------------------------------------------------------------------------------\n");
+	pr_info("\n");
+	pr_info(" irq : %llu", (unsigned long long)sum);
+	pr_info(" -----------------------------------------------------------------------------------\n");
+	/* sum again ? it could be updated? */
+	for_each_irq_nr(j) {
+		per_irq_sum = 0;
+		for_each_possible_cpu(i)
+			per_irq_sum += kstat_irqs_cpu(j, i);
+		if (per_irq_sum) {
+			pr_info(" irq-%4d : %8u %s\n",
+				j, per_irq_sum, irq_to_desc(j)->action ?
+				irq_to_desc(j)->action->name ?: "???" : "???");
+		}
+	}
+	pr_info(" -----------------------------------------------------------------------------------\n");
+	pr_info("\n");
+	pr_info(" softirq : %llu", (unsigned long long)sum_softirq);
+	pr_info(" -----------------------------------------------------------------------------------\n");
+	for (i = 0; i < NR_SOFTIRQS; i++)
+		if (per_softirq_sums[i])
+			pr_info(" softirq-%d : %8u %s\n",
+				i, per_softirq_sums[i], softirq_to_name[i]);
+	pr_info(" -----------------------------------------------------------------------------------\n");
+}
+
+static void dump_state_and_upload(void)
+{
+	if (!sec_debug_level.en.kernel_fault)
+		return;
+
+	sec_debug_set_upload_magic(0x66262564, NULL);
+
+	sec_debug_set_upload_cause(UPLOAD_CAUSE_FORCED_UPLOAD);
+
+	pr_err("(%s) checksum_sched_log: %x\n", __func__, checksum_sched_log());
+
+#ifdef CONFIG_SEC_WATCHDOG_RESET
+	sec_debug_disable_watchdog();
+#endif
+	dump_all_task_info();
+	dump_cpu_stat();
+
+	show_state_filter(TASK_STATE_MAX);	/* no backtrace */
+
+	sec_debug_dump_stack();
+	sec_debug_hw_reset();
+}
+#endif /* CONFIG_SEC_DEBUG_FUPLOAD_DUMP_MORE */
diff --git a/arch/arm/mach-exynos/sec_gaf.c b/arch/arm/mach-exynos/sec_gaf.c
new file mode 100644
index 0000000..a8aa7f0
--- /dev/null
+++ b/arch/arm/mach-exynos/sec_gaf.c
@@ -0,0 +1,224 @@
+/*
+ *  sec_gaf.c
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/sched.h>
+#include <linux/fs.h>
+#include <linux/mount.h>
+#include <asm/pgtable.h>
+
+static struct GAForensicINFO {
+	unsigned short ver;
+	unsigned int size;
+	unsigned short task_struct_struct_state;
+	unsigned short task_struct_struct_comm;
+	unsigned short task_struct_struct_tasks;
+	unsigned short task_struct_struct_pid;
+	unsigned short task_struct_struct_stack;
+	unsigned short task_struct_struct_mm;
+	unsigned short mm_struct_struct_start_data;
+	unsigned short mm_struct_struct_end_data;
+	unsigned short mm_struct_struct_start_brk;
+	unsigned short mm_struct_struct_brk;
+	unsigned short mm_struct_struct_start_stack;
+	unsigned short mm_struct_struct_arg_start;
+	unsigned short mm_struct_struct_arg_end;
+	unsigned short mm_struct_struct_pgd;
+	unsigned short mm_struct_struct_mmap;
+	unsigned short vm_area_struct_struct_vm_start;
+	unsigned short vm_area_struct_struct_vm_end;
+	unsigned short vm_area_struct_struct_vm_next;
+	unsigned short vm_area_struct_struct_vm_file;
+	unsigned short thread_info_struct_cpu_context;
+	unsigned short cpu_context_save_struct_sp;
+	unsigned short file_struct_f_path;
+	unsigned short path_struct_mnt;
+	unsigned short path_struct_dentry;
+	unsigned short dentry_struct_d_parent;
+	unsigned short dentry_struct_d_name;
+	unsigned short qstr_struct_name;
+	unsigned short vfsmount_struct_mnt_mountpoint;
+	unsigned short vfsmount_struct_mnt_root;
+	unsigned short vfsmount_struct_mnt_parent;
+	unsigned int pgdir_shift;
+	unsigned int ptrs_per_pte;
+	unsigned int phys_offset;
+	unsigned int page_offset;
+	unsigned int page_shift;
+	unsigned int page_size;
+	unsigned short task_struct_struct_thread_group;
+	unsigned short task_struct_struct_utime;
+	unsigned short task_struct_struct_stime;
+	unsigned short list_head_struct_next;
+	unsigned short list_head_struct_prev;
+	unsigned short rq_struct_curr;
+
+	unsigned short thread_info_struct_cpu;
+
+	unsigned short task_struct_struct_prio;
+	unsigned short task_struct_struct_static_prio;
+	unsigned short task_struct_struct_normal_prio;
+	unsigned short task_struct_struct_rt_priority;
+
+	unsigned short task_struct_struct_se;
+
+	unsigned short sched_entity_struct_exec_start;
+	unsigned short sched_entity_struct_sum_exec_runtime;
+	unsigned short sched_entity_struct_prev_sum_exec_runtime;
+
+	unsigned short task_struct_struct_sched_info;
+
+	unsigned short sched_info_struct_pcount;
+	unsigned short sched_info_struct_run_delay;
+	unsigned short sched_info_struct_last_arrival;
+	unsigned short sched_info_struct_last_queued;
+
+	unsigned short task_struct_struct_blocked_on;
+
+	unsigned short mutex_waiter_struct_list;
+	unsigned short mutex_waiter_struct_task;
+
+	unsigned short sched_entity_struct_cfs_rq_struct;
+	unsigned short cfs_rq_struct_rq_struct;
+	unsigned short gaf_fp;
+	unsigned short  GAFINFOCheckSum;
+} GAFINFO = {
+	.ver = 0x0300, /* by dh3s.choi 2010 12 14 */
+	.size = sizeof(GAFINFO),
+	.task_struct_struct_state = offsetof(struct task_struct, state),
+	.task_struct_struct_comm = offsetof(struct task_struct, comm),
+	.task_struct_struct_tasks = offsetof(struct task_struct, tasks),
+	.task_struct_struct_pid = offsetof(struct task_struct, pid),
+	.task_struct_struct_stack = offsetof(struct task_struct, stack),
+	.task_struct_struct_mm = offsetof(struct task_struct, mm),
+	.mm_struct_struct_start_data = offsetof(struct mm_struct, start_data),
+	.mm_struct_struct_end_data = offsetof(struct mm_struct, end_data),
+	.mm_struct_struct_start_brk = offsetof(struct mm_struct, start_brk),
+	.mm_struct_struct_brk = offsetof(struct mm_struct, brk),
+	.mm_struct_struct_start_stack = offsetof(struct mm_struct, start_stack),
+	.mm_struct_struct_arg_start = offsetof(struct mm_struct, arg_start),
+	.mm_struct_struct_arg_end = offsetof(struct mm_struct, arg_end),
+	.mm_struct_struct_pgd = offsetof(struct mm_struct, pgd),
+	.mm_struct_struct_mmap = offsetof(struct mm_struct, mmap),
+	.vm_area_struct_struct_vm_start = offsetof(struct vm_area_struct, vm_start),
+	.vm_area_struct_struct_vm_end = offsetof(struct vm_area_struct, vm_end),
+	.vm_area_struct_struct_vm_next = offsetof(struct vm_area_struct, vm_next),
+	.vm_area_struct_struct_vm_file = offsetof(struct vm_area_struct, vm_file),
+	.thread_info_struct_cpu_context = offsetof(struct thread_info, cpu_context),
+	.cpu_context_save_struct_sp = offsetof(struct cpu_context_save, sp),
+	.file_struct_f_path = offsetof(struct file, f_path),
+	.path_struct_mnt = offsetof(struct path, mnt),
+	.path_struct_dentry = offsetof(struct path, dentry),
+	.dentry_struct_d_parent = offsetof(struct dentry, d_parent),
+	.dentry_struct_d_name = offsetof(struct dentry, d_name),
+	.qstr_struct_name = offsetof(struct qstr, name),
+	.vfsmount_struct_mnt_mountpoint = offsetof(struct vfsmount, mnt_mountpoint),
+	.vfsmount_struct_mnt_root = offsetof(struct vfsmount, mnt_root),
+	.vfsmount_struct_mnt_parent = offsetof(struct vfsmount, mnt_parent),
+	.pgdir_shift = PGDIR_SHIFT,
+	.ptrs_per_pte = PTRS_PER_PTE,
+	/* .phys_offset = PHYS_OFFSET, */
+	.page_offset = PAGE_OFFSET,
+	.page_shift = PAGE_SHIFT,
+	.page_size = PAGE_SIZE,
+	.task_struct_struct_thread_group  = offsetof(struct task_struct, thread_group),
+	.task_struct_struct_utime =  offsetof(struct task_struct, utime),
+	.task_struct_struct_stime =  offsetof(struct task_struct, stime),
+	.list_head_struct_next = offsetof(struct list_head, next),
+	.list_head_struct_prev = offsetof(struct list_head, prev),
+
+	.rq_struct_curr = 0,
+
+	.thread_info_struct_cpu = offsetof(struct thread_info, cpu),
+
+	.task_struct_struct_prio = offsetof(struct task_struct, prio),
+	.task_struct_struct_static_prio = offsetof(struct task_struct, static_prio),
+	.task_struct_struct_normal_prio = offsetof(struct task_struct, normal_prio),
+	.task_struct_struct_rt_priority = offsetof(struct task_struct, rt_priority),
+
+	.task_struct_struct_se = offsetof(struct task_struct, se),
+
+	.sched_entity_struct_exec_start = offsetof(struct sched_entity, exec_start),
+	.sched_entity_struct_sum_exec_runtime = offsetof(struct sched_entity, sum_exec_runtime),
+	.sched_entity_struct_prev_sum_exec_runtime = offsetof(struct sched_entity, prev_sum_exec_runtime),
+
+#if defined(CONFIG_SCHEDSTATS) || defined(CONFIG_TASK_DELAY_ACCT)
+	.task_struct_struct_sched_info = offsetof(struct task_struct, sched_info),
+	.sched_info_struct_pcount = offsetof(struct sched_info, pcount),
+	.sched_info_struct_run_delay = offsetof(struct sched_info, run_delay),
+	.sched_info_struct_last_arrival = offsetof(struct sched_info, last_arrival),
+	.sched_info_struct_last_queued = offsetof(struct sched_info, last_queued),
+#else
+	.task_struct_struct_sched_info = 0x1223,
+	.sched_info_struct_pcount = 0x1224,
+	.sched_info_struct_run_delay = 0x1225,
+	.sched_info_struct_last_arrival = 0x1226,
+	.sched_info_struct_last_queued = 0x1227,
+#endif
+
+#ifdef CONFIG_DEBUG_MUTEXES
+	.task_struct_struct_blocked_on = offsetof(struct task_struct, blocked_on),
+	.mutex_waiter_struct_list = offsetof(struct mutex_waiter, list),
+	.mutex_waiter_struct_task = offsetof(struct mutex_waiter, task),
+#else
+	.task_struct_struct_blocked_on = 0x1228,
+	.mutex_waiter_struct_list = 0x1229,
+	.mutex_waiter_struct_task = 0x122a,
+#endif
+
+#ifdef CONFIG_FAIR_GROUP_SCHED
+	.sched_entity_struct_cfs_rq_struct = offsetof(struct sched_entity, cfs_rq),
+#else
+	.sched_entity_struct_cfs_rq_struct = 0x1223,
+#endif
+
+	.cfs_rq_struct_rq_struct = 0,
+
+#ifdef CONFIG_FRAME_POINTER
+	.gaf_fp = 1,
+#else
+	.gaf_fp = 0,
+#endif
+
+	.GAFINFOCheckSum = 0
+};
+
+void sec_gaf_supply_rqinfo(unsigned short curr_offset, unsigned short rq_offset)
+{
+	unsigned short *checksum = &(GAFINFO.GAFINFOCheckSum);
+	unsigned char *memory = (unsigned char *)&GAFINFO;
+	unsigned char address;
+	/*
+	 *  Add GAForensic init for preventing symbol removal for optimization.
+	 */
+	GAFINFO.phys_offset = PHYS_OFFSET;
+	GAFINFO.rq_struct_curr = curr_offset;
+
+#ifdef CONFIG_FAIR_GROUP_SCHED
+	GAFINFO.cfs_rq_struct_rq_struct = rq_offset;
+#else
+	GAFINFO.cfs_rq_struct_rq_struct = 0x1224;
+#endif
+
+	for (*checksum = 0, address = 0;
+	     address < (sizeof(GAFINFO) - sizeof(GAFINFO.GAFINFOCheckSum));
+	     address++) {
+		if ((*checksum) & 0x8000)
+			(*checksum) =
+			    (((*checksum) << 1) | 1) ^ memory[address];
+		else
+			(*checksum) = ((*checksum) << 1) ^ memory[address];
+	}
+}
+EXPORT_SYMBOL(sec_gaf_supply_rqinfo);
+
+static int __init sec_gaf_init(void)
+{
+	GAFINFO.phys_offset = PHYS_OFFSET;
+	return 0;
+}
+
+core_initcall(sec_gaf_init);
diff --git a/arch/arm/mach-exynos/sec_getlog.c b/arch/arm/mach-exynos/sec_getlog.c
new file mode 100644
index 0000000..06a0be6
--- /dev/null
+++ b/arch/arm/mach-exynos/sec_getlog.c
@@ -0,0 +1,126 @@
+/*
+ *  sec_getlog.c
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/errno.h>
+#include <asm/setup.h>
+
+static struct {
+	u32 special_mark_1;
+	u32 special_mark_2;
+	u32 special_mark_3;
+	u32 special_mark_4;
+	void *p_fb;		/* it must be physical address */
+	u32 xres;
+	u32 yres;
+	u32 bpp;		/* color depth : 16 or 24 */
+	u32 frames;		/* frame buffer count : 2 */
+} frame_buf_mark = {
+	.special_mark_1 = (('*' << 24) | ('^' << 16) | ('^' << 8) | ('*' << 0)),
+	.special_mark_2 = (('I' << 24) | ('n' << 16) | ('f' << 8) | ('o' << 0)),
+	.special_mark_3 = (('H' << 24) | ('e' << 16) | ('r' << 8) | ('e' << 0)),
+	.special_mark_4 = (('f' << 24) | ('b' << 16) | ('u' << 8) | ('f' << 0)),
+};
+
+void sec_getlog_supply_fbinfo(void *p_fb, u32 xres, u32 yres, u32 bpp,
+			      u32 frames)
+{
+	if (p_fb) {
+		pr_info("%s: 0x%p %d %d %d %d\n", __func__, p_fb, xres, yres,
+			bpp, frames);
+		frame_buf_mark.p_fb = p_fb;
+		frame_buf_mark.xres = xres;
+		frame_buf_mark.yres = yres;
+		frame_buf_mark.bpp = bpp;
+		frame_buf_mark.frames = frames;
+	}
+}
+EXPORT_SYMBOL(sec_getlog_supply_fbinfo);
+
+static struct {
+	u32 special_mark_1;
+	u32 special_mark_2;
+	u32 special_mark_3;
+	u32 special_mark_4;
+	u32 log_mark_version;
+	u32 framebuffer_mark_version;
+	void *this;		/* this is used for addressing
+				   log buffer in 2 dump files */
+	struct {
+		u32 size;	/* memory block's size */
+		u32 addr;	/* memory block'sPhysical address */
+	} mem[2];
+} marks_ver_mark = {
+	.special_mark_1 = (('*' << 24) | ('^' << 16) | ('^' << 8) | ('*' << 0)),
+	.special_mark_2 = (('I' << 24) | ('n' << 16) | ('f' << 8) | ('o' << 0)),
+	.special_mark_3 = (('H' << 24) | ('e' << 16) | ('r' << 8) | ('e' << 0)),
+	.special_mark_4 = (('v' << 24) | ('e' << 16) | ('r' << 8) | ('s' << 0)),
+	.log_mark_version = 1,
+	.framebuffer_mark_version = 1,
+	.this = &marks_ver_mark,
+};
+
+/* mark for GetLog extraction */
+static struct {
+	u32 special_mark_1;
+	u32 special_mark_2;
+	u32 special_mark_3;
+	u32 special_mark_4;
+	void *p_main;
+	void *p_radio;
+	void *p_events;
+	void *p_system;
+} plat_log_mark = {
+	.special_mark_1 = (('*' << 24) | ('^' << 16) | ('^' << 8) | ('*' << 0)),
+	.special_mark_2 = (('I' << 24) | ('n' << 16) | ('f' << 8) | ('o' << 0)),
+	.special_mark_3 = (('H' << 24) | ('e' << 16) | ('r' << 8) | ('e' << 0)),
+	.special_mark_4 = (('p' << 24) | ('l' << 16) | ('o' << 8) | ('g' << 0)),
+};
+
+void sec_getlog_supply_loggerinfo(void *p_main,
+				  void *p_radio, void *p_events, void *p_system)
+{
+	pr_info("%s: 0x%p 0x%p 0x%p 0x%p\n", __func__, p_main, p_radio,
+		p_events, p_system);
+	plat_log_mark.p_main = p_main;
+	plat_log_mark.p_radio = p_radio;
+	plat_log_mark.p_events = p_events;
+	plat_log_mark.p_system = p_system;
+}
+EXPORT_SYMBOL(sec_getlog_supply_loggerinfo);
+
+static struct {
+	u32 special_mark_1;
+	u32 special_mark_2;
+	u32 special_mark_3;
+	u32 special_mark_4;
+	void *klog_buf;
+} kernel_log_mark = {
+	.special_mark_1 = (('*' << 24) | ('^' << 16) | ('^' << 8) | ('*' << 0)),
+	.special_mark_2 = (('I' << 24) | ('n' << 16) | ('f' << 8) | ('o' << 0)),
+	.special_mark_3 = (('H' << 24) | ('e' << 16) | ('r' << 8) | ('e' << 0)),
+	.special_mark_4 = (('k' << 24) | ('l' << 16) | ('o' << 8) | ('g' << 0)),
+};
+
+void sec_getlog_supply_kloginfo(void *klog_buf)
+{
+	pr_info("%s: 0x%p\n", __func__, klog_buf);
+	kernel_log_mark.klog_buf = klog_buf;
+}
+EXPORT_SYMBOL(sec_getlog_supply_kloginfo);
+
+static int __init sec_getlog_init(void)
+{
+	marks_ver_mark.mem[0].size =
+		meminfo.bank[0].size + meminfo.bank[1].size;
+	marks_ver_mark.mem[0].addr = meminfo.bank[0].start;
+	marks_ver_mark.mem[1].size =
+		meminfo.bank[2].size + meminfo.bank[3].size;
+	marks_ver_mark.mem[1].addr = meminfo.bank[2].start;
+
+	return 0;
+}
+
+core_initcall(sec_getlog_init);
diff --git a/arch/arm/mach-exynos/sec_log.c b/arch/arm/mach-exynos/sec_log.c
new file mode 100644
index 0000000..b55e7da
--- /dev/null
+++ b/arch/arm/mach-exynos/sec_log.c
@@ -0,0 +1,171 @@
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/bootmem.h>
+#include <linux/slab.h>
+#include <linux/stat.h>
+#include <linux/uaccess.h>
+#include <linux/proc_fs.h>
+
+#include <mach/sec_debug.h>
+#include <plat/map-base.h>
+#include <plat/map-s5p.h>
+#include <asm/mach/map.h>
+
+/*
+ * Example usage: sec_log=256K@0x45000000
+ * In above case, log_buf size is 256KB and its base address is
+ * 0x45000000 physically. Actually, *(int *)(base - 8) is log_magic and
+ * *(int *)(base - 4) is log_ptr. So we reserve (size + 8) bytes from
+ * (base - 8).
+ */
+#define LOG_MAGIC 0x4d474f4c	/* "LOGM" */
+
+/* These variables are also protected by logbuf_lock */
+static unsigned *sec_log_ptr;
+static char *sec_log_buf;
+static unsigned sec_log_size;
+
+#ifdef CONFIG_SEC_LOG_LAST_KMSG
+static char *last_kmsg_buffer;
+static unsigned last_kmsg_size;
+static void __init sec_log_save_old(void);
+#else
+static inline void sec_log_save_old(void)
+{
+}
+#endif
+
+extern void register_log_char_hook(void (*f) (char c));
+
+#ifdef CONFIG_SEC_LOG_NONCACHED
+static struct map_desc log_buf_iodesc[] __initdata = {
+	{
+		.virtual = (unsigned long)S3C_VA_KLOG_BUF,
+		.type = MT_DEVICE
+	}
+};
+#endif
+
+static inline void emit_sec_log_char(char c)
+{
+	if (sec_log_buf && sec_log_ptr) {
+		sec_log_buf[*sec_log_ptr & (sec_log_size - 1)] = c;
+		(*sec_log_ptr)++;
+	}
+}
+
+static int __init sec_log_setup(char *str)
+{
+	unsigned size = memparse(str, &str);
+	unsigned long base = 0;
+	unsigned *sec_log_mag;
+
+	/* If we encounter any problem parsing str ... */
+	if (!size || size != roundup_pow_of_two(size) || *str != '@'
+	    || kstrtoul(str + 1, 0, &base))
+		goto out;
+
+	if (reserve_bootmem(base - 8, size + 8, BOOTMEM_EXCLUSIVE)) {
+		pr_err("%s: failed reserving size %d + 8 "
+		       "at base 0x%lx - 8\n", __func__, size, base);
+		goto out;
+	}
+#ifdef CONFIG_SEC_LOG_NONCACHED
+	log_buf_iodesc[0].pfn = __phys_to_pfn((unsigned long)base - 0x100000);
+	log_buf_iodesc[0].length = (unsigned long)(size + 0x100000);
+	iotable_init(log_buf_iodesc, ARRAY_SIZE(log_buf_iodesc));
+	sec_log_mag = (S3C_VA_KLOG_BUF + 0x100000) - 8;
+	sec_log_ptr = (S3C_VA_KLOG_BUF + 0x100000) - 4;
+	sec_log_buf = S3C_VA_KLOG_BUF + 0x100000;
+#else
+	sec_log_mag = phys_to_virt(base) - 8;
+	sec_log_ptr = phys_to_virt(base) - 4;
+	sec_log_buf = phys_to_virt(base);
+#endif
+	sec_log_size = size;
+	pr_info("%s: *sec_log_mag:%x *sec_log_ptr:%x "
+		"sec_log_buf:%p sec_log_size:%d\n",
+		__func__, *sec_log_mag, *sec_log_ptr, sec_log_buf,
+		sec_log_size);
+
+	if (*sec_log_mag != LOG_MAGIC) {
+		pr_info("%s: no old log found\n", __func__);
+		*sec_log_ptr = 0;
+		*sec_log_mag = LOG_MAGIC;
+	} else
+		sec_log_save_old();
+
+	register_log_char_hook(emit_sec_log_char);
+
+	sec_getlog_supply_kloginfo(phys_to_virt(base));
+
+out:
+	return 0;
+}
+
+__setup("sec_log=", sec_log_setup);
+
+#ifdef CONFIG_SEC_LOG_LAST_KMSG
+static void __init sec_log_save_old(void)
+{
+	/* provide previous log as last_kmsg */
+	last_kmsg_size =
+	    min((unsigned)(1 << CONFIG_LOG_BUF_SHIFT), *sec_log_ptr);
+	last_kmsg_buffer = (char *)alloc_bootmem(last_kmsg_size);
+
+	if (last_kmsg_size && last_kmsg_buffer) {
+		unsigned i;
+		for (i = 0; i < last_kmsg_size; i++)
+			last_kmsg_buffer[i] =
+			    sec_log_buf[(*sec_log_ptr - last_kmsg_size +
+					 i) & (sec_log_size - 1)];
+
+		pr_info("%s: saved old log at %d@%p\n",
+			__func__, last_kmsg_size, last_kmsg_buffer);
+	} else
+		pr_err("%s: failed saving old log %d@%p\n",
+		       __func__, last_kmsg_size, last_kmsg_buffer);
+}
+
+static ssize_t sec_log_read_old(struct file *file, char __user *buf,
+				size_t len, loff_t *offset)
+{
+	loff_t pos = *offset;
+	ssize_t count;
+
+	if (pos >= last_kmsg_size)
+		return 0;
+
+	count = min(len, (size_t) (last_kmsg_size - pos));
+	if (copy_to_user(buf, last_kmsg_buffer + pos, count))
+		return -EFAULT;
+
+	*offset += count;
+	return count;
+}
+
+static const struct file_operations last_kmsg_file_ops = {
+	.owner = THIS_MODULE,
+	.read = sec_log_read_old,
+};
+
+static int __init sec_log_late_init(void)
+{
+	struct proc_dir_entry *entry;
+
+	if (last_kmsg_buffer == NULL)
+		return 0;
+
+	entry = create_proc_entry("last_kmsg", S_IFREG | S_IRUGO, NULL);
+	if (!entry) {
+		pr_err("%s: failed to create proc entry\n", __func__);
+		return 0;
+	}
+
+	entry->proc_fops = &last_kmsg_file_ops;
+	entry->size = last_kmsg_size;
+	return 0;
+}
+
+late_initcall(sec_log_late_init);
+#endif
diff --git a/arch/arm/mach-exynos/sec_thermistor.c b/arch/arm/mach-exynos/sec_thermistor.c
new file mode 100644
index 0000000..2ae7ef3
--- /dev/null
+++ b/arch/arm/mach-exynos/sec_thermistor.c
@@ -0,0 +1,285 @@
+/* sec_thermistor.c
+ *
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <plat/adc.h>
+#include <mach/sec_thermistor.h>
+
+#define ADC_SAMPLING_CNT	7
+
+struct sec_therm_info {
+	struct device *dev;
+	struct sec_therm_platform_data *pdata;
+	struct s3c_adc_client *padc;
+	struct delayed_work polling_work;
+
+	int curr_temperature;
+	int curr_temp_adc;
+};
+
+static ssize_t sec_therm_show_temperature(struct device *dev,
+				   struct device_attribute *attr,
+				   char *buf)
+{
+	struct sec_therm_info *info = dev_get_drvdata(dev);
+
+	return sprintf(buf, "%d\n", info->curr_temperature);
+}
+
+static ssize_t sec_therm_show_temp_adc(struct device *dev,
+				   struct device_attribute *attr,
+				   char *buf)
+{
+	struct sec_therm_info *info = dev_get_drvdata(dev);
+
+	return sprintf(buf, "%d\n", info->curr_temp_adc);
+}
+
+static DEVICE_ATTR(temperature, S_IRUGO, sec_therm_show_temperature, NULL);
+static DEVICE_ATTR(temp_adc, S_IRUGO, sec_therm_show_temp_adc, NULL);
+
+static struct attribute *sec_therm_attributes[] = {
+	&dev_attr_temperature.attr,
+	&dev_attr_temp_adc.attr,
+	NULL
+};
+
+static const struct attribute_group sec_therm_group = {
+	.attrs = sec_therm_attributes,
+};
+
+static int sec_therm_get_adc_data(struct sec_therm_info *info)
+{
+	int adc_ch;
+	int adc_data;
+	int adc_max = 0;
+	int adc_min = 0;
+	int adc_total = 0;
+	int i;
+	int err_value;
+
+	adc_ch = info->pdata->adc_channel;
+
+	for (i = 0; i < ADC_SAMPLING_CNT; i++) {
+		adc_data = s3c_adc_read(info->padc, adc_ch);
+
+		if (adc_data < 0) {
+			dev_err(info->dev, "%s : err(%d) returned, skip read\n",
+				__func__, adc_data);
+			err_value = adc_data;
+			goto err;
+		}
+
+		if (i != 0) {
+			if (adc_data > adc_max)
+				adc_max = adc_data;
+			else if (adc_data < adc_min)
+				adc_min = adc_data;
+		} else {
+			adc_max = adc_data;
+			adc_min = adc_data;
+		}
+		adc_total += adc_data;
+	}
+
+	return (adc_total - adc_max - adc_min) / (ADC_SAMPLING_CNT - 2);
+err:
+	return err_value;
+}
+
+static int convert_adc_to_temper(struct sec_therm_info *info, unsigned int adc)
+{
+	int low = 0;
+	int high = 0;
+	int mid = 0;
+
+	if (!info->pdata->adc_table || !info->pdata->adc_arr_size) {
+		/* using fake temp */
+		return 300;
+	}
+
+	high = info->pdata->adc_arr_size - 1;
+
+	while (low <= high) {
+		mid = (low + high) / 2;
+		if (info->pdata->adc_table[mid].adc > adc)
+			high = mid - 1;
+		else if (info->pdata->adc_table[mid].adc < adc)
+			low = mid + 1;
+		else
+			break;
+	}
+	return info->pdata->adc_table[mid].temperature;
+}
+
+static void notify_change_of_temperature(struct sec_therm_info *info)
+{
+	char temp_buf[20];
+	char siop_buf[20];
+	char *envp[2];
+	int env_offset = 0;
+	int siop_level = -1;
+
+	snprintf(temp_buf, sizeof(temp_buf), "TEMPERATURE=%d",
+		 info->curr_temperature);
+	envp[env_offset++] = temp_buf;
+
+	if (info->pdata->get_siop_level)
+		siop_level =
+		    info->pdata->get_siop_level(info->curr_temperature);
+	if (siop_level >= 0) {
+		snprintf(siop_buf, sizeof(siop_buf), "SIOP_LEVEL=%d",
+			 siop_level);
+		envp[env_offset++] = siop_buf;
+		dev_info(info->dev, "%s: uevent: %s\n", __func__, siop_buf);
+	}
+	envp[env_offset] = NULL;
+
+	dev_info(info->dev, "%s: uevent: %s\n", __func__, temp_buf);
+	kobject_uevent_env(&info->dev->kobj, KOBJ_CHANGE, envp);
+}
+
+static void sec_therm_polling_work(struct work_struct *work)
+{
+	struct sec_therm_info *info =
+		container_of(work, struct sec_therm_info, polling_work.work);
+	int adc;
+	int temper;
+
+	adc = sec_therm_get_adc_data(info);
+	dev_dbg(info->dev, "%s: adc=%d\n", __func__, adc);
+
+	if (adc < 0)
+		goto out;
+
+	temper = convert_adc_to_temper(info, adc);
+	dev_dbg(info->dev, "%s: temper=%d\n", __func__, temper);
+
+	/* if temperature was changed, notify to framework */
+	if (info->curr_temperature != temper) {
+		info->curr_temp_adc = adc;
+		info->curr_temperature = temper;
+		notify_change_of_temperature(info);
+	}
+out:
+	schedule_delayed_work(&info->polling_work,
+			msecs_to_jiffies(info->pdata->polling_interval));
+}
+
+static __devinit int sec_therm_probe(struct platform_device *pdev)
+{
+	struct sec_therm_platform_data *pdata = dev_get_platdata(&pdev->dev);
+	struct sec_therm_info *info;
+	int ret = 0;
+
+	dev_info(&pdev->dev, "%s: SEC Thermistor Driver Loading\n", __func__);
+
+	info = kzalloc(sizeof(*info), GFP_KERNEL);
+	if (!info)
+		return -ENOMEM;
+
+	platform_set_drvdata(pdev, info);
+
+	info->dev = &pdev->dev;
+	info->pdata = pdata;
+
+	info->padc = s3c_adc_register(pdev, NULL, NULL, 0);
+
+	ret = sysfs_create_group(&info->dev->kobj, &sec_therm_group);
+
+	if (ret) {
+		dev_err(info->dev,
+			"failed to create sysfs attribute group\n");
+	}
+
+	INIT_DELAYED_WORK_DEFERRABLE(&info->polling_work,
+			sec_therm_polling_work);
+	schedule_delayed_work(&info->polling_work,
+			msecs_to_jiffies(info->pdata->polling_interval));
+
+	return ret;
+}
+
+static int __devexit sec_therm_remove(struct platform_device *pdev)
+{
+	struct sec_therm_info *info = platform_get_drvdata(pdev);
+
+	if (!info)
+		return 0;
+
+	sysfs_remove_group(&info->dev->kobj, &sec_therm_group);
+
+	cancel_delayed_work(&info->polling_work);
+	s3c_adc_release(info->padc);
+	kfree(info);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int sec_therm_suspend(struct device *dev)
+{
+	struct sec_therm_info *info = dev_get_drvdata(dev);
+
+	cancel_delayed_work(&info->polling_work);
+
+	return 0;
+}
+
+static int sec_therm_resume(struct device *dev)
+{
+	struct sec_therm_info *info = dev_get_drvdata(dev);
+
+	schedule_delayed_work(&info->polling_work,
+			msecs_to_jiffies(info->pdata->polling_interval));
+	return 0;
+}
+#else
+#define sec_therm_suspend	NULL
+#define sec_therm_resume	NULL
+#endif /* CONFIG_PM */
+
+static const struct dev_pm_ops sec_thermistor_pm_ops = {
+	.suspend = sec_therm_suspend,
+	.resume = sec_therm_resume,
+};
+
+static struct platform_driver sec_thermistor_driver = {
+	.driver = {
+		   .name = "sec-thermistor",
+		   .owner = THIS_MODULE,
+		   .pm = &sec_thermistor_pm_ops,
+	},
+	.probe = sec_therm_probe,
+	.remove = __devexit_p(sec_therm_remove),
+};
+
+static int __init sec_therm_init(void)
+{
+	return platform_driver_register(&sec_thermistor_driver);
+}
+module_init(sec_therm_init);
+
+static void __exit sec_therm_exit(void)
+{
+	platform_driver_unregister(&sec_thermistor_driver);
+}
+module_exit(sec_therm_exit);
+
+MODULE_AUTHOR("ms925.kim@samsung.com");
+MODULE_DESCRIPTION("sec thermistor driver");
+MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-exynos/sec_watchdog.c b/arch/arm/mach-exynos/sec_watchdog.c
new file mode 100644
index 0000000..b903b80
--- /dev/null
+++ b/arch/arm/mach-exynos/sec_watchdog.c
@@ -0,0 +1,205 @@
+/* sec_watchdog.c copied from herring-watchdog.c
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <plat/regs-watchdog.h>
+#include <mach/map.h>
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+#include <linux/cpufreq.h>
+#include <linux/err.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/workqueue.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/cpu.h>
+
+#ifdef CONFIG_SEC_DEBUG
+#include <mach/sec_debug.h>
+#endif
+
+/* PCLK(=PERIR=ACLK_100)/256/128 (~3200:1s) */
+#define TPS 3200
+#if defined(CONFIG_MACH_P4) && defined(CONFIG_TARGET_LOCALE_USA)
+#define PET_BY_WORKQUEUE
+#else
+#define PET_BY_DIRECT_TIMER
+#endif
+
+/* reset timeout in seconds */
+static unsigned watchdog_reset = 20;
+module_param_named(sec_reset, watchdog_reset, uint, 0644);
+
+/* pet timeout in seconds
+ * 0 means off, 5 is proper */
+static unsigned watchdog_pet = CONFIG_SEC_WATCHDOG_PET_TIME;
+module_param_named(sec_pet, watchdog_pet, uint, 0644);
+
+#if defined(PET_BY_WORKQUEUE)
+static struct workqueue_struct *watchdog_wq;
+static void watchdog_workfunc(struct work_struct *work);
+static DECLARE_DELAYED_WORK(watchdog_work, watchdog_workfunc);
+#elif defined(PET_BY_DIRECT_TIMER)
+static struct timer_list pet_watchdog_timer;
+static void pet_watchdog_timer_fn(unsigned long data);
+#else
+static struct hrtimer watchdog_timer;
+static enum hrtimer_restart watchdog_timerfunc(struct hrtimer *timer);
+#endif
+
+static struct clk *wd_clk;
+static spinlock_t wdt_lock;
+
+#if defined(PET_BY_WORKQUEUE)
+static void watchdog_workfunc(struct work_struct *work)
+{
+	pr_info("%s kicking...%x\n", __func__, readl(S3C2410_WTCNT));
+	writel(watchdog_reset * TPS, S3C2410_WTCNT);
+	queue_delayed_work_on(0, watchdog_wq, &watchdog_work,
+			      watchdog_pet * HZ);
+}
+#elif defined(PET_BY_DIRECT_TIMER)
+static void pet_watchdog_timer_fn(unsigned long data)
+{
+	pr_info("%s kicking...%x\n", __func__, readl(S3C2410_WTCNT));
+	writel(watchdog_reset * TPS, S3C2410_WTCNT);
+	pet_watchdog_timer.expires += watchdog_pet * HZ;
+	add_timer_on(&pet_watchdog_timer, 0);
+}
+#else
+static enum hrtimer_restart watchdog_timerfunc(struct hrtimer *timer)
+{
+	pr_info("%s kicking...%x\n", __func__, readl(S3C2410_WTCNT));
+	writel(watchdog_reset * TPS, S3C2410_WTCNT);
+	hrtimer_start(&watchdog_timer,
+		      ktime_set(watchdog_pet, 0), HRTIMER_MODE_REL);
+	return HRTIMER_NORESTART;
+}
+#endif
+
+static void watchdog_start(void)
+{
+	unsigned int val;
+	unsigned long flags;
+
+	spin_lock_irqsave(&wdt_lock, flags);
+
+	/* set to PCLK / 256 / 128 */
+	val = S3C2410_WTCON_DIV128;
+	val |= S3C2410_WTCON_PRESCALE(255);
+	writel(val, S3C2410_WTCON);
+
+	/* program initial count */
+	writel(watchdog_reset * TPS, S3C2410_WTCNT);
+	writel(watchdog_reset * TPS, S3C2410_WTDAT);
+
+	/* start timer */
+	val |= S3C2410_WTCON_RSTEN | S3C2410_WTCON_ENABLE;
+	writel(val, S3C2410_WTCON);
+	spin_unlock_irqrestore(&wdt_lock, flags);
+
+	/* make sure we're ready to pet the dog */
+#if defined(PET_BY_WORKQUEUE)
+	queue_delayed_work_on(0, watchdog_wq, &watchdog_work,
+			      watchdog_pet * HZ);
+#elif defined(PET_BY_DIRECT_TIMER)
+	pet_watchdog_timer.expires = jiffies + watchdog_pet * HZ;
+	add_timer_on(&pet_watchdog_timer, 0);
+#else
+	hrtimer_start(&watchdog_timer,
+		      ktime_set(watchdog_pet, 0), HRTIMER_MODE_REL);
+#endif
+}
+
+static void watchdog_stop(void)
+{
+	writel(0, S3C2410_WTCON);
+#if defined(PET_BY_WORKQUEUE)
+	/* do nothing? */
+#elif defined(PET_BY_DIRECT_TIMER)
+	del_timer(&pet_watchdog_timer);
+#else
+	hrtimer_cancel(&watchdog_timer);
+#endif
+}
+
+static int watchdog_probe(struct platform_device *pdev)
+{
+	wd_clk = clk_get(NULL, "watchdog");
+	BUG_ON(!wd_clk);
+	clk_enable(wd_clk);
+
+	spin_lock_init(&wdt_lock);
+
+	/* watchdog can be disabled by providing either
+	 * "exynos4210_watchdog.sec_pet=0" or
+	 * "exynos4210_watchdog.sec_reset=0" to CMDLINE */
+	if (!watchdog_reset || !watchdog_pet) {
+		clk_disable(wd_clk);
+		return -ENODEV;
+	}
+
+#if defined(PET_BY_WORKQUEUE)
+	watchdog_wq = create_singlethread_workqueue("pet_watchdog");
+	watchdog_start();
+#elif defined(PET_BY_DIRECT_TIMER)
+	init_timer(&pet_watchdog_timer);
+	pet_watchdog_timer.function = pet_watchdog_timer_fn;
+	watchdog_start();
+#else
+	hrtimer_init(&watchdog_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
+	watchdog_timer.function = watchdog_timerfunc;
+	watchdog_start();
+#endif
+
+	return 0;
+}
+
+static int watchdog_suspend(struct device *dev)
+{
+	watchdog_stop();
+	return 0;
+}
+
+static int watchdog_resume(struct device *dev)
+{
+	watchdog_start();
+	return 0;
+}
+
+static const struct dev_pm_ops watchdog_pm_ops = {
+	.suspend_noirq = watchdog_suspend,
+	.resume_noirq = watchdog_resume,
+};
+
+static struct platform_driver watchdog_driver = {
+	.probe = watchdog_probe,
+	.driver = {
+		   .owner = THIS_MODULE,
+		   .name = "watchdog-reset",
+		   .pm = &watchdog_pm_ops,
+	},
+};
+
+static int __init watchdog_init(void)
+{
+	return platform_driver_register(&watchdog_driver);
+}
+
+module_init(watchdog_init);
diff --git a/arch/arm/mach-exynos/secmem-allocdev.c b/arch/arm/mach-exynos/secmem-allocdev.c
new file mode 100644
index 0000000..ce0b3d4
--- /dev/null
+++ b/arch/arm/mach-exynos/secmem-allocdev.c
@@ -0,0 +1,331 @@
+/*
+ * arch/arm/mach-exynos/secmem-allocdev.c
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/device.h>
+#include <linux/cma.h>
+#include <linux/uaccess.h>
+#include <linux/fs.h>
+#include <linux/pm_runtime.h>
+#include <linux/slab.h>
+#include <linux/mm.h>
+#include <linux/dma-mapping.h>
+
+#include <asm/memory.h>
+#include <asm/cacheflush.h>
+
+#include <plat/devs.h>
+#include <plat/pd.h>
+
+#include <mach/secmem.h>
+#include <mach/dev.h>
+
+#define MFC_SEC_MAGIC_CHUNK0	0x13cdbf16
+#define MFC_SEC_MAGIC_CHUNK1	0x8b803342
+#define MFC_SEC_MAGIC_CHUNK2	0x5e87f4f5
+#define MFC_SEC_MAGIC_CHUNK3	0x3bd05317
+
+struct miscdevice secmem;
+struct secmem_crypto_driver_ftn *crypto_driver;
+#if defined(CONFIG_ION)
+extern struct ion_device *ion_exynos;
+#endif
+
+#if defined(CONFIG_MACH_MIDAS)
+static char *secmem_info[] = {
+	"mfc",		/* 0 */
+	"fimc",         /* 1 */
+	"mfc-shm",      /* 2 */
+	"sectbl",       /* 3 */
+	"fimd",		/* 4 */
+	NULL
+};
+#else
+static char *secmem_info[] = {
+	"mfc",		/* 0 */
+	"fimc",		/* 1 */
+	"mfc-shm",	/* 2 */
+	"sectbl",	/* 3 */
+	"video",	/* 4 */
+	"fimd",		/* 5 */
+	NULL
+};
+#endif
+
+static bool drm_onoff = false;
+
+#define SECMEM_IS_PAGE_ALIGNED(addr) (!((addr) & (~PAGE_MASK)))
+
+static int secmem_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	unsigned long size = vma->vm_end - vma->vm_start;
+
+	BUG_ON(!SECMEM_IS_PAGE_ALIGNED(vma->vm_start));
+	BUG_ON(!SECMEM_IS_PAGE_ALIGNED(vma->vm_end));
+
+	vma->vm_flags |= VM_RESERVED;
+	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+
+	if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
+				size, vma->vm_page_prot)) {
+		printk(KERN_ERR "%s : remap_pfn_range() failed!\n", __func__);
+		return -EAGAIN;
+	}
+
+	return 0;
+}
+
+static long secmem_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
+{
+	switch (cmd) {
+	case SECMEM_IOC_CHUNKINFO:
+	{
+		struct cma_info info;
+		struct secchunk_info minfo;
+		char **mname;
+		int nbufs = 0;
+
+		for (mname = secmem_info; *mname != NULL; mname++)
+			nbufs++;
+
+		if (nbufs == 0)
+			return -ENOMEM;
+
+		if (copy_from_user(&minfo, (void __user *)arg, sizeof(minfo)))
+			return -EFAULT;
+
+		if (minfo.index < 0)
+			return -EINVAL;
+
+		if (minfo.index >= nbufs) {
+			minfo.index = -1; /* No more memory region */
+		} else {
+
+			if (cma_info(&info, secmem.this_device,
+					secmem_info[minfo.index]))
+				return -EINVAL;
+
+			minfo.base = info.lower_bound;
+			minfo.size = info.total_size;
+		}
+
+		if (copy_to_user((void __user *)arg, &minfo, sizeof(minfo)))
+			return -EFAULT;
+	}
+	break;
+
+#if defined(CONFIG_ION) && defined(CONFIG_CPU_EXYNOS5250)
+	case SECMEM_IOC_GET_FD_PHYS_ADDR:
+	{
+		struct ion_client *client;
+		struct secfd_info fd_info;
+		struct ion_fd_data data;
+		size_t len;
+
+		if (copy_from_user(&fd_info, (int __user *)arg,
+					sizeof(fd_info)))
+			return -EFAULT;
+
+		client = ion_client_create(ion_exynos, -1, "DRM");
+		if (IS_ERR(client))
+			printk(KERN_ERR "%s: Failed to get ion_client of DRM\n",
+				__func__);
+
+		data.fd = fd_info.fd;
+		data.handle = ion_import_fd(client, data.fd);
+		printk(KERN_DEBUG "%s: fd from user space = %d\n",
+				__func__, fd_info.fd);
+		if (IS_ERR(data.handle))
+			printk(KERN_ERR "%s: Failed to get ion_handle of DRM\n",
+				__func__);
+
+		if (ion_phys(client, data.handle, &fd_info.phys, &len))
+			printk(KERN_ERR "%s: Failed to get phys. addr of DRM\n",
+				__func__);
+
+		printk(KERN_DEBUG "%s: physical addr from kernel space = %lu\n",
+				__func__, fd_info.phys);
+
+		ion_free(client, data.handle);
+		ion_client_destroy(client);
+
+		if (copy_to_user((void __user *)arg, &fd_info, sizeof(fd_info)))
+			return -EFAULT;
+		break;
+	}
+#endif
+	case SECMEM_IOC_GET_DRM_ONOFF:
+		if (copy_to_user((void __user *)arg, &drm_onoff, sizeof(int)))
+			return -EFAULT;
+		break;
+	case SECMEM_IOC_SET_DRM_ONOFF:
+	{
+		int val = 0;
+
+		if (copy_from_user(&val, (int __user *)arg, sizeof(int)))
+			return -EFAULT;
+
+		if (val) {
+			if (drm_onoff == false) {
+				drm_onoff = true;
+				pm_runtime_forbid((*(secmem.this_device)).parent);
+			} else
+				printk(KERN_ERR "%s: DRM is already on\n", __func__);
+		} else {
+			if (drm_onoff == true) {
+				drm_onoff = false;
+				pm_runtime_allow((*(secmem.this_device)).parent);
+			} else
+				printk(KERN_ERR "%s: DRM is already off\n", __func__);
+		}
+		break;
+	}
+	case SECMEM_IOC_GET_CRYPTO_LOCK:
+	{
+		int i;
+		int ret;
+
+		if (crypto_driver) {
+			for (i = 0; i < 100; i++) {
+				ret = crypto_driver->lock();
+				if (ret == 0)
+					break;
+				printk(KERN_ERR "%s : Retry to get sync lock.\n",
+					__func__);
+			}
+			return ret;
+		}
+		break;
+	}
+	case SECMEM_IOC_RELEASE_CRYPTO_LOCK:
+	{
+		if (crypto_driver)
+			return crypto_driver->release();
+		break;
+	}
+	case SECMEM_IOC_GET_ADDR:
+	{
+		struct secmem_region region;
+
+		if (copy_from_user(&region, (void __user *)arg,
+					sizeof(struct secmem_region)))
+			return -EFAULT;
+
+		if (!region.len) {
+			printk(KERN_ERR "Get secmem address size error. [size : %ld]\n", region.len);
+			return -EFAULT;
+		}
+
+		region.virt_addr = kmalloc(region.len, GFP_KERNEL | GFP_DMA);
+		if (!region.virt_addr) {
+			printk(KERN_ERR "%s: Get memory address failed. [size : %ld]\n", __func__, region.len);
+			return -EFAULT;
+		}
+		region.phys_addr = virt_to_phys(region.virt_addr);
+
+		dma_map_single(secmem.this_device, region.virt_addr, region.len, DMA_TO_DEVICE);
+
+		if (copy_to_user((void __user *)arg, &region,
+					sizeof(struct secmem_region)))
+			return -EFAULT;
+		break;
+	}
+	case SECMEM_IOC_RELEASE_ADDR:
+	{
+		struct secmem_region region;
+
+		if (copy_from_user(&region, (void __user *)arg,
+					sizeof(struct secmem_region)))
+			return -EFAULT;
+
+		if (!region.virt_addr) {
+			printk(KERN_ERR "Get secmem address error. [address : %x]\n", (uint32_t)region.virt_addr);
+			return -EFAULT;
+		}
+
+		kfree(region.virt_addr);
+		break;
+	}
+
+	case SECMEM_IOC_MFC_MAGIC_KEY:
+	{
+		uint32_t mfc_shm_virtaddr;
+		struct cma_info info;
+		struct secchunk_info minfo;
+
+#if defined(CONFIG_CPU_EXYNOS4212) || defined(CONFIG_CPU_EXYNOS4412)
+		if (cma_info(&info, secmem.this_device, "mfc-shm"))
+			return -EINVAL;
+#elif defined(CONFIG_CPU_EXYNOS5250)
+		if (cma_info(&info, secmem.this_device, "mfc_sh"))
+			return -EINVAL;
+#endif
+
+		minfo.base = info.lower_bound;
+		minfo.size = info.total_size;
+
+		mfc_shm_virtaddr = (uint32_t)phys_to_virt(minfo.base);
+
+		*(uint32_t *)(mfc_shm_virtaddr) = MFC_SEC_MAGIC_CHUNK0;
+		*(uint32_t *)(mfc_shm_virtaddr + 0x4) = MFC_SEC_MAGIC_CHUNK1;
+		*(uint32_t *)(mfc_shm_virtaddr + 0x8) = MFC_SEC_MAGIC_CHUNK2;
+		*(uint32_t *)(mfc_shm_virtaddr + 0xC) = MFC_SEC_MAGIC_CHUNK3;
+		break;
+	}
+	default:
+		return -ENOTTY;
+	}
+
+	return 0;
+}
+
+void secmem_crypto_register(struct secmem_crypto_driver_ftn *ftn)
+{
+	crypto_driver = ftn;
+}
+EXPORT_SYMBOL(secmem_crypto_register);
+
+void secmem_crypto_deregister(void)
+{
+	crypto_driver = NULL;
+}
+EXPORT_SYMBOL(secmem_crypto_deregister);
+
+static struct file_operations secmem_fops = {
+	.unlocked_ioctl = &secmem_ioctl,
+	.mmap		= secmem_mmap,
+};
+
+static int __init secmem_init(void)
+{
+	int ret;
+	secmem.minor = MISC_DYNAMIC_MINOR;
+	secmem.name = "s5p-smem";
+	secmem.fops = &secmem_fops;
+
+	ret = misc_register(&secmem);
+	if (ret)
+		return ret;
+
+	crypto_driver = NULL;
+
+	pm_runtime_enable(secmem.this_device);
+
+	return 0;
+}
+
+static void __exit secmem_exit(void)
+{
+	__pm_runtime_disable(secmem.this_device, false);
+	misc_deregister(&secmem);
+}
+
+module_init(secmem_init);
+module_exit(secmem_exit);
diff --git a/arch/arm/mach-exynos/setup-c2c.c b/arch/arm/mach-exynos/setup-c2c.c
new file mode 100644
index 0000000..9d18bb6
--- /dev/null
+++ b/arch/arm/mach-exynos/setup-c2c.c
@@ -0,0 +1,151 @@
+/* linux/arch/arm/mach-exynos/setup-c2c.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * EXYNOS4212 - Helper functions for setting up C2C device(s) GPIO
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+
+#include <mach/gpio.h>
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/c2c.h>
+#include <plat/gpio-cfg.h>
+#include <plat/cpu.h>
+
+void exynos_c2c_set_cprst(void)
+{
+	/* TODO */
+}
+
+void exynos_c2c_clear_cprst(void)
+{
+	/* TODO */
+}
+
+void exynos4_c2c_cfg_gpio(enum c2c_buswidth rx_width, enum c2c_buswidth tx_width,
+						void __iomem *etc8drv_addr)
+{
+	int i;
+
+	/* Set GPIO for C2C Rx */
+	s3c_gpio_cfgrange_nopull(EXYNOS4212_GPV0(0), 8, S3C_GPIO_SFN(2));
+	for (i = 0; i < 8; i++) {
+		s5p_gpio_set_drvstr(EXYNOS4212_GPV0(i), S5P_GPIO_DRVSTR_LV1);
+		s5p_gpio_set_pd_cfg(EXYNOS4212_GPV0(i), S5P_GPIO_PD_INPUT);
+		s5p_gpio_set_pd_pull(EXYNOS4212_GPV0(i), S5P_GPIO_PD_DOWN_ENABLE);
+	}
+
+	if (rx_width == C2C_BUSWIDTH_16) {
+		s3c_gpio_cfgrange_nopull(EXYNOS4212_GPV1(0), 8, S3C_GPIO_SFN(2));
+		for (i = 0; i < 8; i++) {
+			s5p_gpio_set_drvstr(EXYNOS4212_GPV1(i), S5P_GPIO_DRVSTR_LV1);
+			s5p_gpio_set_pd_cfg(EXYNOS4212_GPV1(i), S5P_GPIO_PD_INPUT);
+			s5p_gpio_set_pd_pull(EXYNOS4212_GPV1(i), S5P_GPIO_PD_DOWN_ENABLE);
+		}
+	} else if (rx_width == C2C_BUSWIDTH_10) {
+		s3c_gpio_cfgrange_nopull(EXYNOS4212_GPV1(0), 2, S3C_GPIO_SFN(2));
+		for (i = 0; i < 2; i++) {
+			s5p_gpio_set_drvstr(EXYNOS4212_GPV1(i), S5P_GPIO_DRVSTR_LV1);
+			s5p_gpio_set_pd_cfg(EXYNOS4212_GPV1(i), S5P_GPIO_PD_INPUT);
+			s5p_gpio_set_pd_pull(EXYNOS4212_GPV1(i), S5P_GPIO_PD_DOWN_ENABLE);
+		}
+	}
+
+	/* Set GPIO for C2C Tx */
+	s3c_gpio_cfgrange_nopull(EXYNOS4212_GPV2(0), 8, S3C_GPIO_SFN(2));
+	for (i = 0; i < 8; i++)
+		s5p_gpio_set_drvstr(EXYNOS4212_GPV2(i), S5P_GPIO_DRVSTR_LV3);
+
+	if (tx_width == C2C_BUSWIDTH_16) {
+		s3c_gpio_cfgrange_nopull(EXYNOS4212_GPV3(0), 8, S3C_GPIO_SFN(2));
+		for (i = 0; i < 8; i++)
+			s5p_gpio_set_drvstr(EXYNOS4212_GPV3(i), S5P_GPIO_DRVSTR_LV3);
+	} else if (tx_width == C2C_BUSWIDTH_10) {
+		s3c_gpio_cfgrange_nopull(EXYNOS4212_GPV3(0), 2, S3C_GPIO_SFN(2));
+		for (i = 0; i < 2; i++)
+			s5p_gpio_set_drvstr(EXYNOS4212_GPV3(i), S5P_GPIO_DRVSTR_LV3);
+	}
+
+	/* Set GPIO for WakeReqOut/In */
+	s3c_gpio_cfgrange_nopull(EXYNOS4212_GPV4(0), 2, S3C_GPIO_SFN(2));
+	s5p_gpio_set_pd_cfg(EXYNOS4212_GPV4(0), S5P_GPIO_PD_INPUT);
+	s5p_gpio_set_pd_pull(EXYNOS4212_GPV4(0), S5P_GPIO_PD_DOWN_ENABLE);
+
+	writel(0x5, etc8drv_addr);
+}
+
+void exynos5_c2c_cfg_gpio(enum c2c_buswidth rx_width, enum c2c_buswidth tx_width,
+						void __iomem *etc8drv_addr)
+{
+	int i;
+
+	/* Set GPIO for C2C Rx */
+	s3c_gpio_cfgrange_nopull(EXYNOS5_GPV0(0), 8, S3C_GPIO_SFN(2));
+	for (i = 0; i < 8; i++) {
+		s5p_gpio_set_drvstr(EXYNOS5_GPV0(i), S5P_GPIO_DRVSTR_LV1);
+		s5p_gpio_set_pd_cfg(EXYNOS5_GPV0(i), S5P_GPIO_PD_INPUT);
+		s5p_gpio_set_pd_pull(EXYNOS5_GPV0(i), S5P_GPIO_PD_DOWN_ENABLE);
+	}
+
+	if (rx_width == C2C_BUSWIDTH_16) {
+		s3c_gpio_cfgrange_nopull(EXYNOS5_GPV1(0), 8, S3C_GPIO_SFN(2));
+		for (i = 0; i < 8; i++) {
+			s5p_gpio_set_drvstr(EXYNOS5_GPV1(i), S5P_GPIO_DRVSTR_LV1);
+			s5p_gpio_set_pd_cfg(EXYNOS5_GPV1(i), S5P_GPIO_PD_INPUT);
+			s5p_gpio_set_pd_pull(EXYNOS5_GPV1(i), S5P_GPIO_PD_DOWN_ENABLE);
+		}
+	} else if (rx_width == C2C_BUSWIDTH_10) {
+		s3c_gpio_cfgrange_nopull(EXYNOS5_GPV1(0), 2, S3C_GPIO_SFN(2));
+		for (i = 0; i < 2; i++) {
+			s5p_gpio_set_drvstr(EXYNOS5_GPV1(i), S5P_GPIO_DRVSTR_LV1);
+			s5p_gpio_set_pd_cfg(EXYNOS5_GPV1(i), S5P_GPIO_PD_INPUT);
+			s5p_gpio_set_pd_pull(EXYNOS5_GPV1(i), S5P_GPIO_PD_DOWN_ENABLE);
+		}
+	}
+
+	/* Set GPIO for C2C Tx */
+	s3c_gpio_cfgrange_nopull(EXYNOS5_GPV2(0), 8, S3C_GPIO_SFN(2));
+	for (i = 0; i < 8; i++)
+		s5p_gpio_set_drvstr(EXYNOS5_GPV2(i), S5P_GPIO_DRVSTR_LV3);
+
+	if (tx_width == C2C_BUSWIDTH_16) {
+		s3c_gpio_cfgrange_nopull(EXYNOS5_GPV3(0), 8, S3C_GPIO_SFN(2));
+		for (i = 0; i < 8; i++)
+			s5p_gpio_set_drvstr(EXYNOS5_GPV3(i), S5P_GPIO_DRVSTR_LV3);
+	} else if (tx_width == C2C_BUSWIDTH_10) {
+		s3c_gpio_cfgrange_nopull(EXYNOS5_GPV3(0), 2, S3C_GPIO_SFN(2));
+		for (i = 0; i < 2; i++)
+			s5p_gpio_set_drvstr(EXYNOS5_GPV3(i), S5P_GPIO_DRVSTR_LV3);
+	}
+
+	/* Set GPIO for WakeReqOut/In */
+	s3c_gpio_cfgrange_nopull(EXYNOS5_GPV4(0), 2, S3C_GPIO_SFN(2));
+	s5p_gpio_set_pd_cfg(EXYNOS5_GPV4(0), S5P_GPIO_PD_INPUT);
+	s5p_gpio_set_pd_pull(EXYNOS5_GPV4(0), S5P_GPIO_PD_DOWN_ENABLE);
+
+	writel(0x5, etc8drv_addr);
+}
+
+void exynos_c2c_cfg_gpio(enum c2c_buswidth rx_width, enum c2c_buswidth tx_width)
+{
+	void __iomem *etc8drv_addr;
+	if (soc_is_exynos4212() || soc_is_exynos4412()) {
+		/* ETC8DRV is used for setting Tx clock drive strength */
+		etc8drv_addr = S5P_VA_GPIO4 + 0xAC;
+		exynos4_c2c_cfg_gpio(rx_width, tx_width, etc8drv_addr);
+	} else if (soc_is_exynos5250()) {
+		/* ETC8DRV is used for setting Tx clock drive strength */
+		etc8drv_addr = S5P_VA_GPIO3 + 0xAC;
+		exynos5_c2c_cfg_gpio(rx_width, tx_width, etc8drv_addr);
+	}
+}
\ No newline at end of file
diff --git a/arch/arm/mach-exynos/setup-csis.c b/arch/arm/mach-exynos/setup-csis.c
new file mode 100644
index 0000000..e342aa8
--- /dev/null
+++ b/arch/arm/mach-exynos/setup-csis.c
@@ -0,0 +1,159 @@
+/* linux/arch/arm/mach-exynos/setup-csis.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *	http://www.samsung.com/
+ *
+ * EXYNOS4 - Base MIPI-CSI2 gpio configuration
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/gpio.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <plat/clock.h>
+#include <plat/gpio-cfg.h>
+#include <mach/regs-gpio.h>
+#include <plat/map-s5p.h>
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <plat/csis.h>
+
+#ifdef DEBUG
+#define dbg(fmt, args...) \
+	printk(KERN_INFO "%s:%d: " fmt "\n", __func__, __LINE__, ##args)
+#else
+#define dbg(fmt, args...)
+#endif
+
+struct platform_device; /* don't need the contents */
+
+void s3c_csis0_cfg_gpio(void) { }
+void s3c_csis1_cfg_gpio(void) { }
+
+void s3c_csis0_cfg_phy_global(int on)
+{
+	u32 cfg;
+
+	if (on) {
+		/* MIPI D-PHY Power Enable */
+		cfg = __raw_readl(EXYNOS4_MIPI_CONTROL0);
+		cfg |= EXYNOS4_MIPI_DPHY_S_RESETN;
+		__raw_writel(cfg, EXYNOS4_MIPI_CONTROL0);
+
+		cfg = __raw_readl(EXYNOS4_MIPI_CONTROL0);
+		cfg |= EXYNOS4_MIPI_DPHY_EN;
+		__raw_writel(cfg, EXYNOS4_MIPI_CONTROL0);
+
+		dbg(KERN_INFO "csis0 on\n");
+	} else {
+		/* MIPI Power Disable */
+		cfg = __raw_readl(EXYNOS4_MIPI_CONTROL0);
+		cfg &= ~EXYNOS4_MIPI_DPHY_S_RESETN;
+
+		if (!(cfg & EXYNOS4_MIPI_DPHY_M_RESETN))
+			cfg &= ~EXYNOS4_MIPI_DPHY_EN;
+
+		__raw_writel(cfg, EXYNOS4_MIPI_CONTROL0);
+
+		dbg(KERN_INFO "csis0 off\n");
+	}
+}
+void s3c_csis1_cfg_phy_global(int on)
+{
+	u32 cfg;
+
+	if (on) {
+		/* MIPI D-PHY Power Enable */
+		cfg = __raw_readl(EXYNOS4_MIPI_CONTROL1);
+		cfg |= EXYNOS4_MIPI_DPHY_S_RESETN;
+		__raw_writel(cfg, EXYNOS4_MIPI_CONTROL1);
+
+		cfg = __raw_readl(EXYNOS4_MIPI_CONTROL1);
+		cfg |= EXYNOS4_MIPI_DPHY_EN;
+		__raw_writel(cfg, EXYNOS4_MIPI_CONTROL1);
+
+		dbg(KERN_INFO "csis1 on\n");
+	} else {
+		/* MIPI Power Disable */
+		cfg = __raw_readl(EXYNOS4_MIPI_CONTROL1);
+		cfg &= ~EXYNOS4_MIPI_DPHY_S_RESETN;
+
+		if (!(cfg & EXYNOS4_MIPI_DPHY_M_RESETN))
+			cfg &= ~EXYNOS4_MIPI_DPHY_EN;
+
+		__raw_writel(cfg, EXYNOS4_MIPI_CONTROL1);
+
+		dbg(KERN_INFO "csis1 off\n");
+	}
+}
+int s3c_csis_clk_on(struct platform_device *pdev, struct clk **clk)
+{
+	struct s3c_platform_csis *pdata;
+	struct clk *sclk_csis = NULL;
+	struct clk *mout_mpll = NULL;
+
+	pdata = to_csis_plat(&pdev->dev);
+
+	/* mout_mpll */
+	mout_mpll = clk_get(&pdev->dev, pdata->srclk_name);
+	if (IS_ERR(mout_mpll)) {
+		dev_err(&pdev->dev, "failed to get mout_mpll\n");
+		goto err_clk1;
+	}
+
+	/* sclk_csis */
+	sclk_csis = clk_get(&pdev->dev, pdata->clk_name);
+	if (IS_ERR(sclk_csis)) {
+		dev_err(&pdev->dev, "failed to get sclk_csis\n");
+		goto err_clk2;
+	}
+
+	if (clk_set_parent(sclk_csis, mout_mpll)) {
+		dev_err(&pdev->dev, "Unable to set parent %s of clock %s.\n",
+				mout_mpll->name, sclk_csis->name);
+		goto err_clk3;
+	}
+
+	if (clk_set_rate(sclk_csis, pdata->clk_rate)) {
+		dev_err(&pdev->dev, "%s rate change failed: %lu\n",
+				sclk_csis->name, pdata->clk_rate);
+		goto err_clk3;
+	}
+
+	/* csis */
+	*clk = clk_get(&pdev->dev, "csis");
+	if (IS_ERR(*clk)) {
+		dev_err(&pdev->dev, "failed to get csis clock\n");
+		goto err_clk3;
+	}
+	/* clock enable for csis */
+	clk_enable(*clk);
+	clk_enable(sclk_csis);
+
+	return 0;
+
+err_clk3:
+	clk_put(sclk_csis);
+
+err_clk2:
+	clk_put(mout_mpll);
+
+err_clk1:
+	return -EINVAL;
+}
+int s3c_csis_clk_off(struct platform_device *pdev, struct clk **clk)
+{
+	clk_disable(*clk);
+	clk_put(*clk);
+
+	*clk = NULL;
+
+	return 0;
+}
diff --git a/arch/arm/mach-exynos/setup-dp.c b/arch/arm/mach-exynos/setup-dp.c
new file mode 100644
index 0000000..92821be
--- /dev/null
+++ b/arch/arm/mach-exynos/setup-dp.c
@@ -0,0 +1,32 @@
+/* linux/arch/arm/mach-exynos/setup-dp.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *	http://www.samsung.com/
+ *
+ * Base Samsung Exynos DP configuration
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/io.h>
+#include <mach/regs-clock.h>
+
+void s5p_dp_phy_init(void)
+{
+	u32 reg;
+
+	reg = __raw_readl(S5P_DPTX_PHY_CONTROL);
+	reg |= S5P_DPTX_PHY_ENABLE;
+	__raw_writel(reg, S5P_DPTX_PHY_CONTROL);
+}
+
+void s5p_dp_phy_exit(void)
+{
+	u32 reg;
+
+	reg = __raw_readl(S5P_DPTX_PHY_CONTROL);
+	reg &= ~S5P_DPTX_PHY_ENABLE;
+	__raw_writel(reg, S5P_DPTX_PHY_CONTROL);
+}
diff --git a/arch/arm/mach-exynos/setup-dsim.c b/arch/arm/mach-exynos/setup-dsim.c
new file mode 100644
index 0000000..e1ba8eea
--- /dev/null
+++ b/arch/arm/mach-exynos/setup-dsim.c
@@ -0,0 +1,120 @@
+/* linux/arch/arm/mach-exynos/setup-dsim.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * DSIM controller configuration
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/gpio.h>
+#include <plat/clock.h>
+#include <plat/regs-dsim.h>
+#include <plat/gpio-cfg.h>
+#include <mach/map.h>
+#include <mach/regs-pmu.h>
+
+#define S5P_MIPI_M_RESETN 4
+
+static void s5p_dsim_enable_d_phy(unsigned char enable)
+{
+	unsigned int reg;
+
+	reg = readl(S5P_MIPI_DPHY_CONTROL(0));
+	if (enable)
+		reg |= S5P_MIPI_DPHY_ENABLE;
+	else if (!(reg & S5P_MIPI_DPHY_SRESETN))
+		reg &= ~S5P_MIPI_DPHY_ENABLE;
+	writel(reg, S5P_MIPI_DPHY_CONTROL(0));
+}
+
+static void s5p_dsim_enable_dsi_master(unsigned char enable)
+{
+	unsigned int reg;
+
+	reg = (readl(S5P_MIPI_DPHY_CONTROL(0))) & ~(1 << 2);
+	reg |= (enable << 2);
+	writel(reg, S5P_MIPI_DPHY_CONTROL(0));
+}
+
+void s5p_dsim_enable_clk(void *d_clk, unsigned char enable)
+{
+	int ret = 0;
+	struct clk *dsim_clk = (struct clk *) d_clk;
+
+	if (enable) {
+		ret = clk_enable(dsim_clk);
+		if (ret < 0)
+			printk("failed to clk_enable of dsim\n");
+	} else
+		clk_disable(dsim_clk);
+}
+
+void s5p_dsim_part_reset(void)
+{
+	writel(S5P_MIPI_M_RESETN, S5P_MIPI_DPHY_CONTROL(0));
+}
+
+void s5p_dsim_init_d_phy(unsigned int dsim_base)
+{
+	/* enable D-PHY */
+	s5p_dsim_enable_d_phy(1);
+
+	/* enable DSI master block */
+	s5p_dsim_enable_dsi_master(1);
+}
+
+void s5p_dsim_exit_d_phy(unsigned int dsim_base)
+{
+	/* enable DSI master block */
+	s5p_dsim_enable_dsi_master(0);
+
+	/* enable D-PHY */
+	s5p_dsim_enable_d_phy(0);
+}
+
+static void exynos4_dsim_setup_24bpp(unsigned int start, unsigned int size,
+		unsigned int cfg, s5p_gpio_drvstr_t drvstr)
+{
+	s3c_gpio_cfgrange_nopull(start, size, cfg);
+
+	for (; size > 0; size--, start++)
+		s5p_gpio_set_drvstr(start, drvstr);
+}
+
+void exynos4_dsim_gpio_setup_24bpp(void)
+{
+	unsigned int reg = 0;
+
+	/*
+	 * Set DISPLAY_CONTROL register for Display path selection.
+	 *
+	 * DISPLAY_CONTROL[1:0]
+	 * ---------------------
+	 *  00 | MIE
+	 *  01 | MDINE
+	 *  10 | FIMD : selected
+	 *  11 | FIMD
+	 */
+#ifdef CONFIG_FB_S5P_MDNIE
+	reg = __raw_readl(S3C_VA_SYS + 0x0210);
+	reg &= ~(1<<13);
+	reg &= ~(1<<12);
+	reg &= ~(3<<10);
+	reg |= (1<<0);
+	reg &= ~(1<<1);
+	__raw_writel(reg, S3C_VA_SYS + 0x0210);
+#else
+	reg = __raw_readl(S3C_VA_SYS + 0x0210);
+	reg |= (1 << 1);
+	__raw_writel(reg, S3C_VA_SYS + 0x0210);
+#endif
+}
diff --git a/arch/arm/mach-exynos/setup-fb-s5p.c b/arch/arm/mach-exynos/setup-fb-s5p.c
new file mode 100644
index 0000000..21b2199
--- /dev/null
+++ b/arch/arm/mach-exynos/setup-fb-s5p.c
@@ -0,0 +1,970 @@
+/* linux/arch/arm/mach-exynos/setup-fb-s5p.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Base FIMD controller configuration
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/gpio.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/types.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/gcd.h>
+
+#include <mach/regs-clock.h>
+#include <mach/regs-gpio.h>
+#include <mach/map.h>
+#include <mach/gpio.h>
+#include <mach/board_rev.h>
+
+#include <plat/clock.h>
+#include <plat/gpio-cfg.h>
+#include <plat/cpu.h>
+#include <plat/clock-clksrc.h>
+#include <../../../drivers/video/samsung/s3cfb.h>	/* should be fixed */
+
+struct platform_device; /* don't need the contents */
+
+#ifdef CONFIG_FB_S5P
+#if !defined(CONFIG_FB_S5P_MIPI_DSIM)
+static void s3cfb_gpio_setup_24bpp(unsigned int start, unsigned int size,
+		unsigned int cfg, s5p_gpio_drvstr_t drvstr)
+{
+	u32 reg;
+
+	s3c_gpio_cfgrange_nopull(start, size, cfg);
+
+	for (; size > 0; size--, start++)
+		s5p_gpio_set_drvstr(start, drvstr);
+
+#ifdef CONFIG_FB_S5P_MDNIE
+	reg = __raw_readl(S3C_VA_SYS + 0x0210);
+	reg &= ~(1<<13);
+	reg &= ~(1<<12);
+	reg &= ~(3<<10);
+	reg |= (1<<0);
+	reg &= ~(1<<1);
+	__raw_writel(reg, S3C_VA_SYS + 0x0210);
+#else
+	reg = __raw_readl(S3C_VA_SYS + 0x0210);
+	reg |= (1<<1);
+	__raw_writel(reg, S3C_VA_SYS + 0x0210);
+#endif
+}
+#endif
+
+#if defined(CONFIG_FB_S5P_WA101S) || defined(CONFIG_FB_S5P_LTE480WV)
+void s3cfb_cfg_gpio(struct platform_device *pdev)
+{
+	s3cfb_gpio_setup_24bpp(EXYNOS4_GPF0(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV4);
+	s3cfb_gpio_setup_24bpp(EXYNOS4_GPF1(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV4);
+	s3cfb_gpio_setup_24bpp(EXYNOS4_GPF2(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV4);
+	s3cfb_gpio_setup_24bpp(EXYNOS4_GPF3(0), 4, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV4);
+}
+#elif defined(CONFIG_FB_S5P_AMS369FG06)
+void s3cfb_cfg_gpio(struct platform_device *pdev)
+{
+	s3cfb_gpio_setup_24bpp(EXYNOS4_GPF0(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV1);
+	s3cfb_gpio_setup_24bpp(EXYNOS4_GPF1(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV1);
+	s3cfb_gpio_setup_24bpp(EXYNOS4_GPF2(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV1);
+	s3cfb_gpio_setup_24bpp(EXYNOS4_GPF3(0), 4, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV1);
+}
+#elif defined(CONFIG_FB_S5P_LMS501KF03)
+void s3cfb_cfg_gpio(struct platform_device *pdev)
+{
+	s3cfb_gpio_setup_24bpp(EXYNOS4_GPF0(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV4);
+	s3cfb_gpio_setup_24bpp(EXYNOS4_GPF1(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV1);
+	s3cfb_gpio_setup_24bpp(EXYNOS4_GPF2(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV1);
+	s3cfb_gpio_setup_24bpp(EXYNOS4_GPF3(0), 4, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV1);
+}
+#elif defined(CONFIG_FB_S5P_HT101HD1)
+void s3cfb_cfg_gpio(struct platform_device *pdev)
+{
+	s3cfb_gpio_setup_24bpp(EXYNOS4_GPF0(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV1);
+	s3cfb_gpio_setup_24bpp(EXYNOS4_GPF1(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV1);
+	s3cfb_gpio_setup_24bpp(EXYNOS4_GPF2(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV1);
+	s3cfb_gpio_setup_24bpp(EXYNOS4_GPF3(0), 4, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV1);
+}
+#elif defined(CONFIG_FB_S5P_LD9040) || defined(CONFIG_FB_S5P_S6C1372) || defined(CONFIG_FB_S5P_S6F1202A)
+void s3cfb_cfg_gpio(struct platform_device *pdev)
+{
+	s3cfb_gpio_setup_24bpp(EXYNOS4_GPF0(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV4);
+	s3cfb_gpio_setup_24bpp(EXYNOS4_GPF1(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV4);
+	s3cfb_gpio_setup_24bpp(EXYNOS4_GPF2(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV4);
+	s3cfb_gpio_setup_24bpp(EXYNOS4_GPF3(0), 4, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV4);
+}
+#else
+void s3cfb_cfg_gpio(struct platform_device *pdev)
+{
+	u32 reg;
+
+#ifdef CONFIG_FB_S5P_MDNIE
+	reg = __raw_readl(S3C_VA_SYS + 0x0210);
+	reg &= ~(1<<13);
+	reg &= ~(1<<12);
+	reg &= ~(3<<10);
+	reg |= (1<<0);
+	reg &= ~(1<<1);
+	__raw_writel(reg, S3C_VA_SYS + 0x0210);
+#else
+	reg = __raw_readl(S3C_VA_SYS + 0x0210);
+	reg |= (1<<1);
+	__raw_writel(reg, S3C_VA_SYS + 0x0210);
+#endif
+
+	return;
+}
+#endif
+#endif
+
+#if defined(CONFIG_FB_S5P_WA101S)
+int s3cfb_backlight_on(struct platform_device *pdev)
+{
+#if !defined(CONFIG_BACKLIGHT_PWM)
+	int err;
+
+	err = gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_HIGH, "GPD0");
+	if (err) {
+		printk(KERN_ERR "failed to request GPD0 for "
+			"lcd backlight control\n");
+		return err;
+	}
+	gpio_free(EXYNOS4_GPD0(1));
+#endif
+	return 0;
+}
+
+int s3cfb_backlight_off(struct platform_device *pdev)
+{
+#if !defined(CONFIG_BACKLIGHT_PWM)
+	int err;
+
+	err = gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_LOW, "GPD0");
+	if (err) {
+		printk(KERN_ERR "failed to request GPD0 for "
+			"lcd backlight control\n");
+		return err;
+	}
+	gpio_free(EXYNOS4_GPD0(1));
+#endif
+	return 0;
+}
+
+int s3cfb_lcd_on(struct platform_device *pdev)
+{
+	return 0;
+}
+
+int s3cfb_lcd_off(struct platform_device *pdev)
+{
+	return 0;
+}
+#elif defined(CONFIG_FB_S5P_LTE480WV)
+int s3cfb_backlight_on(struct platform_device *pdev)
+{
+#if !defined(CONFIG_BACKLIGHT_PWM)
+	int err;
+
+	err = gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_HIGH, "GPD0");
+	if (err) {
+		printk(KERN_ERR "failed to request GPD0 for "
+			"lcd backlight control\n");
+		return err;
+	}
+	gpio_free(EXYNOS4_GPD0(1));
+#endif
+	return 0;
+}
+
+int s3cfb_backlight_off(struct platform_device *pdev)
+{
+#if !defined(CONFIG_BACKLIGHT_PWM)
+	int err;
+
+	err = gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_LOW, "GPD0");
+	if (err) {
+		printk(KERN_ERR "failed to request GPD0 for "
+			"lcd backlight control\n");
+		return err;
+	}
+	gpio_free(EXYNOS4_GPD0(1));
+#endif
+	return 0;
+}
+
+int s3cfb_lcd_on(struct platform_device *pdev)
+{
+	int err;
+
+	err = gpio_request_one(EXYNOS4_GPX0(6), GPIOF_OUT_INIT_HIGH, "GPX0");
+	if (err) {
+		printk(KERN_ERR "failed to request GPX0 for "
+			"lcd reset control\n");
+		return err;
+	}
+	msleep(100);
+
+	gpio_set_value(EXYNOS4_GPX0(6), 0);
+	msleep(10);
+
+	gpio_set_value(EXYNOS4_GPX0(6), 1);
+	msleep(10);
+
+	gpio_free(EXYNOS4_GPX0(6));
+
+	return 0;
+}
+
+int s3cfb_lcd_off(struct platform_device *pdev)
+{
+	return 0;
+}
+#elif defined(CONFIG_FB_S5P_HT101HD1)
+int s3cfb_backlight_on(struct platform_device *pdev)
+{
+#if !defined(CONFIG_BACKLIGHT_PWM)
+	int err;
+
+	/* Backlight High */
+	err = gpio_request_one(EXYNOS4_GPD0(0), GPIOF_OUT_INIT_HIGH, "GPD0");
+	if (err) {
+		printk(KERN_ERR "failed to request GPD0 for "
+			"lcd backlight control\n");
+		return err;
+	}
+	gpio_free(EXYNOS4_GPD0(0));
+
+	/* LED_EN (SPI1_MOSI) High */
+	err = gpio_request_one(EXYNOS4_GPB(2), GPIOF_OUT_INIT_HIGH, "GPB");
+	if (err) {
+		printk(KERN_ERR "failed to request GPB for "
+			"lcd LED_EN control\n");
+		return err;
+	}
+	gpio_free(EXYNOS4_GPB(2));
+#endif
+	return 0;
+}
+
+int s3cfb_backlight_off(struct platform_device *pdev)
+{
+#if !defined(CONFIG_BACKLIGHT_PWM)
+	int err;
+
+	/* Backlight Low */
+	err = gpio_request_one(EXYNOS4_GPD0(0), GPIOF_OUT_INIT_LOW, "GPD0");
+	if (err) {
+		printk(KERN_ERR "failed to request GPD0 for "
+			"lcd backlight control\n");
+		return err;
+	}
+	gpio_free(EXYNOS4_GPD0(0));
+
+	/* LED_EN (SPI1_MOSI) Low */
+	err = gpio_request_one(EXYNOS4_GPB(2), GPIOF_OUT_INIT_LOW, "GPB");
+	if (err) {
+		printk(KERN_ERR "failed to request GPB for "
+			"lcd LED_EN control\n");
+		return err;
+	}
+	gpio_free(EXYNOS4_GPB(2));
+#endif
+	return 0;
+}
+
+int s3cfb_lcd_on(struct platform_device *pdev)
+{
+	int err;
+
+	err = gpio_request_one(EXYNOS4_GPH0(1), GPIOF_OUT_INIT_HIGH, "GPH0");
+	if (err) {
+		printk(KERN_ERR "failed to request GPH0 for "
+			"lcd reset control\n");
+		return err;
+	}
+
+	gpio_set_value(EXYNOS4_GPH0(1), 0);
+	gpio_set_value(EXYNOS4_GPH0(1), 1);
+
+	gpio_free(EXYNOS4_GPH0(1));
+
+	return 0;
+}
+
+int s3cfb_lcd_off(struct platform_device *pdev)
+{
+	return 0;
+}
+#elif defined(CONFIG_FB_S5P_AMS369FG06) || defined(CONFIG_FB_S5P_LMS501KF03)
+int s3cfb_backlight_on(struct platform_device *pdev)
+{
+#if !defined(CONFIG_BACKLIGHT_PWM)
+	int err;
+
+	err = gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_HIGH, "GPD0");
+	if (err) {
+		printk(KERN_ERR "failed to request GPD0 for "
+			"lcd backlight control\n");
+		return err;
+	}
+	gpio_free(EXYNOS4_GPD0(1));
+#endif
+	return 0;
+}
+
+int s3cfb_backlight_off(struct platform_device *pdev)
+{
+#if !defined(CONFIG_BACKLIGHT_PWM)
+	int err;
+
+	err = gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_LOW, "GPD0");
+	if (err) {
+		printk(KERN_ERR "failed to request GPD0 for "
+			"lcd backlight control\n");
+		return err;
+	}
+	gpio_free(EXYNOS4_GPD0(1));
+#endif
+	return 0;
+}
+
+int s3cfb_lcd_on(struct platform_device *pdev)
+{
+	int err;
+
+#ifdef CONFIG_MACH_SMDKC210
+	err = gpio_request_one(EXYNOS4_GPX0(6), GPIOF_OUT_INIT_HIGH, "GPX0");
+	if (err) {
+		printk(KERN_ERR "failed to request GPX0 for "
+			"lcd reset control\n");
+		return err;
+	}
+
+	gpio_set_value(EXYNOS4_GPX0(6), 0);
+	mdelay(1);
+
+	gpio_set_value(EXYNOS4_GPX0(6), 1);
+
+	gpio_free(EXYNOS4_GPX0(6));
+#elif defined(CONFIG_MACH_SMDK4X12)
+	if (samsung_board_rev_is_0_1()) {
+		err = gpio_request_one(EXYNOS4212_GPM3(6),
+				GPIOF_OUT_INIT_HIGH, "GPM3");
+		if (err) {
+			printk(KERN_ERR "failed to request GPM3 for "
+				"lcd reset control\n");
+			return err;
+		}
+
+		gpio_set_value(EXYNOS4212_GPM3(6), 0);
+		mdelay(1);
+
+		gpio_set_value(EXYNOS4212_GPM3(6), 1);
+
+		gpio_free(EXYNOS4212_GPM3(6));
+
+	} else {
+		err = gpio_request_one(EXYNOS4_GPX1(5),
+				GPIOF_OUT_INIT_HIGH, "GPX0");
+		if (err) {
+			printk(KERN_ERR "failed to request GPX0 for "
+				"lcd reset control\n");
+			return err;
+		}
+
+		gpio_set_value(EXYNOS4_GPX1(5), 0);
+		mdelay(1);
+
+		gpio_set_value(EXYNOS4_GPX1(5), 1);
+
+		gpio_free(EXYNOS4_GPX1(5));
+	}
+#endif
+
+	return 0;
+}
+
+int s3cfb_lcd_off(struct platform_device *pdev)
+{
+	return 0;
+}
+
+#elif defined(CONFIG_FB_S5P_S6C1372) && !defined(CONFIG_FB_MDNIE_PWM)
+int s3cfb_backlight_on(struct platform_device *pdev)
+{
+	gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_HIGH, "GPD0");
+	gpio_free(EXYNOS4_GPD0(1));
+	return 0;
+}
+
+int s3cfb_backlight_off(struct platform_device *pdev)
+{
+	gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_LOW, "GPD0");
+	gpio_free(EXYNOS4_GPD0(1));
+	return 0;
+}
+
+int s3cfb_lcd_on(struct platform_device *pdev)
+{
+	int err;
+
+	err = gpio_request_one(EXYNOS4_GPC0(1), GPIOF_OUT_INIT_LOW, "GPC0");
+	if (err) {
+		printk(KERN_ERR "failed to request GPC0 for "
+			"lcd backlight control\n");
+		return err;
+	}
+
+	gpio_set_value(EXYNOS4_GPC0(1), GPIO_LEVEL_HIGH);
+	msleep(40);
+
+	/*  LVDS_N_SHDN to low */
+	err = gpio_request_one(EXYNOS4212_GPM0(5), GPIOF_OUT_INIT_LOW, "GPM0");
+	if (err) {
+		printk(KERN_ERR "failed to request GPM0 for "
+			"lcd backlight control\n");
+		return err;
+	}
+
+	gpio_set_value(EXYNOS4212_GPM0(5), GPIO_LEVEL_HIGH);
+	msleep(300);
+
+	err = gpio_request_one(EXYNOS4212_GPM0(1), GPIOF_OUT_INIT_LOW, "GPM0");
+	if (err) {
+		printk(KERN_ERR "failed to request GPM0 for "
+			"lcd backlight control\n");
+		return err;
+	}
+
+	gpio_set_value(EXYNOS4212_GPM0(1), GPIO_LEVEL_HIGH);
+	mdelay(2);
+	return 0;
+}
+
+int s3cfb_lcd_off(struct platform_device *pdev)
+{
+	gpio_set_value(EXYNOS4212_GPM0(1), GPIO_LEVEL_LOW);
+	mdelay(200);
+
+	/*  LVDS_N_SHDN to low */
+	gpio_set_value(EXYNOS4212_GPM0(5), GPIO_LEVEL_LOW);
+	msleep(40);
+
+	gpio_set_value(EXYNOS4_GPC0(1), GPIO_LEVEL_LOW);
+	msleep(400);
+
+	return 0;
+}
+
+#elif defined(CONFIG_FB_S5P_S6C1372) || defined(CONFIG_FB_S5P_S6F1202A)
+int s3cfb_backlight_on(struct platform_device *pdev)
+{
+	return 0;
+}
+
+int s3cfb_backlight_off(struct platform_device *pdev)
+{
+	return 0;
+}
+
+int s3cfb_lcd_on(struct platform_device *pdev)
+{
+#if !defined(CONFIG_FB_MDNIE_PWM)
+	int err;
+
+	err = gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_HIGH, "GPD0");
+	if (err) {
+		printk(KERN_ERR "failed to request GPD0 for lcd reset control\n");
+		return err;
+	}
+	gpio_set_value(GPIO_LCD_EN, GPIO_LEVEL_HIGH);
+	msleep(40);
+	/* LVDS_N_SHDN to high*/
+	gpio_set_value(GPIO_LVDS_NSHDN, GPIO_LEVEL_HIGH);
+	msleep(300);
+#if defined(CONFIG_FB_S5P_S6C1372)
+	gpio_set_value(GPIO_LED_BACKLIGHT_RESET, GPIO_LEVEL_HIGH);
+	mdelay(2);
+#else
+	gpio_set_value(GPIO_LCD_LDO_EN, GPIO_LEVEL_HIGH);
+	msleep(200);
+#endif
+	gpio_set_value(EXYNOS4_GPD0(1), GPIO_LEVEL_HIGH);
+	gpio_free(EXYNOS4_GPD0(1));
+#endif
+	return 0;
+}
+
+int s3cfb_lcd_off(struct platform_device *pdev)
+{
+#if !defined(CONFIG_FB_MDNIE_PWM)
+	int err;
+
+	err = gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_LOW, "GPD0");
+	if (err) {
+		printk(KERN_ERR "failed to request GPD0 for "
+			"lcd reset control\n");
+		return err;
+	}
+
+	/* LVDS_nSHDN low*/
+	gpio_set_value(EXYNOS4_GPD0(1), GPIO_LEVEL_LOW);
+	gpio_free(EXYNOS4_GPD0(1));
+#if defined(CONFIG_FB_S5P_S6C1372)
+	gpio_set_value(GPIO_LED_BACKLIGHT_RESET, GPIO_LEVEL_LOW);
+	msleep(200);
+#else
+	gpio_set_value(GPIO_LCD_LDO_EN, GPIO_LEVEL_LOW);
+	msleep(200);
+#endif
+	/* LVDS_nSHDN low*/
+	gpio_set_value(GPIO_LVDS_NSHDN, GPIO_LEVEL_LOW);
+	msleep(40);
+	/* Disable LVDS Panel Power, 1.2, 1.8, display 3.3V */
+	gpio_set_value(GPIO_LCD_EN, GPIO_LEVEL_LOW);
+	msleep(400);
+#endif
+	return 0;
+}
+
+#else
+int s3cfb_backlight_on(struct platform_device *pdev)
+{
+	return 0;
+}
+
+int s3cfb_backlight_off(struct platform_device *pdev)
+{
+	return 0;
+}
+
+int s3cfb_lcd_on(struct platform_device *pdev)
+{
+	return 0;
+}
+
+int s3cfb_lcd_off(struct platform_device *pdev)
+{
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_FB_S5P_MIPI_DSIM
+int s3cfb_mipi_clk_enable(int enable)
+{
+	struct clk *dsim_clk = NULL;
+
+	dsim_clk = clk_get(NULL, "dsim0");
+	if (IS_ERR(dsim_clk)) {
+		printk(KERN_ERR "failed to get ip clk for dsim0\n");
+		goto err_clk0;
+	}
+
+	if (enable)
+		clk_enable(dsim_clk);
+	else
+		clk_disable(dsim_clk);
+
+	clk_put(dsim_clk);
+
+	return 0;
+
+err_clk0:
+	clk_put(dsim_clk);
+
+	return -EINVAL;
+}
+#endif
+
+int s3cfb_mdnie_clk_on(u32 rate)
+{
+	struct clk *sclk = NULL;
+	struct clk *mout_mpll = NULL;
+	struct clk *mdnie_clk = NULL;
+	int ret = 0;
+
+	mdnie_clk = clk_get(NULL, "mdnie0"); /*   CLOCK GATE IP ENABLE */
+	if (IS_ERR(mdnie_clk)) {
+		printk(KERN_ERR "failed to get ip clk for mdnie0\n");
+		goto err_clk0;
+	}
+	clk_enable(mdnie_clk);
+	clk_put(mdnie_clk);
+
+	sclk = clk_get(NULL, "sclk_mdnie");
+	if (IS_ERR(sclk)) {
+		printk(KERN_ERR "failed to get sclk for mdnie\n");
+		goto err_clk1;
+	}
+
+	if (soc_is_exynos4210())
+		mout_mpll = clk_get(NULL, "mout_mpll");
+	else
+		mout_mpll = clk_get(NULL, "mout_mpll_user");
+
+	if (IS_ERR(mout_mpll)) {
+		printk(KERN_ERR "failed to get mout_mpll\n");
+		goto err_clk2;
+	}
+
+	clk_set_parent(sclk, mout_mpll);
+
+	if (!rate)
+		rate = 800 * MHZ;
+
+	ret = clk_set_rate(sclk, rate);
+
+	clk_put(mout_mpll);
+
+	clk_enable(sclk);
+
+	return 0;
+
+err_clk1:
+	clk_put(mout_mpll);
+err_clk2:
+	clk_put(sclk);
+err_clk0:
+	clk_put(mdnie_clk);
+
+	return -EINVAL;
+}
+
+int s3cfb_mdnie_pwm_clk_on(void)
+{
+	struct clk *sclk = NULL;
+	struct clk *sclk_pre = NULL;
+	struct clk *mout_mpll = NULL;
+	u32 rate = 0;
+
+	sclk = clk_get(NULL, "sclk_mdnie_pwm");
+	if (IS_ERR(sclk)) {
+		printk(KERN_ERR "failed to get sclk for mdnie_pwm\n");
+		goto err_clk1;
+	}
+
+	sclk_pre = clk_get(NULL, "sclk_mdnie_pwm_pre");
+	if (IS_ERR(sclk_pre)) {
+		printk(KERN_ERR "failed to get sclk for mdnie_pwm_pre\n");
+		goto err_clk2;
+	}
+#if defined(CONFIG_FB_S5P_S6C1372)
+	mout_mpll = clk_get(NULL, "xusbxti");
+	if (IS_ERR(mout_mpll)) {
+		printk(KERN_ERR "failed to get mout_mpll\n");
+		goto err_clk3;
+	}
+	clk_set_parent(sclk, mout_mpll);
+	rate = clk_round_rate(sclk, 2200000);
+	if (!rate)
+		rate = 2200000;
+	clk_set_rate(sclk, rate);
+	printk(KERN_INFO "set mdnie_pwm sclk rate to %d\n", rate);
+	clk_set_parent(sclk_pre, mout_mpll);
+	rate = clk_round_rate(sclk_pre, 24000000);
+	if (!rate)
+		rate = 24000000;
+	clk_set_rate(sclk_pre, rate);
+#elif defined(CONFIG_FB_S5P_S6F1202A)
+	if (soc_is_exynos4210())
+		mout_mpll = clk_get(NULL, "mout_mpll");
+	else
+		mout_mpll = clk_get(NULL, "mout_mpll_user");
+	if (IS_ERR(mout_mpll)) {
+		printk(KERN_ERR "failed to get mout_mpll\n");
+		goto err_clk3;
+	}
+	clk_set_parent(sclk, mout_mpll);
+	rate = clk_round_rate(sclk, 50000000);
+	if (!rate)
+		rate = 50000000;
+	clk_set_rate(sclk, rate);
+	printk(KERN_INFO "set mdnie_pwm sclk rate to %d\n", rate);
+	clk_set_parent(sclk_pre, mout_mpll);
+	rate = clk_round_rate(sclk_pre, 160000000);
+	if (!rate)
+		rate = 160000000;
+	clk_set_rate(sclk_pre, rate);
+#else
+	if (soc_is_exynos4210())
+		mout_mpll = clk_get(NULL, "mout_mpll");
+	else
+		mout_mpll = clk_get(NULL, "mout_mpll_user");
+
+	if (IS_ERR(mout_mpll)) {
+		printk(KERN_ERR "failed to get mout_mpll\n");
+		goto err_clk3;
+	}
+
+	clk_set_parent(sclk, mout_mpll);
+
+	rate = 57500000;
+	clk_set_rate(sclk, rate);
+#endif
+	printk(KERN_INFO "set mdnie_pwm sclk rate to %d\n", rate);
+
+	clk_put(mout_mpll);
+
+	clk_enable(sclk);
+
+	return 0;
+
+err_clk3:
+	clk_put(mout_mpll);
+err_clk2:
+	clk_put(sclk_pre);
+err_clk1:
+	clk_put(sclk);
+
+	return -EINVAL;
+}
+
+unsigned int get_clk_rate(struct platform_device *pdev, struct clk *sclk)
+{
+	struct s3c_platform_fb *pdata = pdev->dev.platform_data;
+	struct s3cfb_lcd *lcd = (struct s3cfb_lcd *)pdata->lcd;
+	struct s3cfb_lcd_timing *timing = &lcd->timing;
+	u32 src_clk, vclk, div, rate;
+#if defined(CONFIG_MACH_MIDAS) && defined(CONFIG_FB_S5P_S6E8AA0)
+	u32 vclk_limit, div_limit, fimd_div;
+#endif
+
+	src_clk = clk_get_rate(sclk);
+
+	vclk = (lcd->freq *
+		(timing->h_bp + timing->h_fp + timing->h_sw + lcd->width) *
+		(timing->v_bp + timing->v_fp + timing->v_sw + lcd->height));
+
+	if (!vclk)
+		vclk = src_clk;
+
+	div = DIV_ROUND_CLOSEST(src_clk, vclk);
+
+#if defined(CONFIG_MACH_MIDAS) && defined(CONFIG_FB_S5P_S6E8AA0)
+	vclk_limit = (40 *
+		(timing->h_bp + timing->h_fp + timing->h_sw + lcd->width) *
+		(timing->v_bp + timing->v_fp + timing->v_sw + lcd->height));
+
+	div_limit = DIV_ROUND_CLOSEST(src_clk, vclk_limit);
+
+	fimd_div = gcd(div, div_limit);
+
+	div /= fimd_div;
+#endif
+
+	if (!div) {
+		dev_err(&pdev->dev, "div(%d) should be non-zero\n", div);
+		div = 1;
+	} else if (div > 16) {
+		dev_err(&pdev->dev, "div(%d) max should be 16\n", div);
+		div = 16;
+	}
+
+	rate = src_clk / div;
+
+	if ((src_clk % rate) && (div != 1)) {
+		div--;
+		rate = src_clk / div;
+		if (!(src_clk % rate))
+			rate--;
+	}
+
+	dev_info(&pdev->dev, "vclk=%d, div=%d(%d), rate=%d\n",
+		vclk, DIV_ROUND_CLOSEST(src_clk, vclk), div, rate);
+
+	return rate;
+}
+
+int s3cfb_clk_on(struct platform_device *pdev, struct clk **s3cfb_clk)
+{
+	struct clk *sclk = NULL;
+	struct clk *mout_mpll = NULL;
+	struct clk *lcd_clk = NULL;
+	struct clksrc_clk *src_clk = NULL;
+	u32 clkdiv = 0;
+	struct s3c_platform_fb *pdata = pdev->dev.platform_data;
+	struct s3cfb_lcd *lcd = (struct s3cfb_lcd *)pdata->lcd;
+
+	u32 rate = 0;
+	int ret = 0;
+
+	lcd_clk = clk_get(&pdev->dev, "lcd");
+	if (IS_ERR(lcd_clk)) {
+		dev_err(&pdev->dev, "failed to get operation clk for fimd\n");
+		goto err_clk0;
+	}
+
+	ret = clk_enable(lcd_clk);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "failed to clk_enable of lcd clk for fimd\n");
+		goto err_clk0;
+	}
+	clk_put(lcd_clk);
+
+	sclk = clk_get(&pdev->dev, "sclk_fimd");
+	if (IS_ERR(sclk)) {
+		dev_err(&pdev->dev, "failed to get sclk for fimd\n");
+		goto err_clk1;
+	}
+
+	if (soc_is_exynos4210())
+		mout_mpll = clk_get(&pdev->dev, "mout_mpll");
+	else
+		mout_mpll = clk_get(&pdev->dev, "mout_mpll_user");
+
+	if (IS_ERR(mout_mpll)) {
+		dev_err(&pdev->dev, "failed to get mout_mpll for fimd\n");
+		goto err_clk2;
+	}
+
+	ret = clk_set_parent(sclk, mout_mpll);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "failed to clk_set_parent for fimd\n");
+		goto err_clk2;
+	}
+
+	if (!lcd->vclk) {
+		rate = get_clk_rate(pdev, mout_mpll);
+		if (!rate)
+			rate = 800 * MHZ;	/* MOUT PLL */
+		lcd->vclk = rate;
+	} else
+		rate = lcd->vclk;
+
+	ret = clk_set_rate(sclk, rate);
+
+	if (ret < 0) {
+		dev_err(&pdev->dev, "failed to clk_set_rate of sclk for fimd\n");
+		goto err_clk2;
+	}
+	dev_dbg(&pdev->dev, "set fimd sclk rate to %d\n", rate);
+
+	clk_put(mout_mpll);
+
+	ret = clk_enable(sclk);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "failed to clk_enable of sclk for fimd\n");
+		goto err_clk2;
+	}
+
+	*s3cfb_clk = sclk;
+
+#ifdef CONFIG_FB_S5P_MIPI_DSIM
+	s3cfb_mipi_clk_enable(1);
+#endif
+#ifdef CONFIG_FB_S5P_MDNIE
+	s3cfb_mdnie_clk_on(rate);
+#ifdef CONFIG_FB_MDNIE_PWM
+	s3cfb_mdnie_pwm_clk_on();
+#endif
+#endif
+
+	src_clk = container_of(sclk, struct clksrc_clk, clk);
+	clkdiv = __raw_readl(src_clk->reg_div.reg);
+
+	dev_info(&pdev->dev, "fimd sclk rate %ld, clkdiv 0x%x\n",
+		clk_get_rate(sclk), clkdiv);
+
+	return 0;
+
+err_clk2:
+	clk_put(mout_mpll);
+err_clk1:
+	clk_put(sclk);
+err_clk0:
+	clk_put(lcd_clk);
+
+	return -EINVAL;
+}
+
+int s3cfb_mdnie_clk_off(void)
+{
+	struct clk *sclk = NULL;
+	struct clk *mdnie_clk = NULL;
+
+	mdnie_clk = clk_get(NULL, "mdnie0"); /*   CLOCK GATE IP ENABLE */
+	if (IS_ERR(mdnie_clk)) {
+		printk(KERN_ERR "failed to get ip clk for fimd0\n");
+		goto err_clk0;
+	}
+	clk_disable(mdnie_clk);
+	clk_put(mdnie_clk);
+
+	sclk = clk_get(NULL, "sclk_mdnie");
+	if (IS_ERR(sclk))
+		printk(KERN_ERR "failed to get sclk for mdnie\n");
+
+	clk_disable(sclk);
+	clk_put(sclk);
+
+	return 0;
+
+err_clk0:
+	clk_put(mdnie_clk);
+
+	return -EINVAL;
+}
+
+int s3cfb_mdnie_pwm_clk_off(void)
+{
+	struct clk *sclk = NULL;
+
+	sclk = clk_get(NULL, "sclk_mdnie_pwm");
+	if (IS_ERR(sclk))
+		printk(KERN_ERR "failed to get sclk for mdnie_pwm\n");
+
+	clk_disable(sclk);
+	clk_put(sclk);
+
+	return 0;
+}
+
+int s3cfb_clk_off(struct platform_device *pdev, struct clk **clk)
+{
+	struct clk *lcd_clk = NULL;
+
+	lcd_clk = clk_get(&pdev->dev, "lcd");
+	if (IS_ERR(lcd_clk)) {
+		printk(KERN_ERR "failed to get ip clk for fimd0\n");
+		goto err_clk0;
+	}
+
+	clk_disable(lcd_clk);
+	clk_put(lcd_clk);
+
+	clk_disable(*clk);
+	clk_put(*clk);
+
+	*clk = NULL;
+
+#ifdef CONFIG_FB_S5P_MIPI_DSIM
+	s3cfb_mipi_clk_enable(0);
+#endif
+#ifdef CONFIG_FB_S5P_MDNIE
+	s3cfb_mdnie_clk_off();
+	s3cfb_mdnie_pwm_clk_off();
+#endif
+
+	return 0;
+
+err_clk0:
+	clk_put(lcd_clk);
+
+	return -EINVAL;
+}
+
+void s3cfb_get_clk_name(char *clk_name)
+{
+	strcpy(clk_name, "sclk_fimd");
+}
+
diff --git a/arch/arm/mach-exynos/setup-fimc-is.c b/arch/arm/mach-exynos/setup-fimc-is.c
new file mode 100644
index 0000000..d9d31fd
--- /dev/null
+++ b/arch/arm/mach-exynos/setup-fimc-is.c
@@ -0,0 +1,1111 @@
+/* linux/arch/arm/mach-exynos/setup-fimc-is.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * FIMC-IS gpio and clock configuration
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/gpio.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <plat/clock.h>
+#include <plat/gpio-cfg.h>
+#include <mach/regs-gpio.h>
+#include <plat/map-s5p.h>
+#include <plat/cpu.h>
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <media/exynos_fimc_is.h>
+
+struct platform_device; /* don't need the contents */
+
+#if defined(CONFIG_ARCH_EXYNOS4)
+/*------------------------------------------------------*/
+/*		Exynos4 series - FIMC-IS		*/
+/*------------------------------------------------------*/
+void exynos_fimc_is_cfg_gpio(struct platform_device *pdev)
+{
+	int ret;
+
+#if defined(CONFIG_MACH_SMDK4X12)
+	/* 1. UART setting for FIMC-IS */
+	/* GPM3[5] : TXD_UART_ISP */
+	ret = gpio_request(EXYNOS4212_GPM3(5), "GPM3");
+	if (ret)
+		printk(KERN_ERR "#### failed to request GPM3_5 ####\n");
+	s3c_gpio_cfgpin(EXYNOS4212_GPM3(5), (0x3<<20));
+	s3c_gpio_setpull(EXYNOS4212_GPM3(5), S3C_GPIO_PULL_NONE);
+	gpio_free(EXYNOS4212_GPM3(5));
+
+	/* GPM3[7] : RXD_UART_ISP */
+	ret = gpio_request(EXYNOS4212_GPM3(7), "GPM3");
+	if (ret)
+		printk(KERN_ERR "#### failed to request GPM3_7 ####\n");
+	s3c_gpio_cfgpin(EXYNOS4212_GPM3(7), (0x3<<28));
+	s3c_gpio_setpull(EXYNOS4212_GPM3(7), S3C_GPIO_PULL_NONE);
+	gpio_free(EXYNOS4212_GPM3(7));
+
+	/* 2. GPIO setting for FIMC-IS */
+	ret = gpio_request(EXYNOS4212_GPM4(0), "GPM4");
+	if (ret)
+		printk(KERN_ERR "#### failed to request GPM4_0 ####\n");
+	s3c_gpio_cfgpin(EXYNOS4212_GPM4(0), (0x2<<0));
+	s3c_gpio_setpull(EXYNOS4212_GPM4(0), S3C_GPIO_PULL_NONE);
+	gpio_free(EXYNOS4212_GPM4(0));
+
+	ret = gpio_request(EXYNOS4212_GPM4(1), "GPM4");
+	if (ret)
+		printk(KERN_ERR "#### failed to request GPM4_1 ####\n");
+	s3c_gpio_cfgpin(EXYNOS4212_GPM4(1), (0x2<<4));
+	s3c_gpio_setpull(EXYNOS4212_GPM4(1), S3C_GPIO_PULL_NONE);
+	gpio_free(EXYNOS4212_GPM4(1));
+#endif
+
+	ret = gpio_request(EXYNOS4212_GPM4(2), "GPM4");
+	if (ret)
+		printk(KERN_ERR "#### failed to request GPM4_2 ####\n");
+	s3c_gpio_cfgpin(EXYNOS4212_GPM4(2), (0x2<<8));
+	s3c_gpio_setpull(EXYNOS4212_GPM4(2), S3C_GPIO_PULL_NONE);
+	gpio_free(EXYNOS4212_GPM4(2));
+
+	ret = gpio_request(EXYNOS4212_GPM4(3), "GPM4");
+	if (ret)
+		printk(KERN_ERR "#### failed to request GPM4_3 ####\n");
+	s3c_gpio_cfgpin(EXYNOS4212_GPM4(3), (0x2<<12));
+	s3c_gpio_setpull(EXYNOS4212_GPM4(3), S3C_GPIO_PULL_NONE);
+	gpio_free(EXYNOS4212_GPM4(3));
+}
+
+int exynos_fimc_is_clk_get(struct platform_device *pdev)
+{
+	struct exynos4_platform_fimc_is *pdata;
+	pdata = to_fimc_is_plat(&pdev->dev);
+
+	/* 1. Get clocks for CMU_ISP clock divider setting */
+	/* UART_ISP_SEL - CLK_SRC_ISP (0x1003 C238) , [15:12] */
+	pdata->div_clock[0] = clk_get(&pdev->dev, "mout_mpll_user");
+	if (IS_ERR(pdata->div_clock[0])) {
+		printk(KERN_ERR "failed to get mout_mpll_user\n");
+		goto err_clk1;
+	}
+	/* UART_ISP_RATIO - CLK_DIV_ISP (0x1003 C538) , [31:28] */
+	pdata->div_clock[1] = clk_get(&pdev->dev, "sclk_uart_isp");
+	if (IS_ERR(pdata->div_clock[1])) {
+		printk(KERN_ERR "failed to get sclk_uart_isp\n");
+		goto err_clk2;
+	}
+
+	/* 2. Get clocks for CMU_ISP clock gate setting */
+	/* CLK_MTCADC_ISP - CLK_GATE_IP_ISP0 (0x1004 8800), [27] */
+	pdata->control_clock[0] = clk_get(&pdev->dev, "mtcadc");
+	if (IS_ERR(pdata->control_clock[0])) {
+		printk(KERN_ERR "failed to get mtcadc\n");
+		goto err_clk3;
+	}
+	/* CLK_MPWM_ISP - CLK_GATE_IP_ISP0 (0x1004 8800), [24] */
+	pdata->control_clock[1] = clk_get(&pdev->dev, "mpwm_isp");
+	if (IS_ERR(pdata->control_clock[1])) {
+		printk(KERN_ERR "failed to get mpwm_isp\n");
+		goto err_clk4;
+	}
+	/* CLK_PPMUISPX  - CLK_GATE_IP_ISP0 (0x1004 8800), [21] */
+	/* CLK_PPMUISPMX - CLK_GATE_IP_ISP0 (0x1004 8800), [20] */
+	pdata->control_clock[2] = clk_get(&pdev->dev, "ppmuisp");
+	if (IS_ERR(pdata->control_clock[2])) {
+		printk(KERN_ERR "failed to get ppmuisp\n");
+		goto err_clk5;
+	}
+	/* CLK_QE_LITE1 - CLK_GATE_IP_ISP0 (0x1004 8800), [18] */
+	pdata->control_clock[3] = clk_get(&pdev->dev, "qelite1");
+	if (IS_ERR(pdata->control_clock[3])) {
+		printk(KERN_ERR "failed to get qelite1\n");
+		goto err_clk6;
+	}
+	/* CLK_QE_LITE0 - CLK_GATE_IP_ISP0 (0x1004 8800), [17] */
+	pdata->control_clock[4] = clk_get(&pdev->dev, "qelite0");
+	if (IS_ERR(pdata->control_clock[4])) {
+		printk(KERN_ERR "failed to get qelite0\n");
+		goto err_clk7;
+	}
+	/* CLK_QE_FD - CLK_GATE_IP_ISP0 (0x1004 8800), [16] */
+	pdata->control_clock[5] = clk_get(&pdev->dev, "qefd");
+	if (IS_ERR(pdata->control_clock[5])) {
+		printk(KERN_ERR "failed to get qefd\n");
+		goto err_clk8;
+	}
+	/* CLK_QE_DRC - CLK_GATE_IP_ISP0 (0x1004 8800), [15] */
+	pdata->control_clock[6] = clk_get(&pdev->dev, "qedrc");
+	if (IS_ERR(pdata->control_clock[6])) {
+		printk(KERN_ERR "failed to get qedrc\n");
+		goto err_clk9;
+	}
+	/* CLK_QE_ISP - CLK_GATE_IP_ISP0 (0x1004 8800), [14] */
+	pdata->control_clock[7] = clk_get(&pdev->dev, "qeisp");
+	if (IS_ERR(pdata->control_clock[7])) {
+		printk(KERN_ERR "failed to get qeisp\n");
+		goto err_clk10;
+	}
+	/* CLK_SMMU_LITE1 - CLK_GATE_IP_ISP0 (0x1004 8800), [12] */
+	pdata->control_clock[8] = clk_get(&pdev->dev, "sysmmu_lite1");
+	if (IS_ERR(pdata->control_clock[8])) {
+		printk(KERN_ERR "failed to get sysmmu_lite1\n");
+		goto err_clk11;
+	}
+	/* CLK_SMMU_LITE0 - CLK_GATE_IP_ISP0 (0x1004 8800), [11] */
+	pdata->control_clock[9] = clk_get(&pdev->dev, "sysmmu_lite0");
+	if (IS_ERR(pdata->control_clock[9])) {
+		printk(KERN_ERR "failed to get sysmmu_lite0\n");
+		goto err_clk12;
+	}
+	/* CLK_SPI1_ISP - CLK_GATE_IP_ISP0 (0x1004 8804), [13] */
+	pdata->control_clock[10] = clk_get(&pdev->dev, "spi1_isp");
+	if (IS_ERR(pdata->control_clock[10])) {
+		printk(KERN_ERR "failed to get spi1_isp\n");
+		goto err_clk13;
+	}
+	/* CLK_SPI0_ISP - CLK_GATE_IP_ISP0 (0x1004 8804), [12] */
+	pdata->control_clock[11] = clk_get(&pdev->dev, "spi0_isp");
+	if (IS_ERR(pdata->control_clock[11])) {
+		printk(KERN_ERR "failed to get spi0_isp\n");
+		goto err_clk14;
+	}
+	/* CLK_SMMU_FD - CLK_GATE_IP_ISP0 (0x1004 8800), [10] */
+	pdata->control_clock[12] = clk_get(&pdev->dev, "sysmmu_fd");
+	if (IS_ERR(pdata->control_clock[12])) {
+		printk(KERN_ERR "failed to get sysmmu_fd\n");
+		goto err_clk15;
+	}
+	/* CLK_SMMU_DRC - CLK_GATE_IP_ISP0 (0x1004 8800), [9] */
+	pdata->control_clock[13] = clk_get(&pdev->dev, "sysmmu_drc");
+	if (IS_ERR(pdata->control_clock[13])) {
+		printk(KERN_ERR "failed to get sysmmu_drc\n");
+		goto err_clk16;
+	}
+	/* CLK_SMMU_ISP - CLK_GATE_IP_ISP0 (0x1004 8800), [8] */
+	pdata->control_clock[14] = clk_get(&pdev->dev, "sysmmu_isp");
+	if (IS_ERR(pdata->control_clock[14])) {
+		printk(KERN_ERR "failed to get sysmmu_isp\n");
+		goto err_clk17;
+	}
+	/* CLK_SMMU_ISPCX - CLK_GATE_IP_ISP0 (0x1004 8804), [4] */
+	pdata->control_clock[15] = clk_get(&pdev->dev, "sysmmu_ispcx");
+	if (IS_ERR(pdata->control_clock[15])) {
+		printk(KERN_ERR "failed to get sysmmu_ispcx\n");
+		goto err_clk18;
+	}
+	return 0;
+
+err_clk18:
+	clk_put(pdata->control_clock[14]);
+err_clk17:
+	clk_put(pdata->control_clock[13]);
+err_clk16:
+	clk_put(pdata->control_clock[12]);
+err_clk15:
+	clk_put(pdata->control_clock[11]);
+err_clk14:
+	clk_put(pdata->control_clock[10]);
+err_clk13:
+	clk_put(pdata->control_clock[9]);
+err_clk12:
+	clk_put(pdata->control_clock[8]);
+err_clk11:
+	clk_put(pdata->control_clock[7]);
+err_clk10:
+	clk_put(pdata->control_clock[6]);
+err_clk9:
+	clk_put(pdata->control_clock[5]);
+err_clk8:
+	clk_put(pdata->control_clock[4]);
+err_clk7:
+	clk_put(pdata->control_clock[3]);
+err_clk6:
+	clk_put(pdata->control_clock[2]);
+err_clk5:
+	clk_put(pdata->control_clock[1]);
+err_clk4:
+	clk_put(pdata->control_clock[0]);
+err_clk3:
+	clk_put(pdata->div_clock[1]);
+err_clk2:
+	clk_put(pdata->div_clock[0]);
+err_clk1:
+	return -EINVAL;
+}
+
+int exynos_fimc_is_cfg_clk(struct platform_device *pdev)
+{
+	struct exynos4_platform_fimc_is *pdata;
+	unsigned int tmp;
+	pdata = to_fimc_is_plat(&pdev->dev);
+
+	/* 1. MCUISP */
+	__raw_writel(0x00000011, EXYNOS4_CLKDIV_ISP0);
+	/* 2. ACLK_ISP */
+	__raw_writel(0x00000030, EXYNOS4_CLKDIV_ISP1);
+	/* 3. Set mux - CLK_SRC_TOP1(0x1003 C214) [24],[20]*/
+	tmp = __raw_readl(EXYNOS4_CLKSRC_TOP1);
+	tmp |= (0x1 << EXYNOS4_CLKDIV_TOP1_ACLK200_SUB_SHIFT |
+		0x1 << EXYNOS4_CLKDIV_TOP1_ACLK400_MCUISP_SUB_SHIFT);
+	__raw_writel(tmp, EXYNOS4_CLKSRC_TOP1);
+
+	/* 4. UART-ISP */
+	clk_set_parent(pdata->div_clock[UART_ISP_RATIO],
+					pdata->div_clock[UART_ISP_SEL]);
+	clk_set_rate(pdata->div_clock[UART_ISP_RATIO], 50 * 1000000);
+
+	return 0;
+}
+
+int exynos_fimc_is_clk_on(struct platform_device *pdev)
+{
+	struct exynos4_platform_fimc_is *pdata;
+	int i;
+	pdata = to_fimc_is_plat(&pdev->dev);
+
+	/* 1. CLK_GATE_IP_ISP (0x1003 C938)*/
+#if defined(CONFIG_MACH_SMDK4X12)
+	clk_enable(pdata->div_clock[UART_ISP_RATIO]);
+#endif
+	/* 2. CLK_GATE_IP_ISP0, CLK_GATE_IP_ISP1 (0x1004 8800) (0x1004 8804)*/
+	for (i = 0; i < (EXYNOS4_FIMC_IS_MAX_CONTROL_CLOCKS - 4); i++)
+		clk_enable(pdata->control_clock[i]);
+#if defined(CONFIG_VIDEOBUF2_CMA_PHYS)
+	/* In case of CMA, clocks related system MMU off */
+	clk_enable(pdata->control_clock[EXYNOS4_FIMC_IS_MAX_CONTROL_CLOCKS-4]);
+	clk_enable(pdata->control_clock[EXYNOS4_FIMC_IS_MAX_CONTROL_CLOCKS-3]);
+	clk_enable(pdata->control_clock[EXYNOS4_FIMC_IS_MAX_CONTROL_CLOCKS-2]);
+	clk_enable(pdata->control_clock[EXYNOS4_FIMC_IS_MAX_CONTROL_CLOCKS-1]);
+#endif
+	for (i = 0; i < (EXYNOS4_FIMC_IS_MAX_CONTROL_CLOCKS - 4); i++)
+		clk_disable(pdata->control_clock[i]);
+#if defined(CONFIG_VIDEOBUF2_CMA_PHYS)
+	/* In case of CMA, clocks related system MMU off */
+	clk_disable(pdata->control_clock[EXYNOS4_FIMC_IS_MAX_CONTROL_CLOCKS-4]);
+	clk_disable(pdata->control_clock[EXYNOS4_FIMC_IS_MAX_CONTROL_CLOCKS-3]);
+	clk_disable(pdata->control_clock[EXYNOS4_FIMC_IS_MAX_CONTROL_CLOCKS-2]);
+	clk_disable(pdata->control_clock[EXYNOS4_FIMC_IS_MAX_CONTROL_CLOCKS-1]);
+#endif
+	return 0;
+}
+
+int exynos_fimc_is_clk_off(struct platform_device *pdev)
+{
+	struct exynos4_platform_fimc_is *pdata;
+	pdata = to_fimc_is_plat(&pdev->dev);
+
+	/* 1. CLK_GATE_IP_ISP (0x1003 C938)*/
+#if defined(CONFIG_MACH_SMDK4X12)
+	clk_disable(pdata->div_clock[UART_ISP_RATIO]);
+#endif
+
+	return 0;
+}
+
+int exynos_fimc_is_clk_put(struct platform_device *pdev)
+{
+	struct exynos4_platform_fimc_is *pdata;
+	int i;
+	pdata = to_fimc_is_plat(&pdev->dev);
+
+	for (i = 0; i < EXYNOS4_FIMC_IS_MAX_DIV_CLOCKS; i++)
+		clk_put(pdata->div_clock[i]);
+	for (i = 0; i < EXYNOS4_FIMC_IS_MAX_CONTROL_CLOCKS; i++)
+		clk_put(pdata->control_clock[i]);
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_ARCH_EXYNOS5)
+/*------------------------------------------------------*/
+/*		Exynos5 series - FIMC-IS		*/
+/*------------------------------------------------------*/
+void exynos5_fimc_is_cfg_gpio(struct platform_device *pdev)
+{
+	int ret;
+
+	/* 1. UART setting for FIMC-IS */
+#if defined(CONFIG_MACH_P10)
+	ret = gpio_request(GPIO_5M_nRST, "GPIO_5M_nRST");
+	if (ret)
+		printk(KERN_ERR "#### failed to request GPIO_5M_nRST ####\n");
+	s3c_gpio_cfgpin(GPIO_5M_nRST, (0x2<<0));
+	s3c_gpio_setpull(GPIO_5M_nRST, S3C_GPIO_PULL_NONE);
+	gpio_free(GPIO_5M_nRST);
+#else
+	ret = gpio_request(EXYNOS5_GPE0(0), "GPE0");
+	if (ret)
+		printk(KERN_ERR "#### failed to request GPE0_0 ####\n");
+	s3c_gpio_cfgpin(EXYNOS5_GPE0(0), (0x2<<0));
+	s3c_gpio_setpull(EXYNOS5_GPE0(0), S3C_GPIO_PULL_NONE);
+	gpio_free(EXYNOS5_GPE0(0));
+#endif
+
+#if defined(CONFIG_MACH_P10)
+#else
+	ret = gpio_request(EXYNOS5_GPE0(1), "GPE0");
+	if (ret)
+		printk(KERN_ERR "#### failed to request GPE0_1 ####\n");
+	s3c_gpio_cfgpin(EXYNOS5_GPE0(1), (0x2<<4));
+	s3c_gpio_setpull(EXYNOS5_GPE0(1), S3C_GPIO_PULL_NONE);
+	gpio_free(EXYNOS5_GPE0(1));
+
+	ret = gpio_request(EXYNOS5_GPE0(2), "GPE0");
+	if (ret)
+		printk(KERN_ERR "#### failed to request GPE0_2 ####\n");
+	s3c_gpio_cfgpin(EXYNOS5_GPE0(2), (0x3<<8));
+	s3c_gpio_setpull(EXYNOS5_GPE0(2), S3C_GPIO_PULL_NONE);
+	gpio_free(EXYNOS5_GPE0(2));
+
+	ret = gpio_request(EXYNOS5_GPE0(3), "GPE0");
+	if (ret)
+		printk(KERN_ERR "#### failed to request GPE0_3 ####\n");
+	s3c_gpio_cfgpin(EXYNOS5_GPE0(3), (0x3<<12));
+	s3c_gpio_setpull(EXYNOS5_GPE0(3), S3C_GPIO_PULL_NONE);
+	gpio_free(EXYNOS5_GPE0(3));
+
+	ret = gpio_request(EXYNOS5_GPE0(4), "GPE0");
+	if (ret)
+		printk(KERN_ERR "#### failed to request GPE0_4 ####\n");
+	s3c_gpio_cfgpin(EXYNOS5_GPE0(4), (0x3<<16));
+	s3c_gpio_setpull(EXYNOS5_GPE0(4), S3C_GPIO_PULL_NONE);
+	gpio_free(EXYNOS5_GPE0(4));
+
+	ret = gpio_request(EXYNOS5_GPE0(5), "GPE0");
+	if (ret)
+		printk(KERN_ERR "#### failed to request GPE0_5 ####\n");
+	s3c_gpio_cfgpin(EXYNOS5_GPE0(5), (0x3<<20));
+	s3c_gpio_setpull(EXYNOS5_GPE0(5), S3C_GPIO_PULL_NONE);
+	gpio_free(EXYNOS5_GPE0(5));
+
+	ret = gpio_request(EXYNOS5_GPE0(6), "GPE0");
+	if (ret)
+		printk(KERN_ERR "#### failed to request GPE0_6 ####\n");
+	s3c_gpio_cfgpin(EXYNOS5_GPE0(6), (0x3<<24));
+	s3c_gpio_setpull(EXYNOS5_GPE0(6), S3C_GPIO_PULL_NONE);
+	gpio_free(EXYNOS5_GPE0(6));
+#endif
+
+#if defined(CONFIG_MACH_P10)
+	ret = gpio_request(GPIO_ISP_TXD, "GPIO_ISP_TXD");
+	if (ret)
+		printk(KERN_ERR "#### failed to request GPIO_ISP_TXD ####\n");
+	s3c_gpio_cfgpin(GPIO_ISP_TXD, (0x3<<28));
+	s3c_gpio_setpull(GPIO_ISP_TXD, S3C_GPIO_PULL_NONE);
+	gpio_free(GPIO_ISP_TXD);
+#else
+	ret = gpio_request(EXYNOS5_GPE0(7), "GPE0");
+	if (ret)
+		printk(KERN_ERR "#### failed to request GPE0_7 ####\n");
+	s3c_gpio_cfgpin(EXYNOS5_GPE0(7), (0x3<<28));
+	s3c_gpio_setpull(EXYNOS5_GPE0(7), S3C_GPIO_PULL_NONE);
+	gpio_free(EXYNOS5_GPE0(7));
+#endif
+
+#if defined(CONFIG_MACH_P10)
+#else
+	ret = gpio_request(EXYNOS5_GPE1(0), "GPE1");
+	if (ret)
+		printk(KERN_ERR "#### failed to request GPE1_0 ####\n");
+	s3c_gpio_cfgpin(EXYNOS5_GPE1(0), (0x3<<0));
+	s3c_gpio_setpull(EXYNOS5_GPE1(0), S3C_GPIO_PULL_NONE);
+	gpio_free(EXYNOS5_GPE1(0));
+#endif
+
+#if defined(CONFIG_MACH_P10)
+	ret = gpio_request(GPIO_ISP_RXD, "GPIO_ISP_RXD");
+	if (ret)
+		printk(KERN_ERR "#### failed to request GPIO_ISP_RXD ####\n");
+	s3c_gpio_cfgpin(GPIO_ISP_RXD, (0x3<<4));
+	s3c_gpio_setpull(GPIO_ISP_RXD, S3C_GPIO_PULL_NONE);
+	gpio_free(GPIO_ISP_RXD);
+#else
+	ret = gpio_request(EXYNOS5_GPE1(1), "GPE1");
+	if (ret)
+		printk(KERN_ERR "#### failed to request GPE1_1 ####\n");
+	s3c_gpio_cfgpin(EXYNOS5_GPE1(1), (0x3<<4));
+	s3c_gpio_setpull(EXYNOS5_GPE1(1), S3C_GPIO_PULL_NONE);
+	gpio_free(EXYNOS5_GPE1(1));
+#endif
+
+	/* 2. GPIO setting for FIMC-IS */
+#if defined(CONFIG_MACH_P10)
+	ret = gpio_request(GPIO_5M_CAM_SDA_18V, "GPIO_5M_CAM_SDA_18V");
+	if (ret)
+		printk(KERN_ERR "#### failed to request GPIO_5M_CAM_SDA_18V ####\n");
+	s3c_gpio_cfgpin(GPIO_5M_CAM_SDA_18V, (0x2<<0));
+	s3c_gpio_setpull(GPIO_5M_CAM_SDA_18V, S3C_GPIO_PULL_NONE);
+	gpio_free(GPIO_5M_CAM_SDA_18V);
+#else
+	ret = gpio_request(EXYNOS5_GPF0(0), "GPF0");
+	if (ret)
+		printk(KERN_ERR "#### failed to request GPF0_0 ####\n");
+	s3c_gpio_cfgpin(EXYNOS5_GPF0(0), (0x2<<0));
+	s3c_gpio_setpull(EXYNOS5_GPF0(0), S3C_GPIO_PULL_NONE);
+	gpio_free(EXYNOS5_GPF0(0));
+#endif
+
+#if defined(CONFIG_MACH_P10)
+	ret = gpio_request(GPIO_5M_CAM_SCL_18V, "GPIO_5M_CAM_SCL_18V");
+	if (ret)
+		printk(KERN_ERR "#### failed to request GPIO_5M_CAM_SCL_18V ####\n");
+	s3c_gpio_cfgpin(GPIO_5M_CAM_SCL_18V, (0x2<<4));
+	s3c_gpio_setpull(GPIO_5M_CAM_SCL_18V, S3C_GPIO_PULL_NONE);
+	gpio_free(GPIO_5M_CAM_SCL_18V);
+#else
+	ret = gpio_request(EXYNOS5_GPF0(1), "GPF0");
+	if (ret)
+		printk(KERN_ERR "#### failed to request GPF0_1 ####\n");
+	s3c_gpio_cfgpin(EXYNOS5_GPF0(1), (0x2<<4));
+	s3c_gpio_setpull(EXYNOS5_GPF0(1), S3C_GPIO_PULL_NONE);
+	gpio_free(EXYNOS5_GPF0(1));
+#endif
+
+#if defined(CONFIG_MACH_P10)
+	ret = gpio_request(GPIO_VT_CAM_SDA_18V, "GPIO_VT_CAM_SDA_18V");
+	if (ret)
+		printk(KERN_ERR "#### failed to request GPIO_VT_CAM_SDA_18V ####\n");
+	s3c_gpio_cfgpin(GPIO_VT_CAM_SDA_18V, (0x2<<8));
+	s3c_gpio_setpull(GPIO_VT_CAM_SDA_18V, S3C_GPIO_PULL_NONE);
+	gpio_free(GPIO_VT_CAM_SDA_18V);
+#else
+	ret = gpio_request(EXYNOS5_GPF0(2), "GPF0");
+	if (ret)
+		printk(KERN_ERR "#### failed to request GPF0_2 ####\n");
+	s3c_gpio_cfgpin(EXYNOS5_GPF0(2), (0x2<<8));
+	s3c_gpio_setpull(EXYNOS5_GPF0(2), S3C_GPIO_PULL_NONE);
+	gpio_free(EXYNOS5_GPF0(2));
+#endif
+
+#if defined(CONFIG_MACH_P10)
+	ret = gpio_request(GPIO_VT_CAM_SCL_18V, "GPIO_VT_CAM_SCL_18V");
+	if (ret)
+		printk(KERN_ERR "#### failed to request GPIO_5M_CAM_SDA_18V ####\n");
+	s3c_gpio_cfgpin(GPIO_VT_CAM_SCL_18V, (0x2<<12));
+	s3c_gpio_setpull(GPIO_VT_CAM_SCL_18V, S3C_GPIO_PULL_NONE);
+	gpio_free(GPIO_VT_CAM_SCL_18V);
+#else
+	ret = gpio_request(EXYNOS5_GPF0(0), "GPF0");
+	if (ret)
+		printk(KERN_ERR "#### failed to request GPF0_3 ####\n");
+	s3c_gpio_cfgpin(EXYNOS5_GPF0(3), (0x2<<12));
+	s3c_gpio_setpull(EXYNOS5_GPF0(3), S3C_GPIO_PULL_NONE);
+	gpio_free(EXYNOS5_GPF0(3));
+#endif
+
+#if defined(CONFIG_MACH_P10)
+	ret = gpio_request(GPIO_CMC_CLK_18V, "GPIO_CMC_CLK_18V");
+	if (ret)
+		printk(KERN_ERR "#### failed to request GPIO_CMC_CLK_18V ####\n");
+	s3c_gpio_cfgpin(GPIO_CMC_CLK_18V, (0x3<<0));
+	s3c_gpio_setpull(GPIO_CMC_CLK_18V, S3C_GPIO_PULL_NONE);
+	gpio_free(GPIO_CMC_CLK_18V);
+#else
+	ret = gpio_request(EXYNOS5_GPF1(0), "GPF1");
+	if (ret)
+		printk(KERN_ERR "#### failed to request GPF1_0 ####\n");
+	s3c_gpio_cfgpin(EXYNOS5_GPF1(0), (0x3<<0));
+	s3c_gpio_setpull(EXYNOS5_GPF1(0), S3C_GPIO_PULL_NONE);
+	gpio_free(EXYNOS5_GPF1(0));
+#endif
+
+#if defined(CONFIG_MACH_P10)
+	ret = gpio_request(GPIO_CMC_CS_18V, "GPIO_CMC_CS_18V");
+	if (ret)
+		printk(KERN_ERR "#### failed to request GPIO_CMC_CS_18V ####\n");
+	s3c_gpio_cfgpin(GPIO_CMC_CS_18V, (0x3<<4));
+	s3c_gpio_setpull(GPIO_CMC_CS_18V, S3C_GPIO_PULL_NONE);
+	gpio_free(GPIO_CMC_CS_18V);
+#else
+	ret = gpio_request(EXYNOS5_GPF1(1), "GPF1");
+	if (ret)
+		printk(KERN_ERR "#### failed to request GPF1_0 ####\n");
+	s3c_gpio_cfgpin(EXYNOS5_GPF1(1), (0x3<<4));
+	s3c_gpio_setpull(EXYNOS5_GPF1(1), S3C_GPIO_PULL_NONE);
+	gpio_free(EXYNOS5_GPF1(1));
+#endif
+
+	/* CAM A port(b0010) : PCLK, VSYNC, HREF, CLK_OUT */
+#if defined(CONFIG_MACH_P10)
+	s3c_gpio_cfgrange_nopull(GPIO_CAM_MCLK, 1, S3C_GPIO_SFN(2));
+#else
+	s3c_gpio_cfgrange_nopull(EXYNOS5_GPH0(3), 1, S3C_GPIO_SFN(2));
+#endif
+
+#if defined(CONFIG_MACH_P10)
+	/* CAM A port : POWER */
+	s3c_gpio_cfgpin(GPIO_CAM_IO_EN, S3C_GPIO_OUTPUT);
+	s3c_gpio_setpull(GPIO_CAM_IO_EN, S3C_GPIO_PULL_NONE);
+	gpio_set_value(GPIO_CAM_IO_EN, 1);
+
+	/* CAM A reset*/
+	ret = gpio_request(GPIO_5M_nRST, "GPIO_5M_nRST");
+	if (ret)
+		printk(KERN_ERR "#### failed to request GPIO_5M_nRST ####\n");
+
+	s3c_gpio_setpull(GPIO_5M_nRST, S3C_GPIO_PULL_NONE);
+	gpio_direction_output(GPIO_5M_nRST, 0);
+	gpio_direction_output(GPIO_5M_nRST, 1);
+	gpio_free(GPIO_5M_nRST);
+#else
+	/* CAM A port(b0010) : DATA[0-7] */
+	/* s3c_gpio_cfgrange_nopull(EXYNOS5_GPH1(0), 8, S3C_GPIO_SFN(2)); */
+
+	/* Camera A reset*/
+	ret = gpio_request(EXYNOS5_GPX1(2), "GPX1");
+	if (ret)
+		printk(KERN_ERR "#### failed to request GPX1_2 ####\n");
+
+	s3c_gpio_setpull(EXYNOS5_GPX1(2), S3C_GPIO_PULL_NONE);
+	gpio_direction_output(EXYNOS5_GPX1(2), 0);
+	gpio_direction_output(EXYNOS5_GPX1(2), 1);
+	gpio_free(EXYNOS5_GPX1(2));
+#endif
+
+	/* CAM B port */
+#if defined(CONFIG_MACH_P10)
+	ret = gpio_request(GPIO_VTCAM_MCLK, "GPIO_VTCAM_MCLK");
+	if (ret)
+		printk(KERN_ERR "#### failed to request GPIO_VTCAM_MCLK ####\n");
+	s3c_gpio_cfgpin(GPIO_VTCAM_MCLK, (0x2<<4));
+	s3c_gpio_setpull(GPIO_VTCAM_MCLK, S3C_GPIO_PULL_NONE);
+	gpio_free(GPIO_VTCAM_MCLK);
+#else
+	/* CAM B port */
+	ret = gpio_request(EXYNOS5_GPG2(1), "GPG2");
+	if (ret)
+		printk(KERN_ERR "#### failed to request GPG2_1 ####\n");
+	s3c_gpio_cfgpin(EXYNOS5_GPG2(1), (0x2<<4));
+	s3c_gpio_setpull(EXYNOS5_GPG2(1), S3C_GPIO_PULL_NONE);
+	gpio_free(EXYNOS5_GPG2(1));
+#endif
+
+#if defined(CONFIG_MACH_P10)
+	ret = gpio_request(GPIO_VT_CAM_SDA_18V, "GPIO_VT_CAM_SDA_18V");
+	if (ret)
+		printk(KERN_ERR "#### failed to request GPIO_VT_CAM_SDA_18V ####\n");
+	s3c_gpio_cfgpin(GPIO_VT_CAM_SDA_18V, (0x2<<8));
+	s3c_gpio_setpull(GPIO_VT_CAM_SDA_18V, S3C_GPIO_PULL_NONE);
+	gpio_free(GPIO_VT_CAM_SDA_18V);
+#else
+
+	ret = gpio_request(EXYNOS5_GPF0(2), "GPF0");
+	if (ret)
+		printk(KERN_ERR "#### failed to request GPF0_2 ####\n");
+	s3c_gpio_cfgpin(EXYNOS5_GPF0(2), (0x2<<8));
+	s3c_gpio_setpull(EXYNOS5_GPF0(2), S3C_GPIO_PULL_NONE);
+	gpio_free(EXYNOS5_GPF0(2));
+#endif
+
+#if defined(CONFIG_MACH_P10)
+	ret = gpio_request(GPIO_VT_CAM_SCL_18V, "GPIO_VT_CAM_SCL_18V");
+	if (ret)
+		printk(KERN_ERR "#### failed to request GPIO_VT_CAM_SCL_18V ####\n");
+	s3c_gpio_cfgpin(GPIO_VT_CAM_SCL_18V, (0x2<<12));
+	s3c_gpio_setpull(GPIO_VT_CAM_SCL_18V, S3C_GPIO_PULL_NONE);
+	gpio_free(GPIO_VT_CAM_SCL_18V);
+#else
+
+	ret = gpio_request(EXYNOS5_GPF0(3), "GPF1");
+	if (ret)
+		printk(KERN_ERR "#### failed to request GPF0_3 ####\n");
+	s3c_gpio_cfgpin(EXYNOS5_GPF0(3), (0x2<<12));
+	s3c_gpio_setpull(EXYNOS5_GPF0(3), S3C_GPIO_PULL_NONE);
+	gpio_free(EXYNOS5_GPF0(3));
+#endif
+
+	/* Camera B reset*/
+#if defined(CONFIG_MACH_P10)
+	ret = gpio_request(GPIO_CAM_VT_nRST, "GPIO_CAM_VT_nRST");
+	if (ret)
+		printk(KERN_ERR "#### failed to request GPIO_CAM_VT_nRST ####\n");
+
+	s3c_gpio_setpull(GPIO_CAM_VT_nRST, S3C_GPIO_PULL_NONE);
+	gpio_direction_output(GPIO_CAM_VT_nRST, 0);
+	gpio_direction_output(GPIO_CAM_VT_nRST, 1);
+	gpio_free(GPIO_CAM_VT_nRST);
+#else
+
+	/* Camera B reset*/
+	ret = gpio_request(EXYNOS5_GPX1(0), "GPX1");
+	if (ret)
+		printk(KERN_ERR "#### failed to request GPX1_0 ####\n");
+
+	s3c_gpio_setpull(EXYNOS5_GPX1(0), S3C_GPIO_PULL_NONE);
+	gpio_direction_output(EXYNOS5_GPX1(0), 0);
+	gpio_direction_output(EXYNOS5_GPX1(0), 1);
+	gpio_free(EXYNOS5_GPX1(0));
+#endif
+
+	/* Flash */
+#if defined(CONFIG_MACH_P10)
+	ret = gpio_request(GPIO_CAM_FLASH_SET_T, "GPIO_CAM_FLASH_SET_T");
+	if (ret)
+		printk(KERN_ERR "#### failed to request GPIO_CAM_FLASH_SET_T ####\n");
+
+	s3c_gpio_setpull(GPIO_CAM_FLASH_SET_T, S3C_GPIO_PULL_NONE);
+	gpio_direction_output(GPIO_CAM_FLASH_SET_T, 0);
+	/* turn on */
+	/* gpio_direction_output(GPIO_CAM_FLASH_SET_T, 1); */
+	gpio_free(GPIO_CAM_FLASH_SET_T);
+
+	ret = gpio_request(GPIO_CAM_FLASH_EN_T, "GPIO_CAM_FLASH_EN_T");
+	if (ret)
+		printk(KERN_ERR "#### failed to request GPIO_CAM_FLASH_EN_T ####\n");
+
+	s3c_gpio_setpull(GPIO_CAM_FLASH_EN_T, S3C_GPIO_PULL_NONE);
+	gpio_direction_output(GPIO_CAM_FLASH_EN_T, 0);
+	/* turn on */
+	/* gpio_direction_output(GPIO_CAM_FLASH_EN_T, 1); */
+	gpio_free(GPIO_CAM_FLASH_EN_T);
+#endif
+
+#if defined(CONFIG_MACH_P10)
+	/* CAM A port : POWER */
+	gpio_set_value(GPIO_CAM_IO_EN, 0);
+#endif
+}
+
+int exynos5_fimc_is_cfg_clk(struct platform_device *pdev)
+{
+	struct clk *aclk_mcuisp = NULL;
+	struct clk *aclk_266 = NULL;
+	struct clk *aclk_mcuisp_div0 = NULL;
+	struct clk *aclk_mcuisp_div1 = NULL;
+	struct clk *aclk_266_div0 = NULL;
+	struct clk *aclk_266_div1 = NULL;
+	struct clk *aclk_266_mpwm = NULL;
+	struct clk *sclk_uart_isp = NULL;
+	struct clk *sclk_uart_isp_div = NULL;
+	struct clk *mout_mpll = NULL;
+	struct clk *sclk_mipi = NULL;
+	struct clk *cam_src = NULL;
+	struct clk *cam_A_clk = NULL;
+	unsigned long mcu_isp_400;
+	unsigned long isp_266;
+	unsigned long isp_uart;
+	unsigned long mipi;
+	unsigned long epll;
+
+	/*
+	 * initialize Clocks
+	*/
+
+	printk(KERN_DEBUG "exynos5_fimc_is_cfg_clk\n");
+	/* 1. MCUISP */
+	aclk_mcuisp = clk_get(&pdev->dev, "aclk_400_isp");
+	if (IS_ERR(aclk_mcuisp))
+		return PTR_ERR(aclk_mcuisp);
+
+	aclk_mcuisp_div0 = clk_get(&pdev->dev, "aclk_400_isp_div0");
+	if (IS_ERR(aclk_mcuisp_div0))
+		return PTR_ERR(aclk_mcuisp_div0);
+
+	aclk_mcuisp_div1 = clk_get(&pdev->dev, "aclk_400_isp_div1");
+	if (IS_ERR(aclk_mcuisp_div1))
+		return PTR_ERR(aclk_mcuisp_div1);
+
+	clk_set_rate(aclk_mcuisp_div0, 400 * 1000000);
+	clk_set_rate(aclk_mcuisp_div1, 400 * 1000000);
+
+	mcu_isp_400 = clk_get_rate(aclk_mcuisp);
+	printk(KERN_DEBUG "mcu_isp_400 : %ld\n", mcu_isp_400);
+
+	mcu_isp_400 = clk_get_rate(aclk_mcuisp_div0);
+	printk(KERN_DEBUG "mcu_isp_400_div0 : %ld\n", mcu_isp_400);
+
+	mcu_isp_400 = clk_get_rate(aclk_mcuisp_div1);
+	printk(KERN_DEBUG "aclk_mcuisp_div1 : %ld\n", mcu_isp_400);
+
+	clk_put(aclk_mcuisp);
+	clk_put(aclk_mcuisp_div0);
+	clk_put(aclk_mcuisp_div1);
+
+	/* 2. ACLK_ISP */
+	aclk_266 = clk_get(&pdev->dev, "aclk_266_isp");
+	if (IS_ERR(aclk_266))
+		return PTR_ERR(aclk_266);
+	aclk_266_div0 = clk_get(&pdev->dev, "aclk_266_isp_div0");
+	if (IS_ERR(aclk_266_div0))
+		return PTR_ERR(aclk_266_div0);
+	aclk_266_div1 = clk_get(&pdev->dev, "aclk_266_isp_div1");
+	if (IS_ERR(aclk_266_div1))
+		return PTR_ERR(aclk_266_div1);
+	aclk_266_mpwm = clk_get(&pdev->dev, "aclk_266_isp_divmpwm");
+	if (IS_ERR(aclk_266_mpwm))
+		return PTR_ERR(aclk_266_mpwm);
+
+	clk_set_rate(aclk_266_div0, 134 * 1000000);
+	clk_set_rate(aclk_266_div1, 68 * 1000000);
+
+	isp_266 = clk_get_rate(aclk_266);
+	printk(KERN_DEBUG "isp_266 : %ld\n", isp_266);
+
+	isp_266 = clk_get_rate(aclk_266_div0);
+	printk(KERN_DEBUG "isp_266_div0 : %ld\n", isp_266);
+
+	isp_266 = clk_get_rate(aclk_266_div1);
+	printk(KERN_DEBUG "isp_266_div1 : %ld\n", isp_266);
+
+	isp_266 = clk_get_rate(aclk_266_mpwm);
+	printk(KERN_DEBUG "isp_266_mpwm : %ld\n", isp_266);
+
+	clk_put(aclk_266);
+	clk_put(aclk_266_div0);
+	clk_put(aclk_266_div1);
+	clk_put(aclk_266_mpwm);
+
+	/* 3. UART-ISP */
+	sclk_uart_isp = clk_get(&pdev->dev, "sclk_uart_src_isp");
+	if (IS_ERR(sclk_uart_isp))
+		return PTR_ERR(sclk_uart_isp);
+
+	sclk_uart_isp_div = clk_get(&pdev->dev, "sclk_uart_isp");
+	if (IS_ERR(sclk_uart_isp_div))
+		return PTR_ERR(sclk_uart_isp_div);
+
+	clk_set_parent(sclk_uart_isp_div, sclk_uart_isp);
+	clk_set_rate(sclk_uart_isp_div, 50 * 1000000);
+
+	isp_uart = clk_get_rate(sclk_uart_isp);
+	printk(KERN_DEBUG "isp_uart : %ld\n", isp_uart);
+	isp_uart = clk_get_rate(sclk_uart_isp_div);
+	printk(KERN_DEBUG "isp_uart_div : %ld\n", isp_uart);
+
+	clk_put(sclk_uart_isp);
+	clk_put(sclk_uart_isp_div);
+
+	/* MIPI-CSI */
+	mout_mpll = clk_get(&pdev->dev, "mout_mpll_user");
+	if (IS_ERR(mout_mpll))
+		return PTR_ERR(mout_mpll);
+	sclk_mipi = clk_get(&pdev->dev, "sclk_gscl_wrap0");
+	if (IS_ERR(sclk_mipi))
+		return PTR_ERR(sclk_mipi);
+
+	clk_set_parent(sclk_mipi, mout_mpll);
+	clk_set_rate(sclk_mipi, 267 * 1000000);
+
+	mout_mpll = clk_get(&pdev->dev, "mout_mpll_user");
+	if (IS_ERR(mout_mpll))
+		return PTR_ERR(mout_mpll);
+	sclk_mipi = clk_get(&pdev->dev, "sclk_gscl_wrap1");
+	if (IS_ERR(sclk_mipi))
+		return PTR_ERR(sclk_mipi);
+
+	clk_set_parent(sclk_mipi, mout_mpll);
+	clk_set_rate(sclk_mipi, 267 * 1000000);
+	mipi = clk_get_rate(mout_mpll);
+	printk(KERN_DEBUG "mipi_src : %ld\n", mipi);
+	mipi = clk_get_rate(sclk_mipi);
+	printk(KERN_DEBUG "mipi_div : %ld\n", mipi);
+
+	clk_put(mout_mpll);
+	clk_put(sclk_mipi);
+
+	/* camera A */
+	cam_src = clk_get(&pdev->dev, "xxti");
+	if (IS_ERR(cam_src))
+		return PTR_ERR(cam_src);
+	cam_A_clk = clk_get(&pdev->dev, "sclk_cam0");
+	if (IS_ERR(cam_A_clk))
+		return PTR_ERR(cam_A_clk);
+
+	epll = clk_get_rate(cam_src);
+	printk(KERN_DEBUG "epll : %ld\n", epll);
+
+	clk_set_parent(cam_A_clk, cam_src);
+	clk_set_rate(cam_A_clk, 24 * 1000000);
+
+	clk_put(cam_src);
+	clk_put(cam_A_clk);
+
+	/* camera B */
+	cam_src = clk_get(&pdev->dev, "xxti");
+	if (IS_ERR(cam_src))
+		return PTR_ERR(cam_src);
+	cam_A_clk = clk_get(&pdev->dev, "sclk_cam1");
+	if (IS_ERR(cam_A_clk))
+		return PTR_ERR(cam_A_clk);
+
+	epll = clk_get_rate(cam_src);
+	printk(KERN_DEBUG "epll : %ld\n", epll);
+
+	clk_set_parent(cam_A_clk, cam_src);
+	clk_set_rate(cam_A_clk, 24 * 1000000);
+
+	clk_put(cam_src);
+	clk_put(cam_A_clk);
+	return 0;
+}
+
+#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+
+int exynos5_fimc_is_clk_on(struct platform_device *pdev)
+{
+	struct clk *gsc_ctrl = NULL;
+	struct clk *isp_ctrl = NULL;
+	struct clk *mipi_ctrl = NULL;
+	struct clk *cam_if_top = NULL;
+	struct clk *cam_A_clk = NULL;
+	struct regulator *regulator = NULL;
+
+	printk(KERN_DEBUG "exynos5_fimc_is_clk_on\n");
+
+#if defined(CONFIG_MACH_P10)
+	/* CAM A port : POWER */
+	gpio_set_value(GPIO_CAM_IO_EN, 1);
+
+	/* ISP */
+	regulator = regulator_get(NULL, "cam_core_1.8v");
+	if (IS_ERR(regulator)) {
+		printk(KERN_ERR "%s : regulator_get failed\n", __func__);
+		return PTR_ERR(regulator);
+	}
+	regulator_enable(regulator);
+	regulator_put(regulator);
+
+	/* ldo18 */
+	regulator = regulator_get(NULL, "cam_io_from_1.8v");
+	if (IS_ERR(regulator)) {
+		printk(KERN_ERR "%s : regulator_get failed\n", __func__);
+		return PTR_ERR(regulator);
+	}
+	regulator_enable(regulator);
+	regulator_put(regulator);
+
+	/* ldo24 */
+	regulator = regulator_get(NULL, "cam_af_2.8v");
+	if (IS_ERR(regulator)) {
+		printk(KERN_ERR "%s : regulator_get failed\n", __func__);
+		return PTR_ERR(regulator);
+	}
+	regulator_enable(regulator);
+	regulator_put(regulator);
+
+	/* ldo19 */
+	regulator = regulator_get(NULL, "vt_cam_1.8v");
+	if (IS_ERR(regulator)) {
+		printk(KERN_ERR "%s : regulator_get failed\n", __func__);
+		return PTR_ERR(regulator);
+	}
+	regulator_enable(regulator);
+	regulator_put(regulator);
+#endif
+
+	gsc_ctrl = clk_get(&pdev->dev, "gscl");
+	if (IS_ERR(gsc_ctrl)) {
+		printk(KERN_ERR "%s : clk_get(gscl) failed\n", __func__);
+		return PTR_ERR(gsc_ctrl);
+	}
+
+	clk_enable(gsc_ctrl);
+	clk_put(gsc_ctrl);
+
+	isp_ctrl = clk_get(&pdev->dev, "isp0");
+	if (IS_ERR(isp_ctrl)) {
+		printk(KERN_ERR "%s : clk_get(isp0) failed\n", __func__);
+		return PTR_ERR(isp_ctrl);
+	}
+
+	clk_enable(isp_ctrl);
+	clk_put(isp_ctrl);
+
+	isp_ctrl = clk_get(&pdev->dev, "isp1");
+	if (IS_ERR(isp_ctrl)) {
+		printk(KERN_ERR "%s : clk_get(isp1) failed\n", __func__);
+		return PTR_ERR(isp_ctrl);
+	}
+
+	clk_enable(isp_ctrl);
+	clk_put(isp_ctrl);
+
+	mipi_ctrl = clk_get(&pdev->dev, "gscl_wrap0");
+	if (IS_ERR(mipi_ctrl)) {
+		printk(KERN_ERR "%s : clk_get(gscl_wrap0) failed\n", __func__);
+		return PTR_ERR(mipi_ctrl);
+	}
+
+	clk_enable(mipi_ctrl);
+	clk_put(mipi_ctrl);
+
+	mipi_ctrl = clk_get(&pdev->dev, "gscl_wrap1");
+	if (IS_ERR(mipi_ctrl)) {
+		printk(KERN_ERR "%s : clk_get(gscl_wrap1) failed\n", __func__);
+		return PTR_ERR(mipi_ctrl);
+	}
+
+	clk_enable(mipi_ctrl);
+	clk_put(mipi_ctrl);
+
+	cam_if_top = clk_get(&pdev->dev, "camif_top");
+	if (IS_ERR(cam_if_top)) {
+		printk(KERN_ERR "%s : clk_get(camif_top) failed\n", __func__);
+		return PTR_ERR(cam_if_top);
+	}
+
+	clk_enable(cam_if_top);
+	clk_put(cam_if_top);
+
+	cam_A_clk = clk_get(&pdev->dev, "sclk_cam0");
+	if (IS_ERR(cam_A_clk)) {
+		printk(KERN_ERR "%s : clk_get(sclk_cam0) failed\n", __func__);
+		return PTR_ERR(cam_A_clk);
+	}
+
+	clk_enable(cam_A_clk);
+	clk_put(cam_A_clk);
+
+	cam_A_clk = clk_get(&pdev->dev, "sclk_cam1");
+	if (IS_ERR(cam_A_clk)) {
+		printk(KERN_ERR "%s : clk_get(sclk_cam1) failed\n", __func__);
+		return PTR_ERR(cam_A_clk);
+	}
+
+	clk_enable(cam_A_clk);
+	clk_put(cam_A_clk);
+
+	return 0;
+}
+
+int exynos5_fimc_is_clk_off(struct platform_device *pdev)
+{
+	struct clk *gsc_ctrl = NULL;
+	struct clk *isp_ctrl = NULL;
+	struct clk *mipi_ctrl = NULL;
+	struct clk *cam_if_top = NULL;
+	struct clk *cam_A_clk = NULL;
+	struct regulator *regulator = NULL;
+
+	printk(KERN_DEBUG "exynos5_fimc_is_clk_on\n");
+
+	cam_A_clk = clk_get(&pdev->dev, "sclk_cam1");
+	if (IS_ERR(cam_A_clk)) {
+		printk(KERN_ERR "%s : clk_get(sclk_cam1) failed\n", __func__);
+		return PTR_ERR(cam_A_clk);
+	}
+
+	clk_disable(cam_A_clk);
+	clk_put(cam_A_clk);
+
+   	cam_A_clk = clk_get(&pdev->dev, "sclk_cam0");
+	if (IS_ERR(cam_A_clk)) {
+		printk(KERN_ERR "%s : clk_get(sclk_cam0) failed\n", __func__);
+		return PTR_ERR(cam_A_clk);
+	}
+
+	clk_disable(cam_A_clk);
+	clk_put(cam_A_clk);
+
+	cam_if_top = clk_get(&pdev->dev, "camif_top");
+	if (IS_ERR(cam_if_top)) {
+		printk(KERN_ERR "%s : clk_get(camif_top) failed\n", __func__);
+		return PTR_ERR(cam_if_top);
+	}
+
+	clk_disable(cam_if_top);
+	clk_put(cam_if_top);
+
+	mipi_ctrl = clk_get(&pdev->dev, "gscl_wrap1");
+	if (IS_ERR(mipi_ctrl)) {
+		printk(KERN_ERR "%s : clk_get(gscl_wrap1) failed\n", __func__);
+		return PTR_ERR(mipi_ctrl);
+	}
+
+	clk_disable(mipi_ctrl);
+	clk_put(mipi_ctrl);
+
+	mipi_ctrl = clk_get(&pdev->dev, "gscl_wrap0");
+	if (IS_ERR(mipi_ctrl)) {
+		printk(KERN_ERR "%s : clk_get(gscl_wrap0) failed\n", __func__);
+		return PTR_ERR(mipi_ctrl);
+	}
+
+	clk_disable(mipi_ctrl);
+	clk_put(mipi_ctrl);
+
+   	isp_ctrl = clk_get(&pdev->dev, "isp1");
+	if (IS_ERR(isp_ctrl)) {
+		printk(KERN_ERR "%s : clk_get(isp1) failed\n", __func__);
+		return PTR_ERR(isp_ctrl);
+	}
+
+	clk_disable(isp_ctrl);
+	clk_put(isp_ctrl);
+
+	isp_ctrl = clk_get(&pdev->dev, "isp0");
+	if (IS_ERR(isp_ctrl)) {
+		printk(KERN_ERR "%s : clk_get(isp0) failed\n", __func__);
+		return PTR_ERR(isp_ctrl);
+	}
+
+	clk_disable(isp_ctrl);
+	clk_put(isp_ctrl);
+
+	gsc_ctrl = clk_get(&pdev->dev, "gscl");
+	if (IS_ERR(gsc_ctrl)) {
+		printk(KERN_ERR "%s : clk_get(gscl) failed\n", __func__);
+		return PTR_ERR(gsc_ctrl);
+	}
+
+	clk_disable(gsc_ctrl);
+	clk_put(gsc_ctrl);
+
+#if defined(CONFIG_MACH_P10)
+	/* ldo19 */
+	regulator = regulator_get(NULL, "vt_cam_1.8v");
+	if (IS_ERR(regulator)) {
+		printk(KERN_ERR "%s : regulator_get failed\n", __func__);
+		return PTR_ERR(regulator);
+	}
+	if (regulator_is_enabled(regulator))
+		regulator_force_disable(regulator);
+	regulator_put(regulator);
+
+	/* ldo24 */
+	regulator = regulator_get(NULL, "cam_af_2.8v");
+	if (IS_ERR(regulator)) {
+		printk(KERN_ERR "%s : regulator_get failed\n", __func__);
+		return PTR_ERR(regulator);
+	}
+	if (regulator_is_enabled(regulator))
+		regulator_force_disable(regulator);
+	regulator_put(regulator);
+
+	/* ldo18 */
+	regulator = regulator_get(NULL, "cam_io_from_1.8v");
+	if (IS_ERR(regulator)) {
+		printk(KERN_ERR "%s : regulator_get failed\n", __func__);
+		return PTR_ERR(regulator);
+	}
+	if (regulator_is_enabled(regulator))
+		regulator_force_disable(regulator);
+	regulator_put(regulator);
+
+	/* ISP */
+	regulator = regulator_get(NULL, "cam_core_1.8v");
+	if (IS_ERR(regulator)) {
+		printk(KERN_ERR "%s : regulator_get failed\n", __func__);
+		return PTR_ERR(regulator);
+	}
+	if (regulator_is_enabled(regulator))
+		regulator_force_disable(regulator);
+	regulator_put(regulator);
+
+	/* CAM A port : POWER */
+	gpio_set_value(GPIO_CAM_IO_EN, 0);
+#endif
+
+	return 0;
+}
+#endif
diff --git a/arch/arm/mach-exynos/setup-fimc.c b/arch/arm/mach-exynos/setup-fimc.c
new file mode 100644
index 0000000..4323429
--- /dev/null
+++ b/arch/arm/mach-exynos/setup-fimc.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics Co., Ltd.
+ *
+ * Exynos4 camera interface GPIO configuration.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/gpio.h>
+#include <plat/gpio-cfg.h>
+#include <plat/camport.h>
+
+int exynos4_fimc_setup_gpio(enum s5p_camport_id id)
+{
+	u32 gpio8, gpio5;
+	u32 sfn;
+	int ret;
+
+	switch (id) {
+	case S5P_CAMPORT_A:
+		gpio8 = EXYNOS4210_GPJ0(0); /* PCLK, VSYNC, HREF, DATA[0:4] */
+		gpio5 = EXYNOS4210_GPJ1(0); /* DATA[5:7], CLKOUT, FIELD */
+		sfn = S3C_GPIO_SFN(2);
+		break;
+
+	case S5P_CAMPORT_B:
+		gpio8 = EXYNOS4210_GPE0(0); /* DATA[0:7] */
+		gpio5 = EXYNOS4210_GPE1(0); /* PCLK, VSYNC, HREF, CLKOUT, FIELD */
+		sfn = S3C_GPIO_SFN(3);
+		break;
+
+	default:
+		WARN(1, "Wrong camport id: %d\n", id);
+		return -EINVAL;
+	}
+
+	ret = s3c_gpio_cfgall_range(gpio8, 8, sfn, S3C_GPIO_PULL_UP);
+	if (ret)
+		return ret;
+
+	return s3c_gpio_cfgall_range(gpio5, 5, sfn, S3C_GPIO_PULL_UP);
+}
diff --git a/arch/arm/mach-exynos/setup-fimc0.c b/arch/arm/mach-exynos/setup-fimc0.c
new file mode 100644
index 0000000..e95adcb
--- /dev/null
+++ b/arch/arm/mach-exynos/setup-fimc0.c
@@ -0,0 +1,107 @@
+/* linux/arch/arm/mach-s5pv310/setup-fimc0.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Base FIMC 0 gpio configuration
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/gpio.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <plat/clock.h>
+#include <plat/gpio-cfg.h>
+#include <mach/regs-gpio.h>
+#include <plat/map-s5p.h>
+#include <plat/cpu.h>
+#include <mach/map.h>
+
+struct platform_device; /* don't need the contents */
+
+void s3c_fimc0_cfg_gpio(struct platform_device *pdev)
+{
+#if defined(CONFIG_MACH_SMDK4212) || defined(CONFIG_MACH_SMDK4210)
+	if (soc_is_exynos4210()) {
+		/* CAM A port(b0010) : PCLK, VSYNC, HREF, DATA[0-4] */
+		s3c_gpio_cfgrange_nopull(EXYNOS4210_GPJ0(0), 8, S3C_GPIO_SFN(2));
+		/* CAM A port(b0010) : DATA[5-7], CLKOUT(MIPI CAM also), FIELD */
+		s3c_gpio_cfgrange_nopull(EXYNOS4210_GPJ1(0), 5, S3C_GPIO_SFN(2));
+		/* CAM B port(b0011) : DATA[0-7] */
+		s3c_gpio_cfgrange_nopull(EXYNOS4210_GPE1(0), 8, S3C_GPIO_SFN(3));
+		/* CAM B port(b0011) : PCLK, VSYNC, HREF, FIELD, CLKOUT */
+		s3c_gpio_cfgrange_nopull(EXYNOS4210_GPE0(0), 5, S3C_GPIO_SFN(3));
+	} else {
+		/* CAM A port(b0010) : PCLK, VSYNC, HREF, DATA[0-4] */
+		s3c_gpio_cfgrange_nopull(EXYNOS4212_GPJ0(0), 8, S3C_GPIO_SFN(2));
+		/* CAM A port(b0010) : DATA[5-7], CLKOUT(MIPI CAM also), FIELD */
+		s3c_gpio_cfgrange_nopull(EXYNOS4212_GPJ1(0), 5, S3C_GPIO_SFN(2));
+		/* CAM B port(b0011) : PCLK, DATA[0-6] */
+		s3c_gpio_cfgrange_nopull(EXYNOS4212_GPM0(0), 8, S3C_GPIO_SFN(3));
+		/* CAM B port(b0011) : FIELD, DATA[7]*/
+		s3c_gpio_cfgrange_nopull(EXYNOS4212_GPM1(0), 2, S3C_GPIO_SFN(3));
+		/* CAM B port(b0011) : VSYNC, HREF, CLKOUT*/
+		s3c_gpio_cfgrange_nopull(EXYNOS4212_GPM2(0), 3, S3C_GPIO_SFN(3));
+	}
+	/* note : driver strength to max is unnecessary */
+#elif defined(CONFIG_MACH_PX)
+	/* CAM A port(b0010) : PCLK, VSYNC, HREF, DATA[0-4] */
+	s3c_gpio_cfgrange_nopull(EXYNOS4210_GPJ0(0), 8, S3C_GPIO_SFN(2));
+	/* CAM A port(b0010) : DATA[5-7], CLKOUT(MIPI CAM also), FIELD */
+	s3c_gpio_cfgrange_nopull(EXYNOS4210_GPJ1(0), 5, S3C_GPIO_SFN(2));
+	/* Disable Mclk */
+	s3c_gpio_cfgpin(EXYNOS4210_GPJ1(3), S3C_GPIO_INPUT);
+	s3c_gpio_setpull(EXYNOS4210_GPJ1(3), S3C_GPIO_PULL_DOWN);
+
+	/* CAM B port(b0011) : DATA[0-7] */
+	s3c_gpio_cfgrange_nopull(EXYNOS4210_GPE1(0), 8, S3C_GPIO_SFN(3));
+	/* CAM B port(b0011) : PCLK, VSYNC, HREF, FIELD, CLKOUT */
+	s3c_gpio_cfgrange_nopull(EXYNOS4210_GPE0(0), 5, S3C_GPIO_SFN(3));
+#endif
+}
+
+int s3c_fimc_clk_on(struct platform_device *pdev, struct clk **clk)
+{
+	struct clk *sclk_fimc_lclk = NULL;
+
+	sclk_fimc_lclk = clk_get(&pdev->dev, "sclk_fimc");
+	if (IS_ERR(sclk_fimc_lclk)) {
+		dev_err(&pdev->dev, "failed to get sclk_fimc_lclk\n");
+		goto err_clk1;
+	}
+
+	/* be able to handle clock on/off only with this clock */
+	*clk = clk_get(&pdev->dev, "fimc");
+	if (IS_ERR(clk)) {
+		dev_err(&pdev->dev, "failed to get interface clock\n");
+		goto err_clk2;
+	}
+
+	clk_enable(*clk);
+	clk_enable(sclk_fimc_lclk);
+
+	return 0;
+
+err_clk2:
+	clk_put(sclk_fimc_lclk);
+err_clk1:
+	return -EINVAL;
+}
+
+int s3c_fimc_clk_off(struct platform_device *pdev, struct clk **clk)
+{
+	if (*clk != NULL) {
+		clk_disable(*clk);
+		clk_put(*clk);
+		*clk = NULL;
+	}
+
+	return 0;
+}
diff --git a/arch/arm/mach-exynos/setup-fimc1.c b/arch/arm/mach-exynos/setup-fimc1.c
new file mode 100644
index 0000000..76a1e97
--- /dev/null
+++ b/arch/arm/mach-exynos/setup-fimc1.c
@@ -0,0 +1,21 @@
+/* linux/arch/arm/mach-s5pv310/setup-fimc1.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Base FIMC 1 gpio configuration
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+struct platform_device; /* don't need the contents */
+
+#include <mach/gpio.h>
+#include <plat/gpio-cfg.h>
+
+void s3c_fimc1_cfg_gpio(struct platform_device *pdev) { }
diff --git a/arch/arm/mach-exynos/setup-fimc2.c b/arch/arm/mach-exynos/setup-fimc2.c
new file mode 100644
index 0000000..a0d7fa3
--- /dev/null
+++ b/arch/arm/mach-exynos/setup-fimc2.c
@@ -0,0 +1,21 @@
+/* linux/arch/arm/mach-s5pv310/setup-fimc2.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Base FIMC 2 gpio configuration
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+struct platform_device; /* don't need the contents */
+
+#include <mach/gpio.h>
+#include <plat/gpio-cfg.h>
+
+void s3c_fimc2_cfg_gpio(struct platform_device *pdev) { }
diff --git a/arch/arm/mach-exynos/setup-fimc3.c b/arch/arm/mach-exynos/setup-fimc3.c
new file mode 100644
index 0000000..ee4182f
--- /dev/null
+++ b/arch/arm/mach-exynos/setup-fimc3.c
@@ -0,0 +1,21 @@
+/* linux/arch/arm/mach-s5pv310/setup-fimc3.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Base FIMC 3 gpio configuration
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+struct platform_device; /* don't need the contents */
+
+#include <mach/gpio.h>
+#include <plat/gpio-cfg.h>
+
+void s3c_fimc3_cfg_gpio(struct platform_device *pdev) { }
diff --git a/arch/arm/mach-exynos/setup-fimd.c b/arch/arm/mach-exynos/setup-fimd.c
new file mode 100644
index 0000000..91bad86
--- /dev/null
+++ b/arch/arm/mach-exynos/setup-fimd.c
@@ -0,0 +1,73 @@
+/* linux/arch/arm/mach-exynos/setup-fimd.c
+ *
+ * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * Base Exynos4 FIMD configuration
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/fb.h>
+#include <linux/gpio.h>
+#include <linux/clk.h>
+
+#include <plat/fb.h>
+#include <plat/gpio-cfg.h>
+#include <plat/clock.h>
+
+#include <mach/regs-clock.h>
+#include <mach/map.h>
+
+void exynos4_fimd_cfg_gpios(unsigned int base, unsigned int nr,
+		unsigned int cfg, s5p_gpio_drvstr_t drvstr)
+{
+	s3c_gpio_cfgrange_nopull(base, nr, cfg);
+
+	for (; nr > 0; nr--, base++)
+		s5p_gpio_set_drvstr(base, drvstr);
+}
+
+int __init exynos4_fimd_setup_clock(struct device *dev, const char *bus_clk,
+		const char *parent, unsigned long clk_rate)
+{
+	struct clk *clk_parent;
+	struct clk *sclk;
+
+	sclk = clk_get(dev, bus_clk);
+	if (IS_ERR(sclk))
+		return PTR_ERR(sclk);
+
+	clk_parent = clk_get(NULL, parent);
+	if (IS_ERR(clk_parent)) {
+		clk_put(sclk);
+		return PTR_ERR(clk_parent);
+	}
+
+	if (clk_set_parent(sclk, clk_parent)) {
+		pr_err("Unable to set parent %s of clock %s.\n",
+				clk_parent->name, sclk->name);
+		clk_put(sclk);
+		clk_put(clk_parent);
+		return PTR_ERR(sclk);
+	}
+
+	if (!clk_rate)
+		clk_rate = 87000000UL;
+
+	if (clk_set_rate(sclk, clk_rate)) {
+		pr_err("%s rate change failed: %lu\n", sclk->name, clk_rate);
+		clk_put(sclk);
+		clk_put(clk_parent);
+		return PTR_ERR(sclk);
+	}
+
+	clk_put(sclk);
+	clk_put(clk_parent);
+
+	return 0;
+}
diff --git a/arch/arm/mach-exynos/setup-fimd0.c b/arch/arm/mach-exynos/setup-fimd0.c
new file mode 100644
index 0000000..b763682
--- /dev/null
+++ b/arch/arm/mach-exynos/setup-fimd0.c
@@ -0,0 +1,119 @@
+/* linux/arch/arm/mach-exynos/setup-fimd0.c
+ *
+ * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * Base Exynos4 FIMD 0 configuration
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/fb.h>
+#include <linux/gpio.h>
+#include <linux/clk.h>
+
+#include <plat/fb.h>
+#include <plat/gpio-cfg.h>
+#include <plat/clock.h>
+
+#include <mach/regs-clock.h>
+#include <mach/map.h>
+
+#ifdef CONFIG_FB_S3C
+static void exynos4_fimd0_cfg_gpios(unsigned int base, unsigned int nr,
+		unsigned int cfg, s5p_gpio_drvstr_t drvstr)
+{
+	s3c_gpio_cfgrange_nopull(base, nr, cfg);
+
+	for (; nr > 0; nr--, base++)
+		s5p_gpio_set_drvstr(base, drvstr);
+}
+
+void exynos4_fimd0_gpio_setup_24bpp(void)
+{
+	unsigned int reg = 0;
+#if defined(CONFIG_LCD_WA101S) || defined(CONFIG_LCD_LTE480WV)
+	exynos4_fimd0_cfg_gpios(EXYNOS4_GPF0(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV4);
+	exynos4_fimd0_cfg_gpios(EXYNOS4_GPF1(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV4);
+	exynos4_fimd0_cfg_gpios(EXYNOS4_GPF2(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV4);
+	exynos4_fimd0_cfg_gpios(EXYNOS4_GPF3(0), 4, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV4);
+#elif defined(CONFIG_LCD_AMS369FG06)
+	exynos4_fimd0_cfg_gpios(EXYNOS4_GPF0(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV1);
+	exynos4_fimd0_cfg_gpios(EXYNOS4_GPF1(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV1);
+	exynos4_fimd0_cfg_gpios(EXYNOS4_GPF2(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV1);
+	exynos4_fimd0_cfg_gpios(EXYNOS4_GPF3(0), 4, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV1);
+#elif defined(CONFIG_LCD_LMS501KF03)
+	exynos4_fimd0_cfg_gpios(EXYNOS4_GPF0(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV4);
+	exynos4_fimd0_cfg_gpios(EXYNOS4_GPF1(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV1);
+	exynos4_fimd0_cfg_gpios(EXYNOS4_GPF2(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV1);
+	exynos4_fimd0_cfg_gpios(EXYNOS4_GPF3(0), 4, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV1);
+#endif
+	/*
+	 * Set DISPLAY_CONTROL register for Display path selection.
+	 *
+	 * DISPLAY_CONTROL[1:0]
+	 * ---------------------
+	 *  00 | MIE
+	 *  01 | MDINE
+	 *  10 | FIMD : selected
+	 *  11 | FIMD
+	 */
+#ifdef CONFIG_FB_S5P_MDNIE
+	reg = __raw_readl(S3C_VA_SYS + 0x0210);
+	reg &= ~(1<<13);
+	reg &= ~(1<<12);
+	reg &= ~(3<<10);
+	reg |= (1<<0);
+	reg &= ~(1<<1);
+	__raw_writel(reg, S3C_VA_SYS + 0x0210);
+#else
+	reg = __raw_readl(S3C_VA_SYS + 0x0210);
+	reg |= (1 << 1);
+	__raw_writel(reg, S3C_VA_SYS + 0x0210);
+#endif
+}
+#endif
+
+int __init exynos4_fimd0_setup_clock(struct device *dev, const char *parent,
+					unsigned long clk_rate)
+{
+	struct clk *clk_parent;
+	struct clk *sclk;
+
+	sclk = clk_get(dev, "sclk_fimd");
+	if (IS_ERR(sclk))
+		return PTR_ERR(sclk);
+
+	clk_parent = clk_get(NULL, parent);
+	if (IS_ERR(clk_parent)) {
+		clk_put(sclk);
+		return PTR_ERR(clk_parent);
+	}
+
+	if (clk_set_parent(sclk, clk_parent)) {
+		pr_err("Unable to set parent %s of clock %s.\n",
+				clk_parent->name, sclk->name);
+		clk_put(sclk);
+		clk_put(clk_parent);
+		return PTR_ERR(sclk);
+	}
+
+	if (!clk_rate)
+		clk_rate = 134000000UL;
+
+	if (clk_set_rate(sclk, clk_rate)) {
+		pr_err("%s rate change failed: %lu\n", sclk->name, clk_rate);
+		clk_put(sclk);
+		clk_put(clk_parent);
+		return PTR_ERR(sclk);
+	}
+
+	clk_put(sclk);
+	clk_put(clk_parent);
+
+	return 0;
+}
diff --git a/arch/arm/mach-exynos/setup-gsc.c b/arch/arm/mach-exynos/setup-gsc.c
new file mode 100644
index 0000000..493d756
--- /dev/null
+++ b/arch/arm/mach-exynos/setup-gsc.c
@@ -0,0 +1,95 @@
+/* linux/arch/arm/mach-exynos/setup-gsc.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * Base Exynos5 G-Scaler clock configuration
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <plat/clock.h>
+#include <plat/devs.h>
+#include <mach/regs-clock.h>
+#include <mach/map.h>
+#include <media/exynos_gscaler.h>
+
+void __init exynos5_gsc_set_pdev_name(int id, char *name)
+{
+	switch (id) {
+	case 0:
+		exynos5_device_gsc0.name = name;
+		break;
+	case 1:
+		exynos5_device_gsc1.name = name;
+		break;
+	case 2:
+		exynos5_device_gsc2.name = name;
+		break;
+	case 3:
+		exynos5_device_gsc3.name = name;
+		break;
+	}
+}
+
+int __init exynos5_gsc_set_parent_clock(const char *child, const char *parent)
+{
+	struct clk *clk_parent;
+	struct clk *clk_child;
+
+	clk_child = clk_get(NULL, child);
+	if (IS_ERR(clk_child)) {
+		pr_err("failed to get %s clock.\n", child);
+		return PTR_ERR(clk_child);
+	}
+
+	clk_parent = clk_get(NULL, parent);
+	if (IS_ERR(clk_parent)) {
+		clk_put(clk_child);
+		pr_err("failed to get %s clock.\n", parent);
+		return PTR_ERR(clk_parent);
+	}
+
+	if (clk_set_parent(clk_child, clk_parent)) {
+		pr_err("Unable to set parent %s of clock %s.\n",
+				clk_parent->name, clk_child->name);
+		clk_put(clk_child);
+		clk_put(clk_parent);
+		return PTR_ERR(clk_child);
+	}
+
+	clk_put(clk_child);
+	clk_put(clk_parent);
+
+	return 0;
+}
+
+int __init exynos5_gsc_set_clock_rate(const char *clk, unsigned long clk_rate)
+{
+	struct clk *gsc_clk;
+
+	gsc_clk = clk_get(NULL, clk);
+	if (IS_ERR(gsc_clk)) {
+		pr_err("failed to get %s clock.\n", clk);
+		return PTR_ERR(gsc_clk);
+	}
+
+	if (!clk_rate)
+		clk_rate = 310000000UL;
+
+	if (clk_set_rate(gsc_clk, clk_rate)) {
+		pr_err("%s rate change failed: %lu\n", gsc_clk->name, clk_rate);
+		clk_put(gsc_clk);
+		return PTR_ERR(gsc_clk);
+	}
+
+	clk_put(gsc_clk);
+
+	return 0;
+}
diff --git a/arch/arm/mach-exynos/setup-hdmi.c b/arch/arm/mach-exynos/setup-hdmi.c
new file mode 100644
index 0000000..b3ce85b
--- /dev/null
+++ b/arch/arm/mach-exynos/setup-hdmi.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics Co.Ltd
+ * Author: Joonyoung Shim <jy0922.shim@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundationr
+ */
+
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <plat/gpio-cfg.h>
+
+void s5p_hdmi_cfg_hpd(bool enable)
+{
+	if (enable)
+		s3c_gpio_cfgpin(GPIO_HDMI_HPD, S3C_GPIO_SFN(3));
+	else
+		s3c_gpio_cfgpin(GPIO_HDMI_HPD, S3C_GPIO_SFN(0xf));
+
+	s3c_gpio_setpull(GPIO_HDMI_HPD, S3C_GPIO_PULL_DOWN);
+}
+
+int s5p_hdmi_get_hpd(void)
+{
+	return !!gpio_get_value(GPIO_HDMI_HPD);
+}
diff --git a/arch/arm/mach-exynos/setup-i2c0.c b/arch/arm/mach-exynos/setup-i2c0.c
new file mode 100644
index 0000000..e6ae115
--- /dev/null
+++ b/arch/arm/mach-exynos/setup-i2c0.c
@@ -0,0 +1,31 @@
+/*
+ * linux/arch/arm/mach-exynos/setup-i2c0.c
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * I2C0 GPIO configuration.
+ *
+ * Based on plat-s3c64xx/setup-i2c0.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+struct platform_device; /* don't need the contents */
+
+#include <linux/gpio.h>
+#include <plat/iic.h>
+#include <plat/gpio-cfg.h>
+#include <plat/cpu.h>
+
+void s3c_i2c0_cfg_gpio(struct platform_device *dev)
+{
+	if (soc_is_exynos5210() || soc_is_exynos5250())
+		s3c_gpio_cfgall_range(EXYNOS5_GPB3(0), 2,
+			S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
+	else
+		s3c_gpio_cfgall_range(EXYNOS4_GPD1(0), 2,
+			S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
+}
diff --git a/arch/arm/mach-exynos/setup-i2c1.c b/arch/arm/mach-exynos/setup-i2c1.c
new file mode 100644
index 0000000..4cf6d92
--- /dev/null
+++ b/arch/arm/mach-exynos/setup-i2c1.c
@@ -0,0 +1,28 @@
+/*
+ * linux/arch/arm/mach-exynos/setup-i2c1.c
+ *
+ * Copyright (C) 2010 Samsung Electronics Co., Ltd.
+ *
+ * I2C1 GPIO configuration.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+struct platform_device; /* don't need the contents */
+
+#include <linux/gpio.h>
+#include <plat/iic.h>
+#include <plat/gpio-cfg.h>
+#include <plat/cpu.h>
+
+void s3c_i2c1_cfg_gpio(struct platform_device *dev)
+{
+	if (soc_is_exynos5210() || soc_is_exynos5250())
+		s3c_gpio_cfgall_range(EXYNOS5_GPB3(2), 2,
+			S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
+	else
+		s3c_gpio_cfgall_range(EXYNOS4_GPD1(2), 2,
+			S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
+}
diff --git a/arch/arm/mach-exynos/setup-i2c2.c b/arch/arm/mach-exynos/setup-i2c2.c
new file mode 100644
index 0000000..d85d6ee
--- /dev/null
+++ b/arch/arm/mach-exynos/setup-i2c2.c
@@ -0,0 +1,28 @@
+/*
+ * linux/arch/arm/mach-exynos/setup-i2c2.c
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *
+ * I2C2 GPIO configuration.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+struct platform_device; /* don't need the contents */
+
+#include <linux/gpio.h>
+#include <plat/iic.h>
+#include <plat/gpio-cfg.h>
+#include <plat/cpu.h>
+
+void s3c_i2c2_cfg_gpio(struct platform_device *dev)
+{
+	if (soc_is_exynos5210() || soc_is_exynos5250())
+		s3c_gpio_cfgall_range(EXYNOS5_GPA0(6), 2,
+			S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
+	else
+		s3c_gpio_cfgall_range(EXYNOS4_GPA0(6), 2,
+			S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
+}
diff --git a/arch/arm/mach-exynos/setup-i2c3.c b/arch/arm/mach-exynos/setup-i2c3.c
new file mode 100644
index 0000000..e0ee9b7
--- /dev/null
+++ b/arch/arm/mach-exynos/setup-i2c3.c
@@ -0,0 +1,28 @@
+/*
+ * linux/arch/arm/mach-exynos/setup-i2c3.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *
+ * I2C3 GPIO configuration.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+struct platform_device; /* don't need the contents */
+
+#include <linux/gpio.h>
+#include <plat/iic.h>
+#include <plat/gpio-cfg.h>
+#include <plat/cpu.h>
+
+void s3c_i2c3_cfg_gpio(struct platform_device *dev)
+{
+	if (soc_is_exynos5210() || soc_is_exynos5250())
+		s3c_gpio_cfgall_range(EXYNOS5_GPA1(2), 2,
+			S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
+	else
+		s3c_gpio_cfgall_range(EXYNOS4_GPA1(2), 2,
+			S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
+}
diff --git a/arch/arm/mach-exynos/setup-i2c4.c b/arch/arm/mach-exynos/setup-i2c4.c
new file mode 100644
index 0000000..5e81e78
--- /dev/null
+++ b/arch/arm/mach-exynos/setup-i2c4.c
@@ -0,0 +1,31 @@
+/*
+ * linux/arch/arm/mach-exynos/setup-i2c4.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *
+ * I2C4 GPIO configuration.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+struct platform_device; /* don't need the contents */
+
+#include <linux/gpio.h>
+#include <plat/iic.h>
+#include <plat/gpio-cfg.h>
+#include <plat/cpu.h>
+
+void s3c_i2c4_cfg_gpio(struct platform_device *dev)
+{
+	if (soc_is_exynos4210())
+		s3c_gpio_cfgall_range(EXYNOS4_GPB(2), 2,
+			S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
+	else if (soc_is_exynos4212())
+		s3c_gpio_cfgall_range(EXYNOS4_GPB(0), 2,
+			S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
+	else
+		s3c_gpio_cfgall_range(EXYNOS5_GPA2(0), 2,
+			S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
+}
diff --git a/arch/arm/mach-exynos/setup-i2c5.c b/arch/arm/mach-exynos/setup-i2c5.c
new file mode 100644
index 0000000..8253fc1
--- /dev/null
+++ b/arch/arm/mach-exynos/setup-i2c5.c
@@ -0,0 +1,31 @@
+/*
+ * linux/arch/arm/mach-exynos/setup-i2c5.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *
+ * I2C5 GPIO configuration.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+struct platform_device; /* don't need the contents */
+
+#include <linux/gpio.h>
+#include <plat/iic.h>
+#include <plat/gpio-cfg.h>
+#include <plat/cpu.h>
+
+void s3c_i2c5_cfg_gpio(struct platform_device *dev)
+{
+	if (soc_is_exynos4210())
+		s3c_gpio_cfgall_range(EXYNOS4_GPB(6), 2,
+			S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
+	else if (soc_is_exynos4212())
+		s3c_gpio_cfgall_range(EXYNOS4_GPB(2), 2,
+			S3C_GPIO_SFN(3), S3C_GPIO_PULL_NONE);
+	else
+		s3c_gpio_cfgall_range(EXYNOS5_GPA2(2), 2,
+			S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
+}
diff --git a/arch/arm/mach-exynos/setup-i2c6.c b/arch/arm/mach-exynos/setup-i2c6.c
new file mode 100644
index 0000000..8d4fce9
--- /dev/null
+++ b/arch/arm/mach-exynos/setup-i2c6.c
@@ -0,0 +1,28 @@
+/*
+ * linux/arch/arm/mach-exynos/setup-i2c6.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *
+ * I2C6 GPIO configuration.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+struct platform_device; /* don't need the contents */
+
+#include <linux/gpio.h>
+#include <plat/iic.h>
+#include <plat/gpio-cfg.h>
+#include <plat/cpu.h>
+
+void s3c_i2c6_cfg_gpio(struct platform_device *dev)
+{
+	if (soc_is_exynos5210() || soc_is_exynos5250())
+		s3c_gpio_cfgall_range(EXYNOS5_GPB1(3), 2,
+			S3C_GPIO_SFN(4), S3C_GPIO_PULL_UP);
+	else
+		s3c_gpio_cfgall_range(EXYNOS4_GPC1(3), 2,
+			S3C_GPIO_SFN(4), S3C_GPIO_PULL_UP);
+}
diff --git a/arch/arm/mach-exynos/setup-i2c7.c b/arch/arm/mach-exynos/setup-i2c7.c
new file mode 100644
index 0000000..8122381
--- /dev/null
+++ b/arch/arm/mach-exynos/setup-i2c7.c
@@ -0,0 +1,28 @@
+/*
+ * linux/arch/arm/mach-exynos/setup-i2c7.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *
+ * I2C7 GPIO configuration.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+struct platform_device; /* don't need the contents */
+
+#include <linux/gpio.h>
+#include <plat/iic.h>
+#include <plat/gpio-cfg.h>
+#include <plat/cpu.h>
+
+void s3c_i2c7_cfg_gpio(struct platform_device *dev)
+{
+	if (soc_is_exynos5210() || soc_is_exynos5250())
+		s3c_gpio_cfgall_range(EXYNOS5_GPB2(2), 2,
+			S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
+	else
+		s3c_gpio_cfgall_range(EXYNOS4_GPD0(2), 2,
+			S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
+}
diff --git a/arch/arm/mach-exynos/setup-jpeg.c b/arch/arm/mach-exynos/setup-jpeg.c
new file mode 100644
index 0000000..dc50398
--- /dev/null
+++ b/arch/arm/mach-exynos/setup-jpeg.c
@@ -0,0 +1,133 @@
+/* linux/arch/arm/mach-exynos/setup-jpeg.c
+ *
+ * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * Base Exynos4 JPEG configuration
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+
+#include <plat/gpio-cfg.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+
+#include <mach/regs-clock.h>
+#include <mach/map.h>
+
+int __init exynos4_jpeg_setup_clock(struct device *dev,
+					unsigned long clk_rate)
+{
+	struct clk *sclk = NULL;
+	struct clk *mout_jpeg = NULL;
+	struct clk *mout_mpll = NULL;
+	int ret;
+
+	sclk = clk_get(dev, "aclk_clk_jpeg");
+	if (IS_ERR(sclk)) {
+		dev_err(dev, "failed to get aclk for jpeg\n");
+		goto err_clk1;
+	}
+
+	mout_jpeg = clk_get(dev, "mout_jpeg0");
+
+	if (IS_ERR(mout_jpeg)) {
+		dev_err(dev, "failed to get mout_jpeg0 for jpeg\n");
+		goto err_clk2;
+	}
+
+	ret = clk_set_parent(sclk, mout_jpeg);
+	if (ret < 0) {
+		dev_err(dev, "failed to clk_set_parent for jpeg\n");
+		goto err_clk2;
+	}
+
+	mout_mpll = clk_get(dev, "mout_mpll_user");
+
+	if (IS_ERR(mout_mpll)) {
+		dev_err(dev, "failed to get mout_mpll for jpeg\n");
+		goto err_clk2;
+	}
+
+	ret = clk_set_parent(mout_jpeg, mout_mpll);
+	if (ret < 0) {
+		dev_err(dev, "failed to clk_set_parent for jpeg\n");
+		goto err_clk2;
+	}
+
+	ret = clk_set_rate(sclk, clk_rate);
+	if (ret < 0) {
+		dev_err(dev, "failed to clk_set_rate of sclk for jpeg\n");
+		goto err_clk2;
+	}
+	dev_dbg(dev, "set jpeg aclk rate\n");
+
+	clk_put(mout_jpeg);
+	clk_put(mout_mpll);
+
+	ret = clk_enable(sclk);
+	if (ret < 0) {
+		dev_err(dev, "failed to clk_enable of aclk for jpeg\n");
+		goto err_clk2;
+	}
+
+	return 0;
+
+err_clk2:
+	clk_put(mout_mpll);
+err_clk1:
+	clk_put(sclk);
+
+	return -EINVAL;
+}
+
+int __init exynos5_jpeg_setup_clock(struct device *dev,
+					unsigned long clk_rate)
+{
+	struct clk *sclk;
+	struct clk *mout_user = NULL;
+		int ret;
+
+	sclk = clk_get(dev, "sclk_jpeg");
+	if (IS_ERR(sclk))
+		return PTR_ERR(sclk);
+	if (samsung_rev() >= EXYNOS5250_REV_1_0) {
+		mout_user = clk_get(dev, "mout_mpll_user");
+		if (IS_ERR(sclk))
+			return PTR_ERR(sclk);
+
+		ret = clk_set_parent(sclk, mout_user);
+		if (ret < 0) {
+			dev_err(dev, "failed to clk_set_parent for jpeg\n");
+			goto err_clk;
+		}
+	}
+	if (!clk_rate)
+		clk_rate = 150000000UL;
+
+	if (clk_set_rate(sclk, clk_rate)) {
+		pr_err("%s rate change failed: %lu\n", sclk->name, clk_rate);
+		clk_put(sclk);
+		return PTR_ERR(sclk);
+	}
+
+	clk_put(sclk);
+	if (samsung_rev() >= EXYNOS5250_REV_1_0)
+		clk_put(mout_user);
+
+	return 0;
+	if (samsung_rev() >= EXYNOS5250_REV_1_0) {
+err_clk:
+		clk_put(mout_user);
+
+		return -EINVAL;
+	}
+}
diff --git a/arch/arm/mach-exynos/setup-keypad.c b/arch/arm/mach-exynos/setup-keypad.c
new file mode 100644
index 0000000..2163904
--- /dev/null
+++ b/arch/arm/mach-exynos/setup-keypad.c
@@ -0,0 +1,36 @@
+/* linux/arch/arm/mach-exynos/setup-keypad.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * GPIO configuration for Exynos4 KeyPad device
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/gpio.h>
+#include <plat/gpio-cfg.h>
+
+void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
+{
+	/* Keypads can be of various combinations, Just making sure */
+
+	if (rows > 8) {
+		/* Set all the necessary GPX2 pins: KP_ROW[0~7] */
+		s3c_gpio_cfgall_range(EXYNOS4_GPX2(0), 8,
+					S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
+
+		/* Set all the necessary GPX3 pins: KP_ROW[8~] */
+		s3c_gpio_cfgall_range(EXYNOS4_GPX3(0), (rows - 8),
+					 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
+	} else {
+		/* Set all the necessary GPX2 pins: KP_ROW[x] */
+		s3c_gpio_cfgall_range(EXYNOS4_GPX2(0), rows,
+					 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
+	}
+
+	/* Set all the necessary GPX1 pins to special-function 3: KP_COL[x] */
+	s3c_gpio_cfgrange_nopull(EXYNOS4_GPX1(0), cols, S3C_GPIO_SFN(3));
+}
diff --git a/arch/arm/mach-exynos/setup-mfc.c b/arch/arm/mach-exynos/setup-mfc.c
new file mode 100644
index 0000000..0fc2f28
--- /dev/null
+++ b/arch/arm/mach-exynos/setup-mfc.c
@@ -0,0 +1,54 @@
+/* linux/arch/arm/mach-exynos/setup-mfc.c
+ *
+ * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * Base Exynos4 MFC configuration
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/fb.h>
+#include <linux/gpio.h>
+#include <linux/clk.h>
+
+#include <plat/fb.h>
+#include <plat/gpio-cfg.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/s5p-mfc.h>
+#include <plat/devs.h>
+
+#include <mach/regs-clock.h>
+#include <mach/map.h>
+
+unsigned int mfc_clk_rate;
+int exynos4_mfc_setup_clock(struct device *dev,
+		unsigned long clock_rate)
+{
+	mfc_clk_rate = clock_rate;
+
+	return 0;
+}
+
+static struct s5p_mfc_platdata default_mfc_pd __initdata = {
+	.clock_rate = 200 * MHZ,
+};
+
+void __init s5p_mfc_set_platdata(struct s5p_mfc_platdata *pd)
+{
+	if (!pd)
+		pd = &default_mfc_pd;
+
+	s3c_set_platdata(pd, sizeof(struct s5p_mfc_platdata),
+				&s5p_device_mfc);
+}
+
+void s5p_mfc_setname(struct platform_device *pdev, char *name)
+{
+	pdev->name = name;
+}
diff --git a/arch/arm/mach-exynos/setup-mipidsim.c b/arch/arm/mach-exynos/setup-mipidsim.c
new file mode 100644
index 0000000..e85e1e0
--- /dev/null
+++ b/arch/arm/mach-exynos/setup-mipidsim.c
@@ -0,0 +1,93 @@
+/* linux/arch/arm/mach-exynos/setup-mipidsim.c
+ *
+ * Copyright (c) 2011 Samsung Electronics
+ *
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * ERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * A 02111-1307 USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/regulator/consumer.h>
+
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+
+#include <plat/dsim.h>
+#include <plat/clock.h>
+#include <plat/regs-mipidsim.h>
+
+#define S5P_MIPI_M_RESETN 4
+
+static int s5p_dsim_enable_d_phy(struct mipi_dsim_device *dsim,
+		unsigned int enable)
+{
+	unsigned int reg;
+#if defined(CONFIG_ARCH_EXYNOS5)
+	reg = readl(S5P_MIPI_DPHY_CONTROL(1)) & ~(1 << 0);
+	reg |= (enable << 0);
+	writel(reg, S5P_MIPI_DPHY_CONTROL(1));
+#else
+	reg = readl(S5P_MIPI_DPHY_CONTROL(0)) & ~(1 << 0);
+	reg |= (enable << 0);
+	writel(reg, S5P_MIPI_DPHY_CONTROL(0));
+#endif
+	return 0;
+}
+
+static int s5p_dsim_enable_dsi_master(struct mipi_dsim_device *dsim,
+	unsigned int enable)
+{
+	unsigned int reg;
+#if defined(CONFIG_ARCH_EXYNOS5)
+	reg = readl(S5P_MIPI_DPHY_CONTROL(1)) & ~(1 << 2);
+	reg |= (enable << 2);
+	writel(reg, S5P_MIPI_DPHY_CONTROL(1));
+#else
+	reg = readl(S5P_MIPI_DPHY_CONTROL(0)) & ~(1 << 2);
+	reg |= (enable << 2);
+	writel(reg, S5P_MIPI_DPHY_CONTROL(0));
+#endif
+	return 0;
+}
+
+int s5p_dsim_part_reset(struct mipi_dsim_device *dsim)
+{
+#if defined(CONFIG_ARCH_EXYNOS5)
+	if (dsim->id == 0)
+		writel(S5P_MIPI_M_RESETN, S5P_MIPI_DPHY_CONTROL(1));
+#else
+	if (dsim->id == 0)
+		writel(S5P_MIPI_M_RESETN, S5P_MIPI_DPHY_CONTROL(0));
+#endif
+	return 0;
+}
+
+int s5p_dsim_init_d_phy(struct mipi_dsim_device *dsim, unsigned int enable)
+{
+	/**
+	 * DPHY and aster block must be enabled at the system initialization
+	 * step before data access from/to DPHY begins.
+	 */
+	s5p_dsim_enable_d_phy(dsim, enable);
+
+	s5p_dsim_enable_dsi_master(dsim, enable);
+	return 0;
+}
diff --git a/arch/arm/mach-exynos/setup-mshci-gpio.c b/arch/arm/mach-exynos/setup-mshci-gpio.c
new file mode 100644
index 0000000..4c73310
--- /dev/null
+++ b/arch/arm/mach-exynos/setup-mshci-gpio.c
@@ -0,0 +1,220 @@
+/* linux/arch/arm/mach-exynos/setup-mshci-gpio.c
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * EXYNOS4 - Helper functions for setting up MSHCI device(s) GPIO (HSMMC)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/card.h>
+#include <linux/delay.h>
+
+#include <mach/gpio.h>
+#include <mach/map.h>
+#include <plat/gpio-cfg.h>
+#include <plat/mshci.h>
+#include <plat/cpu.h>
+
+#define GPK0DRV	(S5P_VA_GPIO2 + 0x4C)
+#define GPK1DRV	(S5P_VA_GPIO2 + 0x6C)
+#define GPK2DRV	(S5P_VA_GPIO2 + 0x8C)
+#define GPK3DRV	(S5P_VA_GPIO2 + 0xAC)
+
+#define DIV_FSYS3	(S5P_VA_CMU + 0x0C54C)
+
+#if defined(CONFIG_MACH_M0) && defined(CONFIG_TARGET_LOCALE_EUR)
+#define EPLL_CON0_F	(S5P_VA_CMU + 0x0C110)
+
+void print_epll_con0(void)
+{
+	pr_info("EPLL_CON0 : 0x%x\n",__raw_readl(EPLL_CON0_F));
+}
+#endif
+
+void exynos4_setup_mshci_cfg_gpio(struct platform_device *dev, int width)
+{
+	unsigned int gpio;
+	struct s3c_mshci_platdata *pdata = dev->dev.platform_data;
+
+	/* early_printk("exynos4_setup_mshci_cfg_gpio\n"); */
+
+	/* Set all the necessary GPG0/GPG1 pins to special-function 2 */
+	for (gpio = EXYNOS4_GPK0(0); gpio < EXYNOS4_GPK0(2); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+	}
+
+	/* if CDn pin is used as eMMC_EN pin, it might make a problem
+	   So, a built-in type eMMC is embedded, it dose not set CDn pin */
+	if (pdata->cd_type != S3C_MSHCI_CD_PERMANENT) {
+		s3c_gpio_cfgpin(EXYNOS4_GPK0(2), S3C_GPIO_SFN(3));
+		s3c_gpio_setpull(EXYNOS4_GPK0(2), S3C_GPIO_PULL_NONE);
+	}
+
+	switch (width) {
+	case 8:
+		for (gpio = EXYNOS4_GPK1(3); gpio <= EXYNOS4_GPK1(6); gpio++) {
+			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
+			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		}
+		__raw_writel(0x2AAA, GPK1DRV);
+	case 4:
+		/* GPK[3:6] special-funtion 2 */
+		for (gpio = EXYNOS4_GPK0(3); gpio <= EXYNOS4_GPK0(6); gpio++) {
+			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		}
+		__raw_writel(0x2AAA, GPK0DRV);
+		break;
+	case 1:
+		/* GPK[3] special-funtion 2 */
+		for (gpio = EXYNOS4_GPK0(3); gpio < EXYNOS4_GPK0(4); gpio++) {
+			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		}
+		__raw_writel(0xAA, GPK0DRV);
+	default:
+		break;
+	}
+}
+
+void exynos4_setup_mshci_cfg_ddr(struct platform_device *dev, int ddr)
+{
+	if (ddr) {
+#ifdef CONFIG_EXYNOS4_MSHC_EPLL_45MHZ
+		__raw_writel(0x00, DIV_FSYS3);
+#elif defined(CONFIG_EXYNOS4_MSHC_VPLL_46MHZ)
+		__raw_writel(0x01, DIV_FSYS3);
+#else
+		if ((soc_is_exynos4412() || soc_is_exynos4212()) &&
+			samsung_rev() >= EXYNOS4412_REV_1_0) {
+			__raw_writel(0x1, DIV_FSYS3);
+		} else
+			__raw_writel(0x05, DIV_FSYS3);
+#endif
+	} else {
+#ifdef CONFIG_EXYNOS4_MSHC_EPLL_45MHZ
+		__raw_writel(0x01, DIV_FSYS3);
+#elif defined(CONFIG_EXYNOS4_MSHC_VPLL_46MHZ)
+		__raw_writel(0x03, DIV_FSYS3);
+#else
+		if ((soc_is_exynos4412() || soc_is_exynos4212()) &&
+			samsung_rev() >= EXYNOS4412_REV_1_0)
+			__raw_writel(0x3, DIV_FSYS3);
+		else
+			__raw_writel(0xb, DIV_FSYS3);
+#endif
+	}
+}
+
+void exynos4_setup_mshci_init_card(struct platform_device *dev)
+{
+	/*
+	 * Reset moviNAND for re-init.
+	 * output/low for eMMC_EN and input/pull-none for others
+	 * and then wait 10ms.
+	 */
+	__raw_writel(0x100, S5P_VA_GPIO2 + 0x40);
+	__raw_writel(0, S5P_VA_GPIO2 + 0x44);
+	__raw_writel(0, S5P_VA_GPIO2 + 0x48);
+	__raw_writel(0, S5P_VA_GPIO2 + 0x60);
+	__raw_writel(0, S5P_VA_GPIO2 + 0x64);
+	__raw_writel(0, S5P_VA_GPIO2 + 0x68);
+	mdelay(100);
+
+	/* set data buswidth 8 */
+	exynos4_setup_mshci_cfg_gpio(dev, 8);
+
+	/* power to moviNAND on */
+	gpio_set_value(EXYNOS4_GPK0(2), 1);
+
+	/* to wait a pull-up resistance ready */
+	mdelay(10);
+}
+
+void exynos4_setup_mshci_set_power(struct platform_device *dev, int en)
+{
+	struct s3c_mshci_platdata *pdata = dev->dev.platform_data;
+	unsigned int gpio = 0;
+
+	if (pdata->int_power_gpio) {
+		if (en) {
+#ifdef CONFIG_MACH_Q1_BD
+			mdelay(20);
+#endif
+			/*CMD/CLK*/
+			for (gpio = EXYNOS4_GPK0(0); gpio < EXYNOS4_GPK0(2);
+					gpio++) {
+				s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+				s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+			}
+			/*DAT[0]~[3]*/
+			for (gpio = EXYNOS4_GPK0(3); gpio <= EXYNOS4_GPK0(6);
+					gpio++) {
+				s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+				s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+			}
+			/*DAT[4]~[7]*/
+			for (gpio = EXYNOS4_GPK1(3); gpio <= EXYNOS4_GPK1(6);
+					gpio++) {
+				s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
+				s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+			}
+
+			gpio_set_value(pdata->int_power_gpio, 1);
+			pr_info("%s : internal MMC Card ON samsung-mshc.\n",
+					__func__);
+		} else {
+#if defined(CONFIG_MACH_M0_CTC)
+			s3c_gpio_cfgpin(pdata->int_power_gpio, S3C_GPIO_OUTPUT);
+			s3c_gpio_setpull(pdata->int_power_gpio,
+					S3C_GPIO_PULL_NONE);
+#endif
+			gpio_set_value(pdata->int_power_gpio, 0);
+
+			/*CMD/CLK*/
+			for (gpio = EXYNOS4_GPK0(0); gpio < EXYNOS4_GPK0(2);
+					gpio++) {
+				s3c_gpio_cfgpin(gpio, S3C_GPIO_INPUT);
+				s3c_gpio_setpull(gpio, S3C_GPIO_PULL_DOWN);
+			}
+			/*DAT[0]~[3]*/
+			for (gpio = EXYNOS4_GPK0(3); gpio <= EXYNOS4_GPK0(6);
+					gpio++) {
+				s3c_gpio_cfgpin(gpio, S3C_GPIO_INPUT);
+				s3c_gpio_setpull(gpio, S3C_GPIO_PULL_DOWN);
+			}
+			/*DAT[4]~[7]*/
+			for (gpio = EXYNOS4_GPK1(3); gpio <= EXYNOS4_GPK1(6);
+					gpio++) {
+				s3c_gpio_cfgpin(gpio, S3C_GPIO_INPUT);
+				s3c_gpio_setpull(gpio, S3C_GPIO_PULL_DOWN);
+			}
+			pr_info("%s : internal MMC Card OFF samsung-mshc.\n",
+					__func__);
+			mdelay(50);
+		}
+	}
+}
+
+void exynos4_setup_mshci_shutdown()
+{
+        /* to reset eMMC card, VDD of eMMC should be off over 1ms */
+	__raw_writel(0x100, S5P_VA_GPIO2 + 0x40);
+	__raw_writel(0, S5P_VA_GPIO2 + 0x44);
+	__raw_writel(0, S5P_VA_GPIO2 + 0x48);
+	__raw_writel(0, S5P_VA_GPIO2 + 0x60);
+	__raw_writel(0, S5P_VA_GPIO2 + 0x64);
+	__raw_writel(0, S5P_VA_GPIO2 + 0x68);
+	mdelay(10);
+}
diff --git a/arch/arm/mach-exynos/setup-mshci.c b/arch/arm/mach-exynos/setup-mshci.c
new file mode 100644
index 0000000..caaf0ec
--- /dev/null
+++ b/arch/arm/mach-exynos/setup-mshci.c
@@ -0,0 +1,37 @@
+/* linux/arch/arm/mach-exynos/setup-mshci.c
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * EXYNOS4 - Helper functions for settign up MSHCI device(s)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#include <linux/mmc/card.h>
+#include <linux/mmc/host.h>
+
+#include <plat/mshci.h>
+
+/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
+
+char *exynos4_mshci_clksrcs[1] = {
+	[0] = "sclk_dwmci",	/* sclk for mshc */
+};
+
+void exynos4_setup_mshci_cfg_card(struct platform_device *dev,
+				    void __iomem *r,
+				    struct mmc_ios *ios,
+				    struct mmc_card *card)
+{
+	/* still now, It dose not have something to do on booting time*/
+}
+
diff --git a/arch/arm/mach-exynos/setup-sdhci-gpio.c b/arch/arm/mach-exynos/setup-sdhci-gpio.c
new file mode 100644
index 0000000..1973e79
--- /dev/null
+++ b/arch/arm/mach-exynos/setup-sdhci-gpio.c
@@ -0,0 +1,336 @@
+/* linux/arch/arm/mach-exynos/setup-sdhci-gpio.c
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS4 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/card.h>
+
+#include <plat/gpio-cfg.h>
+#include <plat/regs-sdhci.h>
+#include <plat/sdhci.h>
+
+#if defined(CONFIG_ARCH_EXYNOS4)
+void exynos4_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
+{
+	struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
+	unsigned int gpio;
+
+	/* Set all the necessary GPK0[0:1] pins to special-function 2 */
+	for (gpio = EXYNOS4_GPK0(0); gpio < EXYNOS4_GPK0(2); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+	}
+
+	switch (width) {
+	case 8:
+		for (gpio = EXYNOS4_GPK1(3); gpio <= EXYNOS4_GPK1(6); gpio++) {
+			/* Data pin GPK1[3:6] to special-function 3 */
+			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+			s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+		}
+	case 4:
+		for (gpio = EXYNOS4_GPK0(3); gpio <= EXYNOS4_GPK0(6); gpio++) {
+			/* Data pin GPK0[3:6] to special-function 2 */
+			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+			s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+		}
+	default:
+		break;
+	}
+
+	if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
+		s3c_gpio_cfgpin(EXYNOS4_GPK0(2), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(EXYNOS4_GPK0(2), S3C_GPIO_PULL_UP);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+	}
+}
+
+void exynos4_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
+{
+	struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
+	unsigned int gpio;
+
+	/* Set all the necessary GPK1[0:1] pins to special-function 2 */
+	for (gpio = EXYNOS4_GPK1(0); gpio < EXYNOS4_GPK1(2); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+	}
+
+	for (gpio = EXYNOS4_GPK1(3); gpio <= EXYNOS4_GPK1(6); gpio++) {
+		/* Data pin GPK1[3:6] to special-function 2 */
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+	}
+
+	if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
+		s3c_gpio_cfgpin(EXYNOS4_GPK1(2), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(EXYNOS4_GPK1(2), S3C_GPIO_PULL_UP);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+	}
+}
+
+void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
+{
+	struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
+	unsigned int gpio;
+
+	/* Set all the necessary GPK2[0:1] pins to special-function 2 */
+	for (gpio = EXYNOS4_GPK2(0); gpio < EXYNOS4_GPK2(2); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+#ifdef CONFIG_MACH_U1
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV3);
+#elif defined(CONFIG_MACH_MIDAS)
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+#else
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+#endif
+	}
+
+	switch (width) {
+	case 8:
+		for (gpio = EXYNOS4_GPK3(3); gpio <= EXYNOS4_GPK3(6); gpio++) {
+			/* Data pin GPK3[3:6] to special-function 3 */
+			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+#ifdef CONFIG_MACH_U1
+			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+			s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV3);
+#elif defined(CONFIG_MACH_MIDAS)
+			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+			s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+#else
+			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+			s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+#endif
+		}
+	case 4:
+		for (gpio = EXYNOS4_GPK2(3); gpio <= EXYNOS4_GPK2(6); gpio++) {
+			/* Data pin GPK2[3:6] to special-function 2 */
+			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+#ifdef CONFIG_MACH_U1
+			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+			s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV3);
+#elif defined(CONFIG_MACH_MIDAS)
+			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+			s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+#else
+			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+			s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+#endif
+		}
+	default:
+		break;
+	}
+
+	if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
+		s3c_gpio_cfgpin(EXYNOS4_GPK2(2), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(EXYNOS4_GPK2(2), S3C_GPIO_PULL_NONE);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV2);
+	}
+}
+
+void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width)
+{
+	struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
+	unsigned int gpio;
+
+	/* Set all the necessary GPK3[0:1] pins to special-function 2 */
+	for (gpio = EXYNOS4_GPK3(0); gpio < EXYNOS4_GPK3(2); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+#ifdef CONFIG_MACH_U1
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV2);
+#elif defined(CONFIG_MACH_MIDAS)
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+#elif defined(CONFIG_MACH_PX)
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+#else
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+#endif
+	}
+
+#if defined(CONFIG_MACH_PX)
+	s3c_gpio_setpull(EXYNOS4_GPK3(1), S3C_GPIO_PULL_UP);
+#endif
+
+	for (gpio = EXYNOS4_GPK3(3); gpio <= EXYNOS4_GPK3(6); gpio++) {
+		/* Data pin GPK3[3:6] to special-function 2 */
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+#ifdef CONFIG_MACH_U1
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV2);
+#elif defined(CONFIG_MACH_MIDAS)
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+#elif defined(CONFIG_MACH_PX)
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+#else
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+#endif
+	}
+
+	if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
+		s3c_gpio_cfgpin(EXYNOS4_GPK3(2), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(EXYNOS4_GPK3(2), S3C_GPIO_PULL_NONE);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV2);
+	}
+}
+
+#endif /* CONFIG_ARCH_EXYNOS4 */
+
+#if defined(CONFIG_ARCH_EXYNOS5)
+void exynos5_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
+{
+	struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
+	unsigned int gpio;
+
+	/* Set all the necessary GPC0[0:1] pins to special-function 2 */
+	for (gpio = EXYNOS5_GPC0(0); gpio < EXYNOS5_GPC0(2); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+	}
+
+	switch (width) {
+	case 8:
+		for (gpio = EXYNOS5_GPC1(3); gpio <= EXYNOS5_GPC1(6); gpio++) {
+			/* Data pin GPK1[3:6] to special-function 3 */
+			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+			s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+		}
+	case 4:
+		for (gpio = EXYNOS5_GPC0(3); gpio <= EXYNOS5_GPC0(6); gpio++) {
+			/* Data pin GPK0[3:6] to special-function 2 */
+			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+			s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+		}
+	default:
+		break;
+	}
+
+	if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
+		s3c_gpio_cfgpin(EXYNOS5_GPC0(2), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(EXYNOS5_GPC0(2), S3C_GPIO_PULL_UP);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+	}
+}
+
+void exynos5_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
+{
+	struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
+	unsigned int gpio;
+
+	/* Set all the necessary GPK1[0:1] pins to special-function 2 */
+	for (gpio = EXYNOS5_GPC1(0); gpio < EXYNOS5_GPC1(2); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+	}
+
+	for (gpio = EXYNOS5_GPC1(3); gpio <= EXYNOS5_GPC1(6); gpio++) {
+		/* Data pin GPK1[3:6] to special-function 2 */
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+	}
+
+	if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
+		s3c_gpio_cfgpin(EXYNOS5_GPC1(2), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(EXYNOS5_GPC1(2), S3C_GPIO_PULL_UP);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+	}
+}
+
+void exynos5_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
+{
+	struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
+	unsigned int gpio;
+
+	/* Set all the necessary GPK2[0:1] pins to special-function 2 */
+	for (gpio = EXYNOS5_GPC2(0); gpio < EXYNOS5_GPC2(2); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+	}
+
+	switch (width) {
+	case 8:
+		for (gpio = EXYNOS5_GPC3(3); gpio <= EXYNOS5_GPC3(6); gpio++) {
+			/* Data pin GPK3[3:6] to special-function 3 */
+			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+			s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+		}
+	case 4:
+		for (gpio = EXYNOS5_GPC2(3); gpio <= EXYNOS5_GPC2(6); gpio++) {
+			/* Data pin GPK2[3:6] to special-function 2 */
+			s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+			s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+			s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+		}
+	default:
+		break;
+	}
+
+	if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
+		s3c_gpio_cfgpin(EXYNOS5_GPC2(2), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(EXYNOS5_GPC2(2), S3C_GPIO_PULL_UP);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+	}
+}
+
+void exynos5_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width)
+{
+	struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
+	unsigned int gpio;
+
+	/* Set all the necessary GPK3[0:1] pins to special-function 2 */
+	for (gpio = EXYNOS5_GPC3(0); gpio < EXYNOS5_GPC3(2); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+	}
+
+	for (gpio = EXYNOS5_GPC3(3); gpio <= EXYNOS5_GPC3(6); gpio++) {
+		/* Data pin GPK3[3:6] to special-function 2 */
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+	}
+
+	if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
+		s3c_gpio_cfgpin(EXYNOS5_GPC3(2), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(EXYNOS5_GPC3(2), S3C_GPIO_PULL_UP);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+	}
+}
+
+#endif /* CONFIG_ARCH_EXYNOS5 */
diff --git a/arch/arm/mach-exynos/setup-sdhci.c b/arch/arm/mach-exynos/setup-sdhci.c
new file mode 100644
index 0000000..7c6ea0f
--- /dev/null
+++ b/arch/arm/mach-exynos/setup-sdhci.c
@@ -0,0 +1,69 @@
+/* linux/arch/arm/mach-exynos/setup-sdhci.c
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS4 - Helper functions for settign up SDHCI device(s) (HSMMC)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#include <linux/mmc/card.h>
+#include <linux/mmc/host.h>
+
+#include <plat/regs-sdhci.h>
+
+/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
+
+char *exynos4_hsmmc_clksrcs[4] = {
+	[0] = NULL,
+	[1] = NULL,
+	[2] = "sclk_mmc",	/* mmc_bus */
+	[3] = NULL,
+};
+
+void exynos4_setup_sdhci_cfg_card(struct platform_device *dev, void __iomem *r,
+				  struct mmc_ios *ios, struct mmc_card *card)
+{
+	u32 ctrl2, ctrl3;
+
+	/* don't need to alter anything according to card-type */
+
+	ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
+
+	/* select base clock source to HCLK */
+
+	ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
+
+	/*
+	 * clear async mode, enable conflict mask, rx feedback ctrl, SD
+	 * clk hold and no use debounce count
+	 */
+
+	ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
+		  S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
+		  S3C_SDHCI_CTRL2_ENFBCLKRX |
+		  S3C_SDHCI_CTRL2_DFCNT_NONE |
+		  S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
+
+	/* Tx and Rx feedback clock delay control */
+
+	if (ios->clock < 25 * 1000000)
+		ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
+			 S3C_SDHCI_CTRL3_FCSEL2 |
+			 S3C_SDHCI_CTRL3_FCSEL1 |
+			 S3C_SDHCI_CTRL3_FCSEL0);
+	else
+		ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
+
+	writel(ctrl2, r + S3C_SDHCI_CONTROL2);
+	writel(ctrl3, r + S3C_SDHCI_CONTROL3);
+}
diff --git a/arch/arm/mach-exynos/setup-tvout.c b/arch/arm/mach-exynos/setup-tvout.c
new file mode 100644
index 0000000..7e487f8
--- /dev/null
+++ b/arch/arm/mach-exynos/setup-tvout.c
@@ -0,0 +1,118 @@
+/* linux/arch/arm/mach-exynos/setup-tvout.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Base TVOUT gpio configuration
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/gpio.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/types.h>
+#include <plat/clock.h>
+#include <plat/gpio-cfg.h>
+#include <mach/regs-clock.h>
+#include <mach/regs-gpio.h>
+#include <linux/io.h>
+#include <mach/map.h>
+#include <mach/gpio.h>
+#include <plat/tvout.h>
+#include <plat/cpu.h>
+
+#if defined(CONFIG_ARCH_EXYNOS4)
+#define HDMI_GPX(_nr)	EXYNOS4_GPX3(_nr)
+#elif defined(CONFIG_ARCH_EXYNOS5)
+#define HDMI_GPX(_nr)	EXYNOS5_GPX3(_nr)
+#endif
+
+struct platform_device; /* don't need the contents */
+
+void s5p_int_src_hdmi_hpd(struct platform_device *pdev)
+{
+	printk(KERN_INFO "%s()\n", __func__);
+	s3c_gpio_cfgpin(GPIO_HDMI_HPD, S3C_GPIO_SFN(0x3));
+	s3c_gpio_setpull(GPIO_HDMI_HPD, S3C_GPIO_PULL_NONE);
+}
+
+void s5p_int_src_ext_hpd(struct platform_device *pdev)
+{
+	printk(KERN_INFO "%s()\n", __func__);
+	s3c_gpio_cfgpin(GPIO_HDMI_HPD, S3C_GPIO_SFN(0xf));
+	/* To avoid floating state of the HPD pin *
+	 * in the absence of external pull-up     */
+#if defined(CONFIG_CPU_EXYNOS4212) || defined(CONFIG_CPU_EXYNOS4412)
+	s3c_gpio_setpull(GPIO_HDMI_HPD, S3C_GPIO_PULL_DOWN);
+#else
+	s3c_gpio_setpull(GPIO_HDMI_HPD, S3C_GPIO_PULL_NONE);
+#endif
+}
+
+int s5p_hpd_read_gpio(struct platform_device *pdev)
+{
+	int ret;
+	ret = gpio_get_value(GPIO_HDMI_HPD);
+	printk(KERN_INFO "%s(%d)\n", __func__, ret);
+	return ret;
+}
+
+int s5p_v4l2_hpd_read_gpio(void)
+{
+	return gpio_get_value(HDMI_GPX(7));
+}
+
+void s5p_v4l2_int_src_hdmi_hpd(void)
+{
+	s3c_gpio_cfgpin(HDMI_GPX(7), S3C_GPIO_SFN(0x3));
+	s3c_gpio_setpull(HDMI_GPX(7), S3C_GPIO_PULL_DOWN);
+}
+
+void s5p_v4l2_int_src_ext_hpd(void)
+{
+	s3c_gpio_cfgpin(HDMI_GPX(7), S3C_GPIO_SFN(0xf));
+	s3c_gpio_setpull(HDMI_GPX(7), S3C_GPIO_PULL_DOWN);
+}
+
+void s5p_cec_cfg_gpio(struct platform_device *pdev)
+{
+#ifdef CONFIG_HDMI_CEC
+	s3c_gpio_cfgpin(GPIO_HDMI_CEC, S3C_GPIO_SFN(0x3));
+	s3c_gpio_setpull(GPIO_HDMI_CEC, S3C_GPIO_PULL_NONE);
+#endif
+}
+
+#ifdef CONFIG_VIDEO_EXYNOS_TV
+void s5p_tv_setup(void)
+{
+	int ret;
+
+	/* direct HPD to HDMI chip */
+	if (soc_is_exynos4412()) {
+		gpio_request(GPIO_HDMI_HPD, "hpd-plug");
+
+		gpio_direction_input(GPIO_HDMI_HPD);
+		s3c_gpio_cfgpin(GPIO_HDMI_HPD, S3C_GPIO_SFN(0x3));
+		s3c_gpio_setpull(GPIO_HDMI_HPD, S3C_GPIO_PULL_NONE);
+	} else if (soc_is_exynos5250()) {
+		gpio_request(GPIO_HDMI_HPD, "hpd-plug");
+		gpio_direction_input(GPIO_HDMI_HPD);
+		s3c_gpio_cfgpin(GPIO_HDMI_HPD, S3C_GPIO_SFN(0x3));
+		s3c_gpio_setpull(GPIO_HDMI_HPD, S3C_GPIO_PULL_NONE);
+
+		/* HDMI CEC */
+		gpio_request(GPIO_HDMI_CEC, "hdmi-cec");
+		gpio_direction_input(GPIO_HDMI_CEC);
+		s3c_gpio_cfgpin(GPIO_HDMI_CEC, S3C_GPIO_SFN(0x3));
+		s3c_gpio_setpull(GPIO_HDMI_CEC, S3C_GPIO_PULL_NONE);
+	} else {
+		printk(KERN_ERR "HPD GPIOs are not defined!\n");
+	}
+}
+#endif
diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c
new file mode 100644
index 0000000..bae906f
--- /dev/null
+++ b/arch/arm/mach-exynos/setup-usb-phy.c
@@ -0,0 +1,1407 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics Co.Ltd
+ * Author: Yulgon Kim <yulgon.kim@samsung.com>
+ * Author: Joonyoung Shim <jy0922.shim@samsung.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <mach/regs-pmu.h>
+#include <mach/regs-pmu5.h>
+#include <mach/regs-usb-phy.h>
+#include <plat/cpu.h>
+#include <plat/usb-phy.h>
+#include <plat/regs-usb3-exynos-drd-phy.h>
+#include <linux/interrupt.h>
+#include <plat/usbgadget.h>
+#include <mach/sec_modem.h>
+
+#ifdef CONFIG_USB_OHCI_S5P
+   #include <plat/devs.h>
+   #include <linux/usb.h>
+   #include <linux/usb/otg.h>
+   #include <linux/usb/hcd.h>
+#endif
+
+#ifdef CONFIG_USB_OHCI_S5P
+   #include <plat/devs.h>
+   #include <linux/usb.h>
+   #include <linux/usb/otg.h>
+   #include <linux/usb/hcd.h>
+#endif
+
+#define ETC6PUD		(S5P_VA_GPIO2 + 0x228)
+#define EXYNOS4_USB_CFG		(S3C_VA_SYS + 0x21C)
+#define EXYNOS5_USB_CFG		(S3C_VA_SYS + 0x230)
+
+#define PHY_ENABLE	(1 << 0)
+#define PHY_DISABLE	(0)
+
+#ifdef CONFIG_USB_OHCI_S5P
+struct s5p_ohci_hcd {
+	struct device *dev;
+	struct usb_hcd *hcd;
+	struct clk *clk;
+	int power_on;
+};
+#endif
+
+enum usb_host_type {
+	HOST_PHY_EHCI	= (0x1 << 0),
+	HOST_PHY_OHCI	= (0x1 << 1),
+	HOST_PHY_DEVICE	= (0x1 << 2),
+};
+
+enum usb_phy_type {
+	USB_PHY		= (0x1 << 0),
+	USB_PHY0	= (0x1 << 0),
+	USB_PHY1	= (0x1 << 1),
+	USB_PHY_HSIC0	= (0x1 << 1),
+	USB_PHY_HSIC1	= (0x1 << 2),
+};
+
+struct exynos_usb_phy {
+	u8 lpa_entered;
+	unsigned long flags;
+	unsigned long usage;
+};
+
+static struct exynos_usb_phy usb_phy_control;
+
+static atomic_t host_usage;
+static DEFINE_MUTEX(phy_lock);
+static struct clk *phy_clk = NULL;
+
+static void exynos_usb_mux_change(struct platform_device *pdev, int val)
+{
+	u32 is_host;
+	if (soc_is_exynos4212() || soc_is_exynos4412()) {
+		is_host = readl(EXYNOS4_USB_CFG);
+		writel(val, EXYNOS4_USB_CFG);
+	} else {
+		is_host = readl(EXYNOS5_USB_CFG);
+		writel(val, EXYNOS5_USB_CFG);
+	}
+
+	if (is_host != val)
+		dev_dbg(&pdev->dev, "Change USB MUX from %s to %s",
+			is_host ? "Host" : "Device",
+			val ? "Host" : "Device");
+}
+
+static int exynos4_usb_host_phy_is_on(void)
+{
+	return (readl(EXYNOS4_PHYPWR) & PHY1_STD_ANALOG_POWERDOWN) ? 0 : 1;
+}
+
+static int exynos_usb_device_phy_is_on(void)
+{
+	int ret;
+
+	if (soc_is_exynos4210())
+		ret = (readl(EXYNOS4_PHYPWR) & PHY0_ANALOG_POWERDOWN) ? 0 : 1;
+	else if (soc_is_exynos4212() || soc_is_exynos4412())
+		ret = readl(EXYNOS4_USB_CFG) ? 0 : 1;
+	else
+		ret = readl(EXYNOS5_USB_CFG) ? 0 : 1;
+
+	return ret;
+}
+
+static int exynos4_usb_phy20_is_on(void)
+{
+	return exynos4_usb_host_phy_is_on();
+}
+
+static int exynos5_usb_host_phy20_is_on(void)
+{
+	return (readl(EXYNOS5_PHY_HOST_CTRL0) & HOST_CTRL0_SIDDQ) ? 0 : 1;
+}
+
+static int exynos5_usb_phy30_is_on(void)
+{
+	return readl(EXYNOS5_USBDEV_PHY_CONTROL) ? 1 : 0;
+}
+
+static int exynos_usb_phy_clock_enable(struct platform_device *pdev)
+{
+	int err;
+
+	if (!phy_clk) {
+		if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412())
+			phy_clk = clk_get(&pdev->dev, "usbotg");
+		else
+			phy_clk = clk_get(&pdev->dev, "usbhost");
+
+		if (IS_ERR(phy_clk)) {
+			dev_err(&pdev->dev, "Failed to get phy clock\n");
+			return PTR_ERR(phy_clk);
+		}
+	}
+
+	err = clk_enable(phy_clk);
+
+	return err;
+}
+
+static int exynos_usb_phy_clock_disable(struct platform_device *pdev)
+{
+	if (!phy_clk) {
+		if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412())
+			phy_clk = clk_get(&pdev->dev, "usbotg");
+		else
+			phy_clk = clk_get(&pdev->dev, "usbhost");
+		if (IS_ERR(phy_clk)) {
+			dev_err(&pdev->dev, "Failed to get phy clock\n");
+			return PTR_ERR(phy_clk);
+		}
+	}
+
+	clk_disable(phy_clk);
+
+	return 0;
+}
+
+static u32 exynos_usb_phy_set_clock(struct platform_device *pdev)
+{
+	struct clk *ref_clk;
+	u32 refclk_freq = 0;
+
+	if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412())
+		ref_clk = clk_get(&pdev->dev, "xusbxti");
+	else
+		ref_clk = clk_get(&pdev->dev, "ext_xtal");
+
+	if (IS_ERR(ref_clk)) {
+		dev_err(&pdev->dev, "Failed to get reference clock\n");
+		return PTR_ERR(ref_clk);
+	}
+
+	if (soc_is_exynos4210()) {
+		switch (clk_get_rate(ref_clk)) {
+		case 12 * MHZ:
+			refclk_freq = EXYNOS4210_CLKSEL_12M;
+			break;
+		case 48 * MHZ:
+			refclk_freq = EXYNOS4210_CLKSEL_48M;
+			break;
+		case 24 * MHZ:
+		default:
+			/* default reference clock */
+			refclk_freq = EXYNOS4210_CLKSEL_24M;
+			break;
+		}
+	} else if (soc_is_exynos4212() | soc_is_exynos4412()) {
+		switch (clk_get_rate(ref_clk)) {
+		case 96 * 100000:
+			refclk_freq = EXYNOS4212_CLKSEL_9600K;
+			break;
+		case 10 * MHZ:
+			refclk_freq = EXYNOS4212_CLKSEL_10M;
+			break;
+		case 12 * MHZ:
+			refclk_freq = EXYNOS4212_CLKSEL_12M;
+			break;
+		case 192 * 100000:
+			refclk_freq = EXYNOS4212_CLKSEL_19200K;
+			break;
+		case 20 * MHZ:
+			refclk_freq = EXYNOS4212_CLKSEL_20M;
+			break;
+		case 24 * MHZ:
+		default:
+			/* default reference clock */
+			refclk_freq = EXYNOS4212_CLKSEL_24M;
+			break;
+		}
+	} else {
+		switch (clk_get_rate(ref_clk)) {
+		case 96 * 100000:
+			refclk_freq = EXYNOS5_CLKSEL_9600K;
+			break;
+		case 10 * MHZ:
+			refclk_freq = EXYNOS5_CLKSEL_10M;
+			break;
+		case 12 * MHZ:
+			refclk_freq = EXYNOS5_CLKSEL_12M;
+			break;
+		case 192 * 100000:
+			refclk_freq = EXYNOS5_CLKSEL_19200K;
+			break;
+		case 20 * MHZ:
+			refclk_freq = EXYNOS5_CLKSEL_20M;
+			break;
+		case 50 * MHZ:
+			refclk_freq = EXYNOS5_CLKSEL_50M;
+			break;
+		case 24 * MHZ:
+		default:
+			/* default reference clock */
+			refclk_freq = EXYNOS5_CLKSEL_24M;
+			break;
+		}
+	}
+	clk_put(ref_clk);
+
+	return refclk_freq;
+}
+
+static void exynos_usb_phy_control(enum usb_phy_type phy_type , int on)
+{
+	if (soc_is_exynos4210()) {
+		if (phy_type & USB_PHY0)
+			writel(on, S5P_USBOTG_PHY_CONTROL);
+		if (phy_type & USB_PHY1)
+			writel(on, S5P_USBHOST_PHY_CONTROL);
+	} else if (soc_is_exynos4212() | soc_is_exynos4412()) {
+		if (phy_type & USB_PHY)
+			writel(on, S5P_USB_PHY_CONTROL);
+#ifdef CONFIG_USB_S5P_HSIC0
+		if (phy_type & USB_PHY_HSIC0)
+			writel(on, S5P_HSIC_1_PHY_CONTROL);
+#endif
+#ifdef CONFIG_USB_S5P_HSIC1
+		if (phy_type & USB_PHY_HSIC1)
+			writel(on, S5P_HSIC_2_PHY_CONTROL);
+#endif
+	} else {
+		if (phy_type & USB_PHY0)
+			writel(on, EXYNOS5_USBDEV_PHY_CONTROL);
+		if (phy_type & USB_PHY1)
+			writel(on, EXYNOS5_USBHOST_PHY_CONTROL);
+	}
+}
+
+static int exynos4_usb_phy0_init(struct platform_device *pdev)
+{
+	u32 phypwr;
+	u32 phyclk;
+	u32 rstcon;
+
+	exynos_usb_phy_control(USB_PHY0, PHY_ENABLE);
+
+	/* set clock frequency for PLL */
+	phyclk = readl(EXYNOS4_PHYCLK) & ~(EXYNOS4210_CLKSEL_MASK);
+	phyclk |= exynos_usb_phy_set_clock(pdev);
+	phyclk &= ~(PHY0_COMMON_ON_N);
+	writel(phyclk, EXYNOS4_PHYCLK);
+
+	/* set to normal of PHY0 */
+	phypwr = readl(EXYNOS4_PHYPWR) & ~PHY0_NORMAL_MASK;
+	writel(phypwr, EXYNOS4_PHYPWR);
+
+	/* reset all ports of both PHY and Link */
+	rstcon = readl(EXYNOS4_RSTCON) | PHY0_SWRST_MASK;
+	writel(rstcon, EXYNOS4_RSTCON);
+	udelay(10);
+	rstcon &= ~PHY0_SWRST_MASK;
+	writel(rstcon, EXYNOS4_RSTCON);
+
+	return 0;
+}
+
+static int exynos4_usb_phy0_exit(struct platform_device *pdev)
+{
+	/* unset to normal of PHY0 */
+	writel((readl(EXYNOS4_PHYPWR) | PHY0_NORMAL_MASK),
+			EXYNOS4_PHYPWR);
+
+	exynos_usb_phy_control(USB_PHY0, PHY_DISABLE);
+
+	return 0;
+}
+
+static int exynos4_usb_phy1_suspend(struct platform_device *pdev)
+{
+	u32 phypwr;
+
+	/* set to suspend HSIC 0 and 1 and standard of PHY1 */
+	phypwr = readl(EXYNOS4_PHYPWR);
+	if (soc_is_exynos4210()) {
+		phypwr |= (PHY1_STD_FORCE_SUSPEND
+			| EXYNOS4210_HSIC0_FORCE_SUSPEND
+			| EXYNOS4210_HSIC1_FORCE_SUSPEND);
+	} else {
+		phypwr = readl(EXYNOS4_PHYPWR);
+		phypwr |= (PHY1_STD_FORCE_SUSPEND
+			| EXYNOS4212_HSIC0_FORCE_SUSPEND
+			| EXYNOS4212_HSIC1_FORCE_SUSPEND);
+	}
+	writel(phypwr, EXYNOS4_PHYPWR);
+
+	return 0;
+}
+
+static int exynos4_usb_phy1_resume(struct platform_device *pdev)
+{
+	u32 rstcon;
+	u32 phypwr;
+	int err;
+
+#if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB)
+	/* HSIC LPA: reset-resume, let cp know pda active from LPA */
+	/* slave wake at lpa wake ??? */
+	/* 12.04.27 Move start of phy1_resume, If usb cable power on the
+	 * host phy, EHCI resume miss the PDA_ACTVIE, then CP can't send Host
+	 * wakeup Irq */
+	if (!strcmp(pdev->name, "s5p-ehci"))
+		set_hsic_lpa_states(STATE_HSIC_LPA_WAKE);
+#endif
+
+	if (exynos4_usb_host_phy_is_on()) {
+		/* set to resume HSIC 0 and 1 and standard of PHY1 */
+		phypwr = readl(EXYNOS4_PHYPWR);
+		if (soc_is_exynos4210()) {
+			phypwr &= ~(PHY1_STD_FORCE_SUSPEND
+				| EXYNOS4210_HSIC0_FORCE_SUSPEND
+				| EXYNOS4210_HSIC1_FORCE_SUSPEND);
+		} else {
+			phypwr = readl(EXYNOS4_PHYPWR);
+			phypwr &= ~(PHY1_STD_FORCE_SUSPEND
+				| EXYNOS4212_HSIC0_FORCE_SUSPEND
+				| EXYNOS4212_HSIC1_FORCE_SUSPEND);
+		}
+		writel(phypwr, EXYNOS4_PHYPWR);
+		if (usb_phy_control.lpa_entered) {
+			usb_phy_control.lpa_entered = 0;
+			err = 1;
+		} else
+			err = 0;
+	} else {
+		phypwr = readl(EXYNOS4_PHYPWR);
+		/* set to normal HSIC 0 and 1 of PHY1 */
+		if (soc_is_exynos4210()) {
+			writel(PHY_ENABLE, S5P_USBHOST_PHY_CONTROL);
+
+			phypwr &= ~(PHY1_STD_NORMAL_MASK
+				| EXYNOS4210_HSIC0_NORMAL_MASK
+				| EXYNOS4210_HSIC1_NORMAL_MASK);
+			writel(phypwr, EXYNOS4_PHYPWR);
+
+			/* reset all ports of both PHY and Link */
+			rstcon = readl(EXYNOS4_RSTCON)
+				| EXYNOS4210_HOST_LINK_PORT_SWRST_MASK
+				| EXYNOS4210_PHY1_SWRST_MASK;
+			writel(rstcon, EXYNOS4_RSTCON);
+			udelay(10);
+
+			rstcon &= ~(EXYNOS4210_HOST_LINK_PORT_SWRST_MASK
+				| EXYNOS4210_PHY1_SWRST_MASK);
+			writel(rstcon, EXYNOS4_RSTCON);
+		} else {
+			exynos_usb_phy_control(USB_PHY
+				| USB_PHY_HSIC0
+				| USB_PHY_HSIC1,
+				PHY_ENABLE);
+
+			/* set to normal of Device */
+			phypwr = readl(EXYNOS4_PHYPWR) & ~PHY0_NORMAL_MASK;
+			writel(phypwr, EXYNOS4_PHYPWR);
+
+			/* reset both PHY and Link of Device */
+			rstcon = readl(EXYNOS4_RSTCON) | PHY0_SWRST_MASK;
+			writel(rstcon, EXYNOS4_RSTCON);
+			udelay(10);
+			rstcon &= ~PHY0_SWRST_MASK;
+			writel(rstcon, EXYNOS4_RSTCON);
+
+			/* set to normal of Host */
+			phypwr &= ~(PHY1_STD_NORMAL_MASK
+				| EXYNOS4212_HSIC0_NORMAL_MASK
+				| EXYNOS4212_HSIC1_NORMAL_MASK);
+			writel(phypwr, EXYNOS4_PHYPWR);
+
+			/* reset all ports of both PHY and Link */
+			rstcon = readl(EXYNOS4_RSTCON)
+				| EXYNOS4212_HOST_LINK_PORT_SWRST_MASK
+				| EXYNOS4212_PHY1_SWRST_MASK;
+			writel(rstcon, EXYNOS4_RSTCON);
+			udelay(10);
+
+			rstcon &= ~(EXYNOS4212_HOST_LINK_PORT_SWRST_MASK
+				| EXYNOS4212_PHY1_SWRST_MASK);
+			writel(rstcon, EXYNOS4_RSTCON);
+		}
+		usb_phy_control.lpa_entered = 0;
+		err = 1;
+	}
+	udelay(80);
+
+	return err;
+}
+
+static int exynos4_usb_phy1_init(struct platform_device *pdev)
+{
+	u32 phypwr;
+	u32 phyclk;
+	u32 rstcon;
+
+
+	if (!strcmp(pdev->name, "s5p-ehci"))
+		set_bit(HOST_PHY_EHCI, &usb_phy_control.usage);
+	else if (!strcmp(pdev->name, "s5p-ohci"))
+		set_bit(HOST_PHY_OHCI, &usb_phy_control.usage);
+	else if (!strcmp(pdev->name, "s3c-usbgadget"))
+		set_bit(HOST_PHY_DEVICE, &usb_phy_control.usage);
+
+	dev_info(&pdev->dev, "usb phy usage(%ld)\n",usb_phy_control.usage);
+
+	if (exynos4_usb_host_phy_is_on()) {
+		dev_err(&pdev->dev, "Already power on PHY\n");
+		return 0;
+	}
+
+	/*
+	 *  set XuhostOVERCUR to in-active by controlling ET6PUD[15:14]
+	 *  0x0 : pull-up/down disabled
+	 *  0x1 : pull-down enabled
+	 *  0x2 : reserved
+	 *  0x3 : pull-up enabled
+	 */
+	writel((__raw_readl(ETC6PUD) & ~(0x3 << 14)) | (0x3 << 14),
+		ETC6PUD);
+
+	exynos_usb_phy_control(USB_PHY1, PHY_ENABLE);
+
+	/* set clock frequency for PLL */
+	phyclk = readl(EXYNOS4_PHYCLK) & ~(EXYNOS4210_CLKSEL_MASK);
+	phyclk |= exynos_usb_phy_set_clock(pdev);
+#ifdef CONFIG_USB_OHCI_S5P
+	phyclk |= PHY1_COMMON_ON_N;
+#else
+	phyclk &= ~(PHY1_COMMON_ON_N);
+#endif
+	writel(phyclk, EXYNOS4_PHYCLK);
+
+	/* set to normal HSIC 0 and 1 of PHY1 */
+	phypwr = readl(EXYNOS4_PHYPWR);
+	phypwr &= ~(PHY1_STD_NORMAL_MASK
+		| EXYNOS4210_HSIC0_NORMAL_MASK
+		| EXYNOS4210_HSIC1_NORMAL_MASK);
+	writel(phypwr, EXYNOS4_PHYPWR);
+
+	/* floating prevention logic: disable */
+	writel((readl(EXYNOS4_PHY1CON) | FPENABLEN), EXYNOS4_PHY1CON);
+
+	/* reset all ports of both PHY and Link */
+	rstcon = readl(EXYNOS4_RSTCON)
+		| EXYNOS4210_HOST_LINK_PORT_SWRST_MASK
+		| EXYNOS4210_PHY1_SWRST_MASK;
+	writel(rstcon, EXYNOS4_RSTCON);
+	udelay(10);
+
+	rstcon &= ~(EXYNOS4210_HOST_LINK_PORT_SWRST_MASK
+		| EXYNOS4210_PHY1_SWRST_MASK);
+	writel(rstcon, EXYNOS4_RSTCON);
+	udelay(80);
+
+	return 0;
+}
+
+static int exynos4_usb_phy1_exit(struct platform_device *pdev)
+{
+	u32 phypwr;
+
+
+	if (!strcmp(pdev->name, "s5p-ehci"))
+		clear_bit(HOST_PHY_EHCI, &usb_phy_control.usage);
+	else if (!strcmp(pdev->name, "s5p-ohci"))
+		clear_bit(HOST_PHY_OHCI, &usb_phy_control.usage);
+	else if (!strcmp(pdev->name, "s3c-usbgadget"))
+		clear_bit(HOST_PHY_DEVICE, &usb_phy_control.usage);
+
+	if (usb_phy_control.usage) {
+		dev_info(&pdev->dev, "still being used(%ld)\n",usb_phy_control.usage);
+		return -EBUSY;
+	}
+
+	phypwr = readl(EXYNOS4_PHYPWR)
+		| PHY1_STD_NORMAL_MASK
+		| EXYNOS4210_HSIC0_NORMAL_MASK
+		| EXYNOS4210_HSIC1_NORMAL_MASK;
+	writel(phypwr, EXYNOS4_PHYPWR);
+
+	exynos_usb_phy_control(USB_PHY1, PHY_DISABLE);
+
+	return 0;
+}
+
+static int exynos4_usb_phy20_init(struct platform_device *pdev)
+{
+	u32 phypwr, phyclk, rstcon;
+
+	if (!strcmp(pdev->name, "s5p-ehci"))
+		set_bit(HOST_PHY_EHCI, &usb_phy_control.usage);
+	else if (!strcmp(pdev->name, "s5p-ohci"))
+		set_bit(HOST_PHY_OHCI, &usb_phy_control.usage);
+	else if (!strcmp(pdev->name, "s3c-usbgadget"))
+		set_bit(HOST_PHY_DEVICE, &usb_phy_control.usage);
+
+	dev_info(&pdev->dev, "usb phy usage(%ld)\n", usb_phy_control.usage);
+
+	if (exynos4_usb_phy20_is_on()) {
+		dev_err(&pdev->dev, "Already power on PHY\n");
+		return 0;
+	}
+
+	/*
+	 *  set XuhostOVERCUR to in-active by controlling ET6PUD[15:14]
+	 *  0x0 : pull-up/down disabled
+	 *  0x1 : pull-down enabled
+	 *  0x2 : reserved
+	 *  0x3 : pull-up enabled
+	 */
+	writel((__raw_readl(ETC6PUD) & ~(0x3 << 14)) | (0x3 << 14),
+		ETC6PUD);
+
+	exynos_usb_phy_control(USB_PHY
+		| USB_PHY_HSIC0
+		| USB_PHY_HSIC1,
+		PHY_ENABLE);
+
+	/* USB MUX change from Device to Host */
+	exynos_usb_mux_change(pdev, 1);
+
+	/* set clock frequency for PLL */
+	phyclk = exynos_usb_phy_set_clock(pdev);
+	/* COMMON Block configuration during suspend */
+	phyclk &= ~(PHY0_COMMON_ON_N);
+#ifdef CONFIG_USB_OHCI_S5P
+	phyclk |= PHY1_COMMON_ON_N;
+#else
+	phyclk &= ~(PHY1_COMMON_ON_N);
+#endif
+	writel(phyclk, EXYNOS4_PHYCLK);
+
+	/* set to normal of Device */
+	phypwr = readl(EXYNOS4_PHYPWR) & ~PHY0_NORMAL_MASK;
+	writel(phypwr, EXYNOS4_PHYPWR);
+
+	/* set to normal of Host */
+	phypwr = readl(EXYNOS4_PHYPWR);
+	phypwr &= ~(PHY1_STD_NORMAL_MASK
+		| EXYNOS4212_HSIC0_NORMAL_MASK
+		| EXYNOS4212_HSIC1_NORMAL_MASK);
+	writel(phypwr, EXYNOS4_PHYPWR);
+
+	/* reset both PHY and Link of Device */
+	rstcon = readl(EXYNOS4_RSTCON) | PHY0_SWRST_MASK;
+	writel(rstcon, EXYNOS4_RSTCON);
+	udelay(10);
+	rstcon &= ~PHY0_SWRST_MASK;
+	writel(rstcon, EXYNOS4_RSTCON);
+
+	/* reset both PHY and Link of Host */
+	rstcon = readl(EXYNOS4_RSTCON)
+		| EXYNOS4212_HOST_LINK_PORT_SWRST_MASK
+		| EXYNOS4212_PHY1_SWRST_MASK;
+	writel(rstcon, EXYNOS4_RSTCON);
+	udelay(10);
+
+	rstcon &= ~(EXYNOS4212_HOST_LINK_PORT_SWRST_MASK
+		| EXYNOS4212_PHY1_SWRST_MASK);
+	writel(rstcon, EXYNOS4_RSTCON);
+	udelay(80);
+
+	return 0;
+}
+
+static int exynos4_usb_phy20_exit(struct platform_device *pdev)
+{
+	u32 phypwr;
+
+	if (!strcmp(pdev->name, "s5p-ehci"))
+		clear_bit(HOST_PHY_EHCI, &usb_phy_control.usage);
+	else if (!strcmp(pdev->name, "s5p-ohci"))
+		clear_bit(HOST_PHY_OHCI, &usb_phy_control.usage);
+	else if (!strcmp(pdev->name, "s3c-usbgadget"))
+		clear_bit(HOST_PHY_DEVICE, &usb_phy_control.usage);
+
+	if (usb_phy_control.usage) {
+		dev_info(&pdev->dev, "still being used(%ld)\n",
+			usb_phy_control.usage);
+		return -EBUSY;
+	} else
+		dev_info(&pdev->dev, "usb host phy off\n");
+
+	/* unset to normal of Device */
+	writel((readl(EXYNOS4_PHYPWR) | PHY0_NORMAL_MASK),
+			EXYNOS4_PHYPWR);
+
+	/* unset to normal of Host */
+	phypwr = readl(EXYNOS4_PHYPWR)
+		| PHY1_STD_NORMAL_MASK
+		| EXYNOS4212_HSIC0_NORMAL_MASK
+		| EXYNOS4212_HSIC1_NORMAL_MASK;
+	writel(phypwr, EXYNOS4_PHYPWR);
+
+	exynos_usb_phy_control(USB_PHY
+		| USB_PHY_HSIC0
+		| USB_PHY_HSIC1,
+		PHY_DISABLE);
+
+	usb_phy_control.lpa_entered = 0;
+
+	return 0;
+}
+
+static int exynos5_usb_phy_host_suspend(struct platform_device *pdev)
+{
+	u32 hostphy_ctrl0;
+
+	/* set to suspend HSIC 1 and 2 */
+	writel(readl(EXYNOS5_PHY_HSIC_CTRL1) | HSIC_CTRL_FORCESUSPEND,
+		EXYNOS5_PHY_HSIC_CTRL1);
+	writel(readl(EXYNOS5_PHY_HSIC_CTRL2) | HSIC_CTRL_FORCESUSPEND,
+		EXYNOS5_PHY_HSIC_CTRL2);
+
+	hostphy_ctrl0 = readl(EXYNOS5_PHY_HOST_CTRL0);
+	/* set to suspend standard of PHY20 */
+	hostphy_ctrl0 |= HOST_CTRL0_FORCESUSPEND;
+	writel(hostphy_ctrl0, EXYNOS5_PHY_HOST_CTRL0);
+
+	return 0;
+}
+
+static int exynos5_usb_phy_host_resume(struct platform_device *pdev)
+{
+	u32 hostphy_ctrl0, otgphy_sys, hsic_ctrl;
+	int err;
+
+	if (exynos5_usb_host_phy20_is_on()) {
+		/* set to suspend HSIC 0 and 1 and standard of PHY1 */
+		hostphy_ctrl0 = readl(EXYNOS5_PHY_HOST_CTRL0);
+		hostphy_ctrl0 &= ~(HOST_CTRL0_FORCESUSPEND);
+		writel(hostphy_ctrl0, EXYNOS5_PHY_HOST_CTRL0);
+
+		/* set common_on_n of PHY1 for power consumption */
+		hsic_ctrl = readl(EXYNOS5_PHY_HSIC_CTRL1);
+		hsic_ctrl &= ~(HSIC_CTRL_FORCESUSPEND);
+		writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL1);
+		writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL2);
+		if (usb_phy_control.lpa_entered) {
+			usb_phy_control.lpa_entered = 0;
+			err = 1;
+		} else
+			err = 0;
+	} else {
+		exynos_usb_phy_control(USB_PHY1, PHY_ENABLE);
+
+		/* otg phy reset */
+		otgphy_sys = readl(EXYNOS5_PHY_OTG_SYS);
+		otgphy_sys &= ~(OTG_SYS_SIDDQ_UOTG);
+		otgphy_sys |= (OTG_SYS_PHY0_SW_RST |
+				OTG_SYS_LINK_SW_RST_UOTG |
+				OTG_SYS_PHYLINK_SW_RESET);
+		writel(otgphy_sys, EXYNOS5_PHY_OTG_SYS);
+		udelay(10);
+		otgphy_sys &= ~(OTG_SYS_PHY0_SW_RST |
+				OTG_SYS_LINK_SW_RST_UOTG |
+				OTG_SYS_PHYLINK_SW_RESET);
+		writel(otgphy_sys, EXYNOS5_PHY_OTG_SYS);
+
+		/* reset all ports of both PHY and Link */
+		hostphy_ctrl0 = readl(EXYNOS5_PHY_HOST_CTRL0);
+		hostphy_ctrl0 &= ~(HOST_CTRL0_SIDDQ | HOST_CTRL0_FORCESUSPEND);
+		hostphy_ctrl0 |= (HOST_CTRL0_LINKSWRST | HOST_CTRL0_UTMISWRST);
+		writel(hostphy_ctrl0, EXYNOS5_PHY_HOST_CTRL0);
+		udelay(10);
+		hostphy_ctrl0 &= ~(HOST_CTRL0_LINKSWRST | HOST_CTRL0_UTMISWRST);
+		writel(hostphy_ctrl0, EXYNOS5_PHY_HOST_CTRL0);
+
+		/* HSIC phy reset */
+		hsic_ctrl = readl(EXYNOS5_PHY_HSIC_CTRL1);
+		hsic_ctrl &= ~(HSIC_CTRL_SIDDQ | HSIC_CTRL_FORCESUSPEND);
+		hsic_ctrl |= (HSIC_CTRL_PHYSWRST | HSIC_CTRL_UTMISWRST);
+		writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL1);
+		writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL2);
+		udelay(10);
+		hsic_ctrl &= ~(HSIC_CTRL_PHYSWRST | HSIC_CTRL_UTMISWRST);
+		writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL1);
+		writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL2);
+
+		usb_phy_control.lpa_entered = 0;
+		err = 1;
+	}
+	udelay(80);
+
+	return err;
+}
+
+static int exynos5_usb_phy20_init(struct platform_device *pdev)
+{
+	u32 refclk_freq;
+	u32 hostphy_ctrl0, otgphy_sys, hsic_ctrl, ehcictrl, ohcictrl;
+
+	atomic_inc(&host_usage);
+
+	if (exynos5_usb_host_phy20_is_on()) {
+		dev_err(&pdev->dev, "Already power on PHY\n");
+		return 0;
+	}
+
+	exynos_usb_mux_change(pdev, 1);
+
+	exynos_usb_phy_control(USB_PHY1, PHY_ENABLE);
+
+	/* Host and Device should be set at the same time */
+	hostphy_ctrl0 = readl(EXYNOS5_PHY_HOST_CTRL0);
+	hostphy_ctrl0 &= ~(HOST_CTRL0_FSEL_MASK);
+	otgphy_sys = readl(EXYNOS5_PHY_OTG_SYS);
+	otgphy_sys &= ~(OTG_SYS_CTRL0_FSEL_MASK);
+
+	/* 2.0 phy reference clock configuration */
+	refclk_freq = exynos_usb_phy_set_clock(pdev);
+	hostphy_ctrl0 |= (refclk_freq << HOST_CTRL0_CLKSEL_SHIFT);
+	otgphy_sys |= (refclk_freq << OTG_SYS_CLKSEL_SHIFT);
+
+	/* COMMON Block configuration during suspend */
+	hostphy_ctrl0 |= HOST_CTRL0_COMMONON_N;
+	otgphy_sys &= ~(OTG_SYS_COMMON_ON);
+
+	/* otg phy reset */
+	otgphy_sys &= ~(OTG_SYS_FORCE_SUSPEND | OTG_SYS_SIDDQ_UOTG | OTG_SYS_FORCE_SLEEP);
+	otgphy_sys &= ~(OTG_SYS_REF_CLK_SEL_MASK);
+	otgphy_sys |= (OTG_SYS_REF_CLK_SEL(0x2) | OTG_SYS_OTGDISABLE);
+	otgphy_sys |= (OTG_SYS_PHY0_SW_RST | OTG_SYS_LINK_SW_RST_UOTG | OTG_SYS_PHYLINK_SW_RESET);
+	writel(otgphy_sys, EXYNOS5_PHY_OTG_SYS);
+	udelay(10);
+	otgphy_sys &= ~(OTG_SYS_PHY0_SW_RST | OTG_SYS_LINK_SW_RST_UOTG | OTG_SYS_PHYLINK_SW_RESET);
+	writel(otgphy_sys, EXYNOS5_PHY_OTG_SYS);
+
+	/* host phy reset */
+	hostphy_ctrl0 &= ~(HOST_CTRL0_PHYSWRST | HOST_CTRL0_PHYSWRSTALL | HOST_CTRL0_SIDDQ);
+	hostphy_ctrl0 &= ~(HOST_CTRL0_FORCESUSPEND | HOST_CTRL0_FORCESLEEP);
+	hostphy_ctrl0 |= (HOST_CTRL0_LINKSWRST | HOST_CTRL0_UTMISWRST);
+	writel(hostphy_ctrl0, EXYNOS5_PHY_HOST_CTRL0);
+	udelay(10);
+	hostphy_ctrl0 &= ~(HOST_CTRL0_LINKSWRST | HOST_CTRL0_UTMISWRST);
+	writel(hostphy_ctrl0, EXYNOS5_PHY_HOST_CTRL0);
+
+	/* HSIC phy reset */
+	hsic_ctrl = (HSIC_CTRL_REFCLKDIV(0x24) | HSIC_CTRL_REFCLKSEL(0x2) |
+		HSIC_CTRL_PHYSWRST);
+	writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL1);
+	writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL2);
+	udelay(10);
+	hsic_ctrl &= ~(HSIC_CTRL_PHYSWRST);
+	writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL1);
+	writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL2);
+
+	udelay(80);
+	/* enable EHCI DMA burst  */
+	ehcictrl = readl(EXYNOS5_PHY_HOST_EHCICTRL);
+	ehcictrl |= (EHCICTRL_ENAINCRXALIGN | EHCICTRL_ENAINCR4 |
+			EHCICTRL_ENAINCR8 | EHCICTRL_ENAINCR16);
+	writel(ehcictrl, EXYNOS5_PHY_HOST_EHCICTRL);
+	/* set ohci_suspend_on_n */
+	ohcictrl = readl(EXYNOS5_PHY_HOST_OHCICTRL);
+	ohcictrl |= OHCICTRL_SUSPLGCY;
+	writel(ohcictrl, EXYNOS5_PHY_HOST_OHCICTRL);
+	return 0;
+}
+
+static int exynos5_usb_phy20_exit(struct platform_device *pdev)
+{
+	u32 hostphy_ctrl0, otgphy_sys, hsic_ctrl;
+
+	if (atomic_dec_return(&host_usage) > 0) {
+		dev_info(&pdev->dev, "still being used\n");
+		return -EBUSY;
+	}
+
+	hsic_ctrl = (HSIC_CTRL_REFCLKDIV(0x24) | HSIC_CTRL_REFCLKSEL(0x2) |
+			HSIC_CTRL_SIDDQ | HSIC_CTRL_FORCESLEEP | HSIC_CTRL_FORCESUSPEND);
+	writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL1);
+	writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL2);
+
+	hostphy_ctrl0 = readl(EXYNOS5_PHY_HOST_CTRL0);
+	hostphy_ctrl0 |= (HOST_CTRL0_SIDDQ);
+	hostphy_ctrl0 |= (HOST_CTRL0_FORCESUSPEND | HOST_CTRL0_FORCESLEEP);
+	hostphy_ctrl0 |= (HOST_CTRL0_PHYSWRST | HOST_CTRL0_PHYSWRSTALL);
+	writel(hostphy_ctrl0, EXYNOS5_PHY_HOST_CTRL0);
+
+	otgphy_sys = readl(EXYNOS5_PHY_OTG_SYS);
+	otgphy_sys |= (OTG_SYS_FORCE_SUSPEND | OTG_SYS_SIDDQ_UOTG | OTG_SYS_FORCE_SLEEP);
+	writel(otgphy_sys, EXYNOS5_PHY_OTG_SYS);
+
+	exynos_usb_phy_control(USB_PHY1, PHY_DISABLE);
+
+	return 0;
+}
+
+static int exynos_usb_dev_phy20_init(struct platform_device *pdev)
+{
+	if (soc_is_exynos4212() || soc_is_exynos4412()) {
+		exynos4_usb_phy20_init(pdev);
+		if (usb_phy_control.lpa_entered)
+			exynos4_usb_phy1_suspend(pdev);
+	} else {
+		exynos5_usb_phy20_init(pdev);
+		if (usb_phy_control.lpa_entered)
+			exynos5_usb_phy_host_suspend(pdev);
+	}
+
+	exynos_usb_mux_change(pdev, 0);
+
+	return 0;
+}
+
+static int exynos_usb_dev_phy20_exit(struct platform_device *pdev)
+{
+	if (soc_is_exynos4212() || soc_is_exynos4412())
+		exynos4_usb_phy20_exit(pdev);
+	else
+		exynos5_usb_phy20_exit(pdev);
+
+	exynos_usb_mux_change(pdev, 1);
+
+	return 0;
+}
+
+static int __maybe_unused exynos_usb_hsic_init(struct platform_device *pdev)
+{
+	u32 rstcon, hsic_ctrl;
+
+	if (soc_is_exynos4212() || soc_is_exynos4412()) {
+		exynos_usb_phy_control(USB_PHY_HSIC0
+			| USB_PHY_HSIC1,
+			PHY_ENABLE);
+
+		/* reset both PHY and Link of Host */
+		rstcon = readl(EXYNOS4_RSTCON)
+			| EXYNOS4212_PHY1_HSIC0_SWRST
+			| EXYNOS4212_PHY1_HSIC1_SWRST;
+		writel(rstcon, EXYNOS4_RSTCON);
+		udelay(10);
+
+		rstcon &= ~(EXYNOS4212_PHY1_HSIC0_SWRST
+			| EXYNOS4212_PHY1_HSIC1_SWRST);
+		writel(rstcon, EXYNOS4_RSTCON);
+	} else {
+		/* HSIC phy reset */
+		hsic_ctrl = (HSIC_CTRL_REFCLKDIV(0x24) | HSIC_CTRL_REFCLKSEL(0x2) |
+			HSIC_CTRL_PHYSWRST);
+		writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL1);
+		writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL2);
+		udelay(10);
+		hsic_ctrl &= ~(HSIC_CTRL_PHYSWRST);
+		writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL1);
+		writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL2);
+	}
+
+	return 0;
+}
+
+static int __maybe_unused exynos_usb_hsic_exit(struct platform_device *pdev)
+{
+	u32 hsic_ctrl;
+
+	if (soc_is_exynos4212() || soc_is_exynos4412()) {
+		exynos_usb_phy_control(USB_PHY_HSIC0
+			| USB_PHY_HSIC1,
+			PHY_DISABLE);
+	} else {
+		hsic_ctrl = (HSIC_CTRL_REFCLKDIV(0x24) | HSIC_CTRL_REFCLKSEL(0x2) |
+				HSIC_CTRL_SIDDQ | HSIC_CTRL_FORCESLEEP | HSIC_CTRL_FORCESUSPEND);
+		writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL1);
+		writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL2);
+	}
+
+	return 0;
+}
+
+static int exynos5_usb_phy30_init(struct platform_device *pdev)
+{
+	u32 reg;
+	bool use_ext_clk = true;
+
+	exynos_usb_phy_control(USB_PHY0, PHY_ENABLE);
+
+	/* Reset USB 3.0 PHY */
+	writel(0x00000000, EXYNOS_USB3_PHYREG0);
+	writel(0x24d4e6e4, EXYNOS_USB3_PHYPARAM0);
+	writel(0x03fff820, EXYNOS_USB3_PHYPARAM1);
+	writel(0x00000000, EXYNOS_USB3_PHYRESUME);
+
+	if (soc_is_exynos5250() && samsung_rev() < EXYNOS5250_REV_1_0) {
+		writel(0x087fffc0, EXYNOS_USB3_LINKSYSTEM);
+		writel(0x00000000, EXYNOS_USB3_PHYBATCHG);
+		/* Over-current pin is inactive on SMDK5250 rev 0.0 */
+		writel((readl(EXYNOS_USB3_LINKPORT) & ~(0x3<<4)) |
+			(0x3<<2), EXYNOS_USB3_LINKPORT);
+	} else {
+		writel(0x08000000, EXYNOS_USB3_LINKSYSTEM);
+		writel(0x00000004, EXYNOS_USB3_PHYBATCHG);
+#ifdef CONFIG_USB_EXYNOS_SWITCH
+		writel(readl(EXYNOS_USB3_LINKPORT) |
+			(0xf<<2), EXYNOS_USB3_LINKPORT);
+#endif
+		/* REVISIT :use externel clock 100MHz */
+		if (use_ext_clk)
+			writel(readl(EXYNOS_USB3_PHYPARAM0) | (0x1<<31),
+				EXYNOS_USB3_PHYPARAM0);
+		else
+			writel(readl(EXYNOS_USB3_PHYPARAM0) & ~(0x1<<31),
+				EXYNOS_USB3_PHYPARAM0);
+	}
+
+	/* UTMI Power Control */
+	writel(EXYNOS_USB3_PHYUTMI_OTGDISABLE, EXYNOS_USB3_PHYUTMI);
+
+	/* Set 100MHz external clock */
+	reg = EXYNOS_USB3_PHYCLKRST_PORTRESET |
+		/* HS PLL uses ref_pad_clk{p,m} or ref_alt_clk_{p,m}
+		* as reference */
+		EXYNOS_USB3_PHYCLKRST_REFCLKSEL(2) |
+		/* Digital power supply in normal operating mode */
+		EXYNOS_USB3_PHYCLKRST_RETENABLEN |
+		/* 0x27-100MHz, 0x2a-24MHz, 0x31-20MHz, 0x38-19.2MHz */
+		EXYNOS_USB3_PHYCLKRST_FSEL(0x27) |
+		/* 0x19-100MHz, 0x68-24MHz, 0x7d-20Mhz */
+		EXYNOS_USB3_PHYCLKRST_MPLL_MULTIPLIER(0x19) |
+		/* Enable ref clock for SS function */
+		EXYNOS_USB3_PHYCLKRST_REF_SSP_EN |
+		/* Enable spread spectrum */
+		EXYNOS_USB3_PHYCLKRST_SSC_EN;
+
+	if (!(soc_is_exynos5250() && samsung_rev() < EXYNOS5250_REV_1_0))
+		reg |= EXYNOS_USB3_PHYCLKRST_COMMONONN;
+
+	writel(reg, EXYNOS_USB3_PHYCLKRST);
+
+	udelay(10);
+
+	reg &= ~(EXYNOS_USB3_PHYCLKRST_PORTRESET);
+	writel(reg, EXYNOS_USB3_PHYCLKRST);
+
+	return 0;
+}
+
+static int exynos5_usb_phy30_exit(struct platform_device *pdev)
+{
+	u32 reg;
+
+	reg = EXYNOS_USB3_PHYUTMI_OTGDISABLE |
+		EXYNOS_USB3_PHYUTMI_FORCESUSPEND |
+		EXYNOS_USB3_PHYUTMI_FORCESLEEP;
+	writel(reg, EXYNOS_USB3_PHYUTMI);
+
+	exynos_usb_phy_control(USB_PHY0, PHY_DISABLE);
+
+	return 0;
+}
+
+int exynos4_check_usb_op(void)
+{
+	u32 phypwr;
+	u32 op = 1;
+	unsigned long flags;
+	int ret;
+
+	ret = clk_enable(phy_clk);
+	if (ret)
+		return 0;
+
+	local_irq_save(flags);
+	phypwr = readl(EXYNOS4_PHYPWR);
+
+	/*If USB Device is power on,  */
+	if (exynos_usb_device_phy_is_on()) {
+		op = 1;
+		goto done;
+	} else if (!exynos4_usb_host_phy_is_on()) {
+		op = 0;
+		goto done;
+	}
+
+	/*If USB Device & Host is suspended,  */
+	if (soc_is_exynos4210()) {
+		if (phypwr & (PHY1_STD_FORCE_SUSPEND
+			| EXYNOS4210_HSIC0_FORCE_SUSPEND
+			| EXYNOS4210_HSIC1_FORCE_SUSPEND)) {
+#if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB)
+			/* HSIC LPA: LPA USB phy retention reume call the usb
+			* reset resume, so we should let CP to HSIC L3 mode. */
+			set_hsic_lpa_states(STATE_HSIC_LPA_ENTER);
+#endif
+			writel(readl(EXYNOS4_PHYPWR)
+				| PHY1_STD_ANALOG_POWERDOWN,
+				EXYNOS4_PHYPWR);
+			writel(PHY_DISABLE, S5P_USBHOST_PHY_CONTROL);
+
+			op = 0;
+		}
+	} else {
+		if (phypwr & (PHY1_STD_FORCE_SUSPEND
+			| EXYNOS4212_HSIC0_FORCE_SUSPEND
+			| EXYNOS4212_HSIC1_FORCE_SUSPEND)) {
+#if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB)
+			/* HSIC LPA: LPA USB phy retention reume call the usb
+			* reset resume, so we should let CP to HSIC L3 mode. */
+			set_hsic_lpa_states(STATE_HSIC_LPA_ENTER);
+#endif
+			/* unset to normal of Host */
+			writel(readl(EXYNOS4_PHYPWR)
+				| PHY1_STD_ANALOG_POWERDOWN
+				| EXYNOS4212_HSIC0_ANALOG_POWERDOWN
+				| EXYNOS4212_HSIC1_ANALOG_POWERDOWN,
+				EXYNOS4_PHYPWR);
+			/* unset to normal of Device */
+			writel((readl(EXYNOS4_PHYPWR) | PHY0_NORMAL_MASK),
+					EXYNOS4_PHYPWR);
+
+			exynos_usb_phy_control(USB_PHY
+				| USB_PHY_HSIC0
+				| USB_PHY_HSIC1,
+				PHY_DISABLE);
+
+			op = 0;
+			usb_phy_control.lpa_entered = 1;
+		}
+	}
+done:
+	local_irq_restore(flags);
+	clk_disable(phy_clk);
+
+	return op;
+}
+
+static int exynos5_check_usb_op(void)
+{
+	u32 hostphy_ctrl0, otgphy_sys;
+	u32 op = 1;
+	unsigned long flags;
+	int ret;
+
+	ret = clk_enable(phy_clk);
+	if (ret)
+		return 0;
+
+	local_irq_save(flags);
+	/* Check USB 3.0 DRD power */
+	if (exynos5_usb_phy30_is_on()) {
+		op = 1;
+		goto done;
+	}
+	/*If USB Device is power on,  */
+	if (exynos_usb_device_phy_is_on()) {
+		op = 1;
+		goto done;
+	} else if (!exynos5_usb_host_phy20_is_on()) {
+		op = 0;
+		goto done;
+	}
+
+	hostphy_ctrl0 = readl(EXYNOS5_PHY_HOST_CTRL0);
+
+	if (hostphy_ctrl0 & HOST_CTRL0_FORCESUSPEND) {
+		/* unset to normal of Host */
+		hostphy_ctrl0 |= (HOST_CTRL0_SIDDQ);
+		writel(hostphy_ctrl0, EXYNOS5_PHY_HOST_CTRL0);
+
+		/* unset to normal of Device */
+		otgphy_sys = readl(EXYNOS5_PHY_OTG_SYS);
+		otgphy_sys |= OTG_SYS_SIDDQ_UOTG;
+		writel(otgphy_sys, EXYNOS5_PHY_OTG_SYS);
+
+		exynos_usb_phy_control(USB_PHY1,
+			PHY_DISABLE);
+
+		op = 0;
+		usb_phy_control.lpa_entered = 1;
+	}
+done:
+	local_irq_restore(flags);
+	clk_disable(phy_clk);
+
+	return op;
+}
+
+/**
+ * exynos_check_usb_op - Check usb operation
+ *
+ * USB operation is checked for AP Power mode.
+ * NOTE: Should be checked before Entering AP power mode.
+ * exynos4 - USB Host & Device
+ * exynos5 - USB Host & Device & DRD
+ *
+ * return 1 : operation, 0 : stop.
+ */
+int exynos_check_usb_op(void)
+{
+	if (soc_is_exynos4210() ||
+	    soc_is_exynos4212() ||
+	    soc_is_exynos4412())
+		return exynos4_check_usb_op();
+	else
+		return exynos5_check_usb_op();
+}
+
+int s5p_usb_phy_suspend(struct platform_device *pdev, int type)
+{
+	int ret = 0;
+#ifdef CONFIG_USB_OHCI_S5P
+	struct s5p_ohci_hcd *s5p_ohci = platform_get_drvdata(&s5p_device_ohci);
+	struct usb_hcd *ohci_hcd = s5p_ohci->hcd;
+	u32 phyclk;
+#endif
+
+	if (exynos_usb_phy_clock_enable(pdev))
+		return 0;
+
+	mutex_lock(&phy_lock);
+
+	if (!strcmp(pdev->name, "s5p-ehci"))
+		clear_bit(HOST_PHY_EHCI, &usb_phy_control.flags);
+	else if (!strcmp(pdev->name, "s5p-ohci"))
+		clear_bit(HOST_PHY_OHCI, &usb_phy_control.flags);
+
+	if (usb_phy_control.flags)
+		goto done;
+
+	if (type == S5P_USB_PHY_HOST) {
+		if (soc_is_exynos4210() ||
+			soc_is_exynos4212() ||
+			soc_is_exynos4412()) {
+#ifdef CONFIG_USB_OHCI_S5P
+			/* Set OHCI clock off when ohci_hcd is suspended */
+			if (ohci_hcd->state == HC_STATE_SUSPENDED) {
+				phyclk = readl(EXYNOS4_PHYCLK);
+				phyclk &= ~(PHY1_COMMON_ON_N);
+				writel(phyclk, EXYNOS4_PHYCLK);
+			}
+			dev_info(&pdev->dev, "host_phy_susp:%d\n",
+					ohci_hcd->state);
+#endif
+			ret = exynos4_usb_phy1_suspend(pdev);
+		} else
+			ret = exynos5_usb_phy_host_suspend(pdev);
+	}
+done:
+	mutex_unlock(&phy_lock);
+	exynos_usb_phy_clock_disable(pdev);
+
+	return ret;
+}
+
+int s5p_usb_phy_resume(struct platform_device *pdev, int type)
+{
+	int ret = 0;
+	u32 phyclk;
+
+	if (exynos_usb_phy_clock_enable(pdev))
+		return 0;
+
+	mutex_lock(&phy_lock);
+
+	if (usb_phy_control.flags)
+		goto done;
+
+	if (type == S5P_USB_PHY_HOST) {
+		if (soc_is_exynos4210() ||
+			soc_is_exynos4212() ||
+			soc_is_exynos4412()) {
+			dev_info(&pdev->dev, "host_phy_resume\n");
+#ifdef CONFIG_USB_OHCI_S5P
+			phyclk = readl(EXYNOS4_PHYCLK);
+			phyclk |= PHY1_COMMON_ON_N;
+			writel(phyclk, EXYNOS4_PHYCLK);
+#endif
+			ret = exynos4_usb_phy1_resume(pdev);
+		} else
+			ret = exynos5_usb_phy_host_resume(pdev);
+	}
+done:
+	if (!strcmp(pdev->name, "s5p-ehci"))
+		set_bit(HOST_PHY_EHCI, &usb_phy_control.flags);
+	else if (!strcmp(pdev->name, "s5p-ohci"))
+		set_bit(HOST_PHY_OHCI, &usb_phy_control.flags);
+
+	mutex_unlock(&phy_lock);
+	exynos_usb_phy_clock_disable(pdev);
+
+	return ret;
+}
+
+int s5p_usb_phy0_tune(struct s5p_usbgadget_platdata *pdata, int def_mode)
+{
+	u32 phytune;
+	static u32 def_phytune;
+
+	if (!pdata)
+		return -1;
+
+	printk(KERN_DEBUG "usb: %s read original tune\n", __func__);
+	phytune = readl(PHY0_PHYTUNE);
+	if (!def_phytune) {
+		def_phytune = phytune;
+		printk(KERN_DEBUG "usb: %s save default phytune (0x%x)\n",
+				__func__, def_phytune);
+	}
+
+	printk(KERN_DEBUG "usb: %s original tune=0x%x\n",
+			__func__, phytune);
+	printk(KERN_DEBUG "usb: %s tune_mask=0x%x, tune=0x%x\n",
+			__func__, pdata->phy_tune_mask, pdata->phy_tune);
+
+	if (pdata->phy_tune_mask) {
+		phytune &= ~(pdata->phy_tune_mask);
+		phytune |= pdata->phy_tune;
+		udelay(10);
+		if (def_mode) {
+			printk(KERN_DEBUG "usb: %s set defult tune=0x%x\n",
+					__func__, def_phytune);
+			writel(def_phytune, PHY0_PHYTUNE);
+
+		} else {
+			printk(KERN_DEBUG "usb: %s custom tune=0x%x\n",
+				__func__, phytune);
+			writel(phytune, PHY0_PHYTUNE);
+		}
+		phytune = readl(PHY0_PHYTUNE);
+		printk(KERN_DEBUG "usb: %s modified tune=0x%x\n",
+				__func__, phytune);
+	} else
+		printk(KERN_DEBUG "usb: %s default tune\n", __func__);
+
+	return 0;
+}
+
+void set_exynos_usb_phy_tune(int type)
+{
+	u32 phytune;
+	if (soc_is_exynos4412()) {
+		if (type == S5P_USB_PHY_DEVICE) {
+			phytune = readl(PHY0_PHYTUNE);
+			printk(KERN_DEBUG "usb: %s old phy0 tune=0x%x t=%d\n",
+					__func__, phytune, type);
+			/* sqrxtune [13:11] 3b110 : -15% */
+			phytune &= ~(0x7 << 11);
+			phytune |= (0x6 << 11);
+			udelay(10);
+			writel(phytune, PHY0_PHYTUNE);
+			phytune = readl(PHY0_PHYTUNE);
+			printk(KERN_DEBUG "usb: %s new phy0 tune=0x%x\n",
+					__func__, phytune);
+		} else if (type == S5P_USB_PHY_HOST) {
+			phytune = readl(PHY1_PHYTUNE);
+			printk(KERN_DEBUG "usb: %s old phy1 tune=0x%x t=%d\n",
+					__func__, phytune, type);
+			/* sqrxtune [13:11] 3b110 : -15% */
+			phytune &= ~(0x7 << 11);
+			phytune |= (0x6 << 11);
+			udelay(10);
+			writel(phytune, PHY1_PHYTUNE);
+			phytune = readl(PHY1_PHYTUNE);
+			printk(KERN_DEBUG "usb: %s new phy1 tune=0x%x\n",
+					__func__, phytune);
+		}
+	} else
+		printk(KERN_DEBUG "usb: %s it is not exynos4412.(t=%d)\n",
+				__func__, type);
+}
+
+int s5p_usb_phy_init(struct platform_device *pdev, int type)
+{
+	int ret = -EINVAL;
+
+	if (exynos_usb_phy_clock_enable(pdev))
+		return ret;
+
+	mutex_lock(&phy_lock);
+
+	if (type == S5P_USB_PHY_HOST) {
+		if (!strcmp(pdev->name, "s5p-ehci"))
+			set_bit(HOST_PHY_EHCI, &usb_phy_control.flags);
+		else if (!strcmp(pdev->name, "s5p-ohci"))
+			set_bit(HOST_PHY_OHCI, &usb_phy_control.flags);
+
+#if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB)
+		/* HSIC LPA: Let CP know the slave wakeup from LPA wakeup */
+		if (!strcmp(pdev->name, "s5p-ehci"))
+			set_hsic_lpa_states(STATE_HSIC_LPA_PHY_INIT);
+#endif
+		if (soc_is_exynos4210())
+			ret = exynos4_usb_phy1_init(pdev);
+		else if (soc_is_exynos4212() || soc_is_exynos4412()) {
+			ret = exynos4_usb_phy20_init(pdev);
+			set_exynos_usb_phy_tune(type);
+		} else
+			ret = exynos5_usb_phy20_init(pdev);
+	} else if (type == S5P_USB_PHY_DEVICE) {
+		if (soc_is_exynos4210())
+			ret = exynos4_usb_phy0_init(pdev);
+		else {
+			ret = exynos_usb_dev_phy20_init(pdev);
+			set_exynos_usb_phy_tune(type);
+		}
+		/* set custom usb phy tune */
+		if (pdev->dev.platform_data)
+			ret = s5p_usb_phy0_tune(pdev->dev.platform_data, 0);
+	} else if (type == S5P_USB_PHY_OTGHOST) {
+		if (soc_is_exynos4210())
+			ret = exynos4_usb_phy0_init(pdev);
+		else
+			ret = exynos_usb_dev_phy20_init(pdev);
+	} else if (type == S5P_USB_PHY_DRD)
+		ret = exynos5_usb_phy30_init(pdev);
+
+	mutex_unlock(&phy_lock);
+	exynos_usb_phy_clock_disable(pdev);
+
+	return ret;
+}
+
+int s5p_usb_phy_exit(struct platform_device *pdev, int type)
+{
+	int ret = -EINVAL;
+
+	if (exynos_usb_phy_clock_enable(pdev))
+		return ret;
+
+	mutex_lock(&phy_lock);
+
+	if (type == S5P_USB_PHY_HOST) {
+		if (soc_is_exynos4210())
+			ret = exynos4_usb_phy1_exit(pdev);
+		else if (soc_is_exynos4212() || soc_is_exynos4412())
+			ret = exynos4_usb_phy20_exit(pdev);
+		else
+			ret = exynos5_usb_phy20_exit(pdev);
+
+		if (!strcmp(pdev->name, "s5p-ehci"))
+			clear_bit(HOST_PHY_EHCI, &usb_phy_control.flags);
+		else if (!strcmp(pdev->name, "s5p-ohci"))
+			clear_bit(HOST_PHY_OHCI, &usb_phy_control.flags);
+	} else if (type == S5P_USB_PHY_DEVICE) {
+		/* set default usb phy tune */
+		if (pdev->dev.platform_data && soc_is_exynos4210())
+			ret = s5p_usb_phy0_tune(pdev->dev.platform_data, 1);
+		if (soc_is_exynos4210())
+			ret = exynos4_usb_phy0_exit(pdev);
+		else
+			ret = exynos_usb_dev_phy20_exit(pdev);
+	} else if (type == S5P_USB_PHY_DRD)
+		ret = exynos5_usb_phy30_exit(pdev);
+	else if (type == S5P_USB_PHY_OTGHOST) {
+		if (soc_is_exynos4210())
+			ret = exynos4_usb_phy0_exit(pdev);
+		else
+			ret = exynos_usb_dev_phy20_exit(pdev);
+	}
+
+	mutex_unlock(&phy_lock);
+	exynos_usb_phy_clock_disable(pdev);
+
+	return ret;
+}
diff --git a/arch/arm/mach-exynos/sleep-exynos4.S b/arch/arm/mach-exynos/sleep-exynos4.S
new file mode 100644
index 0000000..d5c2aa0
--- /dev/null
+++ b/arch/arm/mach-exynos/sleep-exynos4.S
@@ -0,0 +1,120 @@
+/* linux/arch/arm/mach-exynos/sleep-exynos4.S
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS4210 power Manager (Suspend-To-RAM) support
+ * Based on S3C2410 sleep code by:
+ *	Ben Dooks, (c) 2004 Simtec Electronics
+ *
+ * Based on PXA/SA1100 sleep code by:
+ *	Nicolas Pitre, (c) 2002 Monta Vista Software Inc
+ *	Cliff Brake, (c) 2001
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/memory.h>
+#include <mach/smc.h>
+
+	.text
+
+	/*
+	 * s3c_cpu_save
+	 *
+	 * entry:
+	 *	r1 = v:p offset
+	 */
+
+ENTRY(s3c_cpu_save)
+
+	stmfd	sp!, { r3 - r12, lr }
+
+	adr	r0, sleep_save_misc
+
+	mrc	p15, 0, r2, c15, c0, 0	@ read power control register
+	str	r2, [r0], #4
+
+	mrc	p15, 0, r2, c15, c0, 1	@ read diagnostic register
+	str	r2, [r0], #4
+
+	ldr	r3, =resume_with_mmu
+	bl	cpu_suspend
+
+	bl	exynos4_cpu_suspend
+
+	/* Restore original sp */
+	mov	r0, sp
+	add	r0, r0, #4
+	ldr	sp, [r0]
+
+	mov	r0, #0
+	b	early_wakeup
+
+resume_with_mmu:
+
+	adr	r0, sleep_save_misc
+
+#ifdef CONFIG_ARM_TRUSTZONE
+	ldr	r1, [r0], #4
+	ldr	r2, [r0], #4
+
+	ldr	r0, =SMC_CMD_C15RESUME
+	mov	r3, #0
+#ifdef REQUIRES_SEC
+	.arch_extension sec
+#endif
+	smc	0
+#else
+	ldr	r1, [r0], #4
+	mcr	p15, 0, r1, c15, c0, 0	@ write power control register
+
+	ldr	r1, [r0], #4
+	mcr	p15, 0, r1, c15, c0, 1	@ write diagnostic register
+#endif
+
+	mov	r0, #1
+early_wakeup:
+
+	ldmfd	sp!, { r3 - r12, pc }
+
+	.ltorg
+
+	/*
+	 * sleep magic, to allow the bootloader to check for an valid
+	 * image to resume to. Must be the first word before the
+	 * s3c_cpu_resume entry.
+	 */
+
+	.word	0x2bedf00d
+
+sleep_save_misc:
+	.long	0
+	.long	0
+
+	/*
+	 * s3c_cpu_resume
+	 *
+	 * resume code entry for bootloader to call
+	 *
+	 * we must put this code here in the data segment as we have no
+	 * other way of restoring the stack pointer after sleep, and we
+	 * must not write to the code segment (code is read-only)
+	 */
+
+ENTRY(s3c_cpu_resume)
+	b	cpu_resume
diff --git a/arch/arm/mach-exynos/sleep-exynos5.S b/arch/arm/mach-exynos/sleep-exynos5.S
new file mode 100644
index 0000000..36b50c1
--- /dev/null
+++ b/arch/arm/mach-exynos/sleep-exynos5.S
@@ -0,0 +1,137 @@
+/* linux/arch/arm/mach-exynos/sleep-exynos5.S
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS5 power Manager (Suspend-To-RAM) support
+ * Based on S3C2410 sleep code by:
+ *	Ben Dooks, (c) 2004 Simtec Electronics
+ *
+ * Based on PXA/SA1100 sleep code by:
+ *	Nicolas Pitre, (c) 2002 Monta Vista Software Inc
+ *	Cliff Brake, (c) 2001
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/memory.h>
+#include <mach/smc.h>
+
+	.text
+
+	/*
+	 * s3c_cpu_save
+	 *
+	 * entry:
+	 *	r1 = v:p offset
+	 */
+
+ENTRY(s3c_cpu_save)
+
+	stmfd	sp!, { r3 - r12, lr }
+
+	adr	r0, sleep_save_misc
+
+#ifdef CONFIG_ARM_TRUSTZONE
+	mrc	p15, 0, r2, c1, c0, 1	@ read aux control register
+	str	r2, [r0], #4
+#endif
+	mrc	p15, 1, r2, c9, c0, 2	@ read l2 control register
+	str	r2, [r0], #4
+	mrc	p15, 1, r2, c15, c0, 3	@ read l2 prefetch register
+	str	r2, [r0], #4
+
+	ldr	r3, =resume_with_mmu
+	bl	cpu_suspend
+
+	bl	exynos5_cpu_suspend
+
+	/* Restore original sp */
+	mov	r0, sp
+	add	r0, r0, #4
+	ldr	sp, [r0]
+
+	mov	r0, #0
+	b	early_wakeup
+
+resume_with_mmu:
+
+	adr	r4, sleep_save_misc
+
+#ifdef CONFIG_ARM_TRUSTZONE
+        mov	r3, #0
+
+	ldr	r0, =SMC_CMD_REG
+	ldr	r1, =SMC_REG_ID_CP15(1, 0, 0, 1)	@ aux control register
+	ldr	r2, [r4], #4
+	smc	0
+	ldr	r0, =SMC_CMD_REG
+	ldr	r1, =SMC_REG_ID_CP15(9, 1, 0, 2)	@ L2 control register
+	ldr	r2, [r4], #4
+	smc	0
+	ldr	r0, =SMC_CMD_REG
+	ldr	r1, =SMC_REG_ID_CP15(15, 1, 0, 3)	@ L2 prefetch register
+	ldr	r2, [r4], #4
+	smc	0
+#else
+	ldr	r2, [r4], #4
+	mcr	p15, 1, r2, c9, c0, 2			@ L2 control register
+	ldr	r2, [r4], #4
+	mcr	p15, 1, r2, c15, c0, 3			@ L2 prefetch register
+#endif
+	mov	r0, #1
+early_wakeup:
+
+	ldmfd	sp!, { r3 - r12, pc }
+
+	.ltorg
+
+	/*
+	 * sleep magic, to allow the bootloader to check for an valid
+	 * image to resume to. Must be the first word before the
+	 * s3c_cpu_resume entry.
+	 */
+
+	.word	0x2bedf00d
+
+sleep_save_misc:
+	.long	0
+	.long	0
+	.long	0
+
+	/*
+	 * s3c_cpu_resume
+	 *
+	 * resume code entry for bootloader to call
+	 *
+	 * we must put this code here in the data segment as we have no
+	 * other way of restoring the stack pointer after sleep, and we
+	 * must not write to the code segment (code is read-only)
+	 */
+
+ENTRY(s3c_cpu_resume)
+	/*
+	 * Set for L2 Cache latency
+	 */
+	mcr	p15, 1, r0, c9, c0, 2
+	ldr	r1, =0x3ff
+	bic	r0, r0, r1
+	ldr	r1, =0x2a2
+	orr	r0, r0, r1
+	mrc	p15, 1, r0, c9, c0, 2
+
+	b	cpu_resume
diff --git a/arch/arm/mach-exynos/stand-hotplug.c b/arch/arm/mach-exynos/stand-hotplug.c
new file mode 100644
index 0000000..2a83c72
--- /dev/null
+++ b/arch/arm/mach-exynos/stand-hotplug.c
@@ -0,0 +1,414 @@
+/* linux/arch/arm/mach-exynos/stand-hotplug.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * EXYNOS - Dynamic CPU hotpluging
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/ioport.h>
+#include <linux/delay.h>
+#include <linux/serial_core.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/cpu.h>
+#include <linux/percpu.h>
+#include <linux/ktime.h>
+#include <linux/tick.h>
+#include <linux/kernel_stat.h>
+#include <linux/sched.h>
+#include <linux/suspend.h>
+#include <linux/reboot.h>
+#include <linux/gpio.h>
+#include <linux/cpufreq.h>
+
+#include <plat/map-base.h>
+#include <plat/gpio-cfg.h>
+#include <plat/s5p-clock.h>
+#include <plat/clock.h>
+
+#include <mach/regs-gpio.h>
+#include <mach/regs-irq.h>
+
+#if defined(CONFIG_MACH_P10)
+#define TRANS_LOAD_H0 5
+#define TRANS_LOAD_L1 2
+#define TRANS_LOAD_H1 100
+
+#define BOOT_DELAY	30
+#define CHECK_DELAY_ON	(.5*HZ * 8)
+#define CHECK_DELAY_OFF	(.5*HZ)
+
+#endif
+
+#if defined(CONFIG_MACH_U1) || defined(CONFIG_MACH_PX)
+#define TRANS_LOAD_H0 30
+#define TRANS_LOAD_L1 20
+#define TRANS_LOAD_H1 100
+
+#define BOOT_DELAY	60
+#define CHECK_DELAY_ON	(.5*HZ * 4)
+#define CHECK_DELAY_OFF	(.5*HZ)
+#endif
+
+#if defined(CONFIG_MACH_MIDAS) || defined(CONFIG_MACH_SMDK4X12)
+#ifdef CONFIG_MACH_S2PLUS
+#define TRANS_LOAD_H0 30
+#define TRANS_LOAD_L1 20
+#define TRANS_LOAD_H1 100
+#else
+#define TRANS_LOAD_H0 20
+#define TRANS_LOAD_L1 10
+#define TRANS_LOAD_H1 35
+#endif
+#define TRANS_LOAD_L2 15
+#define TRANS_LOAD_H2 45
+#define TRANS_LOAD_L3 20
+
+#define BOOT_DELAY	60
+#define CHECK_DELAY_ON	(.5*HZ * 4)
+#define CHECK_DELAY_OFF	(.5*HZ)
+#endif
+
+#define TRANS_RQ 2
+#define TRANS_LOAD_RQ 20
+
+#define CPU_OFF 0
+#define CPU_ON  1
+
+#define HOTPLUG_UNLOCKED 0
+#define HOTPLUG_LOCKED 1
+#define PM_HOTPLUG_DEBUG 1
+#define NUM_CPUS num_possible_cpus()
+#define CPULOAD_TABLE (NR_CPUS + 1)
+
+#define DBG_PRINT(fmt, ...)\
+	if(PM_HOTPLUG_DEBUG)			\
+		printk(KERN_INFO pr_fmt(fmt), ##__VA_ARGS__)
+
+static struct workqueue_struct *hotplug_wq;
+static struct delayed_work hotplug_work;
+
+static unsigned int max_performance;
+static unsigned int freq_min = -1UL;
+
+static unsigned int hotpluging_rate = CHECK_DELAY_OFF;
+module_param_named(rate, hotpluging_rate, uint, 0644);
+static unsigned int user_lock;
+module_param_named(lock, user_lock, uint, 0644);
+static unsigned int trans_rq= TRANS_RQ;
+module_param_named(min_rq, trans_rq, uint, 0644);
+static unsigned int trans_load_rq = TRANS_LOAD_RQ;
+module_param_named(load_rq, trans_load_rq, uint, 0644);
+
+static unsigned int trans_load_h0 = TRANS_LOAD_H0;
+module_param_named(load_h0, trans_load_h0, uint, 0644);
+static unsigned int trans_load_l1 = TRANS_LOAD_L1;
+module_param_named(load_l1, trans_load_l1, uint, 0644);
+static unsigned int trans_load_h1 = TRANS_LOAD_H1;
+module_param_named(load_h1, trans_load_h1, uint, 0644);
+
+#if (NR_CPUS > 2)
+static unsigned int trans_load_l2 = TRANS_LOAD_L2;
+module_param_named(load_l2, trans_load_l2, uint, 0644);
+static unsigned int trans_load_h2 = TRANS_LOAD_H2;
+module_param_named(load_h2, trans_load_h2, uint, 0644);
+static unsigned int trans_load_l3 = TRANS_LOAD_L3;
+module_param_named(load_l3, trans_load_l3, uint, 0644);
+#endif
+
+enum flag{
+	HOTPLUG_NOP,
+	HOTPLUG_IN,
+	HOTPLUG_OUT
+};
+
+struct cpu_time_info {
+	cputime64_t prev_cpu_idle;
+	cputime64_t prev_cpu_wall;
+	unsigned int load;
+};
+
+struct cpu_hotplug_info {
+	unsigned long nr_running;
+	pid_t tgid;
+};
+
+
+static DEFINE_PER_CPU(struct cpu_time_info, hotplug_cpu_time);
+
+/* mutex can be used since hotplug_timer does not run in
+   timer(softirq) context but in process context */
+static DEFINE_MUTEX(hotplug_lock);
+
+bool hotplug_out_chk(unsigned int nr_online_cpu, unsigned int threshold_up,
+		unsigned int avg_load, unsigned int cur_freq)
+{
+#if defined(CONFIG_MACH_P10)
+	return ((nr_online_cpu > 1) &&
+		(avg_load < threshold_up &&
+		cur_freq <= freq_min));
+#else
+	return ((nr_online_cpu > 1) &&
+		(avg_load < threshold_up ||
+		cur_freq <= freq_min));
+#endif
+}
+
+static inline enum flag
+standalone_hotplug(unsigned int load, unsigned long nr_rq_min, unsigned int cpu_rq_min)
+{
+	unsigned int cur_freq;
+	unsigned int nr_online_cpu;
+	unsigned int avg_load;
+	/*load threshold*/
+	unsigned int threshold[CPULOAD_TABLE][2] = {
+		{0, trans_load_h0},
+		{trans_load_l1, trans_load_h1},
+#if (NR_CPUS > 2)
+		{trans_load_l2, trans_load_h2},
+		{trans_load_l3, 100},
+#endif
+		{0, 0}
+	};
+
+	static void __iomem *clk_fimc;
+	unsigned char fimc_stat;
+
+	cur_freq = clk_get_rate(clk_get(NULL, "armclk")) / 1000;
+
+	nr_online_cpu = num_online_cpus();
+
+	avg_load = (unsigned int)((cur_freq * load) / max_performance);
+
+	clk_fimc = ioremap(0x10020000, SZ_4K);
+	fimc_stat = __raw_readl(clk_fimc + 0x0920);
+	iounmap(clk_fimc);
+
+	if ((fimc_stat>>4 & 0x1) == 1)
+		return HOTPLUG_IN;
+
+	if (hotplug_out_chk(nr_online_cpu, threshold[nr_online_cpu - 1][0],
+			    avg_load, cur_freq)) {
+		return HOTPLUG_OUT;
+		/* If total nr_running is less than cpu(on-state) number, hotplug do not hotplug-in */
+	} else if (nr_running() > nr_online_cpu &&
+		   avg_load > threshold[nr_online_cpu - 1][1] && cur_freq > freq_min) {
+
+		return HOTPLUG_IN;
+#if defined(CONFIG_MACH_P10)
+#else
+	} else if (nr_online_cpu > 1 && nr_rq_min < trans_rq) {
+
+		struct cpu_time_info *tmp_info;
+
+		tmp_info = &per_cpu(hotplug_cpu_time, cpu_rq_min);
+		/*If CPU(cpu_rq_min) load is less than trans_load_rq, hotplug-out*/
+		if (tmp_info->load < trans_load_rq)
+			return HOTPLUG_OUT;
+#endif
+	}
+
+	return HOTPLUG_NOP;
+}
+
+static void hotplug_timer(struct work_struct *work)
+{
+	struct cpu_hotplug_info tmp_hotplug_info[4];
+	int i;
+	unsigned int load = 0;
+	unsigned int cpu_rq_min=0;
+	unsigned long nr_rq_min = -1UL;
+	unsigned int select_off_cpu = 0;
+	enum flag flag_hotplug;
+
+	mutex_lock(&hotplug_lock);
+
+	if (user_lock == 1)
+		goto no_hotplug;
+
+	for_each_online_cpu(i) {
+		struct cpu_time_info *tmp_info;
+		cputime64_t cur_wall_time, cur_idle_time;
+		unsigned int idle_time, wall_time;
+
+		tmp_info = &per_cpu(hotplug_cpu_time, i);
+
+		cur_idle_time = get_cpu_idle_time_us(i, &cur_wall_time);
+
+		idle_time = (unsigned int)cputime64_sub(cur_idle_time,
+							tmp_info->prev_cpu_idle);
+		tmp_info->prev_cpu_idle = cur_idle_time;
+
+		wall_time = (unsigned int)cputime64_sub(cur_wall_time,
+							tmp_info->prev_cpu_wall);
+		tmp_info->prev_cpu_wall = cur_wall_time;
+
+		if (wall_time < idle_time)
+			goto no_hotplug;
+
+#ifdef CONFIG_TARGET_LOCALE_P2TMO_TEMP
+		/*For once Divide-by-Zero issue*/
+		if (wall_time == 0)
+			wall_time++;
+#endif
+		tmp_info->load = 100 * (wall_time - idle_time) / wall_time;
+
+		load += tmp_info->load;
+		/*find minimum runqueue length*/
+		tmp_hotplug_info[i].nr_running = get_cpu_nr_running(i);
+
+		if (i && nr_rq_min > tmp_hotplug_info[i].nr_running) {
+			nr_rq_min = tmp_hotplug_info[i].nr_running;
+
+			cpu_rq_min = i;
+		}
+	}
+
+	for (i = NUM_CPUS - 1; i > 0; --i) {
+		if (cpu_online(i) == 0) {
+			select_off_cpu = i;
+			break;
+		}
+	}
+
+	/*standallone hotplug*/
+	flag_hotplug = standalone_hotplug(load, nr_rq_min, cpu_rq_min);
+
+	/*cpu hotplug*/
+	if (flag_hotplug == HOTPLUG_IN && cpu_online(select_off_cpu) == CPU_OFF) {
+		DBG_PRINT("cpu%d turning on!\n", select_off_cpu);
+		cpu_up(select_off_cpu);
+		DBG_PRINT("cpu%d on\n", select_off_cpu);
+		hotpluging_rate = CHECK_DELAY_ON;
+	} else if (flag_hotplug == HOTPLUG_OUT && cpu_online(cpu_rq_min) == CPU_ON) {
+		DBG_PRINT("cpu%d turnning off!\n", cpu_rq_min);
+		cpu_down(cpu_rq_min);
+		DBG_PRINT("cpu%d off!\n", cpu_rq_min);
+		hotpluging_rate = CHECK_DELAY_OFF;
+	} 
+
+no_hotplug:
+
+	queue_delayed_work_on(0, hotplug_wq, &hotplug_work, hotpluging_rate);
+
+	mutex_unlock(&hotplug_lock);
+}
+
+static int exynos4_pm_hotplug_notifier_event(struct notifier_block *this,
+					     unsigned long event, void *ptr)
+{
+	static unsigned user_lock_saved;
+
+	switch (event) {
+	case PM_SUSPEND_PREPARE:
+		mutex_lock(&hotplug_lock);
+		user_lock_saved = user_lock;
+		user_lock = 1;
+		pr_info("%s: saving pm_hotplug lock %x\n",
+			__func__, user_lock_saved);
+		mutex_unlock(&hotplug_lock);
+		return NOTIFY_OK;
+	case PM_POST_RESTORE:
+	case PM_POST_SUSPEND:
+		mutex_lock(&hotplug_lock);
+		pr_info("%s: restoring pm_hotplug lock %x\n",
+			__func__, user_lock_saved);
+		user_lock = user_lock_saved;
+		mutex_unlock(&hotplug_lock);
+		return NOTIFY_OK;
+	}
+	return NOTIFY_DONE;
+}
+
+static struct notifier_block exynos4_pm_hotplug_notifier = {
+	.notifier_call = exynos4_pm_hotplug_notifier_event,
+};
+
+static int hotplug_reboot_notifier_call(struct notifier_block *this,
+					unsigned long code, void *_cmd)
+{
+	mutex_lock(&hotplug_lock);
+	pr_err("%s: disabling pm hotplug\n", __func__);
+	user_lock = 1;
+	mutex_unlock(&hotplug_lock);
+
+	return NOTIFY_DONE;
+}
+
+static struct notifier_block hotplug_reboot_notifier = {
+	.notifier_call = hotplug_reboot_notifier_call,
+};
+
+static int __init exynos4_pm_hotplug_init(void)
+{
+	unsigned int i;
+	unsigned int freq;
+	unsigned int freq_max = 0;
+	struct cpufreq_frequency_table *table;
+
+	printk(KERN_INFO "EXYNOS4 PM-hotplug init function\n");
+	//hotplug_wq = create_workqueue("dynamic hotplug");
+	hotplug_wq = alloc_workqueue("dynamic hotplug", 0, 0);
+	if (!hotplug_wq) {
+		printk(KERN_ERR "Creation of hotplug work failed\n");
+		return -EFAULT;
+	}
+
+	INIT_DELAYED_WORK(&hotplug_work, hotplug_timer);
+
+	queue_delayed_work_on(0, hotplug_wq, &hotplug_work, BOOT_DELAY * HZ);
+#ifdef CONFIG_CPU_FREQ
+	table = cpufreq_frequency_get_table(0);
+
+	for (i = 0; table[i].frequency != CPUFREQ_TABLE_END; i++) {
+		freq = table[i].frequency;
+
+		if (freq != CPUFREQ_ENTRY_INVALID && freq > freq_max)
+			freq_max = freq;
+		else if (freq != CPUFREQ_ENTRY_INVALID && freq_min > freq)
+			freq_min = freq;
+	}
+	/*get max frequence*/
+	max_performance = freq_max * NUM_CPUS;
+#else
+	max_performance = clk_get_rate(clk_get(NULL, "armclk")) / 1000 * NUM_CPUS;
+	freq_min = clk_get_rate(clk_get(NULL, "armclk")) / 1000;
+#endif
+	register_pm_notifier(&exynos4_pm_hotplug_notifier);
+	register_reboot_notifier(&hotplug_reboot_notifier);
+
+	return 0;
+}
+
+late_initcall(exynos4_pm_hotplug_init);
+
+static struct platform_device exynos4_pm_hotplug_device = {
+	.name = "exynos4-dynamic-cpu-hotplug",
+	.id = -1,
+};
+
+static int __init exynos4_pm_hotplug_device_init(void)
+{
+	int ret;
+
+	ret = platform_device_register(&exynos4_pm_hotplug_device);
+
+	if (ret) {
+		printk(KERN_ERR "failed at(%d)\n", __LINE__);
+		return ret;
+	}
+
+	printk(KERN_INFO "exynos4_pm_hotplug_device_init: %d\n", ret);
+
+	return ret;
+}
+
+late_initcall(exynos4_pm_hotplug_device_init);
diff --git a/arch/arm/mach-exynos/subsystem_notif.c b/arch/arm/mach-exynos/subsystem_notif.c
new file mode 100644
index 0000000..f7db54c
--- /dev/null
+++ b/arch/arm/mach-exynos/subsystem_notif.c
@@ -0,0 +1,222 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *
+ * Subsystem Notifier -- Provides notifications
+ * of subsys events.
+ *
+ * Use subsys_notif_register_notifier to register for notifications
+ * and subsys_notif_queue_notification to send notifications.
+ *
+ */
+
+#include <linux/notifier.h>
+#include <linux/init.h>
+#include <linux/debugfs.h>
+#include <linux/module.h>
+#include <linux/workqueue.h>
+#include <linux/stringify.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+
+#include <mach/subsystem_notif.h>
+
+struct subsys_notif_info {
+	char name[50];
+	struct srcu_notifier_head subsys_notif_rcvr_list;
+	struct list_head list;
+};
+
+static LIST_HEAD(subsystem_list);
+static DEFINE_MUTEX(notif_lock);
+static DEFINE_MUTEX(notif_add_lock);
+
+#if defined(SUBSYS_RESTART_DEBUG)
+static void subsys_notif_reg_test_notifier(const char *);
+#endif
+
+static struct subsys_notif_info *_notif_find_subsys(const char *subsys_name)
+{
+	struct subsys_notif_info *subsys;
+
+	mutex_lock(&notif_lock);
+	list_for_each_entry(subsys, &subsystem_list, list)
+		if (!strncmp(subsys->name, subsys_name,
+				ARRAY_SIZE(subsys->name))) {
+			mutex_unlock(&notif_lock);
+			return subsys;
+		}
+	mutex_unlock(&notif_lock);
+
+	return NULL;
+}
+
+void *subsys_notif_register_notifier(
+			const char *subsys_name, struct notifier_block *nb)
+{
+	int ret;
+	struct subsys_notif_info *subsys = _notif_find_subsys(subsys_name);
+
+	if (!subsys) {
+
+		/* Possible first time reference to this subsystem. Add it. */
+		subsys = (struct subsys_notif_info *)
+				subsys_notif_add_subsys(subsys_name);
+
+		if (!subsys)
+			return ERR_PTR(-EINVAL);
+	}
+
+	ret = srcu_notifier_chain_register(
+		&subsys->subsys_notif_rcvr_list, nb);
+
+	if (ret < 0)
+		return ERR_PTR(ret);
+
+	return subsys;
+}
+EXPORT_SYMBOL(subsys_notif_register_notifier);
+
+int subsys_notif_unregister_notifier(void *subsys_handle,
+				struct notifier_block *nb)
+{
+	int ret;
+	struct subsys_notif_info *subsys =
+			(struct subsys_notif_info *)subsys_handle;
+
+	if (!subsys)
+		return -EINVAL;
+
+	ret = srcu_notifier_chain_unregister(
+		&subsys->subsys_notif_rcvr_list, nb);
+
+	return ret;
+}
+EXPORT_SYMBOL(subsys_notif_unregister_notifier);
+
+void *subsys_notif_add_subsys(const char *subsys_name)
+{
+	struct subsys_notif_info *subsys = NULL;
+
+	if (!subsys_name)
+		goto done;
+
+	mutex_lock(&notif_add_lock);
+
+	subsys = _notif_find_subsys(subsys_name);
+
+	if (subsys) {
+		mutex_unlock(&notif_add_lock);
+		goto done;
+	}
+
+	subsys = kmalloc(sizeof(struct subsys_notif_info), GFP_KERNEL);
+
+	if (!subsys) {
+		mutex_unlock(&notif_add_lock);
+		return ERR_PTR(-EINVAL);
+	}
+
+	strlcpy(subsys->name, subsys_name, ARRAY_SIZE(subsys->name));
+
+	srcu_init_notifier_head(&subsys->subsys_notif_rcvr_list);
+
+	INIT_LIST_HEAD(&subsys->list);
+
+	mutex_lock(&notif_lock);
+	list_add_tail(&subsys->list, &subsystem_list);
+	mutex_unlock(&notif_lock);
+
+	#if defined(SUBSYS_RESTART_DEBUG)
+	subsys_notif_reg_test_notifier(subsys->name);
+	#endif
+
+	mutex_unlock(&notif_add_lock);
+
+done:
+	return subsys;
+}
+EXPORT_SYMBOL(subsys_notif_add_subsys);
+
+int subsys_notif_queue_notification(void *subsys_handle,
+					enum subsys_notif_type notif_type)
+{
+	int ret = 0;
+	struct subsys_notif_info *subsys =
+		(struct subsys_notif_info *) subsys_handle;
+
+	if (!subsys)
+		return -EINVAL;
+
+	if (notif_type < 0 || notif_type >= SUBSYS_NOTIF_TYPE_COUNT)
+		return -EINVAL;
+
+	ret = srcu_notifier_call_chain(
+		&subsys->subsys_notif_rcvr_list, notif_type,
+		(void *)subsys);
+
+	return ret;
+}
+EXPORT_SYMBOL(subsys_notif_queue_notification);
+
+#if defined(SUBSYS_RESTART_DEBUG)
+static const char *notif_to_string(enum subsys_notif_type notif_type)
+{
+	switch (notif_type) {
+
+	case	SUBSYS_BEFORE_SHUTDOWN:
+		return __stringify(SUBSYS_BEFORE_SHUTDOWN);
+
+	case	SUBSYS_AFTER_SHUTDOWN:
+		return __stringify(SUBSYS_AFTER_SHUTDOWN);
+
+	case	SUBSYS_BEFORE_POWERUP:
+		return __stringify(SUBSYS_BEFORE_POWERUP);
+
+	case	SUBSYS_AFTER_POWERUP:
+		return __stringify(SUBSYS_AFTER_POWERUP);
+
+	default:
+		return "unknown";
+	}
+}
+
+static int subsys_notifier_test_call(struct notifier_block *this,
+				  unsigned long code,
+				  void *data)
+{
+	switch (code) {
+
+	default:
+		printk(KERN_WARNING "%s: Notification %s from subsystem %p\n",
+			__func__, notif_to_string(code), data);
+	break;
+
+	}
+
+	return NOTIFY_DONE;
+}
+
+static struct notifier_block nb = {
+	.notifier_call = subsys_notifier_test_call,
+};
+
+static void subsys_notif_reg_test_notifier(const char *subsys_name)
+{
+	void *handle = subsys_notif_register_notifier(subsys_name, &nb);
+	printk(KERN_WARNING "%s: Registered test notifier, handle=%p",
+			__func__, handle);
+}
+#endif
+
+MODULE_DESCRIPTION("Subsystem Restart Notifier");
+MODULE_VERSION("1.0");
+MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/mach-exynos/subsystem_restart.c b/arch/arm/mach-exynos/subsystem_restart.c
new file mode 100644
index 0000000..0a76ab3
--- /dev/null
+++ b/arch/arm/mach-exynos/subsystem_restart.c
@@ -0,0 +1,680 @@
+/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt) "subsys-restart: %s(): " fmt, __func__
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/uaccess.h>
+#include <linux/module.h>
+#include <linux/fs.h>
+#include <linux/proc_fs.h>
+#include <linux/delay.h>
+#include <linux/list.h>
+#include <linux/io.h>
+#include <linux/kthread.h>
+#include <linux/time.h>
+#include <linux/wakelock.h>
+#include <linux/suspend.h>
+
+#include <asm/current.h>
+#ifndef CONFIG_ARCH_EXYNOS
+#include <mach/peripheral-loader.h>
+#include <mach/scm.h>
+#include <mach/socinfo.h>
+#endif
+#include <mach/subsystem_notif.h>
+#include <mach/subsystem_restart.h>
+
+#ifndef CONFIG_ARCH_EXYNOS
+#include "smd_private.h"
+#endif
+
+struct subsys_soc_restart_order {
+	const char * const *subsystem_list;
+	int count;
+
+	struct mutex shutdown_lock;
+	struct mutex powerup_lock;
+	struct subsys_data *subsys_ptrs[];
+};
+
+struct restart_wq_data {
+	struct subsys_data *subsys;
+	struct wake_lock ssr_wake_lock;
+	char wakelockname[64];
+	int coupled;
+	struct work_struct work;
+};
+
+struct restart_log {
+	struct timeval time;
+	struct subsys_data *subsys;
+	struct list_head list;
+};
+
+static int restart_level;
+static int enable_ramdumps = 1;
+struct workqueue_struct *ssr_wq;
+
+static LIST_HEAD(restart_log_list);
+static LIST_HEAD(subsystem_list);
+static DEFINE_MUTEX(subsystem_list_lock);
+static DEFINE_MUTEX(soc_order_reg_lock);
+static DEFINE_MUTEX(restart_log_mutex);
+
+/* SOC specific restart orders go here */
+
+#define DEFINE_SINGLE_RESTART_ORDER(name, order)		\
+	static struct subsys_soc_restart_order __##name = {	\
+		.subsystem_list = order,			\
+		.count = ARRAY_SIZE(order),			\
+		.subsys_ptrs = {[ARRAY_SIZE(order)] = NULL}	\
+	};							\
+	static struct subsys_soc_restart_order *name[] = {      \
+		&__##name,					\
+	}
+
+#ifndef CONFIG_ARCH_EXYNOS
+/* MSM 8x60 restart ordering info */
+static const char * const _order_8x60_all[] = {
+	"external_modem",  "modem", "lpass"
+};
+DEFINE_SINGLE_RESTART_ORDER(orders_8x60_all, _order_8x60_all);
+
+static const char * const _order_8x60_modems[] = {"external_modem", "modem"};
+DEFINE_SINGLE_RESTART_ORDER(orders_8x60_modems, _order_8x60_modems);
+#else /* CONFIG_ARCH_EXYNOS */
+/* MSM 8x60 restart ordering info */
+static const char * const _order_8x60_all[] = {
+	"external_modem",
+};
+DEFINE_SINGLE_RESTART_ORDER(orders_8x60_all, _order_8x60_all);
+
+static const char * const _order_8x60_modems[] = {"external_modem"};
+DEFINE_SINGLE_RESTART_ORDER(orders_8x60_modems, _order_8x60_modems);
+#endif
+
+/* MSM 8960 restart ordering info */
+static const char * const order_8960[] = {"modem", "lpass"};
+
+static struct subsys_soc_restart_order restart_orders_8960_one = {
+	.subsystem_list = order_8960,
+	.count = ARRAY_SIZE(order_8960),
+	.subsys_ptrs = {[ARRAY_SIZE(order_8960)] = NULL}
+	};
+
+static struct subsys_soc_restart_order *restart_orders_8960[] = {
+	&restart_orders_8960_one,
+};
+/* These will be assigned to one of the sets above after
+ * runtime SoC identification.
+ */
+static struct subsys_soc_restart_order **restart_orders;
+static int n_restart_orders;
+
+module_param(enable_ramdumps, int, S_IRUGO | S_IWUSR);
+
+static struct subsys_soc_restart_order *_update_restart_order(
+		struct subsys_data *subsys);
+
+#ifndef CONFIG_ARCH_EXYNOS
+int get_restart_level()
+{
+	return restart_level;
+}
+EXPORT_SYMBOL(get_restart_level);
+
+static void restart_level_changed(void)
+{
+	struct subsys_data *subsys;
+
+	if (cpu_is_msm8x60() && restart_level == RESET_SUBSYS_COUPLED) {
+		restart_orders = orders_8x60_all;
+		n_restart_orders = ARRAY_SIZE(orders_8x60_all);
+	}
+
+	if (cpu_is_msm8x60() && restart_level == RESET_SUBSYS_MIXED) {
+		restart_orders = orders_8x60_modems;
+		n_restart_orders = ARRAY_SIZE(orders_8x60_modems);
+	}
+
+	mutex_lock(&subsystem_list_lock);
+	list_for_each_entry(subsys, &subsystem_list, list)
+		subsys->restart_order = _update_restart_order(subsys);
+	mutex_unlock(&subsystem_list_lock);
+}
+
+static int restart_level_set(const char *val, struct kernel_param *kp)
+{
+	int ret;
+	int old_val = restart_level;
+
+	if (cpu_is_msm9615()) {
+		pr_err("Only Phase 1 subsystem restart is supported\n");
+		return -EINVAL;
+	}
+
+	ret = param_set_int(val, kp);
+	if (ret)
+		return ret;
+
+	switch (restart_level) {
+
+	case RESET_SOC:
+	case RESET_SUBSYS_COUPLED:
+	case RESET_SUBSYS_INDEPENDENT:
+		pr_info("Phase %d behavior activated.\n", restart_level);
+	break;
+
+	case RESET_SUBSYS_MIXED:
+		pr_info("Phase 2+ behavior activated.\n");
+	break;
+
+	default:
+		restart_level = old_val;
+		return -EINVAL;
+	break;
+
+	}
+
+	if (restart_level != old_val)
+		restart_level_changed();
+
+	return 0;
+}
+
+module_param_call(restart_level, restart_level_set, param_get_int,
+			&restart_level, 0644);
+#endif
+static struct subsys_data *_find_subsystem(const char *subsys_name)
+{
+	struct subsys_data *subsys;
+
+	mutex_lock(&subsystem_list_lock);
+	list_for_each_entry(subsys, &subsystem_list, list)
+		if (!strncmp(subsys->name, subsys_name,
+				SUBSYS_NAME_MAX_LENGTH)) {
+			mutex_unlock(&subsystem_list_lock);
+			return subsys;
+		}
+	mutex_unlock(&subsystem_list_lock);
+
+	return NULL;
+}
+
+static struct subsys_soc_restart_order *_update_restart_order(
+		struct subsys_data *subsys)
+{
+	int i, j;
+
+	if (!subsys)
+		return NULL;
+
+	if (!subsys->name)
+		return NULL;
+
+	mutex_lock(&soc_order_reg_lock);
+	for (j = 0; j < n_restart_orders; j++) {
+		for (i = 0; i < restart_orders[j]->count; i++)
+			if (!strncmp(restart_orders[j]->subsystem_list[i],
+				subsys->name, SUBSYS_NAME_MAX_LENGTH)) {
+
+					restart_orders[j]->subsys_ptrs[i] =
+						subsys;
+					mutex_unlock(&soc_order_reg_lock);
+					return restart_orders[j];
+			}
+	}
+
+	mutex_unlock(&soc_order_reg_lock);
+
+	return NULL;
+}
+
+static void _send_notification_to_order(struct subsys_data
+			**restart_list, int count,
+			enum subsys_notif_type notif_type)
+{
+	int i;
+
+	for (i = 0; i < count; i++)
+		if (restart_list[i])
+			subsys_notif_queue_notification(
+				restart_list[i]->notif_handle, notif_type);
+}
+
+static int max_restarts;
+module_param(max_restarts, int, 0644);
+
+static long max_history_time = 3600;
+module_param(max_history_time, long, 0644);
+
+static void do_epoch_check(struct subsys_data *subsys)
+{
+	int n = 0;
+	struct timeval *time_first = NULL, *curr_time;
+	struct restart_log *r_log, *temp;
+	static int max_restarts_check;
+	static long max_history_time_check;
+
+	mutex_lock(&restart_log_mutex);
+
+	max_restarts_check = max_restarts;
+	max_history_time_check = max_history_time;
+
+	/* Check if epoch checking is enabled */
+	if (!max_restarts_check)
+		goto out;
+
+	r_log = kmalloc(sizeof(struct restart_log), GFP_KERNEL);
+	if (!r_log)
+		goto out;
+	r_log->subsys = subsys;
+	do_gettimeofday(&r_log->time);
+	curr_time = &r_log->time;
+	INIT_LIST_HEAD(&r_log->list);
+
+	list_add_tail(&r_log->list, &restart_log_list);
+
+	list_for_each_entry_safe(r_log, temp, &restart_log_list, list) {
+
+		if ((curr_time->tv_sec - r_log->time.tv_sec) >
+				max_history_time_check) {
+
+			pr_debug("Deleted node with restart_time = %ld\n",
+					r_log->time.tv_sec);
+			list_del(&r_log->list);
+			kfree(r_log);
+			continue;
+		}
+		if (!n) {
+			time_first = &r_log->time;
+			pr_debug("Time_first: %ld\n", time_first->tv_sec);
+		}
+		n++;
+		pr_debug("Restart_time: %ld\n", r_log->time.tv_sec);
+	}
+
+	if (time_first && n >= max_restarts_check) {
+		if ((curr_time->tv_sec - time_first->tv_sec) <
+				max_history_time_check)
+			panic("Subsystems have crashed %d times in less than "
+				"%ld seconds!", max_restarts_check,
+				max_history_time_check);
+	}
+
+out:
+	mutex_unlock(&restart_log_mutex);
+}
+
+static void subsystem_restart_wq_func(struct work_struct *work)
+{
+	struct restart_wq_data *r_work = container_of(work,
+						struct restart_wq_data, work);
+	struct subsys_data **restart_list;
+	struct subsys_data *subsys = r_work->subsys;
+	struct subsys_soc_restart_order *soc_restart_order = NULL;
+
+	struct mutex *powerup_lock;
+	struct mutex *shutdown_lock;
+
+	int i;
+	int restart_list_count = 0;
+
+	if (r_work->coupled)
+		soc_restart_order = subsys->restart_order;
+
+	/* It's OK to not take the registration lock at this point.
+	 * This is because the subsystem list inside the relevant
+	 * restart order is not being traversed.
+	 */
+	if (!soc_restart_order) {
+		pr_info("i am here\n");
+		restart_list = subsys->single_restart_list;
+		restart_list_count = 1;
+		powerup_lock = &subsys->powerup_lock;
+		shutdown_lock = &subsys->shutdown_lock;
+	} else {
+		pr_info("i am here, 2nd\n");
+		restart_list = soc_restart_order->subsys_ptrs;
+		restart_list_count = soc_restart_order->count;
+		powerup_lock = &soc_restart_order->powerup_lock;
+		shutdown_lock = &soc_restart_order->shutdown_lock;
+	}
+	pr_info("subsys[%p], powerup lock[%p], shutdown_lock[%p]\n", subsys,
+						powerup_lock, shutdown_lock);
+
+	pr_info("[%p]: Attempting to get shutdown lock!\n", current);
+
+	/* Try to acquire shutdown_lock. If this fails, these subsystems are
+	 * already being restarted - return.
+	 */
+	if (!mutex_trylock(shutdown_lock))
+		goto out;
+
+	pr_info("[%p]: Attempting to get powerup lock!\n", current);
+
+	/* Now that we've acquired the shutdown lock, either we're the first to
+	 * restart these subsystems or some other thread is doing the powerup
+	 * sequence for these subsystems. In the latter case, panic and bail
+	 * out, since a subsystem died in its powerup sequence.
+	 */
+	if (!mutex_trylock(powerup_lock))
+		panic("%s[%p]: Subsystem died during powerup!",
+						__func__, current);
+
+	do_epoch_check(subsys);
+
+	/* Now it is necessary to take the registration lock. This is because
+	 * the subsystem list in the SoC restart order will be traversed
+	 * and it shouldn't be changed until _this_ restart sequence completes.
+	 */
+	mutex_lock(&soc_order_reg_lock);
+
+	pr_info("[%p]: Starting restart sequence for %s\n", current,
+			r_work->subsys->name);
+
+	_send_notification_to_order(restart_list,
+				restart_list_count,
+				SUBSYS_BEFORE_SHUTDOWN);
+
+	for (i = 0; i < restart_list_count; i++) {
+
+		if (!restart_list[i])
+			continue;
+
+		pr_info("[%p]: Shutting down %s\n", current,
+			restart_list[i]->name);
+
+		if (restart_list[i]->shutdown(subsys) < 0)
+			panic("subsys-restart: %s[%p]: Failed to shutdown %s!",
+				__func__, current, restart_list[i]->name);
+	}
+
+	_send_notification_to_order(restart_list, restart_list_count,
+				SUBSYS_AFTER_SHUTDOWN);
+
+	/* Now that we've finished shutting down these subsystems, release the
+	 * shutdown lock. If a subsystem restart request comes in for a
+	 * subsystem in _this_ restart order after the unlock below, and
+	 * before the powerup lock is released, panic and bail out.
+	 */
+	mutex_unlock(shutdown_lock);
+
+	/* Collect ram dumps for all subsystems in order here */
+	for (i = 0; i < restart_list_count; i++) {
+		if (!restart_list[i])
+			continue;
+
+		if (restart_list[i]->ramdump)
+			if (restart_list[i]->ramdump(enable_ramdumps,
+							subsys) < 0)
+				pr_warn("%s[%p]: Ramdump failed.\n",
+						restart_list[i]->name, current);
+	}
+
+	_send_notification_to_order(restart_list,
+			restart_list_count,
+			SUBSYS_BEFORE_POWERUP);
+
+	for (i = restart_list_count - 1; i >= 0; i--) {
+
+		if (!restart_list[i])
+			continue;
+
+		pr_info("[%p]: Powering up %s\n", current,
+					restart_list[i]->name);
+
+		if (restart_list[i]->powerup(subsys) < 0)
+			panic("%s[%p]: Failed to powerup %s!", __func__,
+				current, restart_list[i]->name);
+	}
+
+	_send_notification_to_order(restart_list,
+				restart_list_count,
+				SUBSYS_AFTER_POWERUP);
+
+	pr_info("[%p]: Restart sequence for %s completed.\n",
+			current, r_work->subsys->name);
+
+	mutex_unlock(powerup_lock);
+
+	mutex_unlock(&soc_order_reg_lock);
+
+	pr_info("[%p]: Released powerup lock!\n", current);
+
+out:
+	wake_unlock(&r_work->ssr_wake_lock);
+	wake_lock_destroy(&r_work->ssr_wake_lock);
+	kfree(r_work);
+}
+
+int subsystem_restart(const char *subsys_name)
+{
+	struct subsys_data *subsys;
+	struct restart_wq_data *data = NULL;
+	int rc;
+
+	if (!subsys_name) {
+		pr_err("Invalid subsystem name.\n");
+		return -EINVAL;
+	}
+
+	pr_info("Restart sequence requested for %s, restart_level = %d.\n",
+		subsys_name, restart_level);
+
+	/* List of subsystems is protected by a lock. New subsystems can
+	 * still come in.
+	 */
+	subsys = _find_subsystem(subsys_name);
+
+	if (!subsys) {
+		pr_warn("Unregistered subsystem %s!\n", subsys_name);
+		return -EINVAL;
+	}
+
+#ifndef CONFIG_ARCH_EXYNOS
+	if (restart_level != RESET_SOC) {
+		data = kzalloc(sizeof(struct restart_wq_data), GFP_KERNEL);
+		if (!data) {
+			restart_level = RESET_SOC;
+			pr_warn("Failed to alloc restart data. Resetting.\n");
+		} else {
+			if (restart_level == RESET_SUBSYS_COUPLED ||
+					restart_level == RESET_SUBSYS_MIXED)
+				data->coupled = 1;
+			else
+				data->coupled = 0;
+
+			data->subsys = subsys;
+		}
+	}
+
+	switch (restart_level) {
+
+	case RESET_SUBSYS_COUPLED:
+	case RESET_SUBSYS_MIXED:
+	case RESET_SUBSYS_INDEPENDENT:
+		pr_debug("Restarting %s [level=%d]!\n", subsys_name,
+				restart_level);
+
+		snprintf(data->wakelockname, sizeof(data->wakelockname),
+				"ssr(%s)", subsys_name);
+		wake_lock_init(&data->ssr_wake_lock, WAKE_LOCK_SUSPEND,
+			data->wakelockname);
+		wake_lock(&data->ssr_wake_lock);
+
+		INIT_WORK(&data->work, subsystem_restart_wq_func);
+		rc = schedule_work(&data->work);
+
+		if (rc < 0)
+			panic("%s: Unable to schedule work to restart %s",
+			     __func__, subsys->name);
+		break;
+
+	case RESET_SOC:
+		panic("subsys-restart: Resetting the SoC - %s crashed.",
+			subsys->name);
+		break;
+
+	default:
+		panic("subsys-restart: Unknown restart level!\n");
+	break;
+
+	}
+#else /* CONFIG_ARCH_EXYNOS */
+	data = kzalloc(sizeof(struct restart_wq_data), GFP_KERNEL);
+	if (!data) {
+		restart_level = RESET_SOC;
+		pr_warn("Failed to alloc restart data. Resetting.\n");
+		panic("subsys-restart: Resetting the SoC - %s crashed.",
+								subsys->name);
+	} else {
+		data->coupled = 0;
+		data->subsys = subsys;
+	}
+	pr_debug("Restarting %s [level=%d]!\n", subsys_name, restart_level);
+
+	snprintf(data->wakelockname, sizeof(data->wakelockname),
+						"ssr(%s)", subsys_name);
+	wake_lock_init(&data->ssr_wake_lock, WAKE_LOCK_SUSPEND,
+							data->wakelockname);
+	wake_lock(&data->ssr_wake_lock);
+
+	INIT_WORK(&data->work, subsystem_restart_wq_func);
+	rc = schedule_work(&data->work);
+
+	if (rc < 0)
+		panic("%s: Unable to schedule work to restart %s",
+						     __func__, subsys->name);
+#endif
+	return 0;
+}
+EXPORT_SYMBOL(subsystem_restart);
+
+int ssr_register_subsystem(struct subsys_data *subsys)
+{
+	pr_info("%s\n", __func__);
+	if (!subsys)
+		goto err;
+
+	if (!subsys->name)
+		goto err;
+
+	if (!subsys->powerup || !subsys->shutdown)
+		goto err;
+
+	subsys->notif_handle = subsys_notif_add_subsys(subsys->name);
+	subsys->restart_order = _update_restart_order(subsys);
+	subsys->single_restart_list[0] = subsys;
+
+	mutex_init(&subsys->shutdown_lock);
+	mutex_init(&subsys->powerup_lock);
+
+	mutex_lock(&subsystem_list_lock);
+	list_add(&subsys->list, &subsystem_list);
+	mutex_unlock(&subsystem_list_lock);
+
+	return 0;
+
+err:
+	return -EINVAL;
+}
+EXPORT_SYMBOL(ssr_register_subsystem);
+
+static int ssr_panic_handler(struct notifier_block *this,
+				unsigned long event, void *ptr)
+{
+	struct subsys_data *subsys;
+
+	list_for_each_entry(subsys, &subsystem_list, list)
+		if (subsys->crash_shutdown)
+			subsys->crash_shutdown(subsys);
+	return NOTIFY_DONE;
+}
+
+static struct notifier_block panic_nb = {
+	.notifier_call  = ssr_panic_handler,
+};
+
+static int __init ssr_init_soc_restart_orders(void)
+{
+	int i;
+
+	atomic_notifier_chain_register(&panic_notifier_list,
+			&panic_nb);
+#ifndef CONFIG_ARCH_EXYNOS
+	if (cpu_is_msm8x60()) {
+		for (i = 0; i < ARRAY_SIZE(orders_8x60_all); i++) {
+			mutex_init(&orders_8x60_all[i]->powerup_lock);
+			mutex_init(&orders_8x60_all[i]->shutdown_lock);
+		}
+
+		for (i = 0; i < ARRAY_SIZE(orders_8x60_modems); i++) {
+			mutex_init(&orders_8x60_modems[i]->powerup_lock);
+			mutex_init(&orders_8x60_modems[i]->shutdown_lock);
+		}
+
+		restart_orders = orders_8x60_all;
+		n_restart_orders = ARRAY_SIZE(orders_8x60_all);
+	}
+
+	if (cpu_is_msm8960() || cpu_is_msm8930() || cpu_is_msm9615() ||
+			cpu_is_apq8064()) {
+		restart_orders = restart_orders_8960;
+		n_restart_orders = ARRAY_SIZE(restart_orders_8960);
+	}
+#else
+	for (i = 0; i < ARRAY_SIZE(orders_8x60_all); i++) {
+		mutex_init(&orders_8x60_all[i]->powerup_lock);
+		mutex_init(&orders_8x60_all[i]->shutdown_lock);
+	}
+
+	for (i = 0; i < ARRAY_SIZE(orders_8x60_modems); i++) {
+		mutex_init(&orders_8x60_modems[i]->powerup_lock);
+		mutex_init(&orders_8x60_modems[i]->shutdown_lock);
+	}
+
+	restart_orders = orders_8x60_all;
+	n_restart_orders = ARRAY_SIZE(orders_8x60_all);
+#endif
+	if (restart_orders == NULL || n_restart_orders < 1) {
+		WARN_ON(1);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int __init subsys_restart_init(void)
+{
+	int ret = 0;
+
+	pr_info("%s\n", __func__);
+
+	restart_level = RESET_SOC;
+
+	ssr_wq = alloc_workqueue("ssr_wq", 0, 0);
+
+	if (!ssr_wq)
+		panic("Couldn't allocate workqueue for subsystem restart.\n");
+
+	ret = ssr_init_soc_restart_orders();
+
+	return ret;
+}
+
+arch_initcall(subsys_restart_init);
+
+MODULE_DESCRIPTION("Subsystem Restart Driver");
+MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/mach-exynos/sysreg.c b/arch/arm/mach-exynos/sysreg.c
new file mode 100644
index 0000000..9711934
--- /dev/null
+++ b/arch/arm/mach-exynos/sysreg.c
@@ -0,0 +1,78 @@
+/* linux/arch/arm/mach-exynos/sysreg.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ * MyungJoo Ham <myungjoo.ham@samsung.com>
+ *
+ * EXYNOS - System Register PM Support Driver
+ *
+ * Currently support Exynos4210, 4212, 4412.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/syscore_ops.h>
+
+#include <plat/cpu.h>
+#include <plat/map-base.h>
+#include <plat/pm.h>
+
+#ifdef CONFIG_PM_SLEEP
+static struct sleep_save exynos4210_sysreg_save[] = {
+	SAVE_ITEM(S3C_VA_SYS + 0x210),
+	SAVE_ITEM(S3C_VA_SYS + 0x214),
+	SAVE_ITEM(S3C_VA_SYS + 0x218),
+	SAVE_ITEM(S3C_VA_SYS + 0x220),
+	SAVE_ITEM(S3C_VA_SYS + 0x230),
+};
+
+static struct sleep_save exynos4x12_sysreg_save[] = {
+	SAVE_ITEM(S3C_VA_SYS + 0x10C),
+	SAVE_ITEM(S3C_VA_SYS + 0x110),
+	SAVE_ITEM(S3C_VA_SYS + 0x114),
+	SAVE_ITEM(S3C_VA_SYS + 0x20C),
+	SAVE_ITEM(S3C_VA_SYS + 0x210),
+	SAVE_ITEM(S3C_VA_SYS + 0x214),
+	SAVE_ITEM(S3C_VA_SYS + 0x218),
+	SAVE_ITEM(S3C_VA_SYS + 0x21C),
+	SAVE_ITEM(S3C_VA_SYS + 0x320),
+	SAVE_ITEM(S3C_VA_SYS + 0x330),
+};
+
+static int exynos4_sysreg_suspend(void)
+{
+	if (soc_is_exynos4210()) {
+		s3c_pm_do_save(exynos4210_sysreg_save,
+			       ARRAY_SIZE(exynos4210_sysreg_save));
+	} else if (soc_is_exynos4212() || soc_is_exynos4412()) {
+		s3c_pm_do_save(exynos4x12_sysreg_save,
+			       ARRAY_SIZE(exynos4x12_sysreg_save));
+	}
+	return 0;
+}
+
+static void exynos4_sysreg_resume(void)
+{
+	if (soc_is_exynos4210()) {
+		s3c_pm_do_restore_core(exynos4210_sysreg_save,
+				       ARRAY_SIZE(exynos4210_sysreg_save));
+	} else if (soc_is_exynos4212() || soc_is_exynos4412()) {
+		s3c_pm_do_restore_core(exynos4x12_sysreg_save,
+				       ARRAY_SIZE(exynos4x12_sysreg_save));
+	}
+}
+
+static struct syscore_ops exynos4_syscore_ops = {
+	.suspend	= exynos4_sysreg_suspend,
+	.resume		= exynos4_sysreg_resume,
+};
+
+static int __init exynos4_register_sysreg_pm(void)
+{
+	register_syscore_ops(&exynos4_syscore_ops);
+	return 0;
+}
+arch_initcall(exynos4_register_sysreg_pm);
+#endif
diff --git a/arch/arm/mach-exynos/tmu.c b/arch/arm/mach-exynos/tmu.c
new file mode 100644
index 0000000..c39ff65
--- /dev/null
+++ b/arch/arm/mach-exynos/tmu.c
@@ -0,0 +1,1432 @@
+/* linux/arch/arm/mach-exynos/tmu.c
+*
+* Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *      http://www.samsung.com
+*
+ * EXYNOS4 - Thermal Management support
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License version 2 as
+* published by the Free Software Foundation.
+*/
+
+#include <linux/module.h>
+#include <linux/fs.h>
+#include <linux/string.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/power_supply.h>
+#include <linux/interrupt.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+#include <linux/slab.h>
+#include <linux/kobject.h>
+
+#include <asm/irq.h>
+
+#include <mach/regs-tmu.h>
+#include <mach/cpufreq.h>
+#include <mach/map.h>
+#include <mach/smc.h>
+#include <plat/s5p-tmu.h>
+#include <plat/map-s5p.h>
+#include <plat/gpio-cfg.h>
+#include <plat/cpu.h>
+
+#include <mach/asv.h>
+#ifdef CONFIG_BUSFREQ_OPP
+#include <mach/busfreq_exynos4.h>
+#include <mach/dev.h>
+#endif
+
+static enum {
+ENABLE_TEMP_MON	= 0x1,
+ENABLE_TEST_MODE = 0x2,
+} enable_mask = ENABLE_TEMP_MON | ENABLE_TEST_MODE;
+module_param_named(enable_mask, enable_mask, uint, 0644);
+#define ENABLE_DBGMASK (ENABLE_TEMP_MON | ENABLE_TEST_MODE)
+
+/* for factory mode */
+#define CONFIG_TMU_SYSFS
+
+/* flags that throttling or trippint is treated */
+#define THROTTLE_FLAG (0x1 << 0)
+#define WARNING_FLAG (0x1 << 1)
+#define TRIPPING_FLAG	(0x1 << 2)
+#define MEM_THROTTLE_FLAG (0x1 << 4)
+
+#define TIMING_AREF_OFFSET	0x30
+
+static struct workqueue_struct  *tmu_monitor_wq;
+
+static DEFINE_MUTEX(tmu_lock);
+
+
+#if (defined(CONFIG_CPU_EXYNOS4212) || defined(CONFIG_CPU_EXYNOS4412)) \
+	&& defined(CONFIG_VIDEO_MALI400MP)
+extern int mali_voltage_lock_init(void);
+extern int mali_voltage_lock_push(int lock_vol);
+extern int mali_voltage_lock_pop(void);
+#define CONFIG_TC_VOLTAGE /* Temperature compensated voltage */
+#endif
+
+static unsigned int get_curr_temp(struct s5p_tmu_info *info)
+{
+	unsigned char curr_temp_code;
+	int temperature;
+
+	if (!info)
+		return -EAGAIN;
+
+	/* After reading temperature code from register, compensating
+	 * its value and calculating celsius temperatue,
+	 * get current temperatue.
+	*/
+	curr_temp_code =
+		__raw_readl(info->tmu_base + EXYNOS4_TMU_CURRENT_TEMP) & 0xff;
+
+	/* Check range of temprature code with curr_temp_code & efusing info */
+	pr_debug("CURRENT_TEMP = 0x%02x\n", curr_temp_code);
+#if defined(CONFIG_CPU_EXYNOS4212) || defined(CONFIG_CPU_EXYNOS4412)
+	/* temperature code range are between min 10 and 125 */
+	if ((info->te1 - curr_temp_code) > 15
+		|| (curr_temp_code - info->te1) > 100)
+#else
+	/* temperature code range are between min 25 and 125 */
+	if ((curr_temp_code - info->te1) < 0
+		|| (curr_temp_code - info->te1) > 100)
+#endif
+		pr_warning("temperature code is in inaccurate -->"
+			"check if vdd_18_ts is on\n"
+			"or surrounding temp is low.\n");
+
+	/* compensate and calculate current temperature */
+	temperature = curr_temp_code - info->te1 + TMU_DC_VALUE;
+	if (temperature < 0) {
+		/* if temperature lower than 0 degree, set 0 degree */
+		pr_info("current temp is %d celsius degree.\n"
+			"so, set to 0 celsius degree!\n", temperature);
+		temperature = 0;
+	}
+	return (unsigned int)temperature;
+}
+
+static ssize_t show_temperature(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct s5p_tmu_info *info = dev_get_drvdata(dev);
+	unsigned int temperature;
+
+	if (!dev)
+		return -ENODEV;
+
+	mutex_lock(&tmu_lock);
+
+	temperature = get_curr_temp(info);
+
+	mutex_unlock(&tmu_lock);
+
+	return sprintf(buf, "%u\n", temperature);
+}
+
+static ssize_t show_tmu_state(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct s5p_tmu_info *info = dev_get_drvdata(dev);
+
+	if (!dev)
+		return -ENODEV;
+
+	return sprintf(buf, "%d\n", info->tmu_state);
+}
+
+static ssize_t show_lot_id(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	u32 id1 = 0;
+	u32 id2 = 0;
+	id1 = __raw_readl(S5P_VA_CHIPID + 0x14);
+	id2 = __raw_readl(S5P_VA_CHIPID + 0x18);
+
+	return sprintf(buf, "%08x-%08x\n", id1, id2);
+}
+static DEVICE_ATTR(temperature, 0444, show_temperature, NULL);
+static DEVICE_ATTR(tmu_state, 0444, show_tmu_state, NULL);
+static DEVICE_ATTR(lot_id, 0444, show_lot_id, NULL);
+
+static void print_temperature_params(struct s5p_tmu_info *info)
+{
+	struct s5p_platform_tmu *pdata = info->dev->platform_data;
+
+	pr_info("** temperature set value **\n"
+		"1st throttling stop_temp  = %u, start_temp     = %u\n"
+		"2nd throttling stop_temp  = %u, start_tmep     = %u\n"
+		"tripping temp             = %u, s/w emergency temp = %u\n"
+		"mem throttling stop_temp  = %u, start_temp     = %u\n",
+		pdata->ts.stop_1st_throttle,
+		pdata->ts.start_1st_throttle,
+		pdata->ts.stop_2nd_throttle,
+		pdata->ts.start_2nd_throttle,
+		pdata->ts.start_tripping,
+		pdata->ts.start_emergency,
+		pdata->ts.stop_mem_throttle,
+		pdata->ts.start_mem_throttle);
+#if defined(CONFIG_TC_VOLTAGE)
+	pr_info("tc_voltage stop_temp = %u, start_temp = %u\n",
+		pdata->ts.stop_tc, pdata->ts.start_tc);
+#endif
+}
+
+unsigned int get_refresh_interval(unsigned int freq_ref,
+					unsigned int refresh_nsec)
+{
+	unsigned int uRlk, refresh = 0;
+
+	/*
+	 * uRlk = FIN / 100000;
+	 * refresh_usec =  (unsigned int)(fMicrosec * 10);
+	 * uRegVal = ((unsigned int)(uRlk * uMicroSec / 100)) - 1;
+	 * refresh =
+	 * (unsigned int)(freq_ref * (unsigned int)(refresh_usec * 10) / 100) - 1;
+	*/
+	uRlk = freq_ref / 1000000;
+	refresh = ((unsigned int)(uRlk * refresh_nsec / 1000));
+
+	pr_info("@@@ get_refresh_interval = 0x%02x\n", refresh);
+	return refresh;
+}
+
+struct tmu_early_param {
+	int set_ts;
+	struct temperature_params ts;
+	int set_lock;
+	unsigned cpufreq_level_1st_throttle;
+	unsigned cpufreq_level_2nd_throttle;
+	int set_rate;
+	unsigned int sampling_rate;
+	unsigned int monitor_rate;
+};
+static struct tmu_early_param tmu_in;
+
+static int tmu_print_temp_on_off;
+
+static int __init get_temperature_params(char *str)
+{
+	int ints[11];
+
+	unsigned int mask = (enable_mask & ENABLE_DBGMASK);
+
+	if (!(mask & ENABLE_TEST_MODE))
+		return -EPERM;
+
+	get_options(str, ARRAY_SIZE(ints), ints);
+
+	/*  output the input value */
+	pr_info("tmu_test=%s\n", str);
+
+	if (ints[0])
+		tmu_in.set_ts = 1;
+	if (ints[0] > 0)
+		tmu_in.ts.stop_1st_throttle = (unsigned int)ints[1];
+	if (ints[0] > 1)
+		tmu_in.ts.start_1st_throttle = (unsigned int)ints[2];
+	if (ints[0] > 2)
+		tmu_in.ts.stop_2nd_throttle = (unsigned int)ints[3];
+	if (ints[0] > 3)
+		tmu_in.ts.start_2nd_throttle = (unsigned int)ints[4];
+	if (ints[0] > 4)
+		tmu_in.ts.start_tripping = (unsigned int)ints[5];
+	if (ints[0] > 5)
+		tmu_in.ts.start_emergency = (unsigned int)ints[6];
+	if (ints[0] > 6)
+		tmu_in.ts.stop_mem_throttle = (unsigned int)ints[7];
+	if (ints[0] > 7)
+		tmu_in.ts.start_mem_throttle = (unsigned int)ints[8];
+
+	/*  output the input value */
+	pr_info("-->1st throttling temp: start[%u], stop[%u]\n"
+		"-->2nd throttling temp: start[%u], stop[%u]\n"
+		"-->trpping temp[%u], emergency temp[%u]\n"
+		"-->mem throttling temp: start[%u], stop[%u]\n",
+		tmu_in.ts.start_1st_throttle, tmu_in.ts.stop_1st_throttle,
+		tmu_in.ts.start_2nd_throttle, tmu_in.ts.stop_2nd_throttle,
+		tmu_in.ts.start_tripping, tmu_in.ts.start_emergency,
+		tmu_in.ts.start_mem_throttle, tmu_in.ts.stop_mem_throttle);
+#ifdef CONFIG_TC_VOLTAGE
+	if (ints[0] > 8)
+		tmu_in.ts.stop_tc = (unsigned int)ints[9];
+	if (ints[0] > 9)
+		tmu_in.ts.start_tc = (unsigned int)ints[10];
+	pr_info("-->temp compensate : start[%u], stop[%u]\n",
+			tmu_in.ts.start_tc, tmu_in.ts.stop_tc);
+#endif
+	return 0;
+}
+early_param("tmu_test", get_temperature_params);
+
+static int __init get_cpufreq_limit_param(char *str)
+{
+	int ints[3];
+	unsigned int mask = (enable_mask & ENABLE_DBGMASK);
+
+	if (!(mask & ENABLE_TEST_MODE))
+		return -EPERM;
+
+	get_options(str, ARRAY_SIZE(ints), ints);
+	/*  output the input value */
+	pr_info("cpu_level=%s\n", str);
+
+	if (ints[0])
+		tmu_in.set_lock = 1;
+	if (ints[0] > 0)
+		tmu_in.cpufreq_level_1st_throttle = (unsigned int)ints[1];
+	if (ints[0] > 1)
+		tmu_in.cpufreq_level_2nd_throttle = (unsigned int)ints[2];
+
+	pr_info("--> cpufreq_limit: 1st cpu_level = %u, 2nd cpu_level = %u\n",
+		tmu_in.cpufreq_level_1st_throttle,
+		tmu_in.cpufreq_level_2nd_throttle);
+
+	return 0;
+}
+early_param("cpu_level", get_cpufreq_limit_param);
+
+static int __init get_sampling_rate_param(char *str)
+{
+	int ints[3];
+	unsigned int mask = (enable_mask & ENABLE_DBGMASK);
+
+	if (!(mask & ENABLE_TEST_MODE))
+		return -EPERM;
+
+	get_options(str, ARRAY_SIZE(ints), ints);
+	/*  output the input value */
+	pr_info("tmu_sampling_rate=%s\n", str);
+
+	if (ints[0])
+		tmu_in.set_rate = 1;
+	if (ints[0] > 0)
+		tmu_in.sampling_rate = (unsigned int)ints[1];
+	if (ints[0] > 1)
+		tmu_in.monitor_rate = (unsigned int)ints[2];
+
+	pr_info("--> sampling_rate = %u ms, monitor_rate = %u ms\n",
+		tmu_in.sampling_rate, tmu_in.monitor_rate);
+
+	return 0;
+}
+early_param("tmu_sampling_rate", get_sampling_rate_param);
+
+static void exynos4_poll_cur_temp(struct work_struct *work)
+{
+	unsigned int cur_temp;
+	struct delayed_work *delayed_work = to_delayed_work(work);
+	struct s5p_tmu_info *info =
+	    container_of(delayed_work, struct s5p_tmu_info, monitor);
+	unsigned int mask = (enable_mask & ENABLE_DBGMASK);
+
+	mutex_lock(&tmu_lock);
+
+	if (mask & ENABLE_TEMP_MON) {
+		cur_temp = get_curr_temp(info);
+
+		if (tmu_print_temp_on_off)
+			pr_info("curr temp in polling_interval = %u state = %d\n",
+				cur_temp, info->tmu_state);
+		else
+			pr_debug("curr temp in polling_interval = %u\n", cur_temp);
+	}
+	queue_delayed_work_on(0, tmu_monitor_wq, &info->monitor,
+			      info->monitor_period);
+
+	mutex_unlock(&tmu_lock);
+}
+
+static ssize_t tmu_show_print_state(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	int ret;
+
+	ret = sprintf(buf, "[TMU] tmu_print_temp_on_off=%d\n"
+					, tmu_print_temp_on_off);
+
+	return ret;
+}
+
+static ssize_t tmu_store_print_state(struct device *dev,
+	struct device_attribute *attr, const char *buf, size_t count)
+{
+	int ret = 0;
+
+	if (!strncmp(buf, "0", 1)) {
+		tmu_print_temp_on_off = 0;
+		ret = 0;
+	} else if (!strncmp(buf, "1", 1)) {
+		tmu_print_temp_on_off = 1;
+		ret = 1;
+	} else {
+		dev_err(dev, "Invalid cmd !!\n");
+		return -EINVAL;
+	}
+
+	return ret;
+}
+static DEVICE_ATTR(print_state, S_IRUGO | S_IWUSR,\
+	tmu_show_print_state, tmu_store_print_state);
+
+void set_refresh_rate(unsigned int auto_refresh)
+{
+	/*
+	 * uRlk = FIN / 100000;
+	 * refresh_usec =  (unsigned int)(fMicrosec * 10);
+	 * uRegVal = ((unsigned int)(uRlk * uMicroSec / 100)) - 1;
+	*/
+	pr_debug("set_auto_refresh = 0x%02x\n", auto_refresh);
+
+#ifdef CONFIG_ARCH_EXYNOS4
+#ifdef CONFIG_ARM_TRUSTZONE
+	exynos_smc(SMC_CMD_REG,
+		SMC_REG_ID_SFR_W((EXYNOS4_PA_DMC0_4212 + TIMING_AREF_OFFSET)),
+		auto_refresh, 0);
+	exynos_smc(SMC_CMD_REG,
+		SMC_REG_ID_SFR_W((EXYNOS4_PA_DMC1_4212 + TIMING_AREF_OFFSET)),
+		auto_refresh, 0);
+#else
+	/* change auto refresh period in TIMING_AREF register of dmc0  */
+	__raw_writel(auto_refresh, S5P_VA_DMC0 + TIMING_AREF_OFFSET);
+
+	/* change auto refresh period in TIMING_AREF regisger of dmc1 */
+	__raw_writel(auto_refresh, S5P_VA_DMC1 + TIMING_AREF_OFFSET);
+#endif
+#else	/* CONFIG_ARCH_EXYNOS4 */
+#ifdef CONFIG_ARM_TRUSTZONE
+	exynos_smc(SMC_CMD_REG,
+		SMC_REG_ID_SFR_W((EXYNOS5_PA_DMC + TIMING_AREF_OFFSET)),
+		auto_refresh, 0);
+#else
+	/* change auto refresh period in TIMING_AREF register of dmc */
+	__raw_writel(auto_refresh, S5P_VA_DMC0 + TIMING_AREF_OFFSET);
+#endif
+#endif	/* CONFIG_ARCH_EXYNOS4 */
+}
+
+static void set_temperature_params(struct s5p_tmu_info *info)
+{
+	struct s5p_platform_tmu *data = info->dev->platform_data;
+
+	/* In the tmu_test mode, change temperature_params value
+	 * input data.
+	*/
+	if (tmu_in.set_ts)
+		data->ts = tmu_in.ts;
+	if (tmu_in.set_lock) {
+		info->cpufreq_level_1st_throttle =
+				tmu_in.cpufreq_level_1st_throttle;
+		info->cpufreq_level_2nd_throttle =
+				tmu_in.cpufreq_level_2nd_throttle;
+	}
+	if (tmu_in.set_rate) {
+		info->sampling_rate =
+			usecs_to_jiffies(tmu_in.sampling_rate * 1000);
+		info->monitor_period =
+			usecs_to_jiffies(tmu_in.monitor_rate * 1000);
+	}
+	print_temperature_params(info);
+}
+
+static int notify_change_of_tmu_state(struct s5p_tmu_info *info)
+{
+	char temp_buf[20];
+	char *envp[2];
+	int env_offset = 0;
+
+	snprintf(temp_buf, sizeof(temp_buf), "TMUSTATE=%d", info->tmu_state);
+	envp[env_offset++] = temp_buf;
+	envp[env_offset] = NULL;
+
+	pr_info("%s: uevent: %d, name = %s\n",
+			__func__, info->tmu_state, temp_buf);
+
+	return kobject_uevent_env(&info->dev->kobj, KOBJ_CHANGE, envp);
+}
+
+static void exynos_interrupt_enable(struct s5p_tmu_info *info, int enable)
+{
+	static unsigned int save;
+
+	if (!save)
+		save = __raw_readl(info->tmu_base + EXYNOS4_TMU_INTEN);
+
+	if (enable)
+		__raw_writel(save, info->tmu_base + EXYNOS4_TMU_INTEN);
+	else
+		__raw_writel(0x0, info->tmu_base + EXYNOS4_TMU_INTEN);
+}
+
+/**
+ * exynos_tc_volt - locks or frees vdd_arm, vdd_mif/int and vdd_g3d for
+ * temperature compensation.
+ *
+ * This function limits or free voltage of cpufreq, busfreq, and mali driver
+ * according to 2nd arguments.
+ */
+static int exynos_tc_volt(struct s5p_tmu_info *info, int enable)
+{
+	struct s5p_platform_tmu *data = info->dev->platform_data;
+	static int usage;
+	int ret = 0;
+
+	if (!info)
+		return -EPERM;
+
+	if (enable == usage) {
+		pr_debug("TMU: already is %s.\n",
+			enable ? "locked" : "unlocked");
+		return 0;
+	}
+
+	if (enable) {
+		ret = exynos_cpufreq_lock(DVFS_LOCK_ID_TMU, info->cpulevel_tc);
+		if (ret)
+			goto err_lock;
+#ifdef CONFIG_BUSFREQ_OPP
+		ret = dev_lock(info->bus_dev, info->dev, info->busfreq_tc);
+		if (ret)
+			goto err_lock;
+#endif
+		ret = mali_voltage_lock_push(data->temp_compensate.g3d_volt);
+		if (ret < 0) {
+			pr_err("TMU: g3d_push error: %u uV\n",
+				data->temp_compensate.g3d_volt);
+			goto err_lock;
+		}
+	} else {
+		exynos_cpufreq_lock_free(DVFS_LOCK_ID_TMU);
+#ifdef CONFIG_BUSFREQ_OPP
+		ret = dev_unlock(info->bus_dev, info->dev);
+		if (ret)
+			goto err_unlock;
+#endif
+		ret = mali_voltage_lock_pop();
+		if (ret < 0) {
+			pr_err("TMU: g3d_pop error\n");
+			goto err_unlock;
+		}
+	}
+	usage = enable;
+	pr_info("TMU: %s is ok!\n", enable ? "lock" : "unlock");
+	return ret;
+
+err_lock:
+err_unlock:
+	pr_err("TMU: %s is fail.\n", enable ? "lock" : "unlock");
+	return ret;
+}
+
+static void exynos4_handler_tmu_state(struct work_struct *work)
+{
+	struct delayed_work *delayed_work = to_delayed_work(work);
+	struct s5p_tmu_info *info =
+		container_of(delayed_work, struct s5p_tmu_info, polling);
+	struct s5p_platform_tmu *data = info->dev->platform_data;
+	unsigned int cur_temp;
+	static int auto_refresh_changed;
+	static int check_handle;
+	int trend = 0;
+
+	mutex_lock(&tmu_lock);
+
+	cur_temp = get_curr_temp(info);
+	trend = cur_temp - info->last_temperature;
+	pr_debug("curr_temp = %u, temp_diff = %d\n", cur_temp, trend);
+
+	switch (info->tmu_state) {
+#if defined(CONFIG_TC_VOLTAGE)
+	case TMU_STATUS_TC:
+		/* lock has priority than unlock */
+		if (cur_temp <= data->ts.start_tc) {
+			if (exynos_tc_volt(info, 1) < 0)
+				pr_err("TMU: lock error!\n");
+		} else if (cur_temp >= data->ts.stop_tc) {
+			if (exynos_tc_volt(info, 0) < 0) {
+				pr_err("TMU: unlock error!\n");
+			} else {
+				info->tmu_state = TMU_STATUS_NORMAL;
+				pr_info("change state: tc -> normal.\n");
+			}
+		}
+		/* free if upper limit is locked */
+		if (check_handle) {
+			exynos_cpufreq_upper_limit_free(DVFS_LOCK_ID_TMU);
+			check_handle = 0;
+		}
+		break;
+#endif
+	case TMU_STATUS_NORMAL:
+		/* 1. change state: 1st-throttling */
+		if (cur_temp >= data->ts.start_1st_throttle) {
+			info->tmu_state = TMU_STATUS_THROTTLED;
+			pr_info("change state: normal->throttle.\n");
+#if defined(CONFIG_TC_VOLTAGE)
+		/* check whether temp compesation need or not */
+		} else if (cur_temp <= data->ts.start_tc) {
+			if (exynos_tc_volt(info, 1) < 0) {
+				pr_err("TMU: lock error!\n");
+			} else {
+				info->tmu_state = TMU_STATUS_TC;
+				pr_info("change state: normal->tc.\n");
+			}
+#endif
+		/* 2. polling end and uevent */
+		} else if ((cur_temp <= data->ts.stop_1st_throttle)
+			&& (cur_temp <= data->ts.stop_mem_throttle)) {
+			if (check_handle & THROTTLE_FLAG) {
+				exynos_cpufreq_upper_limit_free(DVFS_LOCK_ID_TMU);
+				check_handle &= ~(THROTTLE_FLAG);
+			}
+			pr_debug("check_handle = %d\n", check_handle);
+			notify_change_of_tmu_state(info);
+			pr_info("normal: free cpufreq_limit & interrupt enable.\n");
+
+			/* clear to prevent from interfupt by peindig bit */
+			__raw_writel(INTCLEARALL,
+				info->tmu_base + EXYNOS4_TMU_INTCLEAR);
+			exynos_interrupt_enable(info, 1);
+			enable_irq(info->irq);
+			mutex_unlock(&tmu_lock);
+			return;
+		}
+		break;
+
+	case TMU_STATUS_THROTTLED:
+		/* 1. change state: 2nd-throttling or warning */
+		if (cur_temp >= data->ts.start_2nd_throttle) {
+			info->tmu_state = TMU_STATUS_WARNING;
+			pr_info("change state: 1st throttle->2nd throttle.\n");
+#if defined(CONFIG_TC_VOLTAGE)
+		/* check whether temp compesation need or not */
+		} else if (cur_temp <= data->ts.start_tc) {
+			if (exynos_tc_volt(info, 1) < 0)
+				pr_err("TMU: lock error!\n");
+			else
+				info->tmu_state = TMU_STATUS_TC;
+#endif
+		/* 2. cpufreq limitation and uevent */
+		} else if ((cur_temp >= data->ts.start_1st_throttle) &&
+			!(check_handle & THROTTLE_FLAG)) {
+			if (check_handle & WARNING_FLAG) {
+				exynos_cpufreq_upper_limit_free(DVFS_LOCK_ID_TMU);
+				check_handle &= ~(WARNING_FLAG);
+			}
+			exynos_cpufreq_upper_limit(DVFS_LOCK_ID_TMU,
+					info->cpufreq_level_1st_throttle);
+			check_handle |= THROTTLE_FLAG;
+			pr_debug("check_handle = %d\n", check_handle);
+			notify_change_of_tmu_state(info);
+			pr_info("throttling: set cpufreq upper limit.\n");
+		/* 3. change state: normal */
+		} else if ((cur_temp <= data->ts.stop_1st_throttle)
+			&& (trend < 0)) {
+			info->tmu_state = TMU_STATUS_NORMAL;
+			pr_info("change state: 1st throttle->normal.\n");
+		}
+		break;
+
+	case TMU_STATUS_WARNING:
+		/* 1. change state: tripping */
+		if (cur_temp >= data->ts.start_tripping) {
+			info->tmu_state = TMU_STATUS_TRIPPED;
+			pr_info("change state: 2nd throttle->trip\n");
+#if defined(CONFIG_TC_VOLTAGE)
+		/* check whether temp compesation need or not */
+		} else if (cur_temp <= data->ts.start_tc) {
+			if (exynos_tc_volt(info, 1) < 0)
+				pr_err("TMU: lock error!\n");
+			else
+				info->tmu_state = TMU_STATUS_TC;
+#endif
+		/* 2. cpufreq limitation and uevent */
+		} else if ((cur_temp >= data->ts.start_2nd_throttle) &&
+			!(check_handle & WARNING_FLAG)) {
+			if (check_handle & THROTTLE_FLAG) {
+				exynos_cpufreq_upper_limit_free(DVFS_LOCK_ID_TMU);
+				check_handle &= ~(THROTTLE_FLAG);
+			}
+			exynos_cpufreq_upper_limit(DVFS_LOCK_ID_TMU,
+					info->cpufreq_level_2nd_throttle);
+
+			check_handle |= WARNING_FLAG;
+			pr_debug("check_handle = %d\n", check_handle);
+			notify_change_of_tmu_state(info);
+			pr_info("2nd throttle: cpufreq is limited.\n");
+		/* 3. change state: 1st-throttling */
+		} else if ((cur_temp <= data->ts.stop_2nd_throttle)
+			&& (trend < 0)) {
+			info->tmu_state = TMU_STATUS_THROTTLED;
+			pr_info("change state: 2nd throttle->1st throttle, "
+				"and release cpufreq upper limit.\n");
+		}
+		break;
+
+	case TMU_STATUS_TRIPPED:
+		/* 1. call uevent to shut-down */
+		if ((cur_temp >= data->ts.start_tripping) &&
+			(trend > 0) && !(check_handle & TRIPPING_FLAG)) {
+			notify_change_of_tmu_state(info);
+			pr_info("tripping: on waiting shutdown.\n");
+			check_handle |= TRIPPING_FLAG;
+			pr_debug("check_handle = %d\n", check_handle);
+#if defined(CONFIG_TC_VOLTAGE)
+		/* check whether temp compesation need or not */
+		} else if (cur_temp <= data->ts.start_tc) {
+			if (exynos_tc_volt(info, 1) < 0)
+				pr_err("TMU: lock error!\n");
+			else
+			info->tmu_state = TMU_STATUS_TC;
+#endif
+		/* 2. change state: 2nd-throttling or warning */
+		} else if ((cur_temp <= data->ts.stop_2nd_throttle)
+				&& (trend < 0)) {
+			info->tmu_state = TMU_STATUS_WARNING;
+			pr_info("change state: trip->2nd throttle, "
+				"Check! occured only test mode.\n");
+		}
+		/* 3. chip protection: kernel panic as SW workaround */
+		if ((cur_temp >= data->ts.start_emergency) && (trend > 0)) {
+			panic("Emergency!!!! tripping is not treated!\n");
+			/* clear to prevent from interfupt by peindig bit */
+			__raw_writel(INTCLEARALL,
+				info->tmu_state + EXYNOS4_TMU_INTCLEAR);
+			enable_irq(info->irq);
+			mutex_unlock(&tmu_lock);
+			return;
+		}
+		break;
+
+	case TMU_STATUS_INIT:
+		/* sned tmu initial status to platform */
+		disable_irq(info->irq);
+		if (cur_temp >= data->ts.start_tripping)
+			info->tmu_state = TMU_STATUS_TRIPPED;
+#if defined(CONFIG_TC_VOLTAGE)
+		/* check whether temp compesation need or not */
+		else if (cur_temp <= data->ts.start_tc) {
+			if (exynos_tc_volt(info, 1) < 0)
+				pr_err("TMU: lock error!\n");
+			else
+				info->tmu_state = TMU_STATUS_TC;
+		}
+#endif
+		else if (cur_temp >= data->ts.start_2nd_throttle)
+			info->tmu_state = TMU_STATUS_WARNING;
+		else if (cur_temp >= data->ts.start_1st_throttle)
+			info->tmu_state = TMU_STATUS_THROTTLED;
+		else if (cur_temp <= data->ts.stop_1st_throttle)
+			info->tmu_state = TMU_STATUS_NORMAL;
+
+		notify_change_of_tmu_state(info);
+		pr_info("%s: inform to init state to platform.\n", __func__);
+		break;
+
+	default:
+		pr_warn("Bug: checked tmu_state.\n");
+		if (cur_temp >= data->ts.start_tripping)
+			info->tmu_state = TMU_STATUS_TRIPPED;
+#if defined(CONFIG_TC_VOLTAGE)
+		/* check whether temp compesation need or not */
+		else if (cur_temp <= data->ts.start_tc) {
+			if (exynos_tc_volt(info, 1) < 0)
+				pr_err("TMU: lock error!\n");
+			else
+				info->tmu_state = TMU_STATUS_TC;
+		}
+#endif
+		else
+			info->tmu_state = TMU_STATUS_WARNING;
+		break;
+	} /* end */
+
+	/* memory throttling */
+	if (cur_temp >= data->ts.start_mem_throttle) {
+		if (!(auto_refresh_changed) && (trend > 0)) {
+			pr_info("set auto_refresh 1.95us\n");
+			set_refresh_rate(info->auto_refresh_tq0);
+			auto_refresh_changed = 1;
+		}
+	} else if (cur_temp <= (data->ts.stop_mem_throttle)) {
+		if ((auto_refresh_changed) && (trend < 0)) {
+			pr_info("set auto_refresh 3.9us\n");
+			set_refresh_rate(info->auto_refresh_normal);
+			auto_refresh_changed = 0;
+		}
+	}
+
+	info->last_temperature = cur_temp;
+
+	/* reschedule the next work */
+	queue_delayed_work_on(0, tmu_monitor_wq, &info->polling,
+			info->sampling_rate);
+
+	mutex_unlock(&tmu_lock);
+
+	return;
+}
+
+static int exynos4210_tmu_init(struct s5p_tmu_info *info)
+{
+	struct s5p_platform_tmu *data = info->dev->platform_data;
+	unsigned int tmp;
+	unsigned int temp_code_threshold;
+	unsigned int temp_code_throttle, temp_code_warning, temp_code_trip;
+
+	/* To compensate temperature sensor
+	 * get trim informatoin and save to struct tmu_info
+	 */
+	tmp  = __raw_readl(info->tmu_base + EXYNOS4_TMU_TRIMINFO);
+	info->te1 = tmp & TMU_TRIMINFO_MASK;
+	info->te2 = ((tmp >> 8) & TMU_TRIMINFO_MASK);
+
+	/* check boundary the triminfo */
+	if ((EFUSE_MIN_VALUE > info->te1)
+		|| (info->te1 > EFUSE_MAX_VALUE) ||  (info->te2 != 0))
+		info->te1 = EFUSE_AVG_VALUE;
+
+	pr_info("%s: triminfo = 0x%08x, low 8bit = 0x%02x, high 24 bit = 0x%06x\n",
+			__func__, tmp, info->te1, info->te2);
+
+	/* Need to initial regsiter setting after getting parameter info */
+	/* [28:23] vref [11:8] slope - Tunning parameter */
+	__raw_writel(VREF_SLOPE, info->tmu_base + EXYNOS4_TMU_CONTROL);
+
+	/* Convert celsius temperature value to temperature code value
+	 * such as threshold_level, 1st throttle, 2nd throttle,
+	 * tripping temperature.
+	*/
+	temp_code_threshold = data->ts.stop_1st_throttle
+			+ info->te1 - TMU_DC_VALUE;
+	temp_code_throttle = data->ts.start_1st_throttle
+			- data->ts.stop_1st_throttle;
+	temp_code_warning = data->ts.start_2nd_throttle
+			- data->ts.stop_1st_throttle;
+	temp_code_trip = data->ts.start_tripping
+			- data->ts.stop_1st_throttle;
+
+	/* Set interrupt trigger level */
+	__raw_writel(temp_code_threshold, info->tmu_base + EXYNOS4210_TMU_THRESHOLD_TEMP);
+	__raw_writel(temp_code_throttle, info->tmu_base + EXYNOS4210_TMU_TRIG_LEVEL0);
+	__raw_writel(temp_code_warning, info->tmu_base + EXYNOS4210_TMU_TRIG_LEVEL1);
+	__raw_writel(temp_code_trip, info->tmu_base + EXYNOS4210_TMU_TRIG_LEVEL2);
+	__raw_writel(TRIGGER_LEV_MAX, info->tmu_base + EXYNOS4210_TMU_TRIG_LEVEL3);
+
+	pr_info("THD_TEMP:0x%02x:  TRIG_LEV0: 0x%02x\n"
+		"TRIG_LEV1: 0x%02x TRIG_LEV2: 0x%02x, TRIG_LEV3: 0x%02x\n",
+		__raw_readl(info->tmu_base + EXYNOS4210_TMU_THRESHOLD_TEMP),
+		__raw_readl(info->tmu_base + EXYNOS4210_TMU_TRIG_LEVEL0),
+		__raw_readl(info->tmu_base + EXYNOS4210_TMU_TRIG_LEVEL1),
+		__raw_readl(info->tmu_base + EXYNOS4210_TMU_TRIG_LEVEL2),
+		__raw_readl(info->tmu_base + EXYNOS4210_TMU_TRIG_LEVEL3));
+
+	mdelay(50);
+
+	/* Need to initial regsiter setting after getting parameter info */
+	/* [28:23] vref [11:8] slope - Tunning parameter */
+	__raw_writel(VREF_SLOPE, info->tmu_base + EXYNOS4_TMU_CONTROL);
+	/* TMU core enable */
+	tmp = __raw_readl(info->tmu_base + EXYNOS4_TMU_CONTROL);
+	tmp |= TMUCORE_ENABLE;
+	__raw_writel(tmp, info->tmu_base + EXYNOS4_TMU_CONTROL);
+
+	/* check interrupt status register */
+	pr_debug("tmu interrupt status: 0x%02x\n",
+			__raw_readl(info->tmu_base + EXYNOS4_TMU_INTSTAT));
+
+	/* LEV0 LEV1 LEV2 interrupt enable */
+	__raw_writel(INTEN0 | INTEN1 | INTEN2, info->tmu_base + EXYNOS4_TMU_INTEN);
+	return 0;
+}
+
+static int exynos4x12_tmu_init(struct s5p_tmu_info *info)
+{
+	struct s5p_platform_tmu *data = info->dev->platform_data;
+	unsigned int tmp;
+	unsigned char temp_code_throttle, temp_code_warning, temp_code_trip;
+
+	/* To compensate temperature sensor,
+	 * set triminfo control register & get trim informatoin
+	 * and save to struct tmu_info
+	*/
+	tmp = __raw_readl(info->tmu_base + EXYNOS4x12_TMU_TRIMINFO_CONROL);
+	tmp |= TMU_RELOAD;
+	__raw_writel(tmp, info->tmu_base + EXYNOS4x12_TMU_TRIMINFO_CONROL);
+
+	mdelay(1);
+
+	tmp  = __raw_readl(info->tmu_base + EXYNOS4_TMU_TRIMINFO);
+	info->te1 = tmp & TMU_TRIMINFO_MASK;
+
+	/* In case of non e-fusing chip, s/w workaround */
+	if (tmp == 0)
+		info->te1 = 0x37;
+
+	pr_debug("%s: triminfo reg = 0x%08x, value = %u\n", __func__,
+			tmp, info->te1);
+
+	/* Convert celsius temperature value to temperature code value
+	 * such as 1st throttle, 2nd throttle, tripping temperature.
+	 * its ranges are between 25 cesius(0x32) to 125 cesius4(0x96)
+	*/
+	temp_code_throttle = data->ts.start_1st_throttle
+			+ info->te1 - TMU_DC_VALUE;
+	temp_code_warning = data->ts.start_2nd_throttle
+			+ info->te1 - TMU_DC_VALUE;
+	temp_code_trip = data->ts.start_tripping
+			+ info->te1 - TMU_DC_VALUE;
+
+	pr_debug("temp_code_throttle: %u, temp_code_warning: %u\n"
+		 "temp_code_trip: %u, info->te1 = %u\n",
+		temp_code_throttle, temp_code_warning,
+		temp_code_trip, info->te1);
+
+	/* Set interrupt trigger level */
+	tmp =  ((0xFF << 24) | (temp_code_trip << 16) |
+			(temp_code_warning << 8) | (temp_code_throttle << 0));
+	__raw_writel(tmp, info->tmu_base + EXYNOS4x12_TMU_TRESHOLD_TEMP_RISE);
+
+	pr_debug("THD_TEMP_RISE: 0x%08x\n",
+		__raw_readl(info->tmu_base + EXYNOS4x12_TMU_TRESHOLD_TEMP_RISE));
+
+#if defined(CONFIG_TC_VOLTAGE)
+	/* Get set temperature for tc_voltage and set falling interrupt
+	 * trigger level
+	*/
+	tmp = (data->ts.start_tc + info->te1 - TMU_DC_VALUE) << 0;
+	__raw_writel(tmp, info->tmu_base + EXYNOS4x12_TMU_TRESHOLD_TEMP_FALL);
+	pr_debug("THD_TEMP_FALL: 0x%08x\n",
+		__raw_readl(info->tmu_base + EXYNOS4x12_TMU_TRESHOLD_TEMP_FALL));
+#endif
+
+	/* TMU core enable */
+	tmp = __raw_readl(info->tmu_base + EXYNOS4_TMU_CONTROL);
+	tmp |= (TMUCORE_ENABLE | (0x6 << 20)); /* MUX_ADDR : 110b */
+	__raw_writel(tmp, info->tmu_base + EXYNOS4_TMU_CONTROL);
+
+	/* Because temperature sensing time is appro 940us,
+	 * tmu is enabled and 1st valid sample can get 1ms after.
+	*/
+	mdelay(1);
+	/* check interrupt status register */
+	pr_debug("tmu interrupt status: 0x%08x\n",
+			__raw_readl(info->tmu_base + EXYNOS4_TMU_INTSTAT));
+
+	/* THRESHOLD_TEMP_RISE0, RISE1, RISE2 interrupt enable */
+	__raw_writel(INTEN_RISE0 | INTEN_RISE1 | INTEN_RISE2,
+			info->tmu_base + EXYNOS4_TMU_INTEN);
+
+#if defined(CONFIG_TC_VOLTAGE)
+	tmp = __raw_readl(info->tmu_base + EXYNOS4_TMU_INTEN);
+	tmp |= INTEN_FALL0;
+	__raw_writel(tmp, info->tmu_base + EXYNOS4_TMU_INTEN);
+#endif
+
+	return 0;
+}
+
+static int tmu_initialize(struct platform_device *pdev)
+{
+	struct s5p_tmu_info *info = platform_get_drvdata(pdev);
+	unsigned int tmp;
+	unsigned ret;
+
+	/* check if sensing is idle */
+	tmp = (__raw_readl(info->tmu_base + EXYNOS4_TMU_STATUS) & 0x1);
+	if (!tmp) {
+		pr_err("failed to start tmu driver\n");
+		return -ENOENT;
+	}
+
+	if (soc_is_exynos4210())
+		ret = exynos4210_tmu_init(info);
+	else
+		ret = exynos4x12_tmu_init(info);
+
+	return ret;
+}
+
+static irqreturn_t exynos4x12_tmu_irq_handler(int irq, void *id)
+{
+	struct s5p_tmu_info *info = id;
+	unsigned int status;
+
+	disable_irq_nosync(irq);
+
+	status = __raw_readl(info->tmu_base + EXYNOS4_TMU_INTSTAT) & 0x1FFFF;
+	pr_info("EXYNOS4x12_tmu interrupt: INTSTAT = 0x%08x\n", status);
+
+	/* To handle multiple interrupt pending,
+	 * interrupt by high temperature are serviced with priority.
+	*/
+#if defined(CONFIG_TC_VOLTAGE)
+	if (status & INTSTAT_FALL0) {
+		info->tmu_state = TMU_STATUS_TC;
+
+		__raw_writel(INTCLEARALL, info->tmu_base + EXYNOS4_TMU_INTCLEAR);
+		exynos_interrupt_enable(info, 0);
+	} else if (status & INTSTAT_RISE2) {
+		info->tmu_state = TMU_STATUS_TRIPPED;
+		__raw_writel(INTCLEAR_RISE2, info->tmu_base + EXYNOS4_TMU_INTCLEAR);
+#else
+	if (status & INTSTAT_RISE2) {
+		info->tmu_state = TMU_STATUS_TRIPPED;
+		__raw_writel(INTCLEAR_RISE2, info->tmu_base + EXYNOS4_TMU_INTCLEAR);
+#endif
+	} else if (status & INTSTAT_RISE1) {
+		info->tmu_state = TMU_STATUS_WARNING;
+		__raw_writel(INTCLEAR_RISE1, info->tmu_base + EXYNOS4_TMU_INTCLEAR);
+	} else if (status & INTSTAT_RISE0) {
+		info->tmu_state = TMU_STATUS_THROTTLED;
+		__raw_writel(INTCLEAR_RISE0, info->tmu_base + EXYNOS4_TMU_INTCLEAR);
+	} else {
+		pr_err("%s: interrupt error\n", __func__);
+		__raw_writel(INTCLEARALL, info->tmu_base + EXYNOS4_TMU_INTCLEAR);
+		queue_delayed_work_on(0, tmu_monitor_wq,
+			&info->polling, info->sampling_rate / 2);
+		return -ENODEV;
+	}
+
+	/* read current temperature & save */
+	info->last_temperature =  get_curr_temp(info);
+
+	queue_delayed_work_on(0, tmu_monitor_wq, &info->polling,
+		info->sampling_rate);
+
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t exynos4210_tmu_irq_handler(int irq, void *id)
+{
+	struct s5p_tmu_info *info = id;
+	unsigned int status;
+
+	disable_irq_nosync(irq);
+
+	status = __raw_readl(info->tmu_base + EXYNOS4_TMU_INTSTAT);
+	pr_info("EXYNOS4212_tmu interrupt: INTSTAT = 0x%08x\n", status);
+
+	/* To handle multiple interrupt pending,
+	 * interrupt by high temperature are serviced with priority.
+	*/
+	if (status & TMU_INTSTAT2) {
+		info->tmu_state = TMU_STATUS_TRIPPED;
+		__raw_writel(INTCLEAR2, info->tmu_base + EXYNOS4_TMU_INTCLEAR);
+	} else if (status & TMU_INTSTAT1) {
+		info->tmu_state = TMU_STATUS_WARNING;
+		__raw_writel(INTCLEAR1, info->tmu_base + EXYNOS4_TMU_INTCLEAR);
+	} else if (status & TMU_INTSTAT0) {
+		info->tmu_state = TMU_STATUS_THROTTLED;
+		__raw_writel(INTCLEAR0, info->tmu_base + EXYNOS4_TMU_INTCLEAR);
+	} else {
+		pr_err("%s: interrupt error\n", __func__);
+		__raw_writel(INTCLEARALL, info->tmu_base + EXYNOS4_TMU_INTCLEAR);
+		queue_delayed_work_on(0, tmu_monitor_wq,
+			&info->polling, info->sampling_rate / 2);
+		return -ENODEV;
+	}
+
+	/* read current temperature & save */
+	info->last_temperature =  get_curr_temp(info);
+
+	queue_delayed_work_on(0, tmu_monitor_wq, &info->polling,
+		info->sampling_rate);
+
+	return IRQ_HANDLED;
+}
+
+#ifdef CONFIG_TMU_SYSFS
+static ssize_t s5p_tmu_show_curr_temp(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct s5p_tmu_info *info = dev_get_drvdata(dev);
+	unsigned int curr_temp;
+
+	curr_temp = get_curr_temp(info);
+	curr_temp *= 10;
+	pr_info("curr temp = %d\n", curr_temp);
+
+	return sprintf(buf, "%d\n", curr_temp);
+}
+static DEVICE_ATTR(curr_temp, S_IRUGO, s5p_tmu_show_curr_temp, NULL);
+#endif
+
+static int __devinit s5p_tmu_probe(struct platform_device *pdev)
+{
+	struct s5p_tmu_info *info;
+	struct s5p_platform_tmu *pdata;
+	struct resource *res;
+	unsigned int mask = (enable_mask & ENABLE_DBGMASK);
+	int ret = 0;
+
+	pr_debug("%s: probe=%p\n", __func__, pdev);
+
+	info = kzalloc(sizeof(struct s5p_tmu_info), GFP_KERNEL);
+	if (!info) {
+		dev_err(&pdev->dev, "failed to alloc memory!\n");
+		ret = -ENOMEM;
+		goto err_nomem;
+	}
+	platform_set_drvdata(pdev, info);
+
+	info->dev = &pdev->dev;
+	info->tmu_state = TMU_STATUS_INIT;
+
+	/* set cpufreq limit level at 1st_throttle & 2nd throttle */
+	pdata = info->dev->platform_data;
+	if (pdata->cpufreq.limit_1st_throttle)
+		exynos_cpufreq_get_level(pdata->cpufreq.limit_1st_throttle,
+				&info->cpufreq_level_1st_throttle);
+
+	if (pdata->cpufreq.limit_2nd_throttle)
+		exynos_cpufreq_get_level(pdata->cpufreq.limit_2nd_throttle,
+				&info->cpufreq_level_2nd_throttle);
+
+	pr_info("@@@ %s: cpufreq_limit: 1st_throttle: %u, 2nd_throttle = %u\n",
+		__func__, info->cpufreq_level_1st_throttle,
+		 info->cpufreq_level_2nd_throttle);
+
+#if defined(CONFIG_TC_VOLTAGE) /* Temperature compensated voltage */
+	if (exynos_find_cpufreq_level_by_volt(pdata->temp_compensate.arm_volt,
+		&info->cpulevel_tc) < 0) {
+		dev_err(&pdev->dev, "cpufreq_get_level error\n");
+		ret = -EINVAL;
+		goto err_nomem;
+	}
+#ifdef CONFIG_BUSFREQ_OPP
+	/* To lock bus frequency in OPP mode */
+	info->bus_dev = dev_get("exynos-busfreq");
+	if (info->bus_dev < 0) {
+		dev_err(&pdev->dev, "Failed to get_dev\n");
+		ret = -EINVAL;
+		goto err_nomem;
+	}
+	if (exynos4x12_find_busfreq_by_volt(pdata->temp_compensate.bus_volt,
+		&info->busfreq_tc)) {
+		dev_err(&pdev->dev, "get_busfreq_value error\n");
+		ret = -EINVAL;
+		goto err_nomem;
+	}
+#endif
+	pr_info("%s: cpufreq_level[%u], busfreq_value[%u]\n",
+		 __func__, info->cpulevel_tc, info->busfreq_tc);
+#endif
+	/* Map auto_refresh_rate of normal & tq0 mode */
+	info->auto_refresh_tq0 =
+		get_refresh_interval(FREQ_IN_PLL, AUTO_REFRESH_PERIOD_TQ0);
+	info->auto_refresh_normal =
+		get_refresh_interval(FREQ_IN_PLL, AUTO_REFRESH_PERIOD_NORMAL);
+
+	/* To poll current temp, set sampling rate to ONE second sampling */
+	info->sampling_rate  = usecs_to_jiffies(1000 * 1000);
+	/* 10sec monitroing */
+	info->monitor_period = usecs_to_jiffies(10000 * 1000);
+
+	/* support test mode */
+	if (mask & ENABLE_TEST_MODE)
+		set_temperature_params(info);
+	else
+		print_temperature_params(info);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(&pdev->dev, "failed to get memory region resource\n");
+		ret = -ENODEV;
+		goto err_nores;
+	}
+
+	info->ioarea = request_mem_region(res->start,
+			res->end-res->start + 1, pdev->name);
+	if (!(info->ioarea)) {
+		dev_err(&pdev->dev, "failed to reserve memory region\n");
+		ret = -EBUSY;
+		goto err_nores;
+	}
+
+	info->tmu_base = ioremap(res->start, (res->end - res->start) + 1);
+	if (!(info->tmu_base)) {
+		dev_err(&pdev->dev, "failed ioremap()\n");
+		ret = -ENOMEM;
+		goto err_nomap;
+	}
+	tmu_monitor_wq = create_freezable_workqueue(dev_name(&pdev->dev));
+	if (!tmu_monitor_wq) {
+		pr_info("Creation of tmu_monitor_wq failed\n");
+		ret = -ENOMEM;
+		goto err_wq;
+	}
+
+	/* To support periodic temprature monitoring */
+	if (mask & ENABLE_TEMP_MON) {
+		INIT_DELAYED_WORK_DEFERRABLE(&info->monitor,
+					exynos4_poll_cur_temp);
+		queue_delayed_work_on(0, tmu_monitor_wq, &info->monitor,
+			info->monitor_period);
+	}
+	INIT_DELAYED_WORK_DEFERRABLE(&info->polling, exynos4_handler_tmu_state);
+
+	info->irq = platform_get_irq(pdev, 0);
+	if (info->irq < 0) {
+		dev_err(&pdev->dev, "no irq for thermal %d\n", info->irq);
+		ret = -EINVAL;
+		goto err_irq;
+	}
+
+	if (soc_is_exynos4210())
+		ret = request_irq(info->irq, exynos4210_tmu_irq_handler,
+				IRQF_DISABLED,  "s5p-tmu interrupt", info);
+	else
+		ret = request_irq(info->irq, exynos4x12_tmu_irq_handler,
+				IRQF_DISABLED,  "s5p-tmu interrupt", info);
+
+	if (ret) {
+		dev_err(&pdev->dev, "request_irq is failed. %d\n", ret);
+		goto err_irq;
+	}
+
+	ret = device_create_file(&pdev->dev, &dev_attr_temperature);
+	if (ret != 0) {
+		pr_err("Failed to create temperatue file: %d\n", ret);
+		goto err_sysfs_file1;
+	}
+
+	ret = device_create_file(&pdev->dev, &dev_attr_tmu_state);
+	if (ret != 0) {
+		pr_err("Failed to create tmu_state file: %d\n", ret);
+		goto err_sysfs_file2;
+	}
+	ret = device_create_file(&pdev->dev, &dev_attr_lot_id);
+	if (ret != 0) {
+		pr_err("Failed to create lot id file: %d\n", ret);
+		goto err_sysfs_file3;
+	}
+
+	ret = tmu_initialize(pdev);
+	if (ret)
+		goto err_init;
+
+#ifdef CONFIG_TMU_SYSFS
+	ret = device_create_file(&pdev->dev, &dev_attr_curr_temp);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "Failed to create sysfs group\n");
+		goto err_init;
+	}
+#endif
+
+#ifdef CONFIG_TMU_DEBUG
+	ret = device_create_file(&pdev->dev, &dev_attr_print_state);
+	if (ret) {
+		dev_err(&pdev->dev, "Failed to create tmu sysfs group\n\n");
+		return ret;
+	}
+#endif
+
+#if defined(CONFIG_TC_VOLTAGE)
+	/* s/w workaround for fast service when interrupt is not occured,
+	 * such as current temp is lower than tc interrupt temperature
+	 * or current temp is continuosly increased.
+	*/
+	if (get_curr_temp(info) <= pdata->ts.start_tc) {
+		if (exynos_tc_volt(info, 1) < 0)
+			pr_err("TMU: lock error!\n");
+	}
+	if (mali_voltage_lock_init())
+		pr_err("Failed to initialize mail voltage lock.\n");
+#endif
+
+	/* initialize tmu_state */
+	queue_delayed_work_on(0, tmu_monitor_wq, &info->polling,
+		info->sampling_rate);
+
+	return ret;
+
+err_init:
+	device_remove_file(&pdev->dev, &dev_attr_lot_id);
+
+err_sysfs_file3:
+	device_remove_file(&pdev->dev, &dev_attr_tmu_state);
+
+err_sysfs_file2:
+	device_remove_file(&pdev->dev, &dev_attr_temperature);
+
+err_sysfs_file1:
+	if (info->irq >= 0)
+		free_irq(info->irq, info);
+
+err_irq:
+	destroy_workqueue(tmu_monitor_wq);
+
+err_wq:
+	iounmap(info->tmu_base);
+
+err_nomap:
+	release_resource(info->ioarea);
+	kfree(info->ioarea);
+
+err_nores:
+	kfree(info);
+	info = NULL;
+
+err_nomem:
+	dev_err(&pdev->dev, "initialization failed.\n");
+
+	return ret;
+}
+
+static int __devinit s5p_tmu_remove(struct platform_device *pdev)
+{
+	struct s5p_tmu_info *info = platform_get_drvdata(pdev);
+
+	cancel_delayed_work(&info->polling);
+	destroy_workqueue(tmu_monitor_wq);
+
+	device_remove_file(&pdev->dev, &dev_attr_temperature);
+	device_remove_file(&pdev->dev, &dev_attr_tmu_state);
+
+	if (info->irq >= 0)
+		free_irq(info->irq, info);
+
+	iounmap(info->tmu_base);
+
+	release_resource(info->ioarea);
+	kfree(info->ioarea);
+
+	kfree(info);
+	info = NULL;
+
+	pr_info("%s is removed\n", dev_name(&pdev->dev));
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int s5p_tmu_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct s5p_tmu_info *info = platform_get_drvdata(pdev);
+
+	if (!info)
+		return -EAGAIN;
+
+	/* save register value */
+	info->reg_save[0] = __raw_readl(info->tmu_base + EXYNOS4_TMU_CONTROL);
+	info->reg_save[1] = __raw_readl(info->tmu_base + EXYNOS4_TMU_SAMPLING_INTERNAL);
+	info->reg_save[2] = __raw_readl(info->tmu_base + EXYNOS4_TMU_COUNTER_VALUE0);
+	info->reg_save[3] = __raw_readl(info->tmu_base + EXYNOS4_TMU_COUNTER_VALUE1);
+	info->reg_save[4] = __raw_readl(info->tmu_base + EXYNOS4_TMU_INTEN);
+
+	if (soc_is_exynos4210()) {
+		info->reg_save[5] =
+			__raw_readl(info->tmu_base + EXYNOS4210_TMU_THRESHOLD_TEMP);
+		info->reg_save[6] =
+			 __raw_readl(info->tmu_base + EXYNOS4210_TMU_TRIG_LEVEL0);
+		info->reg_save[7] =
+			 __raw_readl(info->tmu_base + EXYNOS4210_TMU_TRIG_LEVEL1);
+		info->reg_save[8] =
+			 __raw_readl(info->tmu_base + EXYNOS4210_TMU_TRIG_LEVEL2);
+		info->reg_save[9] =
+			 __raw_readl(info->tmu_base + EXYNOS4210_TMU_TRIG_LEVEL3);
+	} else {
+		info->reg_save[5] =
+			__raw_readl(info->tmu_base + EXYNOS4x12_TMU_TRESHOLD_TEMP_RISE);
+#if defined(CONFIG_TC_VOLTAGE)
+		info->reg_save[6] = __raw_readl(info->tmu_base
+					+ EXYNOS4x12_TMU_TRESHOLD_TEMP_FALL);
+#endif
+	}
+	disable_irq(info->irq);
+
+	return 0;
+}
+
+static int s5p_tmu_resume(struct platform_device *pdev)
+{
+	struct s5p_tmu_info *info = platform_get_drvdata(pdev);
+	struct s5p_platform_tmu *data = info->dev->platform_data;
+
+	if (!info)
+		return -EAGAIN;
+
+	/* restore tmu register value */
+	__raw_writel(info->reg_save[0], info->tmu_base + EXYNOS4_TMU_CONTROL);
+	__raw_writel(info->reg_save[1],
+			info->tmu_base + EXYNOS4_TMU_SAMPLING_INTERNAL);
+	__raw_writel(info->reg_save[2],
+			info->tmu_base + EXYNOS4_TMU_COUNTER_VALUE0);
+	__raw_writel(info->reg_save[3],
+			info->tmu_base + EXYNOS4_TMU_COUNTER_VALUE1);
+
+	if (soc_is_exynos4210()) {
+		__raw_writel(info->reg_save[5],
+			info->tmu_base + EXYNOS4210_TMU_THRESHOLD_TEMP);
+		__raw_writel(info->reg_save[6],
+			info->tmu_base + EXYNOS4210_TMU_TRIG_LEVEL0);
+		__raw_writel(info->reg_save[7],
+			info->tmu_base + EXYNOS4210_TMU_TRIG_LEVEL1);
+		__raw_writel(info->reg_save[8],
+			info->tmu_base + EXYNOS4210_TMU_TRIG_LEVEL2);
+		__raw_writel(info->reg_save[9],
+			info->tmu_base + EXYNOS4210_TMU_TRIG_LEVEL3);
+	} else {
+		__raw_writel(info->reg_save[5],
+			info->tmu_base + EXYNOS4x12_TMU_TRESHOLD_TEMP_RISE);
+#if defined(CONFIG_TC_VOLTAGE)
+		__raw_writel(info->reg_save[6],
+			info->tmu_base + EXYNOS4x12_TMU_TRESHOLD_TEMP_FALL);
+#endif
+	}
+	__raw_writel(info->reg_save[4],
+			info->tmu_base + EXYNOS4_TMU_INTEN);
+
+#if defined(CONFIG_TC_VOLTAGE)
+	/* s/w workaround for fast service when interrupt is not occured,
+	 * such as current temp is lower than tc interrupt temperature
+	 * or current temp is continuosly increased..
+	*/
+	mdelay(1);
+	if (get_curr_temp(info) <= data->ts.start_tc) {
+		if (exynos_tc_volt(info, 1) < 0)
+			pr_err("TMU: lock error!\n");
+	}
+#endif
+	/* Find out tmu_state after wakeup */
+	queue_delayed_work_on(0, tmu_monitor_wq, &info->polling, 0);
+
+	return 0;
+}
+#else
+#define s5p_tmu_suspend	NULL
+#define s5p_tmu_resume	NULL
+#endif
+
+static struct platform_driver s5p_tmu_driver = {
+	.probe		= s5p_tmu_probe,
+	.remove		= s5p_tmu_remove,
+	.suspend	= s5p_tmu_suspend,
+	.resume		= s5p_tmu_resume,
+	.driver		= {
+		.name   = "s5p-tmu",
+		.owner  = THIS_MODULE,
+	},
+};
+
+static int __init s5p_tmu_driver_init(void)
+{
+	return platform_driver_register(&s5p_tmu_driver);
+}
+
+static void __exit s5p_tmu_driver_exit(void)
+{
+	platform_driver_unregister(&s5p_tmu_driver);
+}
+late_initcall(s5p_tmu_driver_init);
+module_exit(s5p_tmu_driver_exit);
diff --git a/arch/arm/mach-exynos/tmu_exynos.c b/arch/arm/mach-exynos/tmu_exynos.c
new file mode 100644
index 0000000..47f580d
--- /dev/null
+++ b/arch/arm/mach-exynos/tmu_exynos.c
@@ -0,0 +1,423 @@
+/* linux/arch/arm/mach-exynos/tmu_exynos.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *      http://www.samsung.com
+ *
+ * EXYNOS - Thermal Management support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/fs.h>
+#include <linux/string.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/power_supply.h>
+#include <linux/interrupt.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/slab.h>
+
+#include <linux/irq.h>
+
+#include <mach/regs-tmu.h>
+#include <mach/cpufreq.h>
+#include <plat/s5p-tmu.h>
+
+#define MUX_ADDR_VALUE 6
+
+enum tmu_status_t {
+	TMU_STATUS_INIT = 0,
+	TMU_STATUS_NORMAL,
+	TMU_STATUS_THROTTLED,
+	TMU_STATUS_WARNING,
+	TMU_STATUS_TRIPPED,
+};
+
+static struct workqueue_struct  *tmu_monitor_wq;
+
+static int tmu_tripped_cb(void)
+{
+	struct power_supply *psy = power_supply_get_by_name("battery");
+	union power_supply_propval value;
+
+	if (!psy) {
+		pr_err("%s:fail to get batter ps\n", __func__);
+		return -ENODEV;
+	}
+
+	value.intval = TMU_STATUS_TRIPPED;
+
+	return psy->set_property(psy, POWER_SUPPLY_PROP_TEMP_AMBIENT, &value);
+}
+
+static unsigned char get_cur_temp(struct tmu_info *info)
+{
+	unsigned char curr_temp;
+	unsigned char temperature;
+
+	/* After reading temperature code from register, compensating
+	 * its value and calculating celsius temperatue,
+	 * get current temperatue.
+	 */
+	curr_temp = __raw_readl(info->tmu_base + CURRENT_TEMP) & 0xff;
+
+	/* compensate and calculate current temperature */
+	temperature = curr_temp - info->te1 + TMU_DC_VALUE;
+	if (temperature < 0) {
+		/* temperature code range are between min 25 and 125 */
+		pr_err("%s: Current temperature is unreasonable value\n", __func__);
+	}
+
+	return temperature;
+}
+
+#ifdef CONFIG_TMU_DEBUG
+static void cur_temp_monitor(struct work_struct *work)
+{
+	unsigned char cur_temp;
+	struct delayed_work *delayed_work = to_delayed_work(work);
+	struct tmu_info *info =
+		 container_of(delayed_work, struct tmu_info, monitor);
+
+	cur_temp = get_cur_temp(info);
+	pr_info("current temp = %d\n", cur_temp);
+	queue_delayed_work_on(0, tmu_monitor_wq, &info->monitor,
+			usecs_to_jiffies(1000 * 1000));
+}
+#endif
+
+static void tmu_monitor(struct work_struct *work)
+{
+	struct delayed_work *delayed_work = to_delayed_work(work);
+	struct tmu_info *info =
+		container_of(delayed_work, struct tmu_info, polling);
+	struct tmu_data *data = info->dev->platform_data;
+	unsigned char cur_temp;
+
+#ifdef CONFIG_TMU_DEBUG
+	cancel_delayed_work(&info->monitor);
+#endif
+	cur_temp = get_cur_temp(info);
+	pr_info("Current: %dc, FLAG=%d\n",
+			cur_temp, info->tmu_state);
+
+	switch (info->tmu_state) {
+	case TMU_STATUS_NORMAL:
+#ifdef CONFIG_TMU_DEBUG
+		queue_delayed_work_on(0, tmu_monitor_wq, &info->monitor,
+		usecs_to_jiffies(1000 * 1000));
+#endif
+		cancel_delayed_work(&info->polling);
+		enable_irq(info->irq);
+		break;
+	case TMU_STATUS_THROTTLED:
+		if (cur_temp >= data->ts.start_warning)
+			info->tmu_state = TMU_STATUS_WARNING;
+		else if (cur_temp > data->ts.stop_throttle &&
+				cur_temp < data->ts.start_warning)
+			exynos_cpufreq_upper_limit(DVFS_LOCK_ID_TMU,
+				data->cpulimit.throttle_freq);
+		else if (cur_temp <= data->ts.stop_throttle) {
+			info->tmu_state = TMU_STATUS_NORMAL;
+			exynos_cpufreq_upper_limit_free(DVFS_LOCK_ID_TMU);
+		}
+		queue_delayed_work_on(0, tmu_monitor_wq,
+		&info->polling, usecs_to_jiffies(500 * 1000));
+		break;
+	case TMU_STATUS_WARNING:
+		if (cur_temp >= data->ts.start_tripping)
+			info->tmu_state = TMU_STATUS_TRIPPED;
+		else if (cur_temp > data->ts.stop_warning && \
+				cur_temp < data->ts.start_tripping)
+			exynos_cpufreq_upper_limit(DVFS_LOCK_ID_TMU,
+				data->cpulimit.warning_freq);
+		else if (cur_temp <= data->ts.stop_warning) {
+			info->tmu_state = TMU_STATUS_THROTTLED;
+			exynos_cpufreq_upper_limit_free(DVFS_LOCK_ID_TMU);
+		}
+		queue_delayed_work_on(0, tmu_monitor_wq,
+				&info->polling, usecs_to_jiffies(500 * 1000));
+		break;
+	case TMU_STATUS_TRIPPED:
+		tmu_tripped_cb();
+		queue_delayed_work_on(0, tmu_monitor_wq,
+				&info->polling, usecs_to_jiffies(5000 * 1000));
+	default:
+	    break;
+	}
+	return;
+}
+
+static void s5p_pm_tmu_save(struct tmu_info *info)
+{
+	info->reg_save[0] = __raw_readl(info->tmu_base + TMU_CON);
+	info->reg_save[1] = __raw_readl(info->tmu_base + SAMPLING_INTERNAL);
+	info->reg_save[2] = __raw_readl(info->tmu_base + CNT_VALUE0);
+	info->reg_save[3] = __raw_readl(info->tmu_base + CNT_VALUE1);
+	info->reg_save[4] = __raw_readl(info->tmu_base + THD_TEMP_RISE);
+	info->reg_save[5] = __raw_readl(info->tmu_base + THD_TEMP_FALL);
+	info->reg_save[6] = __raw_readl(info->tmu_base + INTEN);
+}
+
+static void s5p_pm_tmu_restore(struct tmu_info *info)
+{
+	__raw_writel(info->reg_save[0], info->tmu_base + TMU_CON);
+	__raw_writel(info->reg_save[1], info->tmu_base + SAMPLING_INTERNAL);
+	__raw_writel(info->reg_save[2], info->tmu_base + CNT_VALUE0);
+	__raw_writel(info->reg_save[3], info->tmu_base + CNT_VALUE1);
+	__raw_writel(info->reg_save[4], info->tmu_base + THD_TEMP_RISE);
+	__raw_writel(info->reg_save[5], info->tmu_base + THD_TEMP_FALL);
+	__raw_writel(info->reg_save[6], info->tmu_base + INTEN);
+}
+
+static int tmu_start(struct tmu_info *info)
+{
+	struct tmu_data *data = info->dev->platform_data;
+	unsigned int te_temp, con;
+	unsigned int throttle_temp, waring_temp, trip_temp;
+	unsigned int cooling_temp;
+	unsigned int rising_value;
+	unsigned int reg_info; /* debugging */
+
+	/* must reload for using efuse value at EXYNOS4212 */
+	__raw_writel(TRIMINFO_RELOAD, info->tmu_base + TRIMINFO_CON);
+
+	/* get the compensation parameter */
+	te_temp = __raw_readl(info->tmu_base + TRIMINFO);
+	info->te1 = te_temp & TRIM_INFO_MASK;
+	info->te2 = ((te_temp >> 8) & TRIM_INFO_MASK);
+
+	if ((EFUSE_MIN_VALUE > info->te1) || (info->te1 > EFUSE_MAX_VALUE)
+		||  (info->te2 != 0))
+		info->te1 = data->efuse_value;
+
+	/*Get RISING & FALLING Threshold value */
+	throttle_temp = data->ts.start_throttle
+			+ info->te1 - TMU_DC_VALUE;
+	waring_temp = data->ts.start_warning
+			+ info->te1 - TMU_DC_VALUE;
+	trip_temp =  data->ts.start_tripping
+			+ info->te1 - TMU_DC_VALUE;
+	cooling_temp = 0;
+
+	rising_value = (throttle_temp | (waring_temp<<8) | \
+			(trip_temp<<16));
+
+	/* Set interrupt level */
+	__raw_writel(rising_value, info->tmu_base + THD_TEMP_RISE);
+	__raw_writel(cooling_temp, info->tmu_base + THD_TEMP_FALL);
+
+	/* Set frequecny level */
+	exynos_cpufreq_get_level(800000, &data->cpulimit.throttle_freq);
+	exynos_cpufreq_get_level(200000, &data->cpulimit.warning_freq);
+
+	/* Need to initail regsiter setting after getting parameter info */
+	/* [28:23] vref [11:8] slope - Tunning parameter */
+	__raw_writel(data->slope, info->tmu_base + TMU_CON);
+
+	pr_info("TMU initialization is successful!!");
+	reg_info = __raw_readl(info->tmu_base + THD_TEMP_RISE);
+	pr_info("RISING THRESHOLD = %x", reg_info);
+
+	__raw_writel(INTCLEARALL, info->tmu_base + INTCLEAR);
+		/* TMU core enable */
+	con = __raw_readl(info->tmu_base + TMU_CON);
+	con |= (MUX_ADDR_VALUE<<20 | CORE_EN);
+
+	__raw_writel(con, info->tmu_base + TMU_CON);
+
+	/*LEV0 LEV1 LEV2 interrupt enable */
+	__raw_writel(INTEN_RISE0 | INTEN_RISE1 | INTEN_RISE2,	\
+		     info->tmu_base + INTEN);
+	return 0;
+}
+
+static int tmu_initialize(struct platform_device *pdev)
+{
+	struct tmu_info *info = platform_get_drvdata(pdev);
+	unsigned int en;
+
+	en = (__raw_readl(info->tmu_base + TMU_STATUS) & 0x1);
+
+	if (!en) {
+		dev_err(&pdev->dev, "failed to start tmu drvier\n");
+		return -ENOENT;
+	}
+
+	return tmu_start(info);
+}
+
+static irqreturn_t tmu_irq(int irq, void *id)
+{
+	struct tmu_info *info = id;
+	unsigned int status;
+
+	disable_irq_nosync(irq);
+
+	status = __raw_readl(info->tmu_base + INTSTAT);
+
+	if (status & INTSTAT_RISE0) {
+		pr_info("Throttling interrupt occured!!!!\n");
+		__raw_writel(INTCLEAR_RISE0, info->tmu_base + INTCLEAR);
+		info->tmu_state = TMU_STATUS_THROTTLED;
+		queue_delayed_work_on(0, tmu_monitor_wq,
+				&info->polling, usecs_to_jiffies(500 * 1000));
+	} else if (status & INTSTAT_RISE1) {
+		pr_info("Warning interrupt occured!!!!\n");
+		__raw_writel(INTCLEAR_RISE1, info->tmu_base + INTCLEAR);
+		info->tmu_state = TMU_STATUS_WARNING;
+		queue_delayed_work_on(0, tmu_monitor_wq,
+				&info->polling, usecs_to_jiffies(500 * 1000));
+	} else if (status & INTSTAT_RISE2) {
+		pr_info("Tripping interrupt occured!!!!\n");
+		info->tmu_state = TMU_STATUS_TRIPPED;
+		__raw_writel(INTCLEAR_RISE2, info->tmu_base + INTCLEAR);
+		tmu_tripped_cb();
+	} else {
+		pr_err("%s: TMU interrupt error\n", __func__);
+		return -ENODEV;
+	}
+
+	return IRQ_HANDLED;
+}
+
+static int __devinit tmu_probe(struct platform_device *pdev)
+{
+	struct tmu_info *info;
+	struct resource *res;
+	int	ret = 0;
+
+	pr_debug("%s: probe=%p\n", __func__, pdev);
+
+	info = kzalloc(sizeof(struct tmu_info), GFP_KERNEL);
+	if (!info) {
+		dev_err(&pdev->dev, "failed to alloc memory!\n");
+		ret = -ENOMEM;
+		goto err_nores;
+	}
+	platform_set_drvdata(pdev, info);
+
+	info->dev = &pdev->dev;
+	info->tmu_state = TMU_STATUS_INIT;
+
+	info->irq = platform_get_irq(pdev, 0);
+	if (info->irq < 0) {
+		dev_err(&pdev->dev, "no irq for thermal\n");
+		return -ENOENT;
+	}
+
+	ret = request_irq(info->irq, tmu_irq,
+			IRQF_DISABLED,  "tmu interrupt", info);
+	if (ret) {
+		dev_err(&pdev->dev, "IRQ%d error %d\n", info->irq, ret);
+		goto err_noirq;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (res == NULL) {
+		dev_err(&pdev->dev, "failed to get memory region resource\n");
+		return -ENOENT;
+	}
+
+	info->ioarea = request_mem_region(res->start,
+			res->end-res->start+1, pdev->name);
+	if (!(info->ioarea)) {
+		dev_err(&pdev->dev, "failed to reserve memory region\n");
+		ret = -ENOENT;
+		goto err_nores;
+	}
+
+	info->tmu_base = ioremap(res->start, (res->end - res->start) + 1);
+	if (!(info->tmu_base)) {
+		dev_err(&pdev->dev, "failed ioremap()\n");
+		ret = -EINVAL;
+		goto err_nomap;
+	}
+
+	tmu_monitor_wq = create_freezable_workqueue("tmu");
+	if (!tmu_monitor_wq) {
+		pr_info("Creation of tmu_monitor_wq failed\n");
+		return -EFAULT;
+	}
+
+#ifdef CONFIG_TMU_DEBUG
+	INIT_DELAYED_WORK_DEFERRABLE(&info->monitor, cur_temp_monitor);
+	queue_delayed_work_on(0, tmu_monitor_wq, &info->monitor,
+			usecs_to_jiffies(1000 * 1000));
+#endif
+	INIT_DELAYED_WORK_DEFERRABLE(&info->polling, tmu_monitor);
+
+	ret = tmu_initialize(pdev);
+	if (ret)
+		goto err_noinit;
+
+	return ret;
+
+err_noinit:
+	free_irq(info->irq, info);
+err_noirq:
+	iounmap(info->tmu_base);
+err_nomap:
+	release_resource(info->ioarea);
+err_nores:
+	return ret;
+}
+
+static int __devinit tmu_remove(struct platform_device *pdev)
+{
+	struct tmu_info *info = platform_get_drvdata(pdev);
+
+	free_irq(info->irq, (void *)pdev);
+	iounmap(info->tmu_base);
+
+	pr_info("%s is removed\n", dev_name(&pdev->dev));
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int tmu_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct tmu_info *info = platform_get_drvdata(pdev);
+	s5p_pm_tmu_save(info);
+
+	return 0;
+}
+
+static int tmu_resume(struct platform_device *pdev)
+{
+	struct tmu_info *info = platform_get_drvdata(pdev);
+	s5p_pm_tmu_restore(info);
+
+	return 0;
+}
+
+#else
+#define s5p_tmu_suspend	NULL
+#define s5p_tmu_resume	NULL
+#endif
+
+static struct platform_driver tmu_driver = {
+	.probe		= tmu_probe,
+	.remove		= tmu_remove,
+	.suspend	= tmu_suspend,
+	.resume		= tmu_resume,
+	.driver		= {
+		.name	=	"s5p-tmu",
+		.owner	=	THIS_MODULE,
+		},
+};
+
+static int __init tmu_driver_init(void)
+{
+	return platform_driver_register(&tmu_driver);
+}
+
+late_initcall(tmu_driver_init);
diff --git a/arch/arm/mach-exynos/u1-gpio.c b/arch/arm/mach-exynos/u1-gpio.c
new file mode 100644
index 0000000..434ccd2
--- /dev/null
+++ b/arch/arm/mach-exynos/u1-gpio.c
@@ -0,0 +1,678 @@
+#include <linux/gpio.h>
+#include <linux/serial_core.h>
+#include <plat/devs.h>
+#include <plat/gpio-cfg.h>
+#include <plat/regs-serial.h>
+#include <mach/gpio.h>
+#include "u1.h"
+
+struct gpio_init_data {
+	uint num;
+	uint cfg;
+	uint val;
+	uint pud;
+	uint drv;
+};
+
+static struct gpio_init_data u1_init_gpios[] = {
+#if defined(CONFIG_MACH_U1_KOR_LGT)
+	{EXYNOS4_GPA0(4), S3C_GPIO_INPUT,  S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4_GPA0(5), S3C_GPIO_INPUT,  S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4_GPC0(7), S3C_GPIO_INPUT,  S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+#endif
+#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE)
+	{EXYNOS4_GPB(4), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* TDMB_INT */
+	{EXYNOS4_GPB(5), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* TDMB_RST_N */
+	{EXYNOS4_GPC0(1), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* TDMB_EN */
+#endif
+#if defined(CONFIG_ISDBT_FC8100)
+	{EXYNOS4210_GPE1(5), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* ISDBT_RST_N */
+	{EXYNOS4_GPC0(1), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* ISDBT_EN */
+#endif
+	{EXYNOS4_GPC1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* CODEC_SDA_1.8V */
+	{EXYNOS4_GPC1(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* CODEC_SCL_1.8V */
+#if defined(CONFIG_MACH_U1_KOR_LGT)
+	{EXYNOS4_GPD0(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+#endif
+	{EXYNOS4_GPD0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* MHL_SDA_2.8V */
+	{EXYNOS4_GPD0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* MHL_SCL_2.8V */
+	{EXYNOS4_GPD1(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* 8M_CAM_SDA_2.8V */
+	{EXYNOS4_GPD1(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* 8M_CAM_SCL_2.8V */
+	{EXYNOS4_GPD1(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* SENSE_SDA_2.8V */
+	{EXYNOS4_GPD1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* SENSE_SCL_2.8V */
+#if defined(CONFIG_MACH_U1_KOR_LGT)
+	{EXYNOS4210_GPE0(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4210_GPE0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4210_GPE0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4210_GPE0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4210_GPE1(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* MHL_SCL_1.8V */
+	{EXYNOS4210_GPE1(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* MHL_SDA_1.8V */
+	{EXYNOS4210_GPE3(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4210_GPE3(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4210_GPE3(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4210_GPE3(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4210_GPE3(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4210_GPE3(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4210_GPE3(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4210_GPE3(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4210_GPE4(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4210_GPE4(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4210_GPE4(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4210_GPE4(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4210_GPE4(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4210_GPE4(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4210_GPE4(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4210_GPE4(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4210_GPJ0(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4210_GPJ0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4210_GPJ0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4210_GPJ0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4210_GPJ0(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4210_GPJ0(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4210_GPJ0(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4210_GPJ0(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4210_GPJ1(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4210_GPJ1(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4210_GPJ1(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+#endif
+
+	{EXYNOS4_GPK1(1), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPK2(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* PS_ALS_SDA_2.8V */
+	{EXYNOS4_GPK3(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_CMD */
+	{EXYNOS4_GPK3(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* PS_ALS_SCL_2.8V */
+	{EXYNOS4_GPK3(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(0) */
+	{EXYNOS4_GPK3(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(1) */
+	{EXYNOS4_GPK3(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(2) */
+	{EXYNOS4_GPK3(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(3) */
+#if defined(CONFIG_MACH_U1_KOR_LGT)
+	{EXYNOS4_GPL0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+	{EXYNOS4_GPL1(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
+#endif
+	{EXYNOS4_GPX0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* VOL_UP */
+	{EXYNOS4_GPX0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* VOL_DOWN */
+	{EXYNOS4_GPX0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* GPIO_BOOT_MODE */
+	{EXYNOS4_GPX2(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* GPIO_FUEL_ALERT */
+	{EXYNOS4_GPX3(1), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPX3(2), S3C_GPIO_SFN(GPIO_DET_35_AF), S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* GPIO_DET_35 */
+	{EXYNOS4_GPX3(3), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPX3(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1},
+#if defined(CONFIG_TARGET_LOCALE_NTT)
+	{EXYNOS4_GPY0(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+#endif
+	{EXYNOS4_GPY0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY0(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY0(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY1(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY1(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY1(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY2(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY2(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1,},
+	{EXYNOS4_GPY2(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY2(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY2(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY2(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY4(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY5(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY5(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY5(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY5(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY5(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY5(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY5(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY5(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY6(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY6(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY6(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY6(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY6(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY6(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY6(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY6(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+};
+
+/* this table only for u1 board */
+static unsigned int u1_sleep_gpio_table[][3] = {
+	{EXYNOS4_GPA0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},
+	{EXYNOS4_GPA0(1), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(3), S3C_GPIO_SLP_OUT1,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+#if defined(CONFIG_MACH_U1_KOR_LGT)
+	{EXYNOS4_GPA0(6), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+#elif defined(CONFIG_TARGET_LOCALE_NTT)
+	{EXYNOS4_GPA0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4_GPA0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+#if defined(CONFIG_TARGET_LOCALE_NTT)
+	{EXYNOS4_GPA0(7), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4_GPA0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+#if defined(CONFIG_MACH_U1_KOR_LGT)
+	{EXYNOS4_GPA1(0), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4_GPA1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+#endif
+	{EXYNOS4_GPA1(1), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA1(2), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA1(3), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+#if defined(CONFIG_MACH_U1_KOR_LGT)
+	{EXYNOS4_GPA1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4_GPA1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+#endif
+	{EXYNOS4_GPA1(5), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE)
+	{EXYNOS4_GPB(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+#elif defined(CONFIG_TARGET_LOCALE_NTT)
+	{EXYNOS4_GPB(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPB(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPB(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPB(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPB(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPB(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+#else
+	{EXYNOS4_GPB(0), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPB(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPB(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+	{EXYNOS4_GPB(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPC0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE)
+	{EXYNOS4_GPC0(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+#elif defined(CONFIG_ISDBT_FC8100)
+	{EXYNOS4_GPC0(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4_GPC0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+	{EXYNOS4_GPC0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPC0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPC0(4), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+#if defined(CONFIG_MACH_U1_KOR_LGT)
+	{EXYNOS4_GPC1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4_GPC1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+#endif
+	{EXYNOS4_GPC1(1), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+#if defined(CONFIG_MACH_U1_KOR_LGT)
+	{EXYNOS4_GPC1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4_GPC1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+#endif
+	{EXYNOS4_GPC1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPC1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPD0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPD0(1), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPD0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPD0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPD1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPD1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPD1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPD1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+#if !defined(CONFIG_VIDEO_TSI)
+	{EXYNOS4210_GPE0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#if defined(CONFIG_MACH_U1_KOR_LGT)
+	{EXYNOS4210_GPE0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#else
+	{EXYNOS4210_GPE0(1), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+#endif
+#if defined(CONFIG_MACH_U1_KOR_LGT)
+	{EXYNOS4210_GPE0(2), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4210_GPE0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+#if defined(CONFIG_MACH_U1_KOR_LGT)
+	{EXYNOS4210_GPE0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE0(4), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4210_GPE0(3), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE0(4), S3C_GPIO_SLP_OUT1,  S3C_GPIO_PULL_NONE},
+#endif
+#endif /*end CONFIG_VIDEO_TSI*/
+	{EXYNOS4210_GPE1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE1(4), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+#if !defined(CONFIG_VIDEO_TSI)
+#if defined(CONFIG_MACH_U1_KOR_LGT)
+	{EXYNOS4210_GPE1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE1(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE1(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4210_GPE1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE1(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE1(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+#endif /* end CONFIG_VIDEO_TSI */
+
+#if defined(CONFIG_MACH_U1_KOR_LGT)
+	{EXYNOS4210_GPE2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4210_GPE2(0), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_DOWN},
+#endif
+	{EXYNOS4210_GPE2(1), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE2(2), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+#if defined(CONFIG_MACH_U1_KOR_LGT)
+	{EXYNOS4210_GPE2(3), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4210_GPE2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+	{EXYNOS4210_GPE2(4), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE2(5), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4210_GPE3(0), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE3(1), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE3(2), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE3(3), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE3(4), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE3(5), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE3(6), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE3(7), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4210_GPE4(0), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE4(1), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE4(2), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE4(3), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE4(4), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE4(5), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE4(6), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE4(7), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPF0(0), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF0(1), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF0(2), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF0(3), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF0(4), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF0(5), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF0(6), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF0(7), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPF1(0), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF1(1), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF1(2), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF1(3), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF1(4), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF1(5), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF1(6), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF1(7), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPF2(0), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF2(1), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF2(2), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF2(3), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF2(4), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF2(5), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF2(6), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF2(7), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPF3(0), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF3(1), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF3(2), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF3(3), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF3(4), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4210_GPJ0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPJ0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPJ0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPJ0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPJ0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPJ0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPJ0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPJ0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4210_GPJ1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPJ1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPJ1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPJ1(3), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPJ1(4), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPK0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPK1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK1(1), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK1(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPK2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPK3(0), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPL0(0), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL0(1), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPL0(3), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL0(4), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL0(5), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL0(6), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL0(7), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPL1(0), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPL1(2), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPL2(0), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL2(1), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL2(2), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPL2(4), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+#if defined(CONFIG_PN544) && (defined(CONFIG_TARGET_LOCALE_KOR) \
+	|| defined(CONFIG_TARGET_LOCALE_EUR_U1_NFC))
+	{EXYNOS4_GPL2(6), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL2(7), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+#elif defined(CONFIG_TARGET_LOCALE_NTT)
+	{EXYNOS4_GPL2(6), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL2(7), S3C_GPIO_SLP_INPUT,  S3C_GPIO_PULL_DOWN},
+#else
+#if defined(CONFIG_MACH_U1_KOR_LGT)
+	{EXYNOS4_GPL2(6), S3C_GPIO_SLP_OUT1,  S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4_GPL2(6), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+#endif
+	{EXYNOS4_GPL2(7), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+#endif
+
+#if defined(CONFIG_PN544) && defined(CONFIG_TARGET_LOCALE_KOR)
+	{EXYNOS4_GPY0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+#else
+#if defined(CONFIG_MACH_U1_KOR_LGT)
+	{EXYNOS4_GPY0(0), S3C_GPIO_SLP_OUT1,  S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4_GPY0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+#endif
+	{EXYNOS4_GPY0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+#endif
+#if defined(CONFIG_MACH_U1_KOR_LGT)
+	{EXYNOS4_GPY0(2), S3C_GPIO_SLP_OUT1,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY0(3), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY0(4), S3C_GPIO_SLP_OUT1,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY0(5), S3C_GPIO_SLP_OUT1,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPY1(0), S3C_GPIO_SLP_OUT1,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY1(1), S3C_GPIO_SLP_OUT1,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+#else
+	{EXYNOS4_GPY0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPY1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+
+	{EXYNOS4_GPY2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#if defined(CONFIG_MACH_U1_KOR_LGT)
+	{EXYNOS4_GPY2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+#else
+	{EXYNOS4_GPY2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+	{EXYNOS4_GPY2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+#if defined(CONFIG_MACH_U1_KOR_LGT)
+	{EXYNOS4_GPY3(0), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(1), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(2), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(3), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(4), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(5), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(6), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(7), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPY4(0), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(1), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(2), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(3), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(4), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(5), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY4(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPY5(0), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY5(1), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY5(2), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY5(3), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY5(4), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY5(5), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY5(6), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY5(7), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPY6(0), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPY6(1), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPY6(2), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPY6(3), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPY6(4), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPY6(5), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPY6(6), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE}, /* NC */
+	{EXYNOS4_GPY6(7), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE}, /* NC */
+#else
+	{EXYNOS4_GPY3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(1), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(3), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY3(5), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(6), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(7), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPY4(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(2), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(3), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY4(5), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(6), S3C_GPIO_SLP_OUT1,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(7), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPY5(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY5(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPY6(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY6(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY6(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY6(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY6(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY6(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY6(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY6(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+#endif
+
+	{EXYNOS4_GPZ(0), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPZ(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPZ(2), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPZ(3), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPZ(4), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPZ(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPZ(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+};
+
+void u1_config_gpio_table(void)
+{
+	u32 i, gpio;
+
+	for (i = 0; i < ARRAY_SIZE(u1_init_gpios); i++) {
+		gpio = u1_init_gpios[i].num;
+		s3c_gpio_cfgpin(gpio, u1_init_gpios[i].cfg);
+		s3c_gpio_setpull(gpio, u1_init_gpios[i].pud);
+
+		if (u1_init_gpios[i].val != S3C_GPIO_SETPIN_NONE)
+			gpio_set_value(gpio, u1_init_gpios[i].val);
+
+		s5p_gpio_set_drvstr(gpio, u1_init_gpios[i].drv);
+	}
+}
+
+static void config_sleep_gpio_table(int array_size,
+				    unsigned int (*gpio_table)[3])
+{
+	u32 i, gpio;
+
+	for (i = 0; i < array_size; i++) {
+		gpio = gpio_table[i][0];
+		s3c_gpio_slp_cfgpin(gpio, gpio_table[i][1]);
+		s3c_gpio_slp_setpull_updown(gpio, gpio_table[i][2]);
+	}
+}
+
+void u1_config_sleep_gpio_table(void)
+{
+	config_sleep_gpio_table(ARRAY_SIZE(u1_sleep_gpio_table),
+			u1_sleep_gpio_table);
+}
diff --git a/arch/arm/mach-exynos/u1-otg.c b/arch/arm/mach-exynos/u1-otg.c
new file mode 100644
index 0000000..a70c69d
--- /dev/null
+++ b/arch/arm/mach-exynos/u1-otg.c
@@ -0,0 +1,218 @@
+
+#include <mach/regs-usb-phy.h>
+#include "../../../drivers/usb/gadget/s3c_udc.h"
+#include <plat/s5p-otghost.h>
+#include <plat/usb-phy.h>
+
+#define PHY_ENABLE	(1 << 0)
+#define PHY_DISABLE	(0)
+
+static int usb_status;
+static u64 s3c_device_usb_otghcd_dmamask = 0xffffffffUL;
+
+#ifdef USE_S3C_OTG_PHY
+static int c210_otg_host_phy_init(int mode)
+{
+	struct clk *otg_clk;
+	u32 value;
+	int err;
+
+	otg_clk = clk_get(NULL, "usbotg");
+	if (IS_ERR(otg_clk)) {
+		pr_err("otg: Failed to get otg clock\n");
+		return PTR_ERR(otg_clk);
+	}
+
+	err = clk_enable(otg_clk);
+	if (err) {
+		pr_err("otg: Failed to enable otg clock\n");
+		clk_put(otg_clk);
+		return err;
+	}
+
+	writel(PHY_ENABLE, S5P_USBOTG_PHY_CONTROL);
+
+	value = readl(EXYNOS4_PHYCLK) & (~(1<<4) | (7<<0));
+	pr_info("otg : phy clk 0x%x\n", value);
+	writel(value, EXYNOS4_PHYCLK);
+
+	value = readl(EXYNOS4_PHYPWR) & (~(7<<3) & ~(1<<0));
+	pr_info("otg : phy pwr 0x%x\n", value);
+	writel(value, EXYNOS4_PHYPWR);
+
+	value = readl(EXYNOS4_RSTCON) & (~(3<<1) | (1<<0));
+	writel(value, EXYNOS4_RSTCON);
+	udelay(10);
+	value &= ~(7<<0);
+	writel(value, EXYNOS4_RSTCON);
+
+	clk_put(otg_clk);
+
+	return 0;
+}
+
+static int c210_otg_host_phy_exit(int mode)
+{
+	struct clk *otg_clk;
+
+	otg_clk = clk_get(NULL, "usbotg");
+	if (IS_ERR(otg_clk)) {
+		pr_err("otg: Failed to get otg clock\n");
+		return PTR_ERR(otg_clk);
+	}
+
+	writel((readl(EXYNOS4_PHYPWR) | PHY0_NORMAL_MASK),
+			EXYNOS4_PHYPWR);
+
+	writel(PHY_DISABLE, S5P_USBOTG_PHY_CONTROL);
+
+	clk_disable(otg_clk);
+	clk_put(otg_clk);
+
+	return 0;
+}
+#else
+static int c210_otg_host_phy_init(int mode)
+{
+	s5p_usb_phy_init(&s3c_device_usbgadget, S5P_USB_PHY_OTGHOST);
+	return 0;
+}
+static int c210_otg_host_phy_exit(int mode)
+{
+	s5p_usb_phy_exit(&s3c_device_usbgadget, S5P_USB_PHY_OTGHOST);
+	return 0;
+}
+#endif
+
+static void c210_host_notify_cb(int mode)
+{
+	pr_info("otg host_notify : %d\n", mode);
+	host_state_notify(&host_notifier_pdata.ndev, mode);
+}
+
+static struct sec_otghost_data otghost_data = {
+	.clk_usage = 0,
+	.set_pwr_cb = usb_otg_accessory_power,
+	.sec_whlist_table_num = 1,
+	.start = 0,
+	.stop = 0,
+
+	.phy_init = c210_otg_host_phy_init,
+	.phy_exit = c210_otg_host_phy_exit,
+	.host_notify_cb = c210_host_notify_cb,
+};
+
+static struct resource s3c_usb_otghcd_resource[] = {
+	[0] = {
+		.start = S5P_PA_HSOTG,
+		.end   = S5P_PA_HSOTG + SZ_4K - 1,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = IRQ_USB_HSOTG,
+		.end   = IRQ_USB_HSOTG,
+		.flags = IORESOURCE_IRQ,
+	}
+};
+
+static struct platform_device s3c_device_usb_otghcd = {
+	.name		=	"s3c_otghcd",
+	.id		=	-1,
+	.num_resources	=	ARRAY_SIZE(s3c_usb_otghcd_resource),
+	.resource	=	s3c_usb_otghcd_resource,
+	.dev = {
+		.platform_data	=	&otghost_data,
+		.dma_mask	=	&s3c_device_usb_otghcd_dmamask,
+		.coherent_dma_mask	=	0xffffffffUL,
+	}
+};
+
+static char *get_usb_cable_string(int mode)
+{
+	switch (mode) {
+	case USB_CABLE_DETACHED: return "USB Cable Detached";
+	case USB_CABLE_ATTACHED: return "USB Cable Attached";
+	case USB_OTGHOST_ATTACHED: return "Host Attached";
+	case USB_OTGHOST_DETACHED: return "Host Detached";
+	case USB_CABLE_DETACHED_WITHOUT_NOTI:
+		return "USB Cable Detached without noti";
+	default: return "Unknown cable state";
+	}
+}
+
+
+static void c210_otghost_start(struct s3c_udc *dev)
+{
+	host_notifier_pdata.ndev.mode = NOTIFY_HOST_MODE;
+	host_state_notify(&host_notifier_pdata.ndev, NOTIFY_HOST_ADD);
+
+	pr_info("otg start: udc %p, regs %p\n", dev, dev->regs);
+	free_irq(IRQ_USB_HSOTG, dev);
+
+	if (otghost_data.start)
+		otghost_data.start((u32)dev->regs);
+}
+
+static int c210_otghost_stop(struct s3c_udc *dev)
+{
+	struct s5p_usbgadget_platdata *pdata;
+	int ret = 0;
+
+	host_notifier_pdata.ndev.mode = NOTIFY_NONE_MODE;
+	host_state_notify(&host_notifier_pdata.ndev, NOTIFY_HOST_REMOVE);
+
+	if (otghost_data.stop)
+		otghost_data.stop();
+
+	pdata = (struct s5p_usbgadget_platdata *)
+		s3c_device_usbgadget.dev.platform_data;
+
+	pr_info("otg pdata %p, irq_cb %p, irq %p\n",
+			pdata, &pdata->udc_irq, pdata->udc_irq);
+
+	if (pdata && pdata->udc_irq) {
+		pr_info("otg request_irq irq %p, dev %p\n",
+				pdata->udc_irq, dev);
+
+		ret = request_irq(IRQ_USB_HSOTG,
+				pdata->udc_irq, 0, "s3c-udc", dev);
+		if (ret != 0) {
+			pr_info("otg host - can't get irq %i, err %d\n",
+					IRQ_USB_HSOTG, ret);
+			return -1;
+		}
+	}
+
+	return ret;
+}
+
+static int c210_change_usb_mode(struct s3c_udc *dev, int mode)
+{
+	pr_info("otg change mode : %s --> %s (%d --> %d) %s\n",
+			get_usb_cable_string(usb_status),
+			get_usb_cable_string(mode),
+			usb_status, mode,
+			dev->udc_enabled ? "enabled" : "disabled"
+			);
+
+	switch (mode) {
+	case USB_CABLE_DETACHED:
+		if (dev->udc_enabled)
+			usb_gadget_vbus_disconnect(&dev->gadget);
+		break;
+	case USB_CABLE_ATTACHED:
+		if (!dev->udc_enabled)
+			usb_gadget_vbus_connect(&dev->gadget);
+		break;
+	case USB_OTGHOST_ATTACHED:
+		c210_otghost_start(dev);
+		break;
+
+	case USB_OTGHOST_DETACHED:
+		c210_otghost_stop(dev);
+		break;
+	}
+	usb_status = mode;
+	return 0;
+}
+
diff --git a/arch/arm/mach-exynos/u1-panel.c b/arch/arm/mach-exynos/u1-panel.c
new file mode 100644
index 0000000..2da82ab
--- /dev/null
+++ b/arch/arm/mach-exynos/u1-panel.c
@@ -0,0 +1,1665 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/ld9040.h>
+#include "u1-panel.h"
+
+
+static const unsigned short SEQ_SM2_ELVSS_44[] = {
+	0xB2, 0x15,
+	DATA_ONLY, 0x15,
+	DATA_ONLY, 0x15,
+	DATA_ONLY, 0x15,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_SM2_ELVSS_37[] = {
+	0xB2, 0x1C,
+	DATA_ONLY, 0x1C,
+	DATA_ONLY, 0x1C,
+	DATA_ONLY, 0x1C,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_SM2_ELVSS_34[] = {
+	0xB2, 0x1F,
+	DATA_ONLY, 0x1F,
+	DATA_ONLY, 0x1F,
+	DATA_ONLY, 0x1F,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_SM2_ELVSS_30[] = {
+	0xB2, 0x23,
+	DATA_ONLY, 0x23,
+	DATA_ONLY, 0x23,
+	DATA_ONLY, 0x23,
+	ENDDEF, 0x00
+};
+
+static const unsigned short *SEQ_SM2_ELVSS_set[] = {
+	SEQ_SM2_ELVSS_30,
+	SEQ_SM2_ELVSS_34,
+	SEQ_SM2_ELVSS_37,
+	SEQ_SM2_ELVSS_44,
+};
+
+
+static const unsigned short SEQ_PWR_CTRL[] = {
+	0xF4, 0x0A,
+
+	DATA_ONLY, 0x87,
+	DATA_ONLY, 0x25,
+	DATA_ONLY, 0x6A,
+	DATA_ONLY, 0x44,
+	DATA_ONLY, 0x02,
+	ENDDEF, 0x00
+};
+
+
+/* LD9040, 4.27", SM2 A1 Panel Gamma Data */
+static const unsigned short ld9040_sm2_a1_22_300[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA3,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xA6,
+	DATA_ONLY, 0xA6,
+	DATA_ONLY, 0x9F,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xA8,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xA3,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCE,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_22_290[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xA8,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA1,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xA6,
+	DATA_ONLY, 0xA7,
+	DATA_ONLY, 0xA0,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xA2,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCC,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_22_280[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA0,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xA6,
+	DATA_ONLY, 0xA8,
+	DATA_ONLY, 0xA2,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xA4,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCA,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_22_270[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xBD,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x9E,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xA6,
+	DATA_ONLY, 0xA8,
+	DATA_ONLY, 0xA3,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xA4,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC8,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_22_260[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xA8,
+	DATA_ONLY, 0xBD,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x9C,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xA5,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xA2,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xA4,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC5,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_22_250[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xBC,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x9A,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xA5,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xA4,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xA6,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC2,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_22_240[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xBE,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x96,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xA4,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xA4,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xA6,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xBE,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_22_230[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xBE,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x94,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xA4,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xA3,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xA6,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xBB,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_22_220[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xBE,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x91,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xA3,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xA4,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA6,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xA7,
+	DATA_ONLY, 0xBC,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB7,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_22_210[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xBF,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x8E,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xA3,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xA6,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA3,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xA8,
+	DATA_ONLY, 0xBC,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB4,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+
+static const unsigned short ld9040_sm2_a1_22_200[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xC0,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x8B,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xA2,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xA5,
+	DATA_ONLY, 0xBC,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA0,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xA7,
+	DATA_ONLY, 0xBC,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB1,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_22_190[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x88,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xA1,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xA6,
+	DATA_ONLY, 0xBD,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x9C,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xA8,
+	DATA_ONLY, 0xBD,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xAD,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_22_180[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x85,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xA0,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xA6,
+	DATA_ONLY, 0xBD,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x99,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xBE,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA9,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+
+static const unsigned short ld9040_sm2_a1_22_170[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x82,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0x9F,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xA6,
+	DATA_ONLY, 0xBE,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x95,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xBF,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA5,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_22_160[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x7F,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0x9D,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xA7,
+	DATA_ONLY, 0xBF,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x91,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xC0,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA1,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_22_150[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x7C,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0x9B,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xA8,
+	DATA_ONLY, 0xBF,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x8E,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x9D,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_22_140[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x78,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0x9B,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x89,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x99,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_22_130[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x75,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0x9A,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x86,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x95,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_22_120[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x71,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0x97,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x82,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x90,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_22_110[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x6D,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0x96,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x7D,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x8C,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+
+static const unsigned short ld9040_sm2_a1_22_100[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xA8,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x69,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0x93,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x79,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x87,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+
+static const unsigned short ld9040_sm2_a1_22_90[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xA7,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x65,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0x92,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x74,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x82,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+
+
+static const unsigned short ld9040_sm2_a1_22_80[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xA6,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x60,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0x8E,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x6F,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x7C,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+
+static const unsigned short ld9040_sm2_a1_22_70[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xA4,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x5B,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0x8C,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x69,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x76,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+
+static const unsigned short ld9040_sm2_a1_22_60[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0x9F,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x56,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0x89,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x63,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x6F,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_22_50[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0x9E,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x50,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0x88,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x5D,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x68,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_22_40[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0x96,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x49,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0x85,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x55,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x60,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_22_30_dimming[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0x81,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xCD,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x41,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0x80,
+	DATA_ONLY, 0xA7,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x4C,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x56,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+
+static const unsigned short ld9040_sm2_a1_19_300[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xBF,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA4,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xBE,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xBE,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCF,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_290[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA2,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xBF,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xC0,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCD,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_280[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA0,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xBF,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCA,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_270[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x9E,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xC0,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC8,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_260[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x9C,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xC0,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC5,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_250[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x99,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC1,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_240[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x96,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xBE,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_230[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x94,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xBB,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_220[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x91,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA6,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB7,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_210[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x8F,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA3,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB5,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_200[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xBC,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x8C,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA0,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB1,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_190[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xBC,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x89,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x9C,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xAD,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_180[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xBD,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x85,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x99,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA9,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_170[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xBE,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x82,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x95,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA5,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_160[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x7F,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x91,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA1,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_150[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0xBC,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x7C,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x8D,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x9D,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_140[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0xBC,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x79,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x89,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x99,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_130[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xBC,
+	DATA_ONLY, 0xBD,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x75,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x86,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x95,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_120[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0xBE,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x71,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x81,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x90,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_110[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xBE,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x6E,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x7D,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x8C,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_100[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xBE,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x6A,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x78,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x87,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_90[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xC0,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x66,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x74,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x82,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_80[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xCD,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x61,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xA7,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xCE,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x6E,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xCD,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x7C,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_70[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x5C,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0xA4,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xCE,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x69,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xCD,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x75,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_60[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0xBC,
+	DATA_ONLY, 0xCF,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x55,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0x9F,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xD0,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x63,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xD0,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x6E,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_50[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0xBE,
+	DATA_ONLY, 0xCF,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x4F,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0x9B,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xCF,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x5D,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xD0,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x67,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_40[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0xBF,
+	DATA_ONLY, 0xD2,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x48,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0x97,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xD1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x55,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xD2,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x5F,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a1_19_30_dimming[] = {
+	0xF9, 0x2E,
+	DATA_ONLY, 0xA7,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0xC0,
+	DATA_ONLY, 0xD5,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x40,
+	DATA_ONLY, 0x36,
+	DATA_ONLY, 0x93,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xD2,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x4C,
+	DATA_ONLY, 0x2E,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xD2,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x56,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+
+/* LD9040, 4.27", SM2 A1 Panel Gamma Table */
+static const unsigned short *psm2_a1_22Gamma_set[] = {
+	ld9040_sm2_a1_22_30_dimming,
+	ld9040_sm2_a1_22_40,
+	ld9040_sm2_a1_22_70,
+	ld9040_sm2_a1_22_90,
+	ld9040_sm2_a1_22_100,
+	ld9040_sm2_a1_22_110,
+	ld9040_sm2_a1_22_120,
+	ld9040_sm2_a1_22_130,
+	ld9040_sm2_a1_22_140,
+	ld9040_sm2_a1_22_150,
+	ld9040_sm2_a1_22_160,
+	ld9040_sm2_a1_22_170,
+	ld9040_sm2_a1_22_180,
+	ld9040_sm2_a1_22_190,
+	ld9040_sm2_a1_22_200,
+	ld9040_sm2_a1_22_210,
+	ld9040_sm2_a1_22_220,
+	ld9040_sm2_a1_22_230,
+	ld9040_sm2_a1_22_240,
+	ld9040_sm2_a1_22_250,
+	ld9040_sm2_a1_22_300,
+};
+
+static const unsigned short *psm2_a1_19Gamma_set[] = {
+	ld9040_sm2_a1_19_30_dimming,
+	ld9040_sm2_a1_19_40,
+	ld9040_sm2_a1_19_70,
+	ld9040_sm2_a1_19_90,
+	ld9040_sm2_a1_19_100,
+	ld9040_sm2_a1_19_110,
+	ld9040_sm2_a1_19_120,
+	ld9040_sm2_a1_19_130,
+	ld9040_sm2_a1_19_140,
+	ld9040_sm2_a1_19_150,
+	ld9040_sm2_a1_19_160,
+	ld9040_sm2_a1_19_170,
+	ld9040_sm2_a1_19_180,
+	ld9040_sm2_a1_19_190,
+	ld9040_sm2_a1_19_200,
+	ld9040_sm2_a1_19_210,
+	ld9040_sm2_a1_19_220,
+	ld9040_sm2_a1_19_230,
+	ld9040_sm2_a1_19_240,
+	ld9040_sm2_a1_19_250,
+	ld9040_sm2_a1_19_300,
+};
+
+
+struct ld9040_panel_data u1_panel_data = {
+	.seq_user_set = SEQ_USER_SETTING,
+	.seq_displayctl_set = SEQ_DISPCTL,
+	.seq_gtcon_set = SEQ_GTCON,
+	.seq_panelcondition_set = SEQ_PANEL_CONDITION,
+	.seq_pwrctl_set = SEQ_PWR_CTRL,
+	.display_on = SEQ_DISPON,
+	.display_off = SEQ_DISPOFF,
+	.sleep_in = SEQ_SLPIN,
+	.sleep_out = SEQ_SLPOUT,
+	.acl_on = SEQ_ACL_ON,
+	.acl_table = ACL_cutoff_set,
+	.elvss_on = SEQ_ELVSS_ON,
+	.elvss_table = SEQ_SM2_ELVSS_set,
+	.gamma19_table = psm2_a1_19Gamma_set,
+	.gamma22_table = psm2_a1_22Gamma_set,
+	.lcdtype = LCDTYPE_SM2_A1,
+};
+
diff --git a/arch/arm/mach-exynos/u1-panel.h b/arch/arm/mach-exynos/u1-panel.h
new file mode 100644
index 0000000..6a367cb
--- /dev/null
+++ b/arch/arm/mach-exynos/u1-panel.h
@@ -0,0 +1,146 @@
+/*
+ * arch/arm/mach-exynos/u1-panel.h
+ */
+
+#ifndef __C1_PANEL_H__
+#define __C1_PANEL_H__
+
+#define SLEEPMSEC		0x1000
+#define ENDDEF			0x2000
+#define	DEFMASK		0xFF00
+#define COMMAND_ONLY		0xFE
+#define DATA_ONLY		0xFF
+
+
+static const unsigned short SEQ_USER_SETTING[] = {
+	0xF0, 0x5A,
+
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_DISPCTL[] = {
+	0xF2, 0x02,
+
+	DATA_ONLY, 0x06,
+	DATA_ONLY, 0x0A,
+	DATA_ONLY, 0x10,
+	DATA_ONLY, 0x10,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_GTCON[] = {
+	0xF7, 0x09,
+
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_PANEL_CONDITION[] = {
+	0xF8, 0x05,
+	DATA_ONLY, 0x5E,
+	DATA_ONLY, 0x96,
+	DATA_ONLY, 0x6B,
+	DATA_ONLY, 0x7D,
+	DATA_ONLY, 0x0D,
+	DATA_ONLY, 0x3F,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x32,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x07,
+	DATA_ONLY, 0x05,
+	DATA_ONLY, 0x1F,
+	DATA_ONLY, 0x1F,
+	DATA_ONLY, 0x1F,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_SLPOUT[] = {
+	0x11, COMMAND_ONLY,
+	SLEEPMSEC, 120,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_SLPIN[] = {
+	0x10, COMMAND_ONLY,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_DISPON[] = {
+	0x29, COMMAND_ONLY,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_DISPOFF[] = {
+	0x28, COMMAND_ONLY,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_ELVSS_ON[] = {
+	0xB1, 0x0F,
+
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x16,
+	ENDDEF, 0x00
+};
+
+
+static const unsigned short SEQ_ACL_ON[] = {
+	0xC0, 0x01,
+
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_ACL_OFF[] = {
+	0xC0, 0x00,
+
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_ACL_40P[] = {
+	0xC1, 0x4D,
+
+	DATA_ONLY, 0x96,	DATA_ONLY, 0x1D,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x01,	DATA_ONLY, 0xDF,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x03,	DATA_ONLY, 0x1F,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,	DATA_ONLY, 0x01,
+	DATA_ONLY, 0x06,	DATA_ONLY, 0x11,	DATA_ONLY, 0x1A,	DATA_ONLY, 0x20,
+	DATA_ONLY, 0x25,	DATA_ONLY, 0x29,	DATA_ONLY, 0x2D,	DATA_ONLY, 0x30,
+	DATA_ONLY, 0x33,	DATA_ONLY, 0x35,
+
+	0xC0, 0x01,
+
+	ENDDEF, 0x00
+};
+
+
+static const unsigned short SEQ_ACL_50P[] = {
+	0xC1, 0x4D,
+
+	DATA_ONLY, 0x96,	DATA_ONLY, 0x1D,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x01,	DATA_ONLY, 0xDF,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x03,	DATA_ONLY, 0x1F,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,	DATA_ONLY, 0x00,	DATA_ONLY, 0x01,
+	DATA_ONLY, 0x08,	DATA_ONLY, 0x16,	DATA_ONLY, 0x22,	DATA_ONLY, 0x2B,
+	DATA_ONLY, 0x31,	DATA_ONLY, 0x37,	DATA_ONLY, 0x3B,	DATA_ONLY, 0x3F,
+	DATA_ONLY, 0x43,	DATA_ONLY, 0x46,
+
+	0xC0, 0x01,
+
+	ENDDEF, 0x00
+};
+
+static const unsigned short *ACL_cutoff_set[] = {
+	SEQ_ACL_OFF,
+	SEQ_ACL_40P,
+	SEQ_ACL_50P,
+};
+
+#endif
diff --git a/arch/arm/mach-exynos/u1-panel_a2.c b/arch/arm/mach-exynos/u1-panel_a2.c
new file mode 100644
index 0000000..d36ff8a
--- /dev/null
+++ b/arch/arm/mach-exynos/u1-panel_a2.c
@@ -0,0 +1,1668 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/ld9040.h>
+#include "u1-panel.h"
+
+
+static const unsigned short SEQ_SM2_ELVSS_44[] = {
+	0xB2, 0x15,
+
+	DATA_ONLY, 0x15,
+	DATA_ONLY, 0x15,
+	DATA_ONLY, 0x15,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_SM2_ELVSS_37[] = {
+	0xB2, 0x1C,
+
+	DATA_ONLY, 0x1C,
+	DATA_ONLY, 0x1C,
+	DATA_ONLY, 0x1C,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_SM2_ELVSS_34[] = {
+	0xB2, 0x1F,
+
+	DATA_ONLY, 0x1F,
+	DATA_ONLY, 0x1F,
+	DATA_ONLY, 0x1F,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_SM2_ELVSS_30[] = {
+	0xB2, 0x23,
+
+	DATA_ONLY, 0x23,
+	DATA_ONLY, 0x23,
+	DATA_ONLY, 0x23,
+	ENDDEF, 0x00
+};
+
+static const unsigned short *SEQ_SM2_ELVSS_set[] = {
+	SEQ_SM2_ELVSS_30,
+	SEQ_SM2_ELVSS_34,
+	SEQ_SM2_ELVSS_37,
+	SEQ_SM2_ELVSS_44,
+};
+
+
+static const unsigned short SEQ_PWR_CTRL_SM2_A2[] = {
+	0xF4, 0x0A,
+
+	DATA_ONLY, 0xA7,
+	DATA_ONLY, 0x25,
+	DATA_ONLY, 0x6A,
+	DATA_ONLY, 0x44,
+	DATA_ONLY, 0x02,
+	ENDDEF, 0x00
+};
+
+
+/* LD9040, 4.27", SM2 A2 Panel Gamma Data */
+static const unsigned short ld9040_sm2_a2_22_300[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xBC,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xA6,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xA7,
+	DATA_ONLY, 0xBC,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCC,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_22_290[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xA6,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xBD,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0xA7,
+	DATA_ONLY, 0xBD,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xA8,
+	DATA_ONLY, 0xBE,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCA,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_22_280[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xA7,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xBD,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA6,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0xA7,
+	DATA_ONLY, 0xBE,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xA8,
+	DATA_ONLY, 0xBE,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC7,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_22_270[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xA8,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xBF,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA3,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0xA8,
+	DATA_ONLY, 0xBF,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC0,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xA8,
+	DATA_ONLY, 0xBF,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC4,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_22_260[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xA7,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xBE,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA1,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xA7,
+	DATA_ONLY, 0xBF,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xBD,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xA8,
+	DATA_ONLY, 0xBF,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC1,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_22_250[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xA6,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xC0,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x9E,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xC0,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xC0,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xBE,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_22_240[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xA7,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xC0,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x9C,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xC0,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xC0,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xBB,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_22_230[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xA7,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xC0,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x99,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xA8,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB7,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_22_220[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xA7,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x96,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xA7,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB4,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_22_210[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xA6,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x94,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xA7,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB1,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_22_200[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xA7,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x91,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xA7,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xAE,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_22_190[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xA6,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x8E,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xA6,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA8,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xAB,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_22_180[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xA6,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x8B,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xA5,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA4,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA7,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_22_170[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xA5,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x89,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xA3,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA1,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA4,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_22_160[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xA5,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x85,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xA2,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x9D,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x9F,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_22_150[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xA6,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x82,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xA1,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x99,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x9B,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_22_140[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xA5,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x7F,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xA0,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x95,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x97,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_22_130[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xA5,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x7C,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0x9F,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x91,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x93,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_22_120[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xA4,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x77,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0x9D,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x8C,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x8E,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_22_110[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xA4,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x73,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0x9C,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x88,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x89,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_22_100[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xA4,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x70,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0x9B,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x85,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x86,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_22_90[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xA3,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x6B,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0x97,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xCD,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x7F,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xCE,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x80,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_22_80[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xA2,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x67,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0x95,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xCE,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x7A,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xCE,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x7B,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_22_70[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xA2,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x62,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0x94,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xCE,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x74,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xCF,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x75,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_22_60[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xA0,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xCE,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x5C,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0x8E,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xCF,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x6E,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xBC,
+	DATA_ONLY, 0xD1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x6E,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_22_50[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xA0,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xCE,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x57,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0x8C,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xD0,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x68,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xBF,
+	DATA_ONLY, 0xD1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x68,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_22_40[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0x9D,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xCF,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x50,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0x88,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xD1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x60,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0xD3,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x60,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_22_30_dimming[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0x91,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xD1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x48,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0x7A,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xBD,
+	DATA_ONLY, 0xD4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x57,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0xD5,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x56,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_19_300[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xA7,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xA6,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xA7,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCC,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_19_290[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xA7,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA5,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xA6,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xA8,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCA,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_19_280[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xA8,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA2,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xA6,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xA8,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC8,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_19_270[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xA7,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA0,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xA6,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xBE,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xA7,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC5,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_19_260[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xA8,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x9D,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xA8,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC1,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_19_250[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xA8,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x9A,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xA7,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xBD,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_19_240[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xA8,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x97,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xA8,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xBA,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_19_230[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x95,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB7,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_19_220[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x91,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB3,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_19_210[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x8E,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xAF,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_19_200[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x8B,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA7,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xAB,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_19_190[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x88,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA3,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA8,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_19_180[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x85,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x9F,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA4,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_19_170[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x82,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x9B,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA0,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_19_160[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x7F,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x97,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xBC,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x9C,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_19_150[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x7B,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x93,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xBD,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x97,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_19_140[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x77,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x8F,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xBC,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x92,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_19_130[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x73,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x8B,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xBC,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x8D,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_19_120[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xCD,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x6F,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x86,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xBC,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x89,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_19_110[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xCD,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x6B,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xCD,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x81,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xBF,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x84,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_19_100[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xCD,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x66,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xAD,
+	DATA_ONLY, 0xCE,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x7C,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xBE,
+	DATA_ONLY, 0xBD,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xCD,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x7E,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_19_90[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xCE,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x61,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0xCE,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x77,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xBE,
+	DATA_ONLY, 0xBE,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xCE,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x78,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_19_80[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0xCE,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x5B,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0xCE,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x71,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xBE,
+	DATA_ONLY, 0xBF,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xCE,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x72,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_19_70[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0xCF,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x56,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0xCF,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x6B,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xBE,
+	DATA_ONLY, 0xBF,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xCE,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x6C,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_19_60[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xD0,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x50,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xD0,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x64,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xBE,
+	DATA_ONLY, 0xBE,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xD0,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x65,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_19_50[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0xD0,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x4A,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xA7,
+	DATA_ONLY, 0xBD,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xD1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x5C,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xBE,
+	DATA_ONLY, 0xC0,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xD0,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x5D,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_19_40[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xD0,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x42,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xA4,
+	DATA_ONLY, 0xBD,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xD2,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x53,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xBE,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xD1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x53,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_sm2_a2_19_30_dimming[] = {
+	0xF9, 0x0C,
+	DATA_ONLY, 0xB0,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xD1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x38,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0x97,
+	DATA_ONLY, 0xBE,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xD3,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x49,
+	DATA_ONLY, 0x0C,
+	DATA_ONLY, 0xBC,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xD2,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x48,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+/* LD9040, 4.27", SM2 A2 Panel Gamma Table */
+static const unsigned short *psm2_a2_22Gamma_set[] = {
+#if defined(CONFIG_TARGET_LOCALE_NAATT)
+	ld9040_sm2_a2_22_50,
+	ld9040_sm2_a2_22_60,
+#else
+	ld9040_sm2_a2_22_30_dimming,
+	ld9040_sm2_a2_22_40,
+#endif
+	ld9040_sm2_a2_22_70,
+	ld9040_sm2_a2_22_90,
+	ld9040_sm2_a2_22_100,
+	ld9040_sm2_a2_22_110,
+	ld9040_sm2_a2_22_120,
+	ld9040_sm2_a2_22_130,
+	ld9040_sm2_a2_22_140,
+	ld9040_sm2_a2_22_150,
+	ld9040_sm2_a2_22_160,
+	ld9040_sm2_a2_22_170,
+	ld9040_sm2_a2_22_180,
+	ld9040_sm2_a2_22_190,
+	ld9040_sm2_a2_22_200,
+	ld9040_sm2_a2_22_210,
+	ld9040_sm2_a2_22_220,
+	ld9040_sm2_a2_22_230,
+	ld9040_sm2_a2_22_240,
+	ld9040_sm2_a2_22_250,
+	ld9040_sm2_a2_22_300,
+};
+
+static const unsigned short *psm2_a2_19Gamma_set[] = {
+#if defined(CONFIG_TARGET_LOCALE_NAATT)
+	ld9040_sm2_a2_19_50,
+	ld9040_sm2_a2_19_60,
+#else
+	ld9040_sm2_a2_19_30_dimming,
+	ld9040_sm2_a2_19_40,
+#endif
+	ld9040_sm2_a2_19_70,
+	ld9040_sm2_a2_19_90,
+	ld9040_sm2_a2_19_100,
+	ld9040_sm2_a2_19_110,
+	ld9040_sm2_a2_19_120,
+	ld9040_sm2_a2_19_130,
+	ld9040_sm2_a2_19_140,
+	ld9040_sm2_a2_19_150,
+	ld9040_sm2_a2_19_160,
+	ld9040_sm2_a2_19_170,
+	ld9040_sm2_a2_19_180,
+	ld9040_sm2_a2_19_190,
+	ld9040_sm2_a2_19_200,
+	ld9040_sm2_a2_19_210,
+	ld9040_sm2_a2_19_220,
+	ld9040_sm2_a2_19_230,
+	ld9040_sm2_a2_19_240,
+	ld9040_sm2_a2_19_250,
+	ld9040_sm2_a2_19_300,
+};
+
+struct ld9040_panel_data u1_panel_data_a2 = {
+	.seq_user_set = SEQ_USER_SETTING,
+	.seq_displayctl_set = SEQ_DISPCTL,
+	.seq_gtcon_set = SEQ_GTCON,
+	.seq_panelcondition_set = SEQ_PANEL_CONDITION,
+	.seq_pwrctl_set = SEQ_PWR_CTRL_SM2_A2,
+	.display_on = SEQ_DISPON,
+	.display_off = SEQ_DISPOFF,
+	.sleep_in = SEQ_SLPIN,
+	.sleep_out = SEQ_SLPOUT,
+	.acl_on = SEQ_ACL_ON,
+	.acl_table = ACL_cutoff_set,
+	.elvss_on = SEQ_ELVSS_ON,
+	.elvss_table = SEQ_SM2_ELVSS_set,
+	.gamma19_table = psm2_a2_19Gamma_set,
+	.gamma22_table = psm2_a2_22Gamma_set,
+	.lcdtype = LCDTYPE_SM2_A2,
+};
+
diff --git a/arch/arm/mach-exynos/u1-panel_m2.c b/arch/arm/mach-exynos/u1-panel_m2.c
new file mode 100644
index 0000000..954c5a6
--- /dev/null
+++ b/arch/arm/mach-exynos/u1-panel_m2.c
@@ -0,0 +1,1660 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/ld9040.h>
+#include "u1-panel.h"
+
+
+static const unsigned short SEQ_ELVSS_49[] = {
+	0xB2, 0x10,
+
+	DATA_ONLY, 0x10,
+	DATA_ONLY, 0x10,
+	DATA_ONLY, 0x10,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_ELVSS_41[] = {
+	0xB2, 0x17,
+
+	DATA_ONLY, 0x17,
+	DATA_ONLY, 0x17,
+	DATA_ONLY, 0x17,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_ELVSS_39[] = {
+	0xB2, 0x1A,
+
+	DATA_ONLY, 0x1A,
+	DATA_ONLY, 0x1A,
+	DATA_ONLY, 0x1A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short SEQ_ELVSS_35[] = {
+	0xB2, 0x1E,
+
+	DATA_ONLY, 0x1E,
+	DATA_ONLY, 0x1E,
+	DATA_ONLY, 0x1E,
+	ENDDEF, 0x00
+};
+
+static const unsigned short *SEQ_ELVSS_set[] = {
+	SEQ_ELVSS_35,
+	SEQ_ELVSS_39,
+	SEQ_ELVSS_41,
+	SEQ_ELVSS_49,
+};
+
+
+static const unsigned short SEQ_PWR_CTRL[] = {
+	0xF4, 0x0A,
+
+	DATA_ONLY, 0x87,
+	DATA_ONLY, 0x25,
+	DATA_ONLY, 0x6A,
+	DATA_ONLY, 0x44,
+	DATA_ONLY, 0x02,
+	ENDDEF, 0x00
+};
+
+
+/* LD9040, 4.27", M2 Panel Gamma Data : Useless - too old */
+static const unsigned short ld9040_22_300[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xC0,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xD1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xBF,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xDF,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_22_290[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCF,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0xBF,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xDE,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_22_280[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA7,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xBF,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xDA,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_22_270[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA3,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xD6,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_22_260[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xCD,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA3,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0xB4,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xD5,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_22_250[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0xBD,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA0,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xD2,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_22_240[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0xBD,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x9E,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCF,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_22_230[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xCD,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0xBD,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x9B,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xBE,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCB,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_22_220[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xCD,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0xBD,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x98,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC7,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_22_210[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xCE,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0xBD,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x95,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB7,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC3,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_22_200[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xCF,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0xBE,
+	DATA_ONLY, 0xCD,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x92,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB3,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC0,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_22_190[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xCE,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0xBF,
+	DATA_ONLY, 0xCD,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x8F,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xAF,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xBC,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_22_180[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xCE,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0xCD,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x8C,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xAC,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB8,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_22_170[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xCE,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0xCF,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x88,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0xBC,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA7,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB3,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_22_160[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xCE,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0xCF,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x85,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0xBD,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA3,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xAF,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_22_150[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xCF,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0xD1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x82,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0xBE,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x9F,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xAB,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_22_140[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xCF,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0xD0,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x7F,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0xBF,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x9B,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0xBD,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA6,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_22_130[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xCF,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0xD1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x7B,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0xBF,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x97,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0xBE,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA1,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_22_120[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xD0,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0xD3,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x77,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0xC0,
+	DATA_ONLY, 0xCD,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x92,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCD,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0xBE,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x9C,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_22_110[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xD0,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0xD3,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x74,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0xCE,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x8D,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCD,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0xBF,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x98,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_22_100[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xD1,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0xD4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x6F,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0xCF,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x88,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCE,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0xC0,
+	DATA_ONLY, 0xCE,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x92,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_22_90[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xD2,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0xD4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x6A,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC0,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0xD0,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x82,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCE,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0xC0,
+	DATA_ONLY, 0xCF,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x8B,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_22_80[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xD2,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0xD7,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x65,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC0,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0xD2,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x7C,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCE,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0xD1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x85,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_22_70[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xD4,
+	DATA_ONLY, 0xCD,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0xD7,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x60,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xBC,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0xD3,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x76,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCF,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0xD2,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x7F,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_22_60[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xD5,
+	DATA_ONLY, 0xCD,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0xD7,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x5B,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0xD4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x71,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xD0,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0xD3,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x78,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_22_50[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xD6,
+	DATA_ONLY, 0xCE,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0xD8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x55,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0xD6,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x69,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xD1,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0xD5,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x71,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_22_40[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xD9,
+	DATA_ONLY, 0xCE,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0xD9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x4F,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB5,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0xD8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x61,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xD2,
+	DATA_ONLY, 0xCE,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0xD6,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x69,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_22_30_dimming[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xD9,
+	DATA_ONLY, 0xD3,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0xDA,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x46,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB1,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0xD9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x58,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xD2,
+	DATA_ONLY, 0xD0,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0xD8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x5E,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_19_300[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xCD,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0xC0,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xAA,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xD0,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xDE,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_19_290[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xCF,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0xC0,
+	DATA_ONLY, 0xCE,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xD0,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0xB8,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xDF,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_19_280[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xCF,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0xC0,
+	DATA_ONLY, 0xCD,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0xBC,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCD,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0xB9,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xDC,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_19_270[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xD0,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0xC0,
+	DATA_ONLY, 0xCD,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA7,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0xBC,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xD9,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_19_260[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xD0,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0xCD,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA5,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0xBE,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xD6,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_19_250[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xD0,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0xCD,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA2,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0xBD,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0xBB,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xD2,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_19_240[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xCF,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0xCE,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA0,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0xBE,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0xBC,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCF,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_19_230[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xCF,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0xD0,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x9C,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0xBF,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xBD,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCD,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0xBC,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCA,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_19_220[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xCF,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0xD0,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x99,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0xBF,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xBA,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0xBD,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC6,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_19_210[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xD0,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0xD1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x96,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0xC0,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB6,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCD,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0xBD,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC3,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_19_200[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xD1,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0xD2,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x93,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0xC0,
+	DATA_ONLY, 0xCD,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB2,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCD,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0xBE,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xBF,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_19_190[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xD1,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0xD2,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x90,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0xCE,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xAE,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCD,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0xC0,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xBB,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_19_180[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xD2,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0xD2,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x8D,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0xCE,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xAB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCD,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0xC0,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB7,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_19_170[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xD2,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0xD3,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x89,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0xCF,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA7,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCE,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0xCE,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xB2,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_19_160[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xD2,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0xD5,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x86,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0xC2,
+	DATA_ONLY, 0xCF,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA3,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCF,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0xC0,
+	DATA_ONLY, 0xCF,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xAF,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_19_150[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xD1,
+	DATA_ONLY, 0xCD,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0xD6,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x82,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0xD0,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x9F,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCE,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0xCF,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xAA,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_19_140[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xD2,
+	DATA_ONLY, 0xCD,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0xD8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x7E,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0xC4,
+	DATA_ONLY, 0xD3,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x99,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCF,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0xC1,
+	DATA_ONLY, 0xD1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA5,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_19_130[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xD3,
+	DATA_ONLY, 0xCE,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0xD6,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x7B,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0xCD,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0xD2,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x96,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xD0,
+	DATA_ONLY, 0xCD,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0xCF,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xA1,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_19_120[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xD4,
+	DATA_ONLY, 0xCE,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0xD7,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x77,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0xCD,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0xD3,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x91,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xD0,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0xD1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x9B,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_19_110[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xD4,
+	DATA_ONLY, 0xCF,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0xD6,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x74,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0xCE,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0xD4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x8C,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCF,
+	DATA_ONLY, 0xCD,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0xD1,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x97,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_19_100[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xD4,
+	DATA_ONLY, 0xCD,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0xD8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x6F,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0xCE,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0xD5,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x87,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xD0,
+	DATA_ONLY, 0xCD,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0xD4,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x91,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_19_90[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xD6,
+	DATA_ONLY, 0xCF,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0xDA,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x6A,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0xCF,
+	DATA_ONLY, 0xC8,
+	DATA_ONLY, 0xD7,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x81,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xD2,
+	DATA_ONLY, 0xCE,
+	DATA_ONLY, 0xC5,
+	DATA_ONLY, 0xD6,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x8B,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_19_80[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xD7,
+	DATA_ONLY, 0xCF,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0xDA,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x66,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0xCF,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0xD7,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x7C,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xD3,
+	DATA_ONLY, 0xCF,
+	DATA_ONLY, 0xC7,
+	DATA_ONLY, 0xD5,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x86,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_19_70[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xD7,
+	DATA_ONLY, 0xD1,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0xDA,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x61,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0xD0,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0xD8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x77,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xD2,
+	DATA_ONLY, 0xD1,
+	DATA_ONLY, 0xC9,
+	DATA_ONLY, 0xD6,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x7F,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_19_60[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xD9,
+	DATA_ONLY, 0xD0,
+	DATA_ONLY, 0xCD,
+	DATA_ONLY, 0xDA,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x5D,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0xCF,
+	DATA_ONLY, 0xCB,
+	DATA_ONLY, 0xD9,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x70,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xD4,
+	DATA_ONLY, 0xD0,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0xD8,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x78,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_19_50[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xD8,
+	DATA_ONLY, 0xD2,
+	DATA_ONLY, 0xCF,
+	DATA_ONLY, 0xDB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x56,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xCA,
+	DATA_ONLY, 0xD1,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0xDB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x69,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xD3,
+	DATA_ONLY, 0xD1,
+	DATA_ONLY, 0xCC,
+	DATA_ONLY, 0xDA,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x70,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_19_40[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xDA,
+	DATA_ONLY, 0xD2,
+	DATA_ONLY, 0xD1,
+	DATA_ONLY, 0xDC,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x4F,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC6,
+	DATA_ONLY, 0xD2,
+	DATA_ONLY, 0xCF,
+	DATA_ONLY, 0xDB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x61,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xD4,
+	DATA_ONLY, 0xD2,
+	DATA_ONLY, 0xCE,
+	DATA_ONLY, 0xDB,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x68,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+static const unsigned short ld9040_19_30_dimming[] = {
+	0xF9, 0x00,
+	DATA_ONLY, 0xDC,
+	DATA_ONLY, 0xD5,
+	DATA_ONLY, 0xD2,
+	DATA_ONLY, 0xDE,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x46,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xC3,
+	DATA_ONLY, 0xD2,
+	DATA_ONLY, 0xCF,
+	DATA_ONLY, 0xDE,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x58,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0xD3,
+	DATA_ONLY, 0xD4,
+	DATA_ONLY, 0xCF,
+	DATA_ONLY, 0xDD,
+	DATA_ONLY, 0x00,
+	DATA_ONLY, 0x5E,
+	0xFB, 0x02,
+	DATA_ONLY, 0x5A,
+	ENDDEF, 0x00
+};
+
+
+/* LD9040, 4.27", SM2 M2 Panel Gamma Table : Useless - too old */
+static const unsigned short *p22Gamma_set[] = {
+	ld9040_22_30_dimming,
+	ld9040_22_40,
+	ld9040_22_70,
+	ld9040_22_90,
+	ld9040_22_100,
+	ld9040_22_110,
+	ld9040_22_120,
+	ld9040_22_130,
+	ld9040_22_140,
+	ld9040_22_150,
+	ld9040_22_160,
+	ld9040_22_170,
+	ld9040_22_180,
+	ld9040_22_190,
+	ld9040_22_200,
+	ld9040_22_210,
+	ld9040_22_220,
+	ld9040_22_230,
+	ld9040_22_240,
+	ld9040_22_250,
+	ld9040_22_300,
+};
+
+static const unsigned short *p19Gamma_set[] = {
+	ld9040_19_30_dimming,
+	ld9040_19_40,
+	ld9040_19_70,
+	ld9040_19_90,
+	ld9040_19_100,
+	ld9040_19_110,
+	ld9040_19_120,
+	ld9040_19_130,
+	ld9040_19_140,
+	ld9040_19_150,
+	ld9040_19_160,
+	ld9040_19_170,
+	ld9040_19_180,
+	ld9040_19_190,
+	ld9040_19_200,
+	ld9040_19_210,
+	ld9040_19_220,
+	ld9040_19_230,
+	ld9040_19_240,
+	ld9040_19_250,
+	ld9040_19_300,
+};
+
+
+struct ld9040_panel_data u1_panel_data_m2 = {
+	.seq_user_set = SEQ_USER_SETTING,
+	.seq_displayctl_set = SEQ_DISPCTL,
+	.seq_gtcon_set = SEQ_GTCON,
+	.seq_panelcondition_set = SEQ_PANEL_CONDITION,
+	.seq_pwrctl_set = SEQ_PWR_CTRL,
+	.display_on = SEQ_DISPON,
+	.display_off = SEQ_DISPOFF,
+	.sleep_in = SEQ_SLPIN,
+	.sleep_out = SEQ_SLPOUT,
+	.acl_on = SEQ_ACL_ON,
+	.acl_table = ACL_cutoff_set,
+	.elvss_on = SEQ_ELVSS_ON,
+	.elvss_table = SEQ_ELVSS_set,
+	.gamma19_table = p19Gamma_set,
+	.gamma22_table = p22Gamma_set,
+	.lcdtype = LCDTYPE_M2,
+};
+
diff --git a/arch/arm/mach-exynos/u1-wlan.c b/arch/arm/mach-exynos/u1-wlan.c
new file mode 100644
index 0000000..c570fc8
--- /dev/null
+++ b/arch/arm/mach-exynos/u1-wlan.c
@@ -0,0 +1,329 @@
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/skbuff.h>
+#include <linux/wlan_plat.h>
+
+#include <plat/devs.h>
+#include <plat/sdhci.h>
+#include <plat/gpio-cfg.h>
+#include <mach/regs-gpio.h>
+#include <mach/gpio.h>
+
+#ifdef CONFIG_BROADCOM_WIFI_RESERVED_MEM
+
+#define WLAN_STATIC_SCAN_BUF0		5
+#define WLAN_STATIC_SCAN_BUF1		6
+#define PREALLOC_WLAN_SEC_NUM		4
+#define PREALLOC_WLAN_BUF_NUM		160
+#define PREALLOC_WLAN_SECTION_HEADER	24
+
+#define WLAN_SECTION_SIZE_0	(PREALLOC_WLAN_BUF_NUM * 128)
+#define WLAN_SECTION_SIZE_1	(PREALLOC_WLAN_BUF_NUM * 128)
+#define WLAN_SECTION_SIZE_2	(PREALLOC_WLAN_BUF_NUM * 512)
+#define WLAN_SECTION_SIZE_3	(PREALLOC_WLAN_BUF_NUM * 1024)
+
+#define DHD_SKB_HDRSIZE			336
+#define DHD_SKB_1PAGE_BUFSIZE	((PAGE_SIZE*1)-DHD_SKB_HDRSIZE)
+#define DHD_SKB_2PAGE_BUFSIZE	((PAGE_SIZE*2)-DHD_SKB_HDRSIZE)
+#define DHD_SKB_4PAGE_BUFSIZE	((PAGE_SIZE*4)-DHD_SKB_HDRSIZE)
+
+#define WLAN_SKB_BUF_NUM	17
+
+static struct sk_buff *wlan_static_skb[WLAN_SKB_BUF_NUM];
+
+struct wlan_mem_prealloc {
+	void *mem_ptr;
+	unsigned long size;
+};
+
+static struct wlan_mem_prealloc wlan_mem_array[PREALLOC_WLAN_SEC_NUM] = {
+	{NULL, (WLAN_SECTION_SIZE_0 + PREALLOC_WLAN_SECTION_HEADER)},
+	{NULL, (WLAN_SECTION_SIZE_1 + PREALLOC_WLAN_SECTION_HEADER)},
+	{NULL, (WLAN_SECTION_SIZE_2 + PREALLOC_WLAN_SECTION_HEADER)},
+	{NULL, (WLAN_SECTION_SIZE_3 + PREALLOC_WLAN_SECTION_HEADER)}
+};
+
+void *wlan_static_scan_buf0;
+void *wlan_static_scan_buf1;
+static void *brcm_wlan_mem_prealloc(int section, unsigned long size)
+{
+	if (section == PREALLOC_WLAN_SEC_NUM)
+		return wlan_static_skb;
+	if (section == WLAN_STATIC_SCAN_BUF0)
+		return wlan_static_scan_buf0;
+	if (section == WLAN_STATIC_SCAN_BUF1)
+		return wlan_static_scan_buf1;
+	if ((section < 0) || (section > PREALLOC_WLAN_SEC_NUM))
+		return NULL;
+
+	if (wlan_mem_array[section].size < size)
+		return NULL;
+
+	return wlan_mem_array[section].mem_ptr;
+}
+
+static int brcm_init_wlan_mem(void)
+{
+	int i;
+	int j;
+
+	for (i = 0; i < 8; i++) {
+		wlan_static_skb[i] = dev_alloc_skb(DHD_SKB_1PAGE_BUFSIZE);
+		if (!wlan_static_skb[i])
+			goto err_skb_alloc;
+	}
+
+	for (; i < 16; i++) {
+		wlan_static_skb[i] = dev_alloc_skb(DHD_SKB_2PAGE_BUFSIZE);
+		if (!wlan_static_skb[i])
+			goto err_skb_alloc;
+	}
+
+	wlan_static_skb[i] = dev_alloc_skb(DHD_SKB_4PAGE_BUFSIZE);
+	if (!wlan_static_skb[i])
+		goto err_skb_alloc;
+
+	for (i = 0 ; i < PREALLOC_WLAN_SEC_NUM ; i++) {
+		wlan_mem_array[i].mem_ptr =
+				kmalloc(wlan_mem_array[i].size, GFP_KERNEL);
+
+		if (!wlan_mem_array[i].mem_ptr)
+			goto err_mem_alloc;
+	}
+	wlan_static_scan_buf0 = kmalloc(65536, GFP_KERNEL);
+	if (!wlan_static_scan_buf0)
+		goto err_mem_alloc;
+	wlan_static_scan_buf1 = kmalloc(65536, GFP_KERNEL);
+	if (!wlan_static_scan_buf1)
+		goto err_mem_alloc;
+	printk(KERN_INFO"%s: WIFI MEM Allocated\n", __func__);
+	return 0;
+
+ err_mem_alloc:
+	pr_err("Failed to mem_alloc for WLAN\n");
+	for (j = 0 ; j < i ; j++)
+		kfree(wlan_mem_array[j].mem_ptr);
+
+	i = WLAN_SKB_BUF_NUM;
+
+ err_skb_alloc:
+	pr_err("Failed to skb_alloc for WLAN\n");
+	for (j = 0 ; j < i ; j++)
+		dev_kfree_skb(wlan_static_skb[j]);
+
+	return -ENOMEM;
+}
+#endif /* CONFIG_BROADCOM_WIFI_RESERVED_MEM */
+
+static unsigned int wlan_on_gpio_table[][4] = {
+	{GPIO_WLAN_EN , GPIO_WLAN_EN_AF, GPIO_LEVEL_HIGH, S3C_GPIO_PULL_NONE},
+	{GPIO_WLAN_HOST_WAKE, GPIO_WLAN_HOST_WAKE_AF,
+	 GPIO_LEVEL_NONE, S3C_GPIO_PULL_DOWN},
+};
+
+static unsigned int wlan_off_gpio_table[][4] = {
+	{GPIO_WLAN_EN , GPIO_WLAN_EN_AF, GPIO_LEVEL_LOW, S3C_GPIO_PULL_NONE},
+	{GPIO_WLAN_HOST_WAKE, 0 , GPIO_LEVEL_NONE, S3C_GPIO_PULL_DOWN},
+};
+
+static unsigned int wlan_sdio_on_table[][4] = {
+	{GPIO_WLAN_SDIO_CLK, GPIO_WLAN_SDIO_CLK_AF,
+	 GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE},
+	{GPIO_WLAN_SDIO_CMD, GPIO_WLAN_SDIO_CMD_AF,
+	 GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE},
+	{GPIO_WLAN_SDIO_D0, GPIO_WLAN_SDIO_D0_AF,
+	 GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE},
+	{GPIO_WLAN_SDIO_D1, GPIO_WLAN_SDIO_D1_AF,
+	 GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE},
+	{GPIO_WLAN_SDIO_D2, GPIO_WLAN_SDIO_D2_AF,
+	 GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE},
+	{GPIO_WLAN_SDIO_D3, GPIO_WLAN_SDIO_D3_AF,
+	 GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE},
+};
+
+static unsigned int wlan_sdio_off_table[][4] = {
+	{GPIO_WLAN_SDIO_CLK, 1, GPIO_LEVEL_LOW, S3C_GPIO_PULL_NONE},
+	{GPIO_WLAN_SDIO_CMD, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE},
+	{GPIO_WLAN_SDIO_D0, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE},
+	{GPIO_WLAN_SDIO_D1, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE},
+	{GPIO_WLAN_SDIO_D2, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE},
+	{GPIO_WLAN_SDIO_D3, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE},
+};
+
+static void s3c_config_gpio_alive_table
+(int array_size, unsigned int
+(*gpio_table)[4])
+{
+	u32 i, gpio;
+	printk(KERN_INFO"gpio_table = [%d] \r\n" , array_size);
+	for (i = 0; i < array_size; i++) {
+		gpio = gpio_table[i][0];
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(gpio_table[i][1]));
+		s3c_gpio_setpull(gpio, gpio_table[i][3]);
+		if (gpio_table[i][2] != GPIO_LEVEL_NONE)
+			gpio_set_value(gpio, gpio_table[i][2]);
+	}
+}
+
+static int brcm_wlan_power(int onoff)
+{
+	printk(KERN_INFO"------------------------------------------------");
+	printk(KERN_INFO"------------------------------------------------\n");
+	printk(KERN_INFO"%s Enter: power %s\n", __func__, onoff ? "on" : "off");
+	if (onoff) {
+		s3c_config_gpio_alive_table
+		(ARRAY_SIZE(wlan_on_gpio_table), wlan_on_gpio_table);
+		udelay(200);
+		gpio_set_value(GPIO_WLAN_EN, GPIO_LEVEL_HIGH);
+		printk(KERN_DEBUG"WLAN: GPIO_WLAN_EN = %d\n",
+		gpio_get_value(GPIO_WLAN_EN));
+	} else {
+		gpio_set_value(GPIO_WLAN_EN, GPIO_LEVEL_LOW);
+		s3c_config_gpio_alive_table
+		(ARRAY_SIZE(wlan_off_gpio_table), wlan_off_gpio_table);
+		printk(KERN_DEBUG"WLAN: GPIO_WLAN_EN = %d\n",
+		gpio_get_value(GPIO_WLAN_EN));
+	}
+
+	return 0;
+}
+
+static int brcm_wlan_reset(int onoff)
+{
+	gpio_set_value(GPIO_WLAN_EN,
+			onoff ? GPIO_LEVEL_HIGH : GPIO_LEVEL_LOW);
+	return 0;
+}
+
+static int brcm_wlan_set_carddetect(int onoff)
+{
+	if (onoff) {
+		s3c_config_gpio_alive_table(
+ARRAY_SIZE(wlan_sdio_on_table), wlan_sdio_on_table);
+	} else {
+		s3c_config_gpio_alive_table(
+ARRAY_SIZE(wlan_sdio_off_table), wlan_sdio_off_table); }
+
+	udelay(200);
+
+	mmc_force_presence_change(&s3c_device_hsmmc3);
+	msleep(500); /* wait for carddetect */
+	return 0;
+}
+
+/* Customized Locale table : OPTIONAL feature */
+#define WLC_CNTRY_BUF_SZ        4
+struct cntry_locales_custom {
+	char iso_abbrev[WLC_CNTRY_BUF_SZ];
+	char custom_locale[WLC_CNTRY_BUF_SZ];
+	int  custom_locale_rev;
+};
+
+static struct cntry_locales_custom brcm_wlan_translate_custom_table[] = {
+	/* Table should be filled out based
+ on custom platform regulatory requirement */
+	{"",   "XY", 4},  /* universal */
+	{"US", "US", 69}, /* input ISO "US" to : US regrev 69 */
+	{"CA", "US", 69}, /* input ISO "CA" to : US regrev 69 */
+	{"EU", "EU", 5},  /* European union countries */
+	{"AT", "EU", 5},
+	{"BE", "EU", 5},
+	{"BG", "EU", 5},
+	{"CY", "EU", 5},
+	{"CZ", "EU", 5},
+	{"DK", "EU", 5},
+	{"EE", "EU", 5},
+	{"FI", "EU", 5},
+	{"FR", "EU", 5},
+	{"DE", "EU", 5},
+	{"GR", "EU", 5},
+	{"HU", "EU", 5},
+	{"IE", "EU", 5},
+	{"IT", "EU", 5},
+	{"LV", "EU", 5},
+	{"LI", "EU", 5},
+	{"LT", "EU", 5},
+	{"LU", "EU", 5},
+	{"MT", "EU", 5},
+	{"NL", "EU", 5},
+	{"PL", "EU", 5},
+	{"PT", "EU", 5},
+	{"RO", "EU", 5},
+	{"SK", "EU", 5},
+	{"SI", "EU", 5},
+	{"ES", "EU", 5},
+	{"SE", "EU", 5},
+	{"GB", "EU", 5},  /* input ISO "GB" to : EU regrev 05 */
+	{"IL", "IL", 0},
+	{"CH", "CH", 0},
+	{"TR", "TR", 0},
+	{"NO", "NO", 0},
+	{"KR", "XY", 3},
+	{"AU", "XY", 3},
+	{"CN", "XY", 3},  /* input ISO "CN" to : XY regrev 03 */
+	{"TW", "XY", 3},
+	{"AR", "XY", 3},
+	{"MX", "XY", 3}
+};
+
+static void *brcm_wlan_get_country_code(char *ccode)
+{
+	int size = ARRAY_SIZE(brcm_wlan_translate_custom_table);
+	int i;
+
+	if (!ccode)
+		return NULL;
+
+	for (i = 0; i < size; i++)
+		if (strcmp(ccode,
+		brcm_wlan_translate_custom_table[i].iso_abbrev) == 0)
+			return &brcm_wlan_translate_custom_table[i];
+	return &brcm_wlan_translate_custom_table[0];
+}
+
+static struct resource brcm_wlan_resources[] = {
+	[0] = {
+		.name	= "bcmdhd_wlan_irq",
+		.start	= IRQ_EINT(21),
+		.end	= IRQ_EINT(21),
+#ifdef CONFIG_MACH_Q1_BD
+		.flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL | IORESOURCE_IRQ_SHAREABLE,
+#else
+		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
+#endif
+	},
+};
+
+static struct wifi_platform_data brcm_wlan_control = {
+	.set_power	= brcm_wlan_power,
+	.set_reset	= brcm_wlan_reset,
+	.set_carddetect	= brcm_wlan_set_carddetect,
+#ifdef CONFIG_BROADCOM_WIFI_RESERVED_MEM
+	.mem_prealloc	= brcm_wlan_mem_prealloc,
+#endif
+	.get_country_code = brcm_wlan_get_country_code,
+};
+
+static struct platform_device brcm_device_wlan = {
+	.name		= "bcmdhd_wlan",
+	.id		= 1,
+	.num_resources	= ARRAY_SIZE(brcm_wlan_resources),
+	.resource	= brcm_wlan_resources,
+	.dev		= {
+		.platform_data = &brcm_wlan_control,
+	},
+};
+
+int __init brcm_wlan_init(void)
+{
+	printk(KERN_INFO"%s: start\n", __func__);
+
+#ifdef CONFIG_BROADCOM_WIFI_RESERVED_MEM
+	brcm_init_wlan_mem();
+#endif
+
+	return platform_device_register(&brcm_device_wlan);
+}
diff --git a/arch/arm/mach-exynos/u1.h b/arch/arm/mach-exynos/u1.h
new file mode 100644
index 0000000..d77e440
--- /dev/null
+++ b/arch/arm/mach-exynos/u1.h
@@ -0,0 +1,25 @@
+/*
+ * arch/arm/mach-s5pv210/u1.h
+ */
+
+#ifndef __U1_H__
+#define __U1_H__
+
+extern struct ld9040_panel_data u1_panel_data;
+extern struct ld9040_panel_data u1_panel_data_a2;
+extern struct ld9040_panel_data u1_panel_data_m2;
+
+extern int s3c_gpio_slp_cfgpin(unsigned int pin, unsigned int config);
+extern int s3c_gpio_slp_setpull_updown(unsigned int pin, unsigned int config);
+
+extern void u1_config_gpio_table(void);
+extern void u1_config_sleep_gpio_table(void);
+
+extern int brcm_wlan_init(void);
+extern void set_gps_uart_op(int onoff);
+
+#ifdef CONFIG_TARGET_LOCALE_KOR
+extern int u1_switch_get_usb_lock_state(void);
+#endif
+
+#endif
diff --git a/arch/arm/mach-exynos/u1_regulator_consumer.c b/arch/arm/mach-exynos/u1_regulator_consumer.c
new file mode 100644
index 0000000..e142235
--- /dev/null
+++ b/arch/arm/mach-exynos/u1_regulator_consumer.c
@@ -0,0 +1,147 @@
+/* u1-regulator-consumer.c
+ *
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/machine.h>
+
+static int u1_enable_regulator_for_usb_mipi(bool enable)
+{
+	struct regulator *mipi11_regulator;
+	struct regulator *mipi18_regulator;
+#ifndef CONFIG_MACH_U1_KOR_LGT
+	struct regulator *hsic12_regulator;
+#endif
+	struct regulator *usb33_regulator;
+	int ret = 0;
+
+	mipi11_regulator = regulator_get(NULL, "vmipi_1.1v");
+	if (IS_ERR(mipi11_regulator)) {
+		pr_err("%s: failed to get %s\n", __func__, "vmipi_1.1v");
+		ret = -ENODEV;
+		goto out4;
+	}
+
+	mipi18_regulator = regulator_get(NULL, "vmipi_1.8v");
+	if (IS_ERR(mipi18_regulator)) {
+		pr_err("%s: failed to get %s\n", __func__, "vmipi_1.8v");
+		ret = -ENODEV;
+		goto out3;
+	}
+
+#ifndef CONFIG_MACH_U1_KOR_LGT
+	hsic12_regulator = regulator_get(NULL, "vhsic");
+	if (IS_ERR(hsic12_regulator)) {
+		pr_err("%s: failed to get %s\n", __func__, "vhsic 1.2v");
+		ret = -ENODEV;
+		goto out2;
+	}
+#endif
+
+	usb33_regulator = regulator_get(NULL, "vusb_3.3v");
+	if (IS_ERR(usb33_regulator)) {
+		pr_err("%s: failed to get %s\n", __func__, "vusb_3.3v");
+		ret = -ENODEV;
+		goto out1;
+	}
+
+	if (enable) {
+		/* Power On Sequence
+		 * MIPI 1.1V -> HSIC 1.2V -> MIPI 1.8V -> USB 3.3V
+		 */
+		pr_info("%s: enable LDOs\n", __func__);
+		if (!regulator_is_enabled(mipi11_regulator))
+			regulator_enable(mipi11_regulator);
+#ifndef CONFIG_MACH_U1_KOR_LGT
+		if (!regulator_is_enabled(hsic12_regulator))
+			regulator_enable(hsic12_regulator);
+#endif
+		if (!regulator_is_enabled(mipi18_regulator))
+			regulator_enable(mipi18_regulator);
+		if (!regulator_is_enabled(usb33_regulator))
+			regulator_enable(usb33_regulator);
+	} else {
+		/* Power Off Sequence
+		 * USB 3.3V -> MIPI 18V -> HSIC 1.2V -> MIPI 1.1V
+		 */
+		pr_info("%s: disable LDOs\n", __func__);
+		regulator_force_disable(usb33_regulator);
+		regulator_force_disable(mipi18_regulator);
+#ifndef CONFIG_MACH_U1_KOR_LGT
+		regulator_force_disable(hsic12_regulator);
+#endif
+		regulator_force_disable(mipi11_regulator);
+	}
+
+	regulator_put(usb33_regulator);
+out1:
+#ifndef CONFIG_MACH_U1_KOR_LGT
+	regulator_put(hsic12_regulator);
+#endif
+out2:
+	regulator_put(mipi18_regulator);
+out3:
+	regulator_put(mipi11_regulator);
+out4:
+	return ret;
+}
+
+
+static int regulator_consumer_probe(struct platform_device *pdev)
+{
+	pr_info("%s: loading u1-regulator-consumer\n", __func__);
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int regulator_consumer_suspend(struct device *dev)
+{
+	u1_enable_regulator_for_usb_mipi(false);
+	return 0;
+}
+
+static int regulator_consumer_resume(struct device *dev)
+{
+	u1_enable_regulator_for_usb_mipi(true);
+	return 0;
+}
+#else
+#define regulator_consumer_suspend	NULL
+#define regulator_consumer_resume	NULL
+#endif /* CONFIG_PM */
+
+static const struct dev_pm_ops regulator_consumer_pm_ops = {
+	.suspend = regulator_consumer_suspend,
+	.resume = regulator_consumer_resume,
+};
+
+static struct platform_driver regulator_consumer_driver = {
+	.probe = regulator_consumer_probe,
+	.driver = {
+		   .owner = THIS_MODULE,
+		   .name = "u1-regulator-consumer",
+		   .pm = &regulator_consumer_pm_ops,
+	},
+};
+
+static int __init regulator_consumer_init(void)
+{
+	return platform_driver_register(&regulator_consumer_driver);
+}
+module_init(regulator_consumer_init);
+
+MODULE_DESCRIPTION("U1 regulator consumer driver");
+MODULE_AUTHOR("ms925.kim@samsung.com");
+MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-exynos/u1camera-gpio.c b/arch/arm/mach-exynos/u1camera-gpio.c
new file mode 100644
index 0000000..b00b6c5
--- /dev/null
+++ b/arch/arm/mach-exynos/u1camera-gpio.c
@@ -0,0 +1,439 @@
+#include <linux/gpio.h>
+#include <linux/serial_core.h>
+#include <plat/devs.h>
+#include <plat/gpio-cfg.h>
+#include <plat/regs-serial.h>
+#include <mach/gpio.h>
+#include "u1.h"
+
+struct gpio_init_data {
+	uint num;
+	uint cfg;
+	uint val;
+	uint pud;
+	uint drv;
+};
+
+static struct gpio_init_data u1_init_gpios[] = {
+	{EXYNOS4_GPC1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* CODEC_SDA_1.8V */
+	{EXYNOS4_GPC1(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* CODEC_SCL_1.8V */
+
+	{EXYNOS4_GPD0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* MHL_SDA_2.8V */
+	{EXYNOS4_GPD0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* MHL_SCL_2.8V */
+
+	{EXYNOS4_GPD1(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* 8M_CAM_SDA_2.8V */
+	{EXYNOS4_GPD1(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* 8M_CAM_SCL_2.8V */
+	{EXYNOS4_GPD1(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* SENSE_SDA_2.8V */
+	{EXYNOS4_GPD1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* SENSE_SCL_2.8V */
+
+	{EXYNOS4_GPK3(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_CMD */
+	{EXYNOS4_GPK3(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(0) */
+	{EXYNOS4_GPK3(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(1) */
+	{EXYNOS4_GPK3(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(2) */
+	{EXYNOS4_GPK3(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(3) */
+
+	{EXYNOS4_GPX0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* VOL_UP */
+	{EXYNOS4_GPX0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* VOL_DOWN */
+	{EXYNOS4_GPX0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* GPIO_BOOT_MODE */
+
+	{EXYNOS4_GPX2(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* GPIO_FUEL_ALERT */
+
+	{EXYNOS4_GPX3(1), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPX3(2), S3C_GPIO_SFN(GPIO_DET_35_AF), S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* GPIO_DET_35 */
+	{EXYNOS4_GPX3(3), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPX3(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1},
+
+	{EXYNOS4_GPY0(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY0(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY0(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+
+	{EXYNOS4_GPY1(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY1(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY1(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+
+	{EXYNOS4_GPY2(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY2(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1,},
+	{EXYNOS4_GPY2(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY2(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY2(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY2(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+
+	{EXYNOS4_GPY3(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY3(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+
+	{EXYNOS4_GPY4(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY4(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY4(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY4(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+
+	{EXYNOS4_GPY5(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY5(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY5(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY5(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY5(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY5(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY5(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY5(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+
+	{EXYNOS4_GPY6(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY6(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY6(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY6(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY6(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY6(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY6(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+	{EXYNOS4_GPY6(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
+		 S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1},
+};
+
+/* this table only for GC1 board */
+static unsigned int u1_sleep_gpio_table[][3] = {
+	{EXYNOS4_GPA0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPA0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPA0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPA1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPA1(1), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA1(2), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA1(3), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPA1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPA1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPB(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPB(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPB(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPB(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPC0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPC0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPC0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPC0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPC0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPC1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPC1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPC1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPC1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPC1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPD0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPD0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPD0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPD0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPD1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPD1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPD1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPD1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4210_GPE0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE0(3), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE0(4), S3C_GPIO_SLP_OUT1,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4210_GPE1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE1(4), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE1(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE1(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4210_GPE2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPE2(4), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE2(5), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4210_GPE3(0), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE3(1), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE3(2), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE3(3), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE3(4), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE3(5), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE3(6), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE3(7), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4210_GPE4(0), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE4(1), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE4(2), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE4(3), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE4(4), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE4(5), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE4(6), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPE4(7), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPF0(0), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF0(1), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF0(2), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF0(3), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF0(4), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF0(5), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF0(6), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF0(7), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPF1(0), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF1(1), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF1(2), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF1(3), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF1(4), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF1(5), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF1(6), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF1(7), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPF2(0), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF2(1), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF2(2), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF2(3), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF2(4), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF2(5), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF2(6), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF2(7), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPF3(0), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF3(1), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF3(2), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF3(3), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPF3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPF3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4210_GPJ0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPJ0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPJ0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPJ0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPJ0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPJ0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPJ0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPJ0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4210_GPJ1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPJ1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPJ1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4210_GPJ1(3), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4210_GPJ1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPK0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK0(2), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPK1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPK1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPK1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPK1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK1(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPK2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPK2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPK2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+
+	{EXYNOS4_GPK3(0), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPK3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPK3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPL0(0), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPL0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPL0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPL0(6), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL0(7), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPL1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPL1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPL1(2), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPL2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPL2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPL2(2), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPL2(4), S3C_GPIO_SLP_PREV,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPL2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPL2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPY0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPY1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPY2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPY3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY3(1), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY3(3), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
+	{EXYNOS4_GPY3(5), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(6), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY3(7), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+
+	{EXYNOS4_GPY4(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY4(3), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY4(5), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPY4(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY4(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPY5(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* TP */
+	{EXYNOS4_GPY5(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY5(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY5(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY5(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY5(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY5(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY5(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPY6(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY6(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY6(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY6(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY6(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY6(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY6(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPY6(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+
+	{EXYNOS4_GPZ(0), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPZ(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPZ(2), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPZ(3), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPZ(4), S3C_GPIO_SLP_OUT0,  S3C_GPIO_PULL_NONE},
+	{EXYNOS4_GPZ(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+	{EXYNOS4_GPZ(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
+};
+
+void u1_config_gpio_table(void)
+{
+	u32 i, gpio;
+
+	for (i = 0; i < ARRAY_SIZE(u1_init_gpios); i++) {
+		gpio = u1_init_gpios[i].num;
+		s3c_gpio_cfgpin(gpio, u1_init_gpios[i].cfg);
+		s3c_gpio_setpull(gpio, u1_init_gpios[i].pud);
+
+		if (u1_init_gpios[i].val != S3C_GPIO_SETPIN_NONE)
+			gpio_set_value(gpio, u1_init_gpios[i].val);
+
+		s5p_gpio_set_drvstr(gpio, u1_init_gpios[i].drv);
+	}
+}
+
+static void config_sleep_gpio_table(int array_size,
+				    unsigned int (*gpio_table)[3])
+{
+	u32 i, gpio;
+
+	for (i = 0; i < array_size; i++) {
+		gpio = gpio_table[i][0];
+		s3c_gpio_slp_cfgpin(gpio, gpio_table[i][1]);
+		s3c_gpio_slp_setpull_updown(gpio, gpio_table[i][2]);
+	}
+}
+
+void u1_config_sleep_gpio_table(void)
+{
+	config_sleep_gpio_table(ARRAY_SIZE(u1_sleep_gpio_table),
+			u1_sleep_gpio_table);
+}
diff --git a/arch/arm/mach-exynos/wakeup_assist.c b/arch/arm/mach-exynos/wakeup_assist.c
new file mode 100644
index 0000000..fe6d9d7
--- /dev/null
+++ b/arch/arm/mach-exynos/wakeup_assist.c
@@ -0,0 +1,110 @@
+/*
+ * Wakeup assist driver
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/input.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <mach/regs-pmu.h>
+
+#define DEV_NAME "wakeup_assist"
+
+static int wakeup_assist_keycode[] = { KEY_POWER };
+
+static int __devinit wakeup_assist_probe(struct platform_device *pdev)
+{
+	int error;
+	struct input_dev *input_dev;
+
+	input_dev = input_allocate_device();
+
+	if (!input_dev)
+		return -ENOMEM;
+
+	input_dev->name = DEV_NAME;
+	input_dev->id.bustype = BUS_HOST;
+	input_dev->dev.parent = &pdev->dev;
+
+	input_dev->evbit[0] = BIT_MASK(EV_KEY);
+
+	input_set_capability(input_dev, EV_MSC, MSC_SCAN);
+
+	input_dev->keycode = wakeup_assist_keycode;
+	input_dev->keycodesize = sizeof(wakeup_assist_keycode[0]);
+	input_dev->keycodemax = ARRAY_SIZE(wakeup_assist_keycode);
+
+	__set_bit(wakeup_assist_keycode[0], input_dev->keybit);
+	__clear_bit(KEY_RESERVED, input_dev->keybit);
+
+	error = input_register_device(input_dev);
+	if (error) {
+		input_free_device(input_dev);
+		return error;
+	}
+
+	platform_set_drvdata(pdev, input_dev);
+
+	return 0;
+}
+
+static int __devexit wakeup_assist_remove(struct platform_device *pdev)
+{
+	struct input_dev *input_dev = platform_get_drvdata(pdev);
+
+	platform_set_drvdata(pdev, NULL);
+	input_unregister_device(input_dev);
+	input_free_device(input_dev);
+
+	return 0;
+}
+
+static int wakeup_assist_resume(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct input_dev *input_dev = platform_get_drvdata(pdev);
+
+	if (readl(S5P_WAKEUP_STAT) & 0x1) {
+		input_report_key(input_dev, wakeup_assist_keycode[0], 0x2);
+		input_sync(input_dev);
+		input_report_key(input_dev, wakeup_assist_keycode[0], 0x0);
+		input_sync(input_dev);
+	}
+
+	return 0;
+}
+
+static const struct dev_pm_ops wakeup_assist_pm_ops = {
+	.resume		= wakeup_assist_resume,
+};
+
+static struct platform_driver wakeup_assist_driver = {
+	.probe		= wakeup_assist_probe,
+	.remove		= __devexit_p(wakeup_assist_remove),
+	.driver		= {
+		.name	= DEV_NAME,
+		.owner	= THIS_MODULE,
+		.pm	= &wakeup_assist_pm_ops,
+	},
+};
+
+static int __init wakeup_assist_init(void)
+{
+	return platform_driver_register(&wakeup_assist_driver);
+}
+module_init(wakeup_assist_init);
+
+static void __exit wakeup_assist_exit(void)
+{
+	platform_driver_unregister(&wakeup_assist_driver);
+}
+module_exit(wakeup_assist_exit);
+
+MODULE_DESCRIPTION("Wakeup assist driver");
+MODULE_AUTHOR("Eunki Kim <eunki_kim@samsung.com>");
+MODULE_LICENSE("GPL");