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| author | Daniel Wolstenholme <daniel.e.wolstenholme@intel.com> | 2007-05-10 22:33:02 -0700 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2007-05-11 17:41:52 +0100 |
| commit | 2fd0237538480c8d704c385b6f9abc3f6c46b760 (patch) | |
| tree | 4f4052fb01ec00d4717bc7741602e02aa9833ef6 /arch/arm/mach-iop13xx/pci.c | |
| parent | 87b247c41674e29f90bf4938799ab079951ccc6b (diff) | |
| download | kernel_samsung_smdk4412-2fd0237538480c8d704c385b6f9abc3f6c46b760.zip kernel_samsung_smdk4412-2fd0237538480c8d704c385b6f9abc3f6c46b760.tar.gz kernel_samsung_smdk4412-2fd0237538480c8d704c385b6f9abc3f6c46b760.tar.bz2 | |
[ARM] iop13xx: msi support
Enable devices to signal interrupts via PCI memory cycles.
rev6:
* fix enable/disable typo, Michael Ellerman
rev5:
* fix up ack, enable, and disable for iop13xx_msi_chip
rev4:
* move smp compile fix to separate patch
* use dynamic_irq_init in create_irq()
* hookup mask/unmask routines in iop13xx_msi_chip
rev3:
* change msi.c to use linux/smp.h instead of asm/smp.h
* call dynamic_irq_cleanup at destroy_irq time
rev2:
* destroy_irq did not take the full 128 bits of msi_irq_in_use into account
* added missing '&' for calls to test_and_set_bit and clear_bit
[ebiederm@xmission.com: review comments/suggestions]
[dan.j.williams@intel.com: cleanups/forward port to 2.6-git]
Signed-off-by: Daniel Wolstenholme <daniel.e.wolstenholme@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: Eric W. Biederman <ebiederm@xmission.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-iop13xx/pci.c')
| -rw-r--r-- | arch/arm/mach-iop13xx/pci.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c index d1d0d32..1c9e94c 100644 --- a/arch/arm/mach-iop13xx/pci.c +++ b/arch/arm/mach-iop13xx/pci.c @@ -559,6 +559,14 @@ void __init iop13xx_atue_setup(void) int func = iop13xx_atu_function(IOP13XX_INIT_ATU_ATUE); u32 reg_val; +#ifdef CONFIG_PCI_MSI + /* BAR 0 (inbound msi window) */ + __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_MU_MUBAR); + __raw_writel(~(IOP13XX_MU_WINDOW_SIZE - 1), IOP13XX_ATUE_IALR0); + __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_ATUE_IATVR0); + __raw_writel(IOP13XX_MU_BASE_PCI, IOP13XX_ATUE_IABAR0); +#endif + /* BAR 1 (1:1 mapping with Physical RAM) */ /* Set limit and enable */ __raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1, @@ -720,6 +728,14 @@ void __init iop13xx_atux_setup(void) else atux_trhfa_timeout = jiffies; +#ifdef CONFIG_PCI_MSI + /* BAR 0 (inbound msi window) */ + __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_MU_MUBAR); + __raw_writel(~(IOP13XX_MU_WINDOW_SIZE - 1), IOP13XX_ATUX_IALR0); + __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_ATUX_IATVR0); + __raw_writel(IOP13XX_MU_BASE_PCI, IOP13XX_ATUX_IABAR0); +#endif + /* BAR 1 (1:1 mapping with Physical RAM) */ /* Set limit and enable */ __raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1, |