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| author | Kanigeri, Hari <h-kanigeri2@ti.com> | 2010-05-24 02:01:50 +0000 |
|---|---|---|
| committer | Hiroshi DOYU <Hiroshi.DOYU@nokia.com> | 2010-06-29 07:55:06 +0300 |
| commit | 993dd17e32cfb6cc058e1a4394dd113edf764186 (patch) | |
| tree | e1fd70529b7e1a3ccce54ecddb59a91c3978f330 /arch/arm/mach-omap2/iommu2.c | |
| parent | 124933599a11cab4b77a6d79d49312754e8ff88e (diff) | |
| download | kernel_samsung_smdk4412-993dd17e32cfb6cc058e1a4394dd113edf764186.zip kernel_samsung_smdk4412-993dd17e32cfb6cc058e1a4394dd113edf764186.tar.gz kernel_samsung_smdk4412-993dd17e32cfb6cc058e1a4394dd113edf764186.tar.bz2 | |
omap iommu: update irq mask to be specific about twl and tlb
Revise the IRQ mask definitions to handle the MMU faults related
to TWL fault as well as TLB miss fault.
Signed-off-by: Hari Kanigeri <h-kanigeri2@ti.com>
Signed-off-by: Hiroshi Doyu <Hiroshi.DOYU@nokia.com>
Diffstat (limited to 'arch/arm/mach-omap2/iommu2.c')
| -rw-r--r-- | arch/arm/mach-omap2/iommu2.c | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c index e82da68..ebbdae2 100644 --- a/arch/arm/mach-omap2/iommu2.c +++ b/arch/arm/mach-omap2/iommu2.c @@ -44,9 +44,13 @@ #define MMU_IRQ_EMUMISS (1 << 2) #define MMU_IRQ_TRANSLATIONFAULT (1 << 1) #define MMU_IRQ_TLBMISS (1 << 0) -#define MMU_IRQ_MASK \ - (MMU_IRQ_MULTIHITFAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_EMUMISS | \ - MMU_IRQ_TRANSLATIONFAULT) + +#define __MMU_IRQ_FAULT \ + (MMU_IRQ_MULTIHITFAULT | MMU_IRQ_EMUMISS | MMU_IRQ_TRANSLATIONFAULT) +#define MMU_IRQ_MASK \ + (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_TLBMISS) +#define MMU_IRQ_TWL_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT) +#define MMU_IRQ_TLB_MISS_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TLBMISS) /* MMU_CNTL */ #define MMU_CNTL_SHIFT 1 @@ -96,7 +100,7 @@ static int omap2_iommu_enable(struct iommu *obj) l |= (MMU_SYS_IDLE_SMART | MMU_SYS_AUTOIDLE); iommu_write_reg(obj, l, MMU_SYSCONFIG); - iommu_write_reg(obj, MMU_IRQ_MASK, MMU_IRQENABLE); + iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE); iommu_write_reg(obj, pa, MMU_TTB); l = iommu_read_reg(obj, MMU_CNTL); |