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author | Linus Torvalds <torvalds@linux-foundation.org> | 2011-03-17 19:08:06 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2011-03-17 19:08:06 -0700 |
commit | 411f5c7a502769ccc0377c5ba36cb0b283847ba8 (patch) | |
tree | 2c3a29671e3f923de48c55f94194849264a7bf53 /arch/arm/mach-tcc8k | |
parent | 6d7ed21d17e640b120b902a314143e5ef4917a70 (diff) | |
parent | 9ced9f03d12d7539e86b0bff5bc750153c976c34 (diff) | |
download | kernel_samsung_smdk4412-411f5c7a502769ccc0377c5ba36cb0b283847ba8.zip kernel_samsung_smdk4412-411f5c7a502769ccc0377c5ba36cb0b283847ba8.tar.gz kernel_samsung_smdk4412-411f5c7a502769ccc0377c5ba36cb0b283847ba8.tar.bz2 |
Merge branch 'devel-stable' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel-stable' of master.kernel.org:/home/rmk/linux-2.6-arm: (289 commits)
davinci: DM644x EVM: register MUSB device earlier
davinci: add spi devices on tnetv107x evm
davinci: add ssp config for tnetv107x evm board
davinci: add tnetv107x ssp platform device
spi: add ti-ssp spi master driver
mfd: add driver for sequencer serial port
ARM: EXYNOS4: Implement Clock gating for System MMU
ARM: EXYNOS4: Enhancement of System MMU driver
ARM: EXYNOS4: Add support for gpio interrupts
ARM: S5P: Add function to register gpio interrupt bank data
ARM: S5P: Cleanup S5P gpio interrupt code
ARM: EXYNOS4: Add missing GPYx banks
ARM: S3C64XX: Fix section mismatch from cpufreq init
ARM: EXYNOS4: Add keypad device to the SMDKV310
ARM: EXYNOS4: Update clocks for keypad
ARM: EXYNOS4: Update keypad base address
ARM: EXYNOS4: Add keypad device helpers
ARM: EXYNOS4: Add support for SATA on ARMLEX4210
plat-nomadik: make GPIO interrupts work with cpuidle ApSleep
mach-u300: define a dummy filter function for coh901318
...
Fix up various conflicts in
- arch/arm/mach-exynos4/cpufreq.c
- arch/arm/mach-mxs/gpio.c
- drivers/net/Kconfig
- drivers/tty/serial/Kconfig
- drivers/tty/serial/Makefile
- drivers/usb/gadget/fsl_mxc_udc.c
- drivers/video/Kconfig
Diffstat (limited to 'arch/arm/mach-tcc8k')
-rw-r--r-- | arch/arm/mach-tcc8k/board-tcc8000-sdk.c | 19 | ||||
-rw-r--r-- | arch/arm/mach-tcc8k/clock.c | 38 |
2 files changed, 45 insertions, 12 deletions
diff --git a/arch/arm/mach-tcc8k/board-tcc8000-sdk.c b/arch/arm/mach-tcc8k/board-tcc8000-sdk.c index fb6426d..4cb3c2d 100644 --- a/arch/arm/mach-tcc8k/board-tcc8000-sdk.c +++ b/arch/arm/mach-tcc8k/board-tcc8000-sdk.c @@ -6,6 +6,7 @@ * published by the Free Software Foundation. */ +#include <linux/delay.h> #include <linux/init.h> #include <linux/kernel.h> #include <linux/platform_device.h> @@ -17,6 +18,8 @@ #include <asm/mach/time.h> #include <mach/clock.h> +#include <mach/tcc-nand.h> +#include <mach/tcc8k-regs.h> #include "common.h" @@ -51,6 +54,22 @@ static struct sys_timer tcc8k_timer = { static void __init tcc8k_map_io(void) { tcc8k_map_common_io(); + + /* set PLL0 clock to 96MHz, adapt UART0 divisor */ + __raw_writel(0x00026003, CKC_BASE + PLL0CFG_OFFS); + __raw_writel(0x10000001, CKC_BASE + ACLKUART0_OFFS); + + /* set PLL1 clock to 192MHz */ + __raw_writel(0x00016003, CKC_BASE + PLL1CFG_OFFS); + + /* set PLL2 clock to 48MHz */ + __raw_writel(0x00036003, CKC_BASE + PLL2CFG_OFFS); + + /* with CPU freq higher than 150 MHz, need extra DTCM wait */ + __raw_writel(0x00000001, SCFG_BASE + DTCMWAIT_OFFS); + + /* PLL locking time as specified */ + udelay(300); } MACHINE_START(TCC8000_SDK, "Telechips TCC8000-SDK Demo Board") diff --git a/arch/arm/mach-tcc8k/clock.c b/arch/arm/mach-tcc8k/clock.c index 3970a9c..e7cdae5 100644 --- a/arch/arm/mach-tcc8k/clock.c +++ b/arch/arm/mach-tcc8k/clock.c @@ -45,11 +45,12 @@ #define ACLKGSB1 (CKC_BASE + ACLKGSB1_OFFS) #define ACLKGSB2 (CKC_BASE + ACLKGSB2_OFFS) #define ACLKGSB3 (CKC_BASE + ACLKGSB3_OFFS) -#define ACLKUSBH (CKC_BASE + ACLKUSBH_OFFS) #define ACLKTCT (CKC_BASE + ACLKTCT_OFFS) #define ACLKTCX (CKC_BASE + ACLKTCX_OFFS) #define ACLKTCZ (CKC_BASE + ACLKTCZ_OFFS) +#define ACLK_MAX_DIV (0xfff + 1) + /* Crystal frequencies */ static unsigned long xi_rate, xti_rate; @@ -106,9 +107,9 @@ static int root_clk_enable(enum root_clks src) return 0; } -static int root_clk_disable(enum root_clks root_src) +static int root_clk_disable(enum root_clks src) { - switch (root_src) { + switch (src) { case CLK_SRC_PLL0: return pll_enable(0, 0); case CLK_SRC_PLL1: return pll_enable(1, 0); case CLK_SRC_PLL2: return pll_enable(2, 0); @@ -197,7 +198,7 @@ static unsigned long get_rate_pll_div(int pll) addr = CKC_BASE + CLKDIVC1_OFFS; reg = __raw_readl(addr); if (reg & CLKDIVC1_P2E) - div = __raw_readl(addr) & 0x3f; + div = reg & 0x3f; break; } return get_rate_pll(pll) / (div + 1); @@ -258,14 +259,19 @@ static unsigned long aclk_best_div(struct clk *clk, unsigned long rate) { unsigned long div, src, freq, r1, r2; + if (!rate) + return ACLK_MAX_DIV; + src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT; src &= CLK_SRC_MASK; freq = root_clk_get_rate(src); - div = freq / rate + 1; + div = freq / rate; + if (!div) + return 1; + if (div >= ACLK_MAX_DIV) + return ACLK_MAX_DIV; r1 = freq / div; r2 = freq / (div + 1); - if (r2 >= rate) - return div + 1; if ((rate - r2) < (r1 - rate)) return div + 1; @@ -287,7 +293,8 @@ static int aclk_set_rate(struct clk *clk, unsigned long rate) u32 reg; reg = __raw_readl(clk->aclkreg) & ~ACLK_DIV_MASK; - reg |= aclk_best_div(clk, rate); + reg |= aclk_best_div(clk, rate) - 1; + __raw_writel(reg, clk->aclkreg); return 0; } @@ -296,15 +303,22 @@ static unsigned long get_rate_sys(struct clk *clk) unsigned int src; src = __raw_readl(CKC_BASE + CLKCTRL_OFFS) & CLK_SRC_MASK; - return root_clk_get_rate(src); + return root_clk_get_rate(src); } static unsigned long get_rate_bus(struct clk *clk) { - unsigned int div; + unsigned int reg, sdiv, bdiv, rate; - div = (__raw_readl(CKC_BASE + CLKCTRL_OFFS) >> 4) & 0xff; - return get_rate_sys(clk) / (div + 1); + reg = __raw_readl(CKC_BASE + CLKCTRL_OFFS); + rate = get_rate_sys(clk); + sdiv = (reg >> 20) & 3; + if (sdiv) + rate /= sdiv + 1; + bdiv = (reg >> 4) & 0xff; + if (bdiv) + rate /= bdiv + 1; + return rate; } static unsigned long get_rate_cpu(struct clk *clk) |