aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-tegra/common.c
diff options
context:
space:
mode:
authorColin Cross <ccross@android.com>2010-01-28 16:40:29 -0800
committerErik Gilling <konkers@android.com>2010-08-05 14:51:42 -0700
commitd861196163e30c07add471562b45dce38517c9b2 (patch)
tree33c3577854f2e600e0f4dc25620f4932a31d3138 /arch/arm/mach-tegra/common.c
parent5ad36c5f0ece31552a195f2f9e29357a2747536e (diff)
downloadkernel_samsung_smdk4412-d861196163e30c07add471562b45dce38517c9b2.zip
kernel_samsung_smdk4412-d861196163e30c07add471562b45dce38517c9b2.tar.gz
kernel_samsung_smdk4412-d861196163e30c07add471562b45dce38517c9b2.tar.bz2
[ARM] tegra: Add clock support
v2: fixes from Russell King: - include linux/io.h instead of asm/io.h - fix whitespace in Kconfig - Use spin_lock_init to initialize lock - Return -ENOSYS instead of BUG for unimplemented clock ops - Use proper return values in tegra2 clock ops additional changes: - Rename some clocks to match dev_ids - add rate propagation - add debugfs entries - add support for clock listed in clk_lookup under multiple dev_ids v3: - Replace per-clock locking with global clock lock - Autodetect clock state on init - Let clock dividers pick next lower possible frequency - Add support for clock init tables - Minor bug fixes - Fix checkpatch issues Signed-off-by: Colin Cross <ccross@android.com>
Diffstat (limited to 'arch/arm/mach-tegra/common.c')
-rw-r--r--arch/arm/mach-tegra/common.c17
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 20875ee..039a514 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -25,6 +25,21 @@
#include <mach/iomap.h>
#include "board.h"
+#include "clock.h"
+
+static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
+ /* name parent rate enabled */
+ { "clk_m", NULL, 0, true },
+ { "pll_p", "clk_m", 216000000, true },
+ { "pll_p_out1", "pll_p", 28800000, true },
+ { "pll_p_out2", "pll_p", 48000000, true },
+ { "pll_p_out3", "pll_p", 72000000, true },
+ { "pll_p_out4", "pll_p", 108000000, true },
+ { "sys", "pll_p_out4", 108000000, true },
+ { "hclk", "sys", 108000000, true },
+ { "pclk", "hclk", 54000000, true },
+ { NULL, NULL, 0, 0},
+};
void __init tegra_init_cache(void)
{
@@ -40,5 +55,7 @@ void __init tegra_init_cache(void)
void __init tegra_common_init(void)
{
+ tegra_init_clock();
+ tegra_clk_init_from_table(common_clk_init_table);
tegra_init_cache();
}