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| author | Colin Cross <ccross@android.com> | 2010-09-08 19:41:58 -0700 |
|---|---|---|
| committer | Colin Cross <ccross@android.com> | 2011-02-20 23:36:50 -0800 |
| commit | 14133add42928d6759f35f5d94938adf2cda2bb6 (patch) | |
| tree | c582a98713a64f76de87106675aa6061be3b0e3c /arch/arm/mach-tegra/tegra2_clocks.c | |
| parent | 2b84cb4faab698b1708ce841c554546b1c9b2261 (diff) | |
| download | kernel_samsung_smdk4412-14133add42928d6759f35f5d94938adf2cda2bb6.zip kernel_samsung_smdk4412-14133add42928d6759f35f5d94938adf2cda2bb6.tar.gz kernel_samsung_smdk4412-14133add42928d6759f35f5d94938adf2cda2bb6.tar.bz2 | |
ARM: tegra: clock: Don't BUG on changing an enabled PLL
When updating the CPU PLL frequency, keeping the PLL enabled avoids
ramping the PLL all the way down and back up again. Remove the BUG_ON
in tegra2_pll_clk_set_rate to allow the rate to change while the PLL
is enabled.
Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Colin Cross <ccross@android.com>
Diffstat (limited to 'arch/arm/mach-tegra/tegra2_clocks.c')
| -rw-r--r-- | arch/arm/mach-tegra/tegra2_clocks.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c index 6442abe..600a5a4 100644 --- a/arch/arm/mach-tegra/tegra2_clocks.c +++ b/arch/arm/mach-tegra/tegra2_clocks.c @@ -620,7 +620,6 @@ static int tegra2_pll_clk_set_rate(struct clk *c, unsigned long rate) const struct clk_pll_table *sel; pr_debug("%s: %s %lu\n", __func__, c->name, rate); - BUG_ON(c->refcnt != 0); input_rate = c->parent->rate; for (sel = c->pll_table; sel->input_rate != 0; sel++) { |