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author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2006-12-19 14:17:46 +0000 |
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committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2007-02-06 16:46:45 +0000 |
commit | 10c03f69680e9e2acd8a9409a230aef37295ac49 (patch) | |
tree | 7ac927b0e93b20584f25de300ec2a4b2803c8529 /arch/arm/oprofile/op_model_mpcore.h | |
parent | 2d9e1ae06d8f0bb187ea083fabab2dfb6f589270 (diff) | |
download | kernel_samsung_smdk4412-10c03f69680e9e2acd8a9409a230aef37295ac49.zip kernel_samsung_smdk4412-10c03f69680e9e2acd8a9409a230aef37295ac49.tar.gz kernel_samsung_smdk4412-10c03f69680e9e2acd8a9409a230aef37295ac49.tar.bz2 |
[ARM] oprofile: add ARM11 SMP support
Add the glue for ARM11 SMP oprofile support, which also supports the
performance monitor in the coherency unit.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/oprofile/op_model_mpcore.h')
-rw-r--r-- | arch/arm/oprofile/op_model_mpcore.h | 61 |
1 files changed, 61 insertions, 0 deletions
diff --git a/arch/arm/oprofile/op_model_mpcore.h b/arch/arm/oprofile/op_model_mpcore.h new file mode 100644 index 0000000..73d8110 --- /dev/null +++ b/arch/arm/oprofile/op_model_mpcore.h @@ -0,0 +1,61 @@ +/** + * @file op_model_mpcore.c + * MPCORE Event Monitor Driver + * @remark Copyright 2004 ARM SMP Development Team + * @remark Copyright 2000-2004 Deepak Saxena <dsaxena@mvista.com> + * @remark Copyright 2000-2004 MontaVista Software Inc + * @remark Copyright 2004 Dave Jiang <dave.jiang@intel.com> + * @remark Copyright 2004 Intel Corporation + * @remark Copyright 2004 Zwane Mwaikambo <zwane@arm.linux.org.uk> + * @remark Copyright 2004 Oprofile Authors + * + * @remark Read the file COPYING + * + * @author Zwane Mwaikambo + */ +#ifndef OP_MODEL_MPCORE_H +#define OP_MODEL_MPCORE_H + +struct eventmonitor { + unsigned long PMCR; + unsigned char MCEB[8]; + unsigned long MC[8]; +}; + +/* + * List of userspace counter numbers: note that the structure is important. + * The code relies on CPUn's counters being CPU0's counters + 3n + * and on CPU0's counters starting at 0 + */ + +#define COUNTER_CPU0_PMN0 0 +#define COUNTER_CPU0_PMN1 1 +#define COUNTER_CPU0_CCNT 2 + +#define COUNTER_CPU1_PMN0 3 +#define COUNTER_CPU1_PMN1 4 +#define COUNTER_CPU1_CCNT 5 + +#define COUNTER_CPU2_PMN0 6 +#define COUNTER_CPU2_PMN1 7 +#define COUNTER_CPU2_CCNT 8 + +#define COUNTER_CPU3_PMN0 9 +#define COUNTER_CPU3_PMN1 10 +#define COUNTER_CPU3_CCNT 11 + +#define COUNTER_SCU_MN0 12 +#define COUNTER_SCU_MN1 13 +#define COUNTER_SCU_MN2 14 +#define COUNTER_SCU_MN3 15 +#define COUNTER_SCU_MN4 16 +#define COUNTER_SCU_MN5 17 +#define COUNTER_SCU_MN6 18 +#define COUNTER_SCU_MN7 19 +#define NUM_SCU_COUNTERS 8 + +#define SCU_COUNTER(number) ((number) + COUNTER_SCU_MN0) + +#define MPCORE_NUM_COUNTERS SCU_COUNTER(NUM_SCU_COUNTERS) + +#endif |