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author | David Vrabel <david.vrabel@csr.com> | 2009-01-22 19:12:32 +0000 |
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committer | David Vrabel <david.vrabel@csr.com> | 2009-01-22 19:12:32 +0000 |
commit | dff243f7cb3a2ebbb09093066c1bc4a90ff5b3a4 (patch) | |
tree | 1c63e7c2f879cd322ca785671b74b4ff796dd24c /arch/blackfin/mach-bf527/include/mach/anomaly.h | |
parent | a5e6ced58d423cb09c4fc0087dcfdb0b5deb5e1c (diff) | |
parent | f3b8436ad9a8ad36b3c9fa1fe030c7f38e5d3d0b (diff) | |
download | kernel_samsung_smdk4412-dff243f7cb3a2ebbb09093066c1bc4a90ff5b3a4.zip kernel_samsung_smdk4412-dff243f7cb3a2ebbb09093066c1bc4a90ff5b3a4.tar.gz kernel_samsung_smdk4412-dff243f7cb3a2ebbb09093066c1bc4a90ff5b3a4.tar.bz2 |
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6 into for-upstream
Diffstat (limited to 'arch/blackfin/mach-bf527/include/mach/anomaly.h')
-rw-r--r-- | arch/blackfin/mach-bf527/include/mach/anomaly.h | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/arch/blackfin/mach-bf527/include/mach/anomaly.h b/arch/blackfin/mach-bf527/include/mach/anomaly.h index 62373e6..035e8d8 100644 --- a/arch/blackfin/mach-bf527/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf527/include/mach/anomaly.h @@ -28,7 +28,7 @@ /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ #define ANOMALY_05000074 (1) /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ -#define ANOMALY_05000119 (1) +#define ANOMALY_05000119 (1) /* note: brokenness is noted in documentation, not anomaly sheet */ /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ #define ANOMALY_05000122 (1) /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ @@ -37,8 +37,6 @@ #define ANOMALY_05000265 (1) /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ #define ANOMALY_05000310 (1) -/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ -#define ANOMALY_05000312 (ANOMALY_BF527) /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ #define ANOMALY_05000313 (__SILICON_REVISION__ < 2) /* Incorrect Access of OTP_STATUS During otp_write() Function */ @@ -153,6 +151,10 @@ #define ANOMALY_05000430 (ANOMALY_BF527 && __SILICON_REVISION__ > 1) /* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */ #define ANOMALY_05000432 (ANOMALY_BF526) +/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */ +#define ANOMALY_05000435 ((ANOMALY_BF526 && __SILICON_REVISION__ < 1) || ANOMALY_BF527) +/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ +#define ANOMALY_05000443 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000125 (0) @@ -168,7 +170,9 @@ #define ANOMALY_05000285 (0) #define ANOMALY_05000307 (0) #define ANOMALY_05000311 (0) +#define ANOMALY_05000312 (0) #define ANOMALY_05000323 (0) #define ANOMALY_05000363 (0) +#define ANOMALY_05000412 (0) #endif |