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| author | Graf Yang <graf.yang@analog.com> | 2009-05-15 11:01:59 +0000 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2009-06-12 06:11:37 -0400 |
| commit | 1fa9be72b558c39459f98835eb86dbb4ef4da30b (patch) | |
| tree | f0b71c7b7a3639285c64e3f3cbc449c3ff9eee3b /arch/blackfin/mach-common/ints-priority.c | |
| parent | 555487bbb63f527e63fecbff48c86e2c07ce5024 (diff) | |
| download | kernel_samsung_smdk4412-1fa9be72b558c39459f98835eb86dbb4ef4da30b.zip kernel_samsung_smdk4412-1fa9be72b558c39459f98835eb86dbb4ef4da30b.tar.gz kernel_samsung_smdk4412-1fa9be72b558c39459f98835eb86dbb4ef4da30b.tar.bz2 | |
Blackfin: add support for gptimer0 as a tick source
For systems where the core cycles are not a usable tick source (like SMP
or cycles gets updated), enable gptimer0 as an alternative.
Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-common/ints-priority.c')
| -rw-r--r-- | arch/blackfin/mach-common/ints-priority.c | 23 |
1 files changed, 6 insertions, 17 deletions
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c index 389c5e8..6e80861 100644 --- a/arch/blackfin/mach-common/ints-priority.c +++ b/arch/blackfin/mach-common/ints-priority.c @@ -1052,7 +1052,7 @@ int __init init_arch_irq(void) set_irq_chained_handler(irq, bfin_demux_error_irq); break; #endif -#if defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE) +#if defined(CONFIG_TICKSOURCE_GPTMR0) case IRQ_TIMER0: set_irq_handler(irq, handle_percpu_irq); break; @@ -1232,13 +1232,9 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs) if (likely(vec == EVT_IVTMR_P)) { irq = IRQ_CORETMR; - goto core_tick; - } - - SSYNC(); + } else { #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) - { unsigned long sic_status[3]; sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0(); @@ -1254,9 +1250,7 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs) if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag) break; } - } #else - { unsigned long sic_status; sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR(); @@ -1268,15 +1262,13 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs) } else if (sic_status & ivg->isrflag) break; } - } #endif - irq = ivg->irqno; + irq = ivg->irqno; + } if (irq == IRQ_SYSTMR) { -#ifdef CONFIG_GENERIC_CLOCKEVENTS -core_tick: -#else +#ifndef CONFIG_GENERIC_CLOCKEVENTS bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */ #endif /* This is basically what we need from the register frame. */ @@ -1288,9 +1280,6 @@ core_tick: __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10; } -#ifndef CONFIG_GENERIC_CLOCKEVENTS -core_tick: -#endif if (this_domain == ipipe_root_domain) { s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status); barrier(); @@ -1308,7 +1297,7 @@ core_tick: } } - return 0; + return 0; } #endif /* CONFIG_IPIPE */ |