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| author | Fenghua Yu <fenghua.yu@intel.com> | 2008-04-04 11:05:59 -0700 |
|---|---|---|
| committer | Tony Luck <tony.luck@intel.com> | 2008-04-04 11:05:59 -0700 |
| commit | 2046b94e7c4fce92eb8165c2c36c6478f4927178 (patch) | |
| tree | 0dbbdf17d64b521f2debcc8677368ceec8805d8c /arch/ia64/kernel/setup.c | |
| parent | e315c121a858499d84dc88c499046b9f10bb61ec (diff) | |
| download | kernel_samsung_smdk4412-2046b94e7c4fce92eb8165c2c36c6478f4927178.zip kernel_samsung_smdk4412-2046b94e7c4fce92eb8165c2c36c6478f4927178.tar.gz kernel_samsung_smdk4412-2046b94e7c4fce92eb8165c2c36c6478f4927178.tar.bz2 | |
[IA64] Multiple outstanding ptc.g instruction support
According to SDM2.2, Itanium supports multiple outstanding ptc.g instructions.
But current kernel function ia64_global_tlb_purge() uses a spinlock to serialize
ptc.g instructions issued by multiple processors. This serialization might have
scalability issue on a big SMP machine where many processors could purge TLB
in parallel.
The patch fixes this problem by issuing multiple ptc.g instructions in
ia64_global_tlb_purge(). It also adds support for the "PALO" table to get
a platform view of the max number of outstanding ptc.g instructions (which
may be different from the processor view found from PAL_VM_SUMMARY).
PALO specification can be found at: http://www.dig64.org/home/DIG64_PALO_R1_0.pdf
spinaphore implementation by Matthew Wilcox.
Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'arch/ia64/kernel/setup.c')
| -rw-r--r-- | arch/ia64/kernel/setup.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/ia64/kernel/setup.c b/arch/ia64/kernel/setup.c index 4aa9eae..1cbd263 100644 --- a/arch/ia64/kernel/setup.c +++ b/arch/ia64/kernel/setup.c @@ -59,6 +59,7 @@ #include <asm/setup.h> #include <asm/smp.h> #include <asm/system.h> +#include <asm/tlbflush.h> #include <asm/unistd.h> #include <asm/hpsim.h> @@ -946,9 +947,10 @@ cpu_init (void) #endif /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */ - if (ia64_pal_vm_summary(NULL, &vmi) == 0) + if (ia64_pal_vm_summary(NULL, &vmi) == 0) { max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1; - else { + setup_ptcg_sem(vmi.pal_vm_info_2_s.max_purges, 0); + } else { printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n"); max_ctx = (1U << 15) - 1; /* use architected minimum */ } |