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| author | Greg Ungerer <gerg@uclinux.org> | 2011-03-05 22:17:17 +1000 |
|---|---|---|
| committer | Greg Ungerer <gerg@uclinux.org> | 2011-03-15 21:01:53 +1000 |
| commit | 254eef7464f0704290af4b91021f512eb4c98d59 (patch) | |
| tree | 4bc61d36dbb146eed72b166f7f75c06d7384adea /arch/m68k/include/asm/m528xsim.h | |
| parent | f2ba710d17ae221e21a7cccddbbf5257fd93e9fa (diff) | |
| download | kernel_samsung_smdk4412-254eef7464f0704290af4b91021f512eb4c98d59.zip kernel_samsung_smdk4412-254eef7464f0704290af4b91021f512eb4c98d59.tar.gz kernel_samsung_smdk4412-254eef7464f0704290af4b91021f512eb4c98d59.tar.bz2 | |
m68knommu: remove kludge seting of MCF_IPSBAR for ColdFire 54xx
The ColdFire 54xx family shares the same interrupt controller used
on the 523x, 527x and 528x ColdFire parts, but it isn't offset
relative to the IPSBAR register. The 54xx doesn't have an IPSBAR
register.
By including the base address of the peripheral registers in the register
definitions (MCFICM_INTC0 and MCFICM_INTC1 in this case) we can avoid
having to define a fake IPSBAR for the 54xx. And this makes the register
address definitions of these more consistent, the majority of the other
register address defines include the peripheral base address already.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k/include/asm/m528xsim.h')
| -rw-r--r-- | arch/m68k/include/asm/m528xsim.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h index a6d2f4d..a918545 100644 --- a/arch/m68k/include/asm/m528xsim.h +++ b/arch/m68k/include/asm/m528xsim.h @@ -19,8 +19,9 @@ /* * Define the 5280/5282 SIM register set addresses. */ -#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */ -#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 0 */ +#define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */ +#define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */ + #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ |