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author | Manuel Lauss <mano@roarinelk.homelinux.net> | 2008-12-21 09:26:17 +0100 |
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committer | Ralf Baechle <ralf@linux-mips.org> | 2009-01-11 09:57:26 +0000 |
commit | 785e3268e2951d4c0c21417c8e5d8004b2ab2480 (patch) | |
tree | 3e7e98dbaf2592f22f65090325a823d36caa13f7 /arch/mips/alchemy/common/Makefile | |
parent | 7179380ee9bdeb5fa2ff07581f512fe0f5382e5b (diff) | |
download | kernel_samsung_smdk4412-785e3268e2951d4c0c21417c8e5d8004b2ab2480.zip kernel_samsung_smdk4412-785e3268e2951d4c0c21417c8e5d8004b2ab2480.tar.gz kernel_samsung_smdk4412-785e3268e2951d4c0c21417c8e5d8004b2ab2480.tar.bz2 |
MIPS: Alchemy: update core interrupt code.
This patch attempts to modernize core Alchemy interrupt handling code.
- add irq_chips for irq controllers instead of irq type,
- add a set_type() hook to change irq trigger type during runtime,
- add a set_wake() hook to control GPIO0..7 based wakeup,
- use linux' IRQF_TRIGGER_ constants instead of homebrew ones,
- enable GENERIC_HARDIRQS_NO__DO_IRQ.
- simplify plat_irq_dispatch
- merge au1xxx_irqmap into irq.c file, the only place where its
contents are referenced.
- board_init_irq() is now mandatory for every board; use it to register
the remaining (gpio-based) interrupt sources; update all boards
accordingly.
Run-tested on Db1200 and other Au1200 based platforms.
Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
delete mode 100644 arch/mips/alchemy/common/au1xxx_irqmap.c
Diffstat (limited to 'arch/mips/alchemy/common/Makefile')
-rw-r--r-- | arch/mips/alchemy/common/Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile index df48fd6..28b8aeb 100644 --- a/arch/mips/alchemy/common/Makefile +++ b/arch/mips/alchemy/common/Makefile @@ -6,7 +6,7 @@ # obj-y += prom.o irq.o puts.o time.o reset.o \ - au1xxx_irqmap.o clocks.o platform.o power.o setup.o \ + clocks.o platform.o power.o setup.o \ sleeper.o cputable.o dma.o dbdma.o gpio.o obj-$(CONFIG_PCI) += pci.o |