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| author | Manuel Lauss <manuel.lauss@googlemail.com> | 2011-08-12 08:28:35 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2011-09-21 17:53:32 +0200 |
| commit | dd0a028183369cccc0826199a7ccdc850ece289b (patch) | |
| tree | 67c07381130b821bbbd9554cf761c738f4e4e954 /arch/mips/alchemy/devboards/bcsr.c | |
| parent | b7867f1bfcb76c75d98d35f576fcd9d7759a96fe (diff) | |
| download | kernel_samsung_smdk4412-dd0a028183369cccc0826199a7ccdc850ece289b.zip kernel_samsung_smdk4412-dd0a028183369cccc0826199a7ccdc850ece289b.tar.gz kernel_samsung_smdk4412-dd0a028183369cccc0826199a7ccdc850ece289b.tar.bz2 | |
MIPS: Alchemy: DB1200: Disable cascade IRQ in handler
Disable the cascade IRQ in the cascade handler. This is required to
get the DB1300 working, and also gets rid of all spurious interrupts
previously observed on the DB1200; so Config[OD] can be disabled
again for better performance.
Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com>
To: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/2708/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/alchemy/devboards/bcsr.c')
| -rw-r--r-- | arch/mips/alchemy/devboards/bcsr.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/mips/alchemy/devboards/bcsr.c b/arch/mips/alchemy/devboards/bcsr.c index 596ad00..463d2c4 100644 --- a/arch/mips/alchemy/devboards/bcsr.c +++ b/arch/mips/alchemy/devboards/bcsr.c @@ -89,8 +89,12 @@ static void bcsr_csc_handler(unsigned int irq, struct irq_desc *d) { unsigned short bisr = __raw_readw(bcsr_virt + BCSR_REG_INTSTAT); + disable_irq_nosync(irq); + for ( ; bisr; bisr &= bisr - 1) generic_handle_irq(bcsr_csc_base + __ffs(bisr)); + + enable_irq(irq); } /* NOTE: both the enable and mask bits must be cleared, otherwise the |