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author | Manuel Lauss <manuel.lauss@googlemail.com> | 2009-10-04 14:55:24 +0200 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2010-02-27 12:52:50 +0100 |
commit | 9bdcf336d0c061e77f4c45c7b2bc32e3ed6b57e3 (patch) | |
tree | 9cce0d50bb1709654fae719e7175da25279402bc /arch/mips/alchemy/devboards/bcsr.c | |
parent | ebc89718a4b3fa0e440151fb4484541700828a5d (diff) | |
download | kernel_samsung_smdk4412-9bdcf336d0c061e77f4c45c7b2bc32e3ed6b57e3.zip kernel_samsung_smdk4412-9bdcf336d0c061e77f4c45c7b2bc32e3ed6b57e3.tar.gz kernel_samsung_smdk4412-9bdcf336d0c061e77f4c45c7b2bc32e3ed6b57e3.tar.bz2 |
MIPS: Alchemy: devboard register abstraction
All Alchemy development boards have external CPLDs with a few registers
in them. They all share an identical register layout with only a few
minor differences (except the PB1000) in bit functions and base
addresses.
This patch
- adds a primitive facility to initialize and use these external
registers,
- replaces all occurrences of bcsr->xxx accesses with calls to the new
functions (the pb1200 cascade irq handling code is special).
- collects BCSR register information scattered throughout the board
headers in a central place.
Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/alchemy/devboards/bcsr.c')
-rw-r--r-- | arch/mips/alchemy/devboards/bcsr.c | 76 |
1 files changed, 76 insertions, 0 deletions
diff --git a/arch/mips/alchemy/devboards/bcsr.c b/arch/mips/alchemy/devboards/bcsr.c new file mode 100644 index 0000000..85b7715 --- /dev/null +++ b/arch/mips/alchemy/devboards/bcsr.c @@ -0,0 +1,76 @@ +/* + * bcsr.h -- Db1xxx/Pb1xxx Devboard CPLD registers ("BCSR") abstraction. + * + * All Alchemy development boards (except, of course, the weird PB1000) + * have a few registers in a CPLD with standardised layout; they mostly + * only differ in base address. + * All registers are 16bits wide with 32bit spacing. + */ + +#include <linux/module.h> +#include <linux/spinlock.h> +#include <asm/addrspace.h> +#include <asm/io.h> +#include <asm/mach-db1x00/bcsr.h> + +static struct bcsr_reg { + void __iomem *raddr; + spinlock_t lock; +} bcsr_regs[BCSR_CNT]; + +void __init bcsr_init(unsigned long bcsr1_phys, unsigned long bcsr2_phys) +{ + int i; + + bcsr1_phys = KSEG1ADDR(CPHYSADDR(bcsr1_phys)); + bcsr2_phys = KSEG1ADDR(CPHYSADDR(bcsr2_phys)); + + for (i = 0; i < BCSR_CNT; i++) { + if (i >= BCSR_HEXLEDS) + bcsr_regs[i].raddr = (void __iomem *)bcsr2_phys + + (0x04 * (i - BCSR_HEXLEDS)); + else + bcsr_regs[i].raddr = (void __iomem *)bcsr1_phys + + (0x04 * i); + + spin_lock_init(&bcsr_regs[i].lock); + } +} + +unsigned short bcsr_read(enum bcsr_id reg) +{ + unsigned short r; + unsigned long flags; + + spin_lock_irqsave(&bcsr_regs[reg].lock, flags); + r = __raw_readw(bcsr_regs[reg].raddr); + spin_unlock_irqrestore(&bcsr_regs[reg].lock, flags); + return r; +} +EXPORT_SYMBOL_GPL(bcsr_read); + +void bcsr_write(enum bcsr_id reg, unsigned short val) +{ + unsigned long flags; + + spin_lock_irqsave(&bcsr_regs[reg].lock, flags); + __raw_writew(val, bcsr_regs[reg].raddr); + wmb(); + spin_unlock_irqrestore(&bcsr_regs[reg].lock, flags); +} +EXPORT_SYMBOL_GPL(bcsr_write); + +void bcsr_mod(enum bcsr_id reg, unsigned short clr, unsigned short set) +{ + unsigned short r; + unsigned long flags; + + spin_lock_irqsave(&bcsr_regs[reg].lock, flags); + r = __raw_readw(bcsr_regs[reg].raddr); + r &= ~clr; + r |= set; + __raw_writew(r, bcsr_regs[reg].raddr); + wmb(); + spin_unlock_irqrestore(&bcsr_regs[reg].lock, flags); +} +EXPORT_SYMBOL_GPL(bcsr_mod); |